1 /*- 2 * Copyright (C) 2012-2016 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/buf.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/proc.h> 36 #include <sys/smp.h> 37 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include "nvme_private.h" 42 43 static int nvme_pci_probe(device_t); 44 static int nvme_pci_attach(device_t); 45 static int nvme_pci_detach(device_t); 46 static int nvme_pci_suspend(device_t); 47 static int nvme_pci_resume(device_t); 48 49 static void nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr); 50 51 static device_method_t nvme_pci_methods[] = { 52 /* Device interface */ 53 DEVMETHOD(device_probe, nvme_pci_probe), 54 DEVMETHOD(device_attach, nvme_pci_attach), 55 DEVMETHOD(device_detach, nvme_pci_detach), 56 DEVMETHOD(device_suspend, nvme_pci_suspend), 57 DEVMETHOD(device_resume, nvme_pci_resume), 58 DEVMETHOD(device_shutdown, nvme_shutdown), 59 { 0, 0 } 60 }; 61 62 static driver_t nvme_pci_driver = { 63 "nvme", 64 nvme_pci_methods, 65 sizeof(struct nvme_controller), 66 }; 67 68 DRIVER_MODULE(nvme, pci, nvme_pci_driver, nvme_devclass, NULL, 0); 69 70 static struct _pcsid 71 { 72 uint32_t devid; 73 int match_subdevice; 74 uint16_t subdevice; 75 const char *desc; 76 uint32_t quirks; 77 } pci_ids[] = { 78 { 0x01118086, 0, 0, "NVMe Controller" }, 79 { IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" }, 80 { IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" }, 81 { 0x09538086, 1, 0x3702, "DC P3700 SSD" }, 82 { 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" }, 83 { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" }, 84 { 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" }, 85 { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" }, 86 { 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" }, 87 { 0x00031c58, 0, 0, "HGST SN100", QUIRK_DELAY_B4_CHK_RDY }, 88 { 0x00231c58, 0, 0, "WDC SN200", QUIRK_DELAY_B4_CHK_RDY }, 89 { 0x05401c5f, 0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY }, 90 { 0xa821144d, 0, 0, "Samsung PM1725", QUIRK_DELAY_B4_CHK_RDY }, 91 { 0xa822144d, 0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY }, 92 { 0x00000000, 0, 0, NULL } 93 }; 94 95 96 static int 97 nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep) 98 { 99 if (devid != ep->devid) 100 return 0; 101 102 if (!ep->match_subdevice) 103 return 1; 104 105 if (subdevice == ep->subdevice) 106 return 1; 107 else 108 return 0; 109 } 110 111 static int 112 nvme_pci_probe (device_t device) 113 { 114 struct nvme_controller *ctrlr = DEVICE2SOFTC(device); 115 struct _pcsid *ep; 116 uint32_t devid; 117 uint16_t subdevice; 118 119 devid = pci_get_devid(device); 120 subdevice = pci_get_subdevice(device); 121 ep = pci_ids; 122 123 while (ep->devid) { 124 if (nvme_match(devid, subdevice, ep)) 125 break; 126 ++ep; 127 } 128 if (ep->devid) 129 ctrlr->quirks = ep->quirks; 130 131 if (ep->desc) { 132 device_set_desc(device, ep->desc); 133 return (BUS_PROBE_DEFAULT); 134 } 135 136 #if defined(PCIS_STORAGE_NVM) 137 if (pci_get_class(device) == PCIC_STORAGE && 138 pci_get_subclass(device) == PCIS_STORAGE_NVM && 139 pci_get_progif(device) == PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0) { 140 device_set_desc(device, "Generic NVMe Device"); 141 return (BUS_PROBE_GENERIC); 142 } 143 #endif 144 145 return (ENXIO); 146 } 147 148 static int 149 nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr) 150 { 151 152 ctrlr->resource_id = PCIR_BAR(0); 153 154 ctrlr->resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, 155 &ctrlr->resource_id, RF_ACTIVE); 156 157 if(ctrlr->resource == NULL) { 158 nvme_printf(ctrlr, "unable to allocate pci resource\n"); 159 return (ENOMEM); 160 } 161 162 ctrlr->bus_tag = rman_get_bustag(ctrlr->resource); 163 ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource); 164 ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle; 165 166 /* 167 * The NVMe spec allows for the MSI-X table to be placed behind 168 * BAR 4/5, separate from the control/doorbell registers. Always 169 * try to map this bar, because it must be mapped prior to calling 170 * pci_alloc_msix(). If the table isn't behind BAR 4/5, 171 * bus_alloc_resource() will just return NULL which is OK. 172 */ 173 ctrlr->bar4_resource_id = PCIR_BAR(4); 174 ctrlr->bar4_resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, 175 &ctrlr->bar4_resource_id, RF_ACTIVE); 176 177 return (0); 178 } 179 180 static int 181 nvme_pci_attach(device_t dev) 182 { 183 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev); 184 int status; 185 186 ctrlr->dev = dev; 187 status = nvme_ctrlr_allocate_bar(ctrlr); 188 if (status != 0) 189 goto bad; 190 pci_enable_busmaster(dev); 191 nvme_ctrlr_setup_interrupts(ctrlr); 192 return nvme_attach(dev); 193 bad: 194 if (ctrlr->resource != NULL) { 195 bus_release_resource(dev, SYS_RES_MEMORY, 196 ctrlr->resource_id, ctrlr->resource); 197 } 198 199 if (ctrlr->bar4_resource != NULL) { 200 bus_release_resource(dev, SYS_RES_MEMORY, 201 ctrlr->bar4_resource_id, ctrlr->bar4_resource); 202 } 203 204 if (ctrlr->tag) 205 bus_teardown_intr(dev, ctrlr->res, ctrlr->tag); 206 207 if (ctrlr->res) 208 bus_release_resource(dev, SYS_RES_IRQ, 209 rman_get_rid(ctrlr->res), ctrlr->res); 210 211 if (ctrlr->msix_enabled) 212 pci_release_msi(dev); 213 214 return status; 215 } 216 217 static int 218 nvme_pci_detach(device_t dev) 219 { 220 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev); 221 int rv; 222 223 rv = nvme_detach(dev); 224 if (ctrlr->msix_enabled) 225 pci_release_msi(dev); 226 pci_disable_busmaster(dev); 227 return (rv); 228 } 229 230 static int 231 nvme_ctrlr_configure_intx(struct nvme_controller *ctrlr) 232 { 233 234 ctrlr->msix_enabled = 0; 235 ctrlr->num_io_queues = 1; 236 ctrlr->num_cpus_per_ioq = mp_ncpus; 237 ctrlr->rid = 0; 238 ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 239 &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE); 240 241 if (ctrlr->res == NULL) { 242 nvme_printf(ctrlr, "unable to allocate shared IRQ\n"); 243 return (ENOMEM); 244 } 245 246 bus_setup_intr(ctrlr->dev, ctrlr->res, 247 INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_intx_handler, 248 ctrlr, &ctrlr->tag); 249 250 if (ctrlr->tag == NULL) { 251 nvme_printf(ctrlr, "unable to setup intx handler\n"); 252 return (ENOMEM); 253 } 254 255 return (0); 256 } 257 258 static void 259 nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr) 260 { 261 device_t dev; 262 int per_cpu_io_queues; 263 int min_cpus_per_ioq; 264 int num_vectors_requested, num_vectors_allocated; 265 int num_vectors_available; 266 267 dev = ctrlr->dev; 268 min_cpus_per_ioq = 1; 269 TUNABLE_INT_FETCH("hw.nvme.min_cpus_per_ioq", &min_cpus_per_ioq); 270 271 if (min_cpus_per_ioq < 1) { 272 min_cpus_per_ioq = 1; 273 } else if (min_cpus_per_ioq > mp_ncpus) { 274 min_cpus_per_ioq = mp_ncpus; 275 } 276 277 per_cpu_io_queues = 1; 278 TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues); 279 280 if (per_cpu_io_queues == 0) { 281 min_cpus_per_ioq = mp_ncpus; 282 } 283 284 ctrlr->force_intx = 0; 285 TUNABLE_INT_FETCH("hw.nvme.force_intx", &ctrlr->force_intx); 286 287 /* 288 * FreeBSD currently cannot allocate more than about 190 vectors at 289 * boot, meaning that systems with high core count and many devices 290 * requesting per-CPU interrupt vectors will not get their full 291 * allotment. So first, try to allocate as many as we may need to 292 * understand what is available, then immediately release them. 293 * Then figure out how many of those we will actually use, based on 294 * assigning an equal number of cores to each I/O queue. 295 */ 296 297 /* One vector for per core I/O queue, plus one vector for admin queue. */ 298 num_vectors_available = min(pci_msix_count(dev), mp_ncpus + 1); 299 if (pci_alloc_msix(dev, &num_vectors_available) != 0) { 300 num_vectors_available = 0; 301 } 302 pci_release_msi(dev); 303 304 if (ctrlr->force_intx || num_vectors_available < 2) { 305 nvme_ctrlr_configure_intx(ctrlr); 306 return; 307 } 308 309 /* 310 * Do not use all vectors for I/O queues - one must be saved for the 311 * admin queue. 312 */ 313 ctrlr->num_cpus_per_ioq = max(min_cpus_per_ioq, 314 howmany(mp_ncpus, num_vectors_available - 1)); 315 316 ctrlr->num_io_queues = howmany(mp_ncpus, ctrlr->num_cpus_per_ioq); 317 num_vectors_requested = ctrlr->num_io_queues + 1; 318 num_vectors_allocated = num_vectors_requested; 319 320 /* 321 * Now just allocate the number of vectors we need. This should 322 * succeed, since we previously called pci_alloc_msix() 323 * successfully returning at least this many vectors, but just to 324 * be safe, if something goes wrong just revert to INTx. 325 */ 326 if (pci_alloc_msix(dev, &num_vectors_allocated) != 0) { 327 nvme_ctrlr_configure_intx(ctrlr); 328 return; 329 } 330 331 if (num_vectors_allocated < num_vectors_requested) { 332 pci_release_msi(dev); 333 nvme_ctrlr_configure_intx(ctrlr); 334 return; 335 } 336 337 ctrlr->msix_enabled = 1; 338 } 339 340 static int 341 nvme_pci_suspend(device_t dev) 342 { 343 struct nvme_controller *ctrlr; 344 345 ctrlr = DEVICE2SOFTC(dev); 346 return (nvme_ctrlr_suspend(ctrlr)); 347 } 348 349 static int 350 nvme_pci_resume(device_t dev) 351 { 352 struct nvme_controller *ctrlr; 353 354 ctrlr = DEVICE2SOFTC(dev); 355 return (nvme_ctrlr_resume(ctrlr)); 356 } 357