1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/module.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/bus.h> 34 #include <sys/endian.h> 35 #include <sys/malloc.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/stdarg.h> 39 #include <vm/uma.h> 40 #include <machine/resource.h> 41 #include <machine/bus.h> 42 #include <sys/rman.h> 43 #include <sys/sbuf.h> 44 #include <arm/mv/mvreg.h> 45 #include <arm/mv/mvvar.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 #include "mvs.h" 49 50 /* local prototypes */ 51 static int mvs_setup_interrupt(device_t dev); 52 static void mvs_intr(void *data); 53 static int mvs_suspend(device_t dev); 54 static int mvs_resume(device_t dev); 55 static int mvs_ctlr_setup(device_t dev); 56 57 static struct { 58 uint32_t id; 59 uint8_t rev; 60 const char *name; 61 int ports; 62 int quirks; 63 } mvs_ids[] = { 64 {MV_DEV_MV78260, 0x00, "Marvell MV78260", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 65 {MV_DEV_MV78460, 0x00, "Marvell MV78460", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 66 {0, 0x00, NULL, 0, 0} 67 }; 68 69 static int 70 mvs_probe(device_t dev) 71 { 72 int i; 73 uint32_t devid, revid; 74 75 if (!ofw_bus_status_okay(dev)) 76 return (ENXIO); 77 78 if (!ofw_bus_is_compatible(dev, "mrvl,sata")) 79 return (ENXIO); 80 81 soc_id(&devid, &revid); 82 for (i = 0; mvs_ids[i].id != 0; i++) { 83 if (mvs_ids[i].id == devid && 84 mvs_ids[i].rev <= revid) { 85 device_set_descf(dev, "%s SATA controller", 86 mvs_ids[i].name); 87 return (BUS_PROBE_DEFAULT); 88 } 89 } 90 return (ENXIO); 91 } 92 93 static int 94 mvs_attach(device_t dev) 95 { 96 struct mvs_controller *ctlr = device_get_softc(dev); 97 device_t child; 98 int error, unit, i; 99 uint32_t devid, revid; 100 101 soc_id(&devid, &revid); 102 ctlr->dev = dev; 103 i = 0; 104 while (mvs_ids[i].id != 0 && 105 (mvs_ids[i].id != devid || 106 mvs_ids[i].rev > revid)) 107 i++; 108 ctlr->channels = mvs_ids[i].ports; 109 ctlr->quirks = mvs_ids[i].quirks; 110 ctlr->ccc = 0; 111 resource_int_value(device_get_name(dev), 112 device_get_unit(dev), "ccc", &ctlr->ccc); 113 ctlr->cccc = 8; 114 resource_int_value(device_get_name(dev), 115 device_get_unit(dev), "cccc", &ctlr->cccc); 116 if (ctlr->ccc == 0 || ctlr->cccc == 0) { 117 ctlr->ccc = 0; 118 ctlr->cccc = 0; 119 } 120 if (ctlr->ccc > 100000) 121 ctlr->ccc = 100000; 122 device_printf(dev, 123 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n", 124 ((ctlr->quirks & MVS_Q_GENI) ? "I" : 125 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")), 126 ctlr->channels, 127 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"), 128 ((ctlr->quirks & MVS_Q_GENI) ? 129 "not supported" : "supported"), 130 ((ctlr->quirks & MVS_Q_GENIIE) ? 131 " with FBS" : "")); 132 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF); 133 /* We should have a memory BAR(0). */ 134 ctlr->r_rid = 0; 135 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 136 &ctlr->r_rid, RF_ACTIVE))) 137 return ENXIO; 138 if (ATA_INL(ctlr->r_mem, PORT_BASE(0) + SATA_PHYCFG_OFS) != 0) 139 ctlr->quirks |= MVS_Q_SOC65; 140 /* Setup our own memory management for channels. */ 141 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 142 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 143 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 144 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 145 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 146 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 147 return (error); 148 } 149 if ((error = rman_manage_region(&ctlr->sc_iomem, 150 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 151 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 152 rman_fini(&ctlr->sc_iomem); 153 return (error); 154 } 155 mvs_ctlr_setup(dev); 156 /* Setup interrupts. */ 157 if (mvs_setup_interrupt(dev)) { 158 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 159 rman_fini(&ctlr->sc_iomem); 160 return ENXIO; 161 } 162 /* Attach all channels on this controller */ 163 for (unit = 0; unit < ctlr->channels; unit++) { 164 child = device_add_child(dev, "mvsch", DEVICE_UNIT_ANY); 165 if (child == NULL) 166 device_printf(dev, "failed to add channel device\n"); 167 else 168 device_set_ivars(child, (void *)(intptr_t)unit); 169 } 170 bus_attach_children(dev); 171 return 0; 172 } 173 174 static int 175 mvs_detach(device_t dev) 176 { 177 struct mvs_controller *ctlr = device_get_softc(dev); 178 int error; 179 180 /* Detach & delete all children */ 181 error = bus_generic_detach(dev); 182 if (error != 0) 183 return (error); 184 185 /* Free interrupt. */ 186 if (ctlr->irq.r_irq) { 187 bus_teardown_intr(dev, ctlr->irq.r_irq, 188 ctlr->irq.handle); 189 bus_release_resource(dev, SYS_RES_IRQ, 190 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 191 } 192 /* Free memory. */ 193 rman_fini(&ctlr->sc_iomem); 194 if (ctlr->r_mem) 195 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 196 mtx_destroy(&ctlr->mtx); 197 return (0); 198 } 199 200 static int 201 mvs_ctlr_setup(device_t dev) 202 { 203 struct mvs_controller *ctlr = device_get_softc(dev); 204 int ccc = ctlr->ccc, cccc = ctlr->cccc; 205 206 /* Mask chip interrupts */ 207 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 208 /* Clear HC interrupts */ 209 ATA_OUTL(ctlr->r_mem, HC_IC, 0x00000000); 210 /* Clear chip interrupts */ 211 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIC, 0); 212 /* Configure per-HC CCC */ 213 if (ccc && bootverbose) { 214 device_printf(dev, 215 "CCC with %dus/%dcmd enabled\n", 216 ctlr->ccc, ctlr->cccc); 217 } 218 ccc *= 150; 219 ATA_OUTL(ctlr->r_mem, HC_ICT, cccc); 220 ATA_OUTL(ctlr->r_mem, HC_ITT, ccc); 221 /* Enable chip interrupts */ 222 ctlr->gmim = ((ccc ? IC_HC0_COAL_DONE : 223 (IC_DONE_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))) | 224 (IC_ERR_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))); 225 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 226 return (0); 227 } 228 229 static void 230 mvs_edma(device_t dev, device_t child, int mode) 231 { 232 struct mvs_controller *ctlr = device_get_softc(dev); 233 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 234 int bit = IC_DONE_IRQ << (unit * 2); 235 236 if (ctlr->ccc == 0) 237 return; 238 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ 239 mtx_lock(&ctlr->mtx); 240 if (mode == MVS_EDMA_OFF) 241 ctlr->pmim |= bit; 242 else 243 ctlr->pmim &= ~bit; 244 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 245 mtx_unlock(&ctlr->mtx); 246 } 247 248 static int 249 mvs_suspend(device_t dev) 250 { 251 struct mvs_controller *ctlr = device_get_softc(dev); 252 253 bus_generic_suspend(dev); 254 /* Mask chip interrupts */ 255 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 256 return 0; 257 } 258 259 static int 260 mvs_resume(device_t dev) 261 { 262 263 mvs_ctlr_setup(dev); 264 return (bus_generic_resume(dev)); 265 } 266 267 static int 268 mvs_setup_interrupt(device_t dev) 269 { 270 struct mvs_controller *ctlr = device_get_softc(dev); 271 272 /* Allocate all IRQs. */ 273 ctlr->irq.r_irq_rid = 0; 274 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 275 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 276 device_printf(dev, "unable to map interrupt\n"); 277 return (ENXIO); 278 } 279 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL, 280 mvs_intr, ctlr, &ctlr->irq.handle))) { 281 device_printf(dev, "unable to setup interrupt\n"); 282 bus_release_resource(dev, SYS_RES_IRQ, 283 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 284 ctlr->irq.r_irq = NULL; 285 return (ENXIO); 286 } 287 return (0); 288 } 289 290 /* 291 * Common case interrupt handler. 292 */ 293 static void 294 mvs_intr(void *data) 295 { 296 struct mvs_controller *ctlr = data; 297 struct mvs_intr_arg arg; 298 void (*function)(void *); 299 int p, chan_num; 300 u_int32_t ic, aic; 301 302 ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC); 303 if ((ic & IC_HC0) == 0) 304 return; 305 306 /* Acknowledge interrupts of this HC. */ 307 aic = 0; 308 309 /* Processing interrupts from each initialized channel */ 310 for (chan_num = 0; chan_num < ctlr->channels; chan_num++) { 311 if (ic & (IC_DONE_IRQ << (chan_num * 2))) 312 aic |= HC_IC_DONE(chan_num) | HC_IC_DEV(chan_num); 313 } 314 315 if (ic & IC_HC0_COAL_DONE) 316 aic |= HC_IC_COAL; 317 ATA_OUTL(ctlr->r_mem, HC_IC, ~aic); 318 319 /* Call per-port interrupt handler. */ 320 for (p = 0; p < ctlr->channels; p++) { 321 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); 322 if ((arg.cause != 0) && 323 (function = ctlr->interrupt[p].function)) { 324 arg.arg = ctlr->interrupt[p].argument; 325 function(&arg); 326 } 327 ic >>= 2; 328 } 329 } 330 331 static struct resource * 332 mvs_alloc_resource(device_t dev, device_t child, int type, int *rid, 333 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 334 { 335 struct mvs_controller *ctlr = device_get_softc(dev); 336 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 337 struct resource *res = NULL; 338 int offset = PORT_BASE(unit & 0x03); 339 rman_res_t st; 340 341 switch (type) { 342 case SYS_RES_MEMORY: 343 st = rman_get_start(ctlr->r_mem); 344 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 345 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child); 346 if (res) { 347 bus_space_handle_t bsh; 348 bus_space_tag_t bst; 349 bsh = rman_get_bushandle(ctlr->r_mem); 350 bst = rman_get_bustag(ctlr->r_mem); 351 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh); 352 rman_set_bushandle(res, bsh); 353 rman_set_bustag(res, bst); 354 } 355 break; 356 case SYS_RES_IRQ: 357 if (*rid == ATA_IRQ_RID) 358 res = ctlr->irq.r_irq; 359 break; 360 } 361 return (res); 362 } 363 364 static int 365 mvs_release_resource(device_t dev, device_t child, struct resource *r) 366 { 367 368 switch (rman_get_type(r)) { 369 case SYS_RES_MEMORY: 370 rman_release_resource(r); 371 return (0); 372 case SYS_RES_IRQ: 373 if (rman_get_rid(r) != ATA_IRQ_RID) 374 return ENOENT; 375 return (0); 376 } 377 return (EINVAL); 378 } 379 380 static int 381 mvs_setup_intr(device_t dev, device_t child, struct resource *irq, 382 int flags, driver_filter_t *filter, driver_intr_t *function, 383 void *argument, void **cookiep) 384 { 385 struct mvs_controller *ctlr = device_get_softc(dev); 386 int unit = (intptr_t)device_get_ivars(child); 387 388 if (filter != NULL) { 389 printf("mvs.c: we cannot use a filter here\n"); 390 return (EINVAL); 391 } 392 ctlr->interrupt[unit].function = function; 393 ctlr->interrupt[unit].argument = argument; 394 return (0); 395 } 396 397 static int 398 mvs_teardown_intr(device_t dev, device_t child, struct resource *irq, 399 void *cookie) 400 { 401 struct mvs_controller *ctlr = device_get_softc(dev); 402 int unit = (intptr_t)device_get_ivars(child); 403 404 ctlr->interrupt[unit].function = NULL; 405 ctlr->interrupt[unit].argument = NULL; 406 return (0); 407 } 408 409 static int 410 mvs_print_child(device_t dev, device_t child) 411 { 412 int retval; 413 414 retval = bus_print_child_header(dev, child); 415 retval += printf(" at channel %d", 416 (int)(intptr_t)device_get_ivars(child)); 417 retval += bus_print_child_footer(dev, child); 418 419 return (retval); 420 } 421 422 static int 423 mvs_child_location(device_t dev, device_t child, struct sbuf *sb) 424 { 425 426 sbuf_printf(sb, "channel=%d", (int)(intptr_t)device_get_ivars(child)); 427 return (0); 428 } 429 430 static bus_dma_tag_t 431 mvs_get_dma_tag(device_t bus, device_t child) 432 { 433 434 return (bus_get_dma_tag(bus)); 435 } 436 437 static device_method_t mvs_methods[] = { 438 DEVMETHOD(device_probe, mvs_probe), 439 DEVMETHOD(device_attach, mvs_attach), 440 DEVMETHOD(device_detach, mvs_detach), 441 DEVMETHOD(device_suspend, mvs_suspend), 442 DEVMETHOD(device_resume, mvs_resume), 443 DEVMETHOD(bus_print_child, mvs_print_child), 444 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource), 445 DEVMETHOD(bus_release_resource, mvs_release_resource), 446 DEVMETHOD(bus_setup_intr, mvs_setup_intr), 447 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr), 448 DEVMETHOD(bus_child_location, mvs_child_location), 449 DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag), 450 DEVMETHOD(mvs_edma, mvs_edma), 451 { 0, 0 } 452 }; 453 static driver_t mvs_driver = { 454 "mvs", 455 mvs_methods, 456 sizeof(struct mvs_controller) 457 }; 458 DRIVER_MODULE(mvs, simplebus, mvs_driver, 0, 0); 459 MODULE_VERSION(mvs, 1); 460 MODULE_DEPEND(mvs, cam, 1, 1, 1); 461