1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/module.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <vm/uma.h> 42 #include <machine/stdarg.h> 43 #include <machine/resource.h> 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <arm/mv/mvreg.h> 48 #include <arm/mv/mvvar.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 #include "mvs.h" 52 53 /* local prototypes */ 54 static int mvs_setup_interrupt(device_t dev); 55 static void mvs_intr(void *data); 56 static int mvs_suspend(device_t dev); 57 static int mvs_resume(device_t dev); 58 static int mvs_ctlr_setup(device_t dev); 59 60 static struct { 61 uint32_t id; 62 uint8_t rev; 63 const char *name; 64 int ports; 65 int quirks; 66 } mvs_ids[] = { 67 {MV_DEV_88F5182, 0x00, "Marvell 88F5182", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 68 {MV_DEV_88F6281, 0x00, "Marvell 88F6281", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 69 {MV_DEV_88F6282, 0x00, "Marvell 88F6282", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 70 {MV_DEV_MV78100, 0x00, "Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 71 {MV_DEV_MV78100_Z0, 0x00,"Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 72 {MV_DEV_MV78260, 0x00, "Marvell MV78260", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 73 {MV_DEV_MV78460, 0x00, "Marvell MV78460", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 74 {0, 0x00, NULL, 0, 0} 75 }; 76 77 static int 78 mvs_probe(device_t dev) 79 { 80 char buf[64]; 81 int i; 82 uint32_t devid, revid; 83 84 if (!ofw_bus_status_okay(dev)) 85 return (ENXIO); 86 87 if (!ofw_bus_is_compatible(dev, "mrvl,sata")) 88 return (ENXIO); 89 90 soc_id(&devid, &revid); 91 for (i = 0; mvs_ids[i].id != 0; i++) { 92 if (mvs_ids[i].id == devid && 93 mvs_ids[i].rev <= revid) { 94 snprintf(buf, sizeof(buf), "%s SATA controller", 95 mvs_ids[i].name); 96 device_set_desc_copy(dev, buf); 97 return (BUS_PROBE_DEFAULT); 98 } 99 } 100 return (ENXIO); 101 } 102 103 static int 104 mvs_attach(device_t dev) 105 { 106 struct mvs_controller *ctlr = device_get_softc(dev); 107 device_t child; 108 int error, unit, i; 109 uint32_t devid, revid; 110 111 soc_id(&devid, &revid); 112 ctlr->dev = dev; 113 i = 0; 114 while (mvs_ids[i].id != 0 && 115 (mvs_ids[i].id != devid || 116 mvs_ids[i].rev > revid)) 117 i++; 118 ctlr->channels = mvs_ids[i].ports; 119 ctlr->quirks = mvs_ids[i].quirks; 120 ctlr->ccc = 0; 121 resource_int_value(device_get_name(dev), 122 device_get_unit(dev), "ccc", &ctlr->ccc); 123 ctlr->cccc = 8; 124 resource_int_value(device_get_name(dev), 125 device_get_unit(dev), "cccc", &ctlr->cccc); 126 if (ctlr->ccc == 0 || ctlr->cccc == 0) { 127 ctlr->ccc = 0; 128 ctlr->cccc = 0; 129 } 130 if (ctlr->ccc > 100000) 131 ctlr->ccc = 100000; 132 device_printf(dev, 133 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n", 134 ((ctlr->quirks & MVS_Q_GENI) ? "I" : 135 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")), 136 ctlr->channels, 137 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"), 138 ((ctlr->quirks & MVS_Q_GENI) ? 139 "not supported" : "supported"), 140 ((ctlr->quirks & MVS_Q_GENIIE) ? 141 " with FBS" : "")); 142 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF); 143 /* We should have a memory BAR(0). */ 144 ctlr->r_rid = 0; 145 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 146 &ctlr->r_rid, RF_ACTIVE))) 147 return ENXIO; 148 if (ATA_INL(ctlr->r_mem, PORT_BASE(0) + SATA_PHYCFG_OFS) != 0) 149 ctlr->quirks |= MVS_Q_SOC65; 150 /* Setup our own memory management for channels. */ 151 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 152 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 153 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 154 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 155 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 156 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 157 return (error); 158 } 159 if ((error = rman_manage_region(&ctlr->sc_iomem, 160 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 161 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 162 rman_fini(&ctlr->sc_iomem); 163 return (error); 164 } 165 mvs_ctlr_setup(dev); 166 /* Setup interrupts. */ 167 if (mvs_setup_interrupt(dev)) { 168 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 169 rman_fini(&ctlr->sc_iomem); 170 return ENXIO; 171 } 172 /* Attach all channels on this controller */ 173 for (unit = 0; unit < ctlr->channels; unit++) { 174 child = device_add_child(dev, "mvsch", -1); 175 if (child == NULL) 176 device_printf(dev, "failed to add channel device\n"); 177 else 178 device_set_ivars(child, (void *)(intptr_t)unit); 179 } 180 bus_generic_attach(dev); 181 return 0; 182 } 183 184 static int 185 mvs_detach(device_t dev) 186 { 187 struct mvs_controller *ctlr = device_get_softc(dev); 188 189 /* Detach & delete all children */ 190 device_delete_children(dev); 191 192 /* Free interrupt. */ 193 if (ctlr->irq.r_irq) { 194 bus_teardown_intr(dev, ctlr->irq.r_irq, 195 ctlr->irq.handle); 196 bus_release_resource(dev, SYS_RES_IRQ, 197 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 198 } 199 /* Free memory. */ 200 rman_fini(&ctlr->sc_iomem); 201 if (ctlr->r_mem) 202 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 203 mtx_destroy(&ctlr->mtx); 204 return (0); 205 } 206 207 static int 208 mvs_ctlr_setup(device_t dev) 209 { 210 struct mvs_controller *ctlr = device_get_softc(dev); 211 int ccc = ctlr->ccc, cccc = ctlr->cccc; 212 213 /* Mask chip interrupts */ 214 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 215 /* Clear HC interrupts */ 216 ATA_OUTL(ctlr->r_mem, HC_IC, 0x00000000); 217 /* Clear chip interrupts */ 218 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIC, 0); 219 /* Configure per-HC CCC */ 220 if (ccc && bootverbose) { 221 device_printf(dev, 222 "CCC with %dus/%dcmd enabled\n", 223 ctlr->ccc, ctlr->cccc); 224 } 225 ccc *= 150; 226 ATA_OUTL(ctlr->r_mem, HC_ICT, cccc); 227 ATA_OUTL(ctlr->r_mem, HC_ITT, ccc); 228 /* Enable chip interrupts */ 229 ctlr->gmim = ((ccc ? IC_HC0_COAL_DONE : 230 (IC_DONE_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))) | 231 (IC_ERR_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))); 232 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 233 return (0); 234 } 235 236 static void 237 mvs_edma(device_t dev, device_t child, int mode) 238 { 239 struct mvs_controller *ctlr = device_get_softc(dev); 240 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 241 int bit = IC_DONE_IRQ << (unit * 2); 242 243 if (ctlr->ccc == 0) 244 return; 245 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ 246 mtx_lock(&ctlr->mtx); 247 if (mode == MVS_EDMA_OFF) 248 ctlr->pmim |= bit; 249 else 250 ctlr->pmim &= ~bit; 251 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 252 mtx_unlock(&ctlr->mtx); 253 } 254 255 static int 256 mvs_suspend(device_t dev) 257 { 258 struct mvs_controller *ctlr = device_get_softc(dev); 259 260 bus_generic_suspend(dev); 261 /* Mask chip interrupts */ 262 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 263 return 0; 264 } 265 266 static int 267 mvs_resume(device_t dev) 268 { 269 270 mvs_ctlr_setup(dev); 271 return (bus_generic_resume(dev)); 272 } 273 274 static int 275 mvs_setup_interrupt(device_t dev) 276 { 277 struct mvs_controller *ctlr = device_get_softc(dev); 278 279 /* Allocate all IRQs. */ 280 ctlr->irq.r_irq_rid = 0; 281 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 282 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 283 device_printf(dev, "unable to map interrupt\n"); 284 return (ENXIO); 285 } 286 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL, 287 mvs_intr, ctlr, &ctlr->irq.handle))) { 288 device_printf(dev, "unable to setup interrupt\n"); 289 bus_release_resource(dev, SYS_RES_IRQ, 290 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 291 ctlr->irq.r_irq = NULL; 292 return (ENXIO); 293 } 294 return (0); 295 } 296 297 /* 298 * Common case interrupt handler. 299 */ 300 static void 301 mvs_intr(void *data) 302 { 303 struct mvs_controller *ctlr = data; 304 struct mvs_intr_arg arg; 305 void (*function)(void *); 306 int p, chan_num; 307 u_int32_t ic, aic; 308 309 ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC); 310 if ((ic & IC_HC0) == 0) 311 return; 312 313 /* Acknowledge interrupts of this HC. */ 314 aic = 0; 315 316 /* Processing interrupts from each initialized channel */ 317 for (chan_num = 0; chan_num < ctlr->channels; chan_num++) { 318 if (ic & (IC_DONE_IRQ << (chan_num * 2))) 319 aic |= HC_IC_DONE(chan_num) | HC_IC_DEV(chan_num); 320 } 321 322 if (ic & IC_HC0_COAL_DONE) 323 aic |= HC_IC_COAL; 324 ATA_OUTL(ctlr->r_mem, HC_IC, ~aic); 325 326 /* Call per-port interrupt handler. */ 327 for (p = 0; p < ctlr->channels; p++) { 328 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); 329 if ((arg.cause != 0) && 330 (function = ctlr->interrupt[p].function)) { 331 arg.arg = ctlr->interrupt[p].argument; 332 function(&arg); 333 } 334 ic >>= 2; 335 } 336 } 337 338 static struct resource * 339 mvs_alloc_resource(device_t dev, device_t child, int type, int *rid, 340 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 341 { 342 struct mvs_controller *ctlr = device_get_softc(dev); 343 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 344 struct resource *res = NULL; 345 int offset = PORT_BASE(unit & 0x03); 346 rman_res_t st; 347 348 switch (type) { 349 case SYS_RES_MEMORY: 350 st = rman_get_start(ctlr->r_mem); 351 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 352 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child); 353 if (res) { 354 bus_space_handle_t bsh; 355 bus_space_tag_t bst; 356 bsh = rman_get_bushandle(ctlr->r_mem); 357 bst = rman_get_bustag(ctlr->r_mem); 358 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh); 359 rman_set_bushandle(res, bsh); 360 rman_set_bustag(res, bst); 361 } 362 break; 363 case SYS_RES_IRQ: 364 if (*rid == ATA_IRQ_RID) 365 res = ctlr->irq.r_irq; 366 break; 367 } 368 return (res); 369 } 370 371 static int 372 mvs_release_resource(device_t dev, device_t child, int type, int rid, 373 struct resource *r) 374 { 375 376 switch (type) { 377 case SYS_RES_MEMORY: 378 rman_release_resource(r); 379 return (0); 380 case SYS_RES_IRQ: 381 if (rid != ATA_IRQ_RID) 382 return ENOENT; 383 return (0); 384 } 385 return (EINVAL); 386 } 387 388 static int 389 mvs_setup_intr(device_t dev, device_t child, struct resource *irq, 390 int flags, driver_filter_t *filter, driver_intr_t *function, 391 void *argument, void **cookiep) 392 { 393 struct mvs_controller *ctlr = device_get_softc(dev); 394 int unit = (intptr_t)device_get_ivars(child); 395 396 if (filter != NULL) { 397 printf("mvs.c: we cannot use a filter here\n"); 398 return (EINVAL); 399 } 400 ctlr->interrupt[unit].function = function; 401 ctlr->interrupt[unit].argument = argument; 402 return (0); 403 } 404 405 static int 406 mvs_teardown_intr(device_t dev, device_t child, struct resource *irq, 407 void *cookie) 408 { 409 struct mvs_controller *ctlr = device_get_softc(dev); 410 int unit = (intptr_t)device_get_ivars(child); 411 412 ctlr->interrupt[unit].function = NULL; 413 ctlr->interrupt[unit].argument = NULL; 414 return (0); 415 } 416 417 static int 418 mvs_print_child(device_t dev, device_t child) 419 { 420 int retval; 421 422 retval = bus_print_child_header(dev, child); 423 retval += printf(" at channel %d", 424 (int)(intptr_t)device_get_ivars(child)); 425 retval += bus_print_child_footer(dev, child); 426 427 return (retval); 428 } 429 430 static int 431 mvs_child_location(device_t dev, device_t child, struct sbuf *sb) 432 { 433 434 sbuf_printf(sb, "channel=%d", (int)(intptr_t)device_get_ivars(child)); 435 return (0); 436 } 437 438 static bus_dma_tag_t 439 mvs_get_dma_tag(device_t bus, device_t child) 440 { 441 442 return (bus_get_dma_tag(bus)); 443 } 444 445 static device_method_t mvs_methods[] = { 446 DEVMETHOD(device_probe, mvs_probe), 447 DEVMETHOD(device_attach, mvs_attach), 448 DEVMETHOD(device_detach, mvs_detach), 449 DEVMETHOD(device_suspend, mvs_suspend), 450 DEVMETHOD(device_resume, mvs_resume), 451 DEVMETHOD(bus_print_child, mvs_print_child), 452 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource), 453 DEVMETHOD(bus_release_resource, mvs_release_resource), 454 DEVMETHOD(bus_setup_intr, mvs_setup_intr), 455 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr), 456 DEVMETHOD(bus_child_location, mvs_child_location), 457 DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag), 458 DEVMETHOD(mvs_edma, mvs_edma), 459 { 0, 0 } 460 }; 461 static driver_t mvs_driver = { 462 "mvs", 463 mvs_methods, 464 sizeof(struct mvs_controller) 465 }; 466 DRIVER_MODULE(mvs, simplebus, mvs_driver, 0, 0); 467 MODULE_VERSION(mvs, 1); 468 MODULE_DEPEND(mvs, cam, 1, 1, 1); 469