1 /*- 2 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/malloc.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <vm/uma.h> 40 #include <machine/stdarg.h> 41 #include <machine/resource.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <arm/mv/mvreg.h> 45 #include <arm/mv/mvvar.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 #include "mvs.h" 49 50 /* local prototypes */ 51 static int mvs_setup_interrupt(device_t dev); 52 static void mvs_intr(void *data); 53 static int mvs_suspend(device_t dev); 54 static int mvs_resume(device_t dev); 55 static int mvs_ctlr_setup(device_t dev); 56 57 static struct { 58 uint32_t id; 59 uint8_t rev; 60 const char *name; 61 int ports; 62 int quirks; 63 } mvs_ids[] = { 64 {MV_DEV_88F5182, 0x00, "Marvell 88F5182", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 65 {MV_DEV_88F6281, 0x00, "Marvell 88F6281", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 66 {MV_DEV_88F6282, 0x00, "Marvell 88F6282", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 67 {MV_DEV_MV78100, 0x00, "Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 68 {MV_DEV_MV78100_Z0, 0x00,"Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 69 {MV_DEV_MV78260, 0x00, "Marvell MV78260", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 70 {MV_DEV_MV78460, 0x00, "Marvell MV78460", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 71 {0, 0x00, NULL, 0, 0} 72 }; 73 74 static int 75 mvs_probe(device_t dev) 76 { 77 char buf[64]; 78 int i; 79 uint32_t devid, revid; 80 81 if (!ofw_bus_status_okay(dev)) 82 return (ENXIO); 83 84 if (!ofw_bus_is_compatible(dev, "mrvl,sata")) 85 return (ENXIO); 86 87 soc_id(&devid, &revid); 88 for (i = 0; mvs_ids[i].id != 0; i++) { 89 if (mvs_ids[i].id == devid && 90 mvs_ids[i].rev <= revid) { 91 snprintf(buf, sizeof(buf), "%s SATA controller", 92 mvs_ids[i].name); 93 device_set_desc_copy(dev, buf); 94 return (BUS_PROBE_VENDOR); 95 } 96 } 97 return (ENXIO); 98 } 99 100 static int 101 mvs_attach(device_t dev) 102 { 103 struct mvs_controller *ctlr = device_get_softc(dev); 104 device_t child; 105 int error, unit, i; 106 uint32_t devid, revid; 107 108 soc_id(&devid, &revid); 109 ctlr->dev = dev; 110 i = 0; 111 while (mvs_ids[i].id != 0 && 112 (mvs_ids[i].id != devid || 113 mvs_ids[i].rev > revid)) 114 i++; 115 ctlr->channels = mvs_ids[i].ports; 116 ctlr->quirks = mvs_ids[i].quirks; 117 resource_int_value(device_get_name(dev), 118 device_get_unit(dev), "ccc", &ctlr->ccc); 119 ctlr->cccc = 8; 120 resource_int_value(device_get_name(dev), 121 device_get_unit(dev), "cccc", &ctlr->cccc); 122 if (ctlr->ccc == 0 || ctlr->cccc == 0) { 123 ctlr->ccc = 0; 124 ctlr->cccc = 0; 125 } 126 if (ctlr->ccc > 100000) 127 ctlr->ccc = 100000; 128 device_printf(dev, 129 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n", 130 ((ctlr->quirks & MVS_Q_GENI) ? "I" : 131 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")), 132 ctlr->channels, 133 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"), 134 ((ctlr->quirks & MVS_Q_GENI) ? 135 "not supported" : "supported"), 136 ((ctlr->quirks & MVS_Q_GENIIE) ? 137 " with FBS" : "")); 138 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF); 139 /* We should have a memory BAR(0). */ 140 ctlr->r_rid = 0; 141 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 142 &ctlr->r_rid, RF_ACTIVE))) 143 return ENXIO; 144 if (ATA_INL(ctlr->r_mem, PORT_BASE(0) + SATA_PHYCFG_OFS) != 0) 145 ctlr->quirks |= MVS_Q_SOC65; 146 /* Setup our own memory management for channels. */ 147 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 148 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 149 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 150 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 151 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 152 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 153 return (error); 154 } 155 if ((error = rman_manage_region(&ctlr->sc_iomem, 156 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 157 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 158 rman_fini(&ctlr->sc_iomem); 159 return (error); 160 } 161 mvs_ctlr_setup(dev); 162 /* Setup interrupts. */ 163 if (mvs_setup_interrupt(dev)) { 164 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 165 rman_fini(&ctlr->sc_iomem); 166 return ENXIO; 167 } 168 /* Attach all channels on this controller */ 169 for (unit = 0; unit < ctlr->channels; unit++) { 170 child = device_add_child(dev, "mvsch", -1); 171 if (child == NULL) 172 device_printf(dev, "failed to add channel device\n"); 173 else 174 device_set_ivars(child, (void *)(intptr_t)unit); 175 } 176 bus_generic_attach(dev); 177 return 0; 178 } 179 180 static int 181 mvs_detach(device_t dev) 182 { 183 struct mvs_controller *ctlr = device_get_softc(dev); 184 185 /* Detach & delete all children */ 186 device_delete_children(dev); 187 188 /* Free interrupt. */ 189 if (ctlr->irq.r_irq) { 190 bus_teardown_intr(dev, ctlr->irq.r_irq, 191 ctlr->irq.handle); 192 bus_release_resource(dev, SYS_RES_IRQ, 193 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 194 } 195 /* Free memory. */ 196 rman_fini(&ctlr->sc_iomem); 197 if (ctlr->r_mem) 198 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 199 mtx_destroy(&ctlr->mtx); 200 return (0); 201 } 202 203 static int 204 mvs_ctlr_setup(device_t dev) 205 { 206 struct mvs_controller *ctlr = device_get_softc(dev); 207 int ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0; 208 209 /* Mask chip interrupts */ 210 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 211 /* Clear HC interrupts */ 212 ATA_OUTL(ctlr->r_mem, HC_IC, 0x00000000); 213 /* Clear chip interrupts */ 214 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIC, 0); 215 /* Configure per-HC CCC */ 216 if (ccc && bootverbose) { 217 device_printf(dev, 218 "CCC with %dus/%dcmd enabled\n", 219 ctlr->ccc, ctlr->cccc); 220 } 221 ccc *= 150; 222 ATA_OUTL(ctlr->r_mem, HC_ICT, cccc); 223 ATA_OUTL(ctlr->r_mem, HC_ITT, ccc); 224 if (ccc) 225 ccim |= IC_HC0_COAL_DONE; 226 /* Enable chip interrupts */ 227 ctlr->gmim = ((ccc ? IC_HC0_COAL_DONE : 228 (IC_DONE_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))) | 229 (IC_ERR_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))); 230 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 231 return (0); 232 } 233 234 static void 235 mvs_edma(device_t dev, device_t child, int mode) 236 { 237 struct mvs_controller *ctlr = device_get_softc(dev); 238 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 239 int bit = IC_DONE_IRQ << (unit * 2); 240 241 if (ctlr->ccc == 0) 242 return; 243 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ 244 mtx_lock(&ctlr->mtx); 245 if (mode == MVS_EDMA_OFF) 246 ctlr->pmim |= bit; 247 else 248 ctlr->pmim &= ~bit; 249 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 250 mtx_unlock(&ctlr->mtx); 251 } 252 253 static int 254 mvs_suspend(device_t dev) 255 { 256 struct mvs_controller *ctlr = device_get_softc(dev); 257 258 bus_generic_suspend(dev); 259 /* Mask chip interrupts */ 260 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 261 return 0; 262 } 263 264 static int 265 mvs_resume(device_t dev) 266 { 267 268 mvs_ctlr_setup(dev); 269 return (bus_generic_resume(dev)); 270 } 271 272 static int 273 mvs_setup_interrupt(device_t dev) 274 { 275 struct mvs_controller *ctlr = device_get_softc(dev); 276 277 /* Allocate all IRQs. */ 278 ctlr->irq.r_irq_rid = 0; 279 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 280 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 281 device_printf(dev, "unable to map interrupt\n"); 282 return (ENXIO); 283 } 284 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL, 285 mvs_intr, ctlr, &ctlr->irq.handle))) { 286 device_printf(dev, "unable to setup interrupt\n"); 287 bus_release_resource(dev, SYS_RES_IRQ, 288 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 289 ctlr->irq.r_irq = 0; 290 return (ENXIO); 291 } 292 return (0); 293 } 294 295 /* 296 * Common case interrupt handler. 297 */ 298 static void 299 mvs_intr(void *data) 300 { 301 struct mvs_controller *ctlr = data; 302 struct mvs_intr_arg arg; 303 void (*function)(void *); 304 int p, chan_num; 305 u_int32_t ic, aic; 306 307 ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC); 308 if ((ic & IC_HC0) == 0) 309 return; 310 311 /* Acknowledge interrupts of this HC. */ 312 aic = 0; 313 314 /* Processing interrupts from each initialized channel */ 315 for (chan_num = 0; chan_num < ctlr->channels; chan_num++) { 316 if (ic & (IC_DONE_IRQ << (chan_num * 2))) 317 aic |= HC_IC_DONE(chan_num) | HC_IC_DEV(chan_num); 318 } 319 320 if (ic & IC_HC0_COAL_DONE) 321 aic |= HC_IC_COAL; 322 ATA_OUTL(ctlr->r_mem, HC_IC, ~aic); 323 324 /* Call per-port interrupt handler. */ 325 for (p = 0; p < ctlr->channels; p++) { 326 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); 327 if ((arg.cause != 0) && 328 (function = ctlr->interrupt[p].function)) { 329 arg.arg = ctlr->interrupt[p].argument; 330 function(&arg); 331 } 332 ic >>= 2; 333 } 334 } 335 336 static struct resource * 337 mvs_alloc_resource(device_t dev, device_t child, int type, int *rid, 338 u_long start, u_long end, u_long count, u_int flags) 339 { 340 struct mvs_controller *ctlr = device_get_softc(dev); 341 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 342 struct resource *res = NULL; 343 int offset = PORT_BASE(unit & 0x03); 344 long st; 345 346 switch (type) { 347 case SYS_RES_MEMORY: 348 st = rman_get_start(ctlr->r_mem); 349 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 350 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child); 351 if (res) { 352 bus_space_handle_t bsh; 353 bus_space_tag_t bst; 354 bsh = rman_get_bushandle(ctlr->r_mem); 355 bst = rman_get_bustag(ctlr->r_mem); 356 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh); 357 rman_set_bushandle(res, bsh); 358 rman_set_bustag(res, bst); 359 } 360 break; 361 case SYS_RES_IRQ: 362 if (*rid == ATA_IRQ_RID) 363 res = ctlr->irq.r_irq; 364 break; 365 } 366 return (res); 367 } 368 369 static int 370 mvs_release_resource(device_t dev, device_t child, int type, int rid, 371 struct resource *r) 372 { 373 374 switch (type) { 375 case SYS_RES_MEMORY: 376 rman_release_resource(r); 377 return (0); 378 case SYS_RES_IRQ: 379 if (rid != ATA_IRQ_RID) 380 return ENOENT; 381 return (0); 382 } 383 return (EINVAL); 384 } 385 386 static int 387 mvs_setup_intr(device_t dev, device_t child, struct resource *irq, 388 int flags, driver_filter_t *filter, driver_intr_t *function, 389 void *argument, void **cookiep) 390 { 391 struct mvs_controller *ctlr = device_get_softc(dev); 392 int unit = (intptr_t)device_get_ivars(child); 393 394 if (filter != NULL) { 395 printf("mvs.c: we cannot use a filter here\n"); 396 return (EINVAL); 397 } 398 ctlr->interrupt[unit].function = function; 399 ctlr->interrupt[unit].argument = argument; 400 return (0); 401 } 402 403 static int 404 mvs_teardown_intr(device_t dev, device_t child, struct resource *irq, 405 void *cookie) 406 { 407 struct mvs_controller *ctlr = device_get_softc(dev); 408 int unit = (intptr_t)device_get_ivars(child); 409 410 ctlr->interrupt[unit].function = NULL; 411 ctlr->interrupt[unit].argument = NULL; 412 return (0); 413 } 414 415 static int 416 mvs_print_child(device_t dev, device_t child) 417 { 418 int retval; 419 420 retval = bus_print_child_header(dev, child); 421 retval += printf(" at channel %d", 422 (int)(intptr_t)device_get_ivars(child)); 423 retval += bus_print_child_footer(dev, child); 424 425 return (retval); 426 } 427 428 static int 429 mvs_child_location_str(device_t dev, device_t child, char *buf, 430 size_t buflen) 431 { 432 433 snprintf(buf, buflen, "channel=%d", 434 (int)(intptr_t)device_get_ivars(child)); 435 return (0); 436 } 437 438 static bus_dma_tag_t 439 mvs_get_dma_tag(device_t bus, device_t child) 440 { 441 442 return (bus_get_dma_tag(bus)); 443 } 444 445 static device_method_t mvs_methods[] = { 446 DEVMETHOD(device_probe, mvs_probe), 447 DEVMETHOD(device_attach, mvs_attach), 448 DEVMETHOD(device_detach, mvs_detach), 449 DEVMETHOD(device_suspend, mvs_suspend), 450 DEVMETHOD(device_resume, mvs_resume), 451 DEVMETHOD(bus_print_child, mvs_print_child), 452 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource), 453 DEVMETHOD(bus_release_resource, mvs_release_resource), 454 DEVMETHOD(bus_setup_intr, mvs_setup_intr), 455 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr), 456 DEVMETHOD(bus_child_location_str, mvs_child_location_str), 457 DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag), 458 DEVMETHOD(mvs_edma, mvs_edma), 459 { 0, 0 } 460 }; 461 static driver_t mvs_driver = { 462 "mvs", 463 mvs_methods, 464 sizeof(struct mvs_controller) 465 }; 466 DRIVER_MODULE(mvs, simplebus, mvs_driver, mvs_devclass, 0, 0); 467 MODULE_VERSION(mvs, 1); 468 MODULE_DEPEND(mvs, cam, 1, 1, 1); 469