1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/module.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/bus.h> 34 #include <sys/endian.h> 35 #include <sys/malloc.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <vm/uma.h> 39 #include <machine/stdarg.h> 40 #include <machine/resource.h> 41 #include <machine/bus.h> 42 #include <sys/rman.h> 43 #include <sys/sbuf.h> 44 #include <arm/mv/mvreg.h> 45 #include <arm/mv/mvvar.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 #include "mvs.h" 49 50 /* local prototypes */ 51 static int mvs_setup_interrupt(device_t dev); 52 static void mvs_intr(void *data); 53 static int mvs_suspend(device_t dev); 54 static int mvs_resume(device_t dev); 55 static int mvs_ctlr_setup(device_t dev); 56 57 static struct { 58 uint32_t id; 59 uint8_t rev; 60 const char *name; 61 int ports; 62 int quirks; 63 } mvs_ids[] = { 64 {MV_DEV_88F5182, 0x00, "Marvell 88F5182", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 65 {MV_DEV_88F6281, 0x00, "Marvell 88F6281", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 66 {MV_DEV_88F6282, 0x00, "Marvell 88F6282", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 67 {MV_DEV_MV78100, 0x00, "Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 68 {MV_DEV_MV78100_Z0, 0x00,"Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 69 {MV_DEV_MV78260, 0x00, "Marvell MV78260", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 70 {MV_DEV_MV78460, 0x00, "Marvell MV78460", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 71 {0, 0x00, NULL, 0, 0} 72 }; 73 74 static int 75 mvs_probe(device_t dev) 76 { 77 int i; 78 uint32_t devid, revid; 79 80 if (!ofw_bus_status_okay(dev)) 81 return (ENXIO); 82 83 if (!ofw_bus_is_compatible(dev, "mrvl,sata")) 84 return (ENXIO); 85 86 soc_id(&devid, &revid); 87 for (i = 0; mvs_ids[i].id != 0; i++) { 88 if (mvs_ids[i].id == devid && 89 mvs_ids[i].rev <= revid) { 90 device_set_descf(dev, "%s SATA controller", 91 mvs_ids[i].name); 92 return (BUS_PROBE_DEFAULT); 93 } 94 } 95 return (ENXIO); 96 } 97 98 static int 99 mvs_attach(device_t dev) 100 { 101 struct mvs_controller *ctlr = device_get_softc(dev); 102 device_t child; 103 int error, unit, i; 104 uint32_t devid, revid; 105 106 soc_id(&devid, &revid); 107 ctlr->dev = dev; 108 i = 0; 109 while (mvs_ids[i].id != 0 && 110 (mvs_ids[i].id != devid || 111 mvs_ids[i].rev > revid)) 112 i++; 113 ctlr->channels = mvs_ids[i].ports; 114 ctlr->quirks = mvs_ids[i].quirks; 115 ctlr->ccc = 0; 116 resource_int_value(device_get_name(dev), 117 device_get_unit(dev), "ccc", &ctlr->ccc); 118 ctlr->cccc = 8; 119 resource_int_value(device_get_name(dev), 120 device_get_unit(dev), "cccc", &ctlr->cccc); 121 if (ctlr->ccc == 0 || ctlr->cccc == 0) { 122 ctlr->ccc = 0; 123 ctlr->cccc = 0; 124 } 125 if (ctlr->ccc > 100000) 126 ctlr->ccc = 100000; 127 device_printf(dev, 128 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n", 129 ((ctlr->quirks & MVS_Q_GENI) ? "I" : 130 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")), 131 ctlr->channels, 132 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"), 133 ((ctlr->quirks & MVS_Q_GENI) ? 134 "not supported" : "supported"), 135 ((ctlr->quirks & MVS_Q_GENIIE) ? 136 " with FBS" : "")); 137 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF); 138 /* We should have a memory BAR(0). */ 139 ctlr->r_rid = 0; 140 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 141 &ctlr->r_rid, RF_ACTIVE))) 142 return ENXIO; 143 if (ATA_INL(ctlr->r_mem, PORT_BASE(0) + SATA_PHYCFG_OFS) != 0) 144 ctlr->quirks |= MVS_Q_SOC65; 145 /* Setup our own memory management for channels. */ 146 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 147 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 148 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 149 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 150 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 151 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 152 return (error); 153 } 154 if ((error = rman_manage_region(&ctlr->sc_iomem, 155 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 156 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 157 rman_fini(&ctlr->sc_iomem); 158 return (error); 159 } 160 mvs_ctlr_setup(dev); 161 /* Setup interrupts. */ 162 if (mvs_setup_interrupt(dev)) { 163 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 164 rman_fini(&ctlr->sc_iomem); 165 return ENXIO; 166 } 167 /* Attach all channels on this controller */ 168 for (unit = 0; unit < ctlr->channels; unit++) { 169 child = device_add_child(dev, "mvsch", -1); 170 if (child == NULL) 171 device_printf(dev, "failed to add channel device\n"); 172 else 173 device_set_ivars(child, (void *)(intptr_t)unit); 174 } 175 bus_generic_attach(dev); 176 return 0; 177 } 178 179 static int 180 mvs_detach(device_t dev) 181 { 182 struct mvs_controller *ctlr = device_get_softc(dev); 183 184 /* Detach & delete all children */ 185 device_delete_children(dev); 186 187 /* Free interrupt. */ 188 if (ctlr->irq.r_irq) { 189 bus_teardown_intr(dev, ctlr->irq.r_irq, 190 ctlr->irq.handle); 191 bus_release_resource(dev, SYS_RES_IRQ, 192 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 193 } 194 /* Free memory. */ 195 rman_fini(&ctlr->sc_iomem); 196 if (ctlr->r_mem) 197 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 198 mtx_destroy(&ctlr->mtx); 199 return (0); 200 } 201 202 static int 203 mvs_ctlr_setup(device_t dev) 204 { 205 struct mvs_controller *ctlr = device_get_softc(dev); 206 int ccc = ctlr->ccc, cccc = ctlr->cccc; 207 208 /* Mask chip interrupts */ 209 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 210 /* Clear HC interrupts */ 211 ATA_OUTL(ctlr->r_mem, HC_IC, 0x00000000); 212 /* Clear chip interrupts */ 213 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIC, 0); 214 /* Configure per-HC CCC */ 215 if (ccc && bootverbose) { 216 device_printf(dev, 217 "CCC with %dus/%dcmd enabled\n", 218 ctlr->ccc, ctlr->cccc); 219 } 220 ccc *= 150; 221 ATA_OUTL(ctlr->r_mem, HC_ICT, cccc); 222 ATA_OUTL(ctlr->r_mem, HC_ITT, ccc); 223 /* Enable chip interrupts */ 224 ctlr->gmim = ((ccc ? IC_HC0_COAL_DONE : 225 (IC_DONE_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))) | 226 (IC_ERR_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))); 227 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 228 return (0); 229 } 230 231 static void 232 mvs_edma(device_t dev, device_t child, int mode) 233 { 234 struct mvs_controller *ctlr = device_get_softc(dev); 235 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 236 int bit = IC_DONE_IRQ << (unit * 2); 237 238 if (ctlr->ccc == 0) 239 return; 240 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ 241 mtx_lock(&ctlr->mtx); 242 if (mode == MVS_EDMA_OFF) 243 ctlr->pmim |= bit; 244 else 245 ctlr->pmim &= ~bit; 246 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 247 mtx_unlock(&ctlr->mtx); 248 } 249 250 static int 251 mvs_suspend(device_t dev) 252 { 253 struct mvs_controller *ctlr = device_get_softc(dev); 254 255 bus_generic_suspend(dev); 256 /* Mask chip interrupts */ 257 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 258 return 0; 259 } 260 261 static int 262 mvs_resume(device_t dev) 263 { 264 265 mvs_ctlr_setup(dev); 266 return (bus_generic_resume(dev)); 267 } 268 269 static int 270 mvs_setup_interrupt(device_t dev) 271 { 272 struct mvs_controller *ctlr = device_get_softc(dev); 273 274 /* Allocate all IRQs. */ 275 ctlr->irq.r_irq_rid = 0; 276 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 277 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 278 device_printf(dev, "unable to map interrupt\n"); 279 return (ENXIO); 280 } 281 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL, 282 mvs_intr, ctlr, &ctlr->irq.handle))) { 283 device_printf(dev, "unable to setup interrupt\n"); 284 bus_release_resource(dev, SYS_RES_IRQ, 285 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 286 ctlr->irq.r_irq = NULL; 287 return (ENXIO); 288 } 289 return (0); 290 } 291 292 /* 293 * Common case interrupt handler. 294 */ 295 static void 296 mvs_intr(void *data) 297 { 298 struct mvs_controller *ctlr = data; 299 struct mvs_intr_arg arg; 300 void (*function)(void *); 301 int p, chan_num; 302 u_int32_t ic, aic; 303 304 ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC); 305 if ((ic & IC_HC0) == 0) 306 return; 307 308 /* Acknowledge interrupts of this HC. */ 309 aic = 0; 310 311 /* Processing interrupts from each initialized channel */ 312 for (chan_num = 0; chan_num < ctlr->channels; chan_num++) { 313 if (ic & (IC_DONE_IRQ << (chan_num * 2))) 314 aic |= HC_IC_DONE(chan_num) | HC_IC_DEV(chan_num); 315 } 316 317 if (ic & IC_HC0_COAL_DONE) 318 aic |= HC_IC_COAL; 319 ATA_OUTL(ctlr->r_mem, HC_IC, ~aic); 320 321 /* Call per-port interrupt handler. */ 322 for (p = 0; p < ctlr->channels; p++) { 323 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); 324 if ((arg.cause != 0) && 325 (function = ctlr->interrupt[p].function)) { 326 arg.arg = ctlr->interrupt[p].argument; 327 function(&arg); 328 } 329 ic >>= 2; 330 } 331 } 332 333 static struct resource * 334 mvs_alloc_resource(device_t dev, device_t child, int type, int *rid, 335 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 336 { 337 struct mvs_controller *ctlr = device_get_softc(dev); 338 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 339 struct resource *res = NULL; 340 int offset = PORT_BASE(unit & 0x03); 341 rman_res_t st; 342 343 switch (type) { 344 case SYS_RES_MEMORY: 345 st = rman_get_start(ctlr->r_mem); 346 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 347 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child); 348 if (res) { 349 bus_space_handle_t bsh; 350 bus_space_tag_t bst; 351 bsh = rman_get_bushandle(ctlr->r_mem); 352 bst = rman_get_bustag(ctlr->r_mem); 353 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh); 354 rman_set_bushandle(res, bsh); 355 rman_set_bustag(res, bst); 356 } 357 break; 358 case SYS_RES_IRQ: 359 if (*rid == ATA_IRQ_RID) 360 res = ctlr->irq.r_irq; 361 break; 362 } 363 return (res); 364 } 365 366 static int 367 mvs_release_resource(device_t dev, device_t child, struct resource *r) 368 { 369 370 switch (rman_get_type(r)) { 371 case SYS_RES_MEMORY: 372 rman_release_resource(r); 373 return (0); 374 case SYS_RES_IRQ: 375 if (rid != ATA_IRQ_RID) 376 return ENOENT; 377 return (0); 378 } 379 return (EINVAL); 380 } 381 382 static int 383 mvs_setup_intr(device_t dev, device_t child, struct resource *irq, 384 int flags, driver_filter_t *filter, driver_intr_t *function, 385 void *argument, void **cookiep) 386 { 387 struct mvs_controller *ctlr = device_get_softc(dev); 388 int unit = (intptr_t)device_get_ivars(child); 389 390 if (filter != NULL) { 391 printf("mvs.c: we cannot use a filter here\n"); 392 return (EINVAL); 393 } 394 ctlr->interrupt[unit].function = function; 395 ctlr->interrupt[unit].argument = argument; 396 return (0); 397 } 398 399 static int 400 mvs_teardown_intr(device_t dev, device_t child, struct resource *irq, 401 void *cookie) 402 { 403 struct mvs_controller *ctlr = device_get_softc(dev); 404 int unit = (intptr_t)device_get_ivars(child); 405 406 ctlr->interrupt[unit].function = NULL; 407 ctlr->interrupt[unit].argument = NULL; 408 return (0); 409 } 410 411 static int 412 mvs_print_child(device_t dev, device_t child) 413 { 414 int retval; 415 416 retval = bus_print_child_header(dev, child); 417 retval += printf(" at channel %d", 418 (int)(intptr_t)device_get_ivars(child)); 419 retval += bus_print_child_footer(dev, child); 420 421 return (retval); 422 } 423 424 static int 425 mvs_child_location(device_t dev, device_t child, struct sbuf *sb) 426 { 427 428 sbuf_printf(sb, "channel=%d", (int)(intptr_t)device_get_ivars(child)); 429 return (0); 430 } 431 432 static bus_dma_tag_t 433 mvs_get_dma_tag(device_t bus, device_t child) 434 { 435 436 return (bus_get_dma_tag(bus)); 437 } 438 439 static device_method_t mvs_methods[] = { 440 DEVMETHOD(device_probe, mvs_probe), 441 DEVMETHOD(device_attach, mvs_attach), 442 DEVMETHOD(device_detach, mvs_detach), 443 DEVMETHOD(device_suspend, mvs_suspend), 444 DEVMETHOD(device_resume, mvs_resume), 445 DEVMETHOD(bus_print_child, mvs_print_child), 446 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource), 447 DEVMETHOD(bus_release_resource, mvs_release_resource), 448 DEVMETHOD(bus_setup_intr, mvs_setup_intr), 449 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr), 450 DEVMETHOD(bus_child_location, mvs_child_location), 451 DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag), 452 DEVMETHOD(mvs_edma, mvs_edma), 453 { 0, 0 } 454 }; 455 static driver_t mvs_driver = { 456 "mvs", 457 mvs_methods, 458 sizeof(struct mvs_controller) 459 }; 460 DRIVER_MODULE(mvs, simplebus, mvs_driver, 0, 0); 461 MODULE_VERSION(mvs, 1); 462 MODULE_DEPEND(mvs, cam, 1, 1, 1); 463