1 /*- 2 * Copyright (c) 2012-2015 LSI Corp. 3 * Copyright (c) 2013-2016 Avago Technologies 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Copyright (c) 2000-2015 LSI Corporation. 37 * Copyright (c) 2013-2016 Avago Technologies 38 * All rights reserved. 39 * 40 * 41 * Name: mpi2_ioc.h 42 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 43 * Creation Date: October 11, 2006 44 * 45 * mpi2_ioc.h Version: 02.00.27 46 * 47 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 48 * prefix are for use only on MPI v2.5 products, and must not be used 49 * with MPI v2.0 products. Unless otherwise noted, names beginning with 50 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 51 * 52 * Version History 53 * --------------- 54 * 55 * Date Version Description 56 * -------- -------- ------------------------------------------------------ 57 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 58 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to 59 * MaxTargets. 60 * Added TotalImageSize field to FWDownload Request. 61 * Added reserved words to FWUpload Request. 62 * 06-26-07 02.00.02 Added IR Configuration Change List Event. 63 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit 64 * request and replaced it with 65 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. 66 * Replaced the MinReplyQueueDepth field of the IOCFacts 67 * reply with MaxReplyDescriptorPostQueueDepth. 68 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum 69 * depth for the Reply Descriptor Post Queue. 70 * Added SASAddress field to Initiator Device Table 71 * Overflow Event data. 72 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING 73 * for SAS Initiator Device Status Change Event data. 74 * Modified Reason Code defines for SAS Topology Change 75 * List Event data, including adding a bit for PHY Vacant 76 * status, and adding a mask for the Reason Code. 77 * Added define for 78 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. 79 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. 80 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of 81 * the IOCFacts Reply. 82 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 83 * Moved MPI2_VERSION_UNION to mpi2.h. 84 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks 85 * instead of enables, and added SASBroadcastPrimitiveMasks 86 * field. 87 * Added Log Entry Added Event and related structure. 88 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. 89 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. 90 * Added MaxVolumes and MaxPersistentEntries fields to 91 * IOCFacts reply. 92 * Added ProtocalFlags and IOCCapabilities fields to 93 * MPI2_FW_IMAGE_HEADER. 94 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. 95 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to 96 * a U16 (from a U32). 97 * Removed extra 's' from EventMasks name. 98 * 06-27-08 02.00.08 Fixed an offset in a comment. 99 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. 100 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and 101 * renamed MinReplyFrameSize to ReplyFrameSize. 102 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. 103 * Added two new RAIDOperation values for Integrated RAID 104 * Operations Status Event data. 105 * Added four new IR Configuration Change List Event data 106 * ReasonCode values. 107 * Added two new ReasonCode defines for SAS Device Status 108 * Change Event data. 109 * Added three new DiscoveryStatus bits for the SAS 110 * Discovery event data. 111 * Added Multiplexing Status Change bit to the PhyStatus 112 * field of the SAS Topology Change List event data. 113 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. 114 * BootFlags are now product-specific. 115 * Added defines for the indivdual signature bytes 116 * for MPI2_INIT_IMAGE_FOOTER. 117 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. 118 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR 119 * define. 120 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE 121 * define. 122 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. 123 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define. 124 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define. 125 * Added two new reason codes for SAS Device Status Change 126 * Event. 127 * Added new event: SAS PHY Counter. 128 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure. 129 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 130 * Added new product id family for 2208. 131 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST. 132 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY. 133 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY. 134 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY. 135 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define. 136 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define. 137 * Added Host Based Discovery Phy Event data. 138 * Added defines for ProductID Product field 139 * (MPI2_FW_HEADER_PID_). 140 * Modified values for SAS ProductID Family 141 * (MPI2_FW_HEADER_PID_FAMILY_). 142 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines. 143 * Added PowerManagementControl Request structures and 144 * defines. 145 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete. 146 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define. 147 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC. 148 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added 149 * SASNotifyPrimitiveMasks field to 150 * MPI2_EVENT_NOTIFICATION_REQUEST. 151 * Added Temperature Threshold Event. 152 * Added Host Message Event. 153 * Added Send Host Message request and reply. 154 * 05-25-11 02.00.18 For Extended Image Header, added 155 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and 156 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines. 157 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define. 158 * 08-24-11 02.00.19 Added PhysicalPort field to 159 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure. 160 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete. 161 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5. 162 * 03-29-12 02.00.21 Added a product specific range to event values. 163 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE. 164 * Added ElapsedSeconds field to 165 * MPI2_EVENT_DATA_IR_OPERATION_STATUS. 166 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE 167 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY. 168 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE. 169 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY. 170 * Added Encrypted Hash Extended Image. 171 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS. 172 * 11-18-14 02.00.25 Updated copyright information. 173 * 03-16-15 02.00.26 Updated for MPI v2.6. 174 * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and 175 * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT. 176 * Added MPI2_EVENT_PCIE_LINK_COUNTER and 177 * MPI26_EVENT_DATA_PCIE_LINK_COUNTER. 178 * Added MPI26_CTRL_OP_SHUTDOWN. 179 * Added MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG 180 * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS 181 * 08-25-15 02.00.27 Added IC ARCH Class based signature defines 182 * 183 * -------------------------------------------------------------------------- 184 */ 185 186 #ifndef MPI2_IOC_H 187 #define MPI2_IOC_H 188 189 /***************************************************************************** 190 * 191 * IOC Messages 192 * 193 *****************************************************************************/ 194 195 /**************************************************************************** 196 * IOCInit message 197 ****************************************************************************/ 198 199 /* IOCInit Request message */ 200 typedef struct _MPI2_IOC_INIT_REQUEST 201 { 202 U8 WhoInit; /* 0x00 */ 203 U8 Reserved1; /* 0x01 */ 204 U8 ChainOffset; /* 0x02 */ 205 U8 Function; /* 0x03 */ 206 U16 Reserved2; /* 0x04 */ 207 U8 Reserved3; /* 0x06 */ 208 U8 MsgFlags; /* 0x07 */ 209 U8 VP_ID; /* 0x08 */ 210 U8 VF_ID; /* 0x09 */ 211 U16 Reserved4; /* 0x0A */ 212 U16 MsgVersion; /* 0x0C */ 213 U16 HeaderVersion; /* 0x0E */ 214 U32 Reserved5; /* 0x10 */ 215 U16 ConfigurationFlags; /* 0x14 */ 216 U8 HostPageSize; /* 0x16 */ 217 U8 HostMSIxVectors; /* 0x17 */ 218 U16 Reserved8; /* 0x18 */ 219 U16 SystemRequestFrameSize; /* 0x1A */ 220 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 221 U16 ReplyFreeQueueDepth; /* 0x1E */ 222 U32 SenseBufferAddressHigh; /* 0x20 */ 223 U32 SystemReplyAddressHigh; /* 0x24 */ 224 U64 SystemRequestFrameBaseAddress; /* 0x28 */ 225 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 226 U64 ReplyFreeQueueAddress; /* 0x38 */ 227 U64 TimeStamp; /* 0x40 */ 228 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 229 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 230 231 /* WhoInit values */ 232 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 233 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 234 #define MPI2_WHOINIT_ROM_BIOS (0x02) 235 #define MPI2_WHOINIT_PCI_PEER (0x03) 236 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 237 #define MPI2_WHOINIT_MANUFACTURER (0x05) 238 239 /* MsgFlags */ 240 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) 241 242 /* MsgVersion */ 243 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 244 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 245 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 246 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 247 248 /* HeaderVersion */ 249 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) 250 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) 251 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) 252 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) 253 254 /* minimum depth for a Reply Descriptor Post Queue */ 255 #define MPI2_RDPQ_DEPTH_MIN (16) 256 257 /* Reply Descriptor Post Queue Array Entry */ 258 typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY 259 { 260 U64 RDPQBaseAddress; /* 0x00 */ 261 U32 Reserved1; /* 0x08 */ 262 U32 Reserved2; /* 0x0C */ 263 } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 264 MPI2_POINTER PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 265 Mpi2IOCInitRDPQArrayEntry, MPI2_POINTER pMpi2IOCInitRDPQArrayEntry; 266 267 /* IOCInit Reply message */ 268 typedef struct _MPI2_IOC_INIT_REPLY 269 { 270 U8 WhoInit; /* 0x00 */ 271 U8 Reserved1; /* 0x01 */ 272 U8 MsgLength; /* 0x02 */ 273 U8 Function; /* 0x03 */ 274 U16 Reserved2; /* 0x04 */ 275 U8 Reserved3; /* 0x06 */ 276 U8 MsgFlags; /* 0x07 */ 277 U8 VP_ID; /* 0x08 */ 278 U8 VF_ID; /* 0x09 */ 279 U16 Reserved4; /* 0x0A */ 280 U16 Reserved5; /* 0x0C */ 281 U16 IOCStatus; /* 0x0E */ 282 U32 IOCLogInfo; /* 0x10 */ 283 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY, 284 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t; 285 286 287 /**************************************************************************** 288 * IOCFacts message 289 ****************************************************************************/ 290 291 /* IOCFacts Request message */ 292 typedef struct _MPI2_IOC_FACTS_REQUEST 293 { 294 U16 Reserved1; /* 0x00 */ 295 U8 ChainOffset; /* 0x02 */ 296 U8 Function; /* 0x03 */ 297 U16 Reserved2; /* 0x04 */ 298 U8 Reserved3; /* 0x06 */ 299 U8 MsgFlags; /* 0x07 */ 300 U8 VP_ID; /* 0x08 */ 301 U8 VF_ID; /* 0x09 */ 302 U16 Reserved4; /* 0x0A */ 303 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST, 304 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t; 305 306 307 /* IOCFacts Reply message */ 308 typedef struct _MPI2_IOC_FACTS_REPLY 309 { 310 U16 MsgVersion; /* 0x00 */ 311 U8 MsgLength; /* 0x02 */ 312 U8 Function; /* 0x03 */ 313 U16 HeaderVersion; /* 0x04 */ 314 U8 IOCNumber; /* 0x06 */ 315 U8 MsgFlags; /* 0x07 */ 316 U8 VP_ID; /* 0x08 */ 317 U8 VF_ID; /* 0x09 */ 318 U16 Reserved1; /* 0x0A */ 319 U16 IOCExceptions; /* 0x0C */ 320 U16 IOCStatus; /* 0x0E */ 321 U32 IOCLogInfo; /* 0x10 */ 322 U8 MaxChainDepth; /* 0x14 */ 323 U8 WhoInit; /* 0x15 */ 324 U8 NumberOfPorts; /* 0x16 */ 325 U8 MaxMSIxVectors; /* 0x17 */ 326 U16 RequestCredit; /* 0x18 */ 327 U16 ProductID; /* 0x1A */ 328 U32 IOCCapabilities; /* 0x1C */ 329 MPI2_VERSION_UNION FWVersion; /* 0x20 */ 330 U16 IOCRequestFrameSize; /* 0x24 */ 331 U16 IOCMaxChainSegmentSize; /* 0x26 */ /* MPI 2.5 only; Reserved in MPI 2.0 */ 332 U16 MaxInitiators; /* 0x28 */ 333 U16 MaxTargets; /* 0x2A */ 334 U16 MaxSasExpanders; /* 0x2C */ 335 U16 MaxEnclosures; /* 0x2E */ 336 U16 ProtocolFlags; /* 0x30 */ 337 U16 HighPriorityCredit; /* 0x32 */ 338 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */ 339 U8 ReplyFrameSize; /* 0x36 */ 340 U8 MaxVolumes; /* 0x37 */ 341 U16 MaxDevHandle; /* 0x38 */ 342 U16 MaxPersistentEntries; /* 0x3A */ 343 U16 MinDevHandle; /* 0x3C */ 344 U8 CurrentHostPageSize; /* 0x3E */ 345 U8 Reserved4; /* 0x3F */ 346 U8 SGEModifierMask; /* 0x40 */ 347 U8 SGEModifierValue; /* 0x41 */ 348 U8 SGEModifierShift; /* 0x42 */ 349 U8 Reserved5; /* 0x43 */ 350 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY, 351 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t; 352 353 /* MsgVersion */ 354 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 355 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 356 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 357 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 358 359 /* HeaderVersion */ 360 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 361 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 362 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 363 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 364 365 /* IOCExceptions */ 366 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200) 367 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) 368 369 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) 370 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) 371 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) 372 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) 373 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) 374 375 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 376 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) 377 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 378 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 379 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 380 381 /* defines for WhoInit field are after the IOCInit Request */ 382 383 /* ProductID field uses MPI2_FW_HEADER_PID_ */ 384 385 /* IOCCapabilities */ 386 #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000) 387 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000) 388 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) 389 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000) 390 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000) 391 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) 392 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) 393 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) 394 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 395 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) 396 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) 397 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 398 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 399 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 400 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) 401 402 /* ProtocolFlags */ 403 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 404 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 405 406 407 /**************************************************************************** 408 * PortFacts message 409 ****************************************************************************/ 410 411 /* PortFacts Request message */ 412 typedef struct _MPI2_PORT_FACTS_REQUEST 413 { 414 U16 Reserved1; /* 0x00 */ 415 U8 ChainOffset; /* 0x02 */ 416 U8 Function; /* 0x03 */ 417 U16 Reserved2; /* 0x04 */ 418 U8 PortNumber; /* 0x06 */ 419 U8 MsgFlags; /* 0x07 */ 420 U8 VP_ID; /* 0x08 */ 421 U8 VF_ID; /* 0x09 */ 422 U16 Reserved3; /* 0x0A */ 423 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST, 424 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t; 425 426 /* PortFacts Reply message */ 427 typedef struct _MPI2_PORT_FACTS_REPLY 428 { 429 U16 Reserved1; /* 0x00 */ 430 U8 MsgLength; /* 0x02 */ 431 U8 Function; /* 0x03 */ 432 U16 Reserved2; /* 0x04 */ 433 U8 PortNumber; /* 0x06 */ 434 U8 MsgFlags; /* 0x07 */ 435 U8 VP_ID; /* 0x08 */ 436 U8 VF_ID; /* 0x09 */ 437 U16 Reserved3; /* 0x0A */ 438 U16 Reserved4; /* 0x0C */ 439 U16 IOCStatus; /* 0x0E */ 440 U32 IOCLogInfo; /* 0x10 */ 441 U8 Reserved5; /* 0x14 */ 442 U8 PortType; /* 0x15 */ 443 U16 Reserved6; /* 0x16 */ 444 U16 MaxPostedCmdBuffers; /* 0x18 */ 445 U16 Reserved7; /* 0x1A */ 446 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY, 447 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t; 448 449 /* PortType values */ 450 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) 451 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10) 452 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) 453 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 454 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 455 456 457 /**************************************************************************** 458 * PortEnable message 459 ****************************************************************************/ 460 461 /* PortEnable Request message */ 462 typedef struct _MPI2_PORT_ENABLE_REQUEST 463 { 464 U16 Reserved1; /* 0x00 */ 465 U8 ChainOffset; /* 0x02 */ 466 U8 Function; /* 0x03 */ 467 U8 Reserved2; /* 0x04 */ 468 U8 PortFlags; /* 0x05 */ 469 U8 Reserved3; /* 0x06 */ 470 U8 MsgFlags; /* 0x07 */ 471 U8 VP_ID; /* 0x08 */ 472 U8 VF_ID; /* 0x09 */ 473 U16 Reserved4; /* 0x0A */ 474 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST, 475 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t; 476 477 478 /* PortEnable Reply message */ 479 typedef struct _MPI2_PORT_ENABLE_REPLY 480 { 481 U16 Reserved1; /* 0x00 */ 482 U8 MsgLength; /* 0x02 */ 483 U8 Function; /* 0x03 */ 484 U8 Reserved2; /* 0x04 */ 485 U8 PortFlags; /* 0x05 */ 486 U8 Reserved3; /* 0x06 */ 487 U8 MsgFlags; /* 0x07 */ 488 U8 VP_ID; /* 0x08 */ 489 U8 VF_ID; /* 0x09 */ 490 U16 Reserved4; /* 0x0A */ 491 U16 Reserved5; /* 0x0C */ 492 U16 IOCStatus; /* 0x0E */ 493 U32 IOCLogInfo; /* 0x10 */ 494 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY, 495 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t; 496 497 498 /**************************************************************************** 499 * EventNotification message 500 ****************************************************************************/ 501 502 /* EventNotification Request message */ 503 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) 504 505 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST 506 { 507 U16 Reserved1; /* 0x00 */ 508 U8 ChainOffset; /* 0x02 */ 509 U8 Function; /* 0x03 */ 510 U16 Reserved2; /* 0x04 */ 511 U8 Reserved3; /* 0x06 */ 512 U8 MsgFlags; /* 0x07 */ 513 U8 VP_ID; /* 0x08 */ 514 U8 VF_ID; /* 0x09 */ 515 U16 Reserved4; /* 0x0A */ 516 U32 Reserved5; /* 0x0C */ 517 U32 Reserved6; /* 0x10 */ 518 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */ 519 U16 SASBroadcastPrimitiveMasks; /* 0x24 */ 520 U16 SASNotifyPrimitiveMasks; /* 0x26 */ 521 U32 Reserved8; /* 0x28 */ 522 } MPI2_EVENT_NOTIFICATION_REQUEST, 523 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST, 524 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t; 525 526 527 /* EventNotification Reply message */ 528 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY 529 { 530 U16 EventDataLength; /* 0x00 */ 531 U8 MsgLength; /* 0x02 */ 532 U8 Function; /* 0x03 */ 533 U16 Reserved1; /* 0x04 */ 534 U8 AckRequired; /* 0x06 */ 535 U8 MsgFlags; /* 0x07 */ 536 U8 VP_ID; /* 0x08 */ 537 U8 VF_ID; /* 0x09 */ 538 U16 Reserved2; /* 0x0A */ 539 U16 Reserved3; /* 0x0C */ 540 U16 IOCStatus; /* 0x0E */ 541 U32 IOCLogInfo; /* 0x10 */ 542 U16 Event; /* 0x14 */ 543 U16 Reserved4; /* 0x16 */ 544 U32 EventContext; /* 0x18 */ 545 U32 EventData[1]; /* 0x1C */ 546 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY, 547 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t; 548 549 /* AckRequired */ 550 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 551 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 552 553 /* Event */ 554 #define MPI2_EVENT_LOG_DATA (0x0001) 555 #define MPI2_EVENT_STATE_CHANGE (0x0002) 556 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) 557 #define MPI2_EVENT_EVENT_CHANGE (0x000A) 558 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */ 559 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) 560 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) 561 #define MPI2_EVENT_SAS_DISCOVERY (0x0016) 562 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) 563 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) 564 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) 565 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) 566 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) 567 #define MPI2_EVENT_IR_VOLUME (0x001E) 568 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) 569 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) 570 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) 571 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) 572 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023) 573 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024) 574 #define MPI2_EVENT_SAS_QUIESCE (0x0025) 575 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026) 576 #define MPI2_EVENT_TEMP_THRESHOLD (0x0027) 577 #define MPI2_EVENT_HOST_MESSAGE (0x0028) 578 #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029) 579 #define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034) /* MPI v2.6 and later */ 580 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E) 581 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F) 582 583 584 /* Log Entry Added Event data */ 585 586 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ 587 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) 588 589 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED 590 { 591 U64 TimeStamp; /* 0x00 */ 592 U32 Reserved1; /* 0x08 */ 593 U16 LogSequence; /* 0x0C */ 594 U16 LogEntryQualifier; /* 0x0E */ 595 U8 VP_ID; /* 0x10 */ 596 U8 VF_ID; /* 0x11 */ 597 U16 Reserved2; /* 0x12 */ 598 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */ 599 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 600 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 601 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t; 602 603 604 /* GPIO Interrupt Event data */ 605 606 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT 607 { 608 U8 GPIONum; /* 0x00 */ 609 U8 Reserved1; /* 0x01 */ 610 U16 Reserved2; /* 0x02 */ 611 } MPI2_EVENT_DATA_GPIO_INTERRUPT, 612 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT, 613 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t; 614 615 616 /* Temperature Threshold Event data */ 617 618 typedef struct _MPI2_EVENT_DATA_TEMPERATURE 619 { 620 U16 Status; /* 0x00 */ 621 U8 SensorNum; /* 0x02 */ 622 U8 Reserved1; /* 0x03 */ 623 U16 CurrentTemperature; /* 0x04 */ 624 U16 Reserved2; /* 0x06 */ 625 U32 Reserved3; /* 0x08 */ 626 U32 Reserved4; /* 0x0C */ 627 } MPI2_EVENT_DATA_TEMPERATURE, 628 MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE, 629 Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t; 630 631 /* Temperature Threshold Event data Status bits */ 632 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008) 633 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004) 634 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002) 635 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001) 636 637 638 /* Host Message Event data */ 639 640 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE 641 { 642 U8 SourceVF_ID; /* 0x00 */ 643 U8 Reserved1; /* 0x01 */ 644 U16 Reserved2; /* 0x02 */ 645 U32 Reserved3; /* 0x04 */ 646 U32 HostData[1]; /* 0x08 */ 647 } MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE, 648 Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t; 649 650 651 /* Power Performance Change Event data */ 652 653 typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE 654 { 655 U8 CurrentPowerMode; /* 0x00 */ 656 U8 PreviousPowerMode; /* 0x01 */ 657 U16 Reserved1; /* 0x02 */ 658 } MPI2_EVENT_DATA_POWER_PERF_CHANGE, 659 MPI2_POINTER PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE, 660 Mpi2EventDataPowerPerfChange_t, MPI2_POINTER pMpi2EventDataPowerPerfChange_t; 661 662 /* defines for CurrentPowerMode and PreviousPowerMode fields */ 663 #define MPI2_EVENT_PM_INIT_MASK (0xC0) 664 #define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00) 665 #define MPI2_EVENT_PM_INIT_HOST (0x40) 666 #define MPI2_EVENT_PM_INIT_IO_UNIT (0x80) 667 #define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0) 668 669 #define MPI2_EVENT_PM_MODE_MASK (0x07) 670 #define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00) 671 #define MPI2_EVENT_PM_MODE_UNKNOWN (0x01) 672 #define MPI2_EVENT_PM_MODE_FULL_POWER (0x04) 673 #define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05) 674 #define MPI2_EVENT_PM_MODE_STANDBY (0x06) 675 676 677 /* Active Cable Exception Event data */ 678 679 typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT 680 { 681 U32 ActiveCablePowerRequirement; /* 0x00 */ 682 U8 ReasonCode; /* 0x04 */ 683 U8 ReceptacleID; /* 0x05 */ 684 U16 Reserved1; /* 0x06 */ 685 } MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT, 686 MPI2_POINTER PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT, 687 Mpi26EventDataActiveCableExcept_t, 688 MPI2_POINTER pMpi26EventDataActiveCableExcept_t; 689 690 /* defines for ReasonCode field */ 691 #define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00) 692 693 694 /* Hard Reset Received Event data */ 695 696 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED 697 { 698 U8 Reserved1; /* 0x00 */ 699 U8 Port; /* 0x01 */ 700 U16 Reserved2; /* 0x02 */ 701 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 702 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 703 Mpi2EventDataHardResetReceived_t, 704 MPI2_POINTER pMpi2EventDataHardResetReceived_t; 705 706 707 /* Task Set Full Event data */ 708 /* this event is obsolete */ 709 710 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL 711 { 712 U16 DevHandle; /* 0x00 */ 713 U16 CurrentDepth; /* 0x02 */ 714 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL, 715 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t; 716 717 718 /* SAS Device Status Change Event data */ 719 720 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE 721 { 722 U16 TaskTag; /* 0x00 */ 723 U8 ReasonCode; /* 0x02 */ 724 U8 PhysicalPort; /* 0x03 */ 725 U8 ASC; /* 0x04 */ 726 U8 ASCQ; /* 0x05 */ 727 U16 DevHandle; /* 0x06 */ 728 U32 Reserved2; /* 0x08 */ 729 U64 SASAddress; /* 0x0C */ 730 U8 LUN[8]; /* 0x14 */ 731 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 732 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 733 Mpi2EventDataSasDeviceStatusChange_t, 734 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t; 735 736 /* SAS Device Status Change Event data ReasonCode values */ 737 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 738 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 739 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 740 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 741 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 742 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 743 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 744 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 745 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 746 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 747 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) 748 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11) 749 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12) 750 751 752 /* Integrated RAID Operation Status Event data */ 753 754 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS 755 { 756 U16 VolDevHandle; /* 0x00 */ 757 U16 Reserved1; /* 0x02 */ 758 U8 RAIDOperation; /* 0x04 */ 759 U8 PercentComplete; /* 0x05 */ 760 U16 Reserved2; /* 0x06 */ 761 U32 ElapsedSeconds; /* 0x08 */ 762 } MPI2_EVENT_DATA_IR_OPERATION_STATUS, 763 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, 764 Mpi2EventDataIrOperationStatus_t, 765 MPI2_POINTER pMpi2EventDataIrOperationStatus_t; 766 767 /* Integrated RAID Operation Status Event data RAIDOperation values */ 768 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) 769 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) 770 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) 771 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) 772 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) 773 774 775 /* Integrated RAID Volume Event data */ 776 777 typedef struct _MPI2_EVENT_DATA_IR_VOLUME 778 { 779 U16 VolDevHandle; /* 0x00 */ 780 U8 ReasonCode; /* 0x02 */ 781 U8 Reserved1; /* 0x03 */ 782 U32 NewValue; /* 0x04 */ 783 U32 PreviousValue; /* 0x08 */ 784 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME, 785 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t; 786 787 /* Integrated RAID Volume Event data ReasonCode values */ 788 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) 789 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) 790 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) 791 792 793 /* Integrated RAID Physical Disk Event data */ 794 795 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK 796 { 797 U16 Reserved1; /* 0x00 */ 798 U8 ReasonCode; /* 0x02 */ 799 U8 PhysDiskNum; /* 0x03 */ 800 U16 PhysDiskDevHandle; /* 0x04 */ 801 U16 Reserved2; /* 0x06 */ 802 U16 Slot; /* 0x08 */ 803 U16 EnclosureHandle; /* 0x0A */ 804 U32 NewValue; /* 0x0C */ 805 U32 PreviousValue; /* 0x10 */ 806 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 807 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 808 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t; 809 810 /* Integrated RAID Physical Disk Event data ReasonCode values */ 811 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) 812 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) 813 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) 814 815 816 /* Integrated RAID Configuration Change List Event data */ 817 818 /* 819 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 820 * one and check NumElements at runtime. 821 */ 822 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT 823 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1) 824 #endif 825 826 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT 827 { 828 U16 ElementFlags; /* 0x00 */ 829 U16 VolDevHandle; /* 0x02 */ 830 U8 ReasonCode; /* 0x04 */ 831 U8 PhysDiskNum; /* 0x05 */ 832 U16 PhysDiskDevHandle; /* 0x06 */ 833 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, 834 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t; 835 836 /* IR Configuration Change List Event data ElementFlags values */ 837 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) 838 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) 839 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) 840 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) 841 842 /* IR Configuration Change List Event data ReasonCode values */ 843 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) 844 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) 845 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) 846 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) 847 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) 848 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) 849 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) 850 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) 851 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) 852 853 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST 854 { 855 U8 NumElements; /* 0x00 */ 856 U8 Reserved1; /* 0x01 */ 857 U8 Reserved2; /* 0x02 */ 858 U8 ConfigNum; /* 0x03 */ 859 U32 Flags; /* 0x04 */ 860 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */ 861 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 862 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 863 Mpi2EventDataIrConfigChangeList_t, 864 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t; 865 866 /* IR Configuration Change List Event data Flags values */ 867 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) 868 869 870 /* SAS Discovery Event data */ 871 872 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY 873 { 874 U8 Flags; /* 0x00 */ 875 U8 ReasonCode; /* 0x01 */ 876 U8 PhysicalPort; /* 0x02 */ 877 U8 Reserved1; /* 0x03 */ 878 U32 DiscoveryStatus; /* 0x04 */ 879 } MPI2_EVENT_DATA_SAS_DISCOVERY, 880 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, 881 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t; 882 883 /* SAS Discovery Event data Flags values */ 884 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) 885 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) 886 887 /* SAS Discovery Event data ReasonCode values */ 888 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) 889 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) 890 891 /* SAS Discovery Event data DiscoveryStatus values */ 892 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 893 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) 894 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) 895 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 896 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) 897 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 898 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 899 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) 900 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 901 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) 902 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) 903 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) 904 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) 905 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) 906 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) 907 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) 908 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) 909 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) 910 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) 911 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) 912 913 914 /* SAS Broadcast Primitive Event data */ 915 916 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE 917 { 918 U8 PhyNum; /* 0x00 */ 919 U8 Port; /* 0x01 */ 920 U8 PortWidth; /* 0x02 */ 921 U8 Primitive; /* 0x03 */ 922 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 923 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 924 Mpi2EventDataSasBroadcastPrimitive_t, 925 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t; 926 927 /* defines for the Primitive field */ 928 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) 929 #define MPI2_EVENT_PRIMITIVE_SES (0x02) 930 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) 931 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 932 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) 933 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) 934 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 935 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 936 937 938 /* SAS Notify Primitive Event data */ 939 940 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE 941 { 942 U8 PhyNum; /* 0x00 */ 943 U8 Port; /* 0x01 */ 944 U8 Reserved1; /* 0x02 */ 945 U8 Primitive; /* 0x03 */ 946 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 947 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 948 Mpi2EventDataSasNotifyPrimitive_t, 949 MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t; 950 951 /* defines for the Primitive field */ 952 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01) 953 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02) 954 #define MPI2_EVENT_NOTIFY_RESERVED1 (0x03) 955 #define MPI2_EVENT_NOTIFY_RESERVED2 (0x04) 956 957 958 /* SAS Initiator Device Status Change Event data */ 959 960 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE 961 { 962 U8 ReasonCode; /* 0x00 */ 963 U8 PhysicalPort; /* 0x01 */ 964 U16 DevHandle; /* 0x02 */ 965 U64 SASAddress; /* 0x04 */ 966 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 967 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 968 Mpi2EventDataSasInitDevStatusChange_t, 969 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t; 970 971 /* SAS Initiator Device Status Change event ReasonCode values */ 972 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) 973 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 974 975 976 /* SAS Initiator Device Table Overflow Event data */ 977 978 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW 979 { 980 U16 MaxInit; /* 0x00 */ 981 U16 CurrentInit; /* 0x02 */ 982 U64 SASAddress; /* 0x04 */ 983 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 984 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 985 Mpi2EventDataSasInitTableOverflow_t, 986 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t; 987 988 989 /* SAS Topology Change List Event data */ 990 991 /* 992 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 993 * one and check NumEntries at runtime. 994 */ 995 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT 996 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1) 997 #endif 998 999 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY 1000 { 1001 U16 AttachedDevHandle; /* 0x00 */ 1002 U8 LinkRate; /* 0x02 */ 1003 U8 PhyStatus; /* 0x03 */ 1004 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, 1005 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t; 1006 1007 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST 1008 { 1009 U16 EnclosureHandle; /* 0x00 */ 1010 U16 ExpanderDevHandle; /* 0x02 */ 1011 U8 NumPhys; /* 0x04 */ 1012 U8 Reserved1; /* 0x05 */ 1013 U16 Reserved2; /* 0x06 */ 1014 U8 NumEntries; /* 0x08 */ 1015 U8 StartPhyNum; /* 0x09 */ 1016 U8 ExpStatus; /* 0x0A */ 1017 U8 PhysicalPort; /* 0x0B */ 1018 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/ 1019 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 1020 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 1021 Mpi2EventDataSasTopologyChangeList_t, 1022 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t; 1023 1024 /* values for the ExpStatus field */ 1025 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 1026 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) 1027 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 1028 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 1029 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 1030 1031 /* defines for the LinkRate field */ 1032 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) 1033 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 1034 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) 1035 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 1036 1037 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 1038 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 1039 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 1040 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 1041 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 1042 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 1043 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 1044 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) 1045 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) 1046 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) 1047 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B) 1048 1049 /* values for the PhyStatus field */ 1050 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) 1051 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) 1052 /* values for the PhyStatus ReasonCode sub-field */ 1053 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) 1054 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) 1055 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) 1056 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) 1057 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) 1058 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) 1059 1060 1061 /* SAS Enclosure Device Status Change Event data */ 1062 1063 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE 1064 { 1065 U16 EnclosureHandle; /* 0x00 */ 1066 U8 ReasonCode; /* 0x02 */ 1067 U8 PhysicalPort; /* 0x03 */ 1068 U64 EnclosureLogicalID; /* 0x04 */ 1069 U16 NumSlots; /* 0x0C */ 1070 U16 StartSlot; /* 0x0E */ 1071 U32 PhyBits; /* 0x10 */ 1072 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 1073 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 1074 Mpi2EventDataSasEnclDevStatusChange_t, 1075 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t; 1076 1077 /* SAS Enclosure Device Status Change event ReasonCode values */ 1078 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) 1079 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) 1080 1081 1082 /* SAS PHY Counter Event data */ 1083 1084 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER 1085 { 1086 U64 TimeStamp; /* 0x00 */ 1087 U32 Reserved1; /* 0x08 */ 1088 U8 PhyEventCode; /* 0x0C */ 1089 U8 PhyNum; /* 0x0D */ 1090 U16 Reserved2; /* 0x0E */ 1091 U32 PhyEventInfo; /* 0x10 */ 1092 U8 CounterType; /* 0x14 */ 1093 U8 ThresholdWindow; /* 0x15 */ 1094 U8 TimeUnits; /* 0x16 */ 1095 U8 Reserved3; /* 0x17 */ 1096 U32 EventThreshold; /* 0x18 */ 1097 U16 ThresholdFlags; /* 0x1C */ 1098 U16 Reserved4; /* 0x1E */ 1099 } MPI2_EVENT_DATA_SAS_PHY_COUNTER, 1100 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER, 1101 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t; 1102 1103 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */ 1104 1105 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */ 1106 1107 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */ 1108 1109 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */ 1110 1111 1112 /* SAS Quiesce Event data */ 1113 1114 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE 1115 { 1116 U8 ReasonCode; /* 0x00 */ 1117 U8 Reserved1; /* 0x01 */ 1118 U16 Reserved2; /* 0x02 */ 1119 U32 Reserved3; /* 0x04 */ 1120 } MPI2_EVENT_DATA_SAS_QUIESCE, 1121 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE, 1122 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t; 1123 1124 /* SAS Quiesce Event data ReasonCode values */ 1125 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01) 1126 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02) 1127 1128 1129 /* Host Based Discovery Phy Event data */ 1130 1131 typedef struct _MPI2_EVENT_HBD_PHY_SAS 1132 { 1133 U8 Flags; /* 0x00 */ 1134 U8 NegotiatedLinkRate; /* 0x01 */ 1135 U8 PhyNum; /* 0x02 */ 1136 U8 PhysicalPort; /* 0x03 */ 1137 U32 Reserved1; /* 0x04 */ 1138 U8 InitialFrame[28]; /* 0x08 */ 1139 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS, 1140 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t; 1141 1142 /* values for the Flags field */ 1143 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02) 1144 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01) 1145 1146 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */ 1147 1148 typedef union _MPI2_EVENT_HBD_DESCRIPTOR 1149 { 1150 MPI2_EVENT_HBD_PHY_SAS Sas; 1151 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR, 1152 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t; 1153 1154 typedef struct _MPI2_EVENT_DATA_HBD_PHY 1155 { 1156 U8 DescriptorType; /* 0x00 */ 1157 U8 Reserved1; /* 0x01 */ 1158 U16 Reserved2; /* 0x02 */ 1159 U32 Reserved3; /* 0x04 */ 1160 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */ 1161 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY, 1162 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t; 1163 1164 /* values for the DescriptorType field */ 1165 #define MPI2_EVENT_HBD_DT_SAS (0x01) 1166 1167 1168 /**************************************************************************** 1169 * EventAck message 1170 ****************************************************************************/ 1171 1172 /* EventAck Request message */ 1173 typedef struct _MPI2_EVENT_ACK_REQUEST 1174 { 1175 U16 Reserved1; /* 0x00 */ 1176 U8 ChainOffset; /* 0x02 */ 1177 U8 Function; /* 0x03 */ 1178 U16 Reserved2; /* 0x04 */ 1179 U8 Reserved3; /* 0x06 */ 1180 U8 MsgFlags; /* 0x07 */ 1181 U8 VP_ID; /* 0x08 */ 1182 U8 VF_ID; /* 0x09 */ 1183 U16 Reserved4; /* 0x0A */ 1184 U16 Event; /* 0x0C */ 1185 U16 Reserved5; /* 0x0E */ 1186 U32 EventContext; /* 0x10 */ 1187 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST, 1188 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t; 1189 1190 1191 /* EventAck Reply message */ 1192 typedef struct _MPI2_EVENT_ACK_REPLY 1193 { 1194 U16 Reserved1; /* 0x00 */ 1195 U8 MsgLength; /* 0x02 */ 1196 U8 Function; /* 0x03 */ 1197 U16 Reserved2; /* 0x04 */ 1198 U8 Reserved3; /* 0x06 */ 1199 U8 MsgFlags; /* 0x07 */ 1200 U8 VP_ID; /* 0x08 */ 1201 U8 VF_ID; /* 0x09 */ 1202 U16 Reserved4; /* 0x0A */ 1203 U16 Reserved5; /* 0x0C */ 1204 U16 IOCStatus; /* 0x0E */ 1205 U32 IOCLogInfo; /* 0x10 */ 1206 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY, 1207 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t; 1208 1209 1210 /**************************************************************************** 1211 * SendHostMessage message 1212 ****************************************************************************/ 1213 1214 /* SendHostMessage Request message */ 1215 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST 1216 { 1217 U16 HostDataLength; /* 0x00 */ 1218 U8 ChainOffset; /* 0x02 */ 1219 U8 Function; /* 0x03 */ 1220 U16 Reserved1; /* 0x04 */ 1221 U8 Reserved2; /* 0x06 */ 1222 U8 MsgFlags; /* 0x07 */ 1223 U8 VP_ID; /* 0x08 */ 1224 U8 VF_ID; /* 0x09 */ 1225 U16 Reserved3; /* 0x0A */ 1226 U8 Reserved4; /* 0x0C */ 1227 U8 DestVF_ID; /* 0x0D */ 1228 U16 Reserved5; /* 0x0E */ 1229 U32 Reserved6; /* 0x10 */ 1230 U32 Reserved7; /* 0x14 */ 1231 U32 Reserved8; /* 0x18 */ 1232 U32 Reserved9; /* 0x1C */ 1233 U32 Reserved10; /* 0x20 */ 1234 U32 HostData[1]; /* 0x24 */ 1235 } MPI2_SEND_HOST_MESSAGE_REQUEST, 1236 MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST, 1237 Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t; 1238 1239 1240 /* SendHostMessage Reply message */ 1241 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY 1242 { 1243 U16 HostDataLength; /* 0x00 */ 1244 U8 MsgLength; /* 0x02 */ 1245 U8 Function; /* 0x03 */ 1246 U16 Reserved1; /* 0x04 */ 1247 U8 Reserved2; /* 0x06 */ 1248 U8 MsgFlags; /* 0x07 */ 1249 U8 VP_ID; /* 0x08 */ 1250 U8 VF_ID; /* 0x09 */ 1251 U16 Reserved3; /* 0x0A */ 1252 U16 Reserved4; /* 0x0C */ 1253 U16 IOCStatus; /* 0x0E */ 1254 U32 IOCLogInfo; /* 0x10 */ 1255 } MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY, 1256 Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t; 1257 1258 1259 /**************************************************************************** 1260 * FWDownload message 1261 ****************************************************************************/ 1262 1263 /* MPI v2.0 FWDownload Request message */ 1264 typedef struct _MPI2_FW_DOWNLOAD_REQUEST 1265 { 1266 U8 ImageType; /* 0x00 */ 1267 U8 Reserved1; /* 0x01 */ 1268 U8 ChainOffset; /* 0x02 */ 1269 U8 Function; /* 0x03 */ 1270 U16 Reserved2; /* 0x04 */ 1271 U8 Reserved3; /* 0x06 */ 1272 U8 MsgFlags; /* 0x07 */ 1273 U8 VP_ID; /* 0x08 */ 1274 U8 VF_ID; /* 0x09 */ 1275 U16 Reserved4; /* 0x0A */ 1276 U32 TotalImageSize; /* 0x0C */ 1277 U32 Reserved5; /* 0x10 */ 1278 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1279 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST, 1280 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest; 1281 1282 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1283 1284 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) 1285 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1286 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1287 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1288 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1289 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1290 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) 1291 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1292 #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C) /* MPI v2.5 and newer */ 1293 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) 1294 1295 /* MPI v2.0 FWDownload TransactionContext Element */ 1296 typedef struct _MPI2_FW_DOWNLOAD_TCSGE 1297 { 1298 U8 Reserved1; /* 0x00 */ 1299 U8 ContextSize; /* 0x01 */ 1300 U8 DetailsLength; /* 0x02 */ 1301 U8 Flags; /* 0x03 */ 1302 U32 Reserved2; /* 0x04 */ 1303 U32 ImageOffset; /* 0x08 */ 1304 U32 ImageSize; /* 0x0C */ 1305 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE, 1306 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t; 1307 1308 1309 /* MPI v2.5 FWDownload Request message */ 1310 typedef struct _MPI25_FW_DOWNLOAD_REQUEST 1311 { 1312 U8 ImageType; /* 0x00 */ 1313 U8 Reserved1; /* 0x01 */ 1314 U8 ChainOffset; /* 0x02 */ 1315 U8 Function; /* 0x03 */ 1316 U16 Reserved2; /* 0x04 */ 1317 U8 Reserved3; /* 0x06 */ 1318 U8 MsgFlags; /* 0x07 */ 1319 U8 VP_ID; /* 0x08 */ 1320 U8 VF_ID; /* 0x09 */ 1321 U16 Reserved4; /* 0x0A */ 1322 U32 TotalImageSize; /* 0x0C */ 1323 U32 Reserved5; /* 0x10 */ 1324 U32 Reserved6; /* 0x14 */ 1325 U32 ImageOffset; /* 0x18 */ 1326 U32 ImageSize; /* 0x1C */ 1327 MPI25_SGE_IO_UNION SGL; /* 0x20 */ 1328 } MPI25_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_DOWNLOAD_REQUEST, 1329 Mpi25FWDownloadRequest, MPI2_POINTER pMpi25FWDownloadRequest; 1330 1331 1332 /* FWDownload Reply message */ 1333 typedef struct _MPI2_FW_DOWNLOAD_REPLY 1334 { 1335 U8 ImageType; /* 0x00 */ 1336 U8 Reserved1; /* 0x01 */ 1337 U8 MsgLength; /* 0x02 */ 1338 U8 Function; /* 0x03 */ 1339 U16 Reserved2; /* 0x04 */ 1340 U8 Reserved3; /* 0x06 */ 1341 U8 MsgFlags; /* 0x07 */ 1342 U8 VP_ID; /* 0x08 */ 1343 U8 VF_ID; /* 0x09 */ 1344 U16 Reserved4; /* 0x0A */ 1345 U16 Reserved5; /* 0x0C */ 1346 U16 IOCStatus; /* 0x0E */ 1347 U32 IOCLogInfo; /* 0x10 */ 1348 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY, 1349 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t; 1350 1351 1352 /**************************************************************************** 1353 * FWUpload message 1354 ****************************************************************************/ 1355 1356 /* MPI v2.0 FWUpload Request message */ 1357 typedef struct _MPI2_FW_UPLOAD_REQUEST 1358 { 1359 U8 ImageType; /* 0x00 */ 1360 U8 Reserved1; /* 0x01 */ 1361 U8 ChainOffset; /* 0x02 */ 1362 U8 Function; /* 0x03 */ 1363 U16 Reserved2; /* 0x04 */ 1364 U8 Reserved3; /* 0x06 */ 1365 U8 MsgFlags; /* 0x07 */ 1366 U8 VP_ID; /* 0x08 */ 1367 U8 VF_ID; /* 0x09 */ 1368 U16 Reserved4; /* 0x0A */ 1369 U32 Reserved5; /* 0x0C */ 1370 U32 Reserved6; /* 0x10 */ 1371 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1372 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST, 1373 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t; 1374 1375 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) 1376 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1377 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1378 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1379 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1380 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1381 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1382 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1383 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1384 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1385 #define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D) 1386 1387 /* MPI v2.0 FWUpload TransactionContext Element */ 1388 typedef struct _MPI2_FW_UPLOAD_TCSGE 1389 { 1390 U8 Reserved1; /* 0x00 */ 1391 U8 ContextSize; /* 0x01 */ 1392 U8 DetailsLength; /* 0x02 */ 1393 U8 Flags; /* 0x03 */ 1394 U32 Reserved2; /* 0x04 */ 1395 U32 ImageOffset; /* 0x08 */ 1396 U32 ImageSize; /* 0x0C */ 1397 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE, 1398 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t; 1399 1400 1401 /* MPI v2.5 FWUpload Request message */ 1402 typedef struct _MPI25_FW_UPLOAD_REQUEST 1403 { 1404 U8 ImageType; /* 0x00 */ 1405 U8 Reserved1; /* 0x01 */ 1406 U8 ChainOffset; /* 0x02 */ 1407 U8 Function; /* 0x03 */ 1408 U16 Reserved2; /* 0x04 */ 1409 U8 Reserved3; /* 0x06 */ 1410 U8 MsgFlags; /* 0x07 */ 1411 U8 VP_ID; /* 0x08 */ 1412 U8 VF_ID; /* 0x09 */ 1413 U16 Reserved4; /* 0x0A */ 1414 U32 Reserved5; /* 0x0C */ 1415 U32 Reserved6; /* 0x10 */ 1416 U32 Reserved7; /* 0x14 */ 1417 U32 ImageOffset; /* 0x18 */ 1418 U32 ImageSize; /* 0x1C */ 1419 MPI25_SGE_IO_UNION SGL; /* 0x20 */ 1420 } MPI25_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_UPLOAD_REQUEST, 1421 Mpi25FWUploadRequest_t, MPI2_POINTER pMpi25FWUploadRequest_t; 1422 1423 1424 /* FWUpload Reply message */ 1425 typedef struct _MPI2_FW_UPLOAD_REPLY 1426 { 1427 U8 ImageType; /* 0x00 */ 1428 U8 Reserved1; /* 0x01 */ 1429 U8 MsgLength; /* 0x02 */ 1430 U8 Function; /* 0x03 */ 1431 U16 Reserved2; /* 0x04 */ 1432 U8 Reserved3; /* 0x06 */ 1433 U8 MsgFlags; /* 0x07 */ 1434 U8 VP_ID; /* 0x08 */ 1435 U8 VF_ID; /* 0x09 */ 1436 U16 Reserved4; /* 0x0A */ 1437 U16 Reserved5; /* 0x0C */ 1438 U16 IOCStatus; /* 0x0E */ 1439 U32 IOCLogInfo; /* 0x10 */ 1440 U32 ActualImageSize; /* 0x14 */ 1441 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY, 1442 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t; 1443 1444 1445 /* FW Image Header */ 1446 typedef struct _MPI2_FW_IMAGE_HEADER 1447 { 1448 U32 Signature; /* 0x00 */ 1449 U32 Signature0; /* 0x04 */ 1450 U32 Signature1; /* 0x08 */ 1451 U32 Signature2; /* 0x0C */ 1452 MPI2_VERSION_UNION MPIVersion; /* 0x10 */ 1453 MPI2_VERSION_UNION FWVersion; /* 0x14 */ 1454 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */ 1455 MPI2_VERSION_UNION PackageVersion; /* 0x1C */ 1456 U16 VendorID; /* 0x20 */ 1457 U16 ProductID; /* 0x22 */ 1458 U16 ProtocolFlags; /* 0x24 */ 1459 U16 Reserved26; /* 0x26 */ 1460 U32 IOCCapabilities; /* 0x28 */ 1461 U32 ImageSize; /* 0x2C */ 1462 U32 NextImageHeaderOffset; /* 0x30 */ 1463 U32 Checksum; /* 0x34 */ 1464 U32 Reserved38; /* 0x38 */ 1465 U32 Reserved3C; /* 0x3C */ 1466 U32 Reserved40; /* 0x40 */ 1467 U32 Reserved44; /* 0x44 */ 1468 U32 Reserved48; /* 0x48 */ 1469 U32 Reserved4C; /* 0x4C */ 1470 U32 Reserved50; /* 0x50 */ 1471 U32 Reserved54; /* 0x54 */ 1472 U32 Reserved58; /* 0x58 */ 1473 U32 Reserved5C; /* 0x5C */ 1474 U32 BootFlags; /* 0x60 */ /* reserved in MPI v2.5 and earlier */ 1475 U32 FirmwareVersionNameWhat; /* 0x64 */ 1476 U8 FirmwareVersionName[32]; /* 0x68 */ 1477 U32 VendorNameWhat; /* 0x88 */ 1478 U8 VendorName[32]; /* 0x8C */ 1479 U32 PackageNameWhat; /* 0x88 */ 1480 U8 PackageName[32]; /* 0x8C */ 1481 U32 ReservedD0; /* 0xD0 */ 1482 U32 ReservedD4; /* 0xD4 */ 1483 U32 ReservedD8; /* 0xD8 */ 1484 U32 ReservedDC; /* 0xDC */ 1485 U32 ReservedE0; /* 0xE0 */ 1486 U32 ReservedE4; /* 0xE4 */ 1487 U32 ReservedE8; /* 0xE8 */ 1488 U32 ReservedEC; /* 0xEC */ 1489 U32 ReservedF0; /* 0xF0 */ 1490 U32 ReservedF4; /* 0xF4 */ 1491 U32 ReservedF8; /* 0xF8 */ 1492 U32 ReservedFC; /* 0xFC */ 1493 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER, 1494 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t; 1495 1496 /* Signature field */ 1497 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) 1498 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) 1499 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000) 1500 #define MPI26_FW_HEADER_SIGNATURE (0xEB000000) 1501 1502 /* Signature0 field */ 1503 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) 1504 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) 1505 #define MPI26_FW_HEADER_SIGNATURE0_BASE (0x5AEAA500) /* Last byte is defined by architecture */ 1506 #define MPI26_FW_HEADER_SIGNATURE0_ARC_0 (0x5A) 1507 #define MPI26_FW_HEADER_SIGNATURE0_ARC_1 (0x00) 1508 #define MPI26_FW_HEADER_SIGNATURE0_ARC_2 (0x01) 1509 #define MPI26_FW_HEADER_SIGNATURE0 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_0) // legacy (0x5AEAA55A) 1510 #define MPI26_FW_HEADER_SIGNATURE0_3516 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_1) 1511 1512 /* Signature1 field */ 1513 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) 1514 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) 1515 #define MPI26_FW_HEADER_SIGNATURE1 (0xA55AEAA5) 1516 1517 /* Signature2 field */ 1518 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) 1519 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) 1520 #define MPI26_FW_HEADER_SIGNATURE2 (0x5AA55AEA) 1521 1522 1523 /* defines for using the ProductID field */ 1524 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000) 1525 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000) 1526 1527 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00) 1528 #define MPI2_FW_HEADER_PID_PROD_A (0x0000) 1529 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 1530 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700) 1531 1532 1533 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1534 /* SAS ProductID Family bits */ 1535 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013) 1536 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014) 1537 #define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021) 1538 #define MPI26_FW_HEADER_PID_FAMILY_3324_SAS (0x0028) 1539 #define MPI26_FW_HEADER_PID_FAMILY_3516_SAS (0x0031) 1540 1541 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ 1542 1543 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */ 1544 1545 1546 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) 1547 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) 1548 #define MPI26_FW_HEADER_BOOTFLAGS_OFFSET (0x60) 1549 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) 1550 1551 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) 1552 1553 #define MPI2_FW_HEADER_SIZE (0x100) 1554 1555 1556 /* Extended Image Header */ 1557 typedef struct _MPI2_EXT_IMAGE_HEADER 1558 1559 { 1560 U8 ImageType; /* 0x00 */ 1561 U8 Reserved1; /* 0x01 */ 1562 U16 Reserved2; /* 0x02 */ 1563 U32 Checksum; /* 0x04 */ 1564 U32 ImageSize; /* 0x08 */ 1565 U32 NextImageHeaderOffset; /* 0x0C */ 1566 U32 PackageVersion; /* 0x10 */ 1567 U32 Reserved3; /* 0x14 */ 1568 U32 Reserved4; /* 0x18 */ 1569 U32 Reserved5; /* 0x1C */ 1570 U8 IdentifyString[32]; /* 0x20 */ 1571 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER, 1572 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t; 1573 1574 /* useful offsets */ 1575 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) 1576 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) 1577 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) 1578 1579 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40) 1580 1581 /* defines for the ImageType field */ 1582 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 1583 #define MPI2_EXT_IMAGE_TYPE_FW (0x01) 1584 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03) 1585 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04) 1586 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05) 1587 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06) 1588 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) 1589 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08) 1590 #define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09) /* MPI v2.5 and newer */ 1591 #define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80) 1592 #define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF) 1593 1594 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC) /* deprecated */ 1595 1596 1597 1598 /* FLASH Layout Extended Image Data */ 1599 1600 /* 1601 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1602 * one and check RegionsPerLayout at runtime. 1603 */ 1604 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS 1605 #define MPI2_FLASH_NUMBER_OF_REGIONS (1) 1606 #endif 1607 1608 /* 1609 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1610 * one and check NumberOfLayouts at runtime. 1611 */ 1612 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS 1613 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1) 1614 #endif 1615 1616 typedef struct _MPI2_FLASH_REGION 1617 { 1618 U8 RegionType; /* 0x00 */ 1619 U8 Reserved1; /* 0x01 */ 1620 U16 Reserved2; /* 0x02 */ 1621 U32 RegionOffset; /* 0x04 */ 1622 U32 RegionSize; /* 0x08 */ 1623 U32 Reserved3; /* 0x0C */ 1624 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION, 1625 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t; 1626 1627 typedef struct _MPI2_FLASH_LAYOUT 1628 { 1629 U32 FlashSize; /* 0x00 */ 1630 U32 Reserved1; /* 0x04 */ 1631 U32 Reserved2; /* 0x08 */ 1632 U32 Reserved3; /* 0x0C */ 1633 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */ 1634 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT, 1635 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t; 1636 1637 typedef struct _MPI2_FLASH_LAYOUT_DATA 1638 { 1639 U8 ImageRevision; /* 0x00 */ 1640 U8 Reserved1; /* 0x01 */ 1641 U8 SizeOfRegion; /* 0x02 */ 1642 U8 Reserved2; /* 0x03 */ 1643 U16 NumberOfLayouts; /* 0x04 */ 1644 U16 RegionsPerLayout; /* 0x06 */ 1645 U16 MinimumSectorAlignment; /* 0x08 */ 1646 U16 Reserved3; /* 0x0A */ 1647 U32 Reserved4; /* 0x0C */ 1648 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */ 1649 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA, 1650 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t; 1651 1652 /* defines for the RegionType field */ 1653 #define MPI2_FLASH_REGION_UNUSED (0x00) 1654 #define MPI2_FLASH_REGION_FIRMWARE (0x01) 1655 #define MPI2_FLASH_REGION_BIOS (0x02) 1656 #define MPI2_FLASH_REGION_NVDATA (0x03) 1657 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05) 1658 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06) 1659 #define MPI2_FLASH_REGION_CONFIG_1 (0x07) 1660 #define MPI2_FLASH_REGION_CONFIG_2 (0x08) 1661 #define MPI2_FLASH_REGION_MEGARAID (0x09) 1662 #define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK (0x0A) 1663 #define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK) /* older name */ 1664 #define MPI2_FLASH_REGION_CBB_BACKUP (0x0D) 1665 1666 1667 /* ImageRevision */ 1668 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) 1669 1670 1671 1672 /* Supported Devices Extended Image Data */ 1673 1674 /* 1675 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1676 * one and check NumberOfDevices at runtime. 1677 */ 1678 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES 1679 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1) 1680 #endif 1681 1682 typedef struct _MPI2_SUPPORTED_DEVICE 1683 { 1684 U16 DeviceID; /* 0x00 */ 1685 U16 VendorID; /* 0x02 */ 1686 U16 DeviceIDMask; /* 0x04 */ 1687 U16 Reserved1; /* 0x06 */ 1688 U8 LowPCIRev; /* 0x08 */ 1689 U8 HighPCIRev; /* 0x09 */ 1690 U16 Reserved2; /* 0x0A */ 1691 U32 Reserved3; /* 0x0C */ 1692 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE, 1693 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t; 1694 1695 typedef struct _MPI2_SUPPORTED_DEVICES_DATA 1696 { 1697 U8 ImageRevision; /* 0x00 */ 1698 U8 Reserved1; /* 0x01 */ 1699 U8 NumberOfDevices; /* 0x02 */ 1700 U8 Reserved2; /* 0x03 */ 1701 U32 Reserved3; /* 0x04 */ 1702 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */ 1703 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA, 1704 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t; 1705 1706 /* ImageRevision */ 1707 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00) 1708 1709 1710 /* Init Extended Image Data */ 1711 1712 typedef struct _MPI2_INIT_IMAGE_FOOTER 1713 1714 { 1715 U32 BootFlags; /* 0x00 */ 1716 U32 ImageSize; /* 0x04 */ 1717 U32 Signature0; /* 0x08 */ 1718 U32 Signature1; /* 0x0C */ 1719 U32 Signature2; /* 0x10 */ 1720 U32 ResetVector; /* 0x14 */ 1721 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER, 1722 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t; 1723 1724 /* defines for the BootFlags field */ 1725 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00) 1726 1727 /* defines for the ImageSize field */ 1728 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04) 1729 1730 /* defines for the Signature0 field */ 1731 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08) 1732 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA) 1733 1734 /* defines for the Signature1 field */ 1735 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C) 1736 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5) 1737 1738 /* defines for the Signature2 field */ 1739 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10) 1740 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A) 1741 1742 /* Signature fields as individual bytes */ 1743 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA) 1744 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A) 1745 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5) 1746 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A) 1747 1748 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5) 1749 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA) 1750 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A) 1751 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5) 1752 1753 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A) 1754 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5) 1755 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA) 1756 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A) 1757 1758 /* defines for the ResetVector field */ 1759 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14) 1760 1761 1762 /* Encrypted Hash Extended Image Data */ 1763 1764 typedef struct _MPI25_ENCRYPTED_HASH_ENTRY 1765 { 1766 U8 HashImageType; /* 0x00 */ 1767 U8 HashAlgorithm; /* 0x01 */ 1768 U8 EncryptionAlgorithm; /* 0x02 */ 1769 U8 Reserved1; /* 0x03 */ 1770 U32 Reserved2; /* 0x04 */ 1771 U32 EncryptedHash[1]; /* 0x08 */ /* variable length */ 1772 } MPI25_ENCRYPTED_HASH_ENTRY, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_ENTRY, 1773 Mpi25EncryptedHashEntry_t, MPI2_POINTER pMpi25EncryptedHashEntry_t; 1774 1775 /* values for HashImageType */ 1776 #define MPI25_HASH_IMAGE_TYPE_UNUSED (0x00) 1777 #define MPI25_HASH_IMAGE_TYPE_FIRMWARE (0x01) 1778 #define MPI25_HASH_IMAGE_TYPE_BIOS (0x02) 1779 1780 /* values for HashAlgorithm */ 1781 #define MPI25_HASH_ALGORITHM_UNUSED (0x00) 1782 #define MPI25_HASH_ALGORITHM_SHA256 (0x01) 1783 1784 /* values for EncryptionAlgorithm */ 1785 #define MPI25_ENCRYPTION_ALG_UNUSED (0x00) 1786 #define MPI25_ENCRYPTION_ALG_RSA256 (0x01) 1787 1788 typedef struct _MPI25_ENCRYPTED_HASH_DATA 1789 { 1790 U8 ImageVersion; /* 0x00 */ 1791 U8 NumHash; /* 0x01 */ 1792 U16 Reserved1; /* 0x02 */ 1793 U32 Reserved2; /* 0x04 */ 1794 MPI25_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[1]; /* 0x08 */ /* variable number of entries */ 1795 } MPI25_ENCRYPTED_HASH_DATA, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_DATA, 1796 Mpi25EncryptedHashData_t, MPI2_POINTER pMpi25EncryptedHashData_t; 1797 1798 /**************************************************************************** 1799 * PowerManagementControl message 1800 ****************************************************************************/ 1801 1802 /* PowerManagementControl Request message */ 1803 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST 1804 { 1805 U8 Feature; /* 0x00 */ 1806 U8 Reserved1; /* 0x01 */ 1807 U8 ChainOffset; /* 0x02 */ 1808 U8 Function; /* 0x03 */ 1809 U16 Reserved2; /* 0x04 */ 1810 U8 Reserved3; /* 0x06 */ 1811 U8 MsgFlags; /* 0x07 */ 1812 U8 VP_ID; /* 0x08 */ 1813 U8 VF_ID; /* 0x09 */ 1814 U16 Reserved4; /* 0x0A */ 1815 U8 Parameter1; /* 0x0C */ 1816 U8 Parameter2; /* 0x0D */ 1817 U8 Parameter3; /* 0x0E */ 1818 U8 Parameter4; /* 0x0F */ 1819 U32 Reserved5; /* 0x10 */ 1820 U32 Reserved6; /* 0x14 */ 1821 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST, 1822 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t; 1823 1824 /* defines for the Feature field */ 1825 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01) 1826 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02) 1827 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /* obsolete */ 1828 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04) 1829 #define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05) /* reserved in MPI 2.0 */ 1830 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80) 1831 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF) 1832 1833 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */ 1834 /* Parameter1 contains a PHY number */ 1835 /* Parameter2 indicates power condition action using these defines */ 1836 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01) 1837 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02) 1838 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03) 1839 /* Parameter3 and Parameter4 are reserved */ 1840 1841 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */ 1842 /* Parameter1 contains SAS port width modulation group number */ 1843 /* Parameter2 indicates IOC action using these defines */ 1844 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01) 1845 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02) 1846 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03) 1847 /* Parameter3 indicates desired modulation level using these defines */ 1848 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00) 1849 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01) 1850 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02) 1851 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03) 1852 /* Parameter4 is reserved */ 1853 1854 /* this next set (_PCIE_LINK) is obsolete */ 1855 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */ 1856 /* Parameter1 indicates desired PCIe link speed using these defines */ 1857 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /* obsolete */ 1858 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /* obsolete */ 1859 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /* obsolete */ 1860 /* Parameter2 indicates desired PCIe link width using these defines */ 1861 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /* obsolete */ 1862 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /* obsolete */ 1863 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /* obsolete */ 1864 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /* obsolete */ 1865 /* Parameter3 and Parameter4 are reserved */ 1866 1867 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */ 1868 /* Parameter1 indicates desired IOC hardware clock speed using these defines */ 1869 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01) 1870 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02) 1871 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04) 1872 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08) 1873 /* Parameter2, Parameter3, and Parameter4 are reserved */ 1874 1875 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature */ 1876 /* Parameter1 indicates host action regarding global power management mode */ 1877 #define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01) 1878 #define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02) 1879 #define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03) 1880 /* Parameter2 indicates the requested global power management mode */ 1881 #define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01) 1882 #define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08) 1883 #define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40) 1884 /* Parameter3 and Parameter4 are reserved */ 1885 1886 1887 /* PowerManagementControl Reply message */ 1888 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY 1889 { 1890 U8 Feature; /* 0x00 */ 1891 U8 Reserved1; /* 0x01 */ 1892 U8 MsgLength; /* 0x02 */ 1893 U8 Function; /* 0x03 */ 1894 U16 Reserved2; /* 0x04 */ 1895 U8 Reserved3; /* 0x06 */ 1896 U8 MsgFlags; /* 0x07 */ 1897 U8 VP_ID; /* 0x08 */ 1898 U8 VF_ID; /* 0x09 */ 1899 U16 Reserved4; /* 0x0A */ 1900 U16 Reserved5; /* 0x0C */ 1901 U16 IOCStatus; /* 0x0E */ 1902 U32 IOCLogInfo; /* 0x10 */ 1903 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY, 1904 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t; 1905 1906 1907 /**************************************************************************** 1908 * IO Unit Control messages (MPI v2.6 and later only.) 1909 ****************************************************************************/ 1910 1911 /* IO Unit Control Request Message */ 1912 typedef struct _MPI26_IOUNIT_CONTROL_REQUEST 1913 { 1914 U8 Operation; /* 0x00 */ 1915 U8 Reserved1; /* 0x01 */ 1916 U8 ChainOffset; /* 0x02 */ 1917 U8 Function; /* 0x03 */ 1918 U16 DevHandle; /* 0x04 */ 1919 U8 IOCParameter; /* 0x06 */ 1920 U8 MsgFlags; /* 0x07 */ 1921 U8 VP_ID; /* 0x08 */ 1922 U8 VF_ID; /* 0x09 */ 1923 U16 Reserved3; /* 0x0A */ 1924 U16 Reserved4; /* 0x0C */ 1925 U8 PhyNum; /* 0x0E */ 1926 U8 PrimFlags; /* 0x0F */ 1927 U32 Primitive; /* 0x10 */ 1928 U8 LookupMethod; /* 0x14 */ 1929 U8 Reserved5; /* 0x15 */ 1930 U16 SlotNumber; /* 0x16 */ 1931 U64 LookupAddress; /* 0x18 */ 1932 U32 IOCParameterValue; /* 0x20 */ 1933 U32 Reserved7; /* 0x24 */ 1934 U32 Reserved8; /* 0x28 */ 1935 } MPI26_IOUNIT_CONTROL_REQUEST, 1936 MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REQUEST, 1937 Mpi26IoUnitControlRequest_t, MPI2_POINTER pMpi26IoUnitControlRequest_t; 1938 1939 /* values for the Operation field */ 1940 #define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02) 1941 #define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06) 1942 #define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07) 1943 #define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08) 1944 #define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09) 1945 #define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A) 1946 #define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B) 1947 #define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D) 1948 #define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E) 1949 #define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F) 1950 #define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10) 1951 #define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11) 1952 #define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12) 1953 #define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13) 1954 #define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14) 1955 #define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15) 1956 #define MPI26_CTRL_OP_SHUTDOWN (0x16) 1957 #define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17) 1958 #define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18) 1959 #define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19) 1960 #define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80) 1961 1962 /* values for the PrimFlags field */ 1963 #define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08) 1964 #define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02) 1965 #define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01) 1966 1967 /* values for the LookupMethod field */ 1968 #define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01) 1969 #define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02) 1970 #define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) 1971 1972 1973 /* IO Unit Control Reply Message */ 1974 typedef struct _MPI26_IOUNIT_CONTROL_REPLY 1975 { 1976 U8 Operation; /* 0x00 */ 1977 U8 Reserved1; /* 0x01 */ 1978 U8 MsgLength; /* 0x02 */ 1979 U8 Function; /* 0x03 */ 1980 U16 DevHandle; /* 0x04 */ 1981 U8 IOCParameter; /* 0x06 */ 1982 U8 MsgFlags; /* 0x07 */ 1983 U8 VP_ID; /* 0x08 */ 1984 U8 VF_ID; /* 0x09 */ 1985 U16 Reserved3; /* 0x0A */ 1986 U16 Reserved4; /* 0x0C */ 1987 U16 IOCStatus; /* 0x0E */ 1988 U32 IOCLogInfo; /* 0x10 */ 1989 } MPI26_IOUNIT_CONTROL_REPLY, MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REPLY, 1990 Mpi26IoUnitControlReply_t, MPI2_POINTER pMpi26IoUnitControlReply_t; 1991 1992 1993 #endif 1994 1995