1 /*- 2 * Copyright (c) 2013-2020, Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_IFC_H 29 #define MLX5_IFC_H 30 31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> 32 33 enum { 34 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0, 35 MLX5_EVENT_TYPE_COMP = 0x0, 36 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 37 MLX5_EVENT_TYPE_COMM_EST = 0x2, 38 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 39 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 40 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 41 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 42 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 43 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 44 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 45 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 46 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 47 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 48 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 49 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 50 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 51 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 52 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 53 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 54 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 55 MLX5_EVENT_TYPE_XRQ_ERROR = 0x18, 56 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 57 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 58 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 59 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 60 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 61 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 62 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 63 MLX5_EVENT_TYPE_CMD = 0xa, 64 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 65 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 66 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 67 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 68 MLX5_EVENT_TYPE_CODING_GENERAL_OBJ_EVENT = 0x27, 69 }; 70 71 enum { 72 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 73 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 74 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 75 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 76 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 77 }; 78 79 enum { 80 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 81 }; 82 83 enum { 84 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 85 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 86 }; 87 88 enum { 89 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 90 MLX5_OBJ_TYPE_MKEY = 0xff01, 91 MLX5_OBJ_TYPE_QP = 0xff02, 92 MLX5_OBJ_TYPE_PSV = 0xff03, 93 MLX5_OBJ_TYPE_RMP = 0xff04, 94 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 95 MLX5_OBJ_TYPE_RQ = 0xff06, 96 MLX5_OBJ_TYPE_SQ = 0xff07, 97 MLX5_OBJ_TYPE_TIR = 0xff08, 98 MLX5_OBJ_TYPE_TIS = 0xff09, 99 MLX5_OBJ_TYPE_DCT = 0xff0a, 100 MLX5_OBJ_TYPE_XRQ = 0xff0b, 101 MLX5_OBJ_TYPE_RQT = 0xff0e, 102 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 103 MLX5_OBJ_TYPE_CQ = 0xff10, 104 }; 105 106 enum { 107 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 108 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 109 MLX5_CMD_OP_INIT_HCA = 0x102, 110 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 111 MLX5_CMD_OP_ENABLE_HCA = 0x104, 112 MLX5_CMD_OP_DISABLE_HCA = 0x105, 113 MLX5_CMD_OP_QUERY_PAGES = 0x107, 114 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 115 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 116 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 117 MLX5_CMD_OP_SET_ISSI = 0x10b, 118 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 119 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 120 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 121 MLX5_CMD_OP_CREATE_MKEY = 0x200, 122 MLX5_CMD_OP_QUERY_MKEY = 0x201, 123 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 124 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 125 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 126 MLX5_CMD_OP_CREATE_EQ = 0x301, 127 MLX5_CMD_OP_DESTROY_EQ = 0x302, 128 MLX5_CMD_OP_QUERY_EQ = 0x303, 129 MLX5_CMD_OP_GEN_EQE = 0x304, 130 MLX5_CMD_OP_CREATE_CQ = 0x400, 131 MLX5_CMD_OP_DESTROY_CQ = 0x401, 132 MLX5_CMD_OP_QUERY_CQ = 0x402, 133 MLX5_CMD_OP_MODIFY_CQ = 0x403, 134 MLX5_CMD_OP_CREATE_QP = 0x500, 135 MLX5_CMD_OP_DESTROY_QP = 0x501, 136 MLX5_CMD_OP_RST2INIT_QP = 0x502, 137 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 138 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 139 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 140 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 141 MLX5_CMD_OP_2ERR_QP = 0x507, 142 MLX5_CMD_OP_2RST_QP = 0x50a, 143 MLX5_CMD_OP_QUERY_QP = 0x50b, 144 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 145 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 146 MLX5_CMD_OP_CREATE_PSV = 0x600, 147 MLX5_CMD_OP_DESTROY_PSV = 0x601, 148 MLX5_CMD_OP_CREATE_SRQ = 0x700, 149 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 150 MLX5_CMD_OP_QUERY_SRQ = 0x702, 151 MLX5_CMD_OP_ARM_RQ = 0x703, 152 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 153 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 154 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 155 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 156 MLX5_CMD_OP_CREATE_DCT = 0x710, 157 MLX5_CMD_OP_DESTROY_DCT = 0x711, 158 MLX5_CMD_OP_DRAIN_DCT = 0x712, 159 MLX5_CMD_OP_QUERY_DCT = 0x713, 160 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 161 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 162 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 163 MLX5_CMD_OP_CREATE_XRQ = 0x717, 164 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 165 MLX5_CMD_OP_QUERY_XRQ = 0x719, 166 MLX5_CMD_OP_ARM_XRQ = 0x71a, 167 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 168 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 169 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 170 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 171 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 172 173 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 174 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 175 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 176 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 177 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 178 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 179 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 180 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 181 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 182 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 183 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 184 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 185 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 186 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 187 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 188 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 189 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 190 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 191 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 192 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 193 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 194 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 195 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 196 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 197 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 198 MLX5_CMD_OP_ALLOC_PD = 0x800, 199 MLX5_CMD_OP_DEALLOC_PD = 0x801, 200 MLX5_CMD_OP_ALLOC_UAR = 0x802, 201 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 202 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 203 MLX5_CMD_OP_ACCESS_REG = 0x805, 204 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 205 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 206 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 207 MLX5_CMD_OP_MAD_IFC = 0x50d, 208 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 209 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 210 MLX5_CMD_OP_NOP = 0x80d, 211 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 212 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 213 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 214 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 215 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 216 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 217 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 218 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 219 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 220 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 221 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 222 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 223 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 224 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 225 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 226 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 227 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 228 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 229 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 230 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 231 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 232 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 233 MLX5_CMD_OP_CREATE_LAG = 0x840, 234 MLX5_CMD_OP_MODIFY_LAG = 0x841, 235 MLX5_CMD_OP_QUERY_LAG = 0x842, 236 MLX5_CMD_OP_DESTROY_LAG = 0x843, 237 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 238 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 239 MLX5_CMD_OP_CREATE_TIR = 0x900, 240 MLX5_CMD_OP_MODIFY_TIR = 0x901, 241 MLX5_CMD_OP_DESTROY_TIR = 0x902, 242 MLX5_CMD_OP_QUERY_TIR = 0x903, 243 MLX5_CMD_OP_CREATE_SQ = 0x904, 244 MLX5_CMD_OP_MODIFY_SQ = 0x905, 245 MLX5_CMD_OP_DESTROY_SQ = 0x906, 246 MLX5_CMD_OP_QUERY_SQ = 0x907, 247 MLX5_CMD_OP_CREATE_RQ = 0x908, 248 MLX5_CMD_OP_MODIFY_RQ = 0x909, 249 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 250 MLX5_CMD_OP_QUERY_RQ = 0x90b, 251 MLX5_CMD_OP_CREATE_RMP = 0x90c, 252 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 253 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 254 MLX5_CMD_OP_QUERY_RMP = 0x90f, 255 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 256 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 257 MLX5_CMD_OP_CREATE_TIS = 0x912, 258 MLX5_CMD_OP_MODIFY_TIS = 0x913, 259 MLX5_CMD_OP_DESTROY_TIS = 0x914, 260 MLX5_CMD_OP_QUERY_TIS = 0x915, 261 MLX5_CMD_OP_CREATE_RQT = 0x916, 262 MLX5_CMD_OP_MODIFY_RQT = 0x917, 263 MLX5_CMD_OP_DESTROY_RQT = 0x918, 264 MLX5_CMD_OP_QUERY_RQT = 0x919, 265 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 266 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 267 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 268 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 269 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 270 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 271 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 272 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 273 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 274 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 275 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 276 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 277 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 278 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 279 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 280 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 281 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 282 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 283 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 284 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 285 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 286 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 287 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 288 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 289 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 290 MLX5_CMD_OP_CREATE_GENERAL_OBJ = 0xa00, 291 MLX5_CMD_OP_MODIFY_GENERAL_OBJ = 0xa01, 292 MLX5_CMD_OP_QUERY_GENERAL_OBJ = 0xa02, 293 MLX5_CMD_OP_DESTROY_GENERAL_OBJ = 0xa03, 294 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 295 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 296 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 297 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 298 }; 299 300 /* Valid range for general commands that don't work over an object */ 301 enum { 302 MLX5_CMD_OP_GENERAL_START = 0xb00, 303 MLX5_CMD_OP_GENERAL_END = 0xd00, 304 }; 305 306 enum { 307 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 308 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 309 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 310 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 311 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 312 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 313 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 314 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 315 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 316 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 317 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 318 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 319 }; 320 321 enum { 322 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 323 }; 324 325 enum { 326 MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc, 327 }; 328 329 enum { 330 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 331 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 332 }; 333 334 enum { 335 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1, 336 }; 337 338 struct mlx5_ifc_flow_table_fields_supported_bits { 339 u8 outer_dmac[0x1]; 340 u8 outer_smac[0x1]; 341 u8 outer_ether_type[0x1]; 342 u8 reserved_0[0x1]; 343 u8 outer_first_prio[0x1]; 344 u8 outer_first_cfi[0x1]; 345 u8 outer_first_vid[0x1]; 346 u8 reserved_1[0x1]; 347 u8 outer_second_prio[0x1]; 348 u8 outer_second_cfi[0x1]; 349 u8 outer_second_vid[0x1]; 350 u8 outer_ipv6_flow_label[0x1]; 351 u8 outer_sip[0x1]; 352 u8 outer_dip[0x1]; 353 u8 outer_frag[0x1]; 354 u8 outer_ip_protocol[0x1]; 355 u8 outer_ip_ecn[0x1]; 356 u8 outer_ip_dscp[0x1]; 357 u8 outer_udp_sport[0x1]; 358 u8 outer_udp_dport[0x1]; 359 u8 outer_tcp_sport[0x1]; 360 u8 outer_tcp_dport[0x1]; 361 u8 outer_tcp_flags[0x1]; 362 u8 outer_gre_protocol[0x1]; 363 u8 outer_gre_key[0x1]; 364 u8 outer_vxlan_vni[0x1]; 365 u8 outer_geneve_vni[0x1]; 366 u8 outer_geneve_oam[0x1]; 367 u8 outer_geneve_protocol_type[0x1]; 368 u8 outer_geneve_opt_len[0x1]; 369 u8 reserved_2[0x1]; 370 u8 source_eswitch_port[0x1]; 371 372 u8 inner_dmac[0x1]; 373 u8 inner_smac[0x1]; 374 u8 inner_ether_type[0x1]; 375 u8 reserved_3[0x1]; 376 u8 inner_first_prio[0x1]; 377 u8 inner_first_cfi[0x1]; 378 u8 inner_first_vid[0x1]; 379 u8 reserved_4[0x1]; 380 u8 inner_second_prio[0x1]; 381 u8 inner_second_cfi[0x1]; 382 u8 inner_second_vid[0x1]; 383 u8 inner_ipv6_flow_label[0x1]; 384 u8 inner_sip[0x1]; 385 u8 inner_dip[0x1]; 386 u8 inner_frag[0x1]; 387 u8 inner_ip_protocol[0x1]; 388 u8 inner_ip_ecn[0x1]; 389 u8 inner_ip_dscp[0x1]; 390 u8 inner_udp_sport[0x1]; 391 u8 inner_udp_dport[0x1]; 392 u8 inner_tcp_sport[0x1]; 393 u8 inner_tcp_dport[0x1]; 394 u8 inner_tcp_flags[0x1]; 395 u8 reserved_5[0x9]; 396 397 u8 reserved_6[0x1a]; 398 u8 bth_dst_qp[0x1]; 399 u8 reserved_7[0x4]; 400 u8 source_sqn[0x1]; 401 402 u8 reserved_8[0x20]; 403 }; 404 405 struct mlx5_ifc_eth_discard_cntrs_grp_bits { 406 u8 ingress_general_high[0x20]; 407 408 u8 ingress_general_low[0x20]; 409 410 u8 ingress_policy_engine_high[0x20]; 411 412 u8 ingress_policy_engine_low[0x20]; 413 414 u8 ingress_vlan_membership_high[0x20]; 415 416 u8 ingress_vlan_membership_low[0x20]; 417 418 u8 ingress_tag_frame_type_high[0x20]; 419 420 u8 ingress_tag_frame_type_low[0x20]; 421 422 u8 egress_vlan_membership_high[0x20]; 423 424 u8 egress_vlan_membership_low[0x20]; 425 426 u8 loopback_filter_high[0x20]; 427 428 u8 loopback_filter_low[0x20]; 429 430 u8 egress_general_high[0x20]; 431 432 u8 egress_general_low[0x20]; 433 434 u8 reserved_at_1c0[0x40]; 435 436 u8 egress_hoq_high[0x20]; 437 438 u8 egress_hoq_low[0x20]; 439 440 u8 port_isolation_high[0x20]; 441 442 u8 port_isolation_low[0x20]; 443 444 u8 egress_policy_engine_high[0x20]; 445 446 u8 egress_policy_engine_low[0x20]; 447 448 u8 ingress_tx_link_down_high[0x20]; 449 450 u8 ingress_tx_link_down_low[0x20]; 451 452 u8 egress_stp_filter_high[0x20]; 453 454 u8 egress_stp_filter_low[0x20]; 455 456 u8 egress_hoq_stall_high[0x20]; 457 458 u8 egress_hoq_stall_low[0x20]; 459 460 u8 reserved_at_340[0x440]; 461 }; 462 struct mlx5_ifc_flow_table_prop_layout_bits { 463 u8 ft_support[0x1]; 464 u8 flow_tag[0x1]; 465 u8 flow_counter[0x1]; 466 u8 flow_modify_en[0x1]; 467 u8 modify_root[0x1]; 468 u8 identified_miss_table[0x1]; 469 u8 flow_table_modify[0x1]; 470 u8 encap[0x1]; 471 u8 decap[0x1]; 472 u8 reset_root_to_default[0x1]; 473 u8 reserved_at_a[0x16]; 474 475 u8 reserved_at_20[0x2]; 476 u8 log_max_ft_size[0x6]; 477 u8 reserved_at_28[0x10]; 478 u8 max_ft_level[0x8]; 479 480 u8 reserved_at_40[0x20]; 481 482 u8 reserved_at_60[0x18]; 483 u8 log_max_ft_num[0x8]; 484 485 u8 reserved_at_80[0x10]; 486 u8 log_max_flow_counter[0x8]; 487 u8 log_max_destination[0x8]; 488 489 u8 reserved_at_a0[0x18]; 490 u8 log_max_flow[0x8]; 491 492 u8 reserved_at_c0[0x40]; 493 494 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 495 496 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 497 }; 498 499 struct mlx5_ifc_odp_per_transport_service_cap_bits { 500 u8 send[0x1]; 501 u8 receive[0x1]; 502 u8 write[0x1]; 503 u8 read[0x1]; 504 u8 atomic[0x1]; 505 u8 srq_receive[0x1]; 506 u8 reserved_0[0x1a]; 507 }; 508 509 struct mlx5_ifc_flow_counter_list_bits { 510 u8 reserved_0[0x10]; 511 u8 flow_counter_id[0x10]; 512 513 u8 reserved_1[0x20]; 514 }; 515 516 enum { 517 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 518 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 519 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 520 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 521 }; 522 523 struct mlx5_ifc_dest_format_struct_bits { 524 u8 destination_type[0x8]; 525 u8 destination_id[0x18]; 526 527 u8 reserved_0[0x20]; 528 }; 529 530 struct mlx5_ifc_ipv4_layout_bits { 531 u8 reserved_at_0[0x60]; 532 533 u8 ipv4[0x20]; 534 }; 535 536 struct mlx5_ifc_ipv6_layout_bits { 537 u8 ipv6[16][0x8]; 538 }; 539 540 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 541 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 542 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 543 u8 reserved_at_0[0x80]; 544 }; 545 546 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 547 u8 smac_47_16[0x20]; 548 549 u8 smac_15_0[0x10]; 550 u8 ethertype[0x10]; 551 552 u8 dmac_47_16[0x20]; 553 554 u8 dmac_15_0[0x10]; 555 u8 first_prio[0x3]; 556 u8 first_cfi[0x1]; 557 u8 first_vid[0xc]; 558 559 u8 ip_protocol[0x8]; 560 u8 ip_dscp[0x6]; 561 u8 ip_ecn[0x2]; 562 u8 cvlan_tag[0x1]; 563 u8 svlan_tag[0x1]; 564 u8 frag[0x1]; 565 u8 reserved_1[0x4]; 566 u8 tcp_flags[0x9]; 567 568 u8 tcp_sport[0x10]; 569 u8 tcp_dport[0x10]; 570 571 u8 reserved_2[0x20]; 572 573 u8 udp_sport[0x10]; 574 u8 udp_dport[0x10]; 575 576 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 577 578 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 579 }; 580 581 struct mlx5_ifc_fte_match_set_misc_bits { 582 u8 reserved_0[0x8]; 583 u8 source_sqn[0x18]; 584 585 u8 reserved_1[0x10]; 586 u8 source_port[0x10]; 587 588 u8 outer_second_prio[0x3]; 589 u8 outer_second_cfi[0x1]; 590 u8 outer_second_vid[0xc]; 591 u8 inner_second_prio[0x3]; 592 u8 inner_second_cfi[0x1]; 593 u8 inner_second_vid[0xc]; 594 595 u8 outer_second_vlan_tag[0x1]; 596 u8 inner_second_vlan_tag[0x1]; 597 u8 reserved_2[0xe]; 598 u8 gre_protocol[0x10]; 599 600 u8 gre_key_h[0x18]; 601 u8 gre_key_l[0x8]; 602 603 u8 vxlan_vni[0x18]; 604 u8 reserved_3[0x8]; 605 606 u8 geneve_vni[0x18]; 607 u8 reserved4[0x7]; 608 u8 geneve_oam[0x1]; 609 610 u8 reserved_5[0xc]; 611 u8 outer_ipv6_flow_label[0x14]; 612 613 u8 reserved_6[0xc]; 614 u8 inner_ipv6_flow_label[0x14]; 615 616 u8 reserved_7[0xa]; 617 u8 geneve_opt_len[0x6]; 618 u8 geneve_protocol_type[0x10]; 619 620 u8 reserved_8[0x8]; 621 u8 bth_dst_qp[0x18]; 622 623 u8 reserved_9[0xa0]; 624 }; 625 626 struct mlx5_ifc_cmd_pas_bits { 627 u8 pa_h[0x20]; 628 629 u8 pa_l[0x14]; 630 u8 reserved_0[0xc]; 631 }; 632 633 struct mlx5_ifc_uint64_bits { 634 u8 hi[0x20]; 635 636 u8 lo[0x20]; 637 }; 638 639 struct mlx5_ifc_application_prio_entry_bits { 640 u8 reserved_0[0x8]; 641 u8 priority[0x3]; 642 u8 reserved_1[0x2]; 643 u8 sel[0x3]; 644 u8 protocol_id[0x10]; 645 }; 646 647 struct mlx5_ifc_nodnic_ring_doorbell_bits { 648 u8 reserved_0[0x8]; 649 u8 ring_pi[0x10]; 650 u8 reserved_1[0x8]; 651 }; 652 653 enum { 654 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 655 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 656 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 657 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 658 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 659 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 660 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 661 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 662 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 663 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 664 }; 665 666 struct mlx5_ifc_ads_bits { 667 u8 fl[0x1]; 668 u8 free_ar[0x1]; 669 u8 reserved_0[0xe]; 670 u8 pkey_index[0x10]; 671 672 u8 reserved_1[0x8]; 673 u8 grh[0x1]; 674 u8 mlid[0x7]; 675 u8 rlid[0x10]; 676 677 u8 ack_timeout[0x5]; 678 u8 reserved_2[0x3]; 679 u8 src_addr_index[0x8]; 680 u8 log_rtm[0x4]; 681 u8 stat_rate[0x4]; 682 u8 hop_limit[0x8]; 683 684 u8 reserved_3[0x4]; 685 u8 tclass[0x8]; 686 u8 flow_label[0x14]; 687 688 u8 rgid_rip[16][0x8]; 689 690 u8 reserved_4[0x4]; 691 u8 f_dscp[0x1]; 692 u8 f_ecn[0x1]; 693 u8 reserved_5[0x1]; 694 u8 f_eth_prio[0x1]; 695 u8 ecn[0x2]; 696 u8 dscp[0x6]; 697 u8 udp_sport[0x10]; 698 699 u8 dei_cfi[0x1]; 700 u8 eth_prio[0x3]; 701 u8 sl[0x4]; 702 u8 port[0x8]; 703 u8 rmac_47_32[0x10]; 704 705 u8 rmac_31_0[0x20]; 706 }; 707 708 struct mlx5_ifc_diagnostic_counter_cap_bits { 709 u8 sync[0x1]; 710 u8 reserved_0[0xf]; 711 u8 counter_id[0x10]; 712 }; 713 714 struct mlx5_ifc_debug_cap_bits { 715 u8 reserved_0[0x18]; 716 u8 log_max_samples[0x8]; 717 718 u8 single[0x1]; 719 u8 repetitive[0x1]; 720 u8 health_mon_rx_activity[0x1]; 721 u8 reserved_1[0x15]; 722 u8 log_min_sample_period[0x8]; 723 724 u8 reserved_2[0x1c0]; 725 726 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 727 }; 728 729 struct mlx5_ifc_qos_cap_bits { 730 u8 packet_pacing[0x1]; 731 u8 esw_scheduling[0x1]; 732 u8 esw_bw_share[0x1]; 733 u8 esw_rate_limit[0x1]; 734 u8 hll[0x1]; 735 u8 packet_pacing_burst_bound[0x1]; 736 u8 packet_pacing_typical_size[0x1]; 737 u8 reserved_at_7[0x19]; 738 739 u8 reserved_at_20[0x20]; 740 741 u8 packet_pacing_max_rate[0x20]; 742 743 u8 packet_pacing_min_rate[0x20]; 744 745 u8 reserved_at_80[0x10]; 746 u8 packet_pacing_rate_table_size[0x10]; 747 748 u8 esw_element_type[0x10]; 749 u8 esw_tsar_type[0x10]; 750 751 u8 reserved_at_c0[0x10]; 752 u8 max_qos_para_vport[0x10]; 753 754 u8 max_tsar_bw_share[0x20]; 755 756 u8 reserved_at_100[0x700]; 757 }; 758 759 struct mlx5_ifc_snapshot_cap_bits { 760 u8 reserved_0[0x1d]; 761 u8 suspend_qp_uc[0x1]; 762 u8 suspend_qp_ud[0x1]; 763 u8 suspend_qp_rc[0x1]; 764 765 u8 reserved_1[0x1c]; 766 u8 restore_pd[0x1]; 767 u8 restore_uar[0x1]; 768 u8 restore_mkey[0x1]; 769 u8 restore_qp[0x1]; 770 771 u8 reserved_2[0x1e]; 772 u8 named_mkey[0x1]; 773 u8 named_qp[0x1]; 774 775 u8 reserved_3[0x7a0]; 776 }; 777 778 struct mlx5_ifc_e_switch_cap_bits { 779 u8 vport_svlan_strip[0x1]; 780 u8 vport_cvlan_strip[0x1]; 781 u8 vport_svlan_insert[0x1]; 782 u8 vport_cvlan_insert_if_not_exist[0x1]; 783 u8 vport_cvlan_insert_overwrite[0x1]; 784 785 u8 reserved_0[0x19]; 786 787 u8 nic_vport_node_guid_modify[0x1]; 788 u8 nic_vport_port_guid_modify[0x1]; 789 790 u8 reserved_1[0x7e0]; 791 }; 792 793 struct mlx5_ifc_flow_table_eswitch_cap_bits { 794 u8 reserved_0[0x200]; 795 796 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 797 798 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 799 800 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 801 802 u8 reserved_1[0x7800]; 803 }; 804 805 struct mlx5_ifc_flow_table_nic_cap_bits { 806 u8 nic_rx_multi_path_tirs[0x1]; 807 u8 nic_rx_multi_path_tirs_fts[0x1]; 808 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 809 u8 reserved_at_3[0x1fd]; 810 811 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 812 813 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 814 815 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 816 817 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 818 819 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 820 821 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 822 823 u8 reserved_1[0x7200]; 824 }; 825 826 struct mlx5_ifc_pddr_module_info_bits { 827 u8 cable_technology[0x8]; 828 u8 cable_breakout[0x8]; 829 u8 ext_ethernet_compliance_code[0x8]; 830 u8 ethernet_compliance_code[0x8]; 831 832 u8 cable_type[0x4]; 833 u8 cable_vendor[0x4]; 834 u8 cable_length[0x8]; 835 u8 cable_identifier[0x8]; 836 u8 cable_power_class[0x8]; 837 838 u8 reserved_at_40[0x8]; 839 u8 cable_rx_amp[0x8]; 840 u8 cable_rx_emphasis[0x8]; 841 u8 cable_tx_equalization[0x8]; 842 843 u8 reserved_at_60[0x8]; 844 u8 cable_attenuation_12g[0x8]; 845 u8 cable_attenuation_7g[0x8]; 846 u8 cable_attenuation_5g[0x8]; 847 848 u8 reserved_at_80[0x8]; 849 u8 rx_cdr_cap[0x4]; 850 u8 tx_cdr_cap[0x4]; 851 u8 reserved_at_90[0x4]; 852 u8 rx_cdr_state[0x4]; 853 u8 reserved_at_98[0x4]; 854 u8 tx_cdr_state[0x4]; 855 856 u8 vendor_name[16][0x8]; 857 858 u8 vendor_pn[16][0x8]; 859 860 u8 vendor_rev[0x20]; 861 862 u8 fw_version[0x20]; 863 864 u8 vendor_sn[16][0x8]; 865 866 u8 temperature[0x10]; 867 u8 voltage[0x10]; 868 869 u8 rx_power_lane0[0x10]; 870 u8 rx_power_lane1[0x10]; 871 872 u8 rx_power_lane2[0x10]; 873 u8 rx_power_lane3[0x10]; 874 875 u8 reserved_at_2c0[0x40]; 876 877 u8 tx_power_lane0[0x10]; 878 u8 tx_power_lane1[0x10]; 879 880 u8 tx_power_lane2[0x10]; 881 u8 tx_power_lane3[0x10]; 882 883 u8 reserved_at_340[0x40]; 884 885 u8 tx_bias_lane0[0x10]; 886 u8 tx_bias_lane1[0x10]; 887 888 u8 tx_bias_lane2[0x10]; 889 u8 tx_bias_lane3[0x10]; 890 891 u8 reserved_at_3c0[0x40]; 892 893 u8 temperature_high_th[0x10]; 894 u8 temperature_low_th[0x10]; 895 896 u8 voltage_high_th[0x10]; 897 u8 voltage_low_th[0x10]; 898 899 u8 rx_power_high_th[0x10]; 900 u8 rx_power_low_th[0x10]; 901 902 u8 tx_power_high_th[0x10]; 903 u8 tx_power_low_th[0x10]; 904 905 u8 tx_bias_high_th[0x10]; 906 u8 tx_bias_low_th[0x10]; 907 908 u8 reserved_at_4a0[0x10]; 909 u8 wavelength[0x10]; 910 911 u8 reserved_at_4c0[0x300]; 912 }; 913 914 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 915 u8 csum_cap[0x1]; 916 u8 vlan_cap[0x1]; 917 u8 lro_cap[0x1]; 918 u8 lro_psh_flag[0x1]; 919 u8 lro_time_stamp[0x1]; 920 u8 lro_max_msg_sz_mode[0x2]; 921 u8 wqe_vlan_insert[0x1]; 922 u8 self_lb_en_modifiable[0x1]; 923 u8 self_lb_mc[0x1]; 924 u8 self_lb_uc[0x1]; 925 u8 max_lso_cap[0x5]; 926 u8 multi_pkt_send_wqe[0x2]; 927 u8 wqe_inline_mode[0x2]; 928 u8 rss_ind_tbl_cap[0x4]; 929 u8 scatter_fcs[0x1]; 930 u8 reserved_1[0x2]; 931 u8 tunnel_lso_const_out_ip_id[0x1]; 932 u8 tunnel_lro_gre[0x1]; 933 u8 tunnel_lro_vxlan[0x1]; 934 u8 tunnel_statless_gre[0x1]; 935 u8 tunnel_stateless_vxlan[0x1]; 936 937 u8 swp[0x1]; 938 u8 swp_csum[0x1]; 939 u8 swp_lso[0x1]; 940 u8 reserved_2[0x1b]; 941 u8 max_geneve_opt_len[0x1]; 942 u8 tunnel_stateless_geneve_rx[0x1]; 943 944 u8 reserved_3[0x10]; 945 u8 lro_min_mss_size[0x10]; 946 947 u8 reserved_4[0x120]; 948 949 u8 lro_timer_supported_periods[4][0x20]; 950 951 u8 reserved_5[0x600]; 952 }; 953 954 enum { 955 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 956 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 957 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 958 }; 959 960 enum { 961 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 962 MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 963 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 964 }; 965 966 struct mlx5_ifc_roce_cap_bits { 967 u8 roce_apm[0x1]; 968 u8 rts2rts_primary_eth_prio[0x1]; 969 u8 roce_rx_allow_untagged[0x1]; 970 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 971 u8 reserved_at_4[0x1a]; 972 u8 qp_ts_format[0x2]; 973 974 u8 reserved_1[0x60]; 975 976 u8 reserved_2[0xc]; 977 u8 l3_type[0x4]; 978 u8 reserved_3[0x8]; 979 u8 roce_version[0x8]; 980 981 u8 reserved_4[0x10]; 982 u8 r_roce_dest_udp_port[0x10]; 983 984 u8 r_roce_max_src_udp_port[0x10]; 985 u8 r_roce_min_src_udp_port[0x10]; 986 987 u8 reserved_5[0x10]; 988 u8 roce_address_table_size[0x10]; 989 990 u8 reserved_6[0x700]; 991 }; 992 993 struct mlx5_ifc_device_event_cap_bits { 994 u8 user_affiliated_events[4][0x40]; 995 996 u8 user_unaffiliated_events[4][0x40]; 997 }; 998 999 enum { 1000 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 1001 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1002 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1003 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1004 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1005 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1006 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1007 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1008 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1009 }; 1010 1011 enum { 1012 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1013 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1014 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1015 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1016 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1017 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1018 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1019 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1020 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1021 }; 1022 1023 struct mlx5_ifc_atomic_caps_bits { 1024 u8 reserved_0[0x40]; 1025 1026 u8 atomic_req_8B_endianess_mode[0x2]; 1027 u8 reserved_1[0x4]; 1028 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 1029 1030 u8 reserved_2[0x19]; 1031 1032 u8 reserved_3[0x20]; 1033 1034 u8 reserved_4[0x10]; 1035 u8 atomic_operations[0x10]; 1036 1037 u8 reserved_5[0x10]; 1038 u8 atomic_size_qp[0x10]; 1039 1040 u8 reserved_6[0x10]; 1041 u8 atomic_size_dc[0x10]; 1042 1043 u8 reserved_7[0x720]; 1044 }; 1045 1046 struct mlx5_ifc_odp_cap_bits { 1047 u8 reserved_0[0x40]; 1048 1049 u8 sig[0x1]; 1050 u8 reserved_1[0x1f]; 1051 1052 u8 reserved_2[0x20]; 1053 1054 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1055 1056 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1057 1058 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1059 1060 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1061 1062 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1063 1064 u8 reserved_3[0x6e0]; 1065 }; 1066 1067 enum { 1068 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1069 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1070 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1071 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1072 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1073 }; 1074 1075 enum { 1076 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1077 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1078 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1079 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1080 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1081 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1082 }; 1083 1084 enum { 1085 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1086 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1087 }; 1088 1089 enum { 1090 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1091 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1092 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1093 }; 1094 1095 enum { 1096 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1097 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1098 }; 1099 1100 enum { 1101 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1102 MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1103 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1104 }; 1105 1106 enum { 1107 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1108 MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1109 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1110 }; 1111 1112 struct mlx5_ifc_cmd_hca_cap_bits { 1113 u8 reserved_0[0x80]; 1114 1115 u8 log_max_srq_sz[0x8]; 1116 u8 log_max_qp_sz[0x8]; 1117 u8 event_cap[0x1]; 1118 u8 reserved_1[0xa]; 1119 u8 log_max_qp[0x5]; 1120 1121 u8 reserved_2[0xb]; 1122 u8 log_max_srq[0x5]; 1123 u8 reserved_3[0x10]; 1124 1125 u8 reserved_4[0x8]; 1126 u8 log_max_cq_sz[0x8]; 1127 u8 relaxed_ordering_write_umr[0x1]; 1128 u8 relaxed_ordering_read_umr[0x1]; 1129 u8 reserved_5[0x9]; 1130 u8 log_max_cq[0x5]; 1131 1132 u8 log_max_eq_sz[0x8]; 1133 u8 relaxed_ordering_write[0x1]; 1134 u8 relaxed_ordering_read[0x1]; 1135 u8 log_max_mkey[0x6]; 1136 u8 reserved_7[0xb]; 1137 u8 fast_teardown[0x1]; 1138 u8 log_max_eq[0x4]; 1139 1140 u8 max_indirection[0x8]; 1141 u8 reserved_8[0x1]; 1142 u8 log_max_mrw_sz[0x7]; 1143 u8 force_teardown[0x1]; 1144 u8 reserved_9[0x1]; 1145 u8 log_max_bsf_list_size[0x6]; 1146 u8 reserved_10[0x2]; 1147 u8 log_max_klm_list_size[0x6]; 1148 1149 u8 reserved_11[0xa]; 1150 u8 log_max_ra_req_dc[0x6]; 1151 u8 reserved_12[0xa]; 1152 u8 log_max_ra_res_dc[0x6]; 1153 1154 u8 reserved_13[0xa]; 1155 u8 log_max_ra_req_qp[0x6]; 1156 u8 reserved_14[0xa]; 1157 u8 log_max_ra_res_qp[0x6]; 1158 1159 u8 pad_cap[0x1]; 1160 u8 cc_query_allowed[0x1]; 1161 u8 cc_modify_allowed[0x1]; 1162 u8 start_pad[0x1]; 1163 u8 cache_line_128byte[0x1]; 1164 u8 reserved_at_165[0xa]; 1165 u8 qcam_reg[0x1]; 1166 u8 gid_table_size[0x10]; 1167 1168 u8 out_of_seq_cnt[0x1]; 1169 u8 vport_counters[0x1]; 1170 u8 retransmission_q_counters[0x1]; 1171 u8 debug[0x1]; 1172 u8 modify_rq_counters_set_id[0x1]; 1173 u8 rq_delay_drop[0x1]; 1174 u8 max_qp_cnt[0xa]; 1175 u8 pkey_table_size[0x10]; 1176 1177 u8 vport_group_manager[0x1]; 1178 u8 vhca_group_manager[0x1]; 1179 u8 ib_virt[0x1]; 1180 u8 eth_virt[0x1]; 1181 u8 reserved_17[0x1]; 1182 u8 ets[0x1]; 1183 u8 nic_flow_table[0x1]; 1184 u8 eswitch_flow_table[0x1]; 1185 u8 reserved_18[0x1]; 1186 u8 mcam_reg[0x1]; 1187 u8 pcam_reg[0x1]; 1188 u8 local_ca_ack_delay[0x5]; 1189 u8 port_module_event[0x1]; 1190 u8 reserved_19[0x5]; 1191 u8 port_type[0x2]; 1192 u8 num_ports[0x8]; 1193 1194 u8 snapshot[0x1]; 1195 u8 reserved_20[0x2]; 1196 u8 log_max_msg[0x5]; 1197 u8 reserved_21[0x4]; 1198 u8 max_tc[0x4]; 1199 u8 temp_warn_event[0x1]; 1200 u8 dcbx[0x1]; 1201 u8 general_notification_event[0x1]; 1202 u8 reserved_at_1d3[0x2]; 1203 u8 fpga[0x1]; 1204 u8 rol_s[0x1]; 1205 u8 rol_g[0x1]; 1206 u8 reserved_23[0x1]; 1207 u8 wol_s[0x1]; 1208 u8 wol_g[0x1]; 1209 u8 wol_a[0x1]; 1210 u8 wol_b[0x1]; 1211 u8 wol_m[0x1]; 1212 u8 wol_u[0x1]; 1213 u8 wol_p[0x1]; 1214 1215 u8 stat_rate_support[0x10]; 1216 u8 reserved_24[0xc]; 1217 u8 cqe_version[0x4]; 1218 1219 u8 compact_address_vector[0x1]; 1220 u8 striding_rq[0x1]; 1221 u8 reserved_25[0x1]; 1222 u8 ipoib_enhanced_offloads[0x1]; 1223 u8 ipoib_ipoib_offloads[0x1]; 1224 u8 reserved_26[0x8]; 1225 u8 dc_connect_qp[0x1]; 1226 u8 dc_cnak_trace[0x1]; 1227 u8 drain_sigerr[0x1]; 1228 u8 cmdif_checksum[0x2]; 1229 u8 sigerr_cqe[0x1]; 1230 u8 reserved_27[0x1]; 1231 u8 wq_signature[0x1]; 1232 u8 sctr_data_cqe[0x1]; 1233 u8 reserved_28[0x1]; 1234 u8 sho[0x1]; 1235 u8 tph[0x1]; 1236 u8 rf[0x1]; 1237 u8 dct[0x1]; 1238 u8 qos[0x1]; 1239 u8 eth_net_offloads[0x1]; 1240 u8 roce[0x1]; 1241 u8 atomic[0x1]; 1242 u8 reserved_30[0x1]; 1243 1244 u8 cq_oi[0x1]; 1245 u8 cq_resize[0x1]; 1246 u8 cq_moderation[0x1]; 1247 u8 cq_period_mode_modify[0x1]; 1248 u8 cq_invalidate[0x1]; 1249 u8 reserved_at_225[0x1]; 1250 u8 cq_eq_remap[0x1]; 1251 u8 pg[0x1]; 1252 u8 block_lb_mc[0x1]; 1253 u8 exponential_backoff[0x1]; 1254 u8 scqe_break_moderation[0x1]; 1255 u8 cq_period_start_from_cqe[0x1]; 1256 u8 cd[0x1]; 1257 u8 atm[0x1]; 1258 u8 apm[0x1]; 1259 u8 imaicl[0x1]; 1260 u8 reserved_32[0x6]; 1261 u8 qkv[0x1]; 1262 u8 pkv[0x1]; 1263 u8 set_deth_sqpn[0x1]; 1264 u8 reserved_33[0x3]; 1265 u8 xrc[0x1]; 1266 u8 ud[0x1]; 1267 u8 uc[0x1]; 1268 u8 rc[0x1]; 1269 1270 u8 uar_4k[0x1]; 1271 u8 reserved_at_241[0x9]; 1272 u8 uar_sz[0x6]; 1273 u8 reserved_35[0x8]; 1274 u8 log_pg_sz[0x8]; 1275 1276 u8 bf[0x1]; 1277 u8 driver_version[0x1]; 1278 u8 pad_tx_eth_packet[0x1]; 1279 u8 reserved_36[0x8]; 1280 u8 log_bf_reg_size[0x5]; 1281 u8 reserved_37[0x10]; 1282 1283 u8 num_of_diagnostic_counters[0x10]; 1284 u8 max_wqe_sz_sq[0x10]; 1285 1286 u8 reserved_38[0x10]; 1287 u8 max_wqe_sz_rq[0x10]; 1288 1289 u8 reserved_39[0x10]; 1290 u8 max_wqe_sz_sq_dc[0x10]; 1291 1292 u8 reserved_40[0x7]; 1293 u8 max_qp_mcg[0x19]; 1294 1295 u8 reserved_41[0x18]; 1296 u8 log_max_mcg[0x8]; 1297 1298 u8 reserved_42[0x3]; 1299 u8 log_max_transport_domain[0x5]; 1300 u8 reserved_43[0x3]; 1301 u8 log_max_pd[0x5]; 1302 u8 reserved_44[0xb]; 1303 u8 log_max_xrcd[0x5]; 1304 1305 u8 nic_receive_steering_discard[0x1]; 1306 u8 reserved_45[0x7]; 1307 u8 log_max_flow_counter_bulk[0x8]; 1308 u8 max_flow_counter[0x10]; 1309 1310 u8 reserved_46[0x3]; 1311 u8 log_max_rq[0x5]; 1312 u8 reserved_47[0x3]; 1313 u8 log_max_sq[0x5]; 1314 u8 reserved_48[0x3]; 1315 u8 log_max_tir[0x5]; 1316 u8 reserved_49[0x3]; 1317 u8 log_max_tis[0x5]; 1318 1319 u8 basic_cyclic_rcv_wqe[0x1]; 1320 u8 reserved_50[0x2]; 1321 u8 log_max_rmp[0x5]; 1322 u8 reserved_51[0x3]; 1323 u8 log_max_rqt[0x5]; 1324 u8 reserved_52[0x3]; 1325 u8 log_max_rqt_size[0x5]; 1326 u8 reserved_53[0x3]; 1327 u8 log_max_tis_per_sq[0x5]; 1328 1329 u8 reserved_54[0x3]; 1330 u8 log_max_stride_sz_rq[0x5]; 1331 u8 reserved_55[0x3]; 1332 u8 log_min_stride_sz_rq[0x5]; 1333 u8 reserved_56[0x3]; 1334 u8 log_max_stride_sz_sq[0x5]; 1335 u8 reserved_57[0x3]; 1336 u8 log_min_stride_sz_sq[0x5]; 1337 1338 u8 reserved_58[0x1b]; 1339 u8 log_max_wq_sz[0x5]; 1340 1341 u8 nic_vport_change_event[0x1]; 1342 u8 disable_local_lb[0x1]; 1343 u8 reserved_59[0x9]; 1344 u8 log_max_vlan_list[0x5]; 1345 u8 reserved_60[0x3]; 1346 u8 log_max_current_mc_list[0x5]; 1347 u8 reserved_61[0x3]; 1348 u8 log_max_current_uc_list[0x5]; 1349 1350 u8 general_obj_types[0x40]; 1351 1352 u8 sq_ts_format[0x2]; 1353 u8 rq_ts_format[0x2]; 1354 u8 reserved_at_444[0x4]; 1355 u8 create_qp_start_hint[0x18]; 1356 1357 u8 reserved_at_460[0x3]; 1358 u8 log_max_uctx[0x5]; 1359 u8 reserved_at_468[0x3]; 1360 u8 log_max_umem[0x5]; 1361 u8 max_num_eqs[0x10]; 1362 1363 u8 reserved_at_480[0x1]; 1364 u8 tls_tx[0x1]; 1365 u8 reserved_at_482[0x1]; 1366 u8 log_max_l2_table[0x5]; 1367 u8 reserved_64[0x8]; 1368 u8 log_uar_page_sz[0x10]; 1369 1370 u8 reserved_65[0x20]; 1371 1372 u8 device_frequency_mhz[0x20]; 1373 1374 u8 device_frequency_khz[0x20]; 1375 1376 u8 reserved_at_500[0x20]; 1377 u8 num_of_uars_per_page[0x20]; 1378 u8 reserved_at_540[0x40]; 1379 1380 u8 log_max_atomic_size_qp[0x8]; 1381 u8 reserved_67[0x10]; 1382 u8 log_max_atomic_size_dc[0x8]; 1383 1384 u8 reserved_at_5a0[0x13]; 1385 u8 log_max_dek[0x5]; 1386 u8 reserved_at_5b8[0x4]; 1387 u8 mini_cqe_resp_stride_index[0x1]; 1388 u8 cqe_128_always[0x1]; 1389 u8 cqe_compression_128b[0x1]; 1390 1391 u8 cqe_compression[0x1]; 1392 1393 u8 cqe_compression_timeout[0x10]; 1394 u8 cqe_compression_max_num[0x10]; 1395 1396 u8 reserved_5e0[0xc0]; 1397 1398 u8 uctx_cap[0x20]; 1399 1400 u8 reserved_6c0[0xc0]; 1401 1402 u8 vhca_tunnel_commands[0x40]; 1403 u8 reserved_at_7c0[0x40]; 1404 }; 1405 1406 enum mlx5_flow_destination_type { 1407 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1408 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1409 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1410 }; 1411 1412 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1413 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1414 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1415 u8 reserved_0[0x40]; 1416 }; 1417 1418 struct mlx5_ifc_fte_match_param_bits { 1419 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1420 1421 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1422 1423 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1424 1425 u8 reserved_0[0xa00]; 1426 }; 1427 1428 enum { 1429 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1430 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1431 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1432 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1433 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1434 }; 1435 1436 struct mlx5_ifc_rx_hash_field_select_bits { 1437 u8 l3_prot_type[0x1]; 1438 u8 l4_prot_type[0x1]; 1439 u8 selected_fields[0x1e]; 1440 }; 1441 1442 struct mlx5_ifc_tls_capabilities_bits { 1443 u8 tls_1_2_aes_gcm_128[0x1]; 1444 u8 tls_1_3_aes_gcm_128[0x1]; 1445 u8 tls_1_2_aes_gcm_256[0x1]; 1446 u8 tls_1_3_aes_gcm_256[0x1]; 1447 u8 reserved_at_4[0x1c]; 1448 1449 u8 reserved_at_20[0x7e0]; 1450 }; 1451 1452 enum { 1453 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1454 MLX5_WQ_TYPE_CYCLIC = 0x1, 1455 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1456 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1457 }; 1458 1459 enum rq_type { 1460 RQ_TYPE_NONE, 1461 RQ_TYPE_STRIDE, 1462 }; 1463 1464 enum { 1465 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1466 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1467 }; 1468 1469 struct mlx5_ifc_wq_bits { 1470 u8 wq_type[0x4]; 1471 u8 wq_signature[0x1]; 1472 u8 end_padding_mode[0x2]; 1473 u8 cd_slave[0x1]; 1474 u8 reserved_0[0x18]; 1475 1476 u8 hds_skip_first_sge[0x1]; 1477 u8 log2_hds_buf_size[0x3]; 1478 u8 reserved_1[0x7]; 1479 u8 page_offset[0x5]; 1480 u8 lwm[0x10]; 1481 1482 u8 reserved_2[0x8]; 1483 u8 pd[0x18]; 1484 1485 u8 reserved_3[0x8]; 1486 u8 uar_page[0x18]; 1487 1488 u8 dbr_addr[0x40]; 1489 1490 u8 hw_counter[0x20]; 1491 1492 u8 sw_counter[0x20]; 1493 1494 u8 reserved_4[0xc]; 1495 u8 log_wq_stride[0x4]; 1496 u8 reserved_5[0x3]; 1497 u8 log_wq_pg_sz[0x5]; 1498 u8 reserved_6[0x3]; 1499 u8 log_wq_sz[0x5]; 1500 1501 u8 dbr_umem_valid[0x1]; 1502 u8 wq_umem_valid[0x1]; 1503 u8 reserved_7[0x13]; 1504 u8 single_wqe_log_num_of_strides[0x3]; 1505 u8 two_byte_shift_en[0x1]; 1506 u8 reserved_8[0x4]; 1507 u8 single_stride_log_num_of_bytes[0x3]; 1508 1509 u8 reserved_9[0x4c0]; 1510 1511 struct mlx5_ifc_cmd_pas_bits pas[0]; 1512 }; 1513 1514 struct mlx5_ifc_rq_num_bits { 1515 u8 reserved_0[0x8]; 1516 u8 rq_num[0x18]; 1517 }; 1518 1519 struct mlx5_ifc_mac_address_layout_bits { 1520 u8 reserved_0[0x10]; 1521 u8 mac_addr_47_32[0x10]; 1522 1523 u8 mac_addr_31_0[0x20]; 1524 }; 1525 1526 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1527 u8 reserved_0[0xa0]; 1528 1529 u8 min_time_between_cnps[0x20]; 1530 1531 u8 reserved_1[0x12]; 1532 u8 cnp_dscp[0x6]; 1533 u8 reserved_2[0x4]; 1534 u8 cnp_prio_mode[0x1]; 1535 u8 cnp_802p_prio[0x3]; 1536 1537 u8 reserved_3[0x720]; 1538 }; 1539 1540 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1541 u8 reserved_0[0x60]; 1542 1543 u8 reserved_1[0x4]; 1544 u8 clamp_tgt_rate[0x1]; 1545 u8 reserved_2[0x3]; 1546 u8 clamp_tgt_rate_after_time_inc[0x1]; 1547 u8 reserved_3[0x17]; 1548 1549 u8 reserved_4[0x20]; 1550 1551 u8 rpg_time_reset[0x20]; 1552 1553 u8 rpg_byte_reset[0x20]; 1554 1555 u8 rpg_threshold[0x20]; 1556 1557 u8 rpg_max_rate[0x20]; 1558 1559 u8 rpg_ai_rate[0x20]; 1560 1561 u8 rpg_hai_rate[0x20]; 1562 1563 u8 rpg_gd[0x20]; 1564 1565 u8 rpg_min_dec_fac[0x20]; 1566 1567 u8 rpg_min_rate[0x20]; 1568 1569 u8 reserved_5[0xe0]; 1570 1571 u8 rate_to_set_on_first_cnp[0x20]; 1572 1573 u8 dce_tcp_g[0x20]; 1574 1575 u8 dce_tcp_rtt[0x20]; 1576 1577 u8 rate_reduce_monitor_period[0x20]; 1578 1579 u8 reserved_6[0x20]; 1580 1581 u8 initial_alpha_value[0x20]; 1582 1583 u8 reserved_7[0x4a0]; 1584 }; 1585 1586 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1587 u8 reserved_0[0x80]; 1588 1589 u8 rppp_max_rps[0x20]; 1590 1591 u8 rpg_time_reset[0x20]; 1592 1593 u8 rpg_byte_reset[0x20]; 1594 1595 u8 rpg_threshold[0x20]; 1596 1597 u8 rpg_max_rate[0x20]; 1598 1599 u8 rpg_ai_rate[0x20]; 1600 1601 u8 rpg_hai_rate[0x20]; 1602 1603 u8 rpg_gd[0x20]; 1604 1605 u8 rpg_min_dec_fac[0x20]; 1606 1607 u8 rpg_min_rate[0x20]; 1608 1609 u8 reserved_1[0x640]; 1610 }; 1611 1612 enum { 1613 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1614 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1615 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1616 }; 1617 1618 struct mlx5_ifc_resize_field_select_bits { 1619 u8 resize_field_select[0x20]; 1620 }; 1621 1622 enum { 1623 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1624 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1625 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1626 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1627 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1628 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1629 }; 1630 1631 struct mlx5_ifc_modify_field_select_bits { 1632 u8 modify_field_select[0x20]; 1633 }; 1634 1635 struct mlx5_ifc_field_select_r_roce_np_bits { 1636 u8 field_select_r_roce_np[0x20]; 1637 }; 1638 1639 enum { 1640 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1641 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1642 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1643 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1644 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1645 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1646 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1647 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1648 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1649 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1650 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1651 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1652 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1653 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1654 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1655 }; 1656 1657 struct mlx5_ifc_field_select_r_roce_rp_bits { 1658 u8 field_select_r_roce_rp[0x20]; 1659 }; 1660 1661 enum { 1662 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1663 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1664 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1665 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1666 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1667 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1668 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1669 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1670 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1671 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1672 }; 1673 1674 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1675 u8 field_select_8021qaurp[0x20]; 1676 }; 1677 1678 struct mlx5_ifc_pptb_reg_bits { 1679 u8 reserved_at_0[0x2]; 1680 u8 mm[0x2]; 1681 u8 reserved_at_4[0x4]; 1682 u8 local_port[0x8]; 1683 u8 reserved_at_10[0x6]; 1684 u8 cm[0x1]; 1685 u8 um[0x1]; 1686 u8 pm[0x8]; 1687 1688 u8 prio_x_buff[0x20]; 1689 1690 u8 pm_msb[0x8]; 1691 u8 reserved_at_48[0x10]; 1692 u8 ctrl_buff[0x4]; 1693 u8 untagged_buff[0x4]; 1694 }; 1695 1696 struct mlx5_ifc_dcbx_app_reg_bits { 1697 u8 reserved_0[0x8]; 1698 u8 port_number[0x8]; 1699 u8 reserved_1[0x10]; 1700 1701 u8 reserved_2[0x1a]; 1702 u8 num_app_prio[0x6]; 1703 1704 u8 reserved_3[0x40]; 1705 1706 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1707 }; 1708 1709 struct mlx5_ifc_dcbx_param_reg_bits { 1710 u8 dcbx_cee_cap[0x1]; 1711 u8 dcbx_ieee_cap[0x1]; 1712 u8 dcbx_standby_cap[0x1]; 1713 u8 reserved_0[0x5]; 1714 u8 port_number[0x8]; 1715 u8 reserved_1[0xa]; 1716 u8 max_application_table_size[0x6]; 1717 1718 u8 reserved_2[0x15]; 1719 u8 version_oper[0x3]; 1720 u8 reserved_3[0x5]; 1721 u8 version_admin[0x3]; 1722 1723 u8 willing_admin[0x1]; 1724 u8 reserved_4[0x3]; 1725 u8 pfc_cap_oper[0x4]; 1726 u8 reserved_5[0x4]; 1727 u8 pfc_cap_admin[0x4]; 1728 u8 reserved_6[0x4]; 1729 u8 num_of_tc_oper[0x4]; 1730 u8 reserved_7[0x4]; 1731 u8 num_of_tc_admin[0x4]; 1732 1733 u8 remote_willing[0x1]; 1734 u8 reserved_8[0x3]; 1735 u8 remote_pfc_cap[0x4]; 1736 u8 reserved_9[0x14]; 1737 u8 remote_num_of_tc[0x4]; 1738 1739 u8 reserved_10[0x18]; 1740 u8 error[0x8]; 1741 1742 u8 reserved_11[0x160]; 1743 }; 1744 1745 struct mlx5_ifc_qhll_bits { 1746 u8 reserved_at_0[0x8]; 1747 u8 local_port[0x8]; 1748 u8 reserved_at_10[0x10]; 1749 1750 u8 reserved_at_20[0x1b]; 1751 u8 hll_time[0x5]; 1752 1753 u8 stall_en[0x1]; 1754 u8 reserved_at_41[0x1c]; 1755 u8 stall_cnt[0x3]; 1756 }; 1757 1758 struct mlx5_ifc_qetcr_reg_bits { 1759 u8 operation_type[0x2]; 1760 u8 cap_local_admin[0x1]; 1761 u8 cap_remote_admin[0x1]; 1762 u8 reserved_0[0x4]; 1763 u8 port_number[0x8]; 1764 u8 reserved_1[0x10]; 1765 1766 u8 reserved_2[0x20]; 1767 1768 u8 tc[8][0x40]; 1769 1770 u8 global_configuration[0x40]; 1771 }; 1772 1773 struct mlx5_ifc_nodnic_ring_config_reg_bits { 1774 u8 queue_address_63_32[0x20]; 1775 1776 u8 queue_address_31_12[0x14]; 1777 u8 reserved_0[0x6]; 1778 u8 log_size[0x6]; 1779 1780 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1781 1782 u8 reserved_1[0x8]; 1783 u8 queue_number[0x18]; 1784 1785 u8 q_key[0x20]; 1786 1787 u8 reserved_2[0x10]; 1788 u8 pkey_index[0x10]; 1789 1790 u8 reserved_3[0x40]; 1791 }; 1792 1793 struct mlx5_ifc_nodnic_cq_arming_word_bits { 1794 u8 reserved_0[0x8]; 1795 u8 cq_ci[0x10]; 1796 u8 reserved_1[0x8]; 1797 }; 1798 1799 enum { 1800 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1801 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1802 }; 1803 1804 enum { 1805 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1806 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1807 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1808 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1809 }; 1810 1811 struct mlx5_ifc_nodnic_event_word_bits { 1812 u8 driver_reset_needed[0x1]; 1813 u8 port_management_change_event[0x1]; 1814 u8 reserved_0[0x19]; 1815 u8 link_type[0x1]; 1816 u8 port_state[0x4]; 1817 }; 1818 1819 struct mlx5_ifc_nic_vport_change_event_bits { 1820 u8 reserved_0[0x10]; 1821 u8 vport_num[0x10]; 1822 1823 u8 reserved_1[0xc0]; 1824 }; 1825 1826 struct mlx5_ifc_pages_req_event_bits { 1827 u8 reserved_0[0x10]; 1828 u8 function_id[0x10]; 1829 1830 u8 num_pages[0x20]; 1831 1832 u8 reserved_1[0xa0]; 1833 }; 1834 1835 struct mlx5_ifc_cmd_inter_comp_event_bits { 1836 u8 command_completion_vector[0x20]; 1837 1838 u8 reserved_0[0xc0]; 1839 }; 1840 1841 struct mlx5_ifc_stall_vl_event_bits { 1842 u8 reserved_0[0x18]; 1843 u8 port_num[0x1]; 1844 u8 reserved_1[0x3]; 1845 u8 vl[0x4]; 1846 1847 u8 reserved_2[0xa0]; 1848 }; 1849 1850 struct mlx5_ifc_db_bf_congestion_event_bits { 1851 u8 event_subtype[0x8]; 1852 u8 reserved_0[0x8]; 1853 u8 congestion_level[0x8]; 1854 u8 reserved_1[0x8]; 1855 1856 u8 reserved_2[0xa0]; 1857 }; 1858 1859 struct mlx5_ifc_gpio_event_bits { 1860 u8 reserved_0[0x60]; 1861 1862 u8 gpio_event_hi[0x20]; 1863 1864 u8 gpio_event_lo[0x20]; 1865 1866 u8 reserved_1[0x40]; 1867 }; 1868 1869 struct mlx5_ifc_port_state_change_event_bits { 1870 u8 reserved_0[0x40]; 1871 1872 u8 port_num[0x4]; 1873 u8 reserved_1[0x1c]; 1874 1875 u8 reserved_2[0x80]; 1876 }; 1877 1878 struct mlx5_ifc_dropped_packet_logged_bits { 1879 u8 reserved_0[0xe0]; 1880 }; 1881 1882 enum { 1883 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1884 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1885 }; 1886 1887 struct mlx5_ifc_cq_error_bits { 1888 u8 reserved_0[0x8]; 1889 u8 cqn[0x18]; 1890 1891 u8 reserved_1[0x20]; 1892 1893 u8 reserved_2[0x18]; 1894 u8 syndrome[0x8]; 1895 1896 u8 reserved_3[0x80]; 1897 }; 1898 1899 struct mlx5_ifc_rdma_page_fault_event_bits { 1900 u8 bytes_commited[0x20]; 1901 1902 u8 r_key[0x20]; 1903 1904 u8 reserved_0[0x10]; 1905 u8 packet_len[0x10]; 1906 1907 u8 rdma_op_len[0x20]; 1908 1909 u8 rdma_va[0x40]; 1910 1911 u8 reserved_1[0x5]; 1912 u8 rdma[0x1]; 1913 u8 write[0x1]; 1914 u8 requestor[0x1]; 1915 u8 qp_number[0x18]; 1916 }; 1917 1918 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1919 u8 bytes_committed[0x20]; 1920 1921 u8 reserved_0[0x10]; 1922 u8 wqe_index[0x10]; 1923 1924 u8 reserved_1[0x10]; 1925 u8 len[0x10]; 1926 1927 u8 reserved_2[0x60]; 1928 1929 u8 reserved_3[0x5]; 1930 u8 rdma[0x1]; 1931 u8 write_read[0x1]; 1932 u8 requestor[0x1]; 1933 u8 qpn[0x18]; 1934 }; 1935 1936 enum { 1937 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1938 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1939 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1940 }; 1941 1942 struct mlx5_ifc_qp_events_bits { 1943 u8 reserved_0[0xa0]; 1944 1945 u8 type[0x8]; 1946 u8 reserved_1[0x18]; 1947 1948 u8 reserved_2[0x8]; 1949 u8 qpn_rqn_sqn[0x18]; 1950 }; 1951 1952 struct mlx5_ifc_dct_events_bits { 1953 u8 reserved_0[0xc0]; 1954 1955 u8 reserved_1[0x8]; 1956 u8 dct_number[0x18]; 1957 }; 1958 1959 struct mlx5_ifc_comp_event_bits { 1960 u8 reserved_0[0xc0]; 1961 1962 u8 reserved_1[0x8]; 1963 u8 cq_number[0x18]; 1964 }; 1965 1966 struct mlx5_ifc_fw_version_bits { 1967 u8 major[0x10]; 1968 u8 reserved_0[0x10]; 1969 1970 u8 minor[0x10]; 1971 u8 subminor[0x10]; 1972 1973 u8 second[0x8]; 1974 u8 minute[0x8]; 1975 u8 hour[0x8]; 1976 u8 reserved_1[0x8]; 1977 1978 u8 year[0x10]; 1979 u8 month[0x8]; 1980 u8 day[0x8]; 1981 }; 1982 1983 enum { 1984 MLX5_QPC_STATE_RST = 0x0, 1985 MLX5_QPC_STATE_INIT = 0x1, 1986 MLX5_QPC_STATE_RTR = 0x2, 1987 MLX5_QPC_STATE_RTS = 0x3, 1988 MLX5_QPC_STATE_SQER = 0x4, 1989 MLX5_QPC_STATE_SQD = 0x5, 1990 MLX5_QPC_STATE_ERR = 0x6, 1991 MLX5_QPC_STATE_SUSPENDED = 0x9, 1992 }; 1993 1994 enum { 1995 MLX5_QPC_ST_RC = 0x0, 1996 MLX5_QPC_ST_UC = 0x1, 1997 MLX5_QPC_ST_UD = 0x2, 1998 MLX5_QPC_ST_XRC = 0x3, 1999 MLX5_QPC_ST_DCI = 0x5, 2000 MLX5_QPC_ST_QP0 = 0x7, 2001 MLX5_QPC_ST_QP1 = 0x8, 2002 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2003 MLX5_QPC_ST_REG_UMR = 0xc, 2004 }; 2005 2006 enum { 2007 MLX5_QP_PM_ARMED = 0x0, 2008 MLX5_QP_PM_REARM = 0x1, 2009 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2010 MLX5_QP_PM_MIGRATED = 0x3, 2011 }; 2012 2013 enum { 2014 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2015 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2016 }; 2017 2018 enum { 2019 MLX5_QPC_MTU_256_BYTES = 0x1, 2020 MLX5_QPC_MTU_512_BYTES = 0x2, 2021 MLX5_QPC_MTU_1K_BYTES = 0x3, 2022 MLX5_QPC_MTU_2K_BYTES = 0x4, 2023 MLX5_QPC_MTU_4K_BYTES = 0x5, 2024 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2025 }; 2026 2027 enum { 2028 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2029 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2030 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2031 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2032 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2033 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2034 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2035 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2036 }; 2037 2038 enum { 2039 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2040 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2041 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2042 }; 2043 2044 enum { 2045 MLX5_QPC_CS_RES_DISABLE = 0x0, 2046 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2047 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2048 }; 2049 2050 enum { 2051 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2052 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2053 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2054 }; 2055 2056 struct mlx5_ifc_qpc_bits { 2057 u8 state[0x4]; 2058 u8 lag_tx_port_affinity[0x4]; 2059 u8 st[0x8]; 2060 u8 reserved_1[0x3]; 2061 u8 pm_state[0x2]; 2062 u8 reserved_2[0x7]; 2063 u8 end_padding_mode[0x2]; 2064 u8 reserved_3[0x2]; 2065 2066 u8 wq_signature[0x1]; 2067 u8 block_lb_mc[0x1]; 2068 u8 atomic_like_write_en[0x1]; 2069 u8 latency_sensitive[0x1]; 2070 u8 reserved_4[0x1]; 2071 u8 drain_sigerr[0x1]; 2072 u8 reserved_5[0x2]; 2073 u8 pd[0x18]; 2074 2075 u8 mtu[0x3]; 2076 u8 log_msg_max[0x5]; 2077 u8 reserved_6[0x1]; 2078 u8 log_rq_size[0x4]; 2079 u8 log_rq_stride[0x3]; 2080 u8 no_sq[0x1]; 2081 u8 log_sq_size[0x4]; 2082 u8 reserved_at_55[0x3]; 2083 u8 ts_format[0x2]; 2084 u8 reserved_at_5a[0x1]; 2085 u8 rlky[0x1]; 2086 u8 ulp_stateless_offload_mode[0x4]; 2087 2088 u8 counter_set_id[0x8]; 2089 u8 uar_page[0x18]; 2090 2091 u8 reserved_8[0x8]; 2092 u8 user_index[0x18]; 2093 2094 u8 reserved_9[0x3]; 2095 u8 log_page_size[0x5]; 2096 u8 remote_qpn[0x18]; 2097 2098 struct mlx5_ifc_ads_bits primary_address_path; 2099 2100 struct mlx5_ifc_ads_bits secondary_address_path; 2101 2102 u8 log_ack_req_freq[0x4]; 2103 u8 reserved_10[0x4]; 2104 u8 log_sra_max[0x3]; 2105 u8 reserved_11[0x2]; 2106 u8 retry_count[0x3]; 2107 u8 rnr_retry[0x3]; 2108 u8 reserved_12[0x1]; 2109 u8 fre[0x1]; 2110 u8 cur_rnr_retry[0x3]; 2111 u8 cur_retry_count[0x3]; 2112 u8 reserved_13[0x5]; 2113 2114 u8 reserved_14[0x20]; 2115 2116 u8 reserved_15[0x8]; 2117 u8 next_send_psn[0x18]; 2118 2119 u8 reserved_16[0x8]; 2120 u8 cqn_snd[0x18]; 2121 2122 u8 reserved_at_400[0x8]; 2123 2124 u8 deth_sqpn[0x18]; 2125 u8 reserved_17[0x20]; 2126 2127 u8 reserved_18[0x8]; 2128 u8 last_acked_psn[0x18]; 2129 2130 u8 reserved_19[0x8]; 2131 u8 ssn[0x18]; 2132 2133 u8 reserved_20[0x8]; 2134 u8 log_rra_max[0x3]; 2135 u8 reserved_21[0x1]; 2136 u8 atomic_mode[0x4]; 2137 u8 rre[0x1]; 2138 u8 rwe[0x1]; 2139 u8 rae[0x1]; 2140 u8 reserved_22[0x1]; 2141 u8 page_offset[0x6]; 2142 u8 reserved_23[0x3]; 2143 u8 cd_slave_receive[0x1]; 2144 u8 cd_slave_send[0x1]; 2145 u8 cd_master[0x1]; 2146 2147 u8 reserved_24[0x3]; 2148 u8 min_rnr_nak[0x5]; 2149 u8 next_rcv_psn[0x18]; 2150 2151 u8 reserved_25[0x8]; 2152 u8 xrcd[0x18]; 2153 2154 u8 reserved_26[0x8]; 2155 u8 cqn_rcv[0x18]; 2156 2157 u8 dbr_addr[0x40]; 2158 2159 u8 q_key[0x20]; 2160 2161 u8 reserved_27[0x5]; 2162 u8 rq_type[0x3]; 2163 u8 srqn_rmpn[0x18]; 2164 2165 u8 reserved_28[0x8]; 2166 u8 rmsn[0x18]; 2167 2168 u8 hw_sq_wqebb_counter[0x10]; 2169 u8 sw_sq_wqebb_counter[0x10]; 2170 2171 u8 hw_rq_counter[0x20]; 2172 2173 u8 sw_rq_counter[0x20]; 2174 2175 u8 reserved_29[0x20]; 2176 2177 u8 reserved_30[0xf]; 2178 u8 cgs[0x1]; 2179 u8 cs_req[0x8]; 2180 u8 cs_res[0x8]; 2181 2182 u8 dc_access_key[0x40]; 2183 2184 u8 reserved_at_680[0x3]; 2185 u8 dbr_umem_valid[0x1]; 2186 2187 u8 reserved_at_684[0xbc]; 2188 }; 2189 2190 struct mlx5_ifc_roce_addr_layout_bits { 2191 u8 source_l3_address[16][0x8]; 2192 2193 u8 reserved_0[0x3]; 2194 u8 vlan_valid[0x1]; 2195 u8 vlan_id[0xc]; 2196 u8 source_mac_47_32[0x10]; 2197 2198 u8 source_mac_31_0[0x20]; 2199 2200 u8 reserved_1[0x14]; 2201 u8 roce_l3_type[0x4]; 2202 u8 roce_version[0x8]; 2203 2204 u8 reserved_2[0x20]; 2205 }; 2206 2207 struct mlx5_ifc_rdbc_bits { 2208 u8 reserved_0[0x1c]; 2209 u8 type[0x4]; 2210 2211 u8 reserved_1[0x20]; 2212 2213 u8 reserved_2[0x8]; 2214 u8 psn[0x18]; 2215 2216 u8 rkey[0x20]; 2217 2218 u8 address[0x40]; 2219 2220 u8 byte_count[0x20]; 2221 2222 u8 reserved_3[0x20]; 2223 2224 u8 atomic_resp[32][0x8]; 2225 }; 2226 2227 enum { 2228 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2229 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2230 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2231 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2232 }; 2233 2234 struct mlx5_ifc_flow_context_bits { 2235 u8 reserved_0[0x20]; 2236 2237 u8 group_id[0x20]; 2238 2239 u8 reserved_1[0x8]; 2240 u8 flow_tag[0x18]; 2241 2242 u8 reserved_2[0x10]; 2243 u8 action[0x10]; 2244 2245 u8 reserved_3[0x8]; 2246 u8 destination_list_size[0x18]; 2247 2248 u8 reserved_4[0x8]; 2249 u8 flow_counter_list_size[0x18]; 2250 2251 u8 reserved_5[0x140]; 2252 2253 struct mlx5_ifc_fte_match_param_bits match_value; 2254 2255 u8 reserved_6[0x600]; 2256 2257 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2258 }; 2259 2260 enum { 2261 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2262 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2263 }; 2264 2265 struct mlx5_ifc_xrc_srqc_bits { 2266 u8 state[0x4]; 2267 u8 log_xrc_srq_size[0x4]; 2268 u8 reserved_0[0x18]; 2269 2270 u8 wq_signature[0x1]; 2271 u8 cont_srq[0x1]; 2272 u8 reserved_1[0x1]; 2273 u8 rlky[0x1]; 2274 u8 basic_cyclic_rcv_wqe[0x1]; 2275 u8 log_rq_stride[0x3]; 2276 u8 xrcd[0x18]; 2277 2278 u8 page_offset[0x6]; 2279 u8 reserved_at_46[0x1]; 2280 u8 dbr_umem_valid[0x1]; 2281 u8 cqn[0x18]; 2282 2283 u8 reserved_3[0x20]; 2284 2285 u8 reserved_4[0x2]; 2286 u8 log_page_size[0x6]; 2287 u8 user_index[0x18]; 2288 2289 u8 reserved_5[0x20]; 2290 2291 u8 reserved_6[0x8]; 2292 u8 pd[0x18]; 2293 2294 u8 lwm[0x10]; 2295 u8 wqe_cnt[0x10]; 2296 2297 u8 reserved_7[0x40]; 2298 2299 u8 db_record_addr_h[0x20]; 2300 2301 u8 db_record_addr_l[0x1e]; 2302 u8 reserved_8[0x2]; 2303 2304 u8 reserved_9[0x80]; 2305 }; 2306 2307 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2308 u8 counter_error_queues[0x20]; 2309 2310 u8 total_error_queues[0x20]; 2311 2312 u8 send_queue_priority_update_flow[0x20]; 2313 2314 u8 reserved_at_60[0x20]; 2315 2316 u8 nic_receive_steering_discard[0x40]; 2317 2318 u8 receive_discard_vport_down[0x40]; 2319 2320 u8 transmit_discard_vport_down[0x40]; 2321 2322 u8 reserved_at_140[0xec0]; 2323 }; 2324 2325 struct mlx5_ifc_traffic_counter_bits { 2326 u8 packets[0x40]; 2327 2328 u8 octets[0x40]; 2329 }; 2330 2331 struct mlx5_ifc_tisc_bits { 2332 u8 strict_lag_tx_port_affinity[0x1]; 2333 u8 tls_en[0x1]; 2334 u8 reserved_at_2[0x2]; 2335 u8 lag_tx_port_affinity[0x04]; 2336 2337 u8 reserved_at_8[0x4]; 2338 u8 prio[0x4]; 2339 u8 reserved_1[0x10]; 2340 2341 u8 reserved_2[0x100]; 2342 2343 u8 reserved_3[0x8]; 2344 u8 transport_domain[0x18]; 2345 2346 u8 reserved_4[0x8]; 2347 u8 underlay_qpn[0x18]; 2348 2349 u8 reserved_5[0x8]; 2350 u8 pd[0x18]; 2351 2352 u8 reserved_6[0x380]; 2353 }; 2354 2355 enum { 2356 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2357 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2358 }; 2359 2360 enum { 2361 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2362 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2363 }; 2364 2365 enum { 2366 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2367 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2368 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2369 }; 2370 2371 enum { 2372 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2373 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2374 }; 2375 2376 struct mlx5_ifc_tirc_bits { 2377 u8 reserved_0[0x20]; 2378 2379 u8 disp_type[0x4]; 2380 u8 tls_en[0x1]; 2381 u8 reserved_at_25[0x1b]; 2382 2383 u8 reserved_2[0x40]; 2384 2385 u8 reserved_3[0x4]; 2386 u8 lro_timeout_period_usecs[0x10]; 2387 u8 lro_enable_mask[0x4]; 2388 u8 lro_max_msg_sz[0x8]; 2389 2390 u8 reserved_4[0x40]; 2391 2392 u8 reserved_5[0x8]; 2393 u8 inline_rqn[0x18]; 2394 2395 u8 rx_hash_symmetric[0x1]; 2396 u8 reserved_6[0x1]; 2397 u8 tunneled_offload_en[0x1]; 2398 u8 reserved_7[0x5]; 2399 u8 indirect_table[0x18]; 2400 2401 u8 rx_hash_fn[0x4]; 2402 u8 reserved_8[0x2]; 2403 u8 self_lb_en[0x2]; 2404 u8 transport_domain[0x18]; 2405 2406 u8 rx_hash_toeplitz_key[10][0x20]; 2407 2408 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2409 2410 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2411 2412 u8 reserved_9[0x4c0]; 2413 }; 2414 2415 enum { 2416 MLX5_SRQC_STATE_GOOD = 0x0, 2417 MLX5_SRQC_STATE_ERROR = 0x1, 2418 }; 2419 2420 struct mlx5_ifc_srqc_bits { 2421 u8 state[0x4]; 2422 u8 log_srq_size[0x4]; 2423 u8 reserved_0[0x18]; 2424 2425 u8 wq_signature[0x1]; 2426 u8 cont_srq[0x1]; 2427 u8 reserved_1[0x1]; 2428 u8 rlky[0x1]; 2429 u8 reserved_2[0x1]; 2430 u8 log_rq_stride[0x3]; 2431 u8 xrcd[0x18]; 2432 2433 u8 page_offset[0x6]; 2434 u8 reserved_3[0x2]; 2435 u8 cqn[0x18]; 2436 2437 u8 reserved_4[0x20]; 2438 2439 u8 reserved_5[0x2]; 2440 u8 log_page_size[0x6]; 2441 u8 reserved_6[0x18]; 2442 2443 u8 reserved_7[0x20]; 2444 2445 u8 reserved_8[0x8]; 2446 u8 pd[0x18]; 2447 2448 u8 lwm[0x10]; 2449 u8 wqe_cnt[0x10]; 2450 2451 u8 reserved_9[0x40]; 2452 2453 u8 dbr_addr[0x40]; 2454 2455 u8 reserved_10[0x80]; 2456 }; 2457 2458 enum { 2459 MLX5_SQC_STATE_RST = 0x0, 2460 MLX5_SQC_STATE_RDY = 0x1, 2461 MLX5_SQC_STATE_ERR = 0x3, 2462 }; 2463 2464 enum { 2465 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2466 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2467 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2468 }; 2469 2470 struct mlx5_ifc_sqc_bits { 2471 u8 rlkey[0x1]; 2472 u8 cd_master[0x1]; 2473 u8 fre[0x1]; 2474 u8 flush_in_error_en[0x1]; 2475 u8 allow_multi_pkt_send_wqe[0x1]; 2476 u8 min_wqe_inline_mode[0x3]; 2477 u8 state[0x4]; 2478 u8 reg_umr[0x1]; 2479 u8 allow_swp[0x1]; 2480 u8 reserved_at_e[0xc]; 2481 u8 ts_format[0x2]; 2482 u8 reserved_at_1c[0x4]; 2483 2484 u8 reserved_1[0x8]; 2485 u8 user_index[0x18]; 2486 2487 u8 reserved_2[0x8]; 2488 u8 cqn[0x18]; 2489 2490 u8 reserved_3[0x80]; 2491 2492 u8 qos_para_vport_number[0x10]; 2493 u8 packet_pacing_rate_limit_index[0x10]; 2494 2495 u8 tis_lst_sz[0x10]; 2496 u8 reserved_4[0x10]; 2497 2498 u8 reserved_5[0x40]; 2499 2500 u8 reserved_6[0x8]; 2501 u8 tis_num_0[0x18]; 2502 2503 struct mlx5_ifc_wq_bits wq; 2504 }; 2505 2506 enum { 2507 MLX5_TSAR_TYPE_DWRR = 0, 2508 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2509 MLX5_TSAR_TYPE_ETS = 2 2510 }; 2511 2512 struct mlx5_ifc_tsar_element_attributes_bits { 2513 u8 reserved_0[0x8]; 2514 u8 tsar_type[0x8]; 2515 u8 reserved_1[0x10]; 2516 }; 2517 2518 struct mlx5_ifc_vport_element_attributes_bits { 2519 u8 reserved_0[0x10]; 2520 u8 vport_number[0x10]; 2521 }; 2522 2523 struct mlx5_ifc_vport_tc_element_attributes_bits { 2524 u8 traffic_class[0x10]; 2525 u8 vport_number[0x10]; 2526 }; 2527 2528 struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2529 u8 reserved_0[0x0C]; 2530 u8 traffic_class[0x04]; 2531 u8 qos_para_vport_number[0x10]; 2532 }; 2533 2534 enum { 2535 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2536 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2537 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2538 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2539 }; 2540 2541 struct mlx5_ifc_scheduling_context_bits { 2542 u8 element_type[0x8]; 2543 u8 reserved_at_8[0x18]; 2544 2545 u8 element_attributes[0x20]; 2546 2547 u8 parent_element_id[0x20]; 2548 2549 u8 reserved_at_60[0x40]; 2550 2551 u8 bw_share[0x20]; 2552 2553 u8 max_average_bw[0x20]; 2554 2555 u8 reserved_at_e0[0x120]; 2556 }; 2557 2558 struct mlx5_ifc_rqtc_bits { 2559 u8 reserved_0[0xa0]; 2560 2561 u8 reserved_1[0x10]; 2562 u8 rqt_max_size[0x10]; 2563 2564 u8 reserved_2[0x10]; 2565 u8 rqt_actual_size[0x10]; 2566 2567 u8 reserved_3[0x6a0]; 2568 2569 struct mlx5_ifc_rq_num_bits rq_num[0]; 2570 }; 2571 2572 enum { 2573 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2574 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2575 }; 2576 2577 enum { 2578 MLX5_RQC_STATE_RST = 0x0, 2579 MLX5_RQC_STATE_RDY = 0x1, 2580 MLX5_RQC_STATE_ERR = 0x3, 2581 }; 2582 2583 enum { 2584 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2585 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2586 }; 2587 2588 enum { 2589 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2590 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2591 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2592 }; 2593 2594 struct mlx5_ifc_rqc_bits { 2595 u8 rlkey[0x1]; 2596 u8 delay_drop_en[0x1]; 2597 u8 scatter_fcs[0x1]; 2598 u8 vlan_strip_disable[0x1]; 2599 u8 mem_rq_type[0x4]; 2600 u8 state[0x4]; 2601 u8 reserved_1[0x1]; 2602 u8 flush_in_error_en[0x1]; 2603 u8 reserved_at_e[0xc]; 2604 u8 ts_format[0x2]; 2605 u8 reserved_at_1c[0x4]; 2606 2607 u8 reserved_3[0x8]; 2608 u8 user_index[0x18]; 2609 2610 u8 reserved_4[0x8]; 2611 u8 cqn[0x18]; 2612 2613 u8 counter_set_id[0x8]; 2614 u8 reserved_5[0x18]; 2615 2616 u8 reserved_6[0x8]; 2617 u8 rmpn[0x18]; 2618 2619 u8 reserved_7[0xe0]; 2620 2621 struct mlx5_ifc_wq_bits wq; 2622 }; 2623 2624 enum { 2625 MLX5_RMPC_STATE_RDY = 0x1, 2626 MLX5_RMPC_STATE_ERR = 0x3, 2627 }; 2628 2629 struct mlx5_ifc_rmpc_bits { 2630 u8 reserved_0[0x8]; 2631 u8 state[0x4]; 2632 u8 reserved_1[0x14]; 2633 2634 u8 basic_cyclic_rcv_wqe[0x1]; 2635 u8 reserved_2[0x1f]; 2636 2637 u8 reserved_3[0x140]; 2638 2639 struct mlx5_ifc_wq_bits wq; 2640 }; 2641 2642 enum { 2643 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2644 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2645 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2646 }; 2647 2648 struct mlx5_ifc_nic_vport_context_bits { 2649 u8 reserved_0[0x5]; 2650 u8 min_wqe_inline_mode[0x3]; 2651 u8 reserved_1[0x15]; 2652 u8 disable_mc_local_lb[0x1]; 2653 u8 disable_uc_local_lb[0x1]; 2654 u8 roce_en[0x1]; 2655 2656 u8 arm_change_event[0x1]; 2657 u8 reserved_2[0x1a]; 2658 u8 event_on_mtu[0x1]; 2659 u8 event_on_promisc_change[0x1]; 2660 u8 event_on_vlan_change[0x1]; 2661 u8 event_on_mc_address_change[0x1]; 2662 u8 event_on_uc_address_change[0x1]; 2663 2664 u8 reserved_3[0xe0]; 2665 2666 u8 reserved_4[0x10]; 2667 u8 mtu[0x10]; 2668 2669 u8 system_image_guid[0x40]; 2670 2671 u8 port_guid[0x40]; 2672 2673 u8 node_guid[0x40]; 2674 2675 u8 reserved_5[0x140]; 2676 2677 u8 qkey_violation_counter[0x10]; 2678 u8 reserved_6[0x10]; 2679 2680 u8 reserved_7[0x420]; 2681 2682 u8 promisc_uc[0x1]; 2683 u8 promisc_mc[0x1]; 2684 u8 promisc_all[0x1]; 2685 u8 reserved_8[0x2]; 2686 u8 allowed_list_type[0x3]; 2687 u8 reserved_9[0xc]; 2688 u8 allowed_list_size[0xc]; 2689 2690 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2691 2692 u8 reserved_10[0x20]; 2693 2694 u8 current_uc_mac_address[0][0x40]; 2695 }; 2696 2697 enum { 2698 MLX5_ACCESS_MODE_PA = 0x0, 2699 MLX5_ACCESS_MODE_MTT = 0x1, 2700 MLX5_ACCESS_MODE_KLM = 0x2, 2701 MLX5_ACCESS_MODE_KSM = 0x3, 2702 MLX5_ACCESS_MODE_SW_ICM = 0x4, 2703 MLX5_ACCESS_MODE_MEMIC = 0x5, 2704 }; 2705 2706 struct mlx5_ifc_mkc_bits { 2707 u8 reserved_at_0[0x1]; 2708 u8 free[0x1]; 2709 u8 reserved_at_2[0x1]; 2710 u8 access_mode_4_2[0x3]; 2711 u8 reserved_at_6[0x7]; 2712 u8 relaxed_ordering_write[0x1]; 2713 u8 reserved_at_e[0x1]; 2714 u8 small_fence_on_rdma_read_response[0x1]; 2715 u8 umr_en[0x1]; 2716 u8 a[0x1]; 2717 u8 rw[0x1]; 2718 u8 rr[0x1]; 2719 u8 lw[0x1]; 2720 u8 lr[0x1]; 2721 u8 access_mode[0x2]; 2722 u8 reserved_2[0x8]; 2723 2724 u8 qpn[0x18]; 2725 u8 mkey_7_0[0x8]; 2726 2727 u8 reserved_3[0x20]; 2728 2729 u8 length64[0x1]; 2730 u8 bsf_en[0x1]; 2731 u8 sync_umr[0x1]; 2732 u8 reserved_4[0x2]; 2733 u8 expected_sigerr_count[0x1]; 2734 u8 reserved_5[0x1]; 2735 u8 en_rinval[0x1]; 2736 u8 pd[0x18]; 2737 2738 u8 start_addr[0x40]; 2739 2740 u8 len[0x40]; 2741 2742 u8 bsf_octword_size[0x20]; 2743 2744 u8 reserved_6[0x80]; 2745 2746 u8 translations_octword_size[0x20]; 2747 2748 u8 reserved_at_1c0[0x19]; 2749 u8 relaxed_ordering_read[0x1]; 2750 u8 reserved_at_1d9[0x1]; 2751 u8 log_page_size[0x5]; 2752 2753 u8 reserved_8[0x20]; 2754 }; 2755 2756 struct mlx5_ifc_pkey_bits { 2757 u8 reserved_0[0x10]; 2758 u8 pkey[0x10]; 2759 }; 2760 2761 struct mlx5_ifc_array128_auto_bits { 2762 u8 array128_auto[16][0x8]; 2763 }; 2764 2765 enum { 2766 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2767 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2768 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2769 }; 2770 2771 enum { 2772 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2773 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2774 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2775 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2776 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2777 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2778 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2779 }; 2780 2781 enum { 2782 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2783 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2784 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2785 }; 2786 2787 enum { 2788 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2789 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2790 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2791 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2792 }; 2793 2794 enum { 2795 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2796 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2797 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2798 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2799 }; 2800 2801 struct mlx5_ifc_hca_vport_context_bits { 2802 u8 field_select[0x20]; 2803 2804 u8 reserved_0[0xe0]; 2805 2806 u8 sm_virt_aware[0x1]; 2807 u8 has_smi[0x1]; 2808 u8 has_raw[0x1]; 2809 u8 grh_required[0x1]; 2810 u8 reserved_1[0x1]; 2811 u8 min_wqe_inline_mode[0x3]; 2812 u8 reserved_2[0x8]; 2813 u8 port_physical_state[0x4]; 2814 u8 vport_state_policy[0x4]; 2815 u8 port_state[0x4]; 2816 u8 vport_state[0x4]; 2817 2818 u8 reserved_3[0x20]; 2819 2820 u8 system_image_guid[0x40]; 2821 2822 u8 port_guid[0x40]; 2823 2824 u8 node_guid[0x40]; 2825 2826 u8 cap_mask1[0x20]; 2827 2828 u8 cap_mask1_field_select[0x20]; 2829 2830 u8 cap_mask2[0x20]; 2831 2832 u8 cap_mask2_field_select[0x20]; 2833 2834 u8 reserved_4[0x80]; 2835 2836 u8 lid[0x10]; 2837 u8 reserved_5[0x4]; 2838 u8 init_type_reply[0x4]; 2839 u8 lmc[0x3]; 2840 u8 subnet_timeout[0x5]; 2841 2842 u8 sm_lid[0x10]; 2843 u8 sm_sl[0x4]; 2844 u8 reserved_6[0xc]; 2845 2846 u8 qkey_violation_counter[0x10]; 2847 u8 pkey_violation_counter[0x10]; 2848 2849 u8 reserved_7[0xca0]; 2850 }; 2851 2852 union mlx5_ifc_hca_cap_union_bits { 2853 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2854 struct mlx5_ifc_odp_cap_bits odp_cap; 2855 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2856 struct mlx5_ifc_roce_cap_bits roce_cap; 2857 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2858 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2859 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2860 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2861 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2862 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2863 struct mlx5_ifc_qos_cap_bits qos_cap; 2864 struct mlx5_ifc_tls_capabilities_bits tls_capabilities; 2865 u8 reserved_0[0x8000]; 2866 }; 2867 2868 enum { 2869 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 2870 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 2871 }; 2872 2873 struct mlx5_ifc_flow_table_context_bits { 2874 u8 encap_en[0x1]; 2875 u8 decap_en[0x1]; 2876 u8 reserved_at_2[0x2]; 2877 u8 table_miss_action[0x4]; 2878 u8 level[0x8]; 2879 u8 reserved_at_10[0x8]; 2880 u8 log_size[0x8]; 2881 2882 u8 reserved_at_20[0x8]; 2883 u8 table_miss_id[0x18]; 2884 2885 u8 reserved_at_40[0x8]; 2886 u8 lag_master_next_table_id[0x18]; 2887 2888 u8 reserved_at_60[0xe0]; 2889 }; 2890 2891 struct mlx5_ifc_esw_vport_context_bits { 2892 u8 reserved_0[0x3]; 2893 u8 vport_svlan_strip[0x1]; 2894 u8 vport_cvlan_strip[0x1]; 2895 u8 vport_svlan_insert[0x1]; 2896 u8 vport_cvlan_insert[0x2]; 2897 u8 reserved_1[0x18]; 2898 2899 u8 reserved_2[0x20]; 2900 2901 u8 svlan_cfi[0x1]; 2902 u8 svlan_pcp[0x3]; 2903 u8 svlan_id[0xc]; 2904 u8 cvlan_cfi[0x1]; 2905 u8 cvlan_pcp[0x3]; 2906 u8 cvlan_id[0xc]; 2907 2908 u8 reserved_3[0x7a0]; 2909 }; 2910 2911 enum { 2912 MLX5_EQC_STATUS_OK = 0x0, 2913 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2914 }; 2915 2916 enum { 2917 MLX5_EQ_STATE_ARMED = 0x9, 2918 MLX5_EQ_STATE_FIRED = 0xa, 2919 }; 2920 2921 struct mlx5_ifc_eqc_bits { 2922 u8 status[0x4]; 2923 u8 reserved_0[0x9]; 2924 u8 ec[0x1]; 2925 u8 oi[0x1]; 2926 u8 reserved_1[0x5]; 2927 u8 st[0x4]; 2928 u8 reserved_2[0x8]; 2929 2930 u8 reserved_3[0x20]; 2931 2932 u8 reserved_4[0x14]; 2933 u8 page_offset[0x6]; 2934 u8 reserved_5[0x6]; 2935 2936 u8 reserved_6[0x3]; 2937 u8 log_eq_size[0x5]; 2938 u8 uar_page[0x18]; 2939 2940 u8 reserved_7[0x20]; 2941 2942 u8 reserved_8[0x18]; 2943 u8 intr[0x8]; 2944 2945 u8 reserved_9[0x3]; 2946 u8 log_page_size[0x5]; 2947 u8 reserved_10[0x18]; 2948 2949 u8 reserved_11[0x60]; 2950 2951 u8 reserved_12[0x8]; 2952 u8 consumer_counter[0x18]; 2953 2954 u8 reserved_13[0x8]; 2955 u8 producer_counter[0x18]; 2956 2957 u8 reserved_14[0x80]; 2958 }; 2959 2960 enum { 2961 MLX5_DCTC_STATE_ACTIVE = 0x0, 2962 MLX5_DCTC_STATE_DRAINING = 0x1, 2963 MLX5_DCTC_STATE_DRAINED = 0x2, 2964 }; 2965 2966 enum { 2967 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2968 MLX5_DCTC_CS_RES_NA = 0x1, 2969 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2970 }; 2971 2972 enum { 2973 MLX5_DCTC_MTU_256_BYTES = 0x1, 2974 MLX5_DCTC_MTU_512_BYTES = 0x2, 2975 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2976 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2977 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2978 }; 2979 2980 struct mlx5_ifc_dctc_bits { 2981 u8 reserved_0[0x4]; 2982 u8 state[0x4]; 2983 u8 reserved_1[0x18]; 2984 2985 u8 reserved_2[0x8]; 2986 u8 user_index[0x18]; 2987 2988 u8 reserved_3[0x8]; 2989 u8 cqn[0x18]; 2990 2991 u8 counter_set_id[0x8]; 2992 u8 atomic_mode[0x4]; 2993 u8 rre[0x1]; 2994 u8 rwe[0x1]; 2995 u8 rae[0x1]; 2996 u8 atomic_like_write_en[0x1]; 2997 u8 latency_sensitive[0x1]; 2998 u8 rlky[0x1]; 2999 u8 reserved_4[0xe]; 3000 3001 u8 reserved_5[0x8]; 3002 u8 cs_res[0x8]; 3003 u8 reserved_6[0x3]; 3004 u8 min_rnr_nak[0x5]; 3005 u8 reserved_7[0x8]; 3006 3007 u8 reserved_8[0x8]; 3008 u8 srqn[0x18]; 3009 3010 u8 reserved_9[0x8]; 3011 u8 pd[0x18]; 3012 3013 u8 tclass[0x8]; 3014 u8 reserved_10[0x4]; 3015 u8 flow_label[0x14]; 3016 3017 u8 dc_access_key[0x40]; 3018 3019 u8 reserved_11[0x5]; 3020 u8 mtu[0x3]; 3021 u8 port[0x8]; 3022 u8 pkey_index[0x10]; 3023 3024 u8 reserved_12[0x8]; 3025 u8 my_addr_index[0x8]; 3026 u8 reserved_13[0x8]; 3027 u8 hop_limit[0x8]; 3028 3029 u8 dc_access_key_violation_count[0x20]; 3030 3031 u8 reserved_14[0x14]; 3032 u8 dei_cfi[0x1]; 3033 u8 eth_prio[0x3]; 3034 u8 ecn[0x2]; 3035 u8 dscp[0x6]; 3036 3037 u8 reserved_15[0x40]; 3038 }; 3039 3040 enum { 3041 MLX5_CQC_STATUS_OK = 0x0, 3042 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3043 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3044 }; 3045 3046 enum { 3047 CQE_SIZE_64 = 0x0, 3048 CQE_SIZE_128 = 0x1, 3049 }; 3050 3051 enum { 3052 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3053 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3054 }; 3055 3056 enum { 3057 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 3058 MLX5_CQ_STATE_ARMED = 0x9, 3059 MLX5_CQ_STATE_FIRED = 0xa, 3060 }; 3061 3062 struct mlx5_ifc_cqc_bits { 3063 u8 status[0x4]; 3064 u8 reserved_at_4[0x2]; 3065 u8 dbr_umem_valid[0x1]; 3066 u8 reserved_at_7[0x1]; 3067 u8 cqe_sz[0x3]; 3068 u8 cc[0x1]; 3069 u8 reserved_1[0x1]; 3070 u8 scqe_break_moderation_en[0x1]; 3071 u8 oi[0x1]; 3072 u8 cq_period_mode[0x2]; 3073 u8 cqe_compression_en[0x1]; 3074 u8 mini_cqe_res_format[0x2]; 3075 u8 st[0x4]; 3076 u8 reserved_2[0x8]; 3077 3078 u8 reserved_3[0x20]; 3079 3080 u8 reserved_4[0x14]; 3081 u8 page_offset[0x6]; 3082 u8 reserved_5[0x6]; 3083 3084 u8 reserved_6[0x3]; 3085 u8 log_cq_size[0x5]; 3086 u8 uar_page[0x18]; 3087 3088 u8 reserved_7[0x4]; 3089 u8 cq_period[0xc]; 3090 u8 cq_max_count[0x10]; 3091 3092 u8 reserved_8[0x18]; 3093 u8 c_eqn[0x8]; 3094 3095 u8 reserved_9[0x3]; 3096 u8 log_page_size[0x5]; 3097 u8 reserved_10[0x18]; 3098 3099 u8 reserved_11[0x20]; 3100 3101 u8 reserved_12[0x8]; 3102 u8 last_notified_index[0x18]; 3103 3104 u8 reserved_13[0x8]; 3105 u8 last_solicit_index[0x18]; 3106 3107 u8 reserved_14[0x8]; 3108 u8 consumer_counter[0x18]; 3109 3110 u8 reserved_15[0x8]; 3111 u8 producer_counter[0x18]; 3112 3113 u8 reserved_16[0x40]; 3114 3115 u8 dbr_addr[0x40]; 3116 }; 3117 3118 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3119 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3120 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3121 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3122 u8 reserved_0[0x800]; 3123 }; 3124 3125 struct mlx5_ifc_query_adapter_param_block_bits { 3126 u8 reserved_0[0xc0]; 3127 3128 u8 reserved_1[0x8]; 3129 u8 ieee_vendor_id[0x18]; 3130 3131 u8 reserved_2[0x10]; 3132 u8 vsd_vendor_id[0x10]; 3133 3134 u8 vsd[208][0x8]; 3135 3136 u8 vsd_contd_psid[16][0x8]; 3137 }; 3138 3139 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3140 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3141 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3142 u8 reserved_0[0x20]; 3143 }; 3144 3145 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3146 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3147 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3148 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3149 u8 reserved_0[0x20]; 3150 }; 3151 3152 struct mlx5_ifc_bufferx_reg_bits { 3153 u8 reserved_0[0x6]; 3154 u8 lossy[0x1]; 3155 u8 epsb[0x1]; 3156 u8 reserved_1[0xc]; 3157 u8 size[0xc]; 3158 3159 u8 xoff_threshold[0x10]; 3160 u8 xon_threshold[0x10]; 3161 }; 3162 3163 struct mlx5_ifc_config_item_bits { 3164 u8 valid[0x2]; 3165 u8 reserved_0[0x2]; 3166 u8 header_type[0x2]; 3167 u8 reserved_1[0x2]; 3168 u8 default_location[0x1]; 3169 u8 reserved_2[0x7]; 3170 u8 version[0x4]; 3171 u8 reserved_3[0x3]; 3172 u8 length[0x9]; 3173 3174 u8 type[0x20]; 3175 3176 u8 reserved_4[0x10]; 3177 u8 crc16[0x10]; 3178 }; 3179 3180 enum { 3181 MLX5_XRQC_STATE_GOOD = 0x0, 3182 MLX5_XRQC_STATE_ERROR = 0x1, 3183 }; 3184 3185 enum { 3186 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3187 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3188 }; 3189 3190 enum { 3191 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3192 }; 3193 3194 struct mlx5_ifc_tag_matching_topology_context_bits { 3195 u8 log_matching_list_sz[0x4]; 3196 u8 reserved_at_4[0xc]; 3197 u8 append_next_index[0x10]; 3198 3199 u8 sw_phase_cnt[0x10]; 3200 u8 hw_phase_cnt[0x10]; 3201 3202 u8 reserved_at_40[0x40]; 3203 }; 3204 3205 struct mlx5_ifc_xrqc_bits { 3206 u8 state[0x4]; 3207 u8 rlkey[0x1]; 3208 u8 reserved_at_5[0xf]; 3209 u8 topology[0x4]; 3210 u8 reserved_at_18[0x4]; 3211 u8 offload[0x4]; 3212 3213 u8 reserved_at_20[0x8]; 3214 u8 user_index[0x18]; 3215 3216 u8 reserved_at_40[0x8]; 3217 u8 cqn[0x18]; 3218 3219 u8 reserved_at_60[0xa0]; 3220 3221 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3222 3223 u8 reserved_at_180[0x280]; 3224 3225 struct mlx5_ifc_wq_bits wq; 3226 }; 3227 3228 struct mlx5_ifc_nodnic_port_config_reg_bits { 3229 struct mlx5_ifc_nodnic_event_word_bits event; 3230 3231 u8 network_en[0x1]; 3232 u8 dma_en[0x1]; 3233 u8 promisc_en[0x1]; 3234 u8 promisc_multicast_en[0x1]; 3235 u8 reserved_0[0x17]; 3236 u8 receive_filter_en[0x5]; 3237 3238 u8 reserved_1[0x10]; 3239 u8 mac_47_32[0x10]; 3240 3241 u8 mac_31_0[0x20]; 3242 3243 u8 receive_filters_mgid_mac[64][0x8]; 3244 3245 u8 gid[16][0x8]; 3246 3247 u8 reserved_2[0x10]; 3248 u8 lid[0x10]; 3249 3250 u8 reserved_3[0xc]; 3251 u8 sm_sl[0x4]; 3252 u8 sm_lid[0x10]; 3253 3254 u8 completion_address_63_32[0x20]; 3255 3256 u8 completion_address_31_12[0x14]; 3257 u8 reserved_4[0x6]; 3258 u8 log_cq_size[0x6]; 3259 3260 u8 working_buffer_address_63_32[0x20]; 3261 3262 u8 working_buffer_address_31_12[0x14]; 3263 u8 reserved_5[0xc]; 3264 3265 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 3266 3267 u8 pkey_index[0x10]; 3268 u8 pkey[0x10]; 3269 3270 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 3271 3272 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 3273 3274 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 3275 3276 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 3277 3278 u8 reserved_6[0x400]; 3279 }; 3280 3281 union mlx5_ifc_event_auto_bits { 3282 struct mlx5_ifc_comp_event_bits comp_event; 3283 struct mlx5_ifc_dct_events_bits dct_events; 3284 struct mlx5_ifc_qp_events_bits qp_events; 3285 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3286 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3287 struct mlx5_ifc_cq_error_bits cq_error; 3288 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3289 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3290 struct mlx5_ifc_gpio_event_bits gpio_event; 3291 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3292 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3293 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3294 struct mlx5_ifc_pages_req_event_bits pages_req_event; 3295 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 3296 u8 reserved_0[0xe0]; 3297 }; 3298 3299 struct mlx5_ifc_health_buffer_bits { 3300 u8 reserved_0[0x100]; 3301 3302 u8 assert_existptr[0x20]; 3303 3304 u8 assert_callra[0x20]; 3305 3306 u8 reserved_1[0x40]; 3307 3308 u8 fw_version[0x20]; 3309 3310 u8 hw_id[0x20]; 3311 3312 u8 reserved_2[0x20]; 3313 3314 u8 irisc_index[0x8]; 3315 u8 synd[0x8]; 3316 u8 ext_synd[0x10]; 3317 }; 3318 3319 struct mlx5_ifc_register_loopback_control_bits { 3320 u8 no_lb[0x1]; 3321 u8 reserved_0[0x7]; 3322 u8 port[0x8]; 3323 u8 reserved_1[0x10]; 3324 3325 u8 reserved_2[0x60]; 3326 }; 3327 3328 struct mlx5_ifc_lrh_bits { 3329 u8 vl[4]; 3330 u8 lver[4]; 3331 u8 sl[4]; 3332 u8 reserved2[2]; 3333 u8 lnh[2]; 3334 u8 dlid[16]; 3335 u8 reserved5[5]; 3336 u8 pkt_len[11]; 3337 u8 slid[16]; 3338 }; 3339 3340 struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3341 u8 reserved_0[0x40]; 3342 3343 u8 reserved_1[0x10]; 3344 u8 rol_mode[0x8]; 3345 u8 wol_mode[0x8]; 3346 }; 3347 3348 struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3349 u8 reserved_0[0x40]; 3350 3351 u8 rol_mode_valid[0x1]; 3352 u8 wol_mode_valid[0x1]; 3353 u8 reserved_1[0xe]; 3354 u8 rol_mode[0x8]; 3355 u8 wol_mode[0x8]; 3356 3357 u8 reserved_2[0x7a0]; 3358 }; 3359 3360 struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3361 u8 virtual_mac_en[0x1]; 3362 u8 mac_aux_v[0x1]; 3363 u8 reserved_0[0x1e]; 3364 3365 u8 reserved_1[0x40]; 3366 3367 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3368 3369 u8 reserved_2[0x760]; 3370 }; 3371 3372 struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3373 u8 virtual_mac_en[0x1]; 3374 u8 mac_aux_v[0x1]; 3375 u8 reserved_0[0x1e]; 3376 3377 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3378 3379 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3380 3381 u8 reserved_1[0x760]; 3382 }; 3383 3384 struct mlx5_ifc_icmd_query_fw_info_out_bits { 3385 struct mlx5_ifc_fw_version_bits fw_version; 3386 3387 u8 reserved_0[0x10]; 3388 u8 hash_signature[0x10]; 3389 3390 u8 psid[16][0x8]; 3391 3392 u8 reserved_1[0x6e0]; 3393 }; 3394 3395 struct mlx5_ifc_icmd_query_cap_in_bits { 3396 u8 reserved_0[0x10]; 3397 u8 capability_group[0x10]; 3398 }; 3399 3400 struct mlx5_ifc_icmd_query_cap_general_bits { 3401 u8 nv_access[0x1]; 3402 u8 fw_info_psid[0x1]; 3403 u8 reserved_0[0x1e]; 3404 3405 u8 reserved_1[0x16]; 3406 u8 rol_s[0x1]; 3407 u8 rol_g[0x1]; 3408 u8 reserved_2[0x1]; 3409 u8 wol_s[0x1]; 3410 u8 wol_g[0x1]; 3411 u8 wol_a[0x1]; 3412 u8 wol_b[0x1]; 3413 u8 wol_m[0x1]; 3414 u8 wol_u[0x1]; 3415 u8 wol_p[0x1]; 3416 }; 3417 3418 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3419 u8 status[0x8]; 3420 u8 reserved_0[0x18]; 3421 3422 u8 reserved_1[0x7e0]; 3423 }; 3424 3425 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3426 u8 status[0x8]; 3427 u8 reserved_0[0x18]; 3428 3429 u8 reserved_1[0x7e0]; 3430 }; 3431 3432 struct mlx5_ifc_icmd_ocbb_init_in_bits { 3433 u8 address_hi[0x20]; 3434 3435 u8 address_lo[0x20]; 3436 3437 u8 reserved_0[0x7c0]; 3438 }; 3439 3440 struct mlx5_ifc_icmd_init_ocsd_in_bits { 3441 u8 reserved_0[0x20]; 3442 3443 u8 address_hi[0x20]; 3444 3445 u8 address_lo[0x20]; 3446 3447 u8 reserved_1[0x7a0]; 3448 }; 3449 3450 struct mlx5_ifc_icmd_access_reg_out_bits { 3451 u8 reserved_0[0x11]; 3452 u8 status[0x7]; 3453 u8 reserved_1[0x8]; 3454 3455 u8 register_id[0x10]; 3456 u8 reserved_2[0x10]; 3457 3458 u8 reserved_3[0x40]; 3459 3460 u8 reserved_4[0x5]; 3461 u8 len[0xb]; 3462 u8 reserved_5[0x10]; 3463 3464 u8 register_data[0][0x20]; 3465 }; 3466 3467 enum { 3468 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3469 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3470 }; 3471 3472 struct mlx5_ifc_icmd_access_reg_in_bits { 3473 u8 constant_1[0x5]; 3474 u8 constant_2[0xb]; 3475 u8 reserved_0[0x10]; 3476 3477 u8 register_id[0x10]; 3478 u8 reserved_1[0x1]; 3479 u8 method[0x7]; 3480 u8 constant_3[0x8]; 3481 3482 u8 reserved_2[0x40]; 3483 3484 u8 constant_4[0x5]; 3485 u8 len[0xb]; 3486 u8 reserved_3[0x10]; 3487 3488 u8 register_data[0][0x20]; 3489 }; 3490 3491 enum { 3492 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3493 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3494 }; 3495 3496 struct mlx5_ifc_teardown_hca_out_bits { 3497 u8 status[0x8]; 3498 u8 reserved_0[0x18]; 3499 3500 u8 syndrome[0x20]; 3501 3502 u8 reserved_1[0x3f]; 3503 3504 u8 state[0x1]; 3505 }; 3506 3507 enum { 3508 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3509 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3510 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3511 }; 3512 3513 struct mlx5_ifc_teardown_hca_in_bits { 3514 u8 opcode[0x10]; 3515 u8 reserved_0[0x10]; 3516 3517 u8 reserved_1[0x10]; 3518 u8 op_mod[0x10]; 3519 3520 u8 reserved_2[0x10]; 3521 u8 profile[0x10]; 3522 3523 u8 reserved_3[0x20]; 3524 }; 3525 3526 struct mlx5_ifc_set_delay_drop_params_out_bits { 3527 u8 status[0x8]; 3528 u8 reserved_at_8[0x18]; 3529 3530 u8 syndrome[0x20]; 3531 3532 u8 reserved_at_40[0x40]; 3533 }; 3534 3535 struct mlx5_ifc_set_delay_drop_params_in_bits { 3536 u8 opcode[0x10]; 3537 u8 reserved_at_10[0x10]; 3538 3539 u8 reserved_at_20[0x10]; 3540 u8 op_mod[0x10]; 3541 3542 u8 reserved_at_40[0x20]; 3543 3544 u8 reserved_at_60[0x10]; 3545 u8 delay_drop_timeout[0x10]; 3546 }; 3547 3548 struct mlx5_ifc_query_delay_drop_params_out_bits { 3549 u8 status[0x8]; 3550 u8 reserved_at_8[0x18]; 3551 3552 u8 syndrome[0x20]; 3553 3554 u8 reserved_at_40[0x20]; 3555 3556 u8 reserved_at_60[0x10]; 3557 u8 delay_drop_timeout[0x10]; 3558 }; 3559 3560 struct mlx5_ifc_query_delay_drop_params_in_bits { 3561 u8 opcode[0x10]; 3562 u8 reserved_at_10[0x10]; 3563 3564 u8 reserved_at_20[0x10]; 3565 u8 op_mod[0x10]; 3566 3567 u8 reserved_at_40[0x40]; 3568 }; 3569 3570 struct mlx5_ifc_suspend_qp_out_bits { 3571 u8 status[0x8]; 3572 u8 reserved_0[0x18]; 3573 3574 u8 syndrome[0x20]; 3575 3576 u8 reserved_1[0x40]; 3577 }; 3578 3579 struct mlx5_ifc_suspend_qp_in_bits { 3580 u8 opcode[0x10]; 3581 u8 reserved_0[0x10]; 3582 3583 u8 reserved_1[0x10]; 3584 u8 op_mod[0x10]; 3585 3586 u8 reserved_2[0x8]; 3587 u8 qpn[0x18]; 3588 3589 u8 reserved_3[0x20]; 3590 }; 3591 3592 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3593 u8 status[0x8]; 3594 u8 reserved_0[0x18]; 3595 3596 u8 syndrome[0x20]; 3597 3598 u8 reserved_1[0x40]; 3599 }; 3600 3601 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3602 u8 opcode[0x10]; 3603 u8 uid[0x10]; 3604 3605 u8 reserved_1[0x10]; 3606 u8 op_mod[0x10]; 3607 3608 u8 reserved_2[0x8]; 3609 u8 qpn[0x18]; 3610 3611 u8 reserved_3[0x20]; 3612 3613 u8 opt_param_mask[0x20]; 3614 3615 u8 reserved_4[0x20]; 3616 3617 struct mlx5_ifc_qpc_bits qpc; 3618 3619 u8 reserved_5[0x80]; 3620 }; 3621 3622 struct mlx5_ifc_sqd2rts_qp_out_bits { 3623 u8 status[0x8]; 3624 u8 reserved_0[0x18]; 3625 3626 u8 syndrome[0x20]; 3627 3628 u8 reserved_1[0x40]; 3629 }; 3630 3631 struct mlx5_ifc_sqd2rts_qp_in_bits { 3632 u8 opcode[0x10]; 3633 u8 uid[0x10]; 3634 3635 u8 reserved_1[0x10]; 3636 u8 op_mod[0x10]; 3637 3638 u8 reserved_2[0x8]; 3639 u8 qpn[0x18]; 3640 3641 u8 reserved_3[0x20]; 3642 3643 u8 opt_param_mask[0x20]; 3644 3645 u8 reserved_4[0x20]; 3646 3647 struct mlx5_ifc_qpc_bits qpc; 3648 3649 u8 reserved_5[0x80]; 3650 }; 3651 3652 struct mlx5_ifc_set_wol_rol_out_bits { 3653 u8 status[0x8]; 3654 u8 reserved_0[0x18]; 3655 3656 u8 syndrome[0x20]; 3657 3658 u8 reserved_1[0x40]; 3659 }; 3660 3661 struct mlx5_ifc_set_wol_rol_in_bits { 3662 u8 opcode[0x10]; 3663 u8 reserved_0[0x10]; 3664 3665 u8 reserved_1[0x10]; 3666 u8 op_mod[0x10]; 3667 3668 u8 rol_mode_valid[0x1]; 3669 u8 wol_mode_valid[0x1]; 3670 u8 reserved_2[0xe]; 3671 u8 rol_mode[0x8]; 3672 u8 wol_mode[0x8]; 3673 3674 u8 reserved_3[0x20]; 3675 }; 3676 3677 struct mlx5_ifc_set_roce_address_out_bits { 3678 u8 status[0x8]; 3679 u8 reserved_0[0x18]; 3680 3681 u8 syndrome[0x20]; 3682 3683 u8 reserved_1[0x40]; 3684 }; 3685 3686 struct mlx5_ifc_set_roce_address_in_bits { 3687 u8 opcode[0x10]; 3688 u8 reserved_0[0x10]; 3689 3690 u8 reserved_1[0x10]; 3691 u8 op_mod[0x10]; 3692 3693 u8 roce_address_index[0x10]; 3694 u8 reserved_2[0x10]; 3695 3696 u8 reserved_3[0x20]; 3697 3698 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3699 }; 3700 3701 struct mlx5_ifc_set_rdb_out_bits { 3702 u8 status[0x8]; 3703 u8 reserved_0[0x18]; 3704 3705 u8 syndrome[0x20]; 3706 3707 u8 reserved_1[0x40]; 3708 }; 3709 3710 struct mlx5_ifc_set_rdb_in_bits { 3711 u8 opcode[0x10]; 3712 u8 reserved_0[0x10]; 3713 3714 u8 reserved_1[0x10]; 3715 u8 op_mod[0x10]; 3716 3717 u8 reserved_2[0x8]; 3718 u8 qpn[0x18]; 3719 3720 u8 reserved_3[0x18]; 3721 u8 rdb_list_size[0x8]; 3722 3723 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3724 }; 3725 3726 struct mlx5_ifc_set_mad_demux_out_bits { 3727 u8 status[0x8]; 3728 u8 reserved_0[0x18]; 3729 3730 u8 syndrome[0x20]; 3731 3732 u8 reserved_1[0x40]; 3733 }; 3734 3735 enum { 3736 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3737 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3738 }; 3739 3740 struct mlx5_ifc_set_mad_demux_in_bits { 3741 u8 opcode[0x10]; 3742 u8 reserved_0[0x10]; 3743 3744 u8 reserved_1[0x10]; 3745 u8 op_mod[0x10]; 3746 3747 u8 reserved_2[0x20]; 3748 3749 u8 reserved_3[0x6]; 3750 u8 demux_mode[0x2]; 3751 u8 reserved_4[0x18]; 3752 }; 3753 3754 struct mlx5_ifc_set_l2_table_entry_out_bits { 3755 u8 status[0x8]; 3756 u8 reserved_0[0x18]; 3757 3758 u8 syndrome[0x20]; 3759 3760 u8 reserved_1[0x40]; 3761 }; 3762 3763 struct mlx5_ifc_set_l2_table_entry_in_bits { 3764 u8 opcode[0x10]; 3765 u8 reserved_0[0x10]; 3766 3767 u8 reserved_1[0x10]; 3768 u8 op_mod[0x10]; 3769 3770 u8 reserved_2[0x60]; 3771 3772 u8 reserved_3[0x8]; 3773 u8 table_index[0x18]; 3774 3775 u8 reserved_4[0x20]; 3776 3777 u8 reserved_5[0x13]; 3778 u8 vlan_valid[0x1]; 3779 u8 vlan[0xc]; 3780 3781 struct mlx5_ifc_mac_address_layout_bits mac_address; 3782 3783 u8 reserved_6[0xc0]; 3784 }; 3785 3786 struct mlx5_ifc_set_issi_out_bits { 3787 u8 status[0x8]; 3788 u8 reserved_0[0x18]; 3789 3790 u8 syndrome[0x20]; 3791 3792 u8 reserved_1[0x40]; 3793 }; 3794 3795 struct mlx5_ifc_set_issi_in_bits { 3796 u8 opcode[0x10]; 3797 u8 reserved_0[0x10]; 3798 3799 u8 reserved_1[0x10]; 3800 u8 op_mod[0x10]; 3801 3802 u8 reserved_2[0x10]; 3803 u8 current_issi[0x10]; 3804 3805 u8 reserved_3[0x20]; 3806 }; 3807 3808 struct mlx5_ifc_set_hca_cap_out_bits { 3809 u8 status[0x8]; 3810 u8 reserved_0[0x18]; 3811 3812 u8 syndrome[0x20]; 3813 3814 u8 reserved_1[0x40]; 3815 }; 3816 3817 struct mlx5_ifc_set_hca_cap_in_bits { 3818 u8 opcode[0x10]; 3819 u8 reserved_0[0x10]; 3820 3821 u8 reserved_1[0x10]; 3822 u8 op_mod[0x10]; 3823 3824 u8 reserved_2[0x40]; 3825 3826 union mlx5_ifc_hca_cap_union_bits capability; 3827 }; 3828 3829 enum { 3830 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3831 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3832 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3833 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3834 }; 3835 3836 struct mlx5_ifc_set_flow_table_root_out_bits { 3837 u8 status[0x8]; 3838 u8 reserved_0[0x18]; 3839 3840 u8 syndrome[0x20]; 3841 3842 u8 reserved_1[0x40]; 3843 }; 3844 3845 struct mlx5_ifc_set_flow_table_root_in_bits { 3846 u8 opcode[0x10]; 3847 u8 reserved_0[0x10]; 3848 3849 u8 reserved_1[0x10]; 3850 u8 op_mod[0x10]; 3851 3852 u8 other_vport[0x1]; 3853 u8 reserved_2[0xf]; 3854 u8 vport_number[0x10]; 3855 3856 u8 reserved_3[0x20]; 3857 3858 u8 table_type[0x8]; 3859 u8 reserved_4[0x18]; 3860 3861 u8 reserved_5[0x8]; 3862 u8 table_id[0x18]; 3863 3864 u8 reserved_6[0x8]; 3865 u8 underlay_qpn[0x18]; 3866 3867 u8 reserved_7[0x120]; 3868 }; 3869 3870 struct mlx5_ifc_set_fte_out_bits { 3871 u8 status[0x8]; 3872 u8 reserved_0[0x18]; 3873 3874 u8 syndrome[0x20]; 3875 3876 u8 reserved_1[0x40]; 3877 }; 3878 3879 struct mlx5_ifc_set_fte_in_bits { 3880 u8 opcode[0x10]; 3881 u8 reserved_0[0x10]; 3882 3883 u8 reserved_1[0x10]; 3884 u8 op_mod[0x10]; 3885 3886 u8 other_vport[0x1]; 3887 u8 reserved_2[0xf]; 3888 u8 vport_number[0x10]; 3889 3890 u8 reserved_3[0x20]; 3891 3892 u8 table_type[0x8]; 3893 u8 reserved_4[0x18]; 3894 3895 u8 reserved_5[0x8]; 3896 u8 table_id[0x18]; 3897 3898 u8 reserved_6[0x18]; 3899 u8 modify_enable_mask[0x8]; 3900 3901 u8 reserved_7[0x20]; 3902 3903 u8 flow_index[0x20]; 3904 3905 u8 reserved_8[0xe0]; 3906 3907 struct mlx5_ifc_flow_context_bits flow_context; 3908 }; 3909 3910 struct mlx5_ifc_set_driver_version_out_bits { 3911 u8 status[0x8]; 3912 u8 reserved_0[0x18]; 3913 3914 u8 syndrome[0x20]; 3915 3916 u8 reserved_1[0x40]; 3917 }; 3918 3919 struct mlx5_ifc_set_driver_version_in_bits { 3920 u8 opcode[0x10]; 3921 u8 reserved_0[0x10]; 3922 3923 u8 reserved_1[0x10]; 3924 u8 op_mod[0x10]; 3925 3926 u8 reserved_2[0x40]; 3927 3928 u8 driver_version[64][0x8]; 3929 }; 3930 3931 struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3932 u8 status[0x8]; 3933 u8 reserved_0[0x18]; 3934 3935 u8 syndrome[0x20]; 3936 3937 u8 reserved_1[0x40]; 3938 }; 3939 3940 struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3941 u8 opcode[0x10]; 3942 u8 reserved_0[0x10]; 3943 3944 u8 reserved_1[0x10]; 3945 u8 op_mod[0x10]; 3946 3947 u8 enable[0x1]; 3948 u8 reserved_2[0x1f]; 3949 3950 u8 reserved_3[0x160]; 3951 3952 struct mlx5_ifc_cmd_pas_bits pas; 3953 }; 3954 3955 struct mlx5_ifc_set_burst_size_out_bits { 3956 u8 status[0x8]; 3957 u8 reserved_0[0x18]; 3958 3959 u8 syndrome[0x20]; 3960 3961 u8 reserved_1[0x40]; 3962 }; 3963 3964 struct mlx5_ifc_set_burst_size_in_bits { 3965 u8 opcode[0x10]; 3966 u8 reserved_0[0x10]; 3967 3968 u8 reserved_1[0x10]; 3969 u8 op_mod[0x10]; 3970 3971 u8 reserved_2[0x20]; 3972 3973 u8 reserved_3[0x9]; 3974 u8 device_burst_size[0x17]; 3975 }; 3976 3977 struct mlx5_ifc_rts2rts_qp_out_bits { 3978 u8 status[0x8]; 3979 u8 reserved_0[0x18]; 3980 3981 u8 syndrome[0x20]; 3982 3983 u8 reserved_1[0x40]; 3984 }; 3985 3986 struct mlx5_ifc_rts2rts_qp_in_bits { 3987 u8 opcode[0x10]; 3988 u8 uid[0x10]; 3989 3990 u8 reserved_1[0x10]; 3991 u8 op_mod[0x10]; 3992 3993 u8 reserved_2[0x8]; 3994 u8 qpn[0x18]; 3995 3996 u8 reserved_3[0x20]; 3997 3998 u8 opt_param_mask[0x20]; 3999 4000 u8 reserved_4[0x20]; 4001 4002 struct mlx5_ifc_qpc_bits qpc; 4003 4004 u8 reserved_5[0x80]; 4005 }; 4006 4007 struct mlx5_ifc_rtr2rts_qp_out_bits { 4008 u8 status[0x8]; 4009 u8 reserved_0[0x18]; 4010 4011 u8 syndrome[0x20]; 4012 4013 u8 reserved_1[0x40]; 4014 }; 4015 4016 struct mlx5_ifc_rtr2rts_qp_in_bits { 4017 u8 opcode[0x10]; 4018 u8 uid[0x10]; 4019 4020 u8 reserved_1[0x10]; 4021 u8 op_mod[0x10]; 4022 4023 u8 reserved_2[0x8]; 4024 u8 qpn[0x18]; 4025 4026 u8 reserved_3[0x20]; 4027 4028 u8 opt_param_mask[0x20]; 4029 4030 u8 reserved_4[0x20]; 4031 4032 struct mlx5_ifc_qpc_bits qpc; 4033 4034 u8 reserved_5[0x80]; 4035 }; 4036 4037 struct mlx5_ifc_rst2init_qp_out_bits { 4038 u8 status[0x8]; 4039 u8 reserved_0[0x18]; 4040 4041 u8 syndrome[0x20]; 4042 4043 u8 reserved_1[0x40]; 4044 }; 4045 4046 struct mlx5_ifc_rst2init_qp_in_bits { 4047 u8 opcode[0x10]; 4048 u8 uid[0x10]; 4049 4050 u8 reserved_1[0x10]; 4051 u8 op_mod[0x10]; 4052 4053 u8 reserved_2[0x8]; 4054 u8 qpn[0x18]; 4055 4056 u8 reserved_3[0x20]; 4057 4058 u8 opt_param_mask[0x20]; 4059 4060 u8 reserved_4[0x20]; 4061 4062 struct mlx5_ifc_qpc_bits qpc; 4063 4064 u8 reserved_5[0x80]; 4065 }; 4066 4067 struct mlx5_ifc_query_xrq_out_bits { 4068 u8 status[0x8]; 4069 u8 reserved_at_8[0x18]; 4070 4071 u8 syndrome[0x20]; 4072 4073 u8 reserved_at_40[0x40]; 4074 4075 struct mlx5_ifc_xrqc_bits xrq_context; 4076 }; 4077 4078 struct mlx5_ifc_query_xrq_in_bits { 4079 u8 opcode[0x10]; 4080 u8 reserved_at_10[0x10]; 4081 4082 u8 reserved_at_20[0x10]; 4083 u8 op_mod[0x10]; 4084 4085 u8 reserved_at_40[0x8]; 4086 u8 xrqn[0x18]; 4087 4088 u8 reserved_at_60[0x20]; 4089 }; 4090 4091 struct mlx5_ifc_resume_qp_out_bits { 4092 u8 status[0x8]; 4093 u8 reserved_0[0x18]; 4094 4095 u8 syndrome[0x20]; 4096 4097 u8 reserved_1[0x40]; 4098 }; 4099 4100 struct mlx5_ifc_resume_qp_in_bits { 4101 u8 opcode[0x10]; 4102 u8 reserved_0[0x10]; 4103 4104 u8 reserved_1[0x10]; 4105 u8 op_mod[0x10]; 4106 4107 u8 reserved_2[0x8]; 4108 u8 qpn[0x18]; 4109 4110 u8 reserved_3[0x20]; 4111 }; 4112 4113 struct mlx5_ifc_query_xrc_srq_out_bits { 4114 u8 status[0x8]; 4115 u8 reserved_0[0x18]; 4116 4117 u8 syndrome[0x20]; 4118 4119 u8 reserved_1[0x40]; 4120 4121 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4122 4123 u8 reserved_2[0x600]; 4124 4125 u8 pas[0][0x40]; 4126 }; 4127 4128 struct mlx5_ifc_query_xrc_srq_in_bits { 4129 u8 opcode[0x10]; 4130 u8 uid[0x10]; 4131 4132 u8 reserved_1[0x10]; 4133 u8 op_mod[0x10]; 4134 4135 u8 reserved_2[0x8]; 4136 u8 xrc_srqn[0x18]; 4137 4138 u8 reserved_3[0x20]; 4139 }; 4140 4141 struct mlx5_ifc_query_wol_rol_out_bits { 4142 u8 status[0x8]; 4143 u8 reserved_0[0x18]; 4144 4145 u8 syndrome[0x20]; 4146 4147 u8 reserved_1[0x10]; 4148 u8 rol_mode[0x8]; 4149 u8 wol_mode[0x8]; 4150 4151 u8 reserved_2[0x20]; 4152 }; 4153 4154 struct mlx5_ifc_query_wol_rol_in_bits { 4155 u8 opcode[0x10]; 4156 u8 reserved_0[0x10]; 4157 4158 u8 reserved_1[0x10]; 4159 u8 op_mod[0x10]; 4160 4161 u8 reserved_2[0x40]; 4162 }; 4163 4164 enum { 4165 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4166 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4167 }; 4168 4169 struct mlx5_ifc_query_vport_state_out_bits { 4170 u8 status[0x8]; 4171 u8 reserved_0[0x18]; 4172 4173 u8 syndrome[0x20]; 4174 4175 u8 reserved_1[0x20]; 4176 4177 u8 reserved_2[0x18]; 4178 u8 admin_state[0x4]; 4179 u8 state[0x4]; 4180 }; 4181 4182 enum { 4183 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 4184 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 4185 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 4186 }; 4187 4188 struct mlx5_ifc_query_vport_state_in_bits { 4189 u8 opcode[0x10]; 4190 u8 reserved_0[0x10]; 4191 4192 u8 reserved_1[0x10]; 4193 u8 op_mod[0x10]; 4194 4195 u8 other_vport[0x1]; 4196 u8 reserved_2[0xf]; 4197 u8 vport_number[0x10]; 4198 4199 u8 reserved_3[0x20]; 4200 }; 4201 4202 struct mlx5_ifc_query_vnic_env_out_bits { 4203 u8 status[0x8]; 4204 u8 reserved_at_8[0x18]; 4205 4206 u8 syndrome[0x20]; 4207 4208 u8 reserved_at_40[0x40]; 4209 4210 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4211 }; 4212 4213 enum { 4214 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4215 }; 4216 4217 struct mlx5_ifc_query_vnic_env_in_bits { 4218 u8 opcode[0x10]; 4219 u8 reserved_at_10[0x10]; 4220 4221 u8 reserved_at_20[0x10]; 4222 u8 op_mod[0x10]; 4223 4224 u8 other_vport[0x1]; 4225 u8 reserved_at_41[0xf]; 4226 u8 vport_number[0x10]; 4227 4228 u8 reserved_at_60[0x20]; 4229 }; 4230 4231 struct mlx5_ifc_query_vport_counter_out_bits { 4232 u8 status[0x8]; 4233 u8 reserved_0[0x18]; 4234 4235 u8 syndrome[0x20]; 4236 4237 u8 reserved_1[0x40]; 4238 4239 struct mlx5_ifc_traffic_counter_bits received_errors; 4240 4241 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4242 4243 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4244 4245 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4246 4247 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4248 4249 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4250 4251 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4252 4253 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4254 4255 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4256 4257 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4258 4259 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4260 4261 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4262 4263 u8 reserved_2[0xa00]; 4264 }; 4265 4266 enum { 4267 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4268 }; 4269 4270 struct mlx5_ifc_query_vport_counter_in_bits { 4271 u8 opcode[0x10]; 4272 u8 reserved_0[0x10]; 4273 4274 u8 reserved_1[0x10]; 4275 u8 op_mod[0x10]; 4276 4277 u8 other_vport[0x1]; 4278 u8 reserved_2[0xb]; 4279 u8 port_num[0x4]; 4280 u8 vport_number[0x10]; 4281 4282 u8 reserved_3[0x60]; 4283 4284 u8 clear[0x1]; 4285 u8 reserved_4[0x1f]; 4286 4287 u8 reserved_5[0x20]; 4288 }; 4289 4290 struct mlx5_ifc_query_tis_out_bits { 4291 u8 status[0x8]; 4292 u8 reserved_0[0x18]; 4293 4294 u8 syndrome[0x20]; 4295 4296 u8 reserved_1[0x40]; 4297 4298 struct mlx5_ifc_tisc_bits tis_context; 4299 }; 4300 4301 struct mlx5_ifc_query_tis_in_bits { 4302 u8 opcode[0x10]; 4303 u8 reserved_0[0x10]; 4304 4305 u8 reserved_1[0x10]; 4306 u8 op_mod[0x10]; 4307 4308 u8 reserved_2[0x8]; 4309 u8 tisn[0x18]; 4310 4311 u8 reserved_3[0x20]; 4312 }; 4313 4314 struct mlx5_ifc_query_tir_out_bits { 4315 u8 status[0x8]; 4316 u8 reserved_0[0x18]; 4317 4318 u8 syndrome[0x20]; 4319 4320 u8 reserved_1[0xc0]; 4321 4322 struct mlx5_ifc_tirc_bits tir_context; 4323 }; 4324 4325 struct mlx5_ifc_query_tir_in_bits { 4326 u8 opcode[0x10]; 4327 u8 reserved_0[0x10]; 4328 4329 u8 reserved_1[0x10]; 4330 u8 op_mod[0x10]; 4331 4332 u8 reserved_2[0x8]; 4333 u8 tirn[0x18]; 4334 4335 u8 reserved_3[0x20]; 4336 }; 4337 4338 struct mlx5_ifc_query_srq_out_bits { 4339 u8 status[0x8]; 4340 u8 reserved_0[0x18]; 4341 4342 u8 syndrome[0x20]; 4343 4344 u8 reserved_1[0x40]; 4345 4346 struct mlx5_ifc_srqc_bits srq_context_entry; 4347 4348 u8 reserved_2[0x600]; 4349 4350 u8 pas[0][0x40]; 4351 }; 4352 4353 struct mlx5_ifc_query_srq_in_bits { 4354 u8 opcode[0x10]; 4355 u8 reserved_0[0x10]; 4356 4357 u8 reserved_1[0x10]; 4358 u8 op_mod[0x10]; 4359 4360 u8 reserved_2[0x8]; 4361 u8 srqn[0x18]; 4362 4363 u8 reserved_3[0x20]; 4364 }; 4365 4366 struct mlx5_ifc_query_sq_out_bits { 4367 u8 status[0x8]; 4368 u8 reserved_0[0x18]; 4369 4370 u8 syndrome[0x20]; 4371 4372 u8 reserved_1[0xc0]; 4373 4374 struct mlx5_ifc_sqc_bits sq_context; 4375 }; 4376 4377 struct mlx5_ifc_query_sq_in_bits { 4378 u8 opcode[0x10]; 4379 u8 reserved_0[0x10]; 4380 4381 u8 reserved_1[0x10]; 4382 u8 op_mod[0x10]; 4383 4384 u8 reserved_2[0x8]; 4385 u8 sqn[0x18]; 4386 4387 u8 reserved_3[0x20]; 4388 }; 4389 4390 struct mlx5_ifc_query_special_contexts_out_bits { 4391 u8 status[0x8]; 4392 u8 reserved_0[0x18]; 4393 4394 u8 syndrome[0x20]; 4395 4396 u8 dump_fill_mkey[0x20]; 4397 4398 u8 resd_lkey[0x20]; 4399 }; 4400 4401 struct mlx5_ifc_query_special_contexts_in_bits { 4402 u8 opcode[0x10]; 4403 u8 reserved_0[0x10]; 4404 4405 u8 reserved_1[0x10]; 4406 u8 op_mod[0x10]; 4407 4408 u8 reserved_2[0x40]; 4409 }; 4410 4411 struct mlx5_ifc_query_scheduling_element_out_bits { 4412 u8 status[0x8]; 4413 u8 reserved_at_8[0x18]; 4414 4415 u8 syndrome[0x20]; 4416 4417 u8 reserved_at_40[0xc0]; 4418 4419 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4420 4421 u8 reserved_at_300[0x100]; 4422 }; 4423 4424 enum { 4425 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4426 }; 4427 4428 struct mlx5_ifc_query_scheduling_element_in_bits { 4429 u8 opcode[0x10]; 4430 u8 reserved_at_10[0x10]; 4431 4432 u8 reserved_at_20[0x10]; 4433 u8 op_mod[0x10]; 4434 4435 u8 scheduling_hierarchy[0x8]; 4436 u8 reserved_at_48[0x18]; 4437 4438 u8 scheduling_element_id[0x20]; 4439 4440 u8 reserved_at_80[0x180]; 4441 }; 4442 4443 struct mlx5_ifc_query_rqt_out_bits { 4444 u8 status[0x8]; 4445 u8 reserved_0[0x18]; 4446 4447 u8 syndrome[0x20]; 4448 4449 u8 reserved_1[0xc0]; 4450 4451 struct mlx5_ifc_rqtc_bits rqt_context; 4452 }; 4453 4454 struct mlx5_ifc_query_rqt_in_bits { 4455 u8 opcode[0x10]; 4456 u8 reserved_0[0x10]; 4457 4458 u8 reserved_1[0x10]; 4459 u8 op_mod[0x10]; 4460 4461 u8 reserved_2[0x8]; 4462 u8 rqtn[0x18]; 4463 4464 u8 reserved_3[0x20]; 4465 }; 4466 4467 struct mlx5_ifc_query_rq_out_bits { 4468 u8 status[0x8]; 4469 u8 reserved_0[0x18]; 4470 4471 u8 syndrome[0x20]; 4472 4473 u8 reserved_1[0xc0]; 4474 4475 struct mlx5_ifc_rqc_bits rq_context; 4476 }; 4477 4478 struct mlx5_ifc_query_rq_in_bits { 4479 u8 opcode[0x10]; 4480 u8 reserved_0[0x10]; 4481 4482 u8 reserved_1[0x10]; 4483 u8 op_mod[0x10]; 4484 4485 u8 reserved_2[0x8]; 4486 u8 rqn[0x18]; 4487 4488 u8 reserved_3[0x20]; 4489 }; 4490 4491 struct mlx5_ifc_query_roce_address_out_bits { 4492 u8 status[0x8]; 4493 u8 reserved_0[0x18]; 4494 4495 u8 syndrome[0x20]; 4496 4497 u8 reserved_1[0x40]; 4498 4499 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4500 }; 4501 4502 struct mlx5_ifc_query_roce_address_in_bits { 4503 u8 opcode[0x10]; 4504 u8 reserved_0[0x10]; 4505 4506 u8 reserved_1[0x10]; 4507 u8 op_mod[0x10]; 4508 4509 u8 roce_address_index[0x10]; 4510 u8 reserved_2[0x10]; 4511 4512 u8 reserved_3[0x20]; 4513 }; 4514 4515 struct mlx5_ifc_query_rmp_out_bits { 4516 u8 status[0x8]; 4517 u8 reserved_0[0x18]; 4518 4519 u8 syndrome[0x20]; 4520 4521 u8 reserved_1[0xc0]; 4522 4523 struct mlx5_ifc_rmpc_bits rmp_context; 4524 }; 4525 4526 struct mlx5_ifc_query_rmp_in_bits { 4527 u8 opcode[0x10]; 4528 u8 reserved_0[0x10]; 4529 4530 u8 reserved_1[0x10]; 4531 u8 op_mod[0x10]; 4532 4533 u8 reserved_2[0x8]; 4534 u8 rmpn[0x18]; 4535 4536 u8 reserved_3[0x20]; 4537 }; 4538 4539 struct mlx5_ifc_query_rdb_out_bits { 4540 u8 status[0x8]; 4541 u8 reserved_0[0x18]; 4542 4543 u8 syndrome[0x20]; 4544 4545 u8 reserved_1[0x20]; 4546 4547 u8 reserved_2[0x18]; 4548 u8 rdb_list_size[0x8]; 4549 4550 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4551 }; 4552 4553 struct mlx5_ifc_query_rdb_in_bits { 4554 u8 opcode[0x10]; 4555 u8 reserved_0[0x10]; 4556 4557 u8 reserved_1[0x10]; 4558 u8 op_mod[0x10]; 4559 4560 u8 reserved_2[0x8]; 4561 u8 qpn[0x18]; 4562 4563 u8 reserved_3[0x20]; 4564 }; 4565 4566 struct mlx5_ifc_query_qp_out_bits { 4567 u8 status[0x8]; 4568 u8 reserved_0[0x18]; 4569 4570 u8 syndrome[0x20]; 4571 4572 u8 reserved_1[0x40]; 4573 4574 u8 opt_param_mask[0x20]; 4575 4576 u8 reserved_2[0x20]; 4577 4578 struct mlx5_ifc_qpc_bits qpc; 4579 4580 u8 reserved_3[0x80]; 4581 4582 u8 pas[0][0x40]; 4583 }; 4584 4585 struct mlx5_ifc_query_qp_in_bits { 4586 u8 opcode[0x10]; 4587 u8 reserved_0[0x10]; 4588 4589 u8 reserved_1[0x10]; 4590 u8 op_mod[0x10]; 4591 4592 u8 reserved_2[0x8]; 4593 u8 qpn[0x18]; 4594 4595 u8 reserved_3[0x20]; 4596 }; 4597 4598 struct mlx5_ifc_query_q_counter_out_bits { 4599 u8 status[0x8]; 4600 u8 reserved_0[0x18]; 4601 4602 u8 syndrome[0x20]; 4603 4604 u8 reserved_1[0x40]; 4605 4606 u8 rx_write_requests[0x20]; 4607 4608 u8 reserved_2[0x20]; 4609 4610 u8 rx_read_requests[0x20]; 4611 4612 u8 reserved_3[0x20]; 4613 4614 u8 rx_atomic_requests[0x20]; 4615 4616 u8 reserved_4[0x20]; 4617 4618 u8 rx_dct_connect[0x20]; 4619 4620 u8 reserved_5[0x20]; 4621 4622 u8 out_of_buffer[0x20]; 4623 4624 u8 reserved_7[0x20]; 4625 4626 u8 out_of_sequence[0x20]; 4627 4628 u8 reserved_8[0x20]; 4629 4630 u8 duplicate_request[0x20]; 4631 4632 u8 reserved_9[0x20]; 4633 4634 u8 rnr_nak_retry_err[0x20]; 4635 4636 u8 reserved_10[0x20]; 4637 4638 u8 packet_seq_err[0x20]; 4639 4640 u8 reserved_11[0x20]; 4641 4642 u8 implied_nak_seq_err[0x20]; 4643 4644 u8 reserved_12[0x20]; 4645 4646 u8 local_ack_timeout_err[0x20]; 4647 4648 u8 reserved_13[0x20]; 4649 4650 u8 resp_rnr_nak[0x20]; 4651 4652 u8 reserved_14[0x20]; 4653 4654 u8 req_rnr_retries_exceeded[0x20]; 4655 4656 u8 reserved_15[0x460]; 4657 }; 4658 4659 struct mlx5_ifc_query_q_counter_in_bits { 4660 u8 opcode[0x10]; 4661 u8 reserved_0[0x10]; 4662 4663 u8 reserved_1[0x10]; 4664 u8 op_mod[0x10]; 4665 4666 u8 reserved_2[0x80]; 4667 4668 u8 clear[0x1]; 4669 u8 reserved_3[0x1f]; 4670 4671 u8 reserved_4[0x18]; 4672 u8 counter_set_id[0x8]; 4673 }; 4674 4675 struct mlx5_ifc_query_pages_out_bits { 4676 u8 status[0x8]; 4677 u8 reserved_0[0x18]; 4678 4679 u8 syndrome[0x20]; 4680 4681 u8 reserved_1[0x10]; 4682 u8 function_id[0x10]; 4683 4684 u8 num_pages[0x20]; 4685 }; 4686 4687 enum { 4688 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4689 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4690 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4691 }; 4692 4693 struct mlx5_ifc_query_pages_in_bits { 4694 u8 opcode[0x10]; 4695 u8 reserved_0[0x10]; 4696 4697 u8 reserved_1[0x10]; 4698 u8 op_mod[0x10]; 4699 4700 u8 reserved_2[0x10]; 4701 u8 function_id[0x10]; 4702 4703 u8 reserved_3[0x20]; 4704 }; 4705 4706 struct mlx5_ifc_query_nic_vport_context_out_bits { 4707 u8 status[0x8]; 4708 u8 reserved_0[0x18]; 4709 4710 u8 syndrome[0x20]; 4711 4712 u8 reserved_1[0x40]; 4713 4714 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4715 }; 4716 4717 struct mlx5_ifc_query_nic_vport_context_in_bits { 4718 u8 opcode[0x10]; 4719 u8 reserved_0[0x10]; 4720 4721 u8 reserved_1[0x10]; 4722 u8 op_mod[0x10]; 4723 4724 u8 other_vport[0x1]; 4725 u8 reserved_2[0xf]; 4726 u8 vport_number[0x10]; 4727 4728 u8 reserved_3[0x5]; 4729 u8 allowed_list_type[0x3]; 4730 u8 reserved_4[0x18]; 4731 }; 4732 4733 struct mlx5_ifc_query_mkey_out_bits { 4734 u8 status[0x8]; 4735 u8 reserved_0[0x18]; 4736 4737 u8 syndrome[0x20]; 4738 4739 u8 reserved_1[0x40]; 4740 4741 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4742 4743 u8 reserved_2[0x600]; 4744 4745 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4746 4747 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4748 }; 4749 4750 struct mlx5_ifc_query_mkey_in_bits { 4751 u8 opcode[0x10]; 4752 u8 reserved_0[0x10]; 4753 4754 u8 reserved_1[0x10]; 4755 u8 op_mod[0x10]; 4756 4757 u8 reserved_2[0x8]; 4758 u8 mkey_index[0x18]; 4759 4760 u8 pg_access[0x1]; 4761 u8 reserved_3[0x1f]; 4762 }; 4763 4764 struct mlx5_ifc_query_mad_demux_out_bits { 4765 u8 status[0x8]; 4766 u8 reserved_0[0x18]; 4767 4768 u8 syndrome[0x20]; 4769 4770 u8 reserved_1[0x40]; 4771 4772 u8 mad_dumux_parameters_block[0x20]; 4773 }; 4774 4775 struct mlx5_ifc_query_mad_demux_in_bits { 4776 u8 opcode[0x10]; 4777 u8 reserved_0[0x10]; 4778 4779 u8 reserved_1[0x10]; 4780 u8 op_mod[0x10]; 4781 4782 u8 reserved_2[0x40]; 4783 }; 4784 4785 struct mlx5_ifc_query_l2_table_entry_out_bits { 4786 u8 status[0x8]; 4787 u8 reserved_0[0x18]; 4788 4789 u8 syndrome[0x20]; 4790 4791 u8 reserved_1[0xa0]; 4792 4793 u8 reserved_2[0x13]; 4794 u8 vlan_valid[0x1]; 4795 u8 vlan[0xc]; 4796 4797 struct mlx5_ifc_mac_address_layout_bits mac_address; 4798 4799 u8 reserved_3[0xc0]; 4800 }; 4801 4802 struct mlx5_ifc_query_l2_table_entry_in_bits { 4803 u8 opcode[0x10]; 4804 u8 reserved_0[0x10]; 4805 4806 u8 reserved_1[0x10]; 4807 u8 op_mod[0x10]; 4808 4809 u8 reserved_2[0x60]; 4810 4811 u8 reserved_3[0x8]; 4812 u8 table_index[0x18]; 4813 4814 u8 reserved_4[0x140]; 4815 }; 4816 4817 struct mlx5_ifc_query_issi_out_bits { 4818 u8 status[0x8]; 4819 u8 reserved_0[0x18]; 4820 4821 u8 syndrome[0x20]; 4822 4823 u8 reserved_1[0x10]; 4824 u8 current_issi[0x10]; 4825 4826 u8 reserved_2[0xa0]; 4827 4828 u8 supported_issi_reserved[76][0x8]; 4829 u8 supported_issi_dw0[0x20]; 4830 }; 4831 4832 struct mlx5_ifc_query_issi_in_bits { 4833 u8 opcode[0x10]; 4834 u8 reserved_0[0x10]; 4835 4836 u8 reserved_1[0x10]; 4837 u8 op_mod[0x10]; 4838 4839 u8 reserved_2[0x40]; 4840 }; 4841 4842 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4843 u8 status[0x8]; 4844 u8 reserved_0[0x18]; 4845 4846 u8 syndrome[0x20]; 4847 4848 u8 reserved_1[0x40]; 4849 4850 struct mlx5_ifc_pkey_bits pkey[0]; 4851 }; 4852 4853 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4854 u8 opcode[0x10]; 4855 u8 reserved_0[0x10]; 4856 4857 u8 reserved_1[0x10]; 4858 u8 op_mod[0x10]; 4859 4860 u8 other_vport[0x1]; 4861 u8 reserved_2[0xb]; 4862 u8 port_num[0x4]; 4863 u8 vport_number[0x10]; 4864 4865 u8 reserved_3[0x10]; 4866 u8 pkey_index[0x10]; 4867 }; 4868 4869 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4870 u8 status[0x8]; 4871 u8 reserved_0[0x18]; 4872 4873 u8 syndrome[0x20]; 4874 4875 u8 reserved_1[0x20]; 4876 4877 u8 gids_num[0x10]; 4878 u8 reserved_2[0x10]; 4879 4880 struct mlx5_ifc_array128_auto_bits gid[0]; 4881 }; 4882 4883 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4884 u8 opcode[0x10]; 4885 u8 reserved_0[0x10]; 4886 4887 u8 reserved_1[0x10]; 4888 u8 op_mod[0x10]; 4889 4890 u8 other_vport[0x1]; 4891 u8 reserved_2[0xb]; 4892 u8 port_num[0x4]; 4893 u8 vport_number[0x10]; 4894 4895 u8 reserved_3[0x10]; 4896 u8 gid_index[0x10]; 4897 }; 4898 4899 struct mlx5_ifc_query_hca_vport_context_out_bits { 4900 u8 status[0x8]; 4901 u8 reserved_0[0x18]; 4902 4903 u8 syndrome[0x20]; 4904 4905 u8 reserved_1[0x40]; 4906 4907 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4908 }; 4909 4910 struct mlx5_ifc_query_hca_vport_context_in_bits { 4911 u8 opcode[0x10]; 4912 u8 reserved_0[0x10]; 4913 4914 u8 reserved_1[0x10]; 4915 u8 op_mod[0x10]; 4916 4917 u8 other_vport[0x1]; 4918 u8 reserved_2[0xb]; 4919 u8 port_num[0x4]; 4920 u8 vport_number[0x10]; 4921 4922 u8 reserved_3[0x20]; 4923 }; 4924 4925 struct mlx5_ifc_query_hca_cap_out_bits { 4926 u8 status[0x8]; 4927 u8 reserved_0[0x18]; 4928 4929 u8 syndrome[0x20]; 4930 4931 u8 reserved_1[0x40]; 4932 4933 union mlx5_ifc_hca_cap_union_bits capability; 4934 }; 4935 4936 struct mlx5_ifc_query_hca_cap_in_bits { 4937 u8 opcode[0x10]; 4938 u8 reserved_0[0x10]; 4939 4940 u8 reserved_1[0x10]; 4941 u8 op_mod[0x10]; 4942 4943 u8 reserved_2[0x40]; 4944 }; 4945 4946 struct mlx5_ifc_query_flow_table_out_bits { 4947 u8 status[0x8]; 4948 u8 reserved_at_8[0x18]; 4949 4950 u8 syndrome[0x20]; 4951 4952 u8 reserved_at_40[0x80]; 4953 4954 struct mlx5_ifc_flow_table_context_bits flow_table_context; 4955 }; 4956 4957 struct mlx5_ifc_query_flow_table_in_bits { 4958 u8 opcode[0x10]; 4959 u8 reserved_0[0x10]; 4960 4961 u8 reserved_1[0x10]; 4962 u8 op_mod[0x10]; 4963 4964 u8 other_vport[0x1]; 4965 u8 reserved_2[0xf]; 4966 u8 vport_number[0x10]; 4967 4968 u8 reserved_3[0x20]; 4969 4970 u8 table_type[0x8]; 4971 u8 reserved_4[0x18]; 4972 4973 u8 reserved_5[0x8]; 4974 u8 table_id[0x18]; 4975 4976 u8 reserved_6[0x140]; 4977 }; 4978 4979 struct mlx5_ifc_query_fte_out_bits { 4980 u8 status[0x8]; 4981 u8 reserved_0[0x18]; 4982 4983 u8 syndrome[0x20]; 4984 4985 u8 reserved_1[0x1c0]; 4986 4987 struct mlx5_ifc_flow_context_bits flow_context; 4988 }; 4989 4990 struct mlx5_ifc_query_fte_in_bits { 4991 u8 opcode[0x10]; 4992 u8 reserved_0[0x10]; 4993 4994 u8 reserved_1[0x10]; 4995 u8 op_mod[0x10]; 4996 4997 u8 other_vport[0x1]; 4998 u8 reserved_2[0xf]; 4999 u8 vport_number[0x10]; 5000 5001 u8 reserved_3[0x20]; 5002 5003 u8 table_type[0x8]; 5004 u8 reserved_4[0x18]; 5005 5006 u8 reserved_5[0x8]; 5007 u8 table_id[0x18]; 5008 5009 u8 reserved_6[0x40]; 5010 5011 u8 flow_index[0x20]; 5012 5013 u8 reserved_7[0xe0]; 5014 }; 5015 5016 enum { 5017 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5018 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5019 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5020 }; 5021 5022 struct mlx5_ifc_query_flow_group_out_bits { 5023 u8 status[0x8]; 5024 u8 reserved_0[0x18]; 5025 5026 u8 syndrome[0x20]; 5027 5028 u8 reserved_1[0xa0]; 5029 5030 u8 start_flow_index[0x20]; 5031 5032 u8 reserved_2[0x20]; 5033 5034 u8 end_flow_index[0x20]; 5035 5036 u8 reserved_3[0xa0]; 5037 5038 u8 reserved_4[0x18]; 5039 u8 match_criteria_enable[0x8]; 5040 5041 struct mlx5_ifc_fte_match_param_bits match_criteria; 5042 5043 u8 reserved_5[0xe00]; 5044 }; 5045 5046 struct mlx5_ifc_query_flow_group_in_bits { 5047 u8 opcode[0x10]; 5048 u8 reserved_0[0x10]; 5049 5050 u8 reserved_1[0x10]; 5051 u8 op_mod[0x10]; 5052 5053 u8 other_vport[0x1]; 5054 u8 reserved_2[0xf]; 5055 u8 vport_number[0x10]; 5056 5057 u8 reserved_3[0x20]; 5058 5059 u8 table_type[0x8]; 5060 u8 reserved_4[0x18]; 5061 5062 u8 reserved_5[0x8]; 5063 u8 table_id[0x18]; 5064 5065 u8 group_id[0x20]; 5066 5067 u8 reserved_6[0x120]; 5068 }; 5069 5070 struct mlx5_ifc_query_flow_counter_out_bits { 5071 u8 status[0x8]; 5072 u8 reserved_at_8[0x18]; 5073 5074 u8 syndrome[0x20]; 5075 5076 u8 reserved_at_40[0x40]; 5077 5078 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 5079 }; 5080 5081 struct mlx5_ifc_query_flow_counter_in_bits { 5082 u8 opcode[0x10]; 5083 u8 reserved_at_10[0x10]; 5084 5085 u8 reserved_at_20[0x10]; 5086 u8 op_mod[0x10]; 5087 5088 u8 reserved_at_40[0x80]; 5089 5090 u8 clear[0x1]; 5091 u8 reserved_at_c1[0xf]; 5092 u8 num_of_counters[0x10]; 5093 5094 u8 reserved_at_e0[0x10]; 5095 u8 flow_counter_id[0x10]; 5096 }; 5097 5098 struct mlx5_ifc_query_esw_vport_context_out_bits { 5099 u8 status[0x8]; 5100 u8 reserved_0[0x18]; 5101 5102 u8 syndrome[0x20]; 5103 5104 u8 reserved_1[0x40]; 5105 5106 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5107 }; 5108 5109 struct mlx5_ifc_query_esw_vport_context_in_bits { 5110 u8 opcode[0x10]; 5111 u8 reserved_0[0x10]; 5112 5113 u8 reserved_1[0x10]; 5114 u8 op_mod[0x10]; 5115 5116 u8 other_vport[0x1]; 5117 u8 reserved_2[0xf]; 5118 u8 vport_number[0x10]; 5119 5120 u8 reserved_3[0x20]; 5121 }; 5122 5123 struct mlx5_ifc_query_eq_out_bits { 5124 u8 status[0x8]; 5125 u8 reserved_0[0x18]; 5126 5127 u8 syndrome[0x20]; 5128 5129 u8 reserved_1[0x40]; 5130 5131 struct mlx5_ifc_eqc_bits eq_context_entry; 5132 5133 u8 reserved_2[0x40]; 5134 5135 u8 event_bitmask[0x40]; 5136 5137 u8 reserved_3[0x580]; 5138 5139 u8 pas[0][0x40]; 5140 }; 5141 5142 struct mlx5_ifc_query_eq_in_bits { 5143 u8 opcode[0x10]; 5144 u8 reserved_0[0x10]; 5145 5146 u8 reserved_1[0x10]; 5147 u8 op_mod[0x10]; 5148 5149 u8 reserved_2[0x18]; 5150 u8 eq_number[0x8]; 5151 5152 u8 reserved_3[0x20]; 5153 }; 5154 5155 struct mlx5_ifc_query_dct_out_bits { 5156 u8 status[0x8]; 5157 u8 reserved_0[0x18]; 5158 5159 u8 syndrome[0x20]; 5160 5161 u8 reserved_1[0x40]; 5162 5163 struct mlx5_ifc_dctc_bits dct_context_entry; 5164 5165 u8 reserved_2[0x180]; 5166 }; 5167 5168 struct mlx5_ifc_query_dct_in_bits { 5169 u8 opcode[0x10]; 5170 u8 reserved_0[0x10]; 5171 5172 u8 reserved_1[0x10]; 5173 u8 op_mod[0x10]; 5174 5175 u8 reserved_2[0x8]; 5176 u8 dctn[0x18]; 5177 5178 u8 reserved_3[0x20]; 5179 }; 5180 5181 struct mlx5_ifc_query_dc_cnak_trace_out_bits { 5182 u8 status[0x8]; 5183 u8 reserved_0[0x18]; 5184 5185 u8 syndrome[0x20]; 5186 5187 u8 enable[0x1]; 5188 u8 reserved_1[0x1f]; 5189 5190 u8 reserved_2[0x160]; 5191 5192 struct mlx5_ifc_cmd_pas_bits pas; 5193 }; 5194 5195 struct mlx5_ifc_query_dc_cnak_trace_in_bits { 5196 u8 opcode[0x10]; 5197 u8 reserved_0[0x10]; 5198 5199 u8 reserved_1[0x10]; 5200 u8 op_mod[0x10]; 5201 5202 u8 reserved_2[0x40]; 5203 }; 5204 5205 struct mlx5_ifc_packet_reformat_context_in_bits { 5206 u8 reserved_at_0[0x5]; 5207 u8 reformat_type[0x3]; 5208 u8 reserved_at_8[0xe]; 5209 u8 reformat_data_size[0xa]; 5210 5211 u8 reserved_at_20[0x10]; 5212 u8 reformat_data[2][0x8]; 5213 5214 u8 more_reformat_data[0][0x8]; 5215 }; 5216 5217 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5218 u8 status[0x8]; 5219 u8 reserved_at_8[0x18]; 5220 5221 u8 syndrome[0x20]; 5222 5223 u8 reserved_at_40[0xa0]; 5224 5225 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 5226 }; 5227 5228 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5229 u8 opcode[0x10]; 5230 u8 reserved_at_10[0x10]; 5231 5232 u8 reserved_at_20[0x10]; 5233 u8 op_mod[0x10]; 5234 5235 u8 packet_reformat_id[0x20]; 5236 5237 u8 reserved_at_60[0xa0]; 5238 }; 5239 5240 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5241 u8 status[0x8]; 5242 u8 reserved_at_8[0x18]; 5243 5244 u8 syndrome[0x20]; 5245 5246 u8 packet_reformat_id[0x20]; 5247 5248 u8 reserved_at_60[0x20]; 5249 }; 5250 5251 enum mlx5_reformat_ctx_type { 5252 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5253 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5254 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5255 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5256 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5257 }; 5258 5259 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5260 u8 opcode[0x10]; 5261 u8 reserved_at_10[0x10]; 5262 5263 u8 reserved_at_20[0x10]; 5264 u8 op_mod[0x10]; 5265 5266 u8 reserved_at_40[0xa0]; 5267 5268 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5269 }; 5270 5271 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5272 u8 status[0x8]; 5273 u8 reserved_at_8[0x18]; 5274 5275 u8 syndrome[0x20]; 5276 5277 u8 reserved_at_40[0x40]; 5278 }; 5279 5280 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5281 u8 opcode[0x10]; 5282 u8 reserved_at_10[0x10]; 5283 5284 u8 reserved_20[0x10]; 5285 u8 op_mod[0x10]; 5286 5287 u8 packet_reformat_id[0x20]; 5288 5289 u8 reserved_60[0x20]; 5290 }; 5291 5292 struct mlx5_ifc_query_cq_out_bits { 5293 u8 status[0x8]; 5294 u8 reserved_0[0x18]; 5295 5296 u8 syndrome[0x20]; 5297 5298 u8 reserved_1[0x40]; 5299 5300 struct mlx5_ifc_cqc_bits cq_context; 5301 5302 u8 reserved_2[0x600]; 5303 5304 u8 pas[0][0x40]; 5305 }; 5306 5307 struct mlx5_ifc_query_cq_in_bits { 5308 u8 opcode[0x10]; 5309 u8 reserved_0[0x10]; 5310 5311 u8 reserved_1[0x10]; 5312 u8 op_mod[0x10]; 5313 5314 u8 reserved_2[0x8]; 5315 u8 cqn[0x18]; 5316 5317 u8 reserved_3[0x20]; 5318 }; 5319 5320 struct mlx5_ifc_query_cong_status_out_bits { 5321 u8 status[0x8]; 5322 u8 reserved_0[0x18]; 5323 5324 u8 syndrome[0x20]; 5325 5326 u8 reserved_1[0x20]; 5327 5328 u8 enable[0x1]; 5329 u8 tag_enable[0x1]; 5330 u8 reserved_2[0x1e]; 5331 }; 5332 5333 struct mlx5_ifc_query_cong_status_in_bits { 5334 u8 opcode[0x10]; 5335 u8 reserved_0[0x10]; 5336 5337 u8 reserved_1[0x10]; 5338 u8 op_mod[0x10]; 5339 5340 u8 reserved_2[0x18]; 5341 u8 priority[0x4]; 5342 u8 cong_protocol[0x4]; 5343 5344 u8 reserved_3[0x20]; 5345 }; 5346 5347 struct mlx5_ifc_query_cong_statistics_out_bits { 5348 u8 status[0x8]; 5349 u8 reserved_0[0x18]; 5350 5351 u8 syndrome[0x20]; 5352 5353 u8 reserved_1[0x40]; 5354 5355 u8 rp_cur_flows[0x20]; 5356 5357 u8 sum_flows[0x20]; 5358 5359 u8 rp_cnp_ignored_high[0x20]; 5360 5361 u8 rp_cnp_ignored_low[0x20]; 5362 5363 u8 rp_cnp_handled_high[0x20]; 5364 5365 u8 rp_cnp_handled_low[0x20]; 5366 5367 u8 reserved_2[0x100]; 5368 5369 u8 time_stamp_high[0x20]; 5370 5371 u8 time_stamp_low[0x20]; 5372 5373 u8 accumulators_period[0x20]; 5374 5375 u8 np_ecn_marked_roce_packets_high[0x20]; 5376 5377 u8 np_ecn_marked_roce_packets_low[0x20]; 5378 5379 u8 np_cnp_sent_high[0x20]; 5380 5381 u8 np_cnp_sent_low[0x20]; 5382 5383 u8 reserved_3[0x560]; 5384 }; 5385 5386 struct mlx5_ifc_query_cong_statistics_in_bits { 5387 u8 opcode[0x10]; 5388 u8 reserved_0[0x10]; 5389 5390 u8 reserved_1[0x10]; 5391 u8 op_mod[0x10]; 5392 5393 u8 clear[0x1]; 5394 u8 reserved_2[0x1f]; 5395 5396 u8 reserved_3[0x20]; 5397 }; 5398 5399 struct mlx5_ifc_query_cong_params_out_bits { 5400 u8 status[0x8]; 5401 u8 reserved_0[0x18]; 5402 5403 u8 syndrome[0x20]; 5404 5405 u8 reserved_1[0x40]; 5406 5407 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5408 }; 5409 5410 struct mlx5_ifc_query_cong_params_in_bits { 5411 u8 opcode[0x10]; 5412 u8 reserved_0[0x10]; 5413 5414 u8 reserved_1[0x10]; 5415 u8 op_mod[0x10]; 5416 5417 u8 reserved_2[0x1c]; 5418 u8 cong_protocol[0x4]; 5419 5420 u8 reserved_3[0x20]; 5421 }; 5422 5423 struct mlx5_ifc_query_burst_size_out_bits { 5424 u8 status[0x8]; 5425 u8 reserved_0[0x18]; 5426 5427 u8 syndrome[0x20]; 5428 5429 u8 reserved_1[0x20]; 5430 5431 u8 reserved_2[0x9]; 5432 u8 device_burst_size[0x17]; 5433 }; 5434 5435 struct mlx5_ifc_query_burst_size_in_bits { 5436 u8 opcode[0x10]; 5437 u8 reserved_0[0x10]; 5438 5439 u8 reserved_1[0x10]; 5440 u8 op_mod[0x10]; 5441 5442 u8 reserved_2[0x40]; 5443 }; 5444 5445 struct mlx5_ifc_query_adapter_out_bits { 5446 u8 status[0x8]; 5447 u8 reserved_0[0x18]; 5448 5449 u8 syndrome[0x20]; 5450 5451 u8 reserved_1[0x40]; 5452 5453 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5454 }; 5455 5456 struct mlx5_ifc_query_adapter_in_bits { 5457 u8 opcode[0x10]; 5458 u8 reserved_0[0x10]; 5459 5460 u8 reserved_1[0x10]; 5461 u8 op_mod[0x10]; 5462 5463 u8 reserved_2[0x40]; 5464 }; 5465 5466 struct mlx5_ifc_qp_2rst_out_bits { 5467 u8 status[0x8]; 5468 u8 reserved_0[0x18]; 5469 5470 u8 syndrome[0x20]; 5471 5472 u8 reserved_1[0x40]; 5473 }; 5474 5475 struct mlx5_ifc_qp_2rst_in_bits { 5476 u8 opcode[0x10]; 5477 u8 uid[0x10]; 5478 5479 u8 reserved_1[0x10]; 5480 u8 op_mod[0x10]; 5481 5482 u8 reserved_2[0x8]; 5483 u8 qpn[0x18]; 5484 5485 u8 reserved_3[0x20]; 5486 }; 5487 5488 struct mlx5_ifc_qp_2err_out_bits { 5489 u8 status[0x8]; 5490 u8 reserved_0[0x18]; 5491 5492 u8 syndrome[0x20]; 5493 5494 u8 reserved_1[0x40]; 5495 }; 5496 5497 struct mlx5_ifc_qp_2err_in_bits { 5498 u8 opcode[0x10]; 5499 u8 uid[0x10]; 5500 5501 u8 reserved_1[0x10]; 5502 u8 op_mod[0x10]; 5503 5504 u8 reserved_2[0x8]; 5505 u8 qpn[0x18]; 5506 5507 u8 reserved_3[0x20]; 5508 }; 5509 5510 struct mlx5_ifc_para_vport_element_bits { 5511 u8 reserved_at_0[0xc]; 5512 u8 traffic_class[0x4]; 5513 u8 qos_para_vport_number[0x10]; 5514 }; 5515 5516 struct mlx5_ifc_page_fault_resume_out_bits { 5517 u8 status[0x8]; 5518 u8 reserved_0[0x18]; 5519 5520 u8 syndrome[0x20]; 5521 5522 u8 reserved_1[0x40]; 5523 }; 5524 5525 struct mlx5_ifc_page_fault_resume_in_bits { 5526 u8 opcode[0x10]; 5527 u8 reserved_0[0x10]; 5528 5529 u8 reserved_1[0x10]; 5530 u8 op_mod[0x10]; 5531 5532 u8 error[0x1]; 5533 u8 reserved_2[0x4]; 5534 u8 rdma[0x1]; 5535 u8 read_write[0x1]; 5536 u8 req_res[0x1]; 5537 u8 qpn[0x18]; 5538 5539 u8 reserved_3[0x20]; 5540 }; 5541 5542 struct mlx5_ifc_nop_out_bits { 5543 u8 status[0x8]; 5544 u8 reserved_0[0x18]; 5545 5546 u8 syndrome[0x20]; 5547 5548 u8 reserved_1[0x40]; 5549 }; 5550 5551 struct mlx5_ifc_nop_in_bits { 5552 u8 opcode[0x10]; 5553 u8 reserved_0[0x10]; 5554 5555 u8 reserved_1[0x10]; 5556 u8 op_mod[0x10]; 5557 5558 u8 reserved_2[0x40]; 5559 }; 5560 5561 struct mlx5_ifc_modify_vport_state_out_bits { 5562 u8 status[0x8]; 5563 u8 reserved_0[0x18]; 5564 5565 u8 syndrome[0x20]; 5566 5567 u8 reserved_1[0x40]; 5568 }; 5569 5570 enum { 5571 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5572 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5573 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5574 }; 5575 5576 enum { 5577 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5578 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5579 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5580 }; 5581 5582 struct mlx5_ifc_modify_vport_state_in_bits { 5583 u8 opcode[0x10]; 5584 u8 reserved_0[0x10]; 5585 5586 u8 reserved_1[0x10]; 5587 u8 op_mod[0x10]; 5588 5589 u8 other_vport[0x1]; 5590 u8 reserved_2[0xf]; 5591 u8 vport_number[0x10]; 5592 5593 u8 reserved_3[0x18]; 5594 u8 admin_state[0x4]; 5595 u8 reserved_4[0x4]; 5596 }; 5597 5598 struct mlx5_ifc_modify_tis_out_bits { 5599 u8 status[0x8]; 5600 u8 reserved_0[0x18]; 5601 5602 u8 syndrome[0x20]; 5603 5604 u8 reserved_1[0x40]; 5605 }; 5606 5607 struct mlx5_ifc_modify_tis_bitmask_bits { 5608 u8 reserved_at_0[0x20]; 5609 5610 u8 reserved_at_20[0x1d]; 5611 u8 lag_tx_port_affinity[0x1]; 5612 u8 strict_lag_tx_port_affinity[0x1]; 5613 u8 prio[0x1]; 5614 }; 5615 5616 struct mlx5_ifc_modify_tis_in_bits { 5617 u8 opcode[0x10]; 5618 u8 uid[0x10]; 5619 5620 u8 reserved_1[0x10]; 5621 u8 op_mod[0x10]; 5622 5623 u8 reserved_2[0x8]; 5624 u8 tisn[0x18]; 5625 5626 u8 reserved_3[0x20]; 5627 5628 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5629 5630 u8 reserved_4[0x40]; 5631 5632 struct mlx5_ifc_tisc_bits ctx; 5633 }; 5634 5635 struct mlx5_ifc_modify_tir_out_bits { 5636 u8 status[0x8]; 5637 u8 reserved_0[0x18]; 5638 5639 u8 syndrome[0x20]; 5640 5641 u8 reserved_1[0x40]; 5642 }; 5643 5644 enum 5645 { 5646 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5647 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5648 }; 5649 5650 struct mlx5_ifc_modify_tir_in_bits { 5651 u8 opcode[0x10]; 5652 u8 uid[0x10]; 5653 5654 u8 reserved_1[0x10]; 5655 u8 op_mod[0x10]; 5656 5657 u8 reserved_2[0x8]; 5658 u8 tirn[0x18]; 5659 5660 u8 reserved_3[0x20]; 5661 5662 u8 modify_bitmask[0x40]; 5663 5664 u8 reserved_4[0x40]; 5665 5666 struct mlx5_ifc_tirc_bits tir_context; 5667 }; 5668 5669 struct mlx5_ifc_modify_sq_out_bits { 5670 u8 status[0x8]; 5671 u8 reserved_0[0x18]; 5672 5673 u8 syndrome[0x20]; 5674 5675 u8 reserved_1[0x40]; 5676 }; 5677 5678 struct mlx5_ifc_modify_sq_in_bits { 5679 u8 opcode[0x10]; 5680 u8 uid[0x10]; 5681 5682 u8 reserved_1[0x10]; 5683 u8 op_mod[0x10]; 5684 5685 u8 sq_state[0x4]; 5686 u8 reserved_2[0x4]; 5687 u8 sqn[0x18]; 5688 5689 u8 reserved_3[0x20]; 5690 5691 u8 modify_bitmask[0x40]; 5692 5693 u8 reserved_4[0x40]; 5694 5695 struct mlx5_ifc_sqc_bits ctx; 5696 }; 5697 5698 struct mlx5_ifc_modify_scheduling_element_out_bits { 5699 u8 status[0x8]; 5700 u8 reserved_at_8[0x18]; 5701 5702 u8 syndrome[0x20]; 5703 5704 u8 reserved_at_40[0x1c0]; 5705 }; 5706 5707 enum { 5708 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5709 }; 5710 5711 enum { 5712 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5713 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5714 }; 5715 5716 struct mlx5_ifc_modify_scheduling_element_in_bits { 5717 u8 opcode[0x10]; 5718 u8 reserved_at_10[0x10]; 5719 5720 u8 reserved_at_20[0x10]; 5721 u8 op_mod[0x10]; 5722 5723 u8 scheduling_hierarchy[0x8]; 5724 u8 reserved_at_48[0x18]; 5725 5726 u8 scheduling_element_id[0x20]; 5727 5728 u8 reserved_at_80[0x20]; 5729 5730 u8 modify_bitmask[0x20]; 5731 5732 u8 reserved_at_c0[0x40]; 5733 5734 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5735 5736 u8 reserved_at_300[0x100]; 5737 }; 5738 5739 struct mlx5_ifc_modify_rqt_out_bits { 5740 u8 status[0x8]; 5741 u8 reserved_0[0x18]; 5742 5743 u8 syndrome[0x20]; 5744 5745 u8 reserved_1[0x40]; 5746 }; 5747 5748 struct mlx5_ifc_modify_rqt_in_bits { 5749 u8 opcode[0x10]; 5750 u8 uid[0x10]; 5751 5752 u8 reserved_1[0x10]; 5753 u8 op_mod[0x10]; 5754 5755 u8 reserved_2[0x8]; 5756 u8 rqtn[0x18]; 5757 5758 u8 reserved_3[0x20]; 5759 5760 u8 modify_bitmask[0x40]; 5761 5762 u8 reserved_4[0x40]; 5763 5764 struct mlx5_ifc_rqtc_bits ctx; 5765 }; 5766 5767 struct mlx5_ifc_modify_rq_out_bits { 5768 u8 status[0x8]; 5769 u8 reserved_0[0x18]; 5770 5771 u8 syndrome[0x20]; 5772 5773 u8 reserved_1[0x40]; 5774 }; 5775 5776 enum { 5777 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5778 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5779 }; 5780 5781 struct mlx5_ifc_modify_rq_in_bits { 5782 u8 opcode[0x10]; 5783 u8 uid[0x10]; 5784 5785 u8 reserved_1[0x10]; 5786 u8 op_mod[0x10]; 5787 5788 u8 rq_state[0x4]; 5789 u8 reserved_2[0x4]; 5790 u8 rqn[0x18]; 5791 5792 u8 reserved_3[0x20]; 5793 5794 u8 modify_bitmask[0x40]; 5795 5796 u8 reserved_4[0x40]; 5797 5798 struct mlx5_ifc_rqc_bits ctx; 5799 }; 5800 5801 struct mlx5_ifc_modify_rmp_out_bits { 5802 u8 status[0x8]; 5803 u8 reserved_0[0x18]; 5804 5805 u8 syndrome[0x20]; 5806 5807 u8 reserved_1[0x40]; 5808 }; 5809 5810 struct mlx5_ifc_rmp_bitmask_bits { 5811 u8 reserved[0x20]; 5812 5813 u8 reserved1[0x1f]; 5814 u8 lwm[0x1]; 5815 }; 5816 5817 struct mlx5_ifc_modify_rmp_in_bits { 5818 u8 opcode[0x10]; 5819 u8 uid[0x10]; 5820 5821 u8 reserved_1[0x10]; 5822 u8 op_mod[0x10]; 5823 5824 u8 rmp_state[0x4]; 5825 u8 reserved_2[0x4]; 5826 u8 rmpn[0x18]; 5827 5828 u8 reserved_3[0x20]; 5829 5830 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5831 5832 u8 reserved_4[0x40]; 5833 5834 struct mlx5_ifc_rmpc_bits ctx; 5835 }; 5836 5837 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5838 u8 status[0x8]; 5839 u8 reserved_0[0x18]; 5840 5841 u8 syndrome[0x20]; 5842 5843 u8 reserved_1[0x40]; 5844 }; 5845 5846 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5847 u8 reserved_0[0x14]; 5848 u8 disable_uc_local_lb[0x1]; 5849 u8 disable_mc_local_lb[0x1]; 5850 u8 node_guid[0x1]; 5851 u8 port_guid[0x1]; 5852 u8 min_wqe_inline_mode[0x1]; 5853 u8 mtu[0x1]; 5854 u8 change_event[0x1]; 5855 u8 promisc[0x1]; 5856 u8 permanent_address[0x1]; 5857 u8 addresses_list[0x1]; 5858 u8 roce_en[0x1]; 5859 u8 reserved_1[0x1]; 5860 }; 5861 5862 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5863 u8 opcode[0x10]; 5864 u8 reserved_0[0x10]; 5865 5866 u8 reserved_1[0x10]; 5867 u8 op_mod[0x10]; 5868 5869 u8 other_vport[0x1]; 5870 u8 reserved_2[0xf]; 5871 u8 vport_number[0x10]; 5872 5873 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5874 5875 u8 reserved_3[0x780]; 5876 5877 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5878 }; 5879 5880 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5881 u8 status[0x8]; 5882 u8 reserved_0[0x18]; 5883 5884 u8 syndrome[0x20]; 5885 5886 u8 reserved_1[0x40]; 5887 }; 5888 5889 struct mlx5_ifc_grh_bits { 5890 u8 ip_version[4]; 5891 u8 traffic_class[8]; 5892 u8 flow_label[20]; 5893 u8 payload_length[16]; 5894 u8 next_header[8]; 5895 u8 hop_limit[8]; 5896 u8 sgid[128]; 5897 u8 dgid[128]; 5898 }; 5899 5900 struct mlx5_ifc_bth_bits { 5901 u8 opcode[8]; 5902 u8 se[1]; 5903 u8 migreq[1]; 5904 u8 pad_count[2]; 5905 u8 tver[4]; 5906 u8 p_key[16]; 5907 u8 reserved8[8]; 5908 u8 dest_qp[24]; 5909 u8 ack_req[1]; 5910 u8 reserved7[7]; 5911 u8 psn[24]; 5912 }; 5913 5914 struct mlx5_ifc_aeth_bits { 5915 u8 syndrome[8]; 5916 u8 msn[24]; 5917 }; 5918 5919 struct mlx5_ifc_dceth_bits { 5920 u8 reserved0[8]; 5921 u8 session_id[24]; 5922 u8 reserved1[8]; 5923 u8 dci_dct[24]; 5924 }; 5925 5926 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5927 u8 opcode[0x10]; 5928 u8 reserved_0[0x10]; 5929 5930 u8 reserved_1[0x10]; 5931 u8 op_mod[0x10]; 5932 5933 u8 other_vport[0x1]; 5934 u8 reserved_2[0xb]; 5935 u8 port_num[0x4]; 5936 u8 vport_number[0x10]; 5937 5938 u8 reserved_3[0x20]; 5939 5940 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5941 }; 5942 5943 struct mlx5_ifc_modify_flow_table_out_bits { 5944 u8 status[0x8]; 5945 u8 reserved_at_8[0x18]; 5946 5947 u8 syndrome[0x20]; 5948 5949 u8 reserved_at_40[0x40]; 5950 }; 5951 5952 enum { 5953 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 5954 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 5955 }; 5956 5957 struct mlx5_ifc_modify_flow_table_in_bits { 5958 u8 opcode[0x10]; 5959 u8 reserved_at_10[0x10]; 5960 5961 u8 reserved_at_20[0x10]; 5962 u8 op_mod[0x10]; 5963 5964 u8 other_vport[0x1]; 5965 u8 reserved_at_41[0xf]; 5966 u8 vport_number[0x10]; 5967 5968 u8 reserved_at_60[0x10]; 5969 u8 modify_field_select[0x10]; 5970 5971 u8 table_type[0x8]; 5972 u8 reserved_at_88[0x18]; 5973 5974 u8 reserved_at_a0[0x8]; 5975 u8 table_id[0x18]; 5976 5977 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5978 }; 5979 5980 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5981 u8 status[0x8]; 5982 u8 reserved_0[0x18]; 5983 5984 u8 syndrome[0x20]; 5985 5986 u8 reserved_1[0x40]; 5987 }; 5988 5989 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5990 u8 reserved[0x1c]; 5991 u8 vport_cvlan_insert[0x1]; 5992 u8 vport_svlan_insert[0x1]; 5993 u8 vport_cvlan_strip[0x1]; 5994 u8 vport_svlan_strip[0x1]; 5995 }; 5996 5997 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5998 u8 opcode[0x10]; 5999 u8 reserved_0[0x10]; 6000 6001 u8 reserved_1[0x10]; 6002 u8 op_mod[0x10]; 6003 6004 u8 other_vport[0x1]; 6005 u8 reserved_2[0xf]; 6006 u8 vport_number[0x10]; 6007 6008 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6009 6010 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6011 }; 6012 6013 struct mlx5_ifc_modify_cq_out_bits { 6014 u8 status[0x8]; 6015 u8 reserved_0[0x18]; 6016 6017 u8 syndrome[0x20]; 6018 6019 u8 reserved_1[0x40]; 6020 }; 6021 6022 enum { 6023 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6024 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6025 }; 6026 6027 struct mlx5_ifc_modify_cq_in_bits { 6028 u8 opcode[0x10]; 6029 u8 uid[0x10]; 6030 6031 u8 reserved_1[0x10]; 6032 u8 op_mod[0x10]; 6033 6034 u8 reserved_2[0x8]; 6035 u8 cqn[0x18]; 6036 6037 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6038 6039 struct mlx5_ifc_cqc_bits cq_context; 6040 6041 u8 reserved_at_280[0x60]; 6042 6043 u8 cq_umem_valid[0x1]; 6044 u8 reserved_at_2e1[0x1f]; 6045 6046 u8 reserved_at_300[0x580]; 6047 6048 u8 pas[0][0x40]; 6049 }; 6050 6051 struct mlx5_ifc_modify_cong_status_out_bits { 6052 u8 status[0x8]; 6053 u8 reserved_0[0x18]; 6054 6055 u8 syndrome[0x20]; 6056 6057 u8 reserved_1[0x40]; 6058 }; 6059 6060 struct mlx5_ifc_modify_cong_status_in_bits { 6061 u8 opcode[0x10]; 6062 u8 reserved_0[0x10]; 6063 6064 u8 reserved_1[0x10]; 6065 u8 op_mod[0x10]; 6066 6067 u8 reserved_2[0x18]; 6068 u8 priority[0x4]; 6069 u8 cong_protocol[0x4]; 6070 6071 u8 enable[0x1]; 6072 u8 tag_enable[0x1]; 6073 u8 reserved_3[0x1e]; 6074 }; 6075 6076 struct mlx5_ifc_modify_cong_params_out_bits { 6077 u8 status[0x8]; 6078 u8 reserved_0[0x18]; 6079 6080 u8 syndrome[0x20]; 6081 6082 u8 reserved_1[0x40]; 6083 }; 6084 6085 struct mlx5_ifc_modify_cong_params_in_bits { 6086 u8 opcode[0x10]; 6087 u8 reserved_0[0x10]; 6088 6089 u8 reserved_1[0x10]; 6090 u8 op_mod[0x10]; 6091 6092 u8 reserved_2[0x1c]; 6093 u8 cong_protocol[0x4]; 6094 6095 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6096 6097 u8 reserved_3[0x80]; 6098 6099 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6100 }; 6101 6102 struct mlx5_ifc_manage_pages_out_bits { 6103 u8 status[0x8]; 6104 u8 reserved_0[0x18]; 6105 6106 u8 syndrome[0x20]; 6107 6108 u8 output_num_entries[0x20]; 6109 6110 u8 reserved_1[0x20]; 6111 6112 u8 pas[0][0x40]; 6113 }; 6114 6115 enum { 6116 MLX5_PAGES_CANT_GIVE = 0x0, 6117 MLX5_PAGES_GIVE = 0x1, 6118 MLX5_PAGES_TAKE = 0x2, 6119 }; 6120 6121 struct mlx5_ifc_manage_pages_in_bits { 6122 u8 opcode[0x10]; 6123 u8 reserved_0[0x10]; 6124 6125 u8 reserved_1[0x10]; 6126 u8 op_mod[0x10]; 6127 6128 u8 reserved_2[0x10]; 6129 u8 function_id[0x10]; 6130 6131 u8 input_num_entries[0x20]; 6132 6133 u8 pas[0][0x40]; 6134 }; 6135 6136 struct mlx5_ifc_mad_ifc_out_bits { 6137 u8 status[0x8]; 6138 u8 reserved_0[0x18]; 6139 6140 u8 syndrome[0x20]; 6141 6142 u8 reserved_1[0x40]; 6143 6144 u8 response_mad_packet[256][0x8]; 6145 }; 6146 6147 struct mlx5_ifc_mad_ifc_in_bits { 6148 u8 opcode[0x10]; 6149 u8 reserved_0[0x10]; 6150 6151 u8 reserved_1[0x10]; 6152 u8 op_mod[0x10]; 6153 6154 u8 remote_lid[0x10]; 6155 u8 reserved_2[0x8]; 6156 u8 port[0x8]; 6157 6158 u8 reserved_3[0x20]; 6159 6160 u8 mad[256][0x8]; 6161 }; 6162 6163 struct mlx5_ifc_init_hca_out_bits { 6164 u8 status[0x8]; 6165 u8 reserved_0[0x18]; 6166 6167 u8 syndrome[0x20]; 6168 6169 u8 reserved_1[0x40]; 6170 }; 6171 6172 enum { 6173 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 6174 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 6175 }; 6176 6177 struct mlx5_ifc_init_hca_in_bits { 6178 u8 opcode[0x10]; 6179 u8 reserved_0[0x10]; 6180 6181 u8 reserved_1[0x10]; 6182 u8 op_mod[0x10]; 6183 6184 u8 reserved_2[0x40]; 6185 }; 6186 6187 struct mlx5_ifc_init2rtr_qp_out_bits { 6188 u8 status[0x8]; 6189 u8 reserved_0[0x18]; 6190 6191 u8 syndrome[0x20]; 6192 6193 u8 reserved_1[0x40]; 6194 }; 6195 6196 struct mlx5_ifc_init2rtr_qp_in_bits { 6197 u8 opcode[0x10]; 6198 u8 uid[0x10]; 6199 6200 u8 reserved_1[0x10]; 6201 u8 op_mod[0x10]; 6202 6203 u8 reserved_2[0x8]; 6204 u8 qpn[0x18]; 6205 6206 u8 reserved_3[0x20]; 6207 6208 u8 opt_param_mask[0x20]; 6209 6210 u8 reserved_4[0x20]; 6211 6212 struct mlx5_ifc_qpc_bits qpc; 6213 6214 u8 reserved_5[0x80]; 6215 }; 6216 6217 struct mlx5_ifc_init2init_qp_out_bits { 6218 u8 status[0x8]; 6219 u8 reserved_0[0x18]; 6220 6221 u8 syndrome[0x20]; 6222 6223 u8 reserved_1[0x40]; 6224 }; 6225 6226 struct mlx5_ifc_init2init_qp_in_bits { 6227 u8 opcode[0x10]; 6228 u8 uid[0x10]; 6229 6230 u8 reserved_1[0x10]; 6231 u8 op_mod[0x10]; 6232 6233 u8 reserved_2[0x8]; 6234 u8 qpn[0x18]; 6235 6236 u8 reserved_3[0x20]; 6237 6238 u8 opt_param_mask[0x20]; 6239 6240 u8 reserved_4[0x20]; 6241 6242 struct mlx5_ifc_qpc_bits qpc; 6243 6244 u8 reserved_5[0x80]; 6245 }; 6246 6247 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6248 u8 status[0x8]; 6249 u8 reserved_0[0x18]; 6250 6251 u8 syndrome[0x20]; 6252 6253 u8 reserved_1[0x40]; 6254 6255 u8 packet_headers_log[128][0x8]; 6256 6257 u8 packet_syndrome[64][0x8]; 6258 }; 6259 6260 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6261 u8 opcode[0x10]; 6262 u8 reserved_0[0x10]; 6263 6264 u8 reserved_1[0x10]; 6265 u8 op_mod[0x10]; 6266 6267 u8 reserved_2[0x40]; 6268 }; 6269 6270 struct mlx5_ifc_encryption_key_obj_bits { 6271 u8 modify_field_select[0x40]; 6272 6273 u8 reserved_at_40[0x14]; 6274 u8 key_size[0x4]; 6275 u8 reserved_at_58[0x4]; 6276 u8 key_type[0x4]; 6277 6278 u8 reserved_at_60[0x8]; 6279 u8 pd[0x18]; 6280 6281 u8 reserved_at_80[0x180]; 6282 6283 u8 key[8][0x20]; 6284 6285 u8 reserved_at_300[0x500]; 6286 }; 6287 6288 struct mlx5_ifc_gen_eqe_in_bits { 6289 u8 opcode[0x10]; 6290 u8 reserved_0[0x10]; 6291 6292 u8 reserved_1[0x10]; 6293 u8 op_mod[0x10]; 6294 6295 u8 reserved_2[0x18]; 6296 u8 eq_number[0x8]; 6297 6298 u8 reserved_3[0x20]; 6299 6300 u8 eqe[64][0x8]; 6301 }; 6302 6303 struct mlx5_ifc_gen_eq_out_bits { 6304 u8 status[0x8]; 6305 u8 reserved_0[0x18]; 6306 6307 u8 syndrome[0x20]; 6308 6309 u8 reserved_1[0x40]; 6310 }; 6311 6312 struct mlx5_ifc_enable_hca_out_bits { 6313 u8 status[0x8]; 6314 u8 reserved_0[0x18]; 6315 6316 u8 syndrome[0x20]; 6317 6318 u8 reserved_1[0x20]; 6319 }; 6320 6321 struct mlx5_ifc_enable_hca_in_bits { 6322 u8 opcode[0x10]; 6323 u8 reserved_0[0x10]; 6324 6325 u8 reserved_1[0x10]; 6326 u8 op_mod[0x10]; 6327 6328 u8 reserved_2[0x10]; 6329 u8 function_id[0x10]; 6330 6331 u8 reserved_3[0x20]; 6332 }; 6333 6334 struct mlx5_ifc_drain_dct_out_bits { 6335 u8 status[0x8]; 6336 u8 reserved_0[0x18]; 6337 6338 u8 syndrome[0x20]; 6339 6340 u8 reserved_1[0x40]; 6341 }; 6342 6343 struct mlx5_ifc_drain_dct_in_bits { 6344 u8 opcode[0x10]; 6345 u8 uid[0x10]; 6346 6347 u8 reserved_1[0x10]; 6348 u8 op_mod[0x10]; 6349 6350 u8 reserved_2[0x8]; 6351 u8 dctn[0x18]; 6352 6353 u8 reserved_3[0x20]; 6354 }; 6355 6356 struct mlx5_ifc_disable_hca_out_bits { 6357 u8 status[0x8]; 6358 u8 reserved_0[0x18]; 6359 6360 u8 syndrome[0x20]; 6361 6362 u8 reserved_1[0x20]; 6363 }; 6364 6365 struct mlx5_ifc_disable_hca_in_bits { 6366 u8 opcode[0x10]; 6367 u8 reserved_0[0x10]; 6368 6369 u8 reserved_1[0x10]; 6370 u8 op_mod[0x10]; 6371 6372 u8 reserved_2[0x10]; 6373 u8 function_id[0x10]; 6374 6375 u8 reserved_3[0x20]; 6376 }; 6377 6378 struct mlx5_ifc_detach_from_mcg_out_bits { 6379 u8 status[0x8]; 6380 u8 reserved_0[0x18]; 6381 6382 u8 syndrome[0x20]; 6383 6384 u8 reserved_1[0x40]; 6385 }; 6386 6387 struct mlx5_ifc_detach_from_mcg_in_bits { 6388 u8 opcode[0x10]; 6389 u8 uid[0x10]; 6390 6391 u8 reserved_1[0x10]; 6392 u8 op_mod[0x10]; 6393 6394 u8 reserved_2[0x8]; 6395 u8 qpn[0x18]; 6396 6397 u8 reserved_3[0x20]; 6398 6399 u8 multicast_gid[16][0x8]; 6400 }; 6401 6402 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6403 u8 status[0x8]; 6404 u8 reserved_0[0x18]; 6405 6406 u8 syndrome[0x20]; 6407 6408 u8 reserved_1[0x40]; 6409 }; 6410 6411 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6412 u8 opcode[0x10]; 6413 u8 uid[0x10]; 6414 6415 u8 reserved_1[0x10]; 6416 u8 op_mod[0x10]; 6417 6418 u8 reserved_2[0x8]; 6419 u8 xrc_srqn[0x18]; 6420 6421 u8 reserved_3[0x20]; 6422 }; 6423 6424 struct mlx5_ifc_destroy_tis_out_bits { 6425 u8 status[0x8]; 6426 u8 reserved_0[0x18]; 6427 6428 u8 syndrome[0x20]; 6429 6430 u8 reserved_1[0x40]; 6431 }; 6432 6433 struct mlx5_ifc_destroy_tis_in_bits { 6434 u8 opcode[0x10]; 6435 u8 uid[0x10]; 6436 6437 u8 reserved_1[0x10]; 6438 u8 op_mod[0x10]; 6439 6440 u8 reserved_2[0x8]; 6441 u8 tisn[0x18]; 6442 6443 u8 reserved_3[0x20]; 6444 }; 6445 6446 struct mlx5_ifc_destroy_tir_out_bits { 6447 u8 status[0x8]; 6448 u8 reserved_0[0x18]; 6449 6450 u8 syndrome[0x20]; 6451 6452 u8 reserved_1[0x40]; 6453 }; 6454 6455 struct mlx5_ifc_destroy_tir_in_bits { 6456 u8 opcode[0x10]; 6457 u8 uid[0x10]; 6458 6459 u8 reserved_1[0x10]; 6460 u8 op_mod[0x10]; 6461 6462 u8 reserved_2[0x8]; 6463 u8 tirn[0x18]; 6464 6465 u8 reserved_3[0x20]; 6466 }; 6467 6468 struct mlx5_ifc_destroy_srq_out_bits { 6469 u8 status[0x8]; 6470 u8 reserved_0[0x18]; 6471 6472 u8 syndrome[0x20]; 6473 6474 u8 reserved_1[0x40]; 6475 }; 6476 6477 struct mlx5_ifc_destroy_srq_in_bits { 6478 u8 opcode[0x10]; 6479 u8 uid[0x10]; 6480 6481 u8 reserved_1[0x10]; 6482 u8 op_mod[0x10]; 6483 6484 u8 reserved_2[0x8]; 6485 u8 srqn[0x18]; 6486 6487 u8 reserved_3[0x20]; 6488 }; 6489 6490 struct mlx5_ifc_destroy_sq_out_bits { 6491 u8 status[0x8]; 6492 u8 reserved_0[0x18]; 6493 6494 u8 syndrome[0x20]; 6495 6496 u8 reserved_1[0x40]; 6497 }; 6498 6499 struct mlx5_ifc_destroy_sq_in_bits { 6500 u8 opcode[0x10]; 6501 u8 uid[0x10]; 6502 6503 u8 reserved_1[0x10]; 6504 u8 op_mod[0x10]; 6505 6506 u8 reserved_2[0x8]; 6507 u8 sqn[0x18]; 6508 6509 u8 reserved_3[0x20]; 6510 }; 6511 6512 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6513 u8 status[0x8]; 6514 u8 reserved_at_8[0x18]; 6515 6516 u8 syndrome[0x20]; 6517 6518 u8 reserved_at_40[0x1c0]; 6519 }; 6520 6521 enum { 6522 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6523 }; 6524 6525 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6526 u8 opcode[0x10]; 6527 u8 reserved_at_10[0x10]; 6528 6529 u8 reserved_at_20[0x10]; 6530 u8 op_mod[0x10]; 6531 6532 u8 scheduling_hierarchy[0x8]; 6533 u8 reserved_at_48[0x18]; 6534 6535 u8 scheduling_element_id[0x20]; 6536 6537 u8 reserved_at_80[0x180]; 6538 }; 6539 6540 struct mlx5_ifc_destroy_rqt_out_bits { 6541 u8 status[0x8]; 6542 u8 reserved_0[0x18]; 6543 6544 u8 syndrome[0x20]; 6545 6546 u8 reserved_1[0x40]; 6547 }; 6548 6549 struct mlx5_ifc_destroy_rqt_in_bits { 6550 u8 opcode[0x10]; 6551 u8 uid[0x10]; 6552 6553 u8 reserved_1[0x10]; 6554 u8 op_mod[0x10]; 6555 6556 u8 reserved_2[0x8]; 6557 u8 rqtn[0x18]; 6558 6559 u8 reserved_3[0x20]; 6560 }; 6561 6562 struct mlx5_ifc_destroy_rq_out_bits { 6563 u8 status[0x8]; 6564 u8 reserved_0[0x18]; 6565 6566 u8 syndrome[0x20]; 6567 6568 u8 reserved_1[0x40]; 6569 }; 6570 6571 struct mlx5_ifc_destroy_rq_in_bits { 6572 u8 opcode[0x10]; 6573 u8 uid[0x10]; 6574 6575 u8 reserved_1[0x10]; 6576 u8 op_mod[0x10]; 6577 6578 u8 reserved_2[0x8]; 6579 u8 rqn[0x18]; 6580 6581 u8 reserved_3[0x20]; 6582 }; 6583 6584 struct mlx5_ifc_destroy_rmp_out_bits { 6585 u8 status[0x8]; 6586 u8 reserved_0[0x18]; 6587 6588 u8 syndrome[0x20]; 6589 6590 u8 reserved_1[0x40]; 6591 }; 6592 6593 struct mlx5_ifc_destroy_rmp_in_bits { 6594 u8 opcode[0x10]; 6595 u8 reserved_0[0x10]; 6596 6597 u8 reserved_1[0x10]; 6598 u8 op_mod[0x10]; 6599 6600 u8 reserved_2[0x8]; 6601 u8 rmpn[0x18]; 6602 6603 u8 reserved_3[0x20]; 6604 }; 6605 6606 struct mlx5_ifc_destroy_qp_out_bits { 6607 u8 status[0x8]; 6608 u8 reserved_0[0x18]; 6609 6610 u8 syndrome[0x20]; 6611 6612 u8 reserved_1[0x40]; 6613 }; 6614 6615 struct mlx5_ifc_destroy_qp_in_bits { 6616 u8 opcode[0x10]; 6617 u8 uid[0x10]; 6618 6619 u8 reserved_1[0x10]; 6620 u8 op_mod[0x10]; 6621 6622 u8 reserved_2[0x8]; 6623 u8 qpn[0x18]; 6624 6625 u8 reserved_3[0x20]; 6626 }; 6627 6628 struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6629 u8 status[0x8]; 6630 u8 reserved_at_8[0x18]; 6631 6632 u8 syndrome[0x20]; 6633 6634 u8 reserved_at_40[0x1c0]; 6635 }; 6636 6637 struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6638 u8 opcode[0x10]; 6639 u8 reserved_at_10[0x10]; 6640 6641 u8 reserved_at_20[0x10]; 6642 u8 op_mod[0x10]; 6643 6644 u8 reserved_at_40[0x20]; 6645 6646 u8 reserved_at_60[0x10]; 6647 u8 qos_para_vport_number[0x10]; 6648 6649 u8 reserved_at_80[0x180]; 6650 }; 6651 6652 struct mlx5_ifc_destroy_psv_out_bits { 6653 u8 status[0x8]; 6654 u8 reserved_0[0x18]; 6655 6656 u8 syndrome[0x20]; 6657 6658 u8 reserved_1[0x40]; 6659 }; 6660 6661 struct mlx5_ifc_destroy_psv_in_bits { 6662 u8 opcode[0x10]; 6663 u8 reserved_0[0x10]; 6664 6665 u8 reserved_1[0x10]; 6666 u8 op_mod[0x10]; 6667 6668 u8 reserved_2[0x8]; 6669 u8 psvn[0x18]; 6670 6671 u8 reserved_3[0x20]; 6672 }; 6673 6674 struct mlx5_ifc_destroy_mkey_out_bits { 6675 u8 status[0x8]; 6676 u8 reserved_0[0x18]; 6677 6678 u8 syndrome[0x20]; 6679 6680 u8 reserved_1[0x40]; 6681 }; 6682 6683 struct mlx5_ifc_destroy_mkey_in_bits { 6684 u8 opcode[0x10]; 6685 u8 reserved_0[0x10]; 6686 6687 u8 reserved_1[0x10]; 6688 u8 op_mod[0x10]; 6689 6690 u8 reserved_2[0x8]; 6691 u8 mkey_index[0x18]; 6692 6693 u8 reserved_3[0x20]; 6694 }; 6695 6696 struct mlx5_ifc_destroy_flow_table_out_bits { 6697 u8 status[0x8]; 6698 u8 reserved_0[0x18]; 6699 6700 u8 syndrome[0x20]; 6701 6702 u8 reserved_1[0x40]; 6703 }; 6704 6705 struct mlx5_ifc_destroy_flow_table_in_bits { 6706 u8 opcode[0x10]; 6707 u8 reserved_0[0x10]; 6708 6709 u8 reserved_1[0x10]; 6710 u8 op_mod[0x10]; 6711 6712 u8 other_vport[0x1]; 6713 u8 reserved_2[0xf]; 6714 u8 vport_number[0x10]; 6715 6716 u8 reserved_3[0x20]; 6717 6718 u8 table_type[0x8]; 6719 u8 reserved_4[0x18]; 6720 6721 u8 reserved_5[0x8]; 6722 u8 table_id[0x18]; 6723 6724 u8 reserved_6[0x140]; 6725 }; 6726 6727 struct mlx5_ifc_destroy_flow_group_out_bits { 6728 u8 status[0x8]; 6729 u8 reserved_0[0x18]; 6730 6731 u8 syndrome[0x20]; 6732 6733 u8 reserved_1[0x40]; 6734 }; 6735 6736 struct mlx5_ifc_destroy_flow_group_in_bits { 6737 u8 opcode[0x10]; 6738 u8 reserved_0[0x10]; 6739 6740 u8 reserved_1[0x10]; 6741 u8 op_mod[0x10]; 6742 6743 u8 other_vport[0x1]; 6744 u8 reserved_2[0xf]; 6745 u8 vport_number[0x10]; 6746 6747 u8 reserved_3[0x20]; 6748 6749 u8 table_type[0x8]; 6750 u8 reserved_4[0x18]; 6751 6752 u8 reserved_5[0x8]; 6753 u8 table_id[0x18]; 6754 6755 u8 group_id[0x20]; 6756 6757 u8 reserved_6[0x120]; 6758 }; 6759 6760 struct mlx5_ifc_destroy_encryption_key_out_bits { 6761 u8 status[0x8]; 6762 u8 reserved_at_8[0x18]; 6763 6764 u8 syndrome[0x20]; 6765 6766 u8 reserved_at_40[0x40]; 6767 }; 6768 6769 struct mlx5_ifc_destroy_encryption_key_in_bits { 6770 u8 opcode[0x10]; 6771 u8 reserved_at_10[0x10]; 6772 6773 u8 reserved_at_20[0x10]; 6774 u8 obj_type[0x10]; 6775 6776 u8 obj_id[0x20]; 6777 6778 u8 reserved_at_60[0x20]; 6779 }; 6780 6781 struct mlx5_ifc_destroy_eq_out_bits { 6782 u8 status[0x8]; 6783 u8 reserved_0[0x18]; 6784 6785 u8 syndrome[0x20]; 6786 6787 u8 reserved_1[0x40]; 6788 }; 6789 6790 struct mlx5_ifc_destroy_eq_in_bits { 6791 u8 opcode[0x10]; 6792 u8 reserved_0[0x10]; 6793 6794 u8 reserved_1[0x10]; 6795 u8 op_mod[0x10]; 6796 6797 u8 reserved_2[0x18]; 6798 u8 eq_number[0x8]; 6799 6800 u8 reserved_3[0x20]; 6801 }; 6802 6803 struct mlx5_ifc_destroy_dct_out_bits { 6804 u8 status[0x8]; 6805 u8 reserved_0[0x18]; 6806 6807 u8 syndrome[0x20]; 6808 6809 u8 reserved_1[0x40]; 6810 }; 6811 6812 struct mlx5_ifc_destroy_dct_in_bits { 6813 u8 opcode[0x10]; 6814 u8 uid[0x10]; 6815 6816 u8 reserved_1[0x10]; 6817 u8 op_mod[0x10]; 6818 6819 u8 reserved_2[0x8]; 6820 u8 dctn[0x18]; 6821 6822 u8 reserved_3[0x20]; 6823 }; 6824 6825 struct mlx5_ifc_destroy_cq_out_bits { 6826 u8 status[0x8]; 6827 u8 reserved_0[0x18]; 6828 6829 u8 syndrome[0x20]; 6830 6831 u8 reserved_1[0x40]; 6832 }; 6833 6834 struct mlx5_ifc_destroy_cq_in_bits { 6835 u8 opcode[0x10]; 6836 u8 uid[0x10]; 6837 6838 u8 reserved_1[0x10]; 6839 u8 op_mod[0x10]; 6840 6841 u8 reserved_2[0x8]; 6842 u8 cqn[0x18]; 6843 6844 u8 reserved_3[0x20]; 6845 }; 6846 6847 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6848 u8 status[0x8]; 6849 u8 reserved_0[0x18]; 6850 6851 u8 syndrome[0x20]; 6852 6853 u8 reserved_1[0x40]; 6854 }; 6855 6856 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6857 u8 opcode[0x10]; 6858 u8 reserved_0[0x10]; 6859 6860 u8 reserved_1[0x10]; 6861 u8 op_mod[0x10]; 6862 6863 u8 reserved_2[0x20]; 6864 6865 u8 reserved_3[0x10]; 6866 u8 vxlan_udp_port[0x10]; 6867 }; 6868 6869 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6870 u8 status[0x8]; 6871 u8 reserved_0[0x18]; 6872 6873 u8 syndrome[0x20]; 6874 6875 u8 reserved_1[0x40]; 6876 }; 6877 6878 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6879 u8 opcode[0x10]; 6880 u8 reserved_0[0x10]; 6881 6882 u8 reserved_1[0x10]; 6883 u8 op_mod[0x10]; 6884 6885 u8 reserved_2[0x60]; 6886 6887 u8 reserved_3[0x8]; 6888 u8 table_index[0x18]; 6889 6890 u8 reserved_4[0x140]; 6891 }; 6892 6893 struct mlx5_ifc_delete_fte_out_bits { 6894 u8 status[0x8]; 6895 u8 reserved_0[0x18]; 6896 6897 u8 syndrome[0x20]; 6898 6899 u8 reserved_1[0x40]; 6900 }; 6901 6902 struct mlx5_ifc_delete_fte_in_bits { 6903 u8 opcode[0x10]; 6904 u8 reserved_0[0x10]; 6905 6906 u8 reserved_1[0x10]; 6907 u8 op_mod[0x10]; 6908 6909 u8 other_vport[0x1]; 6910 u8 reserved_2[0xf]; 6911 u8 vport_number[0x10]; 6912 6913 u8 reserved_3[0x20]; 6914 6915 u8 table_type[0x8]; 6916 u8 reserved_4[0x18]; 6917 6918 u8 reserved_5[0x8]; 6919 u8 table_id[0x18]; 6920 6921 u8 reserved_6[0x40]; 6922 6923 u8 flow_index[0x20]; 6924 6925 u8 reserved_7[0xe0]; 6926 }; 6927 6928 struct mlx5_ifc_dealloc_xrcd_out_bits { 6929 u8 status[0x8]; 6930 u8 reserved_0[0x18]; 6931 6932 u8 syndrome[0x20]; 6933 6934 u8 reserved_1[0x40]; 6935 }; 6936 6937 struct mlx5_ifc_dealloc_xrcd_in_bits { 6938 u8 opcode[0x10]; 6939 u8 uid[0x10]; 6940 6941 u8 reserved_1[0x10]; 6942 u8 op_mod[0x10]; 6943 6944 u8 reserved_2[0x8]; 6945 u8 xrcd[0x18]; 6946 6947 u8 reserved_3[0x20]; 6948 }; 6949 6950 struct mlx5_ifc_dealloc_uar_out_bits { 6951 u8 status[0x8]; 6952 u8 reserved_0[0x18]; 6953 6954 u8 syndrome[0x20]; 6955 6956 u8 reserved_1[0x40]; 6957 }; 6958 6959 struct mlx5_ifc_dealloc_uar_in_bits { 6960 u8 opcode[0x10]; 6961 u8 reserved_0[0x10]; 6962 6963 u8 reserved_1[0x10]; 6964 u8 op_mod[0x10]; 6965 6966 u8 reserved_2[0x8]; 6967 u8 uar[0x18]; 6968 6969 u8 reserved_3[0x20]; 6970 }; 6971 6972 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6973 u8 status[0x8]; 6974 u8 reserved_0[0x18]; 6975 6976 u8 syndrome[0x20]; 6977 6978 u8 reserved_1[0x40]; 6979 }; 6980 6981 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6982 u8 opcode[0x10]; 6983 u8 uid[0x10]; 6984 6985 u8 reserved_1[0x10]; 6986 u8 op_mod[0x10]; 6987 6988 u8 reserved_2[0x8]; 6989 u8 transport_domain[0x18]; 6990 6991 u8 reserved_3[0x20]; 6992 }; 6993 6994 struct mlx5_ifc_dealloc_q_counter_out_bits { 6995 u8 status[0x8]; 6996 u8 reserved_0[0x18]; 6997 6998 u8 syndrome[0x20]; 6999 7000 u8 reserved_1[0x40]; 7001 }; 7002 7003 struct mlx5_ifc_counter_id_bits { 7004 u8 reserved[0x10]; 7005 u8 counter_id[0x10]; 7006 }; 7007 7008 struct mlx5_ifc_diagnostic_params_context_bits { 7009 u8 num_of_counters[0x10]; 7010 u8 reserved_2[0x8]; 7011 u8 log_num_of_samples[0x8]; 7012 7013 u8 single[0x1]; 7014 u8 repetitive[0x1]; 7015 u8 sync[0x1]; 7016 u8 clear[0x1]; 7017 u8 on_demand[0x1]; 7018 u8 enable[0x1]; 7019 u8 reserved_3[0x12]; 7020 u8 log_sample_period[0x8]; 7021 7022 u8 reserved_4[0x80]; 7023 7024 struct mlx5_ifc_counter_id_bits counter_id[0]; 7025 }; 7026 7027 struct mlx5_ifc_set_diagnostic_params_in_bits { 7028 u8 opcode[0x10]; 7029 u8 reserved_0[0x10]; 7030 7031 u8 reserved_1[0x10]; 7032 u8 op_mod[0x10]; 7033 7034 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 7035 }; 7036 7037 struct mlx5_ifc_set_diagnostic_params_out_bits { 7038 u8 status[0x8]; 7039 u8 reserved_0[0x18]; 7040 7041 u8 syndrome[0x20]; 7042 7043 u8 reserved_1[0x40]; 7044 }; 7045 7046 struct mlx5_ifc_query_diagnostic_counters_in_bits { 7047 u8 opcode[0x10]; 7048 u8 reserved_0[0x10]; 7049 7050 u8 reserved_1[0x10]; 7051 u8 op_mod[0x10]; 7052 7053 u8 num_of_samples[0x10]; 7054 u8 sample_index[0x10]; 7055 7056 u8 reserved_2[0x20]; 7057 }; 7058 7059 struct mlx5_ifc_diagnostic_counter_bits { 7060 u8 counter_id[0x10]; 7061 u8 sample_id[0x10]; 7062 7063 u8 time_stamp_31_0[0x20]; 7064 7065 u8 counter_value_h[0x20]; 7066 7067 u8 counter_value_l[0x20]; 7068 }; 7069 7070 struct mlx5_ifc_query_diagnostic_counters_out_bits { 7071 u8 status[0x8]; 7072 u8 reserved_0[0x18]; 7073 7074 u8 syndrome[0x20]; 7075 7076 u8 reserved_1[0x40]; 7077 7078 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 7079 }; 7080 7081 struct mlx5_ifc_dealloc_q_counter_in_bits { 7082 u8 opcode[0x10]; 7083 u8 reserved_0[0x10]; 7084 7085 u8 reserved_1[0x10]; 7086 u8 op_mod[0x10]; 7087 7088 u8 reserved_2[0x18]; 7089 u8 counter_set_id[0x8]; 7090 7091 u8 reserved_3[0x20]; 7092 }; 7093 7094 struct mlx5_ifc_dealloc_pd_out_bits { 7095 u8 status[0x8]; 7096 u8 reserved_0[0x18]; 7097 7098 u8 syndrome[0x20]; 7099 7100 u8 reserved_1[0x40]; 7101 }; 7102 7103 struct mlx5_ifc_dealloc_pd_in_bits { 7104 u8 opcode[0x10]; 7105 u8 uid[0x10]; 7106 7107 u8 reserved_1[0x10]; 7108 u8 op_mod[0x10]; 7109 7110 u8 reserved_2[0x8]; 7111 u8 pd[0x18]; 7112 7113 u8 reserved_3[0x20]; 7114 }; 7115 7116 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7117 u8 status[0x8]; 7118 u8 reserved_0[0x18]; 7119 7120 u8 syndrome[0x20]; 7121 7122 u8 reserved_1[0x40]; 7123 }; 7124 7125 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7126 u8 opcode[0x10]; 7127 u8 reserved_0[0x10]; 7128 7129 u8 reserved_1[0x10]; 7130 u8 op_mod[0x10]; 7131 7132 u8 reserved_2[0x10]; 7133 u8 flow_counter_id[0x10]; 7134 7135 u8 reserved_3[0x20]; 7136 }; 7137 7138 struct mlx5_ifc_create_xrq_out_bits { 7139 u8 status[0x8]; 7140 u8 reserved_at_8[0x18]; 7141 7142 u8 syndrome[0x20]; 7143 7144 u8 reserved_at_40[0x8]; 7145 u8 xrqn[0x18]; 7146 7147 u8 reserved_at_60[0x20]; 7148 }; 7149 7150 struct mlx5_ifc_create_xrq_in_bits { 7151 u8 opcode[0x10]; 7152 u8 uid[0x10]; 7153 7154 u8 reserved_at_20[0x10]; 7155 u8 op_mod[0x10]; 7156 7157 u8 reserved_at_40[0x40]; 7158 7159 struct mlx5_ifc_xrqc_bits xrq_context; 7160 }; 7161 7162 struct mlx5_ifc_deactivate_tracer_out_bits { 7163 u8 status[0x8]; 7164 u8 reserved_0[0x18]; 7165 7166 u8 syndrome[0x20]; 7167 7168 u8 reserved_1[0x40]; 7169 }; 7170 7171 struct mlx5_ifc_deactivate_tracer_in_bits { 7172 u8 opcode[0x10]; 7173 u8 reserved_0[0x10]; 7174 7175 u8 reserved_1[0x10]; 7176 u8 op_mod[0x10]; 7177 7178 u8 mkey[0x20]; 7179 7180 u8 reserved_2[0x20]; 7181 }; 7182 7183 struct mlx5_ifc_create_xrc_srq_out_bits { 7184 u8 status[0x8]; 7185 u8 reserved_0[0x18]; 7186 7187 u8 syndrome[0x20]; 7188 7189 u8 reserved_1[0x8]; 7190 u8 xrc_srqn[0x18]; 7191 7192 u8 reserved_2[0x20]; 7193 }; 7194 7195 struct mlx5_ifc_create_xrc_srq_in_bits { 7196 u8 opcode[0x10]; 7197 u8 uid[0x10]; 7198 7199 u8 reserved_1[0x10]; 7200 u8 op_mod[0x10]; 7201 7202 u8 reserved_2[0x40]; 7203 7204 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7205 7206 u8 reserved_at_280[0x60]; 7207 7208 u8 xrc_srq_umem_valid[0x1]; 7209 u8 reserved_at_2e1[0x1f]; 7210 7211 u8 reserved_at_300[0x580]; 7212 7213 u8 pas[0][0x40]; 7214 }; 7215 7216 struct mlx5_ifc_create_tis_out_bits { 7217 u8 status[0x8]; 7218 u8 reserved_0[0x18]; 7219 7220 u8 syndrome[0x20]; 7221 7222 u8 reserved_1[0x8]; 7223 u8 tisn[0x18]; 7224 7225 u8 reserved_2[0x20]; 7226 }; 7227 7228 struct mlx5_ifc_create_tis_in_bits { 7229 u8 opcode[0x10]; 7230 u8 uid[0x10]; 7231 7232 u8 reserved_1[0x10]; 7233 u8 op_mod[0x10]; 7234 7235 u8 reserved_2[0xc0]; 7236 7237 struct mlx5_ifc_tisc_bits ctx; 7238 }; 7239 7240 struct mlx5_ifc_create_tir_out_bits { 7241 u8 status[0x8]; 7242 u8 reserved_0[0x18]; 7243 7244 u8 syndrome[0x20]; 7245 7246 u8 reserved_1[0x8]; 7247 u8 tirn[0x18]; 7248 7249 u8 reserved_2[0x20]; 7250 }; 7251 7252 struct mlx5_ifc_create_tir_in_bits { 7253 u8 opcode[0x10]; 7254 u8 uid[0x10]; 7255 7256 u8 reserved_1[0x10]; 7257 u8 op_mod[0x10]; 7258 7259 u8 reserved_2[0xc0]; 7260 7261 struct mlx5_ifc_tirc_bits tir_context; 7262 }; 7263 7264 struct mlx5_ifc_create_srq_out_bits { 7265 u8 status[0x8]; 7266 u8 reserved_0[0x18]; 7267 7268 u8 syndrome[0x20]; 7269 7270 u8 reserved_1[0x8]; 7271 u8 srqn[0x18]; 7272 7273 u8 reserved_2[0x20]; 7274 }; 7275 7276 struct mlx5_ifc_create_srq_in_bits { 7277 u8 opcode[0x10]; 7278 u8 uid[0x10]; 7279 7280 u8 reserved_1[0x10]; 7281 u8 op_mod[0x10]; 7282 7283 u8 reserved_2[0x40]; 7284 7285 struct mlx5_ifc_srqc_bits srq_context_entry; 7286 7287 u8 reserved_3[0x600]; 7288 7289 u8 pas[0][0x40]; 7290 }; 7291 7292 struct mlx5_ifc_create_sq_out_bits { 7293 u8 status[0x8]; 7294 u8 reserved_0[0x18]; 7295 7296 u8 syndrome[0x20]; 7297 7298 u8 reserved_1[0x8]; 7299 u8 sqn[0x18]; 7300 7301 u8 reserved_2[0x20]; 7302 }; 7303 7304 struct mlx5_ifc_create_sq_in_bits { 7305 u8 opcode[0x10]; 7306 u8 uid[0x10]; 7307 7308 u8 reserved_1[0x10]; 7309 u8 op_mod[0x10]; 7310 7311 u8 reserved_2[0xc0]; 7312 7313 struct mlx5_ifc_sqc_bits ctx; 7314 }; 7315 7316 struct mlx5_ifc_create_scheduling_element_out_bits { 7317 u8 status[0x8]; 7318 u8 reserved_at_8[0x18]; 7319 7320 u8 syndrome[0x20]; 7321 7322 u8 reserved_at_40[0x40]; 7323 7324 u8 scheduling_element_id[0x20]; 7325 7326 u8 reserved_at_a0[0x160]; 7327 }; 7328 7329 enum { 7330 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 7331 }; 7332 7333 struct mlx5_ifc_create_scheduling_element_in_bits { 7334 u8 opcode[0x10]; 7335 u8 reserved_at_10[0x10]; 7336 7337 u8 reserved_at_20[0x10]; 7338 u8 op_mod[0x10]; 7339 7340 u8 scheduling_hierarchy[0x8]; 7341 u8 reserved_at_48[0x18]; 7342 7343 u8 reserved_at_60[0xa0]; 7344 7345 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7346 7347 u8 reserved_at_300[0x100]; 7348 }; 7349 7350 struct mlx5_ifc_create_rqt_out_bits { 7351 u8 status[0x8]; 7352 u8 reserved_0[0x18]; 7353 7354 u8 syndrome[0x20]; 7355 7356 u8 reserved_1[0x8]; 7357 u8 rqtn[0x18]; 7358 7359 u8 reserved_2[0x20]; 7360 }; 7361 7362 struct mlx5_ifc_create_rqt_in_bits { 7363 u8 opcode[0x10]; 7364 u8 uid[0x10]; 7365 7366 u8 reserved_1[0x10]; 7367 u8 op_mod[0x10]; 7368 7369 u8 reserved_2[0xc0]; 7370 7371 struct mlx5_ifc_rqtc_bits rqt_context; 7372 }; 7373 7374 struct mlx5_ifc_create_rq_out_bits { 7375 u8 status[0x8]; 7376 u8 reserved_0[0x18]; 7377 7378 u8 syndrome[0x20]; 7379 7380 u8 reserved_1[0x8]; 7381 u8 rqn[0x18]; 7382 7383 u8 reserved_2[0x20]; 7384 }; 7385 7386 struct mlx5_ifc_create_rq_in_bits { 7387 u8 opcode[0x10]; 7388 u8 uid[0x10]; 7389 7390 u8 reserved_1[0x10]; 7391 u8 op_mod[0x10]; 7392 7393 u8 reserved_2[0xc0]; 7394 7395 struct mlx5_ifc_rqc_bits ctx; 7396 }; 7397 7398 struct mlx5_ifc_create_rmp_out_bits { 7399 u8 status[0x8]; 7400 u8 reserved_0[0x18]; 7401 7402 u8 syndrome[0x20]; 7403 7404 u8 reserved_1[0x8]; 7405 u8 rmpn[0x18]; 7406 7407 u8 reserved_2[0x20]; 7408 }; 7409 7410 struct mlx5_ifc_create_rmp_in_bits { 7411 u8 opcode[0x10]; 7412 u8 uid[0x10]; 7413 7414 u8 reserved_1[0x10]; 7415 u8 op_mod[0x10]; 7416 7417 u8 reserved_2[0xc0]; 7418 7419 struct mlx5_ifc_rmpc_bits ctx; 7420 }; 7421 7422 struct mlx5_ifc_create_qp_out_bits { 7423 u8 status[0x8]; 7424 u8 reserved_0[0x18]; 7425 7426 u8 syndrome[0x20]; 7427 7428 u8 reserved_1[0x8]; 7429 u8 qpn[0x18]; 7430 7431 u8 reserved_2[0x20]; 7432 }; 7433 7434 struct mlx5_ifc_create_qp_in_bits { 7435 u8 opcode[0x10]; 7436 u8 uid[0x10]; 7437 7438 u8 reserved_1[0x10]; 7439 u8 op_mod[0x10]; 7440 7441 u8 reserved_2[0x8]; 7442 u8 input_qpn[0x18]; 7443 7444 u8 reserved_3[0x20]; 7445 7446 u8 opt_param_mask[0x20]; 7447 7448 u8 reserved_4[0x20]; 7449 7450 struct mlx5_ifc_qpc_bits qpc; 7451 7452 u8 reserved_at_800[0x60]; 7453 7454 u8 wq_umem_valid[0x1]; 7455 u8 reserved_at_861[0x1f]; 7456 7457 u8 pas[0][0x40]; 7458 }; 7459 7460 struct mlx5_ifc_create_qos_para_vport_out_bits { 7461 u8 status[0x8]; 7462 u8 reserved_at_8[0x18]; 7463 7464 u8 syndrome[0x20]; 7465 7466 u8 reserved_at_40[0x20]; 7467 7468 u8 reserved_at_60[0x10]; 7469 u8 qos_para_vport_number[0x10]; 7470 7471 u8 reserved_at_80[0x180]; 7472 }; 7473 7474 struct mlx5_ifc_create_qos_para_vport_in_bits { 7475 u8 opcode[0x10]; 7476 u8 reserved_at_10[0x10]; 7477 7478 u8 reserved_at_20[0x10]; 7479 u8 op_mod[0x10]; 7480 7481 u8 reserved_at_40[0x1c0]; 7482 }; 7483 7484 struct mlx5_ifc_create_psv_out_bits { 7485 u8 status[0x8]; 7486 u8 reserved_0[0x18]; 7487 7488 u8 syndrome[0x20]; 7489 7490 u8 reserved_1[0x40]; 7491 7492 u8 reserved_2[0x8]; 7493 u8 psv0_index[0x18]; 7494 7495 u8 reserved_3[0x8]; 7496 u8 psv1_index[0x18]; 7497 7498 u8 reserved_4[0x8]; 7499 u8 psv2_index[0x18]; 7500 7501 u8 reserved_5[0x8]; 7502 u8 psv3_index[0x18]; 7503 }; 7504 7505 struct mlx5_ifc_create_psv_in_bits { 7506 u8 opcode[0x10]; 7507 u8 reserved_0[0x10]; 7508 7509 u8 reserved_1[0x10]; 7510 u8 op_mod[0x10]; 7511 7512 u8 num_psv[0x4]; 7513 u8 reserved_2[0x4]; 7514 u8 pd[0x18]; 7515 7516 u8 reserved_3[0x20]; 7517 }; 7518 7519 struct mlx5_ifc_create_mkey_out_bits { 7520 u8 status[0x8]; 7521 u8 reserved_0[0x18]; 7522 7523 u8 syndrome[0x20]; 7524 7525 u8 reserved_1[0x8]; 7526 u8 mkey_index[0x18]; 7527 7528 u8 reserved_2[0x20]; 7529 }; 7530 7531 struct mlx5_ifc_create_mkey_in_bits { 7532 u8 opcode[0x10]; 7533 u8 reserved_0[0x10]; 7534 7535 u8 reserved_1[0x10]; 7536 u8 op_mod[0x10]; 7537 7538 u8 reserved_2[0x20]; 7539 7540 u8 pg_access[0x1]; 7541 u8 mkey_umem_valid[0x1]; 7542 u8 reserved_at_62[0x1e]; 7543 7544 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7545 7546 u8 reserved_4[0x80]; 7547 7548 u8 translations_octword_actual_size[0x20]; 7549 7550 u8 reserved_5[0x560]; 7551 7552 u8 klm_pas_mtt[0][0x20]; 7553 }; 7554 7555 struct mlx5_ifc_create_flow_table_out_bits { 7556 u8 status[0x8]; 7557 u8 reserved_0[0x18]; 7558 7559 u8 syndrome[0x20]; 7560 7561 u8 reserved_1[0x8]; 7562 u8 table_id[0x18]; 7563 7564 u8 reserved_2[0x20]; 7565 }; 7566 7567 struct mlx5_ifc_create_flow_table_in_bits { 7568 u8 opcode[0x10]; 7569 u8 reserved_at_10[0x10]; 7570 7571 u8 reserved_at_20[0x10]; 7572 u8 op_mod[0x10]; 7573 7574 u8 other_vport[0x1]; 7575 u8 reserved_at_41[0xf]; 7576 u8 vport_number[0x10]; 7577 7578 u8 reserved_at_60[0x20]; 7579 7580 u8 table_type[0x8]; 7581 u8 reserved_at_88[0x18]; 7582 7583 u8 reserved_at_a0[0x20]; 7584 7585 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7586 }; 7587 7588 struct mlx5_ifc_create_flow_group_out_bits { 7589 u8 status[0x8]; 7590 u8 reserved_0[0x18]; 7591 7592 u8 syndrome[0x20]; 7593 7594 u8 reserved_1[0x8]; 7595 u8 group_id[0x18]; 7596 7597 u8 reserved_2[0x20]; 7598 }; 7599 7600 enum { 7601 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7602 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7603 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7604 }; 7605 7606 struct mlx5_ifc_create_flow_group_in_bits { 7607 u8 opcode[0x10]; 7608 u8 reserved_0[0x10]; 7609 7610 u8 reserved_1[0x10]; 7611 u8 op_mod[0x10]; 7612 7613 u8 other_vport[0x1]; 7614 u8 reserved_2[0xf]; 7615 u8 vport_number[0x10]; 7616 7617 u8 reserved_3[0x20]; 7618 7619 u8 table_type[0x8]; 7620 u8 reserved_4[0x18]; 7621 7622 u8 reserved_5[0x8]; 7623 u8 table_id[0x18]; 7624 7625 u8 reserved_6[0x20]; 7626 7627 u8 start_flow_index[0x20]; 7628 7629 u8 reserved_7[0x20]; 7630 7631 u8 end_flow_index[0x20]; 7632 7633 u8 reserved_8[0xa0]; 7634 7635 u8 reserved_9[0x18]; 7636 u8 match_criteria_enable[0x8]; 7637 7638 struct mlx5_ifc_fte_match_param_bits match_criteria; 7639 7640 u8 reserved_10[0xe00]; 7641 }; 7642 7643 struct mlx5_ifc_create_encryption_key_out_bits { 7644 u8 status[0x8]; 7645 u8 reserved_at_8[0x18]; 7646 7647 u8 syndrome[0x20]; 7648 7649 u8 obj_id[0x20]; 7650 7651 u8 reserved_at_60[0x20]; 7652 }; 7653 7654 struct mlx5_ifc_create_encryption_key_in_bits { 7655 u8 opcode[0x10]; 7656 u8 reserved_at_10[0x10]; 7657 7658 u8 reserved_at_20[0x10]; 7659 u8 obj_type[0x10]; 7660 7661 u8 reserved_at_40[0x40]; 7662 7663 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 7664 }; 7665 7666 struct mlx5_ifc_create_eq_out_bits { 7667 u8 status[0x8]; 7668 u8 reserved_0[0x18]; 7669 7670 u8 syndrome[0x20]; 7671 7672 u8 reserved_1[0x18]; 7673 u8 eq_number[0x8]; 7674 7675 u8 reserved_2[0x20]; 7676 }; 7677 7678 struct mlx5_ifc_create_eq_in_bits { 7679 u8 opcode[0x10]; 7680 u8 reserved_0[0x10]; 7681 7682 u8 reserved_1[0x10]; 7683 u8 op_mod[0x10]; 7684 7685 u8 reserved_2[0x40]; 7686 7687 struct mlx5_ifc_eqc_bits eq_context_entry; 7688 7689 u8 reserved_3[0x40]; 7690 7691 u8 event_bitmask[0x40]; 7692 7693 u8 reserved_4[0x580]; 7694 7695 u8 pas[0][0x40]; 7696 }; 7697 7698 struct mlx5_ifc_create_dct_out_bits { 7699 u8 status[0x8]; 7700 u8 reserved_0[0x18]; 7701 7702 u8 syndrome[0x20]; 7703 7704 u8 reserved_1[0x8]; 7705 u8 dctn[0x18]; 7706 7707 u8 reserved_2[0x20]; 7708 }; 7709 7710 struct mlx5_ifc_create_dct_in_bits { 7711 u8 opcode[0x10]; 7712 u8 uid[0x10]; 7713 7714 u8 reserved_1[0x10]; 7715 u8 op_mod[0x10]; 7716 7717 u8 reserved_2[0x40]; 7718 7719 struct mlx5_ifc_dctc_bits dct_context_entry; 7720 7721 u8 reserved_3[0x180]; 7722 }; 7723 7724 struct mlx5_ifc_create_cq_out_bits { 7725 u8 status[0x8]; 7726 u8 reserved_0[0x18]; 7727 7728 u8 syndrome[0x20]; 7729 7730 u8 reserved_1[0x8]; 7731 u8 cqn[0x18]; 7732 7733 u8 reserved_2[0x20]; 7734 }; 7735 7736 struct mlx5_ifc_create_cq_in_bits { 7737 u8 opcode[0x10]; 7738 u8 uid[0x10]; 7739 7740 u8 reserved_1[0x10]; 7741 u8 op_mod[0x10]; 7742 7743 u8 reserved_2[0x40]; 7744 7745 struct mlx5_ifc_cqc_bits cq_context; 7746 7747 u8 reserved_at_280[0x60]; 7748 7749 u8 cq_umem_valid[0x1]; 7750 u8 reserved_at_2e1[0x59f]; 7751 7752 u8 pas[0][0x40]; 7753 }; 7754 7755 struct mlx5_ifc_config_int_moderation_out_bits { 7756 u8 status[0x8]; 7757 u8 reserved_0[0x18]; 7758 7759 u8 syndrome[0x20]; 7760 7761 u8 reserved_1[0x4]; 7762 u8 min_delay[0xc]; 7763 u8 int_vector[0x10]; 7764 7765 u8 reserved_2[0x20]; 7766 }; 7767 7768 enum { 7769 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7770 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7771 }; 7772 7773 struct mlx5_ifc_config_int_moderation_in_bits { 7774 u8 opcode[0x10]; 7775 u8 reserved_0[0x10]; 7776 7777 u8 reserved_1[0x10]; 7778 u8 op_mod[0x10]; 7779 7780 u8 reserved_2[0x4]; 7781 u8 min_delay[0xc]; 7782 u8 int_vector[0x10]; 7783 7784 u8 reserved_3[0x20]; 7785 }; 7786 7787 struct mlx5_ifc_attach_to_mcg_out_bits { 7788 u8 status[0x8]; 7789 u8 reserved_0[0x18]; 7790 7791 u8 syndrome[0x20]; 7792 7793 u8 reserved_1[0x40]; 7794 }; 7795 7796 struct mlx5_ifc_attach_to_mcg_in_bits { 7797 u8 opcode[0x10]; 7798 u8 uid[0x10]; 7799 7800 u8 reserved_1[0x10]; 7801 u8 op_mod[0x10]; 7802 7803 u8 reserved_2[0x8]; 7804 u8 qpn[0x18]; 7805 7806 u8 reserved_3[0x20]; 7807 7808 u8 multicast_gid[16][0x8]; 7809 }; 7810 7811 struct mlx5_ifc_arm_xrq_out_bits { 7812 u8 status[0x8]; 7813 u8 reserved_at_8[0x18]; 7814 7815 u8 syndrome[0x20]; 7816 7817 u8 reserved_at_40[0x40]; 7818 }; 7819 7820 struct mlx5_ifc_arm_xrq_in_bits { 7821 u8 opcode[0x10]; 7822 u8 reserved_at_10[0x10]; 7823 7824 u8 reserved_at_20[0x10]; 7825 u8 op_mod[0x10]; 7826 7827 u8 reserved_at_40[0x8]; 7828 u8 xrqn[0x18]; 7829 7830 u8 reserved_at_60[0x10]; 7831 u8 lwm[0x10]; 7832 }; 7833 7834 struct mlx5_ifc_arm_xrc_srq_out_bits { 7835 u8 status[0x8]; 7836 u8 reserved_0[0x18]; 7837 7838 u8 syndrome[0x20]; 7839 7840 u8 reserved_1[0x40]; 7841 }; 7842 7843 enum { 7844 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7845 }; 7846 7847 struct mlx5_ifc_arm_xrc_srq_in_bits { 7848 u8 opcode[0x10]; 7849 u8 uid[0x10]; 7850 7851 u8 reserved_1[0x10]; 7852 u8 op_mod[0x10]; 7853 7854 u8 reserved_2[0x8]; 7855 u8 xrc_srqn[0x18]; 7856 7857 u8 reserved_3[0x10]; 7858 u8 lwm[0x10]; 7859 }; 7860 7861 struct mlx5_ifc_arm_rq_out_bits { 7862 u8 status[0x8]; 7863 u8 reserved_0[0x18]; 7864 7865 u8 syndrome[0x20]; 7866 7867 u8 reserved_1[0x40]; 7868 }; 7869 7870 enum { 7871 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7872 }; 7873 7874 struct mlx5_ifc_arm_rq_in_bits { 7875 u8 opcode[0x10]; 7876 u8 uid[0x10]; 7877 7878 u8 reserved_1[0x10]; 7879 u8 op_mod[0x10]; 7880 7881 u8 reserved_2[0x8]; 7882 u8 srq_number[0x18]; 7883 7884 u8 reserved_3[0x10]; 7885 u8 lwm[0x10]; 7886 }; 7887 7888 struct mlx5_ifc_arm_dct_out_bits { 7889 u8 status[0x8]; 7890 u8 reserved_0[0x18]; 7891 7892 u8 syndrome[0x20]; 7893 7894 u8 reserved_1[0x40]; 7895 }; 7896 7897 struct mlx5_ifc_arm_dct_in_bits { 7898 u8 opcode[0x10]; 7899 u8 reserved_0[0x10]; 7900 7901 u8 reserved_1[0x10]; 7902 u8 op_mod[0x10]; 7903 7904 u8 reserved_2[0x8]; 7905 u8 dctn[0x18]; 7906 7907 u8 reserved_3[0x20]; 7908 }; 7909 7910 struct mlx5_ifc_alloc_xrcd_out_bits { 7911 u8 status[0x8]; 7912 u8 reserved_0[0x18]; 7913 7914 u8 syndrome[0x20]; 7915 7916 u8 reserved_1[0x8]; 7917 u8 xrcd[0x18]; 7918 7919 u8 reserved_2[0x20]; 7920 }; 7921 7922 struct mlx5_ifc_alloc_xrcd_in_bits { 7923 u8 opcode[0x10]; 7924 u8 uid[0x10]; 7925 7926 u8 reserved_1[0x10]; 7927 u8 op_mod[0x10]; 7928 7929 u8 reserved_2[0x40]; 7930 }; 7931 7932 struct mlx5_ifc_alloc_uar_out_bits { 7933 u8 status[0x8]; 7934 u8 reserved_0[0x18]; 7935 7936 u8 syndrome[0x20]; 7937 7938 u8 reserved_1[0x8]; 7939 u8 uar[0x18]; 7940 7941 u8 reserved_2[0x20]; 7942 }; 7943 7944 struct mlx5_ifc_alloc_uar_in_bits { 7945 u8 opcode[0x10]; 7946 u8 reserved_0[0x10]; 7947 7948 u8 reserved_1[0x10]; 7949 u8 op_mod[0x10]; 7950 7951 u8 reserved_2[0x40]; 7952 }; 7953 7954 struct mlx5_ifc_alloc_transport_domain_out_bits { 7955 u8 status[0x8]; 7956 u8 reserved_0[0x18]; 7957 7958 u8 syndrome[0x20]; 7959 7960 u8 reserved_1[0x8]; 7961 u8 transport_domain[0x18]; 7962 7963 u8 reserved_2[0x20]; 7964 }; 7965 7966 struct mlx5_ifc_alloc_transport_domain_in_bits { 7967 u8 opcode[0x10]; 7968 u8 uid[0x10]; 7969 7970 u8 reserved_1[0x10]; 7971 u8 op_mod[0x10]; 7972 7973 u8 reserved_2[0x40]; 7974 }; 7975 7976 struct mlx5_ifc_alloc_q_counter_out_bits { 7977 u8 status[0x8]; 7978 u8 reserved_0[0x18]; 7979 7980 u8 syndrome[0x20]; 7981 7982 u8 reserved_1[0x18]; 7983 u8 counter_set_id[0x8]; 7984 7985 u8 reserved_2[0x20]; 7986 }; 7987 7988 struct mlx5_ifc_alloc_q_counter_in_bits { 7989 u8 opcode[0x10]; 7990 u8 uid[0x10]; 7991 7992 u8 reserved_1[0x10]; 7993 u8 op_mod[0x10]; 7994 7995 u8 reserved_2[0x40]; 7996 }; 7997 7998 struct mlx5_ifc_alloc_pd_out_bits { 7999 u8 status[0x8]; 8000 u8 reserved_0[0x18]; 8001 8002 u8 syndrome[0x20]; 8003 8004 u8 reserved_1[0x8]; 8005 u8 pd[0x18]; 8006 8007 u8 reserved_2[0x20]; 8008 }; 8009 8010 struct mlx5_ifc_alloc_pd_in_bits { 8011 u8 opcode[0x10]; 8012 u8 uid[0x10]; 8013 8014 u8 reserved_1[0x10]; 8015 u8 op_mod[0x10]; 8016 8017 u8 reserved_2[0x40]; 8018 }; 8019 8020 struct mlx5_ifc_alloc_flow_counter_out_bits { 8021 u8 status[0x8]; 8022 u8 reserved_at_8[0x18]; 8023 8024 u8 syndrome[0x20]; 8025 8026 u8 flow_counter_id[0x20]; 8027 8028 u8 reserved_at_60[0x20]; 8029 }; 8030 8031 struct mlx5_ifc_alloc_flow_counter_in_bits { 8032 u8 opcode[0x10]; 8033 u8 reserved_at_10[0x10]; 8034 8035 u8 reserved_at_20[0x10]; 8036 u8 op_mod[0x10]; 8037 8038 u8 reserved_at_40[0x38]; 8039 u8 flow_counter_bulk[0x8]; 8040 }; 8041 8042 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8043 u8 status[0x8]; 8044 u8 reserved_0[0x18]; 8045 8046 u8 syndrome[0x20]; 8047 8048 u8 reserved_1[0x40]; 8049 }; 8050 8051 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8052 u8 opcode[0x10]; 8053 u8 reserved_0[0x10]; 8054 8055 u8 reserved_1[0x10]; 8056 u8 op_mod[0x10]; 8057 8058 u8 reserved_2[0x20]; 8059 8060 u8 reserved_3[0x10]; 8061 u8 vxlan_udp_port[0x10]; 8062 }; 8063 8064 struct mlx5_ifc_activate_tracer_out_bits { 8065 u8 status[0x8]; 8066 u8 reserved_0[0x18]; 8067 8068 u8 syndrome[0x20]; 8069 8070 u8 reserved_1[0x40]; 8071 }; 8072 8073 struct mlx5_ifc_activate_tracer_in_bits { 8074 u8 opcode[0x10]; 8075 u8 reserved_0[0x10]; 8076 8077 u8 reserved_1[0x10]; 8078 u8 op_mod[0x10]; 8079 8080 u8 mkey[0x20]; 8081 8082 u8 reserved_2[0x20]; 8083 }; 8084 8085 struct mlx5_ifc_set_rate_limit_out_bits { 8086 u8 status[0x8]; 8087 u8 reserved_at_8[0x18]; 8088 8089 u8 syndrome[0x20]; 8090 8091 u8 reserved_at_40[0x40]; 8092 }; 8093 8094 struct mlx5_ifc_set_rate_limit_in_bits { 8095 u8 opcode[0x10]; 8096 u8 uid[0x10]; 8097 8098 u8 reserved_at_20[0x10]; 8099 u8 op_mod[0x10]; 8100 8101 u8 reserved_at_40[0x10]; 8102 u8 rate_limit_index[0x10]; 8103 8104 u8 reserved_at_60[0x20]; 8105 8106 u8 rate_limit[0x20]; 8107 8108 u8 burst_upper_bound[0x20]; 8109 8110 u8 reserved_at_c0[0x10]; 8111 u8 typical_packet_size[0x10]; 8112 8113 u8 reserved_at_e0[0x120]; 8114 }; 8115 8116 struct mlx5_ifc_access_register_out_bits { 8117 u8 status[0x8]; 8118 u8 reserved_0[0x18]; 8119 8120 u8 syndrome[0x20]; 8121 8122 u8 reserved_1[0x40]; 8123 8124 u8 register_data[0][0x20]; 8125 }; 8126 8127 enum { 8128 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8129 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8130 }; 8131 8132 struct mlx5_ifc_access_register_in_bits { 8133 u8 opcode[0x10]; 8134 u8 reserved_0[0x10]; 8135 8136 u8 reserved_1[0x10]; 8137 u8 op_mod[0x10]; 8138 8139 u8 reserved_2[0x10]; 8140 u8 register_id[0x10]; 8141 8142 u8 argument[0x20]; 8143 8144 u8 register_data[0][0x20]; 8145 }; 8146 8147 struct mlx5_ifc_sltp_reg_bits { 8148 u8 status[0x4]; 8149 u8 version[0x4]; 8150 u8 local_port[0x8]; 8151 u8 pnat[0x2]; 8152 u8 reserved_0[0x2]; 8153 u8 lane[0x4]; 8154 u8 reserved_1[0x8]; 8155 8156 u8 reserved_2[0x20]; 8157 8158 u8 reserved_3[0x7]; 8159 u8 polarity[0x1]; 8160 u8 ob_tap0[0x8]; 8161 u8 ob_tap1[0x8]; 8162 u8 ob_tap2[0x8]; 8163 8164 u8 reserved_4[0xc]; 8165 u8 ob_preemp_mode[0x4]; 8166 u8 ob_reg[0x8]; 8167 u8 ob_bias[0x8]; 8168 8169 u8 reserved_5[0x20]; 8170 }; 8171 8172 struct mlx5_ifc_slrp_reg_bits { 8173 u8 status[0x4]; 8174 u8 version[0x4]; 8175 u8 local_port[0x8]; 8176 u8 pnat[0x2]; 8177 u8 reserved_0[0x2]; 8178 u8 lane[0x4]; 8179 u8 reserved_1[0x8]; 8180 8181 u8 ib_sel[0x2]; 8182 u8 reserved_2[0x11]; 8183 u8 dp_sel[0x1]; 8184 u8 dp90sel[0x4]; 8185 u8 mix90phase[0x8]; 8186 8187 u8 ffe_tap0[0x8]; 8188 u8 ffe_tap1[0x8]; 8189 u8 ffe_tap2[0x8]; 8190 u8 ffe_tap3[0x8]; 8191 8192 u8 ffe_tap4[0x8]; 8193 u8 ffe_tap5[0x8]; 8194 u8 ffe_tap6[0x8]; 8195 u8 ffe_tap7[0x8]; 8196 8197 u8 ffe_tap8[0x8]; 8198 u8 mixerbias_tap_amp[0x8]; 8199 u8 reserved_3[0x7]; 8200 u8 ffe_tap_en[0x9]; 8201 8202 u8 ffe_tap_offset0[0x8]; 8203 u8 ffe_tap_offset1[0x8]; 8204 u8 slicer_offset0[0x10]; 8205 8206 u8 mixer_offset0[0x10]; 8207 u8 mixer_offset1[0x10]; 8208 8209 u8 mixerbgn_inp[0x8]; 8210 u8 mixerbgn_inn[0x8]; 8211 u8 mixerbgn_refp[0x8]; 8212 u8 mixerbgn_refn[0x8]; 8213 8214 u8 sel_slicer_lctrl_h[0x1]; 8215 u8 sel_slicer_lctrl_l[0x1]; 8216 u8 reserved_4[0x1]; 8217 u8 ref_mixer_vreg[0x5]; 8218 u8 slicer_gctrl[0x8]; 8219 u8 lctrl_input[0x8]; 8220 u8 mixer_offset_cm1[0x8]; 8221 8222 u8 common_mode[0x6]; 8223 u8 reserved_5[0x1]; 8224 u8 mixer_offset_cm0[0x9]; 8225 u8 reserved_6[0x7]; 8226 u8 slicer_offset_cm[0x9]; 8227 }; 8228 8229 struct mlx5_ifc_slrg_reg_bits { 8230 u8 status[0x4]; 8231 u8 version[0x4]; 8232 u8 local_port[0x8]; 8233 u8 pnat[0x2]; 8234 u8 reserved_0[0x2]; 8235 u8 lane[0x4]; 8236 u8 reserved_1[0x8]; 8237 8238 u8 time_to_link_up[0x10]; 8239 u8 reserved_2[0xc]; 8240 u8 grade_lane_speed[0x4]; 8241 8242 u8 grade_version[0x8]; 8243 u8 grade[0x18]; 8244 8245 u8 reserved_3[0x4]; 8246 u8 height_grade_type[0x4]; 8247 u8 height_grade[0x18]; 8248 8249 u8 height_dz[0x10]; 8250 u8 height_dv[0x10]; 8251 8252 u8 reserved_4[0x10]; 8253 u8 height_sigma[0x10]; 8254 8255 u8 reserved_5[0x20]; 8256 8257 u8 reserved_6[0x4]; 8258 u8 phase_grade_type[0x4]; 8259 u8 phase_grade[0x18]; 8260 8261 u8 reserved_7[0x8]; 8262 u8 phase_eo_pos[0x8]; 8263 u8 reserved_8[0x8]; 8264 u8 phase_eo_neg[0x8]; 8265 8266 u8 ffe_set_tested[0x10]; 8267 u8 test_errors_per_lane[0x10]; 8268 }; 8269 8270 struct mlx5_ifc_pvlc_reg_bits { 8271 u8 reserved_0[0x8]; 8272 u8 local_port[0x8]; 8273 u8 reserved_1[0x10]; 8274 8275 u8 reserved_2[0x1c]; 8276 u8 vl_hw_cap[0x4]; 8277 8278 u8 reserved_3[0x1c]; 8279 u8 vl_admin[0x4]; 8280 8281 u8 reserved_4[0x1c]; 8282 u8 vl_operational[0x4]; 8283 }; 8284 8285 struct mlx5_ifc_pude_reg_bits { 8286 u8 swid[0x8]; 8287 u8 local_port[0x8]; 8288 u8 reserved_0[0x4]; 8289 u8 admin_status[0x4]; 8290 u8 reserved_1[0x4]; 8291 u8 oper_status[0x4]; 8292 8293 u8 reserved_2[0x60]; 8294 }; 8295 8296 enum { 8297 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 8298 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 8299 }; 8300 8301 struct mlx5_ifc_ptys_reg_bits { 8302 u8 reserved_0[0x1]; 8303 u8 an_disable_admin[0x1]; 8304 u8 an_disable_cap[0x1]; 8305 u8 reserved_1[0x4]; 8306 u8 force_tx_aba_param[0x1]; 8307 u8 local_port[0x8]; 8308 u8 reserved_2[0xd]; 8309 u8 proto_mask[0x3]; 8310 8311 u8 an_status[0x4]; 8312 u8 reserved_3[0xc]; 8313 u8 data_rate_oper[0x10]; 8314 8315 u8 ext_eth_proto_capability[0x20]; 8316 8317 u8 eth_proto_capability[0x20]; 8318 8319 u8 ib_link_width_capability[0x10]; 8320 u8 ib_proto_capability[0x10]; 8321 8322 u8 ext_eth_proto_admin[0x20]; 8323 8324 u8 eth_proto_admin[0x20]; 8325 8326 u8 ib_link_width_admin[0x10]; 8327 u8 ib_proto_admin[0x10]; 8328 8329 u8 ext_eth_proto_oper[0x20]; 8330 8331 u8 eth_proto_oper[0x20]; 8332 8333 u8 ib_link_width_oper[0x10]; 8334 u8 ib_proto_oper[0x10]; 8335 8336 u8 reserved_4[0x1c]; 8337 u8 connector_type[0x4]; 8338 8339 u8 eth_proto_lp_advertise[0x20]; 8340 8341 u8 reserved_5[0x60]; 8342 }; 8343 8344 struct mlx5_ifc_ptas_reg_bits { 8345 u8 reserved_0[0x20]; 8346 8347 u8 algorithm_options[0x10]; 8348 u8 reserved_1[0x4]; 8349 u8 repetitions_mode[0x4]; 8350 u8 num_of_repetitions[0x8]; 8351 8352 u8 grade_version[0x8]; 8353 u8 height_grade_type[0x4]; 8354 u8 phase_grade_type[0x4]; 8355 u8 height_grade_weight[0x8]; 8356 u8 phase_grade_weight[0x8]; 8357 8358 u8 gisim_measure_bits[0x10]; 8359 u8 adaptive_tap_measure_bits[0x10]; 8360 8361 u8 ber_bath_high_error_threshold[0x10]; 8362 u8 ber_bath_mid_error_threshold[0x10]; 8363 8364 u8 ber_bath_low_error_threshold[0x10]; 8365 u8 one_ratio_high_threshold[0x10]; 8366 8367 u8 one_ratio_high_mid_threshold[0x10]; 8368 u8 one_ratio_low_mid_threshold[0x10]; 8369 8370 u8 one_ratio_low_threshold[0x10]; 8371 u8 ndeo_error_threshold[0x10]; 8372 8373 u8 mixer_offset_step_size[0x10]; 8374 u8 reserved_2[0x8]; 8375 u8 mix90_phase_for_voltage_bath[0x8]; 8376 8377 u8 mixer_offset_start[0x10]; 8378 u8 mixer_offset_end[0x10]; 8379 8380 u8 reserved_3[0x15]; 8381 u8 ber_test_time[0xb]; 8382 }; 8383 8384 struct mlx5_ifc_pspa_reg_bits { 8385 u8 swid[0x8]; 8386 u8 local_port[0x8]; 8387 u8 sub_port[0x8]; 8388 u8 reserved_0[0x8]; 8389 8390 u8 reserved_1[0x20]; 8391 }; 8392 8393 struct mlx5_ifc_ppsc_reg_bits { 8394 u8 reserved_0[0x8]; 8395 u8 local_port[0x8]; 8396 u8 reserved_1[0x10]; 8397 8398 u8 reserved_2[0x60]; 8399 8400 u8 reserved_3[0x1c]; 8401 u8 wrps_admin[0x4]; 8402 8403 u8 reserved_4[0x1c]; 8404 u8 wrps_status[0x4]; 8405 8406 u8 up_th_vld[0x1]; 8407 u8 down_th_vld[0x1]; 8408 u8 reserved_5[0x6]; 8409 u8 up_threshold[0x8]; 8410 u8 reserved_6[0x8]; 8411 u8 down_threshold[0x8]; 8412 8413 u8 reserved_7[0x20]; 8414 8415 u8 reserved_8[0x1c]; 8416 u8 srps_admin[0x4]; 8417 8418 u8 reserved_9[0x60]; 8419 }; 8420 8421 struct mlx5_ifc_pplr_reg_bits { 8422 u8 reserved_0[0x8]; 8423 u8 local_port[0x8]; 8424 u8 reserved_1[0x10]; 8425 8426 u8 reserved_2[0x8]; 8427 u8 lb_cap[0x8]; 8428 u8 reserved_3[0x8]; 8429 u8 lb_en[0x8]; 8430 }; 8431 8432 struct mlx5_ifc_pplm_reg_bits { 8433 u8 reserved_at_0[0x8]; 8434 u8 local_port[0x8]; 8435 u8 reserved_at_10[0x10]; 8436 8437 u8 reserved_at_20[0x20]; 8438 8439 u8 port_profile_mode[0x8]; 8440 u8 static_port_profile[0x8]; 8441 u8 active_port_profile[0x8]; 8442 u8 reserved_at_58[0x8]; 8443 8444 u8 retransmission_active[0x8]; 8445 u8 fec_mode_active[0x18]; 8446 8447 u8 rs_fec_correction_bypass_cap[0x4]; 8448 u8 reserved_at_84[0x8]; 8449 u8 fec_override_cap_56g[0x4]; 8450 u8 fec_override_cap_100g[0x4]; 8451 u8 fec_override_cap_50g[0x4]; 8452 u8 fec_override_cap_25g[0x4]; 8453 u8 fec_override_cap_10g_40g[0x4]; 8454 8455 u8 rs_fec_correction_bypass_admin[0x4]; 8456 u8 reserved_at_a4[0x8]; 8457 u8 fec_override_admin_56g[0x4]; 8458 u8 fec_override_admin_100g[0x4]; 8459 u8 fec_override_admin_50g[0x4]; 8460 u8 fec_override_admin_25g[0x4]; 8461 u8 fec_override_admin_10g_40g[0x4]; 8462 8463 u8 fec_override_cap_400g_8x[0x10]; 8464 u8 fec_override_cap_200g_4x[0x10]; 8465 u8 fec_override_cap_100g_2x[0x10]; 8466 u8 fec_override_cap_50g_1x[0x10]; 8467 8468 u8 fec_override_admin_400g_8x[0x10]; 8469 u8 fec_override_admin_200g_4x[0x10]; 8470 u8 fec_override_admin_100g_2x[0x10]; 8471 u8 fec_override_admin_50g_1x[0x10]; 8472 8473 u8 reserved_at_140[0x140]; 8474 }; 8475 8476 struct mlx5_ifc_ppll_reg_bits { 8477 u8 num_pll_groups[0x8]; 8478 u8 pll_group[0x8]; 8479 u8 reserved_0[0x4]; 8480 u8 num_plls[0x4]; 8481 u8 reserved_1[0x8]; 8482 8483 u8 reserved_2[0x1f]; 8484 u8 ae[0x1]; 8485 8486 u8 pll_status[4][0x40]; 8487 }; 8488 8489 struct mlx5_ifc_ppad_reg_bits { 8490 u8 reserved_0[0x3]; 8491 u8 single_mac[0x1]; 8492 u8 reserved_1[0x4]; 8493 u8 local_port[0x8]; 8494 u8 mac_47_32[0x10]; 8495 8496 u8 mac_31_0[0x20]; 8497 8498 u8 reserved_2[0x40]; 8499 }; 8500 8501 struct mlx5_ifc_pmtu_reg_bits { 8502 u8 reserved_0[0x8]; 8503 u8 local_port[0x8]; 8504 u8 reserved_1[0x10]; 8505 8506 u8 max_mtu[0x10]; 8507 u8 reserved_2[0x10]; 8508 8509 u8 admin_mtu[0x10]; 8510 u8 reserved_3[0x10]; 8511 8512 u8 oper_mtu[0x10]; 8513 u8 reserved_4[0x10]; 8514 }; 8515 8516 struct mlx5_ifc_pmpr_reg_bits { 8517 u8 reserved_0[0x8]; 8518 u8 module[0x8]; 8519 u8 reserved_1[0x10]; 8520 8521 u8 reserved_2[0x18]; 8522 u8 attenuation_5g[0x8]; 8523 8524 u8 reserved_3[0x18]; 8525 u8 attenuation_7g[0x8]; 8526 8527 u8 reserved_4[0x18]; 8528 u8 attenuation_12g[0x8]; 8529 }; 8530 8531 struct mlx5_ifc_pmpe_reg_bits { 8532 u8 reserved_0[0x8]; 8533 u8 module[0x8]; 8534 u8 reserved_1[0xc]; 8535 u8 module_status[0x4]; 8536 8537 u8 reserved_2[0x14]; 8538 u8 error_type[0x4]; 8539 u8 reserved_3[0x8]; 8540 8541 u8 reserved_4[0x40]; 8542 }; 8543 8544 struct mlx5_ifc_pmpc_reg_bits { 8545 u8 module_state_updated[32][0x8]; 8546 }; 8547 8548 struct mlx5_ifc_pmlpn_reg_bits { 8549 u8 reserved_0[0x4]; 8550 u8 mlpn_status[0x4]; 8551 u8 local_port[0x8]; 8552 u8 reserved_1[0x10]; 8553 8554 u8 e[0x1]; 8555 u8 reserved_2[0x1f]; 8556 }; 8557 8558 struct mlx5_ifc_pmlp_reg_bits { 8559 u8 rxtx[0x1]; 8560 u8 reserved_0[0x7]; 8561 u8 local_port[0x8]; 8562 u8 reserved_1[0x8]; 8563 u8 width[0x8]; 8564 8565 u8 lane0_module_mapping[0x20]; 8566 8567 u8 lane1_module_mapping[0x20]; 8568 8569 u8 lane2_module_mapping[0x20]; 8570 8571 u8 lane3_module_mapping[0x20]; 8572 8573 u8 reserved_2[0x160]; 8574 }; 8575 8576 struct mlx5_ifc_pmaos_reg_bits { 8577 u8 reserved_0[0x8]; 8578 u8 module[0x8]; 8579 u8 reserved_1[0x4]; 8580 u8 admin_status[0x4]; 8581 u8 reserved_2[0x4]; 8582 u8 oper_status[0x4]; 8583 8584 u8 ase[0x1]; 8585 u8 ee[0x1]; 8586 u8 reserved_3[0x12]; 8587 u8 error_type[0x4]; 8588 u8 reserved_4[0x6]; 8589 u8 e[0x2]; 8590 8591 u8 reserved_5[0x40]; 8592 }; 8593 8594 struct mlx5_ifc_plpc_reg_bits { 8595 u8 reserved_0[0x4]; 8596 u8 profile_id[0xc]; 8597 u8 reserved_1[0x4]; 8598 u8 proto_mask[0x4]; 8599 u8 reserved_2[0x8]; 8600 8601 u8 reserved_3[0x10]; 8602 u8 lane_speed[0x10]; 8603 8604 u8 reserved_4[0x17]; 8605 u8 lpbf[0x1]; 8606 u8 fec_mode_policy[0x8]; 8607 8608 u8 retransmission_capability[0x8]; 8609 u8 fec_mode_capability[0x18]; 8610 8611 u8 retransmission_support_admin[0x8]; 8612 u8 fec_mode_support_admin[0x18]; 8613 8614 u8 retransmission_request_admin[0x8]; 8615 u8 fec_mode_request_admin[0x18]; 8616 8617 u8 reserved_5[0x80]; 8618 }; 8619 8620 struct mlx5_ifc_pll_status_data_bits { 8621 u8 reserved_0[0x1]; 8622 u8 lock_cal[0x1]; 8623 u8 lock_status[0x2]; 8624 u8 reserved_1[0x2]; 8625 u8 algo_f_ctrl[0xa]; 8626 u8 analog_algo_num_var[0x6]; 8627 u8 f_ctrl_measure[0xa]; 8628 8629 u8 reserved_2[0x2]; 8630 u8 analog_var[0x6]; 8631 u8 reserved_3[0x2]; 8632 u8 high_var[0x6]; 8633 u8 reserved_4[0x2]; 8634 u8 low_var[0x6]; 8635 u8 reserved_5[0x2]; 8636 u8 mid_val[0x6]; 8637 }; 8638 8639 struct mlx5_ifc_plib_reg_bits { 8640 u8 reserved_0[0x8]; 8641 u8 local_port[0x8]; 8642 u8 reserved_1[0x8]; 8643 u8 ib_port[0x8]; 8644 8645 u8 reserved_2[0x60]; 8646 }; 8647 8648 struct mlx5_ifc_plbf_reg_bits { 8649 u8 reserved_0[0x8]; 8650 u8 local_port[0x8]; 8651 u8 reserved_1[0xd]; 8652 u8 lbf_mode[0x3]; 8653 8654 u8 reserved_2[0x20]; 8655 }; 8656 8657 struct mlx5_ifc_pipg_reg_bits { 8658 u8 reserved_0[0x8]; 8659 u8 local_port[0x8]; 8660 u8 reserved_1[0x10]; 8661 8662 u8 dic[0x1]; 8663 u8 reserved_2[0x19]; 8664 u8 ipg[0x4]; 8665 u8 reserved_3[0x2]; 8666 }; 8667 8668 struct mlx5_ifc_pifr_reg_bits { 8669 u8 reserved_0[0x8]; 8670 u8 local_port[0x8]; 8671 u8 reserved_1[0x10]; 8672 8673 u8 reserved_2[0xe0]; 8674 8675 u8 port_filter[8][0x20]; 8676 8677 u8 port_filter_update_en[8][0x20]; 8678 }; 8679 8680 struct mlx5_ifc_phys_layer_cntrs_bits { 8681 u8 time_since_last_clear_high[0x20]; 8682 8683 u8 time_since_last_clear_low[0x20]; 8684 8685 u8 symbol_errors_high[0x20]; 8686 8687 u8 symbol_errors_low[0x20]; 8688 8689 u8 sync_headers_errors_high[0x20]; 8690 8691 u8 sync_headers_errors_low[0x20]; 8692 8693 u8 edpl_bip_errors_lane0_high[0x20]; 8694 8695 u8 edpl_bip_errors_lane0_low[0x20]; 8696 8697 u8 edpl_bip_errors_lane1_high[0x20]; 8698 8699 u8 edpl_bip_errors_lane1_low[0x20]; 8700 8701 u8 edpl_bip_errors_lane2_high[0x20]; 8702 8703 u8 edpl_bip_errors_lane2_low[0x20]; 8704 8705 u8 edpl_bip_errors_lane3_high[0x20]; 8706 8707 u8 edpl_bip_errors_lane3_low[0x20]; 8708 8709 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 8710 8711 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 8712 8713 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 8714 8715 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 8716 8717 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 8718 8719 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 8720 8721 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 8722 8723 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 8724 8725 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 8726 8727 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 8728 8729 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 8730 8731 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 8732 8733 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 8734 8735 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 8736 8737 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 8738 8739 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 8740 8741 u8 rs_fec_corrected_blocks_high[0x20]; 8742 8743 u8 rs_fec_corrected_blocks_low[0x20]; 8744 8745 u8 rs_fec_uncorrectable_blocks_high[0x20]; 8746 8747 u8 rs_fec_uncorrectable_blocks_low[0x20]; 8748 8749 u8 rs_fec_no_errors_blocks_high[0x20]; 8750 8751 u8 rs_fec_no_errors_blocks_low[0x20]; 8752 8753 u8 rs_fec_single_error_blocks_high[0x20]; 8754 8755 u8 rs_fec_single_error_blocks_low[0x20]; 8756 8757 u8 rs_fec_corrected_symbols_total_high[0x20]; 8758 8759 u8 rs_fec_corrected_symbols_total_low[0x20]; 8760 8761 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 8762 8763 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 8764 8765 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 8766 8767 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 8768 8769 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 8770 8771 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 8772 8773 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 8774 8775 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 8776 8777 u8 link_down_events[0x20]; 8778 8779 u8 successful_recovery_events[0x20]; 8780 8781 u8 reserved_0[0x180]; 8782 }; 8783 8784 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 8785 u8 symbol_error_counter[0x10]; 8786 8787 u8 link_error_recovery_counter[0x8]; 8788 8789 u8 link_downed_counter[0x8]; 8790 8791 u8 port_rcv_errors[0x10]; 8792 8793 u8 port_rcv_remote_physical_errors[0x10]; 8794 8795 u8 port_rcv_switch_relay_errors[0x10]; 8796 8797 u8 port_xmit_discards[0x10]; 8798 8799 u8 port_xmit_constraint_errors[0x8]; 8800 8801 u8 port_rcv_constraint_errors[0x8]; 8802 8803 u8 reserved_at_70[0x8]; 8804 8805 u8 link_overrun_errors[0x8]; 8806 8807 u8 reserved_at_80[0x10]; 8808 8809 u8 vl_15_dropped[0x10]; 8810 8811 u8 reserved_at_a0[0xa0]; 8812 }; 8813 8814 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 8815 u8 time_since_last_clear_high[0x20]; 8816 8817 u8 time_since_last_clear_low[0x20]; 8818 8819 u8 phy_received_bits_high[0x20]; 8820 8821 u8 phy_received_bits_low[0x20]; 8822 8823 u8 phy_symbol_errors_high[0x20]; 8824 8825 u8 phy_symbol_errors_low[0x20]; 8826 8827 u8 phy_corrected_bits_high[0x20]; 8828 8829 u8 phy_corrected_bits_low[0x20]; 8830 8831 u8 phy_corrected_bits_lane0_high[0x20]; 8832 8833 u8 phy_corrected_bits_lane0_low[0x20]; 8834 8835 u8 phy_corrected_bits_lane1_high[0x20]; 8836 8837 u8 phy_corrected_bits_lane1_low[0x20]; 8838 8839 u8 phy_corrected_bits_lane2_high[0x20]; 8840 8841 u8 phy_corrected_bits_lane2_low[0x20]; 8842 8843 u8 phy_corrected_bits_lane3_high[0x20]; 8844 8845 u8 phy_corrected_bits_lane3_low[0x20]; 8846 8847 u8 reserved_at_200[0x5c0]; 8848 }; 8849 8850 struct mlx5_ifc_infiniband_port_cntrs_bits { 8851 u8 symbol_error_counter[0x10]; 8852 u8 link_error_recovery_counter[0x8]; 8853 u8 link_downed_counter[0x8]; 8854 8855 u8 port_rcv_errors[0x10]; 8856 u8 port_rcv_remote_physical_errors[0x10]; 8857 8858 u8 port_rcv_switch_relay_errors[0x10]; 8859 u8 port_xmit_discards[0x10]; 8860 8861 u8 port_xmit_constraint_errors[0x8]; 8862 u8 port_rcv_constraint_errors[0x8]; 8863 u8 reserved_0[0x8]; 8864 u8 local_link_integrity_errors[0x4]; 8865 u8 excessive_buffer_overrun_errors[0x4]; 8866 8867 u8 reserved_1[0x10]; 8868 u8 vl_15_dropped[0x10]; 8869 8870 u8 port_xmit_data[0x20]; 8871 8872 u8 port_rcv_data[0x20]; 8873 8874 u8 port_xmit_pkts[0x20]; 8875 8876 u8 port_rcv_pkts[0x20]; 8877 8878 u8 port_xmit_wait[0x20]; 8879 8880 u8 reserved_2[0x680]; 8881 }; 8882 8883 struct mlx5_ifc_phrr_reg_bits { 8884 u8 clr[0x1]; 8885 u8 reserved_0[0x7]; 8886 u8 local_port[0x8]; 8887 u8 reserved_1[0x10]; 8888 8889 u8 hist_group[0x8]; 8890 u8 reserved_2[0x10]; 8891 u8 hist_id[0x8]; 8892 8893 u8 reserved_3[0x40]; 8894 8895 u8 time_since_last_clear_high[0x20]; 8896 8897 u8 time_since_last_clear_low[0x20]; 8898 8899 u8 bin[10][0x20]; 8900 }; 8901 8902 struct mlx5_ifc_phbr_for_prio_reg_bits { 8903 u8 reserved_0[0x18]; 8904 u8 prio[0x8]; 8905 }; 8906 8907 struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8908 u8 reserved_0[0x18]; 8909 u8 tclass[0x8]; 8910 }; 8911 8912 struct mlx5_ifc_phbr_binding_reg_bits { 8913 u8 opcode[0x4]; 8914 u8 reserved_0[0x4]; 8915 u8 local_port[0x8]; 8916 u8 pnat[0x2]; 8917 u8 reserved_1[0xe]; 8918 8919 u8 hist_group[0x8]; 8920 u8 reserved_2[0x10]; 8921 u8 hist_id[0x8]; 8922 8923 u8 reserved_3[0x10]; 8924 u8 hist_type[0x10]; 8925 8926 u8 hist_parameters[0x20]; 8927 8928 u8 hist_min_value[0x20]; 8929 8930 u8 hist_max_value[0x20]; 8931 8932 u8 sample_time[0x20]; 8933 }; 8934 8935 enum { 8936 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 8937 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 8938 }; 8939 8940 struct mlx5_ifc_pfcc_reg_bits { 8941 u8 dcbx_operation_type[0x2]; 8942 u8 cap_local_admin[0x1]; 8943 u8 cap_remote_admin[0x1]; 8944 u8 reserved_0[0x4]; 8945 u8 local_port[0x8]; 8946 u8 pnat[0x2]; 8947 u8 reserved_1[0xc]; 8948 u8 shl_cap[0x1]; 8949 u8 shl_opr[0x1]; 8950 8951 u8 ppan[0x4]; 8952 u8 reserved_2[0x4]; 8953 u8 prio_mask_tx[0x8]; 8954 u8 reserved_3[0x8]; 8955 u8 prio_mask_rx[0x8]; 8956 8957 u8 pptx[0x1]; 8958 u8 aptx[0x1]; 8959 u8 reserved_4[0x6]; 8960 u8 pfctx[0x8]; 8961 u8 reserved_5[0x8]; 8962 u8 cbftx[0x8]; 8963 8964 u8 pprx[0x1]; 8965 u8 aprx[0x1]; 8966 u8 reserved_6[0x6]; 8967 u8 pfcrx[0x8]; 8968 u8 reserved_7[0x8]; 8969 u8 cbfrx[0x8]; 8970 8971 u8 device_stall_minor_watermark[0x10]; 8972 u8 device_stall_critical_watermark[0x10]; 8973 8974 u8 reserved_8[0x60]; 8975 }; 8976 8977 struct mlx5_ifc_pelc_reg_bits { 8978 u8 op[0x4]; 8979 u8 reserved_0[0x4]; 8980 u8 local_port[0x8]; 8981 u8 reserved_1[0x10]; 8982 8983 u8 op_admin[0x8]; 8984 u8 op_capability[0x8]; 8985 u8 op_request[0x8]; 8986 u8 op_active[0x8]; 8987 8988 u8 admin[0x40]; 8989 8990 u8 capability[0x40]; 8991 8992 u8 request[0x40]; 8993 8994 u8 active[0x40]; 8995 8996 u8 reserved_2[0x80]; 8997 }; 8998 8999 struct mlx5_ifc_peir_reg_bits { 9000 u8 reserved_0[0x8]; 9001 u8 local_port[0x8]; 9002 u8 reserved_1[0x10]; 9003 9004 u8 reserved_2[0xc]; 9005 u8 error_count[0x4]; 9006 u8 reserved_3[0x10]; 9007 9008 u8 reserved_4[0xc]; 9009 u8 lane[0x4]; 9010 u8 reserved_5[0x8]; 9011 u8 error_type[0x8]; 9012 }; 9013 9014 struct mlx5_ifc_qcam_access_reg_cap_mask { 9015 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9016 u8 qpdpm[0x1]; 9017 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9018 u8 qdpm[0x1]; 9019 u8 qpts[0x1]; 9020 u8 qcap[0x1]; 9021 u8 qcam_access_reg_cap_mask_0[0x1]; 9022 }; 9023 9024 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9025 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9026 u8 qpts_trust_both[0x1]; 9027 }; 9028 9029 struct mlx5_ifc_qcam_reg_bits { 9030 u8 reserved_at_0[0x8]; 9031 u8 feature_group[0x8]; 9032 u8 reserved_at_10[0x8]; 9033 u8 access_reg_group[0x8]; 9034 u8 reserved_at_20[0x20]; 9035 9036 union { 9037 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9038 u8 reserved_at_0[0x80]; 9039 } qos_access_reg_cap_mask; 9040 9041 u8 reserved_at_c0[0x80]; 9042 9043 union { 9044 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9045 u8 reserved_at_0[0x80]; 9046 } qos_feature_cap_mask; 9047 9048 u8 reserved_at_1c0[0x80]; 9049 }; 9050 9051 struct mlx5_ifc_pcam_enhanced_features_bits { 9052 u8 reserved_at_0[0x6d]; 9053 u8 rx_icrc_encapsulated_counter[0x1]; 9054 u8 reserved_at_6e[0x4]; 9055 u8 ptys_extended_ethernet[0x1]; 9056 u8 reserved_at_73[0x3]; 9057 u8 pfcc_mask[0x1]; 9058 u8 reserved_at_77[0x3]; 9059 u8 per_lane_error_counters[0x1]; 9060 u8 rx_buffer_fullness_counters[0x1]; 9061 u8 ptys_connector_type[0x1]; 9062 u8 reserved_at_7d[0x1]; 9063 u8 ppcnt_discard_group[0x1]; 9064 u8 ppcnt_statistical_group[0x1]; 9065 }; 9066 9067 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9068 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9069 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9070 9071 u8 reserved_at_40[0xe]; 9072 u8 pddr[0x1]; 9073 u8 reserved_at_4f[0xd]; 9074 9075 u8 pplm[0x1]; 9076 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9077 9078 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9079 u8 pbmc[0x1]; 9080 u8 pptb[0x1]; 9081 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9082 u8 ppcnt[0x1]; 9083 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9084 }; 9085 9086 struct mlx5_ifc_pcam_reg_bits { 9087 u8 reserved_at_0[0x8]; 9088 u8 feature_group[0x8]; 9089 u8 reserved_at_10[0x8]; 9090 u8 access_reg_group[0x8]; 9091 9092 u8 reserved_at_20[0x20]; 9093 9094 union { 9095 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9096 u8 reserved_at_0[0x80]; 9097 } port_access_reg_cap_mask; 9098 9099 u8 reserved_at_c0[0x80]; 9100 9101 union { 9102 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9103 u8 reserved_at_0[0x80]; 9104 } feature_cap_mask; 9105 9106 u8 reserved_at_1c0[0xc0]; 9107 }; 9108 9109 struct mlx5_ifc_mcam_enhanced_features_bits { 9110 u8 reserved_at_0[0x6e]; 9111 u8 pcie_status_and_power[0x1]; 9112 u8 reserved_at_111[0x10]; 9113 u8 pcie_performance_group[0x1]; 9114 }; 9115 9116 struct mlx5_ifc_mcam_access_reg_bits { 9117 u8 reserved_at_0[0x1c]; 9118 u8 mcda[0x1]; 9119 u8 mcc[0x1]; 9120 u8 mcqi[0x1]; 9121 u8 reserved_at_1f[0x1]; 9122 9123 u8 regs_95_to_64[0x20]; 9124 u8 regs_63_to_32[0x20]; 9125 u8 regs_31_to_0[0x20]; 9126 }; 9127 9128 struct mlx5_ifc_mcam_reg_bits { 9129 u8 reserved_at_0[0x8]; 9130 u8 feature_group[0x8]; 9131 u8 reserved_at_10[0x8]; 9132 u8 access_reg_group[0x8]; 9133 9134 u8 reserved_at_20[0x20]; 9135 9136 union { 9137 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9138 u8 reserved_at_0[0x80]; 9139 } mng_access_reg_cap_mask; 9140 9141 u8 reserved_at_c0[0x80]; 9142 9143 union { 9144 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9145 u8 reserved_at_0[0x80]; 9146 } mng_feature_cap_mask; 9147 9148 u8 reserved_at_1c0[0x80]; 9149 }; 9150 9151 struct mlx5_ifc_pcap_reg_bits { 9152 u8 reserved_0[0x8]; 9153 u8 local_port[0x8]; 9154 u8 reserved_1[0x10]; 9155 9156 u8 port_capability_mask[4][0x20]; 9157 }; 9158 9159 struct mlx5_ifc_pbmc_reg_bits { 9160 u8 reserved_at_0[0x8]; 9161 u8 local_port[0x8]; 9162 u8 reserved_at_10[0x10]; 9163 9164 u8 xoff_timer_value[0x10]; 9165 u8 xoff_refresh[0x10]; 9166 9167 u8 reserved_at_40[0x9]; 9168 u8 fullness_threshold[0x7]; 9169 u8 port_buffer_size[0x10]; 9170 9171 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9172 9173 u8 reserved_at_2e0[0x80]; 9174 }; 9175 9176 struct mlx5_ifc_paos_reg_bits { 9177 u8 swid[0x8]; 9178 u8 local_port[0x8]; 9179 u8 reserved_0[0x4]; 9180 u8 admin_status[0x4]; 9181 u8 reserved_1[0x4]; 9182 u8 oper_status[0x4]; 9183 9184 u8 ase[0x1]; 9185 u8 ee[0x1]; 9186 u8 reserved_2[0x1c]; 9187 u8 e[0x2]; 9188 9189 u8 reserved_3[0x40]; 9190 }; 9191 9192 struct mlx5_ifc_pamp_reg_bits { 9193 u8 reserved_0[0x8]; 9194 u8 opamp_group[0x8]; 9195 u8 reserved_1[0xc]; 9196 u8 opamp_group_type[0x4]; 9197 9198 u8 start_index[0x10]; 9199 u8 reserved_2[0x4]; 9200 u8 num_of_indices[0xc]; 9201 9202 u8 index_data[18][0x10]; 9203 }; 9204 9205 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 9206 u8 llr_rx_cells_high[0x20]; 9207 9208 u8 llr_rx_cells_low[0x20]; 9209 9210 u8 llr_rx_error_high[0x20]; 9211 9212 u8 llr_rx_error_low[0x20]; 9213 9214 u8 llr_rx_crc_error_high[0x20]; 9215 9216 u8 llr_rx_crc_error_low[0x20]; 9217 9218 u8 llr_tx_cells_high[0x20]; 9219 9220 u8 llr_tx_cells_low[0x20]; 9221 9222 u8 llr_tx_ret_cells_high[0x20]; 9223 9224 u8 llr_tx_ret_cells_low[0x20]; 9225 9226 u8 llr_tx_ret_events_high[0x20]; 9227 9228 u8 llr_tx_ret_events_low[0x20]; 9229 9230 u8 reserved_0[0x640]; 9231 }; 9232 9233 struct mlx5_ifc_mtmp_reg_bits { 9234 u8 i[0x1]; 9235 u8 reserved_at_1[0x18]; 9236 u8 sensor_index[0x7]; 9237 9238 u8 reserved_at_20[0x10]; 9239 u8 temperature[0x10]; 9240 9241 u8 mte[0x1]; 9242 u8 mtr[0x1]; 9243 u8 reserved_at_42[0x0e]; 9244 u8 max_temperature[0x10]; 9245 9246 u8 tee[0x2]; 9247 u8 reserved_at_62[0x0e]; 9248 u8 temperature_threshold_hi[0x10]; 9249 9250 u8 reserved_at_80[0x10]; 9251 u8 temperature_threshold_lo[0x10]; 9252 9253 u8 reserved_at_100[0x20]; 9254 9255 u8 sensor_name[0x40]; 9256 }; 9257 9258 struct mlx5_ifc_lane_2_module_mapping_bits { 9259 u8 reserved_0[0x6]; 9260 u8 rx_lane[0x2]; 9261 u8 reserved_1[0x6]; 9262 u8 tx_lane[0x2]; 9263 u8 reserved_2[0x8]; 9264 u8 module[0x8]; 9265 }; 9266 9267 struct mlx5_ifc_eth_per_traffic_class_layout_bits { 9268 u8 transmit_queue_high[0x20]; 9269 9270 u8 transmit_queue_low[0x20]; 9271 9272 u8 reserved_0[0x780]; 9273 }; 9274 9275 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 9276 u8 no_buffer_discard_uc_high[0x20]; 9277 9278 u8 no_buffer_discard_uc_low[0x20]; 9279 9280 u8 wred_discard_high[0x20]; 9281 9282 u8 wred_discard_low[0x20]; 9283 9284 u8 reserved_0[0x740]; 9285 }; 9286 9287 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 9288 u8 rx_octets_high[0x20]; 9289 9290 u8 rx_octets_low[0x20]; 9291 9292 u8 reserved_0[0xc0]; 9293 9294 u8 rx_frames_high[0x20]; 9295 9296 u8 rx_frames_low[0x20]; 9297 9298 u8 tx_octets_high[0x20]; 9299 9300 u8 tx_octets_low[0x20]; 9301 9302 u8 reserved_1[0xc0]; 9303 9304 u8 tx_frames_high[0x20]; 9305 9306 u8 tx_frames_low[0x20]; 9307 9308 u8 rx_pause_high[0x20]; 9309 9310 u8 rx_pause_low[0x20]; 9311 9312 u8 rx_pause_duration_high[0x20]; 9313 9314 u8 rx_pause_duration_low[0x20]; 9315 9316 u8 tx_pause_high[0x20]; 9317 9318 u8 tx_pause_low[0x20]; 9319 9320 u8 tx_pause_duration_high[0x20]; 9321 9322 u8 tx_pause_duration_low[0x20]; 9323 9324 u8 rx_pause_transition_high[0x20]; 9325 9326 u8 rx_pause_transition_low[0x20]; 9327 9328 u8 rx_discards_high[0x20]; 9329 9330 u8 rx_discards_low[0x20]; 9331 9332 u8 device_stall_minor_watermark_cnt_high[0x20]; 9333 9334 u8 device_stall_minor_watermark_cnt_low[0x20]; 9335 9336 u8 device_stall_critical_watermark_cnt_high[0x20]; 9337 9338 u8 device_stall_critical_watermark_cnt_low[0x20]; 9339 9340 u8 reserved_2[0x340]; 9341 }; 9342 9343 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 9344 u8 port_transmit_wait_high[0x20]; 9345 9346 u8 port_transmit_wait_low[0x20]; 9347 9348 u8 ecn_marked_high[0x20]; 9349 9350 u8 ecn_marked_low[0x20]; 9351 9352 u8 no_buffer_discard_mc_high[0x20]; 9353 9354 u8 no_buffer_discard_mc_low[0x20]; 9355 9356 u8 rx_ebp_high[0x20]; 9357 9358 u8 rx_ebp_low[0x20]; 9359 9360 u8 tx_ebp_high[0x20]; 9361 9362 u8 tx_ebp_low[0x20]; 9363 9364 u8 rx_buffer_almost_full_high[0x20]; 9365 9366 u8 rx_buffer_almost_full_low[0x20]; 9367 9368 u8 rx_buffer_full_high[0x20]; 9369 9370 u8 rx_buffer_full_low[0x20]; 9371 9372 u8 rx_icrc_encapsulated_high[0x20]; 9373 9374 u8 rx_icrc_encapsulated_low[0x20]; 9375 9376 u8 reserved_0[0x80]; 9377 9378 u8 tx_stats_pkts64octets_high[0x20]; 9379 9380 u8 tx_stats_pkts64octets_low[0x20]; 9381 9382 u8 tx_stats_pkts65to127octets_high[0x20]; 9383 9384 u8 tx_stats_pkts65to127octets_low[0x20]; 9385 9386 u8 tx_stats_pkts128to255octets_high[0x20]; 9387 9388 u8 tx_stats_pkts128to255octets_low[0x20]; 9389 9390 u8 tx_stats_pkts256to511octets_high[0x20]; 9391 9392 u8 tx_stats_pkts256to511octets_low[0x20]; 9393 9394 u8 tx_stats_pkts512to1023octets_high[0x20]; 9395 9396 u8 tx_stats_pkts512to1023octets_low[0x20]; 9397 9398 u8 tx_stats_pkts1024to1518octets_high[0x20]; 9399 9400 u8 tx_stats_pkts1024to1518octets_low[0x20]; 9401 9402 u8 tx_stats_pkts1519to2047octets_high[0x20]; 9403 9404 u8 tx_stats_pkts1519to2047octets_low[0x20]; 9405 9406 u8 tx_stats_pkts2048to4095octets_high[0x20]; 9407 9408 u8 tx_stats_pkts2048to4095octets_low[0x20]; 9409 9410 u8 tx_stats_pkts4096to8191octets_high[0x20]; 9411 9412 u8 tx_stats_pkts4096to8191octets_low[0x20]; 9413 9414 u8 tx_stats_pkts8192to10239octets_high[0x20]; 9415 9416 u8 tx_stats_pkts8192to10239octets_low[0x20]; 9417 9418 u8 reserved_1[0x2C0]; 9419 }; 9420 9421 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 9422 u8 a_frames_transmitted_ok_high[0x20]; 9423 9424 u8 a_frames_transmitted_ok_low[0x20]; 9425 9426 u8 a_frames_received_ok_high[0x20]; 9427 9428 u8 a_frames_received_ok_low[0x20]; 9429 9430 u8 a_frame_check_sequence_errors_high[0x20]; 9431 9432 u8 a_frame_check_sequence_errors_low[0x20]; 9433 9434 u8 a_alignment_errors_high[0x20]; 9435 9436 u8 a_alignment_errors_low[0x20]; 9437 9438 u8 a_octets_transmitted_ok_high[0x20]; 9439 9440 u8 a_octets_transmitted_ok_low[0x20]; 9441 9442 u8 a_octets_received_ok_high[0x20]; 9443 9444 u8 a_octets_received_ok_low[0x20]; 9445 9446 u8 a_multicast_frames_xmitted_ok_high[0x20]; 9447 9448 u8 a_multicast_frames_xmitted_ok_low[0x20]; 9449 9450 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 9451 9452 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 9453 9454 u8 a_multicast_frames_received_ok_high[0x20]; 9455 9456 u8 a_multicast_frames_received_ok_low[0x20]; 9457 9458 u8 a_broadcast_frames_recieved_ok_high[0x20]; 9459 9460 u8 a_broadcast_frames_recieved_ok_low[0x20]; 9461 9462 u8 a_in_range_length_errors_high[0x20]; 9463 9464 u8 a_in_range_length_errors_low[0x20]; 9465 9466 u8 a_out_of_range_length_field_high[0x20]; 9467 9468 u8 a_out_of_range_length_field_low[0x20]; 9469 9470 u8 a_frame_too_long_errors_high[0x20]; 9471 9472 u8 a_frame_too_long_errors_low[0x20]; 9473 9474 u8 a_symbol_error_during_carrier_high[0x20]; 9475 9476 u8 a_symbol_error_during_carrier_low[0x20]; 9477 9478 u8 a_mac_control_frames_transmitted_high[0x20]; 9479 9480 u8 a_mac_control_frames_transmitted_low[0x20]; 9481 9482 u8 a_mac_control_frames_received_high[0x20]; 9483 9484 u8 a_mac_control_frames_received_low[0x20]; 9485 9486 u8 a_unsupported_opcodes_received_high[0x20]; 9487 9488 u8 a_unsupported_opcodes_received_low[0x20]; 9489 9490 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 9491 9492 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 9493 9494 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 9495 9496 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 9497 9498 u8 reserved_0[0x300]; 9499 }; 9500 9501 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 9502 u8 dot3stats_alignment_errors_high[0x20]; 9503 9504 u8 dot3stats_alignment_errors_low[0x20]; 9505 9506 u8 dot3stats_fcs_errors_high[0x20]; 9507 9508 u8 dot3stats_fcs_errors_low[0x20]; 9509 9510 u8 dot3stats_single_collision_frames_high[0x20]; 9511 9512 u8 dot3stats_single_collision_frames_low[0x20]; 9513 9514 u8 dot3stats_multiple_collision_frames_high[0x20]; 9515 9516 u8 dot3stats_multiple_collision_frames_low[0x20]; 9517 9518 u8 dot3stats_sqe_test_errors_high[0x20]; 9519 9520 u8 dot3stats_sqe_test_errors_low[0x20]; 9521 9522 u8 dot3stats_deferred_transmissions_high[0x20]; 9523 9524 u8 dot3stats_deferred_transmissions_low[0x20]; 9525 9526 u8 dot3stats_late_collisions_high[0x20]; 9527 9528 u8 dot3stats_late_collisions_low[0x20]; 9529 9530 u8 dot3stats_excessive_collisions_high[0x20]; 9531 9532 u8 dot3stats_excessive_collisions_low[0x20]; 9533 9534 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 9535 9536 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 9537 9538 u8 dot3stats_carrier_sense_errors_high[0x20]; 9539 9540 u8 dot3stats_carrier_sense_errors_low[0x20]; 9541 9542 u8 dot3stats_frame_too_longs_high[0x20]; 9543 9544 u8 dot3stats_frame_too_longs_low[0x20]; 9545 9546 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 9547 9548 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 9549 9550 u8 dot3stats_symbol_errors_high[0x20]; 9551 9552 u8 dot3stats_symbol_errors_low[0x20]; 9553 9554 u8 dot3control_in_unknown_opcodes_high[0x20]; 9555 9556 u8 dot3control_in_unknown_opcodes_low[0x20]; 9557 9558 u8 dot3in_pause_frames_high[0x20]; 9559 9560 u8 dot3in_pause_frames_low[0x20]; 9561 9562 u8 dot3out_pause_frames_high[0x20]; 9563 9564 u8 dot3out_pause_frames_low[0x20]; 9565 9566 u8 reserved_0[0x3c0]; 9567 }; 9568 9569 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 9570 u8 if_in_octets_high[0x20]; 9571 9572 u8 if_in_octets_low[0x20]; 9573 9574 u8 if_in_ucast_pkts_high[0x20]; 9575 9576 u8 if_in_ucast_pkts_low[0x20]; 9577 9578 u8 if_in_discards_high[0x20]; 9579 9580 u8 if_in_discards_low[0x20]; 9581 9582 u8 if_in_errors_high[0x20]; 9583 9584 u8 if_in_errors_low[0x20]; 9585 9586 u8 if_in_unknown_protos_high[0x20]; 9587 9588 u8 if_in_unknown_protos_low[0x20]; 9589 9590 u8 if_out_octets_high[0x20]; 9591 9592 u8 if_out_octets_low[0x20]; 9593 9594 u8 if_out_ucast_pkts_high[0x20]; 9595 9596 u8 if_out_ucast_pkts_low[0x20]; 9597 9598 u8 if_out_discards_high[0x20]; 9599 9600 u8 if_out_discards_low[0x20]; 9601 9602 u8 if_out_errors_high[0x20]; 9603 9604 u8 if_out_errors_low[0x20]; 9605 9606 u8 if_in_multicast_pkts_high[0x20]; 9607 9608 u8 if_in_multicast_pkts_low[0x20]; 9609 9610 u8 if_in_broadcast_pkts_high[0x20]; 9611 9612 u8 if_in_broadcast_pkts_low[0x20]; 9613 9614 u8 if_out_multicast_pkts_high[0x20]; 9615 9616 u8 if_out_multicast_pkts_low[0x20]; 9617 9618 u8 if_out_broadcast_pkts_high[0x20]; 9619 9620 u8 if_out_broadcast_pkts_low[0x20]; 9621 9622 u8 reserved_0[0x480]; 9623 }; 9624 9625 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 9626 u8 ether_stats_drop_events_high[0x20]; 9627 9628 u8 ether_stats_drop_events_low[0x20]; 9629 9630 u8 ether_stats_octets_high[0x20]; 9631 9632 u8 ether_stats_octets_low[0x20]; 9633 9634 u8 ether_stats_pkts_high[0x20]; 9635 9636 u8 ether_stats_pkts_low[0x20]; 9637 9638 u8 ether_stats_broadcast_pkts_high[0x20]; 9639 9640 u8 ether_stats_broadcast_pkts_low[0x20]; 9641 9642 u8 ether_stats_multicast_pkts_high[0x20]; 9643 9644 u8 ether_stats_multicast_pkts_low[0x20]; 9645 9646 u8 ether_stats_crc_align_errors_high[0x20]; 9647 9648 u8 ether_stats_crc_align_errors_low[0x20]; 9649 9650 u8 ether_stats_undersize_pkts_high[0x20]; 9651 9652 u8 ether_stats_undersize_pkts_low[0x20]; 9653 9654 u8 ether_stats_oversize_pkts_high[0x20]; 9655 9656 u8 ether_stats_oversize_pkts_low[0x20]; 9657 9658 u8 ether_stats_fragments_high[0x20]; 9659 9660 u8 ether_stats_fragments_low[0x20]; 9661 9662 u8 ether_stats_jabbers_high[0x20]; 9663 9664 u8 ether_stats_jabbers_low[0x20]; 9665 9666 u8 ether_stats_collisions_high[0x20]; 9667 9668 u8 ether_stats_collisions_low[0x20]; 9669 9670 u8 ether_stats_pkts64octets_high[0x20]; 9671 9672 u8 ether_stats_pkts64octets_low[0x20]; 9673 9674 u8 ether_stats_pkts65to127octets_high[0x20]; 9675 9676 u8 ether_stats_pkts65to127octets_low[0x20]; 9677 9678 u8 ether_stats_pkts128to255octets_high[0x20]; 9679 9680 u8 ether_stats_pkts128to255octets_low[0x20]; 9681 9682 u8 ether_stats_pkts256to511octets_high[0x20]; 9683 9684 u8 ether_stats_pkts256to511octets_low[0x20]; 9685 9686 u8 ether_stats_pkts512to1023octets_high[0x20]; 9687 9688 u8 ether_stats_pkts512to1023octets_low[0x20]; 9689 9690 u8 ether_stats_pkts1024to1518octets_high[0x20]; 9691 9692 u8 ether_stats_pkts1024to1518octets_low[0x20]; 9693 9694 u8 ether_stats_pkts1519to2047octets_high[0x20]; 9695 9696 u8 ether_stats_pkts1519to2047octets_low[0x20]; 9697 9698 u8 ether_stats_pkts2048to4095octets_high[0x20]; 9699 9700 u8 ether_stats_pkts2048to4095octets_low[0x20]; 9701 9702 u8 ether_stats_pkts4096to8191octets_high[0x20]; 9703 9704 u8 ether_stats_pkts4096to8191octets_low[0x20]; 9705 9706 u8 ether_stats_pkts8192to10239octets_high[0x20]; 9707 9708 u8 ether_stats_pkts8192to10239octets_low[0x20]; 9709 9710 u8 reserved_0[0x280]; 9711 }; 9712 9713 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 9714 u8 symbol_error_counter[0x10]; 9715 u8 link_error_recovery_counter[0x8]; 9716 u8 link_downed_counter[0x8]; 9717 9718 u8 port_rcv_errors[0x10]; 9719 u8 port_rcv_remote_physical_errors[0x10]; 9720 9721 u8 port_rcv_switch_relay_errors[0x10]; 9722 u8 port_xmit_discards[0x10]; 9723 9724 u8 port_xmit_constraint_errors[0x8]; 9725 u8 port_rcv_constraint_errors[0x8]; 9726 u8 reserved_0[0x8]; 9727 u8 local_link_integrity_errors[0x4]; 9728 u8 excessive_buffer_overrun_errors[0x4]; 9729 9730 u8 reserved_1[0x10]; 9731 u8 vl_15_dropped[0x10]; 9732 9733 u8 port_xmit_data[0x20]; 9734 9735 u8 port_rcv_data[0x20]; 9736 9737 u8 port_xmit_pkts[0x20]; 9738 9739 u8 port_rcv_pkts[0x20]; 9740 9741 u8 port_xmit_wait[0x20]; 9742 9743 u8 reserved_2[0x680]; 9744 }; 9745 9746 struct mlx5_ifc_trc_tlb_reg_bits { 9747 u8 reserved_0[0x80]; 9748 9749 u8 tlb_addr[0][0x40]; 9750 }; 9751 9752 struct mlx5_ifc_trc_read_fifo_reg_bits { 9753 u8 reserved_0[0x10]; 9754 u8 requested_event_num[0x10]; 9755 9756 u8 reserved_1[0x20]; 9757 9758 u8 reserved_2[0x10]; 9759 u8 acual_event_num[0x10]; 9760 9761 u8 reserved_3[0x20]; 9762 9763 u8 event[0][0x40]; 9764 }; 9765 9766 struct mlx5_ifc_trc_lock_reg_bits { 9767 u8 reserved_0[0x1f]; 9768 u8 lock[0x1]; 9769 9770 u8 reserved_1[0x60]; 9771 }; 9772 9773 struct mlx5_ifc_trc_filter_reg_bits { 9774 u8 status[0x1]; 9775 u8 reserved_0[0xf]; 9776 u8 filter_index[0x10]; 9777 9778 u8 reserved_1[0x20]; 9779 9780 u8 filter_val[0x20]; 9781 9782 u8 reserved_2[0x1a0]; 9783 }; 9784 9785 struct mlx5_ifc_trc_event_reg_bits { 9786 u8 status[0x1]; 9787 u8 reserved_0[0xf]; 9788 u8 event_index[0x10]; 9789 9790 u8 reserved_1[0x20]; 9791 9792 u8 event_id[0x20]; 9793 9794 u8 event_selector_val[0x10]; 9795 u8 event_selector_size[0x10]; 9796 9797 u8 reserved_2[0x180]; 9798 }; 9799 9800 struct mlx5_ifc_trc_conf_reg_bits { 9801 u8 limit_en[0x1]; 9802 u8 reserved_0[0x3]; 9803 u8 dump_mode[0x4]; 9804 u8 reserved_1[0x15]; 9805 u8 state[0x3]; 9806 9807 u8 reserved_2[0x20]; 9808 9809 u8 limit_event_index[0x20]; 9810 9811 u8 mkey[0x20]; 9812 9813 u8 fifo_ready_ev_num[0x20]; 9814 9815 u8 reserved_3[0x160]; 9816 }; 9817 9818 struct mlx5_ifc_trc_cap_reg_bits { 9819 u8 reserved_0[0x18]; 9820 u8 dump_mode[0x8]; 9821 9822 u8 reserved_1[0x20]; 9823 9824 u8 num_of_events[0x10]; 9825 u8 num_of_filters[0x10]; 9826 9827 u8 fifo_size[0x20]; 9828 9829 u8 tlb_size[0x10]; 9830 u8 event_size[0x10]; 9831 9832 u8 reserved_2[0x160]; 9833 }; 9834 9835 struct mlx5_ifc_set_node_in_bits { 9836 u8 node_description[64][0x8]; 9837 }; 9838 9839 struct mlx5_ifc_register_power_settings_bits { 9840 u8 reserved_0[0x18]; 9841 u8 power_settings_level[0x8]; 9842 9843 u8 reserved_1[0x60]; 9844 }; 9845 9846 struct mlx5_ifc_register_host_endianess_bits { 9847 u8 he[0x1]; 9848 u8 reserved_0[0x1f]; 9849 9850 u8 reserved_1[0x60]; 9851 }; 9852 9853 struct mlx5_ifc_register_diag_buffer_ctrl_bits { 9854 u8 physical_address[0x40]; 9855 }; 9856 9857 struct mlx5_ifc_qtct_reg_bits { 9858 u8 operation_type[0x2]; 9859 u8 cap_local_admin[0x1]; 9860 u8 cap_remote_admin[0x1]; 9861 u8 reserved_0[0x4]; 9862 u8 port_number[0x8]; 9863 u8 reserved_1[0xd]; 9864 u8 prio[0x3]; 9865 9866 u8 reserved_2[0x1d]; 9867 u8 tclass[0x3]; 9868 }; 9869 9870 struct mlx5_ifc_qpdp_reg_bits { 9871 u8 reserved_0[0x8]; 9872 u8 port_number[0x8]; 9873 u8 reserved_1[0x10]; 9874 9875 u8 reserved_2[0x1d]; 9876 u8 pprio[0x3]; 9877 }; 9878 9879 struct mlx5_ifc_port_info_ro_fields_param_bits { 9880 u8 reserved_0[0x8]; 9881 u8 port[0x8]; 9882 u8 max_gid[0x10]; 9883 9884 u8 reserved_1[0x20]; 9885 9886 u8 port_guid[0x40]; 9887 }; 9888 9889 struct mlx5_ifc_nvqc_reg_bits { 9890 u8 type[0x20]; 9891 9892 u8 reserved_0[0x18]; 9893 u8 version[0x4]; 9894 u8 reserved_1[0x2]; 9895 u8 support_wr[0x1]; 9896 u8 support_rd[0x1]; 9897 }; 9898 9899 struct mlx5_ifc_nvia_reg_bits { 9900 u8 reserved_0[0x1d]; 9901 u8 target[0x3]; 9902 9903 u8 reserved_1[0x20]; 9904 }; 9905 9906 struct mlx5_ifc_nvdi_reg_bits { 9907 struct mlx5_ifc_config_item_bits configuration_item_header; 9908 }; 9909 9910 struct mlx5_ifc_nvda_reg_bits { 9911 struct mlx5_ifc_config_item_bits configuration_item_header; 9912 9913 u8 configuration_item_data[0x20]; 9914 }; 9915 9916 struct mlx5_ifc_node_info_ro_fields_param_bits { 9917 u8 system_image_guid[0x40]; 9918 9919 u8 reserved_0[0x40]; 9920 9921 u8 node_guid[0x40]; 9922 9923 u8 reserved_1[0x10]; 9924 u8 max_pkey[0x10]; 9925 9926 u8 reserved_2[0x20]; 9927 }; 9928 9929 struct mlx5_ifc_ets_tcn_config_reg_bits { 9930 u8 g[0x1]; 9931 u8 b[0x1]; 9932 u8 r[0x1]; 9933 u8 reserved_0[0x9]; 9934 u8 group[0x4]; 9935 u8 reserved_1[0x9]; 9936 u8 bw_allocation[0x7]; 9937 9938 u8 reserved_2[0xc]; 9939 u8 max_bw_units[0x4]; 9940 u8 reserved_3[0x8]; 9941 u8 max_bw_value[0x8]; 9942 }; 9943 9944 struct mlx5_ifc_ets_global_config_reg_bits { 9945 u8 reserved_0[0x2]; 9946 u8 r[0x1]; 9947 u8 reserved_1[0x1d]; 9948 9949 u8 reserved_2[0xc]; 9950 u8 max_bw_units[0x4]; 9951 u8 reserved_3[0x8]; 9952 u8 max_bw_value[0x8]; 9953 }; 9954 9955 struct mlx5_ifc_qetc_reg_bits { 9956 u8 reserved_at_0[0x8]; 9957 u8 port_number[0x8]; 9958 u8 reserved_at_10[0x30]; 9959 9960 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9961 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9962 }; 9963 9964 struct mlx5_ifc_nodnic_mac_filters_bits { 9965 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 9966 9967 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 9968 9969 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 9970 9971 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 9972 9973 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 9974 9975 u8 reserved_0[0xc0]; 9976 }; 9977 9978 struct mlx5_ifc_nodnic_gid_filters_bits { 9979 u8 mgid_filter0[16][0x8]; 9980 9981 u8 mgid_filter1[16][0x8]; 9982 9983 u8 mgid_filter2[16][0x8]; 9984 9985 u8 mgid_filter3[16][0x8]; 9986 }; 9987 9988 enum { 9989 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 9990 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 9991 }; 9992 9993 enum { 9994 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 9995 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 9996 }; 9997 9998 struct mlx5_ifc_nodnic_config_reg_bits { 9999 u8 no_dram_nic_revision[0x8]; 10000 u8 hardware_format[0x8]; 10001 u8 support_receive_filter[0x1]; 10002 u8 support_promisc_filter[0x1]; 10003 u8 support_promisc_multicast_filter[0x1]; 10004 u8 reserved_0[0x2]; 10005 u8 log_working_buffer_size[0x3]; 10006 u8 log_pkey_table_size[0x4]; 10007 u8 reserved_1[0x3]; 10008 u8 num_ports[0x1]; 10009 10010 u8 reserved_2[0x2]; 10011 u8 log_max_ring_size[0x6]; 10012 u8 reserved_3[0x18]; 10013 10014 u8 lkey[0x20]; 10015 10016 u8 cqe_format[0x4]; 10017 u8 reserved_4[0x1c]; 10018 10019 u8 node_guid[0x40]; 10020 10021 u8 reserved_5[0x740]; 10022 10023 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 10024 10025 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 10026 }; 10027 10028 struct mlx5_ifc_vlan_layout_bits { 10029 u8 reserved_0[0x14]; 10030 u8 vlan[0xc]; 10031 10032 u8 reserved_1[0x20]; 10033 }; 10034 10035 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10036 u8 reserved_0[0x20]; 10037 10038 u8 mkey[0x20]; 10039 10040 u8 addressh_63_32[0x20]; 10041 10042 u8 addressl_31_0[0x20]; 10043 }; 10044 10045 struct mlx5_ifc_ud_adrs_vector_bits { 10046 u8 dc_key[0x40]; 10047 10048 u8 ext[0x1]; 10049 u8 reserved_0[0x7]; 10050 u8 destination_qp_dct[0x18]; 10051 10052 u8 static_rate[0x4]; 10053 u8 sl_eth_prio[0x4]; 10054 u8 fl[0x1]; 10055 u8 mlid[0x7]; 10056 u8 rlid_udp_sport[0x10]; 10057 10058 u8 reserved_1[0x20]; 10059 10060 u8 rmac_47_16[0x20]; 10061 10062 u8 rmac_15_0[0x10]; 10063 u8 tclass[0x8]; 10064 u8 hop_limit[0x8]; 10065 10066 u8 reserved_2[0x1]; 10067 u8 grh[0x1]; 10068 u8 reserved_3[0x2]; 10069 u8 src_addr_index[0x8]; 10070 u8 flow_label[0x14]; 10071 10072 u8 rgid_rip[16][0x8]; 10073 }; 10074 10075 struct mlx5_ifc_port_module_event_bits { 10076 u8 reserved_0[0x8]; 10077 u8 module[0x8]; 10078 u8 reserved_1[0xc]; 10079 u8 module_status[0x4]; 10080 10081 u8 reserved_2[0x14]; 10082 u8 error_type[0x4]; 10083 u8 reserved_3[0x8]; 10084 10085 u8 reserved_4[0xa0]; 10086 }; 10087 10088 struct mlx5_ifc_icmd_control_bits { 10089 u8 opcode[0x10]; 10090 u8 status[0x8]; 10091 u8 reserved_0[0x7]; 10092 u8 busy[0x1]; 10093 }; 10094 10095 struct mlx5_ifc_eqe_bits { 10096 u8 reserved_0[0x8]; 10097 u8 event_type[0x8]; 10098 u8 reserved_1[0x8]; 10099 u8 event_sub_type[0x8]; 10100 10101 u8 reserved_2[0xe0]; 10102 10103 union mlx5_ifc_event_auto_bits event_data; 10104 10105 u8 reserved_3[0x10]; 10106 u8 signature[0x8]; 10107 u8 reserved_4[0x7]; 10108 u8 owner[0x1]; 10109 }; 10110 10111 enum { 10112 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10113 }; 10114 10115 struct mlx5_ifc_cmd_queue_entry_bits { 10116 u8 type[0x8]; 10117 u8 reserved_0[0x18]; 10118 10119 u8 input_length[0x20]; 10120 10121 u8 input_mailbox_pointer_63_32[0x20]; 10122 10123 u8 input_mailbox_pointer_31_9[0x17]; 10124 u8 reserved_1[0x9]; 10125 10126 u8 command_input_inline_data[16][0x8]; 10127 10128 u8 command_output_inline_data[16][0x8]; 10129 10130 u8 output_mailbox_pointer_63_32[0x20]; 10131 10132 u8 output_mailbox_pointer_31_9[0x17]; 10133 u8 reserved_2[0x9]; 10134 10135 u8 output_length[0x20]; 10136 10137 u8 token[0x8]; 10138 u8 signature[0x8]; 10139 u8 reserved_3[0x8]; 10140 u8 status[0x7]; 10141 u8 ownership[0x1]; 10142 }; 10143 10144 struct mlx5_ifc_cmd_out_bits { 10145 u8 status[0x8]; 10146 u8 reserved_0[0x18]; 10147 10148 u8 syndrome[0x20]; 10149 10150 u8 command_output[0x20]; 10151 }; 10152 10153 struct mlx5_ifc_cmd_in_bits { 10154 u8 opcode[0x10]; 10155 u8 reserved_0[0x10]; 10156 10157 u8 reserved_1[0x10]; 10158 u8 op_mod[0x10]; 10159 10160 u8 command[0][0x20]; 10161 }; 10162 10163 struct mlx5_ifc_cmd_if_box_bits { 10164 u8 mailbox_data[512][0x8]; 10165 10166 u8 reserved_0[0x180]; 10167 10168 u8 next_pointer_63_32[0x20]; 10169 10170 u8 next_pointer_31_10[0x16]; 10171 u8 reserved_1[0xa]; 10172 10173 u8 block_number[0x20]; 10174 10175 u8 reserved_2[0x8]; 10176 u8 token[0x8]; 10177 u8 ctrl_signature[0x8]; 10178 u8 signature[0x8]; 10179 }; 10180 10181 struct mlx5_ifc_mtt_bits { 10182 u8 ptag_63_32[0x20]; 10183 10184 u8 ptag_31_8[0x18]; 10185 u8 reserved_0[0x6]; 10186 u8 wr_en[0x1]; 10187 u8 rd_en[0x1]; 10188 }; 10189 10190 struct mlx5_ifc_tls_progress_params_bits { 10191 u8 valid[0x1]; 10192 u8 reserved_at_1[0x7]; 10193 u8 pd[0x18]; 10194 10195 u8 next_record_tcp_sn[0x20]; 10196 10197 u8 hw_resync_tcp_sn[0x20]; 10198 10199 u8 record_tracker_state[0x2]; 10200 u8 auth_state[0x2]; 10201 u8 reserved_at_64[0x4]; 10202 u8 hw_offset_record_number[0x18]; 10203 }; 10204 10205 struct mlx5_ifc_tls_static_params_bits { 10206 u8 const_2[0x2]; 10207 u8 tls_version[0x4]; 10208 u8 const_1[0x2]; 10209 u8 reserved_at_8[0x14]; 10210 u8 encryption_standard[0x4]; 10211 10212 u8 reserved_at_20[0x20]; 10213 10214 u8 initial_record_number[0x40]; 10215 10216 u8 resync_tcp_sn[0x20]; 10217 10218 u8 gcm_iv[0x20]; 10219 10220 u8 implicit_iv[0x40]; 10221 10222 u8 reserved_at_100[0x8]; 10223 u8 dek_index[0x18]; 10224 10225 u8 reserved_at_120[0xe0]; 10226 }; 10227 10228 /* Vendor Specific Capabilities, VSC */ 10229 enum { 10230 MLX5_VSC_DOMAIN_ICMD = 0x1, 10231 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 10232 MLX5_VSC_DOMAIN_SCAN_CRSPACE = 0x7, 10233 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 10234 }; 10235 10236 struct mlx5_ifc_vendor_specific_cap_bits { 10237 u8 type[0x8]; 10238 u8 length[0x8]; 10239 u8 next_pointer[0x8]; 10240 u8 capability_id[0x8]; 10241 10242 u8 status[0x3]; 10243 u8 reserved_0[0xd]; 10244 u8 space[0x10]; 10245 10246 u8 counter[0x20]; 10247 10248 u8 semaphore[0x20]; 10249 10250 u8 flag[0x1]; 10251 u8 reserved_1[0x1]; 10252 u8 address[0x1e]; 10253 10254 u8 data[0x20]; 10255 }; 10256 10257 struct mlx5_ifc_vsc_space_bits { 10258 u8 status[0x3]; 10259 u8 reserved0[0xd]; 10260 u8 space[0x10]; 10261 }; 10262 10263 struct mlx5_ifc_vsc_addr_bits { 10264 u8 flag[0x1]; 10265 u8 reserved0[0x1]; 10266 u8 address[0x1e]; 10267 }; 10268 10269 enum { 10270 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10271 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10272 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10273 }; 10274 10275 enum { 10276 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10277 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10278 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10279 }; 10280 10281 enum { 10282 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 10283 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 10284 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 10285 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 10286 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 10287 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 10288 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 10289 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 10290 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 10291 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 10292 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 10293 }; 10294 10295 struct mlx5_ifc_initial_seg_bits { 10296 u8 fw_rev_minor[0x10]; 10297 u8 fw_rev_major[0x10]; 10298 10299 u8 cmd_interface_rev[0x10]; 10300 u8 fw_rev_subminor[0x10]; 10301 10302 u8 reserved_0[0x40]; 10303 10304 u8 cmdq_phy_addr_63_32[0x20]; 10305 10306 u8 cmdq_phy_addr_31_12[0x14]; 10307 u8 reserved_1[0x2]; 10308 u8 nic_interface[0x2]; 10309 u8 log_cmdq_size[0x4]; 10310 u8 log_cmdq_stride[0x4]; 10311 10312 u8 command_doorbell_vector[0x20]; 10313 10314 u8 reserved_2[0xf00]; 10315 10316 u8 initializing[0x1]; 10317 u8 reserved_3[0x4]; 10318 u8 nic_interface_supported[0x3]; 10319 u8 reserved_4[0x18]; 10320 10321 struct mlx5_ifc_health_buffer_bits health_buffer; 10322 10323 u8 no_dram_nic_offset[0x20]; 10324 10325 u8 reserved_5[0x6de0]; 10326 10327 u8 internal_timer_h[0x20]; 10328 10329 u8 internal_timer_l[0x20]; 10330 10331 u8 reserved_6[0x20]; 10332 10333 u8 reserved_7[0x1f]; 10334 u8 clear_int[0x1]; 10335 10336 u8 health_syndrome[0x8]; 10337 u8 health_counter[0x18]; 10338 10339 u8 reserved_8[0x17fc0]; 10340 }; 10341 10342 union mlx5_ifc_icmd_interface_document_bits { 10343 struct mlx5_ifc_fw_version_bits fw_version; 10344 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 10345 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 10346 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 10347 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 10348 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 10349 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 10350 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 10351 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 10352 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 10353 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 10354 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 10355 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 10356 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 10357 u8 reserved_0[0x42c0]; 10358 }; 10359 10360 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 10361 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10362 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10363 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10364 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10365 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10366 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10367 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10368 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10369 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 10370 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 10371 u8 reserved_0[0x7c0]; 10372 }; 10373 10374 struct mlx5_ifc_ppcnt_reg_bits { 10375 u8 swid[0x8]; 10376 u8 local_port[0x8]; 10377 u8 pnat[0x2]; 10378 u8 reserved_0[0x8]; 10379 u8 grp[0x6]; 10380 10381 u8 clr[0x1]; 10382 u8 reserved_1[0x1c]; 10383 u8 prio_tc[0x3]; 10384 10385 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10386 }; 10387 10388 struct mlx5_ifc_pcie_lanes_counters_bits { 10389 u8 life_time_counter_high[0x20]; 10390 10391 u8 life_time_counter_low[0x20]; 10392 10393 u8 error_counter_lane0[0x20]; 10394 10395 u8 error_counter_lane1[0x20]; 10396 10397 u8 error_counter_lane2[0x20]; 10398 10399 u8 error_counter_lane3[0x20]; 10400 10401 u8 error_counter_lane4[0x20]; 10402 10403 u8 error_counter_lane5[0x20]; 10404 10405 u8 error_counter_lane6[0x20]; 10406 10407 u8 error_counter_lane7[0x20]; 10408 10409 u8 error_counter_lane8[0x20]; 10410 10411 u8 error_counter_lane9[0x20]; 10412 10413 u8 error_counter_lane10[0x20]; 10414 10415 u8 error_counter_lane11[0x20]; 10416 10417 u8 error_counter_lane12[0x20]; 10418 10419 u8 error_counter_lane13[0x20]; 10420 10421 u8 error_counter_lane14[0x20]; 10422 10423 u8 error_counter_lane15[0x20]; 10424 10425 u8 reserved_at_240[0x580]; 10426 }; 10427 10428 struct mlx5_ifc_pcie_lanes_counters_ext_bits { 10429 u8 reserved_at_0[0x40]; 10430 10431 u8 error_counter_lane0[0x20]; 10432 10433 u8 error_counter_lane1[0x20]; 10434 10435 u8 error_counter_lane2[0x20]; 10436 10437 u8 error_counter_lane3[0x20]; 10438 10439 u8 error_counter_lane4[0x20]; 10440 10441 u8 error_counter_lane5[0x20]; 10442 10443 u8 error_counter_lane6[0x20]; 10444 10445 u8 error_counter_lane7[0x20]; 10446 10447 u8 error_counter_lane8[0x20]; 10448 10449 u8 error_counter_lane9[0x20]; 10450 10451 u8 error_counter_lane10[0x20]; 10452 10453 u8 error_counter_lane11[0x20]; 10454 10455 u8 error_counter_lane12[0x20]; 10456 10457 u8 error_counter_lane13[0x20]; 10458 10459 u8 error_counter_lane14[0x20]; 10460 10461 u8 error_counter_lane15[0x20]; 10462 10463 u8 reserved_at_240[0x580]; 10464 }; 10465 10466 struct mlx5_ifc_pcie_perf_counters_bits { 10467 u8 life_time_counter_high[0x20]; 10468 10469 u8 life_time_counter_low[0x20]; 10470 10471 u8 rx_errors[0x20]; 10472 10473 u8 tx_errors[0x20]; 10474 10475 u8 l0_to_recovery_eieos[0x20]; 10476 10477 u8 l0_to_recovery_ts[0x20]; 10478 10479 u8 l0_to_recovery_framing[0x20]; 10480 10481 u8 l0_to_recovery_retrain[0x20]; 10482 10483 u8 crc_error_dllp[0x20]; 10484 10485 u8 crc_error_tlp[0x20]; 10486 10487 u8 tx_overflow_buffer_pkt[0x40]; 10488 10489 u8 outbound_stalled_reads[0x20]; 10490 10491 u8 outbound_stalled_writes[0x20]; 10492 10493 u8 outbound_stalled_reads_events[0x20]; 10494 10495 u8 outbound_stalled_writes_events[0x20]; 10496 10497 u8 tx_overflow_buffer_marked_pkt[0x40]; 10498 10499 u8 reserved_at_240[0x580]; 10500 }; 10501 10502 struct mlx5_ifc_pcie_perf_counters_ext_bits { 10503 u8 reserved_at_0[0x40]; 10504 10505 u8 rx_errors[0x20]; 10506 10507 u8 tx_errors[0x20]; 10508 10509 u8 reserved_at_80[0xc0]; 10510 10511 u8 tx_overflow_buffer_pkt[0x40]; 10512 10513 u8 outbound_stalled_reads[0x20]; 10514 10515 u8 outbound_stalled_writes[0x20]; 10516 10517 u8 outbound_stalled_reads_events[0x20]; 10518 10519 u8 outbound_stalled_writes_events[0x20]; 10520 10521 u8 tx_overflow_buffer_marked_pkt[0x40]; 10522 10523 u8 reserved_at_240[0x580]; 10524 }; 10525 10526 struct mlx5_ifc_pcie_timers_states_bits { 10527 u8 life_time_counter_high[0x20]; 10528 10529 u8 life_time_counter_low[0x20]; 10530 10531 u8 time_to_boot_image_start[0x20]; 10532 10533 u8 time_to_link_image[0x20]; 10534 10535 u8 calibration_time[0x20]; 10536 10537 u8 time_to_first_perst[0x20]; 10538 10539 u8 time_to_detect_state[0x20]; 10540 10541 u8 time_to_l0[0x20]; 10542 10543 u8 time_to_crs_en[0x20]; 10544 10545 u8 time_to_plastic_image_start[0x20]; 10546 10547 u8 time_to_iron_image_start[0x20]; 10548 10549 u8 perst_handler[0x20]; 10550 10551 u8 times_in_l1[0x20]; 10552 10553 u8 times_in_l23[0x20]; 10554 10555 u8 dl_down[0x20]; 10556 10557 u8 config_cycle1usec[0x20]; 10558 10559 u8 config_cycle2to7usec[0x20]; 10560 10561 u8 config_cycle8to15usec[0x20]; 10562 10563 u8 config_cycle16to63usec[0x20]; 10564 10565 u8 config_cycle64usec[0x20]; 10566 10567 u8 correctable_err_msg_sent[0x20]; 10568 10569 u8 non_fatal_err_msg_sent[0x20]; 10570 10571 u8 fatal_err_msg_sent[0x20]; 10572 10573 u8 reserved_at_2e0[0x4e0]; 10574 }; 10575 10576 struct mlx5_ifc_pcie_timers_states_ext_bits { 10577 u8 reserved_at_0[0x40]; 10578 10579 u8 time_to_boot_image_start[0x20]; 10580 10581 u8 time_to_link_image[0x20]; 10582 10583 u8 calibration_time[0x20]; 10584 10585 u8 time_to_first_perst[0x20]; 10586 10587 u8 time_to_detect_state[0x20]; 10588 10589 u8 time_to_l0[0x20]; 10590 10591 u8 time_to_crs_en[0x20]; 10592 10593 u8 time_to_plastic_image_start[0x20]; 10594 10595 u8 time_to_iron_image_start[0x20]; 10596 10597 u8 perst_handler[0x20]; 10598 10599 u8 times_in_l1[0x20]; 10600 10601 u8 times_in_l23[0x20]; 10602 10603 u8 dl_down[0x20]; 10604 10605 u8 config_cycle1usec[0x20]; 10606 10607 u8 config_cycle2to7usec[0x20]; 10608 10609 u8 config_cycle8to15usec[0x20]; 10610 10611 u8 config_cycle16to63usec[0x20]; 10612 10613 u8 config_cycle64usec[0x20]; 10614 10615 u8 correctable_err_msg_sent[0x20]; 10616 10617 u8 non_fatal_err_msg_sent[0x20]; 10618 10619 u8 fatal_err_msg_sent[0x20]; 10620 10621 u8 reserved_at_2e0[0x4e0]; 10622 }; 10623 10624 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits { 10625 struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters; 10626 struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters; 10627 struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states; 10628 u8 reserved_at_0[0x7c0]; 10629 }; 10630 10631 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits { 10632 struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext; 10633 struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext; 10634 struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext; 10635 u8 reserved_at_0[0x7c0]; 10636 }; 10637 10638 struct mlx5_ifc_mpcnt_reg_bits { 10639 u8 reserved_at_0[0x2]; 10640 u8 depth[0x6]; 10641 u8 pcie_index[0x8]; 10642 u8 node[0x8]; 10643 u8 reserved_at_18[0x2]; 10644 u8 grp[0x6]; 10645 10646 u8 clr[0x1]; 10647 u8 reserved_at_21[0x1f]; 10648 10649 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set; 10650 }; 10651 10652 struct mlx5_ifc_mpcnt_reg_ext_bits { 10653 u8 reserved_at_0[0x2]; 10654 u8 depth[0x6]; 10655 u8 pcie_index[0x8]; 10656 u8 node[0x8]; 10657 u8 reserved_at_18[0x2]; 10658 u8 grp[0x6]; 10659 10660 u8 clr[0x1]; 10661 u8 reserved_at_21[0x1f]; 10662 10663 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set; 10664 }; 10665 10666 struct mlx5_ifc_monitor_opcodes_layout_bits { 10667 u8 reserved_at_0[0x10]; 10668 u8 monitor_opcode[0x10]; 10669 }; 10670 10671 union mlx5_ifc_pddr_status_opcode_bits { 10672 struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes; 10673 u8 reserved_at_0[0x20]; 10674 }; 10675 10676 struct mlx5_ifc_troubleshooting_info_page_layout_bits { 10677 u8 reserved_at_0[0x10]; 10678 u8 group_opcode[0x10]; 10679 10680 union mlx5_ifc_pddr_status_opcode_bits status_opcode; 10681 10682 u8 user_feedback_data[0x10]; 10683 u8 user_feedback_index[0x10]; 10684 10685 u8 status_message[0x760]; 10686 }; 10687 10688 union mlx5_ifc_pddr_page_data_bits { 10689 struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page; 10690 struct mlx5_ifc_pddr_module_info_bits pddr_module_info; 10691 u8 reserved_at_0[0x7c0]; 10692 }; 10693 10694 struct mlx5_ifc_pddr_reg_bits { 10695 u8 reserved_at_0[0x8]; 10696 u8 local_port[0x8]; 10697 u8 pnat[0x2]; 10698 u8 reserved_at_12[0xe]; 10699 10700 u8 reserved_at_20[0x18]; 10701 u8 page_select[0x8]; 10702 10703 union mlx5_ifc_pddr_page_data_bits page_data; 10704 }; 10705 10706 enum { 10707 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050, 10708 MLX5_MPEIN_PWR_STATUS_INVALID = 0, 10709 MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1, 10710 MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2, 10711 }; 10712 10713 struct mlx5_ifc_mpein_reg_bits { 10714 u8 reserved_at_0[0x2]; 10715 u8 depth[0x6]; 10716 u8 pcie_index[0x8]; 10717 u8 node[0x8]; 10718 u8 reserved_at_18[0x8]; 10719 10720 u8 capability_mask[0x20]; 10721 10722 u8 reserved_at_40[0x8]; 10723 u8 link_width_enabled[0x8]; 10724 u8 link_speed_enabled[0x10]; 10725 10726 u8 lane0_physical_position[0x8]; 10727 u8 link_width_active[0x8]; 10728 u8 link_speed_active[0x10]; 10729 10730 u8 num_of_pfs[0x10]; 10731 u8 num_of_vfs[0x10]; 10732 10733 u8 bdf0[0x10]; 10734 u8 reserved_at_b0[0x10]; 10735 10736 u8 max_read_request_size[0x4]; 10737 u8 max_payload_size[0x4]; 10738 u8 reserved_at_c8[0x5]; 10739 u8 pwr_status[0x3]; 10740 u8 port_type[0x4]; 10741 u8 reserved_at_d4[0xb]; 10742 u8 lane_reversal[0x1]; 10743 10744 u8 reserved_at_e0[0x14]; 10745 u8 pci_power[0xc]; 10746 10747 u8 reserved_at_100[0x20]; 10748 10749 u8 device_status[0x10]; 10750 u8 port_state[0x8]; 10751 u8 reserved_at_138[0x8]; 10752 10753 u8 reserved_at_140[0x10]; 10754 u8 receiver_detect_result[0x10]; 10755 10756 u8 reserved_at_160[0x20]; 10757 }; 10758 10759 struct mlx5_ifc_mpein_reg_ext_bits { 10760 u8 reserved_at_0[0x2]; 10761 u8 depth[0x6]; 10762 u8 pcie_index[0x8]; 10763 u8 node[0x8]; 10764 u8 reserved_at_18[0x8]; 10765 10766 u8 reserved_at_20[0x20]; 10767 10768 u8 reserved_at_40[0x8]; 10769 u8 link_width_enabled[0x8]; 10770 u8 link_speed_enabled[0x10]; 10771 10772 u8 lane0_physical_position[0x8]; 10773 u8 link_width_active[0x8]; 10774 u8 link_speed_active[0x10]; 10775 10776 u8 num_of_pfs[0x10]; 10777 u8 num_of_vfs[0x10]; 10778 10779 u8 bdf0[0x10]; 10780 u8 reserved_at_b0[0x10]; 10781 10782 u8 max_read_request_size[0x4]; 10783 u8 max_payload_size[0x4]; 10784 u8 reserved_at_c8[0x5]; 10785 u8 pwr_status[0x3]; 10786 u8 port_type[0x4]; 10787 u8 reserved_at_d4[0xb]; 10788 u8 lane_reversal[0x1]; 10789 }; 10790 10791 struct mlx5_ifc_mcqi_cap_bits { 10792 u8 supported_info_bitmask[0x20]; 10793 10794 u8 component_size[0x20]; 10795 10796 u8 max_component_size[0x20]; 10797 10798 u8 log_mcda_word_size[0x4]; 10799 u8 reserved_at_64[0xc]; 10800 u8 mcda_max_write_size[0x10]; 10801 10802 u8 rd_en[0x1]; 10803 u8 reserved_at_81[0x1]; 10804 u8 match_chip_id[0x1]; 10805 u8 match_psid[0x1]; 10806 u8 check_user_timestamp[0x1]; 10807 u8 match_base_guid_mac[0x1]; 10808 u8 reserved_at_86[0x1a]; 10809 }; 10810 10811 struct mlx5_ifc_mcqi_reg_bits { 10812 u8 read_pending_component[0x1]; 10813 u8 reserved_at_1[0xf]; 10814 u8 component_index[0x10]; 10815 10816 u8 reserved_at_20[0x20]; 10817 10818 u8 reserved_at_40[0x1b]; 10819 u8 info_type[0x5]; 10820 10821 u8 info_size[0x20]; 10822 10823 u8 offset[0x20]; 10824 10825 u8 reserved_at_a0[0x10]; 10826 u8 data_size[0x10]; 10827 10828 u8 data[0][0x20]; 10829 }; 10830 10831 struct mlx5_ifc_mcc_reg_bits { 10832 u8 reserved_at_0[0x4]; 10833 u8 time_elapsed_since_last_cmd[0xc]; 10834 u8 reserved_at_10[0x8]; 10835 u8 instruction[0x8]; 10836 10837 u8 reserved_at_20[0x10]; 10838 u8 component_index[0x10]; 10839 10840 u8 reserved_at_40[0x8]; 10841 u8 update_handle[0x18]; 10842 10843 u8 handle_owner_type[0x4]; 10844 u8 handle_owner_host_id[0x4]; 10845 u8 reserved_at_68[0x1]; 10846 u8 control_progress[0x7]; 10847 u8 error_code[0x8]; 10848 u8 reserved_at_78[0x4]; 10849 u8 control_state[0x4]; 10850 10851 u8 component_size[0x20]; 10852 10853 u8 reserved_at_a0[0x60]; 10854 }; 10855 10856 struct mlx5_ifc_mcda_reg_bits { 10857 u8 reserved_at_0[0x8]; 10858 u8 update_handle[0x18]; 10859 10860 u8 offset[0x20]; 10861 10862 u8 reserved_at_40[0x10]; 10863 u8 size[0x10]; 10864 10865 u8 reserved_at_60[0x20]; 10866 10867 u8 data[0][0x20]; 10868 }; 10869 10870 union mlx5_ifc_ports_control_registers_document_bits { 10871 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 10872 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10873 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10874 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10875 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10876 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10877 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10878 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10879 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10880 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 10881 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 10882 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10883 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 10884 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10885 struct mlx5_ifc_paos_reg_bits paos_reg; 10886 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 10887 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10888 struct mlx5_ifc_peir_reg_bits peir_reg; 10889 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10890 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10891 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 10892 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 10893 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 10894 struct mlx5_ifc_phrr_reg_bits phrr_reg; 10895 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10896 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10897 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10898 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10899 struct mlx5_ifc_plib_reg_bits plib_reg; 10900 struct mlx5_ifc_pll_status_data_bits pll_status_data; 10901 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10902 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10903 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10904 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10905 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10906 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10907 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10908 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10909 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10910 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10911 struct mlx5_ifc_ppll_reg_bits ppll_reg; 10912 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10913 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10914 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10915 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10916 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10917 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10918 struct mlx5_ifc_pude_reg_bits pude_reg; 10919 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10920 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10921 struct mlx5_ifc_slrp_reg_bits slrp_reg; 10922 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10923 u8 reserved_0[0x7880]; 10924 }; 10925 10926 union mlx5_ifc_debug_enhancements_document_bits { 10927 struct mlx5_ifc_health_buffer_bits health_buffer; 10928 u8 reserved_0[0x200]; 10929 }; 10930 10931 union mlx5_ifc_no_dram_nic_document_bits { 10932 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 10933 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 10934 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 10935 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 10936 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 10937 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 10938 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 10939 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 10940 u8 reserved_0[0x3160]; 10941 }; 10942 10943 union mlx5_ifc_uplink_pci_interface_document_bits { 10944 struct mlx5_ifc_initial_seg_bits initial_seg; 10945 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 10946 u8 reserved_0[0x20120]; 10947 }; 10948 10949 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10950 u8 e[0x1]; 10951 u8 reserved_at_01[0x0b]; 10952 u8 prio[0x04]; 10953 }; 10954 10955 struct mlx5_ifc_qpdpm_reg_bits { 10956 u8 reserved_at_0[0x8]; 10957 u8 local_port[0x8]; 10958 u8 reserved_at_10[0x10]; 10959 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10960 }; 10961 10962 struct mlx5_ifc_qpts_reg_bits { 10963 u8 reserved_at_0[0x8]; 10964 u8 local_port[0x8]; 10965 u8 reserved_at_10[0x2d]; 10966 u8 trust_state[0x3]; 10967 }; 10968 10969 struct mlx5_ifc_mfrl_reg_bits { 10970 u8 reserved_at_0[0x38]; 10971 u8 reset_level[0x8]; 10972 }; 10973 10974 enum { 10975 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP = 0x9009, 10976 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR = 0x9109, 10977 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP = 0x900a, 10978 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE = 0x900b, 10979 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR = 0x900f, 10980 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE = 0x910b, 10981 MLX5_MAX_TEMPERATURE = 16, 10982 }; 10983 10984 struct mlx5_ifc_mtbr_temp_record_bits { 10985 u8 max_temperature[0x10]; 10986 u8 temperature[0x10]; 10987 }; 10988 10989 struct mlx5_ifc_mtbr_reg_bits { 10990 u8 reserved_at_0[0x14]; 10991 u8 base_sensor_index[0xc]; 10992 10993 u8 reserved_at_20[0x18]; 10994 u8 num_rec[0x8]; 10995 10996 u8 reserved_at_40[0x40]; 10997 10998 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 10999 }; 11000 11001 struct mlx5_ifc_mtbr_reg_ext_bits { 11002 u8 reserved_at_0[0x14]; 11003 u8 base_sensor_index[0xc]; 11004 11005 u8 reserved_at_20[0x18]; 11006 u8 num_rec[0x8]; 11007 11008 u8 reserved_at_40[0x40]; 11009 11010 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 11011 }; 11012 11013 struct mlx5_ifc_mtcap_bits { 11014 u8 reserved_at_0[0x19]; 11015 u8 sensor_count[0x7]; 11016 11017 u8 reserved_at_20[0x19]; 11018 u8 internal_sensor_count[0x7]; 11019 11020 u8 sensor_map[0x40]; 11021 }; 11022 11023 struct mlx5_ifc_mtcap_ext_bits { 11024 u8 reserved_at_0[0x19]; 11025 u8 sensor_count[0x7]; 11026 11027 u8 reserved_at_20[0x20]; 11028 11029 u8 sensor_map[0x40]; 11030 }; 11031 11032 struct mlx5_ifc_mtecr_bits { 11033 u8 reserved_at_0[0x4]; 11034 u8 last_sensor[0xc]; 11035 u8 reserved_at_10[0x4]; 11036 u8 sensor_count[0xc]; 11037 11038 u8 reserved_at_20[0x19]; 11039 u8 internal_sensor_count[0x7]; 11040 11041 u8 sensor_map_0[0x20]; 11042 11043 u8 reserved_at_60[0x2a0]; 11044 }; 11045 11046 struct mlx5_ifc_mtecr_ext_bits { 11047 u8 reserved_at_0[0x4]; 11048 u8 last_sensor[0xc]; 11049 u8 reserved_at_10[0x4]; 11050 u8 sensor_count[0xc]; 11051 11052 u8 reserved_at_20[0x20]; 11053 11054 u8 sensor_map_0[0x20]; 11055 11056 u8 reserved_at_60[0x2a0]; 11057 }; 11058 11059 struct mlx5_ifc_mtewe_bits { 11060 u8 reserved_at_0[0x4]; 11061 u8 last_sensor[0xc]; 11062 u8 reserved_at_10[0x4]; 11063 u8 sensor_count[0xc]; 11064 11065 u8 sensor_warning_0[0x20]; 11066 11067 u8 reserved_at_40[0x2a0]; 11068 }; 11069 11070 struct mlx5_ifc_mtewe_ext_bits { 11071 u8 reserved_at_0[0x4]; 11072 u8 last_sensor[0xc]; 11073 u8 reserved_at_10[0x4]; 11074 u8 sensor_count[0xc]; 11075 11076 u8 sensor_warning_0[0x20]; 11077 11078 u8 reserved_at_40[0x2a0]; 11079 }; 11080 11081 struct mlx5_ifc_mtmp_bits { 11082 u8 reserved_at_0[0x14]; 11083 u8 sensor_index[0xc]; 11084 11085 u8 reserved_at_20[0x10]; 11086 u8 temperature[0x10]; 11087 11088 u8 mte[0x1]; 11089 u8 mtr[0x1]; 11090 u8 reserved_at_42[0xe]; 11091 u8 max_temperature[0x10]; 11092 11093 u8 tee[0x2]; 11094 u8 reserved_at_62[0xe]; 11095 u8 temperature_threshold_hi[0x10]; 11096 11097 u8 reserved_at_80[0x10]; 11098 u8 temperature_threshold_lo[0x10]; 11099 11100 u8 reserved_at_a0[0x20]; 11101 11102 u8 sensor_name_hi[0x20]; 11103 11104 u8 sensor_name_lo[0x20]; 11105 }; 11106 11107 struct mlx5_ifc_mtmp_ext_bits { 11108 u8 reserved_at_0[0x14]; 11109 u8 sensor_index[0xc]; 11110 11111 u8 reserved_at_20[0x10]; 11112 u8 temperature[0x10]; 11113 11114 u8 mte[0x1]; 11115 u8 mtr[0x1]; 11116 u8 reserved_at_42[0xe]; 11117 u8 max_temperature[0x10]; 11118 11119 u8 tee[0x2]; 11120 u8 reserved_at_62[0xe]; 11121 u8 temperature_threshold_hi[0x10]; 11122 11123 u8 reserved_at_80[0x10]; 11124 u8 temperature_threshold_lo[0x10]; 11125 11126 u8 reserved_at_a0[0x20]; 11127 11128 u8 sensor_name_hi[0x20]; 11129 11130 u8 sensor_name_lo[0x20]; 11131 }; 11132 11133 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 11134 u8 opcode[0x10]; 11135 u8 uid[0x10]; 11136 11137 u8 vhca_tunnel_id[0x10]; 11138 u8 obj_type[0x10]; 11139 11140 u8 obj_id[0x20]; 11141 11142 u8 reserved_at_60[0x20]; 11143 }; 11144 11145 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 11146 u8 status[0x8]; 11147 u8 reserved_at_8[0x18]; 11148 11149 u8 syndrome[0x20]; 11150 11151 u8 obj_id[0x20]; 11152 11153 u8 reserved_at_60[0x20]; 11154 }; 11155 11156 struct mlx5_ifc_umem_bits { 11157 u8 reserved_at_0[0x80]; 11158 11159 u8 reserved_at_80[0x1b]; 11160 u8 log_page_size[0x5]; 11161 11162 u8 page_offset[0x20]; 11163 11164 u8 num_of_mtt[0x40]; 11165 11166 struct mlx5_ifc_mtt_bits mtt[0]; 11167 }; 11168 11169 struct mlx5_ifc_uctx_bits { 11170 u8 cap[0x20]; 11171 11172 u8 reserved_at_20[0x160]; 11173 }; 11174 11175 struct mlx5_ifc_create_umem_in_bits { 11176 u8 opcode[0x10]; 11177 u8 uid[0x10]; 11178 11179 u8 reserved_at_20[0x10]; 11180 u8 op_mod[0x10]; 11181 11182 u8 reserved_at_40[0x40]; 11183 11184 struct mlx5_ifc_umem_bits umem; 11185 }; 11186 11187 struct mlx5_ifc_create_uctx_in_bits { 11188 u8 opcode[0x10]; 11189 u8 reserved_at_10[0x10]; 11190 11191 u8 reserved_at_20[0x10]; 11192 u8 op_mod[0x10]; 11193 11194 u8 reserved_at_40[0x40]; 11195 11196 struct mlx5_ifc_uctx_bits uctx; 11197 }; 11198 11199 struct mlx5_ifc_destroy_uctx_in_bits { 11200 u8 opcode[0x10]; 11201 u8 reserved_at_10[0x10]; 11202 11203 u8 reserved_at_20[0x10]; 11204 u8 op_mod[0x10]; 11205 11206 u8 reserved_at_40[0x10]; 11207 u8 uid[0x10]; 11208 11209 u8 reserved_at_60[0x20]; 11210 }; 11211 11212 struct mlx5_ifc_mtrc_string_db_param_bits { 11213 u8 string_db_base_address[0x20]; 11214 11215 u8 reserved_at_20[0x8]; 11216 u8 string_db_size[0x18]; 11217 }; 11218 11219 struct mlx5_ifc_mtrc_cap_bits { 11220 u8 trace_owner[0x1]; 11221 u8 trace_to_memory[0x1]; 11222 u8 reserved_at_2[0x4]; 11223 u8 trc_ver[0x2]; 11224 u8 reserved_at_8[0x14]; 11225 u8 num_string_db[0x4]; 11226 11227 u8 first_string_trace[0x8]; 11228 u8 num_string_trace[0x8]; 11229 u8 reserved_at_30[0x28]; 11230 11231 u8 log_max_trace_buffer_size[0x8]; 11232 11233 u8 reserved_at_60[0x20]; 11234 11235 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11236 11237 u8 reserved_at_280[0x180]; 11238 }; 11239 11240 struct mlx5_ifc_mtrc_conf_bits { 11241 u8 reserved_at_0[0x1c]; 11242 u8 trace_mode[0x4]; 11243 u8 reserved_at_20[0x18]; 11244 u8 log_trace_buffer_size[0x8]; 11245 u8 trace_mkey[0x20]; 11246 u8 reserved_at_60[0x3a0]; 11247 }; 11248 11249 struct mlx5_ifc_mtrc_stdb_bits { 11250 u8 string_db_index[0x4]; 11251 u8 reserved_at_4[0x4]; 11252 u8 read_size[0x18]; 11253 u8 start_offset[0x20]; 11254 u8 string_db_data[0]; 11255 }; 11256 11257 struct mlx5_ifc_mtrc_ctrl_bits { 11258 u8 trace_status[0x2]; 11259 u8 reserved_at_2[0x2]; 11260 u8 arm_event[0x1]; 11261 u8 reserved_at_5[0xb]; 11262 u8 modify_field_select[0x10]; 11263 u8 reserved_at_20[0x2b]; 11264 u8 current_timestamp52_32[0x15]; 11265 u8 current_timestamp31_0[0x20]; 11266 u8 reserved_at_80[0x180]; 11267 }; 11268 11269 struct mlx5_ifc_affiliated_event_header_bits { 11270 u8 reserved_at_0[0x10]; 11271 u8 obj_type[0x10]; 11272 11273 u8 obj_id[0x20]; 11274 }; 11275 11276 #endif /* MLX5_IFC_H */ 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