1 /*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_IFC_H 29 #define MLX5_IFC_H 30 31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> 32 33 enum { 34 MLX5_EVENT_TYPE_COMP = 0x0, 35 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 36 MLX5_EVENT_TYPE_COMM_EST = 0x2, 37 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 38 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 39 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 40 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 41 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 42 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 43 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 44 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 45 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 46 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 47 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 48 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 49 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 50 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 51 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 52 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 53 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 54 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 55 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 56 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 57 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 58 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 59 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 60 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 61 MLX5_EVENT_TYPE_CMD = 0xa, 62 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 63 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 64 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 65 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 66 MLX5_EVENT_TYPE_CODING_GENERAL_OBJ_EVENT = 0x27, 67 }; 68 69 enum { 70 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 71 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 72 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 73 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 74 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 75 }; 76 77 enum { 78 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 79 }; 80 81 enum { 82 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 83 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 84 }; 85 86 enum { 87 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 88 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 89 MLX5_CMD_OP_INIT_HCA = 0x102, 90 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 91 MLX5_CMD_OP_ENABLE_HCA = 0x104, 92 MLX5_CMD_OP_DISABLE_HCA = 0x105, 93 MLX5_CMD_OP_QUERY_PAGES = 0x107, 94 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 95 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 96 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 97 MLX5_CMD_OP_SET_ISSI = 0x10b, 98 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 99 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 100 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 101 MLX5_CMD_OP_CREATE_MKEY = 0x200, 102 MLX5_CMD_OP_QUERY_MKEY = 0x201, 103 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 104 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 105 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 106 MLX5_CMD_OP_CREATE_EQ = 0x301, 107 MLX5_CMD_OP_DESTROY_EQ = 0x302, 108 MLX5_CMD_OP_QUERY_EQ = 0x303, 109 MLX5_CMD_OP_GEN_EQE = 0x304, 110 MLX5_CMD_OP_CREATE_CQ = 0x400, 111 MLX5_CMD_OP_DESTROY_CQ = 0x401, 112 MLX5_CMD_OP_QUERY_CQ = 0x402, 113 MLX5_CMD_OP_MODIFY_CQ = 0x403, 114 MLX5_CMD_OP_CREATE_QP = 0x500, 115 MLX5_CMD_OP_DESTROY_QP = 0x501, 116 MLX5_CMD_OP_RST2INIT_QP = 0x502, 117 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 118 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 119 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 120 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 121 MLX5_CMD_OP_2ERR_QP = 0x507, 122 MLX5_CMD_OP_2RST_QP = 0x50a, 123 MLX5_CMD_OP_QUERY_QP = 0x50b, 124 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 125 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 126 MLX5_CMD_OP_CREATE_PSV = 0x600, 127 MLX5_CMD_OP_DESTROY_PSV = 0x601, 128 MLX5_CMD_OP_CREATE_SRQ = 0x700, 129 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 130 MLX5_CMD_OP_QUERY_SRQ = 0x702, 131 MLX5_CMD_OP_ARM_RQ = 0x703, 132 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 133 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 134 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 135 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 136 MLX5_CMD_OP_CREATE_DCT = 0x710, 137 MLX5_CMD_OP_DESTROY_DCT = 0x711, 138 MLX5_CMD_OP_DRAIN_DCT = 0x712, 139 MLX5_CMD_OP_QUERY_DCT = 0x713, 140 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 141 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 142 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 143 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 144 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 145 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 146 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 147 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 148 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 149 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 150 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 151 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 152 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 153 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 154 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 155 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 156 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 157 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 158 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 159 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 160 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 161 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 162 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 163 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 164 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 165 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 166 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 167 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 168 MLX5_CMD_OP_ALLOC_PD = 0x800, 169 MLX5_CMD_OP_DEALLOC_PD = 0x801, 170 MLX5_CMD_OP_ALLOC_UAR = 0x802, 171 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 172 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 173 MLX5_CMD_OP_ACCESS_REG = 0x805, 174 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 175 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 176 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 177 MLX5_CMD_OP_MAD_IFC = 0x50d, 178 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 179 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 180 MLX5_CMD_OP_NOP = 0x80d, 181 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 182 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 183 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 184 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 185 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 186 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 187 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 188 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 189 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 190 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 191 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 192 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 193 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 194 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 195 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 196 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 197 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 198 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 199 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 200 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 201 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 202 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 203 MLX5_CMD_OP_CREATE_LAG = 0x840, 204 MLX5_CMD_OP_MODIFY_LAG = 0x841, 205 MLX5_CMD_OP_QUERY_LAG = 0x842, 206 MLX5_CMD_OP_DESTROY_LAG = 0x843, 207 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 208 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 209 MLX5_CMD_OP_CREATE_TIR = 0x900, 210 MLX5_CMD_OP_MODIFY_TIR = 0x901, 211 MLX5_CMD_OP_DESTROY_TIR = 0x902, 212 MLX5_CMD_OP_QUERY_TIR = 0x903, 213 MLX5_CMD_OP_CREATE_SQ = 0x904, 214 MLX5_CMD_OP_MODIFY_SQ = 0x905, 215 MLX5_CMD_OP_DESTROY_SQ = 0x906, 216 MLX5_CMD_OP_QUERY_SQ = 0x907, 217 MLX5_CMD_OP_CREATE_RQ = 0x908, 218 MLX5_CMD_OP_MODIFY_RQ = 0x909, 219 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 220 MLX5_CMD_OP_QUERY_RQ = 0x90b, 221 MLX5_CMD_OP_CREATE_RMP = 0x90c, 222 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 223 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 224 MLX5_CMD_OP_QUERY_RMP = 0x90f, 225 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 226 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 227 MLX5_CMD_OP_CREATE_TIS = 0x912, 228 MLX5_CMD_OP_MODIFY_TIS = 0x913, 229 MLX5_CMD_OP_DESTROY_TIS = 0x914, 230 MLX5_CMD_OP_QUERY_TIS = 0x915, 231 MLX5_CMD_OP_CREATE_RQT = 0x916, 232 MLX5_CMD_OP_MODIFY_RQT = 0x917, 233 MLX5_CMD_OP_DESTROY_RQT = 0x918, 234 MLX5_CMD_OP_QUERY_RQT = 0x919, 235 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 236 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 237 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 238 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 239 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 240 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 241 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 242 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 243 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 244 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 245 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 246 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 247 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 248 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 249 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 250 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 251 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 252 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 253 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 254 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 255 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 256 MLX5_CMD_OP_CREATE_GENERAL_OBJ = 0xa00, 257 MLX5_CMD_OP_MODIFY_GENERAL_OBJ = 0xa01, 258 MLX5_CMD_OP_QUERY_GENERAL_OBJ = 0xa02, 259 MLX5_CMD_OP_DESTROY_GENERAL_OBJ = 0xa03, 260 261 }; 262 263 enum { 264 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 265 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 266 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 267 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 268 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 269 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 270 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 271 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 272 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 273 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 274 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 275 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 276 }; 277 278 enum { 279 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 280 }; 281 282 enum { 283 MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc, 284 }; 285 286 enum { 287 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 288 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 289 }; 290 291 enum { 292 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1, 293 }; 294 295 struct mlx5_ifc_flow_table_fields_supported_bits { 296 u8 outer_dmac[0x1]; 297 u8 outer_smac[0x1]; 298 u8 outer_ether_type[0x1]; 299 u8 reserved_0[0x1]; 300 u8 outer_first_prio[0x1]; 301 u8 outer_first_cfi[0x1]; 302 u8 outer_first_vid[0x1]; 303 u8 reserved_1[0x1]; 304 u8 outer_second_prio[0x1]; 305 u8 outer_second_cfi[0x1]; 306 u8 outer_second_vid[0x1]; 307 u8 outer_ipv6_flow_label[0x1]; 308 u8 outer_sip[0x1]; 309 u8 outer_dip[0x1]; 310 u8 outer_frag[0x1]; 311 u8 outer_ip_protocol[0x1]; 312 u8 outer_ip_ecn[0x1]; 313 u8 outer_ip_dscp[0x1]; 314 u8 outer_udp_sport[0x1]; 315 u8 outer_udp_dport[0x1]; 316 u8 outer_tcp_sport[0x1]; 317 u8 outer_tcp_dport[0x1]; 318 u8 outer_tcp_flags[0x1]; 319 u8 outer_gre_protocol[0x1]; 320 u8 outer_gre_key[0x1]; 321 u8 outer_vxlan_vni[0x1]; 322 u8 outer_geneve_vni[0x1]; 323 u8 outer_geneve_oam[0x1]; 324 u8 outer_geneve_protocol_type[0x1]; 325 u8 outer_geneve_opt_len[0x1]; 326 u8 reserved_2[0x1]; 327 u8 source_eswitch_port[0x1]; 328 329 u8 inner_dmac[0x1]; 330 u8 inner_smac[0x1]; 331 u8 inner_ether_type[0x1]; 332 u8 reserved_3[0x1]; 333 u8 inner_first_prio[0x1]; 334 u8 inner_first_cfi[0x1]; 335 u8 inner_first_vid[0x1]; 336 u8 reserved_4[0x1]; 337 u8 inner_second_prio[0x1]; 338 u8 inner_second_cfi[0x1]; 339 u8 inner_second_vid[0x1]; 340 u8 inner_ipv6_flow_label[0x1]; 341 u8 inner_sip[0x1]; 342 u8 inner_dip[0x1]; 343 u8 inner_frag[0x1]; 344 u8 inner_ip_protocol[0x1]; 345 u8 inner_ip_ecn[0x1]; 346 u8 inner_ip_dscp[0x1]; 347 u8 inner_udp_sport[0x1]; 348 u8 inner_udp_dport[0x1]; 349 u8 inner_tcp_sport[0x1]; 350 u8 inner_tcp_dport[0x1]; 351 u8 inner_tcp_flags[0x1]; 352 u8 reserved_5[0x9]; 353 354 u8 reserved_6[0x1a]; 355 u8 bth_dst_qp[0x1]; 356 u8 reserved_7[0x4]; 357 u8 source_sqn[0x1]; 358 359 u8 reserved_8[0x20]; 360 }; 361 362 struct mlx5_ifc_eth_discard_cntrs_grp_bits { 363 u8 ingress_general_high[0x20]; 364 365 u8 ingress_general_low[0x20]; 366 367 u8 ingress_policy_engine_high[0x20]; 368 369 u8 ingress_policy_engine_low[0x20]; 370 371 u8 ingress_vlan_membership_high[0x20]; 372 373 u8 ingress_vlan_membership_low[0x20]; 374 375 u8 ingress_tag_frame_type_high[0x20]; 376 377 u8 ingress_tag_frame_type_low[0x20]; 378 379 u8 egress_vlan_membership_high[0x20]; 380 381 u8 egress_vlan_membership_low[0x20]; 382 383 u8 loopback_filter_high[0x20]; 384 385 u8 loopback_filter_low[0x20]; 386 387 u8 egress_general_high[0x20]; 388 389 u8 egress_general_low[0x20]; 390 391 u8 reserved_at_1c0[0x40]; 392 393 u8 egress_hoq_high[0x20]; 394 395 u8 egress_hoq_low[0x20]; 396 397 u8 port_isolation_high[0x20]; 398 399 u8 port_isolation_low[0x20]; 400 401 u8 egress_policy_engine_high[0x20]; 402 403 u8 egress_policy_engine_low[0x20]; 404 405 u8 ingress_tx_link_down_high[0x20]; 406 407 u8 ingress_tx_link_down_low[0x20]; 408 409 u8 egress_stp_filter_high[0x20]; 410 411 u8 egress_stp_filter_low[0x20]; 412 413 u8 egress_hoq_stall_high[0x20]; 414 415 u8 egress_hoq_stall_low[0x20]; 416 417 u8 reserved_at_340[0x440]; 418 }; 419 struct mlx5_ifc_flow_table_prop_layout_bits { 420 u8 ft_support[0x1]; 421 u8 flow_tag[0x1]; 422 u8 flow_counter[0x1]; 423 u8 flow_modify_en[0x1]; 424 u8 modify_root[0x1]; 425 u8 identified_miss_table[0x1]; 426 u8 flow_table_modify[0x1]; 427 u8 encap[0x1]; 428 u8 decap[0x1]; 429 u8 reset_root_to_default[0x1]; 430 u8 reserved_at_a[0x16]; 431 432 u8 reserved_at_20[0x2]; 433 u8 log_max_ft_size[0x6]; 434 u8 reserved_at_28[0x10]; 435 u8 max_ft_level[0x8]; 436 437 u8 reserved_at_40[0x20]; 438 439 u8 reserved_at_60[0x18]; 440 u8 log_max_ft_num[0x8]; 441 442 u8 reserved_at_80[0x10]; 443 u8 log_max_flow_counter[0x8]; 444 u8 log_max_destination[0x8]; 445 446 u8 reserved_at_a0[0x18]; 447 u8 log_max_flow[0x8]; 448 449 u8 reserved_at_c0[0x40]; 450 451 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 452 453 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 454 }; 455 456 struct mlx5_ifc_odp_per_transport_service_cap_bits { 457 u8 send[0x1]; 458 u8 receive[0x1]; 459 u8 write[0x1]; 460 u8 read[0x1]; 461 u8 atomic[0x1]; 462 u8 srq_receive[0x1]; 463 u8 reserved_0[0x1a]; 464 }; 465 466 struct mlx5_ifc_flow_counter_list_bits { 467 u8 reserved_0[0x10]; 468 u8 flow_counter_id[0x10]; 469 470 u8 reserved_1[0x20]; 471 }; 472 473 enum { 474 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 475 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 476 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 477 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 478 }; 479 480 struct mlx5_ifc_dest_format_struct_bits { 481 u8 destination_type[0x8]; 482 u8 destination_id[0x18]; 483 484 u8 reserved_0[0x20]; 485 }; 486 487 struct mlx5_ifc_ipv4_layout_bits { 488 u8 reserved_at_0[0x60]; 489 490 u8 ipv4[0x20]; 491 }; 492 493 struct mlx5_ifc_ipv6_layout_bits { 494 u8 ipv6[16][0x8]; 495 }; 496 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 498 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 499 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 500 u8 reserved_at_0[0x80]; 501 }; 502 503 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 504 u8 smac_47_16[0x20]; 505 506 u8 smac_15_0[0x10]; 507 u8 ethertype[0x10]; 508 509 u8 dmac_47_16[0x20]; 510 511 u8 dmac_15_0[0x10]; 512 u8 first_prio[0x3]; 513 u8 first_cfi[0x1]; 514 u8 first_vid[0xc]; 515 516 u8 ip_protocol[0x8]; 517 u8 ip_dscp[0x6]; 518 u8 ip_ecn[0x2]; 519 u8 cvlan_tag[0x1]; 520 u8 svlan_tag[0x1]; 521 u8 frag[0x1]; 522 u8 reserved_1[0x4]; 523 u8 tcp_flags[0x9]; 524 525 u8 tcp_sport[0x10]; 526 u8 tcp_dport[0x10]; 527 528 u8 reserved_2[0x20]; 529 530 u8 udp_sport[0x10]; 531 u8 udp_dport[0x10]; 532 533 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 534 535 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 536 }; 537 538 struct mlx5_ifc_fte_match_set_misc_bits { 539 u8 reserved_0[0x8]; 540 u8 source_sqn[0x18]; 541 542 u8 reserved_1[0x10]; 543 u8 source_port[0x10]; 544 545 u8 outer_second_prio[0x3]; 546 u8 outer_second_cfi[0x1]; 547 u8 outer_second_vid[0xc]; 548 u8 inner_second_prio[0x3]; 549 u8 inner_second_cfi[0x1]; 550 u8 inner_second_vid[0xc]; 551 552 u8 outer_second_vlan_tag[0x1]; 553 u8 inner_second_vlan_tag[0x1]; 554 u8 reserved_2[0xe]; 555 u8 gre_protocol[0x10]; 556 557 u8 gre_key_h[0x18]; 558 u8 gre_key_l[0x8]; 559 560 u8 vxlan_vni[0x18]; 561 u8 reserved_3[0x8]; 562 563 u8 geneve_vni[0x18]; 564 u8 reserved4[0x7]; 565 u8 geneve_oam[0x1]; 566 567 u8 reserved_5[0xc]; 568 u8 outer_ipv6_flow_label[0x14]; 569 570 u8 reserved_6[0xc]; 571 u8 inner_ipv6_flow_label[0x14]; 572 573 u8 reserved_7[0xa]; 574 u8 geneve_opt_len[0x6]; 575 u8 geneve_protocol_type[0x10]; 576 577 u8 reserved_8[0x8]; 578 u8 bth_dst_qp[0x18]; 579 580 u8 reserved_9[0xa0]; 581 }; 582 583 struct mlx5_ifc_cmd_pas_bits { 584 u8 pa_h[0x20]; 585 586 u8 pa_l[0x14]; 587 u8 reserved_0[0xc]; 588 }; 589 590 struct mlx5_ifc_uint64_bits { 591 u8 hi[0x20]; 592 593 u8 lo[0x20]; 594 }; 595 596 struct mlx5_ifc_application_prio_entry_bits { 597 u8 reserved_0[0x8]; 598 u8 priority[0x3]; 599 u8 reserved_1[0x2]; 600 u8 sel[0x3]; 601 u8 protocol_id[0x10]; 602 }; 603 604 struct mlx5_ifc_nodnic_ring_doorbell_bits { 605 u8 reserved_0[0x8]; 606 u8 ring_pi[0x10]; 607 u8 reserved_1[0x8]; 608 }; 609 610 enum { 611 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 612 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 613 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 614 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 615 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 616 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 617 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 618 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 619 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 620 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 621 }; 622 623 struct mlx5_ifc_ads_bits { 624 u8 fl[0x1]; 625 u8 free_ar[0x1]; 626 u8 reserved_0[0xe]; 627 u8 pkey_index[0x10]; 628 629 u8 reserved_1[0x8]; 630 u8 grh[0x1]; 631 u8 mlid[0x7]; 632 u8 rlid[0x10]; 633 634 u8 ack_timeout[0x5]; 635 u8 reserved_2[0x3]; 636 u8 src_addr_index[0x8]; 637 u8 log_rtm[0x4]; 638 u8 stat_rate[0x4]; 639 u8 hop_limit[0x8]; 640 641 u8 reserved_3[0x4]; 642 u8 tclass[0x8]; 643 u8 flow_label[0x14]; 644 645 u8 rgid_rip[16][0x8]; 646 647 u8 reserved_4[0x4]; 648 u8 f_dscp[0x1]; 649 u8 f_ecn[0x1]; 650 u8 reserved_5[0x1]; 651 u8 f_eth_prio[0x1]; 652 u8 ecn[0x2]; 653 u8 dscp[0x6]; 654 u8 udp_sport[0x10]; 655 656 u8 dei_cfi[0x1]; 657 u8 eth_prio[0x3]; 658 u8 sl[0x4]; 659 u8 port[0x8]; 660 u8 rmac_47_32[0x10]; 661 662 u8 rmac_31_0[0x20]; 663 }; 664 665 struct mlx5_ifc_diagnostic_counter_cap_bits { 666 u8 sync[0x1]; 667 u8 reserved_0[0xf]; 668 u8 counter_id[0x10]; 669 }; 670 671 struct mlx5_ifc_debug_cap_bits { 672 u8 reserved_0[0x18]; 673 u8 log_max_samples[0x8]; 674 675 u8 single[0x1]; 676 u8 repetitive[0x1]; 677 u8 health_mon_rx_activity[0x1]; 678 u8 reserved_1[0x15]; 679 u8 log_min_sample_period[0x8]; 680 681 u8 reserved_2[0x1c0]; 682 683 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 684 }; 685 686 struct mlx5_ifc_qos_cap_bits { 687 u8 packet_pacing[0x1]; 688 u8 esw_scheduling[0x1]; 689 u8 esw_bw_share[0x1]; 690 u8 esw_rate_limit[0x1]; 691 u8 hll[0x1]; 692 u8 packet_pacing_burst_bound[0x1]; 693 u8 packet_pacing_typical_size[0x1]; 694 u8 reserved_at_7[0x19]; 695 696 u8 reserved_at_20[0x20]; 697 698 u8 packet_pacing_max_rate[0x20]; 699 700 u8 packet_pacing_min_rate[0x20]; 701 702 u8 reserved_at_80[0x10]; 703 u8 packet_pacing_rate_table_size[0x10]; 704 705 u8 esw_element_type[0x10]; 706 u8 esw_tsar_type[0x10]; 707 708 u8 reserved_at_c0[0x10]; 709 u8 max_qos_para_vport[0x10]; 710 711 u8 max_tsar_bw_share[0x20]; 712 713 u8 reserved_at_100[0x700]; 714 }; 715 716 struct mlx5_ifc_snapshot_cap_bits { 717 u8 reserved_0[0x1d]; 718 u8 suspend_qp_uc[0x1]; 719 u8 suspend_qp_ud[0x1]; 720 u8 suspend_qp_rc[0x1]; 721 722 u8 reserved_1[0x1c]; 723 u8 restore_pd[0x1]; 724 u8 restore_uar[0x1]; 725 u8 restore_mkey[0x1]; 726 u8 restore_qp[0x1]; 727 728 u8 reserved_2[0x1e]; 729 u8 named_mkey[0x1]; 730 u8 named_qp[0x1]; 731 732 u8 reserved_3[0x7a0]; 733 }; 734 735 struct mlx5_ifc_e_switch_cap_bits { 736 u8 vport_svlan_strip[0x1]; 737 u8 vport_cvlan_strip[0x1]; 738 u8 vport_svlan_insert[0x1]; 739 u8 vport_cvlan_insert_if_not_exist[0x1]; 740 u8 vport_cvlan_insert_overwrite[0x1]; 741 742 u8 reserved_0[0x19]; 743 744 u8 nic_vport_node_guid_modify[0x1]; 745 u8 nic_vport_port_guid_modify[0x1]; 746 747 u8 reserved_1[0x7e0]; 748 }; 749 750 struct mlx5_ifc_flow_table_eswitch_cap_bits { 751 u8 reserved_0[0x200]; 752 753 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 754 755 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 756 757 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 758 759 u8 reserved_1[0x7800]; 760 }; 761 762 struct mlx5_ifc_flow_table_nic_cap_bits { 763 u8 nic_rx_multi_path_tirs[0x1]; 764 u8 nic_rx_multi_path_tirs_fts[0x1]; 765 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 766 u8 reserved_at_3[0x1fd]; 767 768 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 769 770 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 771 772 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 773 774 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 775 776 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 777 778 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 779 780 u8 reserved_1[0x7200]; 781 }; 782 783 struct mlx5_ifc_pddr_module_info_bits { 784 u8 cable_technology[0x8]; 785 u8 cable_breakout[0x8]; 786 u8 ext_ethernet_compliance_code[0x8]; 787 u8 ethernet_compliance_code[0x8]; 788 789 u8 cable_type[0x4]; 790 u8 cable_vendor[0x4]; 791 u8 cable_length[0x8]; 792 u8 cable_identifier[0x8]; 793 u8 cable_power_class[0x8]; 794 795 u8 reserved_at_40[0x8]; 796 u8 cable_rx_amp[0x8]; 797 u8 cable_rx_emphasis[0x8]; 798 u8 cable_tx_equalization[0x8]; 799 800 u8 reserved_at_60[0x8]; 801 u8 cable_attenuation_12g[0x8]; 802 u8 cable_attenuation_7g[0x8]; 803 u8 cable_attenuation_5g[0x8]; 804 805 u8 reserved_at_80[0x8]; 806 u8 rx_cdr_cap[0x4]; 807 u8 tx_cdr_cap[0x4]; 808 u8 reserved_at_90[0x4]; 809 u8 rx_cdr_state[0x4]; 810 u8 reserved_at_98[0x4]; 811 u8 tx_cdr_state[0x4]; 812 813 u8 vendor_name[16][0x8]; 814 815 u8 vendor_pn[16][0x8]; 816 817 u8 vendor_rev[0x20]; 818 819 u8 fw_version[0x20]; 820 821 u8 vendor_sn[16][0x8]; 822 823 u8 temperature[0x10]; 824 u8 voltage[0x10]; 825 826 u8 rx_power_lane0[0x10]; 827 u8 rx_power_lane1[0x10]; 828 829 u8 rx_power_lane2[0x10]; 830 u8 rx_power_lane3[0x10]; 831 832 u8 reserved_at_2c0[0x40]; 833 834 u8 tx_power_lane0[0x10]; 835 u8 tx_power_lane1[0x10]; 836 837 u8 tx_power_lane2[0x10]; 838 u8 tx_power_lane3[0x10]; 839 840 u8 reserved_at_340[0x40]; 841 842 u8 tx_bias_lane0[0x10]; 843 u8 tx_bias_lane1[0x10]; 844 845 u8 tx_bias_lane2[0x10]; 846 u8 tx_bias_lane3[0x10]; 847 848 u8 reserved_at_3c0[0x40]; 849 850 u8 temperature_high_th[0x10]; 851 u8 temperature_low_th[0x10]; 852 853 u8 voltage_high_th[0x10]; 854 u8 voltage_low_th[0x10]; 855 856 u8 rx_power_high_th[0x10]; 857 u8 rx_power_low_th[0x10]; 858 859 u8 tx_power_high_th[0x10]; 860 u8 tx_power_low_th[0x10]; 861 862 u8 tx_bias_high_th[0x10]; 863 u8 tx_bias_low_th[0x10]; 864 865 u8 reserved_at_4a0[0x10]; 866 u8 wavelength[0x10]; 867 868 u8 reserved_at_4c0[0x300]; 869 }; 870 871 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 872 u8 csum_cap[0x1]; 873 u8 vlan_cap[0x1]; 874 u8 lro_cap[0x1]; 875 u8 lro_psh_flag[0x1]; 876 u8 lro_time_stamp[0x1]; 877 u8 lro_max_msg_sz_mode[0x2]; 878 u8 wqe_vlan_insert[0x1]; 879 u8 self_lb_en_modifiable[0x1]; 880 u8 self_lb_mc[0x1]; 881 u8 self_lb_uc[0x1]; 882 u8 max_lso_cap[0x5]; 883 u8 multi_pkt_send_wqe[0x2]; 884 u8 wqe_inline_mode[0x2]; 885 u8 rss_ind_tbl_cap[0x4]; 886 u8 scatter_fcs[0x1]; 887 u8 reserved_1[0x2]; 888 u8 tunnel_lso_const_out_ip_id[0x1]; 889 u8 tunnel_lro_gre[0x1]; 890 u8 tunnel_lro_vxlan[0x1]; 891 u8 tunnel_statless_gre[0x1]; 892 u8 tunnel_stateless_vxlan[0x1]; 893 894 u8 swp[0x1]; 895 u8 swp_csum[0x1]; 896 u8 swp_lso[0x1]; 897 u8 reserved_2[0x1b]; 898 u8 max_geneve_opt_len[0x1]; 899 u8 tunnel_stateless_geneve_rx[0x1]; 900 901 u8 reserved_3[0x10]; 902 u8 lro_min_mss_size[0x10]; 903 904 u8 reserved_4[0x120]; 905 906 u8 lro_timer_supported_periods[4][0x20]; 907 908 u8 reserved_5[0x600]; 909 }; 910 911 enum { 912 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 913 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 914 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 915 }; 916 917 struct mlx5_ifc_roce_cap_bits { 918 u8 roce_apm[0x1]; 919 u8 rts2rts_primary_eth_prio[0x1]; 920 u8 roce_rx_allow_untagged[0x1]; 921 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 922 923 u8 reserved_0[0x1c]; 924 925 u8 reserved_1[0x60]; 926 927 u8 reserved_2[0xc]; 928 u8 l3_type[0x4]; 929 u8 reserved_3[0x8]; 930 u8 roce_version[0x8]; 931 932 u8 reserved_4[0x10]; 933 u8 r_roce_dest_udp_port[0x10]; 934 935 u8 r_roce_max_src_udp_port[0x10]; 936 u8 r_roce_min_src_udp_port[0x10]; 937 938 u8 reserved_5[0x10]; 939 u8 roce_address_table_size[0x10]; 940 941 u8 reserved_6[0x700]; 942 }; 943 944 enum { 945 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 946 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 947 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 948 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 949 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 950 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 951 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 952 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 953 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 954 }; 955 956 enum { 957 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 958 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 959 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 960 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 961 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 962 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 963 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 964 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 965 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 966 }; 967 968 struct mlx5_ifc_atomic_caps_bits { 969 u8 reserved_0[0x40]; 970 971 u8 atomic_req_8B_endianess_mode[0x2]; 972 u8 reserved_1[0x4]; 973 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 974 975 u8 reserved_2[0x19]; 976 977 u8 reserved_3[0x20]; 978 979 u8 reserved_4[0x10]; 980 u8 atomic_operations[0x10]; 981 982 u8 reserved_5[0x10]; 983 u8 atomic_size_qp[0x10]; 984 985 u8 reserved_6[0x10]; 986 u8 atomic_size_dc[0x10]; 987 988 u8 reserved_7[0x720]; 989 }; 990 991 struct mlx5_ifc_odp_cap_bits { 992 u8 reserved_0[0x40]; 993 994 u8 sig[0x1]; 995 u8 reserved_1[0x1f]; 996 997 u8 reserved_2[0x20]; 998 999 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1000 1001 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1002 1003 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1004 1005 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1006 1007 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1008 1009 u8 reserved_3[0x6e0]; 1010 }; 1011 1012 enum { 1013 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1014 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1015 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1016 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1017 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1018 }; 1019 1020 enum { 1021 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1022 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1023 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1024 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1025 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1026 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1027 }; 1028 1029 enum { 1030 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1031 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1032 }; 1033 1034 enum { 1035 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1036 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1037 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1038 }; 1039 1040 struct mlx5_ifc_cmd_hca_cap_bits { 1041 u8 reserved_0[0x80]; 1042 1043 u8 log_max_srq_sz[0x8]; 1044 u8 log_max_qp_sz[0x8]; 1045 u8 reserved_1[0xb]; 1046 u8 log_max_qp[0x5]; 1047 1048 u8 reserved_2[0xb]; 1049 u8 log_max_srq[0x5]; 1050 u8 reserved_3[0x10]; 1051 1052 u8 reserved_4[0x8]; 1053 u8 log_max_cq_sz[0x8]; 1054 u8 reserved_5[0xb]; 1055 u8 log_max_cq[0x5]; 1056 1057 u8 log_max_eq_sz[0x8]; 1058 u8 relaxed_ordering_write[1]; 1059 u8 reserved_6[0x1]; 1060 u8 log_max_mkey[0x6]; 1061 u8 reserved_7[0xb]; 1062 u8 fast_teardown[0x1]; 1063 u8 log_max_eq[0x4]; 1064 1065 u8 max_indirection[0x8]; 1066 u8 reserved_8[0x1]; 1067 u8 log_max_mrw_sz[0x7]; 1068 u8 force_teardown[0x1]; 1069 u8 reserved_9[0x1]; 1070 u8 log_max_bsf_list_size[0x6]; 1071 u8 reserved_10[0x2]; 1072 u8 log_max_klm_list_size[0x6]; 1073 1074 u8 reserved_11[0xa]; 1075 u8 log_max_ra_req_dc[0x6]; 1076 u8 reserved_12[0xa]; 1077 u8 log_max_ra_res_dc[0x6]; 1078 1079 u8 reserved_13[0xa]; 1080 u8 log_max_ra_req_qp[0x6]; 1081 u8 reserved_14[0xa]; 1082 u8 log_max_ra_res_qp[0x6]; 1083 1084 u8 pad_cap[0x1]; 1085 u8 cc_query_allowed[0x1]; 1086 u8 cc_modify_allowed[0x1]; 1087 u8 start_pad[0x1]; 1088 u8 cache_line_128byte[0x1]; 1089 u8 reserved_at_165[0xa]; 1090 u8 qcam_reg[0x1]; 1091 u8 gid_table_size[0x10]; 1092 1093 u8 out_of_seq_cnt[0x1]; 1094 u8 vport_counters[0x1]; 1095 u8 retransmission_q_counters[0x1]; 1096 u8 debug[0x1]; 1097 u8 modify_rq_counters_set_id[0x1]; 1098 u8 rq_delay_drop[0x1]; 1099 u8 max_qp_cnt[0xa]; 1100 u8 pkey_table_size[0x10]; 1101 1102 u8 vport_group_manager[0x1]; 1103 u8 vhca_group_manager[0x1]; 1104 u8 ib_virt[0x1]; 1105 u8 eth_virt[0x1]; 1106 u8 reserved_17[0x1]; 1107 u8 ets[0x1]; 1108 u8 nic_flow_table[0x1]; 1109 u8 eswitch_flow_table[0x1]; 1110 u8 reserved_18[0x1]; 1111 u8 mcam_reg[0x1]; 1112 u8 pcam_reg[0x1]; 1113 u8 local_ca_ack_delay[0x5]; 1114 u8 port_module_event[0x1]; 1115 u8 reserved_19[0x5]; 1116 u8 port_type[0x2]; 1117 u8 num_ports[0x8]; 1118 1119 u8 snapshot[0x1]; 1120 u8 reserved_20[0x2]; 1121 u8 log_max_msg[0x5]; 1122 u8 reserved_21[0x4]; 1123 u8 max_tc[0x4]; 1124 u8 temp_warn_event[0x1]; 1125 u8 dcbx[0x1]; 1126 u8 general_notification_event[0x1]; 1127 u8 reserved_at_1d3[0x2]; 1128 u8 fpga[0x1]; 1129 u8 rol_s[0x1]; 1130 u8 rol_g[0x1]; 1131 u8 reserved_23[0x1]; 1132 u8 wol_s[0x1]; 1133 u8 wol_g[0x1]; 1134 u8 wol_a[0x1]; 1135 u8 wol_b[0x1]; 1136 u8 wol_m[0x1]; 1137 u8 wol_u[0x1]; 1138 u8 wol_p[0x1]; 1139 1140 u8 stat_rate_support[0x10]; 1141 u8 reserved_24[0xc]; 1142 u8 cqe_version[0x4]; 1143 1144 u8 compact_address_vector[0x1]; 1145 u8 striding_rq[0x1]; 1146 u8 reserved_25[0x1]; 1147 u8 ipoib_enhanced_offloads[0x1]; 1148 u8 ipoib_ipoib_offloads[0x1]; 1149 u8 reserved_26[0x8]; 1150 u8 dc_connect_qp[0x1]; 1151 u8 dc_cnak_trace[0x1]; 1152 u8 drain_sigerr[0x1]; 1153 u8 cmdif_checksum[0x2]; 1154 u8 sigerr_cqe[0x1]; 1155 u8 reserved_27[0x1]; 1156 u8 wq_signature[0x1]; 1157 u8 sctr_data_cqe[0x1]; 1158 u8 reserved_28[0x1]; 1159 u8 sho[0x1]; 1160 u8 tph[0x1]; 1161 u8 rf[0x1]; 1162 u8 dct[0x1]; 1163 u8 qos[0x1]; 1164 u8 eth_net_offloads[0x1]; 1165 u8 roce[0x1]; 1166 u8 atomic[0x1]; 1167 u8 reserved_30[0x1]; 1168 1169 u8 cq_oi[0x1]; 1170 u8 cq_resize[0x1]; 1171 u8 cq_moderation[0x1]; 1172 u8 cq_period_mode_modify[0x1]; 1173 u8 cq_invalidate[0x1]; 1174 u8 reserved_at_225[0x1]; 1175 u8 cq_eq_remap[0x1]; 1176 u8 pg[0x1]; 1177 u8 block_lb_mc[0x1]; 1178 u8 exponential_backoff[0x1]; 1179 u8 scqe_break_moderation[0x1]; 1180 u8 cq_period_start_from_cqe[0x1]; 1181 u8 cd[0x1]; 1182 u8 atm[0x1]; 1183 u8 apm[0x1]; 1184 u8 imaicl[0x1]; 1185 u8 reserved_32[0x6]; 1186 u8 qkv[0x1]; 1187 u8 pkv[0x1]; 1188 u8 set_deth_sqpn[0x1]; 1189 u8 reserved_33[0x3]; 1190 u8 xrc[0x1]; 1191 u8 ud[0x1]; 1192 u8 uc[0x1]; 1193 u8 rc[0x1]; 1194 1195 u8 uar_4k[0x1]; 1196 u8 reserved_at_241[0x9]; 1197 u8 uar_sz[0x6]; 1198 u8 reserved_35[0x8]; 1199 u8 log_pg_sz[0x8]; 1200 1201 u8 bf[0x1]; 1202 u8 driver_version[0x1]; 1203 u8 pad_tx_eth_packet[0x1]; 1204 u8 reserved_36[0x8]; 1205 u8 log_bf_reg_size[0x5]; 1206 u8 reserved_37[0x10]; 1207 1208 u8 num_of_diagnostic_counters[0x10]; 1209 u8 max_wqe_sz_sq[0x10]; 1210 1211 u8 reserved_38[0x10]; 1212 u8 max_wqe_sz_rq[0x10]; 1213 1214 u8 reserved_39[0x10]; 1215 u8 max_wqe_sz_sq_dc[0x10]; 1216 1217 u8 reserved_40[0x7]; 1218 u8 max_qp_mcg[0x19]; 1219 1220 u8 reserved_41[0x18]; 1221 u8 log_max_mcg[0x8]; 1222 1223 u8 reserved_42[0x3]; 1224 u8 log_max_transport_domain[0x5]; 1225 u8 reserved_43[0x3]; 1226 u8 log_max_pd[0x5]; 1227 u8 reserved_44[0xb]; 1228 u8 log_max_xrcd[0x5]; 1229 1230 u8 nic_receive_steering_discard[0x1]; 1231 u8 reserved_45[0x7]; 1232 u8 log_max_flow_counter_bulk[0x8]; 1233 u8 max_flow_counter[0x10]; 1234 1235 u8 reserved_46[0x3]; 1236 u8 log_max_rq[0x5]; 1237 u8 reserved_47[0x3]; 1238 u8 log_max_sq[0x5]; 1239 u8 reserved_48[0x3]; 1240 u8 log_max_tir[0x5]; 1241 u8 reserved_49[0x3]; 1242 u8 log_max_tis[0x5]; 1243 1244 u8 basic_cyclic_rcv_wqe[0x1]; 1245 u8 reserved_50[0x2]; 1246 u8 log_max_rmp[0x5]; 1247 u8 reserved_51[0x3]; 1248 u8 log_max_rqt[0x5]; 1249 u8 reserved_52[0x3]; 1250 u8 log_max_rqt_size[0x5]; 1251 u8 reserved_53[0x3]; 1252 u8 log_max_tis_per_sq[0x5]; 1253 1254 u8 reserved_54[0x3]; 1255 u8 log_max_stride_sz_rq[0x5]; 1256 u8 reserved_55[0x3]; 1257 u8 log_min_stride_sz_rq[0x5]; 1258 u8 reserved_56[0x3]; 1259 u8 log_max_stride_sz_sq[0x5]; 1260 u8 reserved_57[0x3]; 1261 u8 log_min_stride_sz_sq[0x5]; 1262 1263 u8 reserved_58[0x1b]; 1264 u8 log_max_wq_sz[0x5]; 1265 1266 u8 nic_vport_change_event[0x1]; 1267 u8 disable_local_lb[0x1]; 1268 u8 reserved_59[0x9]; 1269 u8 log_max_vlan_list[0x5]; 1270 u8 reserved_60[0x3]; 1271 u8 log_max_current_mc_list[0x5]; 1272 u8 reserved_61[0x3]; 1273 u8 log_max_current_uc_list[0x5]; 1274 1275 u8 general_obj_types[0x40]; 1276 1277 u8 reserved_at_440[0x8]; 1278 u8 create_qp_start_hint[0x18]; 1279 1280 u8 reserved_at_460[0x3]; 1281 u8 log_max_uctx[0x5]; 1282 u8 reserved_at_468[0x3]; 1283 u8 log_max_umem[0x5]; 1284 u8 max_num_eqs[0x10]; 1285 1286 u8 reserved_at_480[0x1]; 1287 u8 tls_tx[0x1]; 1288 u8 reserved_at_482[0x1]; 1289 u8 log_max_l2_table[0x5]; 1290 u8 reserved_64[0x8]; 1291 u8 log_uar_page_sz[0x10]; 1292 1293 u8 reserved_65[0x20]; 1294 1295 u8 device_frequency_mhz[0x20]; 1296 1297 u8 device_frequency_khz[0x20]; 1298 1299 u8 reserved_at_500[0x20]; 1300 u8 num_of_uars_per_page[0x20]; 1301 u8 reserved_at_540[0x40]; 1302 1303 u8 log_max_atomic_size_qp[0x8]; 1304 u8 reserved_67[0x10]; 1305 u8 log_max_atomic_size_dc[0x8]; 1306 1307 u8 reserved_at_5a0[0x13]; 1308 u8 log_max_dek[0x5]; 1309 u8 reserved_at_5b8[0x4]; 1310 u8 mini_cqe_resp_stride_index[0x1]; 1311 u8 cqe_128_always[0x1]; 1312 u8 cqe_compression_128b[0x1]; 1313 1314 u8 cqe_compression[0x1]; 1315 1316 u8 cqe_compression_timeout[0x10]; 1317 u8 cqe_compression_max_num[0x10]; 1318 1319 u8 reserved_69[0x220]; 1320 }; 1321 1322 enum mlx5_flow_destination_type { 1323 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1324 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1325 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1326 }; 1327 1328 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1329 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1330 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1331 u8 reserved_0[0x40]; 1332 }; 1333 1334 struct mlx5_ifc_fte_match_param_bits { 1335 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1336 1337 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1338 1339 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1340 1341 u8 reserved_0[0xa00]; 1342 }; 1343 1344 enum { 1345 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1346 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1347 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1348 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1349 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1350 }; 1351 1352 struct mlx5_ifc_rx_hash_field_select_bits { 1353 u8 l3_prot_type[0x1]; 1354 u8 l4_prot_type[0x1]; 1355 u8 selected_fields[0x1e]; 1356 }; 1357 1358 struct mlx5_ifc_tls_capabilities_bits { 1359 u8 tls_1_2_aes_gcm_128[0x1]; 1360 u8 tls_1_3_aes_gcm_128[0x1]; 1361 u8 tls_1_2_aes_gcm_256[0x1]; 1362 u8 tls_1_3_aes_gcm_256[0x1]; 1363 u8 reserved_at_4[0x1c]; 1364 1365 u8 reserved_at_20[0x7e0]; 1366 }; 1367 1368 enum { 1369 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1370 MLX5_WQ_TYPE_CYCLIC = 0x1, 1371 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1372 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1373 }; 1374 1375 enum rq_type { 1376 RQ_TYPE_NONE, 1377 RQ_TYPE_STRIDE, 1378 }; 1379 1380 enum { 1381 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1382 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1383 }; 1384 1385 struct mlx5_ifc_wq_bits { 1386 u8 wq_type[0x4]; 1387 u8 wq_signature[0x1]; 1388 u8 end_padding_mode[0x2]; 1389 u8 cd_slave[0x1]; 1390 u8 reserved_0[0x18]; 1391 1392 u8 hds_skip_first_sge[0x1]; 1393 u8 log2_hds_buf_size[0x3]; 1394 u8 reserved_1[0x7]; 1395 u8 page_offset[0x5]; 1396 u8 lwm[0x10]; 1397 1398 u8 reserved_2[0x8]; 1399 u8 pd[0x18]; 1400 1401 u8 reserved_3[0x8]; 1402 u8 uar_page[0x18]; 1403 1404 u8 dbr_addr[0x40]; 1405 1406 u8 hw_counter[0x20]; 1407 1408 u8 sw_counter[0x20]; 1409 1410 u8 reserved_4[0xc]; 1411 u8 log_wq_stride[0x4]; 1412 u8 reserved_5[0x3]; 1413 u8 log_wq_pg_sz[0x5]; 1414 u8 reserved_6[0x3]; 1415 u8 log_wq_sz[0x5]; 1416 1417 u8 reserved_7[0x15]; 1418 u8 single_wqe_log_num_of_strides[0x3]; 1419 u8 two_byte_shift_en[0x1]; 1420 u8 reserved_8[0x4]; 1421 u8 single_stride_log_num_of_bytes[0x3]; 1422 1423 u8 reserved_9[0x4c0]; 1424 1425 struct mlx5_ifc_cmd_pas_bits pas[0]; 1426 }; 1427 1428 struct mlx5_ifc_rq_num_bits { 1429 u8 reserved_0[0x8]; 1430 u8 rq_num[0x18]; 1431 }; 1432 1433 struct mlx5_ifc_mac_address_layout_bits { 1434 u8 reserved_0[0x10]; 1435 u8 mac_addr_47_32[0x10]; 1436 1437 u8 mac_addr_31_0[0x20]; 1438 }; 1439 1440 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1441 u8 reserved_0[0xa0]; 1442 1443 u8 min_time_between_cnps[0x20]; 1444 1445 u8 reserved_1[0x12]; 1446 u8 cnp_dscp[0x6]; 1447 u8 reserved_2[0x4]; 1448 u8 cnp_prio_mode[0x1]; 1449 u8 cnp_802p_prio[0x3]; 1450 1451 u8 reserved_3[0x720]; 1452 }; 1453 1454 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1455 u8 reserved_0[0x60]; 1456 1457 u8 reserved_1[0x4]; 1458 u8 clamp_tgt_rate[0x1]; 1459 u8 reserved_2[0x3]; 1460 u8 clamp_tgt_rate_after_time_inc[0x1]; 1461 u8 reserved_3[0x17]; 1462 1463 u8 reserved_4[0x20]; 1464 1465 u8 rpg_time_reset[0x20]; 1466 1467 u8 rpg_byte_reset[0x20]; 1468 1469 u8 rpg_threshold[0x20]; 1470 1471 u8 rpg_max_rate[0x20]; 1472 1473 u8 rpg_ai_rate[0x20]; 1474 1475 u8 rpg_hai_rate[0x20]; 1476 1477 u8 rpg_gd[0x20]; 1478 1479 u8 rpg_min_dec_fac[0x20]; 1480 1481 u8 rpg_min_rate[0x20]; 1482 1483 u8 reserved_5[0xe0]; 1484 1485 u8 rate_to_set_on_first_cnp[0x20]; 1486 1487 u8 dce_tcp_g[0x20]; 1488 1489 u8 dce_tcp_rtt[0x20]; 1490 1491 u8 rate_reduce_monitor_period[0x20]; 1492 1493 u8 reserved_6[0x20]; 1494 1495 u8 initial_alpha_value[0x20]; 1496 1497 u8 reserved_7[0x4a0]; 1498 }; 1499 1500 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1501 u8 reserved_0[0x80]; 1502 1503 u8 rppp_max_rps[0x20]; 1504 1505 u8 rpg_time_reset[0x20]; 1506 1507 u8 rpg_byte_reset[0x20]; 1508 1509 u8 rpg_threshold[0x20]; 1510 1511 u8 rpg_max_rate[0x20]; 1512 1513 u8 rpg_ai_rate[0x20]; 1514 1515 u8 rpg_hai_rate[0x20]; 1516 1517 u8 rpg_gd[0x20]; 1518 1519 u8 rpg_min_dec_fac[0x20]; 1520 1521 u8 rpg_min_rate[0x20]; 1522 1523 u8 reserved_1[0x640]; 1524 }; 1525 1526 enum { 1527 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1528 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1529 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1530 }; 1531 1532 struct mlx5_ifc_resize_field_select_bits { 1533 u8 resize_field_select[0x20]; 1534 }; 1535 1536 enum { 1537 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1538 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1539 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1540 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1541 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1542 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1543 }; 1544 1545 struct mlx5_ifc_modify_field_select_bits { 1546 u8 modify_field_select[0x20]; 1547 }; 1548 1549 struct mlx5_ifc_field_select_r_roce_np_bits { 1550 u8 field_select_r_roce_np[0x20]; 1551 }; 1552 1553 enum { 1554 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1555 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1556 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1557 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1558 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1559 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1560 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1561 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1562 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1563 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1564 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1565 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1566 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1567 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1568 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1569 }; 1570 1571 struct mlx5_ifc_field_select_r_roce_rp_bits { 1572 u8 field_select_r_roce_rp[0x20]; 1573 }; 1574 1575 enum { 1576 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1577 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1578 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1579 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1580 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1581 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1582 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1583 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1584 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1585 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1586 }; 1587 1588 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1589 u8 field_select_8021qaurp[0x20]; 1590 }; 1591 1592 struct mlx5_ifc_pptb_reg_bits { 1593 u8 reserved_at_0[0x2]; 1594 u8 mm[0x2]; 1595 u8 reserved_at_4[0x4]; 1596 u8 local_port[0x8]; 1597 u8 reserved_at_10[0x6]; 1598 u8 cm[0x1]; 1599 u8 um[0x1]; 1600 u8 pm[0x8]; 1601 1602 u8 prio_x_buff[0x20]; 1603 1604 u8 pm_msb[0x8]; 1605 u8 reserved_at_48[0x10]; 1606 u8 ctrl_buff[0x4]; 1607 u8 untagged_buff[0x4]; 1608 }; 1609 1610 struct mlx5_ifc_dcbx_app_reg_bits { 1611 u8 reserved_0[0x8]; 1612 u8 port_number[0x8]; 1613 u8 reserved_1[0x10]; 1614 1615 u8 reserved_2[0x1a]; 1616 u8 num_app_prio[0x6]; 1617 1618 u8 reserved_3[0x40]; 1619 1620 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1621 }; 1622 1623 struct mlx5_ifc_dcbx_param_reg_bits { 1624 u8 dcbx_cee_cap[0x1]; 1625 u8 dcbx_ieee_cap[0x1]; 1626 u8 dcbx_standby_cap[0x1]; 1627 u8 reserved_0[0x5]; 1628 u8 port_number[0x8]; 1629 u8 reserved_1[0xa]; 1630 u8 max_application_table_size[0x6]; 1631 1632 u8 reserved_2[0x15]; 1633 u8 version_oper[0x3]; 1634 u8 reserved_3[0x5]; 1635 u8 version_admin[0x3]; 1636 1637 u8 willing_admin[0x1]; 1638 u8 reserved_4[0x3]; 1639 u8 pfc_cap_oper[0x4]; 1640 u8 reserved_5[0x4]; 1641 u8 pfc_cap_admin[0x4]; 1642 u8 reserved_6[0x4]; 1643 u8 num_of_tc_oper[0x4]; 1644 u8 reserved_7[0x4]; 1645 u8 num_of_tc_admin[0x4]; 1646 1647 u8 remote_willing[0x1]; 1648 u8 reserved_8[0x3]; 1649 u8 remote_pfc_cap[0x4]; 1650 u8 reserved_9[0x14]; 1651 u8 remote_num_of_tc[0x4]; 1652 1653 u8 reserved_10[0x18]; 1654 u8 error[0x8]; 1655 1656 u8 reserved_11[0x160]; 1657 }; 1658 1659 struct mlx5_ifc_qhll_bits { 1660 u8 reserved_at_0[0x8]; 1661 u8 local_port[0x8]; 1662 u8 reserved_at_10[0x10]; 1663 1664 u8 reserved_at_20[0x1b]; 1665 u8 hll_time[0x5]; 1666 1667 u8 stall_en[0x1]; 1668 u8 reserved_at_41[0x1c]; 1669 u8 stall_cnt[0x3]; 1670 }; 1671 1672 struct mlx5_ifc_qetcr_reg_bits { 1673 u8 operation_type[0x2]; 1674 u8 cap_local_admin[0x1]; 1675 u8 cap_remote_admin[0x1]; 1676 u8 reserved_0[0x4]; 1677 u8 port_number[0x8]; 1678 u8 reserved_1[0x10]; 1679 1680 u8 reserved_2[0x20]; 1681 1682 u8 tc[8][0x40]; 1683 1684 u8 global_configuration[0x40]; 1685 }; 1686 1687 struct mlx5_ifc_nodnic_ring_config_reg_bits { 1688 u8 queue_address_63_32[0x20]; 1689 1690 u8 queue_address_31_12[0x14]; 1691 u8 reserved_0[0x6]; 1692 u8 log_size[0x6]; 1693 1694 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1695 1696 u8 reserved_1[0x8]; 1697 u8 queue_number[0x18]; 1698 1699 u8 q_key[0x20]; 1700 1701 u8 reserved_2[0x10]; 1702 u8 pkey_index[0x10]; 1703 1704 u8 reserved_3[0x40]; 1705 }; 1706 1707 struct mlx5_ifc_nodnic_cq_arming_word_bits { 1708 u8 reserved_0[0x8]; 1709 u8 cq_ci[0x10]; 1710 u8 reserved_1[0x8]; 1711 }; 1712 1713 enum { 1714 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1715 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1716 }; 1717 1718 enum { 1719 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1720 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1721 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1722 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1723 }; 1724 1725 struct mlx5_ifc_nodnic_event_word_bits { 1726 u8 driver_reset_needed[0x1]; 1727 u8 port_management_change_event[0x1]; 1728 u8 reserved_0[0x19]; 1729 u8 link_type[0x1]; 1730 u8 port_state[0x4]; 1731 }; 1732 1733 struct mlx5_ifc_nic_vport_change_event_bits { 1734 u8 reserved_0[0x10]; 1735 u8 vport_num[0x10]; 1736 1737 u8 reserved_1[0xc0]; 1738 }; 1739 1740 struct mlx5_ifc_pages_req_event_bits { 1741 u8 reserved_0[0x10]; 1742 u8 function_id[0x10]; 1743 1744 u8 num_pages[0x20]; 1745 1746 u8 reserved_1[0xa0]; 1747 }; 1748 1749 struct mlx5_ifc_cmd_inter_comp_event_bits { 1750 u8 command_completion_vector[0x20]; 1751 1752 u8 reserved_0[0xc0]; 1753 }; 1754 1755 struct mlx5_ifc_stall_vl_event_bits { 1756 u8 reserved_0[0x18]; 1757 u8 port_num[0x1]; 1758 u8 reserved_1[0x3]; 1759 u8 vl[0x4]; 1760 1761 u8 reserved_2[0xa0]; 1762 }; 1763 1764 struct mlx5_ifc_db_bf_congestion_event_bits { 1765 u8 event_subtype[0x8]; 1766 u8 reserved_0[0x8]; 1767 u8 congestion_level[0x8]; 1768 u8 reserved_1[0x8]; 1769 1770 u8 reserved_2[0xa0]; 1771 }; 1772 1773 struct mlx5_ifc_gpio_event_bits { 1774 u8 reserved_0[0x60]; 1775 1776 u8 gpio_event_hi[0x20]; 1777 1778 u8 gpio_event_lo[0x20]; 1779 1780 u8 reserved_1[0x40]; 1781 }; 1782 1783 struct mlx5_ifc_port_state_change_event_bits { 1784 u8 reserved_0[0x40]; 1785 1786 u8 port_num[0x4]; 1787 u8 reserved_1[0x1c]; 1788 1789 u8 reserved_2[0x80]; 1790 }; 1791 1792 struct mlx5_ifc_dropped_packet_logged_bits { 1793 u8 reserved_0[0xe0]; 1794 }; 1795 1796 enum { 1797 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1798 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1799 }; 1800 1801 struct mlx5_ifc_cq_error_bits { 1802 u8 reserved_0[0x8]; 1803 u8 cqn[0x18]; 1804 1805 u8 reserved_1[0x20]; 1806 1807 u8 reserved_2[0x18]; 1808 u8 syndrome[0x8]; 1809 1810 u8 reserved_3[0x80]; 1811 }; 1812 1813 struct mlx5_ifc_rdma_page_fault_event_bits { 1814 u8 bytes_commited[0x20]; 1815 1816 u8 r_key[0x20]; 1817 1818 u8 reserved_0[0x10]; 1819 u8 packet_len[0x10]; 1820 1821 u8 rdma_op_len[0x20]; 1822 1823 u8 rdma_va[0x40]; 1824 1825 u8 reserved_1[0x5]; 1826 u8 rdma[0x1]; 1827 u8 write[0x1]; 1828 u8 requestor[0x1]; 1829 u8 qp_number[0x18]; 1830 }; 1831 1832 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1833 u8 bytes_committed[0x20]; 1834 1835 u8 reserved_0[0x10]; 1836 u8 wqe_index[0x10]; 1837 1838 u8 reserved_1[0x10]; 1839 u8 len[0x10]; 1840 1841 u8 reserved_2[0x60]; 1842 1843 u8 reserved_3[0x5]; 1844 u8 rdma[0x1]; 1845 u8 write_read[0x1]; 1846 u8 requestor[0x1]; 1847 u8 qpn[0x18]; 1848 }; 1849 1850 enum { 1851 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1852 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1853 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1854 }; 1855 1856 struct mlx5_ifc_qp_events_bits { 1857 u8 reserved_0[0xa0]; 1858 1859 u8 type[0x8]; 1860 u8 reserved_1[0x18]; 1861 1862 u8 reserved_2[0x8]; 1863 u8 qpn_rqn_sqn[0x18]; 1864 }; 1865 1866 struct mlx5_ifc_dct_events_bits { 1867 u8 reserved_0[0xc0]; 1868 1869 u8 reserved_1[0x8]; 1870 u8 dct_number[0x18]; 1871 }; 1872 1873 struct mlx5_ifc_comp_event_bits { 1874 u8 reserved_0[0xc0]; 1875 1876 u8 reserved_1[0x8]; 1877 u8 cq_number[0x18]; 1878 }; 1879 1880 struct mlx5_ifc_fw_version_bits { 1881 u8 major[0x10]; 1882 u8 reserved_0[0x10]; 1883 1884 u8 minor[0x10]; 1885 u8 subminor[0x10]; 1886 1887 u8 second[0x8]; 1888 u8 minute[0x8]; 1889 u8 hour[0x8]; 1890 u8 reserved_1[0x8]; 1891 1892 u8 year[0x10]; 1893 u8 month[0x8]; 1894 u8 day[0x8]; 1895 }; 1896 1897 enum { 1898 MLX5_QPC_STATE_RST = 0x0, 1899 MLX5_QPC_STATE_INIT = 0x1, 1900 MLX5_QPC_STATE_RTR = 0x2, 1901 MLX5_QPC_STATE_RTS = 0x3, 1902 MLX5_QPC_STATE_SQER = 0x4, 1903 MLX5_QPC_STATE_SQD = 0x5, 1904 MLX5_QPC_STATE_ERR = 0x6, 1905 MLX5_QPC_STATE_SUSPENDED = 0x9, 1906 }; 1907 1908 enum { 1909 MLX5_QPC_ST_RC = 0x0, 1910 MLX5_QPC_ST_UC = 0x1, 1911 MLX5_QPC_ST_UD = 0x2, 1912 MLX5_QPC_ST_XRC = 0x3, 1913 MLX5_QPC_ST_DCI = 0x5, 1914 MLX5_QPC_ST_QP0 = 0x7, 1915 MLX5_QPC_ST_QP1 = 0x8, 1916 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1917 MLX5_QPC_ST_REG_UMR = 0xc, 1918 }; 1919 1920 enum { 1921 MLX5_QP_PM_ARMED = 0x0, 1922 MLX5_QP_PM_REARM = 0x1, 1923 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1924 MLX5_QP_PM_MIGRATED = 0x3, 1925 }; 1926 1927 enum { 1928 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1929 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1930 }; 1931 1932 enum { 1933 MLX5_QPC_MTU_256_BYTES = 0x1, 1934 MLX5_QPC_MTU_512_BYTES = 0x2, 1935 MLX5_QPC_MTU_1K_BYTES = 0x3, 1936 MLX5_QPC_MTU_2K_BYTES = 0x4, 1937 MLX5_QPC_MTU_4K_BYTES = 0x5, 1938 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1939 }; 1940 1941 enum { 1942 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1943 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1944 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1945 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1946 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1947 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1948 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1949 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1950 }; 1951 1952 enum { 1953 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1954 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1955 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1956 }; 1957 1958 enum { 1959 MLX5_QPC_CS_RES_DISABLE = 0x0, 1960 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1961 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1962 }; 1963 1964 struct mlx5_ifc_qpc_bits { 1965 u8 state[0x4]; 1966 u8 lag_tx_port_affinity[0x4]; 1967 u8 st[0x8]; 1968 u8 reserved_1[0x3]; 1969 u8 pm_state[0x2]; 1970 u8 reserved_2[0x7]; 1971 u8 end_padding_mode[0x2]; 1972 u8 reserved_3[0x2]; 1973 1974 u8 wq_signature[0x1]; 1975 u8 block_lb_mc[0x1]; 1976 u8 atomic_like_write_en[0x1]; 1977 u8 latency_sensitive[0x1]; 1978 u8 reserved_4[0x1]; 1979 u8 drain_sigerr[0x1]; 1980 u8 reserved_5[0x2]; 1981 u8 pd[0x18]; 1982 1983 u8 mtu[0x3]; 1984 u8 log_msg_max[0x5]; 1985 u8 reserved_6[0x1]; 1986 u8 log_rq_size[0x4]; 1987 u8 log_rq_stride[0x3]; 1988 u8 no_sq[0x1]; 1989 u8 log_sq_size[0x4]; 1990 u8 reserved_7[0x6]; 1991 u8 rlky[0x1]; 1992 u8 ulp_stateless_offload_mode[0x4]; 1993 1994 u8 counter_set_id[0x8]; 1995 u8 uar_page[0x18]; 1996 1997 u8 reserved_8[0x8]; 1998 u8 user_index[0x18]; 1999 2000 u8 reserved_9[0x3]; 2001 u8 log_page_size[0x5]; 2002 u8 remote_qpn[0x18]; 2003 2004 struct mlx5_ifc_ads_bits primary_address_path; 2005 2006 struct mlx5_ifc_ads_bits secondary_address_path; 2007 2008 u8 log_ack_req_freq[0x4]; 2009 u8 reserved_10[0x4]; 2010 u8 log_sra_max[0x3]; 2011 u8 reserved_11[0x2]; 2012 u8 retry_count[0x3]; 2013 u8 rnr_retry[0x3]; 2014 u8 reserved_12[0x1]; 2015 u8 fre[0x1]; 2016 u8 cur_rnr_retry[0x3]; 2017 u8 cur_retry_count[0x3]; 2018 u8 reserved_13[0x5]; 2019 2020 u8 reserved_14[0x20]; 2021 2022 u8 reserved_15[0x8]; 2023 u8 next_send_psn[0x18]; 2024 2025 u8 reserved_16[0x8]; 2026 u8 cqn_snd[0x18]; 2027 2028 u8 reserved_at_400[0x8]; 2029 2030 u8 deth_sqpn[0x18]; 2031 u8 reserved_17[0x20]; 2032 2033 u8 reserved_18[0x8]; 2034 u8 last_acked_psn[0x18]; 2035 2036 u8 reserved_19[0x8]; 2037 u8 ssn[0x18]; 2038 2039 u8 reserved_20[0x8]; 2040 u8 log_rra_max[0x3]; 2041 u8 reserved_21[0x1]; 2042 u8 atomic_mode[0x4]; 2043 u8 rre[0x1]; 2044 u8 rwe[0x1]; 2045 u8 rae[0x1]; 2046 u8 reserved_22[0x1]; 2047 u8 page_offset[0x6]; 2048 u8 reserved_23[0x3]; 2049 u8 cd_slave_receive[0x1]; 2050 u8 cd_slave_send[0x1]; 2051 u8 cd_master[0x1]; 2052 2053 u8 reserved_24[0x3]; 2054 u8 min_rnr_nak[0x5]; 2055 u8 next_rcv_psn[0x18]; 2056 2057 u8 reserved_25[0x8]; 2058 u8 xrcd[0x18]; 2059 2060 u8 reserved_26[0x8]; 2061 u8 cqn_rcv[0x18]; 2062 2063 u8 dbr_addr[0x40]; 2064 2065 u8 q_key[0x20]; 2066 2067 u8 reserved_27[0x5]; 2068 u8 rq_type[0x3]; 2069 u8 srqn_rmpn[0x18]; 2070 2071 u8 reserved_28[0x8]; 2072 u8 rmsn[0x18]; 2073 2074 u8 hw_sq_wqebb_counter[0x10]; 2075 u8 sw_sq_wqebb_counter[0x10]; 2076 2077 u8 hw_rq_counter[0x20]; 2078 2079 u8 sw_rq_counter[0x20]; 2080 2081 u8 reserved_29[0x20]; 2082 2083 u8 reserved_30[0xf]; 2084 u8 cgs[0x1]; 2085 u8 cs_req[0x8]; 2086 u8 cs_res[0x8]; 2087 2088 u8 dc_access_key[0x40]; 2089 2090 u8 rdma_active[0x1]; 2091 u8 comm_est[0x1]; 2092 u8 suspended[0x1]; 2093 u8 reserved_31[0x5]; 2094 u8 send_msg_psn[0x18]; 2095 2096 u8 reserved_32[0x8]; 2097 u8 rcv_msg_psn[0x18]; 2098 2099 u8 rdma_va[0x40]; 2100 2101 u8 rdma_key[0x20]; 2102 2103 u8 reserved_33[0x20]; 2104 }; 2105 2106 struct mlx5_ifc_roce_addr_layout_bits { 2107 u8 source_l3_address[16][0x8]; 2108 2109 u8 reserved_0[0x3]; 2110 u8 vlan_valid[0x1]; 2111 u8 vlan_id[0xc]; 2112 u8 source_mac_47_32[0x10]; 2113 2114 u8 source_mac_31_0[0x20]; 2115 2116 u8 reserved_1[0x14]; 2117 u8 roce_l3_type[0x4]; 2118 u8 roce_version[0x8]; 2119 2120 u8 reserved_2[0x20]; 2121 }; 2122 2123 struct mlx5_ifc_rdbc_bits { 2124 u8 reserved_0[0x1c]; 2125 u8 type[0x4]; 2126 2127 u8 reserved_1[0x20]; 2128 2129 u8 reserved_2[0x8]; 2130 u8 psn[0x18]; 2131 2132 u8 rkey[0x20]; 2133 2134 u8 address[0x40]; 2135 2136 u8 byte_count[0x20]; 2137 2138 u8 reserved_3[0x20]; 2139 2140 u8 atomic_resp[32][0x8]; 2141 }; 2142 2143 enum { 2144 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2145 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2146 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2147 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2148 }; 2149 2150 struct mlx5_ifc_flow_context_bits { 2151 u8 reserved_0[0x20]; 2152 2153 u8 group_id[0x20]; 2154 2155 u8 reserved_1[0x8]; 2156 u8 flow_tag[0x18]; 2157 2158 u8 reserved_2[0x10]; 2159 u8 action[0x10]; 2160 2161 u8 reserved_3[0x8]; 2162 u8 destination_list_size[0x18]; 2163 2164 u8 reserved_4[0x8]; 2165 u8 flow_counter_list_size[0x18]; 2166 2167 u8 reserved_5[0x140]; 2168 2169 struct mlx5_ifc_fte_match_param_bits match_value; 2170 2171 u8 reserved_6[0x600]; 2172 2173 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2174 }; 2175 2176 enum { 2177 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2178 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2179 }; 2180 2181 struct mlx5_ifc_xrc_srqc_bits { 2182 u8 state[0x4]; 2183 u8 log_xrc_srq_size[0x4]; 2184 u8 reserved_0[0x18]; 2185 2186 u8 wq_signature[0x1]; 2187 u8 cont_srq[0x1]; 2188 u8 reserved_1[0x1]; 2189 u8 rlky[0x1]; 2190 u8 basic_cyclic_rcv_wqe[0x1]; 2191 u8 log_rq_stride[0x3]; 2192 u8 xrcd[0x18]; 2193 2194 u8 page_offset[0x6]; 2195 u8 reserved_2[0x2]; 2196 u8 cqn[0x18]; 2197 2198 u8 reserved_3[0x20]; 2199 2200 u8 reserved_4[0x2]; 2201 u8 log_page_size[0x6]; 2202 u8 user_index[0x18]; 2203 2204 u8 reserved_5[0x20]; 2205 2206 u8 reserved_6[0x8]; 2207 u8 pd[0x18]; 2208 2209 u8 lwm[0x10]; 2210 u8 wqe_cnt[0x10]; 2211 2212 u8 reserved_7[0x40]; 2213 2214 u8 db_record_addr_h[0x20]; 2215 2216 u8 db_record_addr_l[0x1e]; 2217 u8 reserved_8[0x2]; 2218 2219 u8 reserved_9[0x80]; 2220 }; 2221 2222 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2223 u8 counter_error_queues[0x20]; 2224 2225 u8 total_error_queues[0x20]; 2226 2227 u8 send_queue_priority_update_flow[0x20]; 2228 2229 u8 reserved_at_60[0x20]; 2230 2231 u8 nic_receive_steering_discard[0x40]; 2232 2233 u8 receive_discard_vport_down[0x40]; 2234 2235 u8 transmit_discard_vport_down[0x40]; 2236 2237 u8 reserved_at_140[0xec0]; 2238 }; 2239 2240 struct mlx5_ifc_traffic_counter_bits { 2241 u8 packets[0x40]; 2242 2243 u8 octets[0x40]; 2244 }; 2245 2246 struct mlx5_ifc_tisc_bits { 2247 u8 strict_lag_tx_port_affinity[0x1]; 2248 u8 tls_en[0x1]; 2249 u8 reserved_at_2[0x2]; 2250 u8 lag_tx_port_affinity[0x04]; 2251 2252 u8 reserved_at_8[0x4]; 2253 u8 prio[0x4]; 2254 u8 reserved_1[0x10]; 2255 2256 u8 reserved_2[0x100]; 2257 2258 u8 reserved_3[0x8]; 2259 u8 transport_domain[0x18]; 2260 2261 u8 reserved_4[0x8]; 2262 u8 underlay_qpn[0x18]; 2263 2264 u8 reserved_5[0x8]; 2265 u8 pd[0x18]; 2266 2267 u8 reserved_6[0x380]; 2268 }; 2269 2270 enum { 2271 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2272 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2273 }; 2274 2275 enum { 2276 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2277 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2278 }; 2279 2280 enum { 2281 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2282 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2283 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2284 }; 2285 2286 enum { 2287 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2288 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2289 }; 2290 2291 struct mlx5_ifc_tirc_bits { 2292 u8 reserved_0[0x20]; 2293 2294 u8 disp_type[0x4]; 2295 u8 tls_en[0x1]; 2296 u8 reserved_at_25[0x1b]; 2297 2298 u8 reserved_2[0x40]; 2299 2300 u8 reserved_3[0x4]; 2301 u8 lro_timeout_period_usecs[0x10]; 2302 u8 lro_enable_mask[0x4]; 2303 u8 lro_max_msg_sz[0x8]; 2304 2305 u8 reserved_4[0x40]; 2306 2307 u8 reserved_5[0x8]; 2308 u8 inline_rqn[0x18]; 2309 2310 u8 rx_hash_symmetric[0x1]; 2311 u8 reserved_6[0x1]; 2312 u8 tunneled_offload_en[0x1]; 2313 u8 reserved_7[0x5]; 2314 u8 indirect_table[0x18]; 2315 2316 u8 rx_hash_fn[0x4]; 2317 u8 reserved_8[0x2]; 2318 u8 self_lb_en[0x2]; 2319 u8 transport_domain[0x18]; 2320 2321 u8 rx_hash_toeplitz_key[10][0x20]; 2322 2323 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2324 2325 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2326 2327 u8 reserved_9[0x4c0]; 2328 }; 2329 2330 enum { 2331 MLX5_SRQC_STATE_GOOD = 0x0, 2332 MLX5_SRQC_STATE_ERROR = 0x1, 2333 }; 2334 2335 struct mlx5_ifc_srqc_bits { 2336 u8 state[0x4]; 2337 u8 log_srq_size[0x4]; 2338 u8 reserved_0[0x18]; 2339 2340 u8 wq_signature[0x1]; 2341 u8 cont_srq[0x1]; 2342 u8 reserved_1[0x1]; 2343 u8 rlky[0x1]; 2344 u8 reserved_2[0x1]; 2345 u8 log_rq_stride[0x3]; 2346 u8 xrcd[0x18]; 2347 2348 u8 page_offset[0x6]; 2349 u8 reserved_3[0x2]; 2350 u8 cqn[0x18]; 2351 2352 u8 reserved_4[0x20]; 2353 2354 u8 reserved_5[0x2]; 2355 u8 log_page_size[0x6]; 2356 u8 reserved_6[0x18]; 2357 2358 u8 reserved_7[0x20]; 2359 2360 u8 reserved_8[0x8]; 2361 u8 pd[0x18]; 2362 2363 u8 lwm[0x10]; 2364 u8 wqe_cnt[0x10]; 2365 2366 u8 reserved_9[0x40]; 2367 2368 u8 dbr_addr[0x40]; 2369 2370 u8 reserved_10[0x80]; 2371 }; 2372 2373 enum { 2374 MLX5_SQC_STATE_RST = 0x0, 2375 MLX5_SQC_STATE_RDY = 0x1, 2376 MLX5_SQC_STATE_ERR = 0x3, 2377 }; 2378 2379 struct mlx5_ifc_sqc_bits { 2380 u8 rlkey[0x1]; 2381 u8 cd_master[0x1]; 2382 u8 fre[0x1]; 2383 u8 flush_in_error_en[0x1]; 2384 u8 allow_multi_pkt_send_wqe[0x1]; 2385 u8 min_wqe_inline_mode[0x3]; 2386 u8 state[0x4]; 2387 u8 reg_umr[0x1]; 2388 u8 allow_swp[0x1]; 2389 u8 reserved_0[0x12]; 2390 2391 u8 reserved_1[0x8]; 2392 u8 user_index[0x18]; 2393 2394 u8 reserved_2[0x8]; 2395 u8 cqn[0x18]; 2396 2397 u8 reserved_3[0x80]; 2398 2399 u8 qos_para_vport_number[0x10]; 2400 u8 packet_pacing_rate_limit_index[0x10]; 2401 2402 u8 tis_lst_sz[0x10]; 2403 u8 reserved_4[0x10]; 2404 2405 u8 reserved_5[0x40]; 2406 2407 u8 reserved_6[0x8]; 2408 u8 tis_num_0[0x18]; 2409 2410 struct mlx5_ifc_wq_bits wq; 2411 }; 2412 2413 enum { 2414 MLX5_TSAR_TYPE_DWRR = 0, 2415 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2416 MLX5_TSAR_TYPE_ETS = 2 2417 }; 2418 2419 struct mlx5_ifc_tsar_element_attributes_bits { 2420 u8 reserved_0[0x8]; 2421 u8 tsar_type[0x8]; 2422 u8 reserved_1[0x10]; 2423 }; 2424 2425 struct mlx5_ifc_vport_element_attributes_bits { 2426 u8 reserved_0[0x10]; 2427 u8 vport_number[0x10]; 2428 }; 2429 2430 struct mlx5_ifc_vport_tc_element_attributes_bits { 2431 u8 traffic_class[0x10]; 2432 u8 vport_number[0x10]; 2433 }; 2434 2435 struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2436 u8 reserved_0[0x0C]; 2437 u8 traffic_class[0x04]; 2438 u8 qos_para_vport_number[0x10]; 2439 }; 2440 2441 enum { 2442 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2443 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2444 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2445 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2446 }; 2447 2448 struct mlx5_ifc_scheduling_context_bits { 2449 u8 element_type[0x8]; 2450 u8 reserved_at_8[0x18]; 2451 2452 u8 element_attributes[0x20]; 2453 2454 u8 parent_element_id[0x20]; 2455 2456 u8 reserved_at_60[0x40]; 2457 2458 u8 bw_share[0x20]; 2459 2460 u8 max_average_bw[0x20]; 2461 2462 u8 reserved_at_e0[0x120]; 2463 }; 2464 2465 struct mlx5_ifc_rqtc_bits { 2466 u8 reserved_0[0xa0]; 2467 2468 u8 reserved_1[0x10]; 2469 u8 rqt_max_size[0x10]; 2470 2471 u8 reserved_2[0x10]; 2472 u8 rqt_actual_size[0x10]; 2473 2474 u8 reserved_3[0x6a0]; 2475 2476 struct mlx5_ifc_rq_num_bits rq_num[0]; 2477 }; 2478 2479 enum { 2480 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2481 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2482 }; 2483 2484 enum { 2485 MLX5_RQC_STATE_RST = 0x0, 2486 MLX5_RQC_STATE_RDY = 0x1, 2487 MLX5_RQC_STATE_ERR = 0x3, 2488 }; 2489 2490 enum { 2491 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2492 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2493 }; 2494 2495 struct mlx5_ifc_rqc_bits { 2496 u8 rlkey[0x1]; 2497 u8 delay_drop_en[0x1]; 2498 u8 scatter_fcs[0x1]; 2499 u8 vlan_strip_disable[0x1]; 2500 u8 mem_rq_type[0x4]; 2501 u8 state[0x4]; 2502 u8 reserved_1[0x1]; 2503 u8 flush_in_error_en[0x1]; 2504 u8 reserved_2[0x12]; 2505 2506 u8 reserved_3[0x8]; 2507 u8 user_index[0x18]; 2508 2509 u8 reserved_4[0x8]; 2510 u8 cqn[0x18]; 2511 2512 u8 counter_set_id[0x8]; 2513 u8 reserved_5[0x18]; 2514 2515 u8 reserved_6[0x8]; 2516 u8 rmpn[0x18]; 2517 2518 u8 reserved_7[0xe0]; 2519 2520 struct mlx5_ifc_wq_bits wq; 2521 }; 2522 2523 enum { 2524 MLX5_RMPC_STATE_RDY = 0x1, 2525 MLX5_RMPC_STATE_ERR = 0x3, 2526 }; 2527 2528 struct mlx5_ifc_rmpc_bits { 2529 u8 reserved_0[0x8]; 2530 u8 state[0x4]; 2531 u8 reserved_1[0x14]; 2532 2533 u8 basic_cyclic_rcv_wqe[0x1]; 2534 u8 reserved_2[0x1f]; 2535 2536 u8 reserved_3[0x140]; 2537 2538 struct mlx5_ifc_wq_bits wq; 2539 }; 2540 2541 enum { 2542 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2543 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2544 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2545 }; 2546 2547 struct mlx5_ifc_nic_vport_context_bits { 2548 u8 reserved_0[0x5]; 2549 u8 min_wqe_inline_mode[0x3]; 2550 u8 reserved_1[0x15]; 2551 u8 disable_mc_local_lb[0x1]; 2552 u8 disable_uc_local_lb[0x1]; 2553 u8 roce_en[0x1]; 2554 2555 u8 arm_change_event[0x1]; 2556 u8 reserved_2[0x1a]; 2557 u8 event_on_mtu[0x1]; 2558 u8 event_on_promisc_change[0x1]; 2559 u8 event_on_vlan_change[0x1]; 2560 u8 event_on_mc_address_change[0x1]; 2561 u8 event_on_uc_address_change[0x1]; 2562 2563 u8 reserved_3[0xe0]; 2564 2565 u8 reserved_4[0x10]; 2566 u8 mtu[0x10]; 2567 2568 u8 system_image_guid[0x40]; 2569 2570 u8 port_guid[0x40]; 2571 2572 u8 node_guid[0x40]; 2573 2574 u8 reserved_5[0x140]; 2575 2576 u8 qkey_violation_counter[0x10]; 2577 u8 reserved_6[0x10]; 2578 2579 u8 reserved_7[0x420]; 2580 2581 u8 promisc_uc[0x1]; 2582 u8 promisc_mc[0x1]; 2583 u8 promisc_all[0x1]; 2584 u8 reserved_8[0x2]; 2585 u8 allowed_list_type[0x3]; 2586 u8 reserved_9[0xc]; 2587 u8 allowed_list_size[0xc]; 2588 2589 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2590 2591 u8 reserved_10[0x20]; 2592 2593 u8 current_uc_mac_address[0][0x40]; 2594 }; 2595 2596 enum { 2597 MLX5_ACCESS_MODE_PA = 0x0, 2598 MLX5_ACCESS_MODE_MTT = 0x1, 2599 MLX5_ACCESS_MODE_KLM = 0x2, 2600 }; 2601 2602 struct mlx5_ifc_mkc_bits { 2603 u8 reserved_at_0[0x1]; 2604 u8 free[0x1]; 2605 u8 reserved_at_2[0x1]; 2606 u8 access_mode_4_2[0x3]; 2607 u8 reserved_at_6[0x7]; 2608 u8 relaxed_ordering_write[0x1]; 2609 u8 reserved_at_e[0x1]; 2610 u8 small_fence_on_rdma_read_response[0x1]; 2611 u8 umr_en[0x1]; 2612 u8 a[0x1]; 2613 u8 rw[0x1]; 2614 u8 rr[0x1]; 2615 u8 lw[0x1]; 2616 u8 lr[0x1]; 2617 u8 access_mode[0x2]; 2618 u8 reserved_2[0x8]; 2619 2620 u8 qpn[0x18]; 2621 u8 mkey_7_0[0x8]; 2622 2623 u8 reserved_3[0x20]; 2624 2625 u8 length64[0x1]; 2626 u8 bsf_en[0x1]; 2627 u8 sync_umr[0x1]; 2628 u8 reserved_4[0x2]; 2629 u8 expected_sigerr_count[0x1]; 2630 u8 reserved_5[0x1]; 2631 u8 en_rinval[0x1]; 2632 u8 pd[0x18]; 2633 2634 u8 start_addr[0x40]; 2635 2636 u8 len[0x40]; 2637 2638 u8 bsf_octword_size[0x20]; 2639 2640 u8 reserved_6[0x80]; 2641 2642 u8 translations_octword_size[0x20]; 2643 2644 u8 reserved_7[0x1b]; 2645 u8 log_page_size[0x5]; 2646 2647 u8 reserved_8[0x20]; 2648 }; 2649 2650 struct mlx5_ifc_pkey_bits { 2651 u8 reserved_0[0x10]; 2652 u8 pkey[0x10]; 2653 }; 2654 2655 struct mlx5_ifc_array128_auto_bits { 2656 u8 array128_auto[16][0x8]; 2657 }; 2658 2659 enum { 2660 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2661 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2662 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2663 }; 2664 2665 enum { 2666 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2667 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2668 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2669 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2670 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2671 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2672 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2673 }; 2674 2675 enum { 2676 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2677 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2678 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2679 }; 2680 2681 enum { 2682 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2683 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2684 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2685 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2686 }; 2687 2688 enum { 2689 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2690 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2691 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2692 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2693 }; 2694 2695 struct mlx5_ifc_hca_vport_context_bits { 2696 u8 field_select[0x20]; 2697 2698 u8 reserved_0[0xe0]; 2699 2700 u8 sm_virt_aware[0x1]; 2701 u8 has_smi[0x1]; 2702 u8 has_raw[0x1]; 2703 u8 grh_required[0x1]; 2704 u8 reserved_1[0x1]; 2705 u8 min_wqe_inline_mode[0x3]; 2706 u8 reserved_2[0x8]; 2707 u8 port_physical_state[0x4]; 2708 u8 vport_state_policy[0x4]; 2709 u8 port_state[0x4]; 2710 u8 vport_state[0x4]; 2711 2712 u8 reserved_3[0x20]; 2713 2714 u8 system_image_guid[0x40]; 2715 2716 u8 port_guid[0x40]; 2717 2718 u8 node_guid[0x40]; 2719 2720 u8 cap_mask1[0x20]; 2721 2722 u8 cap_mask1_field_select[0x20]; 2723 2724 u8 cap_mask2[0x20]; 2725 2726 u8 cap_mask2_field_select[0x20]; 2727 2728 u8 reserved_4[0x80]; 2729 2730 u8 lid[0x10]; 2731 u8 reserved_5[0x4]; 2732 u8 init_type_reply[0x4]; 2733 u8 lmc[0x3]; 2734 u8 subnet_timeout[0x5]; 2735 2736 u8 sm_lid[0x10]; 2737 u8 sm_sl[0x4]; 2738 u8 reserved_6[0xc]; 2739 2740 u8 qkey_violation_counter[0x10]; 2741 u8 pkey_violation_counter[0x10]; 2742 2743 u8 reserved_7[0xca0]; 2744 }; 2745 2746 union mlx5_ifc_hca_cap_union_bits { 2747 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2748 struct mlx5_ifc_odp_cap_bits odp_cap; 2749 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2750 struct mlx5_ifc_roce_cap_bits roce_cap; 2751 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2752 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2753 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2754 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2755 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2756 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2757 struct mlx5_ifc_qos_cap_bits qos_cap; 2758 struct mlx5_ifc_tls_capabilities_bits tls_capabilities; 2759 u8 reserved_0[0x8000]; 2760 }; 2761 2762 enum { 2763 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 2764 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 2765 }; 2766 2767 struct mlx5_ifc_flow_table_context_bits { 2768 u8 encap_en[0x1]; 2769 u8 decap_en[0x1]; 2770 u8 reserved_at_2[0x2]; 2771 u8 table_miss_action[0x4]; 2772 u8 level[0x8]; 2773 u8 reserved_at_10[0x8]; 2774 u8 log_size[0x8]; 2775 2776 u8 reserved_at_20[0x8]; 2777 u8 table_miss_id[0x18]; 2778 2779 u8 reserved_at_40[0x8]; 2780 u8 lag_master_next_table_id[0x18]; 2781 2782 u8 reserved_at_60[0xe0]; 2783 }; 2784 2785 struct mlx5_ifc_esw_vport_context_bits { 2786 u8 reserved_0[0x3]; 2787 u8 vport_svlan_strip[0x1]; 2788 u8 vport_cvlan_strip[0x1]; 2789 u8 vport_svlan_insert[0x1]; 2790 u8 vport_cvlan_insert[0x2]; 2791 u8 reserved_1[0x18]; 2792 2793 u8 reserved_2[0x20]; 2794 2795 u8 svlan_cfi[0x1]; 2796 u8 svlan_pcp[0x3]; 2797 u8 svlan_id[0xc]; 2798 u8 cvlan_cfi[0x1]; 2799 u8 cvlan_pcp[0x3]; 2800 u8 cvlan_id[0xc]; 2801 2802 u8 reserved_3[0x7a0]; 2803 }; 2804 2805 enum { 2806 MLX5_EQC_STATUS_OK = 0x0, 2807 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2808 }; 2809 2810 enum { 2811 MLX5_EQ_STATE_ARMED = 0x9, 2812 MLX5_EQ_STATE_FIRED = 0xa, 2813 }; 2814 2815 struct mlx5_ifc_eqc_bits { 2816 u8 status[0x4]; 2817 u8 reserved_0[0x9]; 2818 u8 ec[0x1]; 2819 u8 oi[0x1]; 2820 u8 reserved_1[0x5]; 2821 u8 st[0x4]; 2822 u8 reserved_2[0x8]; 2823 2824 u8 reserved_3[0x20]; 2825 2826 u8 reserved_4[0x14]; 2827 u8 page_offset[0x6]; 2828 u8 reserved_5[0x6]; 2829 2830 u8 reserved_6[0x3]; 2831 u8 log_eq_size[0x5]; 2832 u8 uar_page[0x18]; 2833 2834 u8 reserved_7[0x20]; 2835 2836 u8 reserved_8[0x18]; 2837 u8 intr[0x8]; 2838 2839 u8 reserved_9[0x3]; 2840 u8 log_page_size[0x5]; 2841 u8 reserved_10[0x18]; 2842 2843 u8 reserved_11[0x60]; 2844 2845 u8 reserved_12[0x8]; 2846 u8 consumer_counter[0x18]; 2847 2848 u8 reserved_13[0x8]; 2849 u8 producer_counter[0x18]; 2850 2851 u8 reserved_14[0x80]; 2852 }; 2853 2854 enum { 2855 MLX5_DCTC_STATE_ACTIVE = 0x0, 2856 MLX5_DCTC_STATE_DRAINING = 0x1, 2857 MLX5_DCTC_STATE_DRAINED = 0x2, 2858 }; 2859 2860 enum { 2861 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2862 MLX5_DCTC_CS_RES_NA = 0x1, 2863 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2864 }; 2865 2866 enum { 2867 MLX5_DCTC_MTU_256_BYTES = 0x1, 2868 MLX5_DCTC_MTU_512_BYTES = 0x2, 2869 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2870 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2871 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2872 }; 2873 2874 struct mlx5_ifc_dctc_bits { 2875 u8 reserved_0[0x4]; 2876 u8 state[0x4]; 2877 u8 reserved_1[0x18]; 2878 2879 u8 reserved_2[0x8]; 2880 u8 user_index[0x18]; 2881 2882 u8 reserved_3[0x8]; 2883 u8 cqn[0x18]; 2884 2885 u8 counter_set_id[0x8]; 2886 u8 atomic_mode[0x4]; 2887 u8 rre[0x1]; 2888 u8 rwe[0x1]; 2889 u8 rae[0x1]; 2890 u8 atomic_like_write_en[0x1]; 2891 u8 latency_sensitive[0x1]; 2892 u8 rlky[0x1]; 2893 u8 reserved_4[0xe]; 2894 2895 u8 reserved_5[0x8]; 2896 u8 cs_res[0x8]; 2897 u8 reserved_6[0x3]; 2898 u8 min_rnr_nak[0x5]; 2899 u8 reserved_7[0x8]; 2900 2901 u8 reserved_8[0x8]; 2902 u8 srqn[0x18]; 2903 2904 u8 reserved_9[0x8]; 2905 u8 pd[0x18]; 2906 2907 u8 tclass[0x8]; 2908 u8 reserved_10[0x4]; 2909 u8 flow_label[0x14]; 2910 2911 u8 dc_access_key[0x40]; 2912 2913 u8 reserved_11[0x5]; 2914 u8 mtu[0x3]; 2915 u8 port[0x8]; 2916 u8 pkey_index[0x10]; 2917 2918 u8 reserved_12[0x8]; 2919 u8 my_addr_index[0x8]; 2920 u8 reserved_13[0x8]; 2921 u8 hop_limit[0x8]; 2922 2923 u8 dc_access_key_violation_count[0x20]; 2924 2925 u8 reserved_14[0x14]; 2926 u8 dei_cfi[0x1]; 2927 u8 eth_prio[0x3]; 2928 u8 ecn[0x2]; 2929 u8 dscp[0x6]; 2930 2931 u8 reserved_15[0x40]; 2932 }; 2933 2934 enum { 2935 MLX5_CQC_STATUS_OK = 0x0, 2936 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2937 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2938 }; 2939 2940 enum { 2941 CQE_SIZE_64 = 0x0, 2942 CQE_SIZE_128 = 0x1, 2943 }; 2944 2945 enum { 2946 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2947 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2948 }; 2949 2950 enum { 2951 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 2952 MLX5_CQ_STATE_ARMED = 0x9, 2953 MLX5_CQ_STATE_FIRED = 0xa, 2954 }; 2955 2956 struct mlx5_ifc_cqc_bits { 2957 u8 status[0x4]; 2958 u8 reserved_0[0x4]; 2959 u8 cqe_sz[0x3]; 2960 u8 cc[0x1]; 2961 u8 reserved_1[0x1]; 2962 u8 scqe_break_moderation_en[0x1]; 2963 u8 oi[0x1]; 2964 u8 cq_period_mode[0x2]; 2965 u8 cqe_compression_en[0x1]; 2966 u8 mini_cqe_res_format[0x2]; 2967 u8 st[0x4]; 2968 u8 reserved_2[0x8]; 2969 2970 u8 reserved_3[0x20]; 2971 2972 u8 reserved_4[0x14]; 2973 u8 page_offset[0x6]; 2974 u8 reserved_5[0x6]; 2975 2976 u8 reserved_6[0x3]; 2977 u8 log_cq_size[0x5]; 2978 u8 uar_page[0x18]; 2979 2980 u8 reserved_7[0x4]; 2981 u8 cq_period[0xc]; 2982 u8 cq_max_count[0x10]; 2983 2984 u8 reserved_8[0x18]; 2985 u8 c_eqn[0x8]; 2986 2987 u8 reserved_9[0x3]; 2988 u8 log_page_size[0x5]; 2989 u8 reserved_10[0x18]; 2990 2991 u8 reserved_11[0x20]; 2992 2993 u8 reserved_12[0x8]; 2994 u8 last_notified_index[0x18]; 2995 2996 u8 reserved_13[0x8]; 2997 u8 last_solicit_index[0x18]; 2998 2999 u8 reserved_14[0x8]; 3000 u8 consumer_counter[0x18]; 3001 3002 u8 reserved_15[0x8]; 3003 u8 producer_counter[0x18]; 3004 3005 u8 reserved_16[0x40]; 3006 3007 u8 dbr_addr[0x40]; 3008 }; 3009 3010 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3011 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3012 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3013 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3014 u8 reserved_0[0x800]; 3015 }; 3016 3017 struct mlx5_ifc_query_adapter_param_block_bits { 3018 u8 reserved_0[0xc0]; 3019 3020 u8 reserved_1[0x8]; 3021 u8 ieee_vendor_id[0x18]; 3022 3023 u8 reserved_2[0x10]; 3024 u8 vsd_vendor_id[0x10]; 3025 3026 u8 vsd[208][0x8]; 3027 3028 u8 vsd_contd_psid[16][0x8]; 3029 }; 3030 3031 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3032 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3033 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3034 u8 reserved_0[0x20]; 3035 }; 3036 3037 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3038 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3039 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3040 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3041 u8 reserved_0[0x20]; 3042 }; 3043 3044 struct mlx5_ifc_bufferx_reg_bits { 3045 u8 reserved_0[0x6]; 3046 u8 lossy[0x1]; 3047 u8 epsb[0x1]; 3048 u8 reserved_1[0xc]; 3049 u8 size[0xc]; 3050 3051 u8 xoff_threshold[0x10]; 3052 u8 xon_threshold[0x10]; 3053 }; 3054 3055 struct mlx5_ifc_config_item_bits { 3056 u8 valid[0x2]; 3057 u8 reserved_0[0x2]; 3058 u8 header_type[0x2]; 3059 u8 reserved_1[0x2]; 3060 u8 default_location[0x1]; 3061 u8 reserved_2[0x7]; 3062 u8 version[0x4]; 3063 u8 reserved_3[0x3]; 3064 u8 length[0x9]; 3065 3066 u8 type[0x20]; 3067 3068 u8 reserved_4[0x10]; 3069 u8 crc16[0x10]; 3070 }; 3071 3072 struct mlx5_ifc_nodnic_port_config_reg_bits { 3073 struct mlx5_ifc_nodnic_event_word_bits event; 3074 3075 u8 network_en[0x1]; 3076 u8 dma_en[0x1]; 3077 u8 promisc_en[0x1]; 3078 u8 promisc_multicast_en[0x1]; 3079 u8 reserved_0[0x17]; 3080 u8 receive_filter_en[0x5]; 3081 3082 u8 reserved_1[0x10]; 3083 u8 mac_47_32[0x10]; 3084 3085 u8 mac_31_0[0x20]; 3086 3087 u8 receive_filters_mgid_mac[64][0x8]; 3088 3089 u8 gid[16][0x8]; 3090 3091 u8 reserved_2[0x10]; 3092 u8 lid[0x10]; 3093 3094 u8 reserved_3[0xc]; 3095 u8 sm_sl[0x4]; 3096 u8 sm_lid[0x10]; 3097 3098 u8 completion_address_63_32[0x20]; 3099 3100 u8 completion_address_31_12[0x14]; 3101 u8 reserved_4[0x6]; 3102 u8 log_cq_size[0x6]; 3103 3104 u8 working_buffer_address_63_32[0x20]; 3105 3106 u8 working_buffer_address_31_12[0x14]; 3107 u8 reserved_5[0xc]; 3108 3109 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 3110 3111 u8 pkey_index[0x10]; 3112 u8 pkey[0x10]; 3113 3114 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 3115 3116 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 3117 3118 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 3119 3120 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 3121 3122 u8 reserved_6[0x400]; 3123 }; 3124 3125 union mlx5_ifc_event_auto_bits { 3126 struct mlx5_ifc_comp_event_bits comp_event; 3127 struct mlx5_ifc_dct_events_bits dct_events; 3128 struct mlx5_ifc_qp_events_bits qp_events; 3129 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3130 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3131 struct mlx5_ifc_cq_error_bits cq_error; 3132 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3133 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3134 struct mlx5_ifc_gpio_event_bits gpio_event; 3135 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3136 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3137 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3138 struct mlx5_ifc_pages_req_event_bits pages_req_event; 3139 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 3140 u8 reserved_0[0xe0]; 3141 }; 3142 3143 struct mlx5_ifc_health_buffer_bits { 3144 u8 reserved_0[0x100]; 3145 3146 u8 assert_existptr[0x20]; 3147 3148 u8 assert_callra[0x20]; 3149 3150 u8 reserved_1[0x40]; 3151 3152 u8 fw_version[0x20]; 3153 3154 u8 hw_id[0x20]; 3155 3156 u8 reserved_2[0x20]; 3157 3158 u8 irisc_index[0x8]; 3159 u8 synd[0x8]; 3160 u8 ext_synd[0x10]; 3161 }; 3162 3163 struct mlx5_ifc_register_loopback_control_bits { 3164 u8 no_lb[0x1]; 3165 u8 reserved_0[0x7]; 3166 u8 port[0x8]; 3167 u8 reserved_1[0x10]; 3168 3169 u8 reserved_2[0x60]; 3170 }; 3171 3172 struct mlx5_ifc_lrh_bits { 3173 u8 vl[4]; 3174 u8 lver[4]; 3175 u8 sl[4]; 3176 u8 reserved2[2]; 3177 u8 lnh[2]; 3178 u8 dlid[16]; 3179 u8 reserved5[5]; 3180 u8 pkt_len[11]; 3181 u8 slid[16]; 3182 }; 3183 3184 struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3185 u8 reserved_0[0x40]; 3186 3187 u8 reserved_1[0x10]; 3188 u8 rol_mode[0x8]; 3189 u8 wol_mode[0x8]; 3190 }; 3191 3192 struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3193 u8 reserved_0[0x40]; 3194 3195 u8 rol_mode_valid[0x1]; 3196 u8 wol_mode_valid[0x1]; 3197 u8 reserved_1[0xe]; 3198 u8 rol_mode[0x8]; 3199 u8 wol_mode[0x8]; 3200 3201 u8 reserved_2[0x7a0]; 3202 }; 3203 3204 struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3205 u8 virtual_mac_en[0x1]; 3206 u8 mac_aux_v[0x1]; 3207 u8 reserved_0[0x1e]; 3208 3209 u8 reserved_1[0x40]; 3210 3211 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3212 3213 u8 reserved_2[0x760]; 3214 }; 3215 3216 struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3217 u8 virtual_mac_en[0x1]; 3218 u8 mac_aux_v[0x1]; 3219 u8 reserved_0[0x1e]; 3220 3221 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3222 3223 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3224 3225 u8 reserved_1[0x760]; 3226 }; 3227 3228 struct mlx5_ifc_icmd_query_fw_info_out_bits { 3229 struct mlx5_ifc_fw_version_bits fw_version; 3230 3231 u8 reserved_0[0x10]; 3232 u8 hash_signature[0x10]; 3233 3234 u8 psid[16][0x8]; 3235 3236 u8 reserved_1[0x6e0]; 3237 }; 3238 3239 struct mlx5_ifc_icmd_query_cap_in_bits { 3240 u8 reserved_0[0x10]; 3241 u8 capability_group[0x10]; 3242 }; 3243 3244 struct mlx5_ifc_icmd_query_cap_general_bits { 3245 u8 nv_access[0x1]; 3246 u8 fw_info_psid[0x1]; 3247 u8 reserved_0[0x1e]; 3248 3249 u8 reserved_1[0x16]; 3250 u8 rol_s[0x1]; 3251 u8 rol_g[0x1]; 3252 u8 reserved_2[0x1]; 3253 u8 wol_s[0x1]; 3254 u8 wol_g[0x1]; 3255 u8 wol_a[0x1]; 3256 u8 wol_b[0x1]; 3257 u8 wol_m[0x1]; 3258 u8 wol_u[0x1]; 3259 u8 wol_p[0x1]; 3260 }; 3261 3262 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3263 u8 status[0x8]; 3264 u8 reserved_0[0x18]; 3265 3266 u8 reserved_1[0x7e0]; 3267 }; 3268 3269 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3270 u8 status[0x8]; 3271 u8 reserved_0[0x18]; 3272 3273 u8 reserved_1[0x7e0]; 3274 }; 3275 3276 struct mlx5_ifc_icmd_ocbb_init_in_bits { 3277 u8 address_hi[0x20]; 3278 3279 u8 address_lo[0x20]; 3280 3281 u8 reserved_0[0x7c0]; 3282 }; 3283 3284 struct mlx5_ifc_icmd_init_ocsd_in_bits { 3285 u8 reserved_0[0x20]; 3286 3287 u8 address_hi[0x20]; 3288 3289 u8 address_lo[0x20]; 3290 3291 u8 reserved_1[0x7a0]; 3292 }; 3293 3294 struct mlx5_ifc_icmd_access_reg_out_bits { 3295 u8 reserved_0[0x11]; 3296 u8 status[0x7]; 3297 u8 reserved_1[0x8]; 3298 3299 u8 register_id[0x10]; 3300 u8 reserved_2[0x10]; 3301 3302 u8 reserved_3[0x40]; 3303 3304 u8 reserved_4[0x5]; 3305 u8 len[0xb]; 3306 u8 reserved_5[0x10]; 3307 3308 u8 register_data[0][0x20]; 3309 }; 3310 3311 enum { 3312 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3313 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3314 }; 3315 3316 struct mlx5_ifc_icmd_access_reg_in_bits { 3317 u8 constant_1[0x5]; 3318 u8 constant_2[0xb]; 3319 u8 reserved_0[0x10]; 3320 3321 u8 register_id[0x10]; 3322 u8 reserved_1[0x1]; 3323 u8 method[0x7]; 3324 u8 constant_3[0x8]; 3325 3326 u8 reserved_2[0x40]; 3327 3328 u8 constant_4[0x5]; 3329 u8 len[0xb]; 3330 u8 reserved_3[0x10]; 3331 3332 u8 register_data[0][0x20]; 3333 }; 3334 3335 enum { 3336 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3337 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3338 }; 3339 3340 struct mlx5_ifc_teardown_hca_out_bits { 3341 u8 status[0x8]; 3342 u8 reserved_0[0x18]; 3343 3344 u8 syndrome[0x20]; 3345 3346 u8 reserved_1[0x3f]; 3347 3348 u8 state[0x1]; 3349 }; 3350 3351 enum { 3352 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3353 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3354 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3355 }; 3356 3357 struct mlx5_ifc_teardown_hca_in_bits { 3358 u8 opcode[0x10]; 3359 u8 reserved_0[0x10]; 3360 3361 u8 reserved_1[0x10]; 3362 u8 op_mod[0x10]; 3363 3364 u8 reserved_2[0x10]; 3365 u8 profile[0x10]; 3366 3367 u8 reserved_3[0x20]; 3368 }; 3369 3370 struct mlx5_ifc_set_delay_drop_params_out_bits { 3371 u8 status[0x8]; 3372 u8 reserved_at_8[0x18]; 3373 3374 u8 syndrome[0x20]; 3375 3376 u8 reserved_at_40[0x40]; 3377 }; 3378 3379 struct mlx5_ifc_set_delay_drop_params_in_bits { 3380 u8 opcode[0x10]; 3381 u8 reserved_at_10[0x10]; 3382 3383 u8 reserved_at_20[0x10]; 3384 u8 op_mod[0x10]; 3385 3386 u8 reserved_at_40[0x20]; 3387 3388 u8 reserved_at_60[0x10]; 3389 u8 delay_drop_timeout[0x10]; 3390 }; 3391 3392 struct mlx5_ifc_query_delay_drop_params_out_bits { 3393 u8 status[0x8]; 3394 u8 reserved_at_8[0x18]; 3395 3396 u8 syndrome[0x20]; 3397 3398 u8 reserved_at_40[0x20]; 3399 3400 u8 reserved_at_60[0x10]; 3401 u8 delay_drop_timeout[0x10]; 3402 }; 3403 3404 struct mlx5_ifc_query_delay_drop_params_in_bits { 3405 u8 opcode[0x10]; 3406 u8 reserved_at_10[0x10]; 3407 3408 u8 reserved_at_20[0x10]; 3409 u8 op_mod[0x10]; 3410 3411 u8 reserved_at_40[0x40]; 3412 }; 3413 3414 struct mlx5_ifc_suspend_qp_out_bits { 3415 u8 status[0x8]; 3416 u8 reserved_0[0x18]; 3417 3418 u8 syndrome[0x20]; 3419 3420 u8 reserved_1[0x40]; 3421 }; 3422 3423 struct mlx5_ifc_suspend_qp_in_bits { 3424 u8 opcode[0x10]; 3425 u8 reserved_0[0x10]; 3426 3427 u8 reserved_1[0x10]; 3428 u8 op_mod[0x10]; 3429 3430 u8 reserved_2[0x8]; 3431 u8 qpn[0x18]; 3432 3433 u8 reserved_3[0x20]; 3434 }; 3435 3436 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3437 u8 status[0x8]; 3438 u8 reserved_0[0x18]; 3439 3440 u8 syndrome[0x20]; 3441 3442 u8 reserved_1[0x40]; 3443 }; 3444 3445 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3446 u8 opcode[0x10]; 3447 u8 reserved_0[0x10]; 3448 3449 u8 reserved_1[0x10]; 3450 u8 op_mod[0x10]; 3451 3452 u8 reserved_2[0x8]; 3453 u8 qpn[0x18]; 3454 3455 u8 reserved_3[0x20]; 3456 3457 u8 opt_param_mask[0x20]; 3458 3459 u8 reserved_4[0x20]; 3460 3461 struct mlx5_ifc_qpc_bits qpc; 3462 3463 u8 reserved_5[0x80]; 3464 }; 3465 3466 struct mlx5_ifc_sqd2rts_qp_out_bits { 3467 u8 status[0x8]; 3468 u8 reserved_0[0x18]; 3469 3470 u8 syndrome[0x20]; 3471 3472 u8 reserved_1[0x40]; 3473 }; 3474 3475 struct mlx5_ifc_sqd2rts_qp_in_bits { 3476 u8 opcode[0x10]; 3477 u8 reserved_0[0x10]; 3478 3479 u8 reserved_1[0x10]; 3480 u8 op_mod[0x10]; 3481 3482 u8 reserved_2[0x8]; 3483 u8 qpn[0x18]; 3484 3485 u8 reserved_3[0x20]; 3486 3487 u8 opt_param_mask[0x20]; 3488 3489 u8 reserved_4[0x20]; 3490 3491 struct mlx5_ifc_qpc_bits qpc; 3492 3493 u8 reserved_5[0x80]; 3494 }; 3495 3496 struct mlx5_ifc_set_wol_rol_out_bits { 3497 u8 status[0x8]; 3498 u8 reserved_0[0x18]; 3499 3500 u8 syndrome[0x20]; 3501 3502 u8 reserved_1[0x40]; 3503 }; 3504 3505 struct mlx5_ifc_set_wol_rol_in_bits { 3506 u8 opcode[0x10]; 3507 u8 reserved_0[0x10]; 3508 3509 u8 reserved_1[0x10]; 3510 u8 op_mod[0x10]; 3511 3512 u8 rol_mode_valid[0x1]; 3513 u8 wol_mode_valid[0x1]; 3514 u8 reserved_2[0xe]; 3515 u8 rol_mode[0x8]; 3516 u8 wol_mode[0x8]; 3517 3518 u8 reserved_3[0x20]; 3519 }; 3520 3521 struct mlx5_ifc_set_roce_address_out_bits { 3522 u8 status[0x8]; 3523 u8 reserved_0[0x18]; 3524 3525 u8 syndrome[0x20]; 3526 3527 u8 reserved_1[0x40]; 3528 }; 3529 3530 struct mlx5_ifc_set_roce_address_in_bits { 3531 u8 opcode[0x10]; 3532 u8 reserved_0[0x10]; 3533 3534 u8 reserved_1[0x10]; 3535 u8 op_mod[0x10]; 3536 3537 u8 roce_address_index[0x10]; 3538 u8 reserved_2[0x10]; 3539 3540 u8 reserved_3[0x20]; 3541 3542 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3543 }; 3544 3545 struct mlx5_ifc_set_rdb_out_bits { 3546 u8 status[0x8]; 3547 u8 reserved_0[0x18]; 3548 3549 u8 syndrome[0x20]; 3550 3551 u8 reserved_1[0x40]; 3552 }; 3553 3554 struct mlx5_ifc_set_rdb_in_bits { 3555 u8 opcode[0x10]; 3556 u8 reserved_0[0x10]; 3557 3558 u8 reserved_1[0x10]; 3559 u8 op_mod[0x10]; 3560 3561 u8 reserved_2[0x8]; 3562 u8 qpn[0x18]; 3563 3564 u8 reserved_3[0x18]; 3565 u8 rdb_list_size[0x8]; 3566 3567 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3568 }; 3569 3570 struct mlx5_ifc_set_mad_demux_out_bits { 3571 u8 status[0x8]; 3572 u8 reserved_0[0x18]; 3573 3574 u8 syndrome[0x20]; 3575 3576 u8 reserved_1[0x40]; 3577 }; 3578 3579 enum { 3580 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3581 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3582 }; 3583 3584 struct mlx5_ifc_set_mad_demux_in_bits { 3585 u8 opcode[0x10]; 3586 u8 reserved_0[0x10]; 3587 3588 u8 reserved_1[0x10]; 3589 u8 op_mod[0x10]; 3590 3591 u8 reserved_2[0x20]; 3592 3593 u8 reserved_3[0x6]; 3594 u8 demux_mode[0x2]; 3595 u8 reserved_4[0x18]; 3596 }; 3597 3598 struct mlx5_ifc_set_l2_table_entry_out_bits { 3599 u8 status[0x8]; 3600 u8 reserved_0[0x18]; 3601 3602 u8 syndrome[0x20]; 3603 3604 u8 reserved_1[0x40]; 3605 }; 3606 3607 struct mlx5_ifc_set_l2_table_entry_in_bits { 3608 u8 opcode[0x10]; 3609 u8 reserved_0[0x10]; 3610 3611 u8 reserved_1[0x10]; 3612 u8 op_mod[0x10]; 3613 3614 u8 reserved_2[0x60]; 3615 3616 u8 reserved_3[0x8]; 3617 u8 table_index[0x18]; 3618 3619 u8 reserved_4[0x20]; 3620 3621 u8 reserved_5[0x13]; 3622 u8 vlan_valid[0x1]; 3623 u8 vlan[0xc]; 3624 3625 struct mlx5_ifc_mac_address_layout_bits mac_address; 3626 3627 u8 reserved_6[0xc0]; 3628 }; 3629 3630 struct mlx5_ifc_set_issi_out_bits { 3631 u8 status[0x8]; 3632 u8 reserved_0[0x18]; 3633 3634 u8 syndrome[0x20]; 3635 3636 u8 reserved_1[0x40]; 3637 }; 3638 3639 struct mlx5_ifc_set_issi_in_bits { 3640 u8 opcode[0x10]; 3641 u8 reserved_0[0x10]; 3642 3643 u8 reserved_1[0x10]; 3644 u8 op_mod[0x10]; 3645 3646 u8 reserved_2[0x10]; 3647 u8 current_issi[0x10]; 3648 3649 u8 reserved_3[0x20]; 3650 }; 3651 3652 struct mlx5_ifc_set_hca_cap_out_bits { 3653 u8 status[0x8]; 3654 u8 reserved_0[0x18]; 3655 3656 u8 syndrome[0x20]; 3657 3658 u8 reserved_1[0x40]; 3659 }; 3660 3661 struct mlx5_ifc_set_hca_cap_in_bits { 3662 u8 opcode[0x10]; 3663 u8 reserved_0[0x10]; 3664 3665 u8 reserved_1[0x10]; 3666 u8 op_mod[0x10]; 3667 3668 u8 reserved_2[0x40]; 3669 3670 union mlx5_ifc_hca_cap_union_bits capability; 3671 }; 3672 3673 enum { 3674 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3675 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3676 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3677 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3678 }; 3679 3680 struct mlx5_ifc_set_flow_table_root_out_bits { 3681 u8 status[0x8]; 3682 u8 reserved_0[0x18]; 3683 3684 u8 syndrome[0x20]; 3685 3686 u8 reserved_1[0x40]; 3687 }; 3688 3689 struct mlx5_ifc_set_flow_table_root_in_bits { 3690 u8 opcode[0x10]; 3691 u8 reserved_0[0x10]; 3692 3693 u8 reserved_1[0x10]; 3694 u8 op_mod[0x10]; 3695 3696 u8 other_vport[0x1]; 3697 u8 reserved_2[0xf]; 3698 u8 vport_number[0x10]; 3699 3700 u8 reserved_3[0x20]; 3701 3702 u8 table_type[0x8]; 3703 u8 reserved_4[0x18]; 3704 3705 u8 reserved_5[0x8]; 3706 u8 table_id[0x18]; 3707 3708 u8 reserved_6[0x8]; 3709 u8 underlay_qpn[0x18]; 3710 3711 u8 reserved_7[0x120]; 3712 }; 3713 3714 struct mlx5_ifc_set_fte_out_bits { 3715 u8 status[0x8]; 3716 u8 reserved_0[0x18]; 3717 3718 u8 syndrome[0x20]; 3719 3720 u8 reserved_1[0x40]; 3721 }; 3722 3723 struct mlx5_ifc_set_fte_in_bits { 3724 u8 opcode[0x10]; 3725 u8 reserved_0[0x10]; 3726 3727 u8 reserved_1[0x10]; 3728 u8 op_mod[0x10]; 3729 3730 u8 other_vport[0x1]; 3731 u8 reserved_2[0xf]; 3732 u8 vport_number[0x10]; 3733 3734 u8 reserved_3[0x20]; 3735 3736 u8 table_type[0x8]; 3737 u8 reserved_4[0x18]; 3738 3739 u8 reserved_5[0x8]; 3740 u8 table_id[0x18]; 3741 3742 u8 reserved_6[0x18]; 3743 u8 modify_enable_mask[0x8]; 3744 3745 u8 reserved_7[0x20]; 3746 3747 u8 flow_index[0x20]; 3748 3749 u8 reserved_8[0xe0]; 3750 3751 struct mlx5_ifc_flow_context_bits flow_context; 3752 }; 3753 3754 struct mlx5_ifc_set_driver_version_out_bits { 3755 u8 status[0x8]; 3756 u8 reserved_0[0x18]; 3757 3758 u8 syndrome[0x20]; 3759 3760 u8 reserved_1[0x40]; 3761 }; 3762 3763 struct mlx5_ifc_set_driver_version_in_bits { 3764 u8 opcode[0x10]; 3765 u8 reserved_0[0x10]; 3766 3767 u8 reserved_1[0x10]; 3768 u8 op_mod[0x10]; 3769 3770 u8 reserved_2[0x40]; 3771 3772 u8 driver_version[64][0x8]; 3773 }; 3774 3775 struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3776 u8 status[0x8]; 3777 u8 reserved_0[0x18]; 3778 3779 u8 syndrome[0x20]; 3780 3781 u8 reserved_1[0x40]; 3782 }; 3783 3784 struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3785 u8 opcode[0x10]; 3786 u8 reserved_0[0x10]; 3787 3788 u8 reserved_1[0x10]; 3789 u8 op_mod[0x10]; 3790 3791 u8 enable[0x1]; 3792 u8 reserved_2[0x1f]; 3793 3794 u8 reserved_3[0x160]; 3795 3796 struct mlx5_ifc_cmd_pas_bits pas; 3797 }; 3798 3799 struct mlx5_ifc_set_burst_size_out_bits { 3800 u8 status[0x8]; 3801 u8 reserved_0[0x18]; 3802 3803 u8 syndrome[0x20]; 3804 3805 u8 reserved_1[0x40]; 3806 }; 3807 3808 struct mlx5_ifc_set_burst_size_in_bits { 3809 u8 opcode[0x10]; 3810 u8 reserved_0[0x10]; 3811 3812 u8 reserved_1[0x10]; 3813 u8 op_mod[0x10]; 3814 3815 u8 reserved_2[0x20]; 3816 3817 u8 reserved_3[0x9]; 3818 u8 device_burst_size[0x17]; 3819 }; 3820 3821 struct mlx5_ifc_rts2rts_qp_out_bits { 3822 u8 status[0x8]; 3823 u8 reserved_0[0x18]; 3824 3825 u8 syndrome[0x20]; 3826 3827 u8 reserved_1[0x40]; 3828 }; 3829 3830 struct mlx5_ifc_rts2rts_qp_in_bits { 3831 u8 opcode[0x10]; 3832 u8 reserved_0[0x10]; 3833 3834 u8 reserved_1[0x10]; 3835 u8 op_mod[0x10]; 3836 3837 u8 reserved_2[0x8]; 3838 u8 qpn[0x18]; 3839 3840 u8 reserved_3[0x20]; 3841 3842 u8 opt_param_mask[0x20]; 3843 3844 u8 reserved_4[0x20]; 3845 3846 struct mlx5_ifc_qpc_bits qpc; 3847 3848 u8 reserved_5[0x80]; 3849 }; 3850 3851 struct mlx5_ifc_rtr2rts_qp_out_bits { 3852 u8 status[0x8]; 3853 u8 reserved_0[0x18]; 3854 3855 u8 syndrome[0x20]; 3856 3857 u8 reserved_1[0x40]; 3858 }; 3859 3860 struct mlx5_ifc_rtr2rts_qp_in_bits { 3861 u8 opcode[0x10]; 3862 u8 reserved_0[0x10]; 3863 3864 u8 reserved_1[0x10]; 3865 u8 op_mod[0x10]; 3866 3867 u8 reserved_2[0x8]; 3868 u8 qpn[0x18]; 3869 3870 u8 reserved_3[0x20]; 3871 3872 u8 opt_param_mask[0x20]; 3873 3874 u8 reserved_4[0x20]; 3875 3876 struct mlx5_ifc_qpc_bits qpc; 3877 3878 u8 reserved_5[0x80]; 3879 }; 3880 3881 struct mlx5_ifc_rst2init_qp_out_bits { 3882 u8 status[0x8]; 3883 u8 reserved_0[0x18]; 3884 3885 u8 syndrome[0x20]; 3886 3887 u8 reserved_1[0x40]; 3888 }; 3889 3890 struct mlx5_ifc_rst2init_qp_in_bits { 3891 u8 opcode[0x10]; 3892 u8 reserved_0[0x10]; 3893 3894 u8 reserved_1[0x10]; 3895 u8 op_mod[0x10]; 3896 3897 u8 reserved_2[0x8]; 3898 u8 qpn[0x18]; 3899 3900 u8 reserved_3[0x20]; 3901 3902 u8 opt_param_mask[0x20]; 3903 3904 u8 reserved_4[0x20]; 3905 3906 struct mlx5_ifc_qpc_bits qpc; 3907 3908 u8 reserved_5[0x80]; 3909 }; 3910 3911 struct mlx5_ifc_resume_qp_out_bits { 3912 u8 status[0x8]; 3913 u8 reserved_0[0x18]; 3914 3915 u8 syndrome[0x20]; 3916 3917 u8 reserved_1[0x40]; 3918 }; 3919 3920 struct mlx5_ifc_resume_qp_in_bits { 3921 u8 opcode[0x10]; 3922 u8 reserved_0[0x10]; 3923 3924 u8 reserved_1[0x10]; 3925 u8 op_mod[0x10]; 3926 3927 u8 reserved_2[0x8]; 3928 u8 qpn[0x18]; 3929 3930 u8 reserved_3[0x20]; 3931 }; 3932 3933 struct mlx5_ifc_query_xrc_srq_out_bits { 3934 u8 status[0x8]; 3935 u8 reserved_0[0x18]; 3936 3937 u8 syndrome[0x20]; 3938 3939 u8 reserved_1[0x40]; 3940 3941 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3942 3943 u8 reserved_2[0x600]; 3944 3945 u8 pas[0][0x40]; 3946 }; 3947 3948 struct mlx5_ifc_query_xrc_srq_in_bits { 3949 u8 opcode[0x10]; 3950 u8 reserved_0[0x10]; 3951 3952 u8 reserved_1[0x10]; 3953 u8 op_mod[0x10]; 3954 3955 u8 reserved_2[0x8]; 3956 u8 xrc_srqn[0x18]; 3957 3958 u8 reserved_3[0x20]; 3959 }; 3960 3961 struct mlx5_ifc_query_wol_rol_out_bits { 3962 u8 status[0x8]; 3963 u8 reserved_0[0x18]; 3964 3965 u8 syndrome[0x20]; 3966 3967 u8 reserved_1[0x10]; 3968 u8 rol_mode[0x8]; 3969 u8 wol_mode[0x8]; 3970 3971 u8 reserved_2[0x20]; 3972 }; 3973 3974 struct mlx5_ifc_query_wol_rol_in_bits { 3975 u8 opcode[0x10]; 3976 u8 reserved_0[0x10]; 3977 3978 u8 reserved_1[0x10]; 3979 u8 op_mod[0x10]; 3980 3981 u8 reserved_2[0x40]; 3982 }; 3983 3984 enum { 3985 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3986 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3987 }; 3988 3989 struct mlx5_ifc_query_vport_state_out_bits { 3990 u8 status[0x8]; 3991 u8 reserved_0[0x18]; 3992 3993 u8 syndrome[0x20]; 3994 3995 u8 reserved_1[0x20]; 3996 3997 u8 reserved_2[0x18]; 3998 u8 admin_state[0x4]; 3999 u8 state[0x4]; 4000 }; 4001 4002 enum { 4003 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 4004 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 4005 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 4006 }; 4007 4008 struct mlx5_ifc_query_vport_state_in_bits { 4009 u8 opcode[0x10]; 4010 u8 reserved_0[0x10]; 4011 4012 u8 reserved_1[0x10]; 4013 u8 op_mod[0x10]; 4014 4015 u8 other_vport[0x1]; 4016 u8 reserved_2[0xf]; 4017 u8 vport_number[0x10]; 4018 4019 u8 reserved_3[0x20]; 4020 }; 4021 4022 struct mlx5_ifc_query_vnic_env_out_bits { 4023 u8 status[0x8]; 4024 u8 reserved_at_8[0x18]; 4025 4026 u8 syndrome[0x20]; 4027 4028 u8 reserved_at_40[0x40]; 4029 4030 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4031 }; 4032 4033 enum { 4034 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4035 }; 4036 4037 struct mlx5_ifc_query_vnic_env_in_bits { 4038 u8 opcode[0x10]; 4039 u8 reserved_at_10[0x10]; 4040 4041 u8 reserved_at_20[0x10]; 4042 u8 op_mod[0x10]; 4043 4044 u8 other_vport[0x1]; 4045 u8 reserved_at_41[0xf]; 4046 u8 vport_number[0x10]; 4047 4048 u8 reserved_at_60[0x20]; 4049 }; 4050 4051 struct mlx5_ifc_query_vport_counter_out_bits { 4052 u8 status[0x8]; 4053 u8 reserved_0[0x18]; 4054 4055 u8 syndrome[0x20]; 4056 4057 u8 reserved_1[0x40]; 4058 4059 struct mlx5_ifc_traffic_counter_bits received_errors; 4060 4061 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4062 4063 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4064 4065 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4066 4067 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4068 4069 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4070 4071 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4072 4073 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4074 4075 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4076 4077 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4078 4079 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4080 4081 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4082 4083 u8 reserved_2[0xa00]; 4084 }; 4085 4086 enum { 4087 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4088 }; 4089 4090 struct mlx5_ifc_query_vport_counter_in_bits { 4091 u8 opcode[0x10]; 4092 u8 reserved_0[0x10]; 4093 4094 u8 reserved_1[0x10]; 4095 u8 op_mod[0x10]; 4096 4097 u8 other_vport[0x1]; 4098 u8 reserved_2[0xb]; 4099 u8 port_num[0x4]; 4100 u8 vport_number[0x10]; 4101 4102 u8 reserved_3[0x60]; 4103 4104 u8 clear[0x1]; 4105 u8 reserved_4[0x1f]; 4106 4107 u8 reserved_5[0x20]; 4108 }; 4109 4110 struct mlx5_ifc_query_tis_out_bits { 4111 u8 status[0x8]; 4112 u8 reserved_0[0x18]; 4113 4114 u8 syndrome[0x20]; 4115 4116 u8 reserved_1[0x40]; 4117 4118 struct mlx5_ifc_tisc_bits tis_context; 4119 }; 4120 4121 struct mlx5_ifc_query_tis_in_bits { 4122 u8 opcode[0x10]; 4123 u8 reserved_0[0x10]; 4124 4125 u8 reserved_1[0x10]; 4126 u8 op_mod[0x10]; 4127 4128 u8 reserved_2[0x8]; 4129 u8 tisn[0x18]; 4130 4131 u8 reserved_3[0x20]; 4132 }; 4133 4134 struct mlx5_ifc_query_tir_out_bits { 4135 u8 status[0x8]; 4136 u8 reserved_0[0x18]; 4137 4138 u8 syndrome[0x20]; 4139 4140 u8 reserved_1[0xc0]; 4141 4142 struct mlx5_ifc_tirc_bits tir_context; 4143 }; 4144 4145 struct mlx5_ifc_query_tir_in_bits { 4146 u8 opcode[0x10]; 4147 u8 reserved_0[0x10]; 4148 4149 u8 reserved_1[0x10]; 4150 u8 op_mod[0x10]; 4151 4152 u8 reserved_2[0x8]; 4153 u8 tirn[0x18]; 4154 4155 u8 reserved_3[0x20]; 4156 }; 4157 4158 struct mlx5_ifc_query_srq_out_bits { 4159 u8 status[0x8]; 4160 u8 reserved_0[0x18]; 4161 4162 u8 syndrome[0x20]; 4163 4164 u8 reserved_1[0x40]; 4165 4166 struct mlx5_ifc_srqc_bits srq_context_entry; 4167 4168 u8 reserved_2[0x600]; 4169 4170 u8 pas[0][0x40]; 4171 }; 4172 4173 struct mlx5_ifc_query_srq_in_bits { 4174 u8 opcode[0x10]; 4175 u8 reserved_0[0x10]; 4176 4177 u8 reserved_1[0x10]; 4178 u8 op_mod[0x10]; 4179 4180 u8 reserved_2[0x8]; 4181 u8 srqn[0x18]; 4182 4183 u8 reserved_3[0x20]; 4184 }; 4185 4186 struct mlx5_ifc_query_sq_out_bits { 4187 u8 status[0x8]; 4188 u8 reserved_0[0x18]; 4189 4190 u8 syndrome[0x20]; 4191 4192 u8 reserved_1[0xc0]; 4193 4194 struct mlx5_ifc_sqc_bits sq_context; 4195 }; 4196 4197 struct mlx5_ifc_query_sq_in_bits { 4198 u8 opcode[0x10]; 4199 u8 reserved_0[0x10]; 4200 4201 u8 reserved_1[0x10]; 4202 u8 op_mod[0x10]; 4203 4204 u8 reserved_2[0x8]; 4205 u8 sqn[0x18]; 4206 4207 u8 reserved_3[0x20]; 4208 }; 4209 4210 struct mlx5_ifc_query_special_contexts_out_bits { 4211 u8 status[0x8]; 4212 u8 reserved_0[0x18]; 4213 4214 u8 syndrome[0x20]; 4215 4216 u8 dump_fill_mkey[0x20]; 4217 4218 u8 resd_lkey[0x20]; 4219 }; 4220 4221 struct mlx5_ifc_query_special_contexts_in_bits { 4222 u8 opcode[0x10]; 4223 u8 reserved_0[0x10]; 4224 4225 u8 reserved_1[0x10]; 4226 u8 op_mod[0x10]; 4227 4228 u8 reserved_2[0x40]; 4229 }; 4230 4231 struct mlx5_ifc_query_scheduling_element_out_bits { 4232 u8 status[0x8]; 4233 u8 reserved_at_8[0x18]; 4234 4235 u8 syndrome[0x20]; 4236 4237 u8 reserved_at_40[0xc0]; 4238 4239 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4240 4241 u8 reserved_at_300[0x100]; 4242 }; 4243 4244 enum { 4245 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4246 }; 4247 4248 struct mlx5_ifc_query_scheduling_element_in_bits { 4249 u8 opcode[0x10]; 4250 u8 reserved_at_10[0x10]; 4251 4252 u8 reserved_at_20[0x10]; 4253 u8 op_mod[0x10]; 4254 4255 u8 scheduling_hierarchy[0x8]; 4256 u8 reserved_at_48[0x18]; 4257 4258 u8 scheduling_element_id[0x20]; 4259 4260 u8 reserved_at_80[0x180]; 4261 }; 4262 4263 struct mlx5_ifc_query_rqt_out_bits { 4264 u8 status[0x8]; 4265 u8 reserved_0[0x18]; 4266 4267 u8 syndrome[0x20]; 4268 4269 u8 reserved_1[0xc0]; 4270 4271 struct mlx5_ifc_rqtc_bits rqt_context; 4272 }; 4273 4274 struct mlx5_ifc_query_rqt_in_bits { 4275 u8 opcode[0x10]; 4276 u8 reserved_0[0x10]; 4277 4278 u8 reserved_1[0x10]; 4279 u8 op_mod[0x10]; 4280 4281 u8 reserved_2[0x8]; 4282 u8 rqtn[0x18]; 4283 4284 u8 reserved_3[0x20]; 4285 }; 4286 4287 struct mlx5_ifc_query_rq_out_bits { 4288 u8 status[0x8]; 4289 u8 reserved_0[0x18]; 4290 4291 u8 syndrome[0x20]; 4292 4293 u8 reserved_1[0xc0]; 4294 4295 struct mlx5_ifc_rqc_bits rq_context; 4296 }; 4297 4298 struct mlx5_ifc_query_rq_in_bits { 4299 u8 opcode[0x10]; 4300 u8 reserved_0[0x10]; 4301 4302 u8 reserved_1[0x10]; 4303 u8 op_mod[0x10]; 4304 4305 u8 reserved_2[0x8]; 4306 u8 rqn[0x18]; 4307 4308 u8 reserved_3[0x20]; 4309 }; 4310 4311 struct mlx5_ifc_query_roce_address_out_bits { 4312 u8 status[0x8]; 4313 u8 reserved_0[0x18]; 4314 4315 u8 syndrome[0x20]; 4316 4317 u8 reserved_1[0x40]; 4318 4319 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4320 }; 4321 4322 struct mlx5_ifc_query_roce_address_in_bits { 4323 u8 opcode[0x10]; 4324 u8 reserved_0[0x10]; 4325 4326 u8 reserved_1[0x10]; 4327 u8 op_mod[0x10]; 4328 4329 u8 roce_address_index[0x10]; 4330 u8 reserved_2[0x10]; 4331 4332 u8 reserved_3[0x20]; 4333 }; 4334 4335 struct mlx5_ifc_query_rmp_out_bits { 4336 u8 status[0x8]; 4337 u8 reserved_0[0x18]; 4338 4339 u8 syndrome[0x20]; 4340 4341 u8 reserved_1[0xc0]; 4342 4343 struct mlx5_ifc_rmpc_bits rmp_context; 4344 }; 4345 4346 struct mlx5_ifc_query_rmp_in_bits { 4347 u8 opcode[0x10]; 4348 u8 reserved_0[0x10]; 4349 4350 u8 reserved_1[0x10]; 4351 u8 op_mod[0x10]; 4352 4353 u8 reserved_2[0x8]; 4354 u8 rmpn[0x18]; 4355 4356 u8 reserved_3[0x20]; 4357 }; 4358 4359 struct mlx5_ifc_query_rdb_out_bits { 4360 u8 status[0x8]; 4361 u8 reserved_0[0x18]; 4362 4363 u8 syndrome[0x20]; 4364 4365 u8 reserved_1[0x20]; 4366 4367 u8 reserved_2[0x18]; 4368 u8 rdb_list_size[0x8]; 4369 4370 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4371 }; 4372 4373 struct mlx5_ifc_query_rdb_in_bits { 4374 u8 opcode[0x10]; 4375 u8 reserved_0[0x10]; 4376 4377 u8 reserved_1[0x10]; 4378 u8 op_mod[0x10]; 4379 4380 u8 reserved_2[0x8]; 4381 u8 qpn[0x18]; 4382 4383 u8 reserved_3[0x20]; 4384 }; 4385 4386 struct mlx5_ifc_query_qp_out_bits { 4387 u8 status[0x8]; 4388 u8 reserved_0[0x18]; 4389 4390 u8 syndrome[0x20]; 4391 4392 u8 reserved_1[0x40]; 4393 4394 u8 opt_param_mask[0x20]; 4395 4396 u8 reserved_2[0x20]; 4397 4398 struct mlx5_ifc_qpc_bits qpc; 4399 4400 u8 reserved_3[0x80]; 4401 4402 u8 pas[0][0x40]; 4403 }; 4404 4405 struct mlx5_ifc_query_qp_in_bits { 4406 u8 opcode[0x10]; 4407 u8 reserved_0[0x10]; 4408 4409 u8 reserved_1[0x10]; 4410 u8 op_mod[0x10]; 4411 4412 u8 reserved_2[0x8]; 4413 u8 qpn[0x18]; 4414 4415 u8 reserved_3[0x20]; 4416 }; 4417 4418 struct mlx5_ifc_query_q_counter_out_bits { 4419 u8 status[0x8]; 4420 u8 reserved_0[0x18]; 4421 4422 u8 syndrome[0x20]; 4423 4424 u8 reserved_1[0x40]; 4425 4426 u8 rx_write_requests[0x20]; 4427 4428 u8 reserved_2[0x20]; 4429 4430 u8 rx_read_requests[0x20]; 4431 4432 u8 reserved_3[0x20]; 4433 4434 u8 rx_atomic_requests[0x20]; 4435 4436 u8 reserved_4[0x20]; 4437 4438 u8 rx_dct_connect[0x20]; 4439 4440 u8 reserved_5[0x20]; 4441 4442 u8 out_of_buffer[0x20]; 4443 4444 u8 reserved_7[0x20]; 4445 4446 u8 out_of_sequence[0x20]; 4447 4448 u8 reserved_8[0x20]; 4449 4450 u8 duplicate_request[0x20]; 4451 4452 u8 reserved_9[0x20]; 4453 4454 u8 rnr_nak_retry_err[0x20]; 4455 4456 u8 reserved_10[0x20]; 4457 4458 u8 packet_seq_err[0x20]; 4459 4460 u8 reserved_11[0x20]; 4461 4462 u8 implied_nak_seq_err[0x20]; 4463 4464 u8 reserved_12[0x20]; 4465 4466 u8 local_ack_timeout_err[0x20]; 4467 4468 u8 reserved_13[0x20]; 4469 4470 u8 resp_rnr_nak[0x20]; 4471 4472 u8 reserved_14[0x20]; 4473 4474 u8 req_rnr_retries_exceeded[0x20]; 4475 4476 u8 reserved_15[0x460]; 4477 }; 4478 4479 struct mlx5_ifc_query_q_counter_in_bits { 4480 u8 opcode[0x10]; 4481 u8 reserved_0[0x10]; 4482 4483 u8 reserved_1[0x10]; 4484 u8 op_mod[0x10]; 4485 4486 u8 reserved_2[0x80]; 4487 4488 u8 clear[0x1]; 4489 u8 reserved_3[0x1f]; 4490 4491 u8 reserved_4[0x18]; 4492 u8 counter_set_id[0x8]; 4493 }; 4494 4495 struct mlx5_ifc_query_pages_out_bits { 4496 u8 status[0x8]; 4497 u8 reserved_0[0x18]; 4498 4499 u8 syndrome[0x20]; 4500 4501 u8 reserved_1[0x10]; 4502 u8 function_id[0x10]; 4503 4504 u8 num_pages[0x20]; 4505 }; 4506 4507 enum { 4508 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4509 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4510 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4511 }; 4512 4513 struct mlx5_ifc_query_pages_in_bits { 4514 u8 opcode[0x10]; 4515 u8 reserved_0[0x10]; 4516 4517 u8 reserved_1[0x10]; 4518 u8 op_mod[0x10]; 4519 4520 u8 reserved_2[0x10]; 4521 u8 function_id[0x10]; 4522 4523 u8 reserved_3[0x20]; 4524 }; 4525 4526 struct mlx5_ifc_query_nic_vport_context_out_bits { 4527 u8 status[0x8]; 4528 u8 reserved_0[0x18]; 4529 4530 u8 syndrome[0x20]; 4531 4532 u8 reserved_1[0x40]; 4533 4534 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4535 }; 4536 4537 struct mlx5_ifc_query_nic_vport_context_in_bits { 4538 u8 opcode[0x10]; 4539 u8 reserved_0[0x10]; 4540 4541 u8 reserved_1[0x10]; 4542 u8 op_mod[0x10]; 4543 4544 u8 other_vport[0x1]; 4545 u8 reserved_2[0xf]; 4546 u8 vport_number[0x10]; 4547 4548 u8 reserved_3[0x5]; 4549 u8 allowed_list_type[0x3]; 4550 u8 reserved_4[0x18]; 4551 }; 4552 4553 struct mlx5_ifc_query_mkey_out_bits { 4554 u8 status[0x8]; 4555 u8 reserved_0[0x18]; 4556 4557 u8 syndrome[0x20]; 4558 4559 u8 reserved_1[0x40]; 4560 4561 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4562 4563 u8 reserved_2[0x600]; 4564 4565 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4566 4567 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4568 }; 4569 4570 struct mlx5_ifc_query_mkey_in_bits { 4571 u8 opcode[0x10]; 4572 u8 reserved_0[0x10]; 4573 4574 u8 reserved_1[0x10]; 4575 u8 op_mod[0x10]; 4576 4577 u8 reserved_2[0x8]; 4578 u8 mkey_index[0x18]; 4579 4580 u8 pg_access[0x1]; 4581 u8 reserved_3[0x1f]; 4582 }; 4583 4584 struct mlx5_ifc_query_mad_demux_out_bits { 4585 u8 status[0x8]; 4586 u8 reserved_0[0x18]; 4587 4588 u8 syndrome[0x20]; 4589 4590 u8 reserved_1[0x40]; 4591 4592 u8 mad_dumux_parameters_block[0x20]; 4593 }; 4594 4595 struct mlx5_ifc_query_mad_demux_in_bits { 4596 u8 opcode[0x10]; 4597 u8 reserved_0[0x10]; 4598 4599 u8 reserved_1[0x10]; 4600 u8 op_mod[0x10]; 4601 4602 u8 reserved_2[0x40]; 4603 }; 4604 4605 struct mlx5_ifc_query_l2_table_entry_out_bits { 4606 u8 status[0x8]; 4607 u8 reserved_0[0x18]; 4608 4609 u8 syndrome[0x20]; 4610 4611 u8 reserved_1[0xa0]; 4612 4613 u8 reserved_2[0x13]; 4614 u8 vlan_valid[0x1]; 4615 u8 vlan[0xc]; 4616 4617 struct mlx5_ifc_mac_address_layout_bits mac_address; 4618 4619 u8 reserved_3[0xc0]; 4620 }; 4621 4622 struct mlx5_ifc_query_l2_table_entry_in_bits { 4623 u8 opcode[0x10]; 4624 u8 reserved_0[0x10]; 4625 4626 u8 reserved_1[0x10]; 4627 u8 op_mod[0x10]; 4628 4629 u8 reserved_2[0x60]; 4630 4631 u8 reserved_3[0x8]; 4632 u8 table_index[0x18]; 4633 4634 u8 reserved_4[0x140]; 4635 }; 4636 4637 struct mlx5_ifc_query_issi_out_bits { 4638 u8 status[0x8]; 4639 u8 reserved_0[0x18]; 4640 4641 u8 syndrome[0x20]; 4642 4643 u8 reserved_1[0x10]; 4644 u8 current_issi[0x10]; 4645 4646 u8 reserved_2[0xa0]; 4647 4648 u8 supported_issi_reserved[76][0x8]; 4649 u8 supported_issi_dw0[0x20]; 4650 }; 4651 4652 struct mlx5_ifc_query_issi_in_bits { 4653 u8 opcode[0x10]; 4654 u8 reserved_0[0x10]; 4655 4656 u8 reserved_1[0x10]; 4657 u8 op_mod[0x10]; 4658 4659 u8 reserved_2[0x40]; 4660 }; 4661 4662 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4663 u8 status[0x8]; 4664 u8 reserved_0[0x18]; 4665 4666 u8 syndrome[0x20]; 4667 4668 u8 reserved_1[0x40]; 4669 4670 struct mlx5_ifc_pkey_bits pkey[0]; 4671 }; 4672 4673 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4674 u8 opcode[0x10]; 4675 u8 reserved_0[0x10]; 4676 4677 u8 reserved_1[0x10]; 4678 u8 op_mod[0x10]; 4679 4680 u8 other_vport[0x1]; 4681 u8 reserved_2[0xb]; 4682 u8 port_num[0x4]; 4683 u8 vport_number[0x10]; 4684 4685 u8 reserved_3[0x10]; 4686 u8 pkey_index[0x10]; 4687 }; 4688 4689 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4690 u8 status[0x8]; 4691 u8 reserved_0[0x18]; 4692 4693 u8 syndrome[0x20]; 4694 4695 u8 reserved_1[0x20]; 4696 4697 u8 gids_num[0x10]; 4698 u8 reserved_2[0x10]; 4699 4700 struct mlx5_ifc_array128_auto_bits gid[0]; 4701 }; 4702 4703 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4704 u8 opcode[0x10]; 4705 u8 reserved_0[0x10]; 4706 4707 u8 reserved_1[0x10]; 4708 u8 op_mod[0x10]; 4709 4710 u8 other_vport[0x1]; 4711 u8 reserved_2[0xb]; 4712 u8 port_num[0x4]; 4713 u8 vport_number[0x10]; 4714 4715 u8 reserved_3[0x10]; 4716 u8 gid_index[0x10]; 4717 }; 4718 4719 struct mlx5_ifc_query_hca_vport_context_out_bits { 4720 u8 status[0x8]; 4721 u8 reserved_0[0x18]; 4722 4723 u8 syndrome[0x20]; 4724 4725 u8 reserved_1[0x40]; 4726 4727 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4728 }; 4729 4730 struct mlx5_ifc_query_hca_vport_context_in_bits { 4731 u8 opcode[0x10]; 4732 u8 reserved_0[0x10]; 4733 4734 u8 reserved_1[0x10]; 4735 u8 op_mod[0x10]; 4736 4737 u8 other_vport[0x1]; 4738 u8 reserved_2[0xb]; 4739 u8 port_num[0x4]; 4740 u8 vport_number[0x10]; 4741 4742 u8 reserved_3[0x20]; 4743 }; 4744 4745 struct mlx5_ifc_query_hca_cap_out_bits { 4746 u8 status[0x8]; 4747 u8 reserved_0[0x18]; 4748 4749 u8 syndrome[0x20]; 4750 4751 u8 reserved_1[0x40]; 4752 4753 union mlx5_ifc_hca_cap_union_bits capability; 4754 }; 4755 4756 struct mlx5_ifc_query_hca_cap_in_bits { 4757 u8 opcode[0x10]; 4758 u8 reserved_0[0x10]; 4759 4760 u8 reserved_1[0x10]; 4761 u8 op_mod[0x10]; 4762 4763 u8 reserved_2[0x40]; 4764 }; 4765 4766 struct mlx5_ifc_query_flow_table_out_bits { 4767 u8 status[0x8]; 4768 u8 reserved_at_8[0x18]; 4769 4770 u8 syndrome[0x20]; 4771 4772 u8 reserved_at_40[0x80]; 4773 4774 struct mlx5_ifc_flow_table_context_bits flow_table_context; 4775 }; 4776 4777 struct mlx5_ifc_query_flow_table_in_bits { 4778 u8 opcode[0x10]; 4779 u8 reserved_0[0x10]; 4780 4781 u8 reserved_1[0x10]; 4782 u8 op_mod[0x10]; 4783 4784 u8 other_vport[0x1]; 4785 u8 reserved_2[0xf]; 4786 u8 vport_number[0x10]; 4787 4788 u8 reserved_3[0x20]; 4789 4790 u8 table_type[0x8]; 4791 u8 reserved_4[0x18]; 4792 4793 u8 reserved_5[0x8]; 4794 u8 table_id[0x18]; 4795 4796 u8 reserved_6[0x140]; 4797 }; 4798 4799 struct mlx5_ifc_query_fte_out_bits { 4800 u8 status[0x8]; 4801 u8 reserved_0[0x18]; 4802 4803 u8 syndrome[0x20]; 4804 4805 u8 reserved_1[0x1c0]; 4806 4807 struct mlx5_ifc_flow_context_bits flow_context; 4808 }; 4809 4810 struct mlx5_ifc_query_fte_in_bits { 4811 u8 opcode[0x10]; 4812 u8 reserved_0[0x10]; 4813 4814 u8 reserved_1[0x10]; 4815 u8 op_mod[0x10]; 4816 4817 u8 other_vport[0x1]; 4818 u8 reserved_2[0xf]; 4819 u8 vport_number[0x10]; 4820 4821 u8 reserved_3[0x20]; 4822 4823 u8 table_type[0x8]; 4824 u8 reserved_4[0x18]; 4825 4826 u8 reserved_5[0x8]; 4827 u8 table_id[0x18]; 4828 4829 u8 reserved_6[0x40]; 4830 4831 u8 flow_index[0x20]; 4832 4833 u8 reserved_7[0xe0]; 4834 }; 4835 4836 enum { 4837 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4838 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4839 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4840 }; 4841 4842 struct mlx5_ifc_query_flow_group_out_bits { 4843 u8 status[0x8]; 4844 u8 reserved_0[0x18]; 4845 4846 u8 syndrome[0x20]; 4847 4848 u8 reserved_1[0xa0]; 4849 4850 u8 start_flow_index[0x20]; 4851 4852 u8 reserved_2[0x20]; 4853 4854 u8 end_flow_index[0x20]; 4855 4856 u8 reserved_3[0xa0]; 4857 4858 u8 reserved_4[0x18]; 4859 u8 match_criteria_enable[0x8]; 4860 4861 struct mlx5_ifc_fte_match_param_bits match_criteria; 4862 4863 u8 reserved_5[0xe00]; 4864 }; 4865 4866 struct mlx5_ifc_query_flow_group_in_bits { 4867 u8 opcode[0x10]; 4868 u8 reserved_0[0x10]; 4869 4870 u8 reserved_1[0x10]; 4871 u8 op_mod[0x10]; 4872 4873 u8 other_vport[0x1]; 4874 u8 reserved_2[0xf]; 4875 u8 vport_number[0x10]; 4876 4877 u8 reserved_3[0x20]; 4878 4879 u8 table_type[0x8]; 4880 u8 reserved_4[0x18]; 4881 4882 u8 reserved_5[0x8]; 4883 u8 table_id[0x18]; 4884 4885 u8 group_id[0x20]; 4886 4887 u8 reserved_6[0x120]; 4888 }; 4889 4890 struct mlx5_ifc_query_flow_counter_out_bits { 4891 u8 status[0x8]; 4892 u8 reserved_at_8[0x18]; 4893 4894 u8 syndrome[0x20]; 4895 4896 u8 reserved_at_40[0x40]; 4897 4898 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4899 }; 4900 4901 struct mlx5_ifc_query_flow_counter_in_bits { 4902 u8 opcode[0x10]; 4903 u8 reserved_at_10[0x10]; 4904 4905 u8 reserved_at_20[0x10]; 4906 u8 op_mod[0x10]; 4907 4908 u8 reserved_at_40[0x80]; 4909 4910 u8 clear[0x1]; 4911 u8 reserved_at_c1[0xf]; 4912 u8 num_of_counters[0x10]; 4913 4914 u8 reserved_at_e0[0x10]; 4915 u8 flow_counter_id[0x10]; 4916 }; 4917 4918 struct mlx5_ifc_query_esw_vport_context_out_bits { 4919 u8 status[0x8]; 4920 u8 reserved_0[0x18]; 4921 4922 u8 syndrome[0x20]; 4923 4924 u8 reserved_1[0x40]; 4925 4926 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4927 }; 4928 4929 struct mlx5_ifc_query_esw_vport_context_in_bits { 4930 u8 opcode[0x10]; 4931 u8 reserved_0[0x10]; 4932 4933 u8 reserved_1[0x10]; 4934 u8 op_mod[0x10]; 4935 4936 u8 other_vport[0x1]; 4937 u8 reserved_2[0xf]; 4938 u8 vport_number[0x10]; 4939 4940 u8 reserved_3[0x20]; 4941 }; 4942 4943 struct mlx5_ifc_query_eq_out_bits { 4944 u8 status[0x8]; 4945 u8 reserved_0[0x18]; 4946 4947 u8 syndrome[0x20]; 4948 4949 u8 reserved_1[0x40]; 4950 4951 struct mlx5_ifc_eqc_bits eq_context_entry; 4952 4953 u8 reserved_2[0x40]; 4954 4955 u8 event_bitmask[0x40]; 4956 4957 u8 reserved_3[0x580]; 4958 4959 u8 pas[0][0x40]; 4960 }; 4961 4962 struct mlx5_ifc_query_eq_in_bits { 4963 u8 opcode[0x10]; 4964 u8 reserved_0[0x10]; 4965 4966 u8 reserved_1[0x10]; 4967 u8 op_mod[0x10]; 4968 4969 u8 reserved_2[0x18]; 4970 u8 eq_number[0x8]; 4971 4972 u8 reserved_3[0x20]; 4973 }; 4974 4975 struct mlx5_ifc_query_dct_out_bits { 4976 u8 status[0x8]; 4977 u8 reserved_0[0x18]; 4978 4979 u8 syndrome[0x20]; 4980 4981 u8 reserved_1[0x40]; 4982 4983 struct mlx5_ifc_dctc_bits dct_context_entry; 4984 4985 u8 reserved_2[0x180]; 4986 }; 4987 4988 struct mlx5_ifc_query_dct_in_bits { 4989 u8 opcode[0x10]; 4990 u8 reserved_0[0x10]; 4991 4992 u8 reserved_1[0x10]; 4993 u8 op_mod[0x10]; 4994 4995 u8 reserved_2[0x8]; 4996 u8 dctn[0x18]; 4997 4998 u8 reserved_3[0x20]; 4999 }; 5000 5001 struct mlx5_ifc_query_dc_cnak_trace_out_bits { 5002 u8 status[0x8]; 5003 u8 reserved_0[0x18]; 5004 5005 u8 syndrome[0x20]; 5006 5007 u8 enable[0x1]; 5008 u8 reserved_1[0x1f]; 5009 5010 u8 reserved_2[0x160]; 5011 5012 struct mlx5_ifc_cmd_pas_bits pas; 5013 }; 5014 5015 struct mlx5_ifc_query_dc_cnak_trace_in_bits { 5016 u8 opcode[0x10]; 5017 u8 reserved_0[0x10]; 5018 5019 u8 reserved_1[0x10]; 5020 u8 op_mod[0x10]; 5021 5022 u8 reserved_2[0x40]; 5023 }; 5024 5025 struct mlx5_ifc_query_cq_out_bits { 5026 u8 status[0x8]; 5027 u8 reserved_0[0x18]; 5028 5029 u8 syndrome[0x20]; 5030 5031 u8 reserved_1[0x40]; 5032 5033 struct mlx5_ifc_cqc_bits cq_context; 5034 5035 u8 reserved_2[0x600]; 5036 5037 u8 pas[0][0x40]; 5038 }; 5039 5040 struct mlx5_ifc_query_cq_in_bits { 5041 u8 opcode[0x10]; 5042 u8 reserved_0[0x10]; 5043 5044 u8 reserved_1[0x10]; 5045 u8 op_mod[0x10]; 5046 5047 u8 reserved_2[0x8]; 5048 u8 cqn[0x18]; 5049 5050 u8 reserved_3[0x20]; 5051 }; 5052 5053 struct mlx5_ifc_query_cong_status_out_bits { 5054 u8 status[0x8]; 5055 u8 reserved_0[0x18]; 5056 5057 u8 syndrome[0x20]; 5058 5059 u8 reserved_1[0x20]; 5060 5061 u8 enable[0x1]; 5062 u8 tag_enable[0x1]; 5063 u8 reserved_2[0x1e]; 5064 }; 5065 5066 struct mlx5_ifc_query_cong_status_in_bits { 5067 u8 opcode[0x10]; 5068 u8 reserved_0[0x10]; 5069 5070 u8 reserved_1[0x10]; 5071 u8 op_mod[0x10]; 5072 5073 u8 reserved_2[0x18]; 5074 u8 priority[0x4]; 5075 u8 cong_protocol[0x4]; 5076 5077 u8 reserved_3[0x20]; 5078 }; 5079 5080 struct mlx5_ifc_query_cong_statistics_out_bits { 5081 u8 status[0x8]; 5082 u8 reserved_0[0x18]; 5083 5084 u8 syndrome[0x20]; 5085 5086 u8 reserved_1[0x40]; 5087 5088 u8 rp_cur_flows[0x20]; 5089 5090 u8 sum_flows[0x20]; 5091 5092 u8 rp_cnp_ignored_high[0x20]; 5093 5094 u8 rp_cnp_ignored_low[0x20]; 5095 5096 u8 rp_cnp_handled_high[0x20]; 5097 5098 u8 rp_cnp_handled_low[0x20]; 5099 5100 u8 reserved_2[0x100]; 5101 5102 u8 time_stamp_high[0x20]; 5103 5104 u8 time_stamp_low[0x20]; 5105 5106 u8 accumulators_period[0x20]; 5107 5108 u8 np_ecn_marked_roce_packets_high[0x20]; 5109 5110 u8 np_ecn_marked_roce_packets_low[0x20]; 5111 5112 u8 np_cnp_sent_high[0x20]; 5113 5114 u8 np_cnp_sent_low[0x20]; 5115 5116 u8 reserved_3[0x560]; 5117 }; 5118 5119 struct mlx5_ifc_query_cong_statistics_in_bits { 5120 u8 opcode[0x10]; 5121 u8 reserved_0[0x10]; 5122 5123 u8 reserved_1[0x10]; 5124 u8 op_mod[0x10]; 5125 5126 u8 clear[0x1]; 5127 u8 reserved_2[0x1f]; 5128 5129 u8 reserved_3[0x20]; 5130 }; 5131 5132 struct mlx5_ifc_query_cong_params_out_bits { 5133 u8 status[0x8]; 5134 u8 reserved_0[0x18]; 5135 5136 u8 syndrome[0x20]; 5137 5138 u8 reserved_1[0x40]; 5139 5140 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5141 }; 5142 5143 struct mlx5_ifc_query_cong_params_in_bits { 5144 u8 opcode[0x10]; 5145 u8 reserved_0[0x10]; 5146 5147 u8 reserved_1[0x10]; 5148 u8 op_mod[0x10]; 5149 5150 u8 reserved_2[0x1c]; 5151 u8 cong_protocol[0x4]; 5152 5153 u8 reserved_3[0x20]; 5154 }; 5155 5156 struct mlx5_ifc_query_burst_size_out_bits { 5157 u8 status[0x8]; 5158 u8 reserved_0[0x18]; 5159 5160 u8 syndrome[0x20]; 5161 5162 u8 reserved_1[0x20]; 5163 5164 u8 reserved_2[0x9]; 5165 u8 device_burst_size[0x17]; 5166 }; 5167 5168 struct mlx5_ifc_query_burst_size_in_bits { 5169 u8 opcode[0x10]; 5170 u8 reserved_0[0x10]; 5171 5172 u8 reserved_1[0x10]; 5173 u8 op_mod[0x10]; 5174 5175 u8 reserved_2[0x40]; 5176 }; 5177 5178 struct mlx5_ifc_query_adapter_out_bits { 5179 u8 status[0x8]; 5180 u8 reserved_0[0x18]; 5181 5182 u8 syndrome[0x20]; 5183 5184 u8 reserved_1[0x40]; 5185 5186 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5187 }; 5188 5189 struct mlx5_ifc_query_adapter_in_bits { 5190 u8 opcode[0x10]; 5191 u8 reserved_0[0x10]; 5192 5193 u8 reserved_1[0x10]; 5194 u8 op_mod[0x10]; 5195 5196 u8 reserved_2[0x40]; 5197 }; 5198 5199 struct mlx5_ifc_qp_2rst_out_bits { 5200 u8 status[0x8]; 5201 u8 reserved_0[0x18]; 5202 5203 u8 syndrome[0x20]; 5204 5205 u8 reserved_1[0x40]; 5206 }; 5207 5208 struct mlx5_ifc_qp_2rst_in_bits { 5209 u8 opcode[0x10]; 5210 u8 reserved_0[0x10]; 5211 5212 u8 reserved_1[0x10]; 5213 u8 op_mod[0x10]; 5214 5215 u8 reserved_2[0x8]; 5216 u8 qpn[0x18]; 5217 5218 u8 reserved_3[0x20]; 5219 }; 5220 5221 struct mlx5_ifc_qp_2err_out_bits { 5222 u8 status[0x8]; 5223 u8 reserved_0[0x18]; 5224 5225 u8 syndrome[0x20]; 5226 5227 u8 reserved_1[0x40]; 5228 }; 5229 5230 struct mlx5_ifc_qp_2err_in_bits { 5231 u8 opcode[0x10]; 5232 u8 reserved_0[0x10]; 5233 5234 u8 reserved_1[0x10]; 5235 u8 op_mod[0x10]; 5236 5237 u8 reserved_2[0x8]; 5238 u8 qpn[0x18]; 5239 5240 u8 reserved_3[0x20]; 5241 }; 5242 5243 struct mlx5_ifc_para_vport_element_bits { 5244 u8 reserved_at_0[0xc]; 5245 u8 traffic_class[0x4]; 5246 u8 qos_para_vport_number[0x10]; 5247 }; 5248 5249 struct mlx5_ifc_page_fault_resume_out_bits { 5250 u8 status[0x8]; 5251 u8 reserved_0[0x18]; 5252 5253 u8 syndrome[0x20]; 5254 5255 u8 reserved_1[0x40]; 5256 }; 5257 5258 struct mlx5_ifc_page_fault_resume_in_bits { 5259 u8 opcode[0x10]; 5260 u8 reserved_0[0x10]; 5261 5262 u8 reserved_1[0x10]; 5263 u8 op_mod[0x10]; 5264 5265 u8 error[0x1]; 5266 u8 reserved_2[0x4]; 5267 u8 rdma[0x1]; 5268 u8 read_write[0x1]; 5269 u8 req_res[0x1]; 5270 u8 qpn[0x18]; 5271 5272 u8 reserved_3[0x20]; 5273 }; 5274 5275 struct mlx5_ifc_nop_out_bits { 5276 u8 status[0x8]; 5277 u8 reserved_0[0x18]; 5278 5279 u8 syndrome[0x20]; 5280 5281 u8 reserved_1[0x40]; 5282 }; 5283 5284 struct mlx5_ifc_nop_in_bits { 5285 u8 opcode[0x10]; 5286 u8 reserved_0[0x10]; 5287 5288 u8 reserved_1[0x10]; 5289 u8 op_mod[0x10]; 5290 5291 u8 reserved_2[0x40]; 5292 }; 5293 5294 struct mlx5_ifc_modify_vport_state_out_bits { 5295 u8 status[0x8]; 5296 u8 reserved_0[0x18]; 5297 5298 u8 syndrome[0x20]; 5299 5300 u8 reserved_1[0x40]; 5301 }; 5302 5303 enum { 5304 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5305 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5306 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5307 }; 5308 5309 enum { 5310 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5311 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5312 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5313 }; 5314 5315 struct mlx5_ifc_modify_vport_state_in_bits { 5316 u8 opcode[0x10]; 5317 u8 reserved_0[0x10]; 5318 5319 u8 reserved_1[0x10]; 5320 u8 op_mod[0x10]; 5321 5322 u8 other_vport[0x1]; 5323 u8 reserved_2[0xf]; 5324 u8 vport_number[0x10]; 5325 5326 u8 reserved_3[0x18]; 5327 u8 admin_state[0x4]; 5328 u8 reserved_4[0x4]; 5329 }; 5330 5331 struct mlx5_ifc_modify_tis_out_bits { 5332 u8 status[0x8]; 5333 u8 reserved_0[0x18]; 5334 5335 u8 syndrome[0x20]; 5336 5337 u8 reserved_1[0x40]; 5338 }; 5339 5340 struct mlx5_ifc_modify_tis_bitmask_bits { 5341 u8 reserved_at_0[0x20]; 5342 5343 u8 reserved_at_20[0x1d]; 5344 u8 lag_tx_port_affinity[0x1]; 5345 u8 strict_lag_tx_port_affinity[0x1]; 5346 u8 prio[0x1]; 5347 }; 5348 5349 struct mlx5_ifc_modify_tis_in_bits { 5350 u8 opcode[0x10]; 5351 u8 reserved_0[0x10]; 5352 5353 u8 reserved_1[0x10]; 5354 u8 op_mod[0x10]; 5355 5356 u8 reserved_2[0x8]; 5357 u8 tisn[0x18]; 5358 5359 u8 reserved_3[0x20]; 5360 5361 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5362 5363 u8 reserved_4[0x40]; 5364 5365 struct mlx5_ifc_tisc_bits ctx; 5366 }; 5367 5368 struct mlx5_ifc_modify_tir_out_bits { 5369 u8 status[0x8]; 5370 u8 reserved_0[0x18]; 5371 5372 u8 syndrome[0x20]; 5373 5374 u8 reserved_1[0x40]; 5375 }; 5376 5377 enum 5378 { 5379 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5380 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5381 }; 5382 5383 struct mlx5_ifc_modify_tir_in_bits { 5384 u8 opcode[0x10]; 5385 u8 reserved_0[0x10]; 5386 5387 u8 reserved_1[0x10]; 5388 u8 op_mod[0x10]; 5389 5390 u8 reserved_2[0x8]; 5391 u8 tirn[0x18]; 5392 5393 u8 reserved_3[0x20]; 5394 5395 u8 modify_bitmask[0x40]; 5396 5397 u8 reserved_4[0x40]; 5398 5399 struct mlx5_ifc_tirc_bits tir_context; 5400 }; 5401 5402 struct mlx5_ifc_modify_sq_out_bits { 5403 u8 status[0x8]; 5404 u8 reserved_0[0x18]; 5405 5406 u8 syndrome[0x20]; 5407 5408 u8 reserved_1[0x40]; 5409 }; 5410 5411 struct mlx5_ifc_modify_sq_in_bits { 5412 u8 opcode[0x10]; 5413 u8 reserved_0[0x10]; 5414 5415 u8 reserved_1[0x10]; 5416 u8 op_mod[0x10]; 5417 5418 u8 sq_state[0x4]; 5419 u8 reserved_2[0x4]; 5420 u8 sqn[0x18]; 5421 5422 u8 reserved_3[0x20]; 5423 5424 u8 modify_bitmask[0x40]; 5425 5426 u8 reserved_4[0x40]; 5427 5428 struct mlx5_ifc_sqc_bits ctx; 5429 }; 5430 5431 struct mlx5_ifc_modify_scheduling_element_out_bits { 5432 u8 status[0x8]; 5433 u8 reserved_at_8[0x18]; 5434 5435 u8 syndrome[0x20]; 5436 5437 u8 reserved_at_40[0x1c0]; 5438 }; 5439 5440 enum { 5441 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5442 }; 5443 5444 enum { 5445 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5446 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5447 }; 5448 5449 struct mlx5_ifc_modify_scheduling_element_in_bits { 5450 u8 opcode[0x10]; 5451 u8 reserved_at_10[0x10]; 5452 5453 u8 reserved_at_20[0x10]; 5454 u8 op_mod[0x10]; 5455 5456 u8 scheduling_hierarchy[0x8]; 5457 u8 reserved_at_48[0x18]; 5458 5459 u8 scheduling_element_id[0x20]; 5460 5461 u8 reserved_at_80[0x20]; 5462 5463 u8 modify_bitmask[0x20]; 5464 5465 u8 reserved_at_c0[0x40]; 5466 5467 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5468 5469 u8 reserved_at_300[0x100]; 5470 }; 5471 5472 struct mlx5_ifc_modify_rqt_out_bits { 5473 u8 status[0x8]; 5474 u8 reserved_0[0x18]; 5475 5476 u8 syndrome[0x20]; 5477 5478 u8 reserved_1[0x40]; 5479 }; 5480 5481 struct mlx5_ifc_modify_rqt_in_bits { 5482 u8 opcode[0x10]; 5483 u8 reserved_0[0x10]; 5484 5485 u8 reserved_1[0x10]; 5486 u8 op_mod[0x10]; 5487 5488 u8 reserved_2[0x8]; 5489 u8 rqtn[0x18]; 5490 5491 u8 reserved_3[0x20]; 5492 5493 u8 modify_bitmask[0x40]; 5494 5495 u8 reserved_4[0x40]; 5496 5497 struct mlx5_ifc_rqtc_bits ctx; 5498 }; 5499 5500 struct mlx5_ifc_modify_rq_out_bits { 5501 u8 status[0x8]; 5502 u8 reserved_0[0x18]; 5503 5504 u8 syndrome[0x20]; 5505 5506 u8 reserved_1[0x40]; 5507 }; 5508 5509 enum { 5510 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5511 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5512 }; 5513 5514 struct mlx5_ifc_modify_rq_in_bits { 5515 u8 opcode[0x10]; 5516 u8 reserved_0[0x10]; 5517 5518 u8 reserved_1[0x10]; 5519 u8 op_mod[0x10]; 5520 5521 u8 rq_state[0x4]; 5522 u8 reserved_2[0x4]; 5523 u8 rqn[0x18]; 5524 5525 u8 reserved_3[0x20]; 5526 5527 u8 modify_bitmask[0x40]; 5528 5529 u8 reserved_4[0x40]; 5530 5531 struct mlx5_ifc_rqc_bits ctx; 5532 }; 5533 5534 struct mlx5_ifc_modify_rmp_out_bits { 5535 u8 status[0x8]; 5536 u8 reserved_0[0x18]; 5537 5538 u8 syndrome[0x20]; 5539 5540 u8 reserved_1[0x40]; 5541 }; 5542 5543 struct mlx5_ifc_rmp_bitmask_bits { 5544 u8 reserved[0x20]; 5545 5546 u8 reserved1[0x1f]; 5547 u8 lwm[0x1]; 5548 }; 5549 5550 struct mlx5_ifc_modify_rmp_in_bits { 5551 u8 opcode[0x10]; 5552 u8 reserved_0[0x10]; 5553 5554 u8 reserved_1[0x10]; 5555 u8 op_mod[0x10]; 5556 5557 u8 rmp_state[0x4]; 5558 u8 reserved_2[0x4]; 5559 u8 rmpn[0x18]; 5560 5561 u8 reserved_3[0x20]; 5562 5563 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5564 5565 u8 reserved_4[0x40]; 5566 5567 struct mlx5_ifc_rmpc_bits ctx; 5568 }; 5569 5570 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5571 u8 status[0x8]; 5572 u8 reserved_0[0x18]; 5573 5574 u8 syndrome[0x20]; 5575 5576 u8 reserved_1[0x40]; 5577 }; 5578 5579 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5580 u8 reserved_0[0x14]; 5581 u8 disable_uc_local_lb[0x1]; 5582 u8 disable_mc_local_lb[0x1]; 5583 u8 node_guid[0x1]; 5584 u8 port_guid[0x1]; 5585 u8 min_wqe_inline_mode[0x1]; 5586 u8 mtu[0x1]; 5587 u8 change_event[0x1]; 5588 u8 promisc[0x1]; 5589 u8 permanent_address[0x1]; 5590 u8 addresses_list[0x1]; 5591 u8 roce_en[0x1]; 5592 u8 reserved_1[0x1]; 5593 }; 5594 5595 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5596 u8 opcode[0x10]; 5597 u8 reserved_0[0x10]; 5598 5599 u8 reserved_1[0x10]; 5600 u8 op_mod[0x10]; 5601 5602 u8 other_vport[0x1]; 5603 u8 reserved_2[0xf]; 5604 u8 vport_number[0x10]; 5605 5606 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5607 5608 u8 reserved_3[0x780]; 5609 5610 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5611 }; 5612 5613 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5614 u8 status[0x8]; 5615 u8 reserved_0[0x18]; 5616 5617 u8 syndrome[0x20]; 5618 5619 u8 reserved_1[0x40]; 5620 }; 5621 5622 struct mlx5_ifc_grh_bits { 5623 u8 ip_version[4]; 5624 u8 traffic_class[8]; 5625 u8 flow_label[20]; 5626 u8 payload_length[16]; 5627 u8 next_header[8]; 5628 u8 hop_limit[8]; 5629 u8 sgid[128]; 5630 u8 dgid[128]; 5631 }; 5632 5633 struct mlx5_ifc_bth_bits { 5634 u8 opcode[8]; 5635 u8 se[1]; 5636 u8 migreq[1]; 5637 u8 pad_count[2]; 5638 u8 tver[4]; 5639 u8 p_key[16]; 5640 u8 reserved8[8]; 5641 u8 dest_qp[24]; 5642 u8 ack_req[1]; 5643 u8 reserved7[7]; 5644 u8 psn[24]; 5645 }; 5646 5647 struct mlx5_ifc_aeth_bits { 5648 u8 syndrome[8]; 5649 u8 msn[24]; 5650 }; 5651 5652 struct mlx5_ifc_dceth_bits { 5653 u8 reserved0[8]; 5654 u8 session_id[24]; 5655 u8 reserved1[8]; 5656 u8 dci_dct[24]; 5657 }; 5658 5659 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5660 u8 opcode[0x10]; 5661 u8 reserved_0[0x10]; 5662 5663 u8 reserved_1[0x10]; 5664 u8 op_mod[0x10]; 5665 5666 u8 other_vport[0x1]; 5667 u8 reserved_2[0xb]; 5668 u8 port_num[0x4]; 5669 u8 vport_number[0x10]; 5670 5671 u8 reserved_3[0x20]; 5672 5673 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5674 }; 5675 5676 struct mlx5_ifc_modify_flow_table_out_bits { 5677 u8 status[0x8]; 5678 u8 reserved_at_8[0x18]; 5679 5680 u8 syndrome[0x20]; 5681 5682 u8 reserved_at_40[0x40]; 5683 }; 5684 5685 enum { 5686 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 5687 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 5688 }; 5689 5690 struct mlx5_ifc_modify_flow_table_in_bits { 5691 u8 opcode[0x10]; 5692 u8 reserved_at_10[0x10]; 5693 5694 u8 reserved_at_20[0x10]; 5695 u8 op_mod[0x10]; 5696 5697 u8 other_vport[0x1]; 5698 u8 reserved_at_41[0xf]; 5699 u8 vport_number[0x10]; 5700 5701 u8 reserved_at_60[0x10]; 5702 u8 modify_field_select[0x10]; 5703 5704 u8 table_type[0x8]; 5705 u8 reserved_at_88[0x18]; 5706 5707 u8 reserved_at_a0[0x8]; 5708 u8 table_id[0x18]; 5709 5710 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5711 }; 5712 5713 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5714 u8 status[0x8]; 5715 u8 reserved_0[0x18]; 5716 5717 u8 syndrome[0x20]; 5718 5719 u8 reserved_1[0x40]; 5720 }; 5721 5722 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5723 u8 reserved[0x1c]; 5724 u8 vport_cvlan_insert[0x1]; 5725 u8 vport_svlan_insert[0x1]; 5726 u8 vport_cvlan_strip[0x1]; 5727 u8 vport_svlan_strip[0x1]; 5728 }; 5729 5730 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5731 u8 opcode[0x10]; 5732 u8 reserved_0[0x10]; 5733 5734 u8 reserved_1[0x10]; 5735 u8 op_mod[0x10]; 5736 5737 u8 other_vport[0x1]; 5738 u8 reserved_2[0xf]; 5739 u8 vport_number[0x10]; 5740 5741 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5742 5743 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5744 }; 5745 5746 struct mlx5_ifc_modify_cq_out_bits { 5747 u8 status[0x8]; 5748 u8 reserved_0[0x18]; 5749 5750 u8 syndrome[0x20]; 5751 5752 u8 reserved_1[0x40]; 5753 }; 5754 5755 enum { 5756 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5757 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5758 }; 5759 5760 struct mlx5_ifc_modify_cq_in_bits { 5761 u8 opcode[0x10]; 5762 u8 reserved_0[0x10]; 5763 5764 u8 reserved_1[0x10]; 5765 u8 op_mod[0x10]; 5766 5767 u8 reserved_2[0x8]; 5768 u8 cqn[0x18]; 5769 5770 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5771 5772 struct mlx5_ifc_cqc_bits cq_context; 5773 5774 u8 reserved_3[0x600]; 5775 5776 u8 pas[0][0x40]; 5777 }; 5778 5779 struct mlx5_ifc_modify_cong_status_out_bits { 5780 u8 status[0x8]; 5781 u8 reserved_0[0x18]; 5782 5783 u8 syndrome[0x20]; 5784 5785 u8 reserved_1[0x40]; 5786 }; 5787 5788 struct mlx5_ifc_modify_cong_status_in_bits { 5789 u8 opcode[0x10]; 5790 u8 reserved_0[0x10]; 5791 5792 u8 reserved_1[0x10]; 5793 u8 op_mod[0x10]; 5794 5795 u8 reserved_2[0x18]; 5796 u8 priority[0x4]; 5797 u8 cong_protocol[0x4]; 5798 5799 u8 enable[0x1]; 5800 u8 tag_enable[0x1]; 5801 u8 reserved_3[0x1e]; 5802 }; 5803 5804 struct mlx5_ifc_modify_cong_params_out_bits { 5805 u8 status[0x8]; 5806 u8 reserved_0[0x18]; 5807 5808 u8 syndrome[0x20]; 5809 5810 u8 reserved_1[0x40]; 5811 }; 5812 5813 struct mlx5_ifc_modify_cong_params_in_bits { 5814 u8 opcode[0x10]; 5815 u8 reserved_0[0x10]; 5816 5817 u8 reserved_1[0x10]; 5818 u8 op_mod[0x10]; 5819 5820 u8 reserved_2[0x1c]; 5821 u8 cong_protocol[0x4]; 5822 5823 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5824 5825 u8 reserved_3[0x80]; 5826 5827 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5828 }; 5829 5830 struct mlx5_ifc_manage_pages_out_bits { 5831 u8 status[0x8]; 5832 u8 reserved_0[0x18]; 5833 5834 u8 syndrome[0x20]; 5835 5836 u8 output_num_entries[0x20]; 5837 5838 u8 reserved_1[0x20]; 5839 5840 u8 pas[0][0x40]; 5841 }; 5842 5843 enum { 5844 MLX5_PAGES_CANT_GIVE = 0x0, 5845 MLX5_PAGES_GIVE = 0x1, 5846 MLX5_PAGES_TAKE = 0x2, 5847 }; 5848 5849 struct mlx5_ifc_manage_pages_in_bits { 5850 u8 opcode[0x10]; 5851 u8 reserved_0[0x10]; 5852 5853 u8 reserved_1[0x10]; 5854 u8 op_mod[0x10]; 5855 5856 u8 reserved_2[0x10]; 5857 u8 function_id[0x10]; 5858 5859 u8 input_num_entries[0x20]; 5860 5861 u8 pas[0][0x40]; 5862 }; 5863 5864 struct mlx5_ifc_mad_ifc_out_bits { 5865 u8 status[0x8]; 5866 u8 reserved_0[0x18]; 5867 5868 u8 syndrome[0x20]; 5869 5870 u8 reserved_1[0x40]; 5871 5872 u8 response_mad_packet[256][0x8]; 5873 }; 5874 5875 struct mlx5_ifc_mad_ifc_in_bits { 5876 u8 opcode[0x10]; 5877 u8 reserved_0[0x10]; 5878 5879 u8 reserved_1[0x10]; 5880 u8 op_mod[0x10]; 5881 5882 u8 remote_lid[0x10]; 5883 u8 reserved_2[0x8]; 5884 u8 port[0x8]; 5885 5886 u8 reserved_3[0x20]; 5887 5888 u8 mad[256][0x8]; 5889 }; 5890 5891 struct mlx5_ifc_init_hca_out_bits { 5892 u8 status[0x8]; 5893 u8 reserved_0[0x18]; 5894 5895 u8 syndrome[0x20]; 5896 5897 u8 reserved_1[0x40]; 5898 }; 5899 5900 enum { 5901 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 5902 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 5903 }; 5904 5905 struct mlx5_ifc_init_hca_in_bits { 5906 u8 opcode[0x10]; 5907 u8 reserved_0[0x10]; 5908 5909 u8 reserved_1[0x10]; 5910 u8 op_mod[0x10]; 5911 5912 u8 reserved_2[0x40]; 5913 }; 5914 5915 struct mlx5_ifc_init2rtr_qp_out_bits { 5916 u8 status[0x8]; 5917 u8 reserved_0[0x18]; 5918 5919 u8 syndrome[0x20]; 5920 5921 u8 reserved_1[0x40]; 5922 }; 5923 5924 struct mlx5_ifc_init2rtr_qp_in_bits { 5925 u8 opcode[0x10]; 5926 u8 reserved_0[0x10]; 5927 5928 u8 reserved_1[0x10]; 5929 u8 op_mod[0x10]; 5930 5931 u8 reserved_2[0x8]; 5932 u8 qpn[0x18]; 5933 5934 u8 reserved_3[0x20]; 5935 5936 u8 opt_param_mask[0x20]; 5937 5938 u8 reserved_4[0x20]; 5939 5940 struct mlx5_ifc_qpc_bits qpc; 5941 5942 u8 reserved_5[0x80]; 5943 }; 5944 5945 struct mlx5_ifc_init2init_qp_out_bits { 5946 u8 status[0x8]; 5947 u8 reserved_0[0x18]; 5948 5949 u8 syndrome[0x20]; 5950 5951 u8 reserved_1[0x40]; 5952 }; 5953 5954 struct mlx5_ifc_init2init_qp_in_bits { 5955 u8 opcode[0x10]; 5956 u8 reserved_0[0x10]; 5957 5958 u8 reserved_1[0x10]; 5959 u8 op_mod[0x10]; 5960 5961 u8 reserved_2[0x8]; 5962 u8 qpn[0x18]; 5963 5964 u8 reserved_3[0x20]; 5965 5966 u8 opt_param_mask[0x20]; 5967 5968 u8 reserved_4[0x20]; 5969 5970 struct mlx5_ifc_qpc_bits qpc; 5971 5972 u8 reserved_5[0x80]; 5973 }; 5974 5975 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5976 u8 status[0x8]; 5977 u8 reserved_0[0x18]; 5978 5979 u8 syndrome[0x20]; 5980 5981 u8 reserved_1[0x40]; 5982 5983 u8 packet_headers_log[128][0x8]; 5984 5985 u8 packet_syndrome[64][0x8]; 5986 }; 5987 5988 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5989 u8 opcode[0x10]; 5990 u8 reserved_0[0x10]; 5991 5992 u8 reserved_1[0x10]; 5993 u8 op_mod[0x10]; 5994 5995 u8 reserved_2[0x40]; 5996 }; 5997 5998 struct mlx5_ifc_encryption_key_obj_bits { 5999 u8 modify_field_select[0x40]; 6000 6001 u8 reserved_at_40[0x14]; 6002 u8 key_size[0x4]; 6003 u8 reserved_at_58[0x4]; 6004 u8 key_type[0x4]; 6005 6006 u8 reserved_at_60[0x8]; 6007 u8 pd[0x18]; 6008 6009 u8 reserved_at_80[0x180]; 6010 6011 u8 key[8][0x20]; 6012 6013 u8 reserved_at_300[0x500]; 6014 }; 6015 6016 struct mlx5_ifc_gen_eqe_in_bits { 6017 u8 opcode[0x10]; 6018 u8 reserved_0[0x10]; 6019 6020 u8 reserved_1[0x10]; 6021 u8 op_mod[0x10]; 6022 6023 u8 reserved_2[0x18]; 6024 u8 eq_number[0x8]; 6025 6026 u8 reserved_3[0x20]; 6027 6028 u8 eqe[64][0x8]; 6029 }; 6030 6031 struct mlx5_ifc_gen_eq_out_bits { 6032 u8 status[0x8]; 6033 u8 reserved_0[0x18]; 6034 6035 u8 syndrome[0x20]; 6036 6037 u8 reserved_1[0x40]; 6038 }; 6039 6040 struct mlx5_ifc_enable_hca_out_bits { 6041 u8 status[0x8]; 6042 u8 reserved_0[0x18]; 6043 6044 u8 syndrome[0x20]; 6045 6046 u8 reserved_1[0x20]; 6047 }; 6048 6049 struct mlx5_ifc_enable_hca_in_bits { 6050 u8 opcode[0x10]; 6051 u8 reserved_0[0x10]; 6052 6053 u8 reserved_1[0x10]; 6054 u8 op_mod[0x10]; 6055 6056 u8 reserved_2[0x10]; 6057 u8 function_id[0x10]; 6058 6059 u8 reserved_3[0x20]; 6060 }; 6061 6062 struct mlx5_ifc_drain_dct_out_bits { 6063 u8 status[0x8]; 6064 u8 reserved_0[0x18]; 6065 6066 u8 syndrome[0x20]; 6067 6068 u8 reserved_1[0x40]; 6069 }; 6070 6071 struct mlx5_ifc_drain_dct_in_bits { 6072 u8 opcode[0x10]; 6073 u8 reserved_0[0x10]; 6074 6075 u8 reserved_1[0x10]; 6076 u8 op_mod[0x10]; 6077 6078 u8 reserved_2[0x8]; 6079 u8 dctn[0x18]; 6080 6081 u8 reserved_3[0x20]; 6082 }; 6083 6084 struct mlx5_ifc_disable_hca_out_bits { 6085 u8 status[0x8]; 6086 u8 reserved_0[0x18]; 6087 6088 u8 syndrome[0x20]; 6089 6090 u8 reserved_1[0x20]; 6091 }; 6092 6093 struct mlx5_ifc_disable_hca_in_bits { 6094 u8 opcode[0x10]; 6095 u8 reserved_0[0x10]; 6096 6097 u8 reserved_1[0x10]; 6098 u8 op_mod[0x10]; 6099 6100 u8 reserved_2[0x10]; 6101 u8 function_id[0x10]; 6102 6103 u8 reserved_3[0x20]; 6104 }; 6105 6106 struct mlx5_ifc_detach_from_mcg_out_bits { 6107 u8 status[0x8]; 6108 u8 reserved_0[0x18]; 6109 6110 u8 syndrome[0x20]; 6111 6112 u8 reserved_1[0x40]; 6113 }; 6114 6115 struct mlx5_ifc_detach_from_mcg_in_bits { 6116 u8 opcode[0x10]; 6117 u8 reserved_0[0x10]; 6118 6119 u8 reserved_1[0x10]; 6120 u8 op_mod[0x10]; 6121 6122 u8 reserved_2[0x8]; 6123 u8 qpn[0x18]; 6124 6125 u8 reserved_3[0x20]; 6126 6127 u8 multicast_gid[16][0x8]; 6128 }; 6129 6130 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6131 u8 status[0x8]; 6132 u8 reserved_0[0x18]; 6133 6134 u8 syndrome[0x20]; 6135 6136 u8 reserved_1[0x40]; 6137 }; 6138 6139 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6140 u8 opcode[0x10]; 6141 u8 reserved_0[0x10]; 6142 6143 u8 reserved_1[0x10]; 6144 u8 op_mod[0x10]; 6145 6146 u8 reserved_2[0x8]; 6147 u8 xrc_srqn[0x18]; 6148 6149 u8 reserved_3[0x20]; 6150 }; 6151 6152 struct mlx5_ifc_destroy_tis_out_bits { 6153 u8 status[0x8]; 6154 u8 reserved_0[0x18]; 6155 6156 u8 syndrome[0x20]; 6157 6158 u8 reserved_1[0x40]; 6159 }; 6160 6161 struct mlx5_ifc_destroy_tis_in_bits { 6162 u8 opcode[0x10]; 6163 u8 reserved_0[0x10]; 6164 6165 u8 reserved_1[0x10]; 6166 u8 op_mod[0x10]; 6167 6168 u8 reserved_2[0x8]; 6169 u8 tisn[0x18]; 6170 6171 u8 reserved_3[0x20]; 6172 }; 6173 6174 struct mlx5_ifc_destroy_tir_out_bits { 6175 u8 status[0x8]; 6176 u8 reserved_0[0x18]; 6177 6178 u8 syndrome[0x20]; 6179 6180 u8 reserved_1[0x40]; 6181 }; 6182 6183 struct mlx5_ifc_destroy_tir_in_bits { 6184 u8 opcode[0x10]; 6185 u8 reserved_0[0x10]; 6186 6187 u8 reserved_1[0x10]; 6188 u8 op_mod[0x10]; 6189 6190 u8 reserved_2[0x8]; 6191 u8 tirn[0x18]; 6192 6193 u8 reserved_3[0x20]; 6194 }; 6195 6196 struct mlx5_ifc_destroy_srq_out_bits { 6197 u8 status[0x8]; 6198 u8 reserved_0[0x18]; 6199 6200 u8 syndrome[0x20]; 6201 6202 u8 reserved_1[0x40]; 6203 }; 6204 6205 struct mlx5_ifc_destroy_srq_in_bits { 6206 u8 opcode[0x10]; 6207 u8 reserved_0[0x10]; 6208 6209 u8 reserved_1[0x10]; 6210 u8 op_mod[0x10]; 6211 6212 u8 reserved_2[0x8]; 6213 u8 srqn[0x18]; 6214 6215 u8 reserved_3[0x20]; 6216 }; 6217 6218 struct mlx5_ifc_destroy_sq_out_bits { 6219 u8 status[0x8]; 6220 u8 reserved_0[0x18]; 6221 6222 u8 syndrome[0x20]; 6223 6224 u8 reserved_1[0x40]; 6225 }; 6226 6227 struct mlx5_ifc_destroy_sq_in_bits { 6228 u8 opcode[0x10]; 6229 u8 reserved_0[0x10]; 6230 6231 u8 reserved_1[0x10]; 6232 u8 op_mod[0x10]; 6233 6234 u8 reserved_2[0x8]; 6235 u8 sqn[0x18]; 6236 6237 u8 reserved_3[0x20]; 6238 }; 6239 6240 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6241 u8 status[0x8]; 6242 u8 reserved_at_8[0x18]; 6243 6244 u8 syndrome[0x20]; 6245 6246 u8 reserved_at_40[0x1c0]; 6247 }; 6248 6249 enum { 6250 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6251 }; 6252 6253 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6254 u8 opcode[0x10]; 6255 u8 reserved_at_10[0x10]; 6256 6257 u8 reserved_at_20[0x10]; 6258 u8 op_mod[0x10]; 6259 6260 u8 scheduling_hierarchy[0x8]; 6261 u8 reserved_at_48[0x18]; 6262 6263 u8 scheduling_element_id[0x20]; 6264 6265 u8 reserved_at_80[0x180]; 6266 }; 6267 6268 struct mlx5_ifc_destroy_rqt_out_bits { 6269 u8 status[0x8]; 6270 u8 reserved_0[0x18]; 6271 6272 u8 syndrome[0x20]; 6273 6274 u8 reserved_1[0x40]; 6275 }; 6276 6277 struct mlx5_ifc_destroy_rqt_in_bits { 6278 u8 opcode[0x10]; 6279 u8 reserved_0[0x10]; 6280 6281 u8 reserved_1[0x10]; 6282 u8 op_mod[0x10]; 6283 6284 u8 reserved_2[0x8]; 6285 u8 rqtn[0x18]; 6286 6287 u8 reserved_3[0x20]; 6288 }; 6289 6290 struct mlx5_ifc_destroy_rq_out_bits { 6291 u8 status[0x8]; 6292 u8 reserved_0[0x18]; 6293 6294 u8 syndrome[0x20]; 6295 6296 u8 reserved_1[0x40]; 6297 }; 6298 6299 struct mlx5_ifc_destroy_rq_in_bits { 6300 u8 opcode[0x10]; 6301 u8 reserved_0[0x10]; 6302 6303 u8 reserved_1[0x10]; 6304 u8 op_mod[0x10]; 6305 6306 u8 reserved_2[0x8]; 6307 u8 rqn[0x18]; 6308 6309 u8 reserved_3[0x20]; 6310 }; 6311 6312 struct mlx5_ifc_destroy_rmp_out_bits { 6313 u8 status[0x8]; 6314 u8 reserved_0[0x18]; 6315 6316 u8 syndrome[0x20]; 6317 6318 u8 reserved_1[0x40]; 6319 }; 6320 6321 struct mlx5_ifc_destroy_rmp_in_bits { 6322 u8 opcode[0x10]; 6323 u8 reserved_0[0x10]; 6324 6325 u8 reserved_1[0x10]; 6326 u8 op_mod[0x10]; 6327 6328 u8 reserved_2[0x8]; 6329 u8 rmpn[0x18]; 6330 6331 u8 reserved_3[0x20]; 6332 }; 6333 6334 struct mlx5_ifc_destroy_qp_out_bits { 6335 u8 status[0x8]; 6336 u8 reserved_0[0x18]; 6337 6338 u8 syndrome[0x20]; 6339 6340 u8 reserved_1[0x40]; 6341 }; 6342 6343 struct mlx5_ifc_destroy_qp_in_bits { 6344 u8 opcode[0x10]; 6345 u8 reserved_0[0x10]; 6346 6347 u8 reserved_1[0x10]; 6348 u8 op_mod[0x10]; 6349 6350 u8 reserved_2[0x8]; 6351 u8 qpn[0x18]; 6352 6353 u8 reserved_3[0x20]; 6354 }; 6355 6356 struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6357 u8 status[0x8]; 6358 u8 reserved_at_8[0x18]; 6359 6360 u8 syndrome[0x20]; 6361 6362 u8 reserved_at_40[0x1c0]; 6363 }; 6364 6365 struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6366 u8 opcode[0x10]; 6367 u8 reserved_at_10[0x10]; 6368 6369 u8 reserved_at_20[0x10]; 6370 u8 op_mod[0x10]; 6371 6372 u8 reserved_at_40[0x20]; 6373 6374 u8 reserved_at_60[0x10]; 6375 u8 qos_para_vport_number[0x10]; 6376 6377 u8 reserved_at_80[0x180]; 6378 }; 6379 6380 struct mlx5_ifc_destroy_psv_out_bits { 6381 u8 status[0x8]; 6382 u8 reserved_0[0x18]; 6383 6384 u8 syndrome[0x20]; 6385 6386 u8 reserved_1[0x40]; 6387 }; 6388 6389 struct mlx5_ifc_destroy_psv_in_bits { 6390 u8 opcode[0x10]; 6391 u8 reserved_0[0x10]; 6392 6393 u8 reserved_1[0x10]; 6394 u8 op_mod[0x10]; 6395 6396 u8 reserved_2[0x8]; 6397 u8 psvn[0x18]; 6398 6399 u8 reserved_3[0x20]; 6400 }; 6401 6402 struct mlx5_ifc_destroy_mkey_out_bits { 6403 u8 status[0x8]; 6404 u8 reserved_0[0x18]; 6405 6406 u8 syndrome[0x20]; 6407 6408 u8 reserved_1[0x40]; 6409 }; 6410 6411 struct mlx5_ifc_destroy_mkey_in_bits { 6412 u8 opcode[0x10]; 6413 u8 reserved_0[0x10]; 6414 6415 u8 reserved_1[0x10]; 6416 u8 op_mod[0x10]; 6417 6418 u8 reserved_2[0x8]; 6419 u8 mkey_index[0x18]; 6420 6421 u8 reserved_3[0x20]; 6422 }; 6423 6424 struct mlx5_ifc_destroy_flow_table_out_bits { 6425 u8 status[0x8]; 6426 u8 reserved_0[0x18]; 6427 6428 u8 syndrome[0x20]; 6429 6430 u8 reserved_1[0x40]; 6431 }; 6432 6433 struct mlx5_ifc_destroy_flow_table_in_bits { 6434 u8 opcode[0x10]; 6435 u8 reserved_0[0x10]; 6436 6437 u8 reserved_1[0x10]; 6438 u8 op_mod[0x10]; 6439 6440 u8 other_vport[0x1]; 6441 u8 reserved_2[0xf]; 6442 u8 vport_number[0x10]; 6443 6444 u8 reserved_3[0x20]; 6445 6446 u8 table_type[0x8]; 6447 u8 reserved_4[0x18]; 6448 6449 u8 reserved_5[0x8]; 6450 u8 table_id[0x18]; 6451 6452 u8 reserved_6[0x140]; 6453 }; 6454 6455 struct mlx5_ifc_destroy_flow_group_out_bits { 6456 u8 status[0x8]; 6457 u8 reserved_0[0x18]; 6458 6459 u8 syndrome[0x20]; 6460 6461 u8 reserved_1[0x40]; 6462 }; 6463 6464 struct mlx5_ifc_destroy_flow_group_in_bits { 6465 u8 opcode[0x10]; 6466 u8 reserved_0[0x10]; 6467 6468 u8 reserved_1[0x10]; 6469 u8 op_mod[0x10]; 6470 6471 u8 other_vport[0x1]; 6472 u8 reserved_2[0xf]; 6473 u8 vport_number[0x10]; 6474 6475 u8 reserved_3[0x20]; 6476 6477 u8 table_type[0x8]; 6478 u8 reserved_4[0x18]; 6479 6480 u8 reserved_5[0x8]; 6481 u8 table_id[0x18]; 6482 6483 u8 group_id[0x20]; 6484 6485 u8 reserved_6[0x120]; 6486 }; 6487 6488 struct mlx5_ifc_destroy_encryption_key_out_bits { 6489 u8 status[0x8]; 6490 u8 reserved_at_8[0x18]; 6491 6492 u8 syndrome[0x20]; 6493 6494 u8 reserved_at_40[0x40]; 6495 }; 6496 6497 struct mlx5_ifc_destroy_encryption_key_in_bits { 6498 u8 opcode[0x10]; 6499 u8 reserved_at_10[0x10]; 6500 6501 u8 reserved_at_20[0x10]; 6502 u8 obj_type[0x10]; 6503 6504 u8 obj_id[0x20]; 6505 6506 u8 reserved_at_60[0x20]; 6507 }; 6508 6509 struct mlx5_ifc_destroy_eq_out_bits { 6510 u8 status[0x8]; 6511 u8 reserved_0[0x18]; 6512 6513 u8 syndrome[0x20]; 6514 6515 u8 reserved_1[0x40]; 6516 }; 6517 6518 struct mlx5_ifc_destroy_eq_in_bits { 6519 u8 opcode[0x10]; 6520 u8 reserved_0[0x10]; 6521 6522 u8 reserved_1[0x10]; 6523 u8 op_mod[0x10]; 6524 6525 u8 reserved_2[0x18]; 6526 u8 eq_number[0x8]; 6527 6528 u8 reserved_3[0x20]; 6529 }; 6530 6531 struct mlx5_ifc_destroy_dct_out_bits { 6532 u8 status[0x8]; 6533 u8 reserved_0[0x18]; 6534 6535 u8 syndrome[0x20]; 6536 6537 u8 reserved_1[0x40]; 6538 }; 6539 6540 struct mlx5_ifc_destroy_dct_in_bits { 6541 u8 opcode[0x10]; 6542 u8 reserved_0[0x10]; 6543 6544 u8 reserved_1[0x10]; 6545 u8 op_mod[0x10]; 6546 6547 u8 reserved_2[0x8]; 6548 u8 dctn[0x18]; 6549 6550 u8 reserved_3[0x20]; 6551 }; 6552 6553 struct mlx5_ifc_destroy_cq_out_bits { 6554 u8 status[0x8]; 6555 u8 reserved_0[0x18]; 6556 6557 u8 syndrome[0x20]; 6558 6559 u8 reserved_1[0x40]; 6560 }; 6561 6562 struct mlx5_ifc_destroy_cq_in_bits { 6563 u8 opcode[0x10]; 6564 u8 reserved_0[0x10]; 6565 6566 u8 reserved_1[0x10]; 6567 u8 op_mod[0x10]; 6568 6569 u8 reserved_2[0x8]; 6570 u8 cqn[0x18]; 6571 6572 u8 reserved_3[0x20]; 6573 }; 6574 6575 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6576 u8 status[0x8]; 6577 u8 reserved_0[0x18]; 6578 6579 u8 syndrome[0x20]; 6580 6581 u8 reserved_1[0x40]; 6582 }; 6583 6584 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6585 u8 opcode[0x10]; 6586 u8 reserved_0[0x10]; 6587 6588 u8 reserved_1[0x10]; 6589 u8 op_mod[0x10]; 6590 6591 u8 reserved_2[0x20]; 6592 6593 u8 reserved_3[0x10]; 6594 u8 vxlan_udp_port[0x10]; 6595 }; 6596 6597 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6598 u8 status[0x8]; 6599 u8 reserved_0[0x18]; 6600 6601 u8 syndrome[0x20]; 6602 6603 u8 reserved_1[0x40]; 6604 }; 6605 6606 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6607 u8 opcode[0x10]; 6608 u8 reserved_0[0x10]; 6609 6610 u8 reserved_1[0x10]; 6611 u8 op_mod[0x10]; 6612 6613 u8 reserved_2[0x60]; 6614 6615 u8 reserved_3[0x8]; 6616 u8 table_index[0x18]; 6617 6618 u8 reserved_4[0x140]; 6619 }; 6620 6621 struct mlx5_ifc_delete_fte_out_bits { 6622 u8 status[0x8]; 6623 u8 reserved_0[0x18]; 6624 6625 u8 syndrome[0x20]; 6626 6627 u8 reserved_1[0x40]; 6628 }; 6629 6630 struct mlx5_ifc_delete_fte_in_bits { 6631 u8 opcode[0x10]; 6632 u8 reserved_0[0x10]; 6633 6634 u8 reserved_1[0x10]; 6635 u8 op_mod[0x10]; 6636 6637 u8 other_vport[0x1]; 6638 u8 reserved_2[0xf]; 6639 u8 vport_number[0x10]; 6640 6641 u8 reserved_3[0x20]; 6642 6643 u8 table_type[0x8]; 6644 u8 reserved_4[0x18]; 6645 6646 u8 reserved_5[0x8]; 6647 u8 table_id[0x18]; 6648 6649 u8 reserved_6[0x40]; 6650 6651 u8 flow_index[0x20]; 6652 6653 u8 reserved_7[0xe0]; 6654 }; 6655 6656 struct mlx5_ifc_dealloc_xrcd_out_bits { 6657 u8 status[0x8]; 6658 u8 reserved_0[0x18]; 6659 6660 u8 syndrome[0x20]; 6661 6662 u8 reserved_1[0x40]; 6663 }; 6664 6665 struct mlx5_ifc_dealloc_xrcd_in_bits { 6666 u8 opcode[0x10]; 6667 u8 reserved_0[0x10]; 6668 6669 u8 reserved_1[0x10]; 6670 u8 op_mod[0x10]; 6671 6672 u8 reserved_2[0x8]; 6673 u8 xrcd[0x18]; 6674 6675 u8 reserved_3[0x20]; 6676 }; 6677 6678 struct mlx5_ifc_dealloc_uar_out_bits { 6679 u8 status[0x8]; 6680 u8 reserved_0[0x18]; 6681 6682 u8 syndrome[0x20]; 6683 6684 u8 reserved_1[0x40]; 6685 }; 6686 6687 struct mlx5_ifc_dealloc_uar_in_bits { 6688 u8 opcode[0x10]; 6689 u8 reserved_0[0x10]; 6690 6691 u8 reserved_1[0x10]; 6692 u8 op_mod[0x10]; 6693 6694 u8 reserved_2[0x8]; 6695 u8 uar[0x18]; 6696 6697 u8 reserved_3[0x20]; 6698 }; 6699 6700 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6701 u8 status[0x8]; 6702 u8 reserved_0[0x18]; 6703 6704 u8 syndrome[0x20]; 6705 6706 u8 reserved_1[0x40]; 6707 }; 6708 6709 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6710 u8 opcode[0x10]; 6711 u8 reserved_0[0x10]; 6712 6713 u8 reserved_1[0x10]; 6714 u8 op_mod[0x10]; 6715 6716 u8 reserved_2[0x8]; 6717 u8 transport_domain[0x18]; 6718 6719 u8 reserved_3[0x20]; 6720 }; 6721 6722 struct mlx5_ifc_dealloc_q_counter_out_bits { 6723 u8 status[0x8]; 6724 u8 reserved_0[0x18]; 6725 6726 u8 syndrome[0x20]; 6727 6728 u8 reserved_1[0x40]; 6729 }; 6730 6731 struct mlx5_ifc_counter_id_bits { 6732 u8 reserved[0x10]; 6733 u8 counter_id[0x10]; 6734 }; 6735 6736 struct mlx5_ifc_diagnostic_params_context_bits { 6737 u8 num_of_counters[0x10]; 6738 u8 reserved_2[0x8]; 6739 u8 log_num_of_samples[0x8]; 6740 6741 u8 single[0x1]; 6742 u8 repetitive[0x1]; 6743 u8 sync[0x1]; 6744 u8 clear[0x1]; 6745 u8 on_demand[0x1]; 6746 u8 enable[0x1]; 6747 u8 reserved_3[0x12]; 6748 u8 log_sample_period[0x8]; 6749 6750 u8 reserved_4[0x80]; 6751 6752 struct mlx5_ifc_counter_id_bits counter_id[0]; 6753 }; 6754 6755 struct mlx5_ifc_set_diagnostic_params_in_bits { 6756 u8 opcode[0x10]; 6757 u8 reserved_0[0x10]; 6758 6759 u8 reserved_1[0x10]; 6760 u8 op_mod[0x10]; 6761 6762 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 6763 }; 6764 6765 struct mlx5_ifc_set_diagnostic_params_out_bits { 6766 u8 status[0x8]; 6767 u8 reserved_0[0x18]; 6768 6769 u8 syndrome[0x20]; 6770 6771 u8 reserved_1[0x40]; 6772 }; 6773 6774 struct mlx5_ifc_query_diagnostic_counters_in_bits { 6775 u8 opcode[0x10]; 6776 u8 reserved_0[0x10]; 6777 6778 u8 reserved_1[0x10]; 6779 u8 op_mod[0x10]; 6780 6781 u8 num_of_samples[0x10]; 6782 u8 sample_index[0x10]; 6783 6784 u8 reserved_2[0x20]; 6785 }; 6786 6787 struct mlx5_ifc_diagnostic_counter_bits { 6788 u8 counter_id[0x10]; 6789 u8 sample_id[0x10]; 6790 6791 u8 time_stamp_31_0[0x20]; 6792 6793 u8 counter_value_h[0x20]; 6794 6795 u8 counter_value_l[0x20]; 6796 }; 6797 6798 struct mlx5_ifc_query_diagnostic_counters_out_bits { 6799 u8 status[0x8]; 6800 u8 reserved_0[0x18]; 6801 6802 u8 syndrome[0x20]; 6803 6804 u8 reserved_1[0x40]; 6805 6806 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 6807 }; 6808 6809 struct mlx5_ifc_dealloc_q_counter_in_bits { 6810 u8 opcode[0x10]; 6811 u8 reserved_0[0x10]; 6812 6813 u8 reserved_1[0x10]; 6814 u8 op_mod[0x10]; 6815 6816 u8 reserved_2[0x18]; 6817 u8 counter_set_id[0x8]; 6818 6819 u8 reserved_3[0x20]; 6820 }; 6821 6822 struct mlx5_ifc_dealloc_pd_out_bits { 6823 u8 status[0x8]; 6824 u8 reserved_0[0x18]; 6825 6826 u8 syndrome[0x20]; 6827 6828 u8 reserved_1[0x40]; 6829 }; 6830 6831 struct mlx5_ifc_dealloc_pd_in_bits { 6832 u8 opcode[0x10]; 6833 u8 reserved_0[0x10]; 6834 6835 u8 reserved_1[0x10]; 6836 u8 op_mod[0x10]; 6837 6838 u8 reserved_2[0x8]; 6839 u8 pd[0x18]; 6840 6841 u8 reserved_3[0x20]; 6842 }; 6843 6844 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6845 u8 status[0x8]; 6846 u8 reserved_0[0x18]; 6847 6848 u8 syndrome[0x20]; 6849 6850 u8 reserved_1[0x40]; 6851 }; 6852 6853 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6854 u8 opcode[0x10]; 6855 u8 reserved_0[0x10]; 6856 6857 u8 reserved_1[0x10]; 6858 u8 op_mod[0x10]; 6859 6860 u8 reserved_2[0x10]; 6861 u8 flow_counter_id[0x10]; 6862 6863 u8 reserved_3[0x20]; 6864 }; 6865 6866 struct mlx5_ifc_deactivate_tracer_out_bits { 6867 u8 status[0x8]; 6868 u8 reserved_0[0x18]; 6869 6870 u8 syndrome[0x20]; 6871 6872 u8 reserved_1[0x40]; 6873 }; 6874 6875 struct mlx5_ifc_deactivate_tracer_in_bits { 6876 u8 opcode[0x10]; 6877 u8 reserved_0[0x10]; 6878 6879 u8 reserved_1[0x10]; 6880 u8 op_mod[0x10]; 6881 6882 u8 mkey[0x20]; 6883 6884 u8 reserved_2[0x20]; 6885 }; 6886 6887 struct mlx5_ifc_create_xrc_srq_out_bits { 6888 u8 status[0x8]; 6889 u8 reserved_0[0x18]; 6890 6891 u8 syndrome[0x20]; 6892 6893 u8 reserved_1[0x8]; 6894 u8 xrc_srqn[0x18]; 6895 6896 u8 reserved_2[0x20]; 6897 }; 6898 6899 struct mlx5_ifc_create_xrc_srq_in_bits { 6900 u8 opcode[0x10]; 6901 u8 reserved_0[0x10]; 6902 6903 u8 reserved_1[0x10]; 6904 u8 op_mod[0x10]; 6905 6906 u8 reserved_2[0x40]; 6907 6908 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6909 6910 u8 reserved_3[0x600]; 6911 6912 u8 pas[0][0x40]; 6913 }; 6914 6915 struct mlx5_ifc_create_tis_out_bits { 6916 u8 status[0x8]; 6917 u8 reserved_0[0x18]; 6918 6919 u8 syndrome[0x20]; 6920 6921 u8 reserved_1[0x8]; 6922 u8 tisn[0x18]; 6923 6924 u8 reserved_2[0x20]; 6925 }; 6926 6927 struct mlx5_ifc_create_tis_in_bits { 6928 u8 opcode[0x10]; 6929 u8 reserved_0[0x10]; 6930 6931 u8 reserved_1[0x10]; 6932 u8 op_mod[0x10]; 6933 6934 u8 reserved_2[0xc0]; 6935 6936 struct mlx5_ifc_tisc_bits ctx; 6937 }; 6938 6939 struct mlx5_ifc_create_tir_out_bits { 6940 u8 status[0x8]; 6941 u8 reserved_0[0x18]; 6942 6943 u8 syndrome[0x20]; 6944 6945 u8 reserved_1[0x8]; 6946 u8 tirn[0x18]; 6947 6948 u8 reserved_2[0x20]; 6949 }; 6950 6951 struct mlx5_ifc_create_tir_in_bits { 6952 u8 opcode[0x10]; 6953 u8 reserved_0[0x10]; 6954 6955 u8 reserved_1[0x10]; 6956 u8 op_mod[0x10]; 6957 6958 u8 reserved_2[0xc0]; 6959 6960 struct mlx5_ifc_tirc_bits tir_context; 6961 }; 6962 6963 struct mlx5_ifc_create_srq_out_bits { 6964 u8 status[0x8]; 6965 u8 reserved_0[0x18]; 6966 6967 u8 syndrome[0x20]; 6968 6969 u8 reserved_1[0x8]; 6970 u8 srqn[0x18]; 6971 6972 u8 reserved_2[0x20]; 6973 }; 6974 6975 struct mlx5_ifc_create_srq_in_bits { 6976 u8 opcode[0x10]; 6977 u8 reserved_0[0x10]; 6978 6979 u8 reserved_1[0x10]; 6980 u8 op_mod[0x10]; 6981 6982 u8 reserved_2[0x40]; 6983 6984 struct mlx5_ifc_srqc_bits srq_context_entry; 6985 6986 u8 reserved_3[0x600]; 6987 6988 u8 pas[0][0x40]; 6989 }; 6990 6991 struct mlx5_ifc_create_sq_out_bits { 6992 u8 status[0x8]; 6993 u8 reserved_0[0x18]; 6994 6995 u8 syndrome[0x20]; 6996 6997 u8 reserved_1[0x8]; 6998 u8 sqn[0x18]; 6999 7000 u8 reserved_2[0x20]; 7001 }; 7002 7003 struct mlx5_ifc_create_sq_in_bits { 7004 u8 opcode[0x10]; 7005 u8 reserved_0[0x10]; 7006 7007 u8 reserved_1[0x10]; 7008 u8 op_mod[0x10]; 7009 7010 u8 reserved_2[0xc0]; 7011 7012 struct mlx5_ifc_sqc_bits ctx; 7013 }; 7014 7015 struct mlx5_ifc_create_scheduling_element_out_bits { 7016 u8 status[0x8]; 7017 u8 reserved_at_8[0x18]; 7018 7019 u8 syndrome[0x20]; 7020 7021 u8 reserved_at_40[0x40]; 7022 7023 u8 scheduling_element_id[0x20]; 7024 7025 u8 reserved_at_a0[0x160]; 7026 }; 7027 7028 enum { 7029 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 7030 }; 7031 7032 struct mlx5_ifc_create_scheduling_element_in_bits { 7033 u8 opcode[0x10]; 7034 u8 reserved_at_10[0x10]; 7035 7036 u8 reserved_at_20[0x10]; 7037 u8 op_mod[0x10]; 7038 7039 u8 scheduling_hierarchy[0x8]; 7040 u8 reserved_at_48[0x18]; 7041 7042 u8 reserved_at_60[0xa0]; 7043 7044 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7045 7046 u8 reserved_at_300[0x100]; 7047 }; 7048 7049 struct mlx5_ifc_create_rqt_out_bits { 7050 u8 status[0x8]; 7051 u8 reserved_0[0x18]; 7052 7053 u8 syndrome[0x20]; 7054 7055 u8 reserved_1[0x8]; 7056 u8 rqtn[0x18]; 7057 7058 u8 reserved_2[0x20]; 7059 }; 7060 7061 struct mlx5_ifc_create_rqt_in_bits { 7062 u8 opcode[0x10]; 7063 u8 reserved_0[0x10]; 7064 7065 u8 reserved_1[0x10]; 7066 u8 op_mod[0x10]; 7067 7068 u8 reserved_2[0xc0]; 7069 7070 struct mlx5_ifc_rqtc_bits rqt_context; 7071 }; 7072 7073 struct mlx5_ifc_create_rq_out_bits { 7074 u8 status[0x8]; 7075 u8 reserved_0[0x18]; 7076 7077 u8 syndrome[0x20]; 7078 7079 u8 reserved_1[0x8]; 7080 u8 rqn[0x18]; 7081 7082 u8 reserved_2[0x20]; 7083 }; 7084 7085 struct mlx5_ifc_create_rq_in_bits { 7086 u8 opcode[0x10]; 7087 u8 reserved_0[0x10]; 7088 7089 u8 reserved_1[0x10]; 7090 u8 op_mod[0x10]; 7091 7092 u8 reserved_2[0xc0]; 7093 7094 struct mlx5_ifc_rqc_bits ctx; 7095 }; 7096 7097 struct mlx5_ifc_create_rmp_out_bits { 7098 u8 status[0x8]; 7099 u8 reserved_0[0x18]; 7100 7101 u8 syndrome[0x20]; 7102 7103 u8 reserved_1[0x8]; 7104 u8 rmpn[0x18]; 7105 7106 u8 reserved_2[0x20]; 7107 }; 7108 7109 struct mlx5_ifc_create_rmp_in_bits { 7110 u8 opcode[0x10]; 7111 u8 reserved_0[0x10]; 7112 7113 u8 reserved_1[0x10]; 7114 u8 op_mod[0x10]; 7115 7116 u8 reserved_2[0xc0]; 7117 7118 struct mlx5_ifc_rmpc_bits ctx; 7119 }; 7120 7121 struct mlx5_ifc_create_qp_out_bits { 7122 u8 status[0x8]; 7123 u8 reserved_0[0x18]; 7124 7125 u8 syndrome[0x20]; 7126 7127 u8 reserved_1[0x8]; 7128 u8 qpn[0x18]; 7129 7130 u8 reserved_2[0x20]; 7131 }; 7132 7133 struct mlx5_ifc_create_qp_in_bits { 7134 u8 opcode[0x10]; 7135 u8 reserved_0[0x10]; 7136 7137 u8 reserved_1[0x10]; 7138 u8 op_mod[0x10]; 7139 7140 u8 reserved_2[0x8]; 7141 u8 input_qpn[0x18]; 7142 7143 u8 reserved_3[0x20]; 7144 7145 u8 opt_param_mask[0x20]; 7146 7147 u8 reserved_4[0x20]; 7148 7149 struct mlx5_ifc_qpc_bits qpc; 7150 7151 u8 reserved_5[0x80]; 7152 7153 u8 pas[0][0x40]; 7154 }; 7155 7156 struct mlx5_ifc_create_qos_para_vport_out_bits { 7157 u8 status[0x8]; 7158 u8 reserved_at_8[0x18]; 7159 7160 u8 syndrome[0x20]; 7161 7162 u8 reserved_at_40[0x20]; 7163 7164 u8 reserved_at_60[0x10]; 7165 u8 qos_para_vport_number[0x10]; 7166 7167 u8 reserved_at_80[0x180]; 7168 }; 7169 7170 struct mlx5_ifc_create_qos_para_vport_in_bits { 7171 u8 opcode[0x10]; 7172 u8 reserved_at_10[0x10]; 7173 7174 u8 reserved_at_20[0x10]; 7175 u8 op_mod[0x10]; 7176 7177 u8 reserved_at_40[0x1c0]; 7178 }; 7179 7180 struct mlx5_ifc_create_psv_out_bits { 7181 u8 status[0x8]; 7182 u8 reserved_0[0x18]; 7183 7184 u8 syndrome[0x20]; 7185 7186 u8 reserved_1[0x40]; 7187 7188 u8 reserved_2[0x8]; 7189 u8 psv0_index[0x18]; 7190 7191 u8 reserved_3[0x8]; 7192 u8 psv1_index[0x18]; 7193 7194 u8 reserved_4[0x8]; 7195 u8 psv2_index[0x18]; 7196 7197 u8 reserved_5[0x8]; 7198 u8 psv3_index[0x18]; 7199 }; 7200 7201 struct mlx5_ifc_create_psv_in_bits { 7202 u8 opcode[0x10]; 7203 u8 reserved_0[0x10]; 7204 7205 u8 reserved_1[0x10]; 7206 u8 op_mod[0x10]; 7207 7208 u8 num_psv[0x4]; 7209 u8 reserved_2[0x4]; 7210 u8 pd[0x18]; 7211 7212 u8 reserved_3[0x20]; 7213 }; 7214 7215 struct mlx5_ifc_create_mkey_out_bits { 7216 u8 status[0x8]; 7217 u8 reserved_0[0x18]; 7218 7219 u8 syndrome[0x20]; 7220 7221 u8 reserved_1[0x8]; 7222 u8 mkey_index[0x18]; 7223 7224 u8 reserved_2[0x20]; 7225 }; 7226 7227 struct mlx5_ifc_create_mkey_in_bits { 7228 u8 opcode[0x10]; 7229 u8 reserved_0[0x10]; 7230 7231 u8 reserved_1[0x10]; 7232 u8 op_mod[0x10]; 7233 7234 u8 reserved_2[0x20]; 7235 7236 u8 pg_access[0x1]; 7237 u8 reserved_3[0x1f]; 7238 7239 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7240 7241 u8 reserved_4[0x80]; 7242 7243 u8 translations_octword_actual_size[0x20]; 7244 7245 u8 reserved_5[0x560]; 7246 7247 u8 klm_pas_mtt[0][0x20]; 7248 }; 7249 7250 struct mlx5_ifc_create_flow_table_out_bits { 7251 u8 status[0x8]; 7252 u8 reserved_0[0x18]; 7253 7254 u8 syndrome[0x20]; 7255 7256 u8 reserved_1[0x8]; 7257 u8 table_id[0x18]; 7258 7259 u8 reserved_2[0x20]; 7260 }; 7261 7262 struct mlx5_ifc_create_flow_table_in_bits { 7263 u8 opcode[0x10]; 7264 u8 reserved_at_10[0x10]; 7265 7266 u8 reserved_at_20[0x10]; 7267 u8 op_mod[0x10]; 7268 7269 u8 other_vport[0x1]; 7270 u8 reserved_at_41[0xf]; 7271 u8 vport_number[0x10]; 7272 7273 u8 reserved_at_60[0x20]; 7274 7275 u8 table_type[0x8]; 7276 u8 reserved_at_88[0x18]; 7277 7278 u8 reserved_at_a0[0x20]; 7279 7280 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7281 }; 7282 7283 struct mlx5_ifc_create_flow_group_out_bits { 7284 u8 status[0x8]; 7285 u8 reserved_0[0x18]; 7286 7287 u8 syndrome[0x20]; 7288 7289 u8 reserved_1[0x8]; 7290 u8 group_id[0x18]; 7291 7292 u8 reserved_2[0x20]; 7293 }; 7294 7295 enum { 7296 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7297 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7298 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7299 }; 7300 7301 struct mlx5_ifc_create_flow_group_in_bits { 7302 u8 opcode[0x10]; 7303 u8 reserved_0[0x10]; 7304 7305 u8 reserved_1[0x10]; 7306 u8 op_mod[0x10]; 7307 7308 u8 other_vport[0x1]; 7309 u8 reserved_2[0xf]; 7310 u8 vport_number[0x10]; 7311 7312 u8 reserved_3[0x20]; 7313 7314 u8 table_type[0x8]; 7315 u8 reserved_4[0x18]; 7316 7317 u8 reserved_5[0x8]; 7318 u8 table_id[0x18]; 7319 7320 u8 reserved_6[0x20]; 7321 7322 u8 start_flow_index[0x20]; 7323 7324 u8 reserved_7[0x20]; 7325 7326 u8 end_flow_index[0x20]; 7327 7328 u8 reserved_8[0xa0]; 7329 7330 u8 reserved_9[0x18]; 7331 u8 match_criteria_enable[0x8]; 7332 7333 struct mlx5_ifc_fte_match_param_bits match_criteria; 7334 7335 u8 reserved_10[0xe00]; 7336 }; 7337 7338 struct mlx5_ifc_create_encryption_key_out_bits { 7339 u8 status[0x8]; 7340 u8 reserved_at_8[0x18]; 7341 7342 u8 syndrome[0x20]; 7343 7344 u8 obj_id[0x20]; 7345 7346 u8 reserved_at_60[0x20]; 7347 }; 7348 7349 struct mlx5_ifc_create_encryption_key_in_bits { 7350 u8 opcode[0x10]; 7351 u8 reserved_at_10[0x10]; 7352 7353 u8 reserved_at_20[0x10]; 7354 u8 obj_type[0x10]; 7355 7356 u8 reserved_at_40[0x40]; 7357 7358 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 7359 }; 7360 7361 struct mlx5_ifc_create_eq_out_bits { 7362 u8 status[0x8]; 7363 u8 reserved_0[0x18]; 7364 7365 u8 syndrome[0x20]; 7366 7367 u8 reserved_1[0x18]; 7368 u8 eq_number[0x8]; 7369 7370 u8 reserved_2[0x20]; 7371 }; 7372 7373 struct mlx5_ifc_create_eq_in_bits { 7374 u8 opcode[0x10]; 7375 u8 reserved_0[0x10]; 7376 7377 u8 reserved_1[0x10]; 7378 u8 op_mod[0x10]; 7379 7380 u8 reserved_2[0x40]; 7381 7382 struct mlx5_ifc_eqc_bits eq_context_entry; 7383 7384 u8 reserved_3[0x40]; 7385 7386 u8 event_bitmask[0x40]; 7387 7388 u8 reserved_4[0x580]; 7389 7390 u8 pas[0][0x40]; 7391 }; 7392 7393 struct mlx5_ifc_create_dct_out_bits { 7394 u8 status[0x8]; 7395 u8 reserved_0[0x18]; 7396 7397 u8 syndrome[0x20]; 7398 7399 u8 reserved_1[0x8]; 7400 u8 dctn[0x18]; 7401 7402 u8 reserved_2[0x20]; 7403 }; 7404 7405 struct mlx5_ifc_create_dct_in_bits { 7406 u8 opcode[0x10]; 7407 u8 reserved_0[0x10]; 7408 7409 u8 reserved_1[0x10]; 7410 u8 op_mod[0x10]; 7411 7412 u8 reserved_2[0x40]; 7413 7414 struct mlx5_ifc_dctc_bits dct_context_entry; 7415 7416 u8 reserved_3[0x180]; 7417 }; 7418 7419 struct mlx5_ifc_create_cq_out_bits { 7420 u8 status[0x8]; 7421 u8 reserved_0[0x18]; 7422 7423 u8 syndrome[0x20]; 7424 7425 u8 reserved_1[0x8]; 7426 u8 cqn[0x18]; 7427 7428 u8 reserved_2[0x20]; 7429 }; 7430 7431 struct mlx5_ifc_create_cq_in_bits { 7432 u8 opcode[0x10]; 7433 u8 reserved_0[0x10]; 7434 7435 u8 reserved_1[0x10]; 7436 u8 op_mod[0x10]; 7437 7438 u8 reserved_2[0x40]; 7439 7440 struct mlx5_ifc_cqc_bits cq_context; 7441 7442 u8 reserved_3[0x600]; 7443 7444 u8 pas[0][0x40]; 7445 }; 7446 7447 struct mlx5_ifc_config_int_moderation_out_bits { 7448 u8 status[0x8]; 7449 u8 reserved_0[0x18]; 7450 7451 u8 syndrome[0x20]; 7452 7453 u8 reserved_1[0x4]; 7454 u8 min_delay[0xc]; 7455 u8 int_vector[0x10]; 7456 7457 u8 reserved_2[0x20]; 7458 }; 7459 7460 enum { 7461 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7462 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7463 }; 7464 7465 struct mlx5_ifc_config_int_moderation_in_bits { 7466 u8 opcode[0x10]; 7467 u8 reserved_0[0x10]; 7468 7469 u8 reserved_1[0x10]; 7470 u8 op_mod[0x10]; 7471 7472 u8 reserved_2[0x4]; 7473 u8 min_delay[0xc]; 7474 u8 int_vector[0x10]; 7475 7476 u8 reserved_3[0x20]; 7477 }; 7478 7479 struct mlx5_ifc_attach_to_mcg_out_bits { 7480 u8 status[0x8]; 7481 u8 reserved_0[0x18]; 7482 7483 u8 syndrome[0x20]; 7484 7485 u8 reserved_1[0x40]; 7486 }; 7487 7488 struct mlx5_ifc_attach_to_mcg_in_bits { 7489 u8 opcode[0x10]; 7490 u8 reserved_0[0x10]; 7491 7492 u8 reserved_1[0x10]; 7493 u8 op_mod[0x10]; 7494 7495 u8 reserved_2[0x8]; 7496 u8 qpn[0x18]; 7497 7498 u8 reserved_3[0x20]; 7499 7500 u8 multicast_gid[16][0x8]; 7501 }; 7502 7503 struct mlx5_ifc_arm_xrc_srq_out_bits { 7504 u8 status[0x8]; 7505 u8 reserved_0[0x18]; 7506 7507 u8 syndrome[0x20]; 7508 7509 u8 reserved_1[0x40]; 7510 }; 7511 7512 enum { 7513 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7514 }; 7515 7516 struct mlx5_ifc_arm_xrc_srq_in_bits { 7517 u8 opcode[0x10]; 7518 u8 reserved_0[0x10]; 7519 7520 u8 reserved_1[0x10]; 7521 u8 op_mod[0x10]; 7522 7523 u8 reserved_2[0x8]; 7524 u8 xrc_srqn[0x18]; 7525 7526 u8 reserved_3[0x10]; 7527 u8 lwm[0x10]; 7528 }; 7529 7530 struct mlx5_ifc_arm_rq_out_bits { 7531 u8 status[0x8]; 7532 u8 reserved_0[0x18]; 7533 7534 u8 syndrome[0x20]; 7535 7536 u8 reserved_1[0x40]; 7537 }; 7538 7539 enum { 7540 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7541 }; 7542 7543 struct mlx5_ifc_arm_rq_in_bits { 7544 u8 opcode[0x10]; 7545 u8 reserved_0[0x10]; 7546 7547 u8 reserved_1[0x10]; 7548 u8 op_mod[0x10]; 7549 7550 u8 reserved_2[0x8]; 7551 u8 srq_number[0x18]; 7552 7553 u8 reserved_3[0x10]; 7554 u8 lwm[0x10]; 7555 }; 7556 7557 struct mlx5_ifc_arm_dct_out_bits { 7558 u8 status[0x8]; 7559 u8 reserved_0[0x18]; 7560 7561 u8 syndrome[0x20]; 7562 7563 u8 reserved_1[0x40]; 7564 }; 7565 7566 struct mlx5_ifc_arm_dct_in_bits { 7567 u8 opcode[0x10]; 7568 u8 reserved_0[0x10]; 7569 7570 u8 reserved_1[0x10]; 7571 u8 op_mod[0x10]; 7572 7573 u8 reserved_2[0x8]; 7574 u8 dctn[0x18]; 7575 7576 u8 reserved_3[0x20]; 7577 }; 7578 7579 struct mlx5_ifc_alloc_xrcd_out_bits { 7580 u8 status[0x8]; 7581 u8 reserved_0[0x18]; 7582 7583 u8 syndrome[0x20]; 7584 7585 u8 reserved_1[0x8]; 7586 u8 xrcd[0x18]; 7587 7588 u8 reserved_2[0x20]; 7589 }; 7590 7591 struct mlx5_ifc_alloc_xrcd_in_bits { 7592 u8 opcode[0x10]; 7593 u8 reserved_0[0x10]; 7594 7595 u8 reserved_1[0x10]; 7596 u8 op_mod[0x10]; 7597 7598 u8 reserved_2[0x40]; 7599 }; 7600 7601 struct mlx5_ifc_alloc_uar_out_bits { 7602 u8 status[0x8]; 7603 u8 reserved_0[0x18]; 7604 7605 u8 syndrome[0x20]; 7606 7607 u8 reserved_1[0x8]; 7608 u8 uar[0x18]; 7609 7610 u8 reserved_2[0x20]; 7611 }; 7612 7613 struct mlx5_ifc_alloc_uar_in_bits { 7614 u8 opcode[0x10]; 7615 u8 reserved_0[0x10]; 7616 7617 u8 reserved_1[0x10]; 7618 u8 op_mod[0x10]; 7619 7620 u8 reserved_2[0x40]; 7621 }; 7622 7623 struct mlx5_ifc_alloc_transport_domain_out_bits { 7624 u8 status[0x8]; 7625 u8 reserved_0[0x18]; 7626 7627 u8 syndrome[0x20]; 7628 7629 u8 reserved_1[0x8]; 7630 u8 transport_domain[0x18]; 7631 7632 u8 reserved_2[0x20]; 7633 }; 7634 7635 struct mlx5_ifc_alloc_transport_domain_in_bits { 7636 u8 opcode[0x10]; 7637 u8 reserved_0[0x10]; 7638 7639 u8 reserved_1[0x10]; 7640 u8 op_mod[0x10]; 7641 7642 u8 reserved_2[0x40]; 7643 }; 7644 7645 struct mlx5_ifc_alloc_q_counter_out_bits { 7646 u8 status[0x8]; 7647 u8 reserved_0[0x18]; 7648 7649 u8 syndrome[0x20]; 7650 7651 u8 reserved_1[0x18]; 7652 u8 counter_set_id[0x8]; 7653 7654 u8 reserved_2[0x20]; 7655 }; 7656 7657 struct mlx5_ifc_alloc_q_counter_in_bits { 7658 u8 opcode[0x10]; 7659 u8 reserved_0[0x10]; 7660 7661 u8 reserved_1[0x10]; 7662 u8 op_mod[0x10]; 7663 7664 u8 reserved_2[0x40]; 7665 }; 7666 7667 struct mlx5_ifc_alloc_pd_out_bits { 7668 u8 status[0x8]; 7669 u8 reserved_0[0x18]; 7670 7671 u8 syndrome[0x20]; 7672 7673 u8 reserved_1[0x8]; 7674 u8 pd[0x18]; 7675 7676 u8 reserved_2[0x20]; 7677 }; 7678 7679 struct mlx5_ifc_alloc_pd_in_bits { 7680 u8 opcode[0x10]; 7681 u8 reserved_0[0x10]; 7682 7683 u8 reserved_1[0x10]; 7684 u8 op_mod[0x10]; 7685 7686 u8 reserved_2[0x40]; 7687 }; 7688 7689 struct mlx5_ifc_alloc_flow_counter_out_bits { 7690 u8 status[0x8]; 7691 u8 reserved_0[0x18]; 7692 7693 u8 syndrome[0x20]; 7694 7695 u8 reserved_1[0x10]; 7696 u8 flow_counter_id[0x10]; 7697 7698 u8 reserved_2[0x20]; 7699 }; 7700 7701 struct mlx5_ifc_alloc_flow_counter_in_bits { 7702 u8 opcode[0x10]; 7703 u8 reserved_0[0x10]; 7704 7705 u8 reserved_1[0x10]; 7706 u8 op_mod[0x10]; 7707 7708 u8 reserved_2[0x40]; 7709 }; 7710 7711 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7712 u8 status[0x8]; 7713 u8 reserved_0[0x18]; 7714 7715 u8 syndrome[0x20]; 7716 7717 u8 reserved_1[0x40]; 7718 }; 7719 7720 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7721 u8 opcode[0x10]; 7722 u8 reserved_0[0x10]; 7723 7724 u8 reserved_1[0x10]; 7725 u8 op_mod[0x10]; 7726 7727 u8 reserved_2[0x20]; 7728 7729 u8 reserved_3[0x10]; 7730 u8 vxlan_udp_port[0x10]; 7731 }; 7732 7733 struct mlx5_ifc_activate_tracer_out_bits { 7734 u8 status[0x8]; 7735 u8 reserved_0[0x18]; 7736 7737 u8 syndrome[0x20]; 7738 7739 u8 reserved_1[0x40]; 7740 }; 7741 7742 struct mlx5_ifc_activate_tracer_in_bits { 7743 u8 opcode[0x10]; 7744 u8 reserved_0[0x10]; 7745 7746 u8 reserved_1[0x10]; 7747 u8 op_mod[0x10]; 7748 7749 u8 mkey[0x20]; 7750 7751 u8 reserved_2[0x20]; 7752 }; 7753 7754 struct mlx5_ifc_set_rate_limit_out_bits { 7755 u8 status[0x8]; 7756 u8 reserved_at_8[0x18]; 7757 7758 u8 syndrome[0x20]; 7759 7760 u8 reserved_at_40[0x40]; 7761 }; 7762 7763 struct mlx5_ifc_set_rate_limit_in_bits { 7764 u8 opcode[0x10]; 7765 u8 reserved_at_10[0x10]; 7766 7767 u8 reserved_at_20[0x10]; 7768 u8 op_mod[0x10]; 7769 7770 u8 reserved_at_40[0x10]; 7771 u8 rate_limit_index[0x10]; 7772 7773 u8 reserved_at_60[0x20]; 7774 7775 u8 rate_limit[0x20]; 7776 7777 u8 burst_upper_bound[0x20]; 7778 7779 u8 reserved_at_c0[0x10]; 7780 u8 typical_packet_size[0x10]; 7781 7782 u8 reserved_at_e0[0x120]; 7783 }; 7784 7785 struct mlx5_ifc_access_register_out_bits { 7786 u8 status[0x8]; 7787 u8 reserved_0[0x18]; 7788 7789 u8 syndrome[0x20]; 7790 7791 u8 reserved_1[0x40]; 7792 7793 u8 register_data[0][0x20]; 7794 }; 7795 7796 enum { 7797 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7798 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7799 }; 7800 7801 struct mlx5_ifc_access_register_in_bits { 7802 u8 opcode[0x10]; 7803 u8 reserved_0[0x10]; 7804 7805 u8 reserved_1[0x10]; 7806 u8 op_mod[0x10]; 7807 7808 u8 reserved_2[0x10]; 7809 u8 register_id[0x10]; 7810 7811 u8 argument[0x20]; 7812 7813 u8 register_data[0][0x20]; 7814 }; 7815 7816 struct mlx5_ifc_sltp_reg_bits { 7817 u8 status[0x4]; 7818 u8 version[0x4]; 7819 u8 local_port[0x8]; 7820 u8 pnat[0x2]; 7821 u8 reserved_0[0x2]; 7822 u8 lane[0x4]; 7823 u8 reserved_1[0x8]; 7824 7825 u8 reserved_2[0x20]; 7826 7827 u8 reserved_3[0x7]; 7828 u8 polarity[0x1]; 7829 u8 ob_tap0[0x8]; 7830 u8 ob_tap1[0x8]; 7831 u8 ob_tap2[0x8]; 7832 7833 u8 reserved_4[0xc]; 7834 u8 ob_preemp_mode[0x4]; 7835 u8 ob_reg[0x8]; 7836 u8 ob_bias[0x8]; 7837 7838 u8 reserved_5[0x20]; 7839 }; 7840 7841 struct mlx5_ifc_slrp_reg_bits { 7842 u8 status[0x4]; 7843 u8 version[0x4]; 7844 u8 local_port[0x8]; 7845 u8 pnat[0x2]; 7846 u8 reserved_0[0x2]; 7847 u8 lane[0x4]; 7848 u8 reserved_1[0x8]; 7849 7850 u8 ib_sel[0x2]; 7851 u8 reserved_2[0x11]; 7852 u8 dp_sel[0x1]; 7853 u8 dp90sel[0x4]; 7854 u8 mix90phase[0x8]; 7855 7856 u8 ffe_tap0[0x8]; 7857 u8 ffe_tap1[0x8]; 7858 u8 ffe_tap2[0x8]; 7859 u8 ffe_tap3[0x8]; 7860 7861 u8 ffe_tap4[0x8]; 7862 u8 ffe_tap5[0x8]; 7863 u8 ffe_tap6[0x8]; 7864 u8 ffe_tap7[0x8]; 7865 7866 u8 ffe_tap8[0x8]; 7867 u8 mixerbias_tap_amp[0x8]; 7868 u8 reserved_3[0x7]; 7869 u8 ffe_tap_en[0x9]; 7870 7871 u8 ffe_tap_offset0[0x8]; 7872 u8 ffe_tap_offset1[0x8]; 7873 u8 slicer_offset0[0x10]; 7874 7875 u8 mixer_offset0[0x10]; 7876 u8 mixer_offset1[0x10]; 7877 7878 u8 mixerbgn_inp[0x8]; 7879 u8 mixerbgn_inn[0x8]; 7880 u8 mixerbgn_refp[0x8]; 7881 u8 mixerbgn_refn[0x8]; 7882 7883 u8 sel_slicer_lctrl_h[0x1]; 7884 u8 sel_slicer_lctrl_l[0x1]; 7885 u8 reserved_4[0x1]; 7886 u8 ref_mixer_vreg[0x5]; 7887 u8 slicer_gctrl[0x8]; 7888 u8 lctrl_input[0x8]; 7889 u8 mixer_offset_cm1[0x8]; 7890 7891 u8 common_mode[0x6]; 7892 u8 reserved_5[0x1]; 7893 u8 mixer_offset_cm0[0x9]; 7894 u8 reserved_6[0x7]; 7895 u8 slicer_offset_cm[0x9]; 7896 }; 7897 7898 struct mlx5_ifc_slrg_reg_bits { 7899 u8 status[0x4]; 7900 u8 version[0x4]; 7901 u8 local_port[0x8]; 7902 u8 pnat[0x2]; 7903 u8 reserved_0[0x2]; 7904 u8 lane[0x4]; 7905 u8 reserved_1[0x8]; 7906 7907 u8 time_to_link_up[0x10]; 7908 u8 reserved_2[0xc]; 7909 u8 grade_lane_speed[0x4]; 7910 7911 u8 grade_version[0x8]; 7912 u8 grade[0x18]; 7913 7914 u8 reserved_3[0x4]; 7915 u8 height_grade_type[0x4]; 7916 u8 height_grade[0x18]; 7917 7918 u8 height_dz[0x10]; 7919 u8 height_dv[0x10]; 7920 7921 u8 reserved_4[0x10]; 7922 u8 height_sigma[0x10]; 7923 7924 u8 reserved_5[0x20]; 7925 7926 u8 reserved_6[0x4]; 7927 u8 phase_grade_type[0x4]; 7928 u8 phase_grade[0x18]; 7929 7930 u8 reserved_7[0x8]; 7931 u8 phase_eo_pos[0x8]; 7932 u8 reserved_8[0x8]; 7933 u8 phase_eo_neg[0x8]; 7934 7935 u8 ffe_set_tested[0x10]; 7936 u8 test_errors_per_lane[0x10]; 7937 }; 7938 7939 struct mlx5_ifc_pvlc_reg_bits { 7940 u8 reserved_0[0x8]; 7941 u8 local_port[0x8]; 7942 u8 reserved_1[0x10]; 7943 7944 u8 reserved_2[0x1c]; 7945 u8 vl_hw_cap[0x4]; 7946 7947 u8 reserved_3[0x1c]; 7948 u8 vl_admin[0x4]; 7949 7950 u8 reserved_4[0x1c]; 7951 u8 vl_operational[0x4]; 7952 }; 7953 7954 struct mlx5_ifc_pude_reg_bits { 7955 u8 swid[0x8]; 7956 u8 local_port[0x8]; 7957 u8 reserved_0[0x4]; 7958 u8 admin_status[0x4]; 7959 u8 reserved_1[0x4]; 7960 u8 oper_status[0x4]; 7961 7962 u8 reserved_2[0x60]; 7963 }; 7964 7965 enum { 7966 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 7967 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 7968 }; 7969 7970 struct mlx5_ifc_ptys_reg_bits { 7971 u8 reserved_0[0x1]; 7972 u8 an_disable_admin[0x1]; 7973 u8 an_disable_cap[0x1]; 7974 u8 reserved_1[0x4]; 7975 u8 force_tx_aba_param[0x1]; 7976 u8 local_port[0x8]; 7977 u8 reserved_2[0xd]; 7978 u8 proto_mask[0x3]; 7979 7980 u8 an_status[0x4]; 7981 u8 reserved_3[0xc]; 7982 u8 data_rate_oper[0x10]; 7983 7984 u8 ext_eth_proto_capability[0x20]; 7985 7986 u8 eth_proto_capability[0x20]; 7987 7988 u8 ib_link_width_capability[0x10]; 7989 u8 ib_proto_capability[0x10]; 7990 7991 u8 ext_eth_proto_admin[0x20]; 7992 7993 u8 eth_proto_admin[0x20]; 7994 7995 u8 ib_link_width_admin[0x10]; 7996 u8 ib_proto_admin[0x10]; 7997 7998 u8 ext_eth_proto_oper[0x20]; 7999 8000 u8 eth_proto_oper[0x20]; 8001 8002 u8 ib_link_width_oper[0x10]; 8003 u8 ib_proto_oper[0x10]; 8004 8005 u8 reserved_4[0x1c]; 8006 u8 connector_type[0x4]; 8007 8008 u8 eth_proto_lp_advertise[0x20]; 8009 8010 u8 reserved_5[0x60]; 8011 }; 8012 8013 struct mlx5_ifc_ptas_reg_bits { 8014 u8 reserved_0[0x20]; 8015 8016 u8 algorithm_options[0x10]; 8017 u8 reserved_1[0x4]; 8018 u8 repetitions_mode[0x4]; 8019 u8 num_of_repetitions[0x8]; 8020 8021 u8 grade_version[0x8]; 8022 u8 height_grade_type[0x4]; 8023 u8 phase_grade_type[0x4]; 8024 u8 height_grade_weight[0x8]; 8025 u8 phase_grade_weight[0x8]; 8026 8027 u8 gisim_measure_bits[0x10]; 8028 u8 adaptive_tap_measure_bits[0x10]; 8029 8030 u8 ber_bath_high_error_threshold[0x10]; 8031 u8 ber_bath_mid_error_threshold[0x10]; 8032 8033 u8 ber_bath_low_error_threshold[0x10]; 8034 u8 one_ratio_high_threshold[0x10]; 8035 8036 u8 one_ratio_high_mid_threshold[0x10]; 8037 u8 one_ratio_low_mid_threshold[0x10]; 8038 8039 u8 one_ratio_low_threshold[0x10]; 8040 u8 ndeo_error_threshold[0x10]; 8041 8042 u8 mixer_offset_step_size[0x10]; 8043 u8 reserved_2[0x8]; 8044 u8 mix90_phase_for_voltage_bath[0x8]; 8045 8046 u8 mixer_offset_start[0x10]; 8047 u8 mixer_offset_end[0x10]; 8048 8049 u8 reserved_3[0x15]; 8050 u8 ber_test_time[0xb]; 8051 }; 8052 8053 struct mlx5_ifc_pspa_reg_bits { 8054 u8 swid[0x8]; 8055 u8 local_port[0x8]; 8056 u8 sub_port[0x8]; 8057 u8 reserved_0[0x8]; 8058 8059 u8 reserved_1[0x20]; 8060 }; 8061 8062 struct mlx5_ifc_ppsc_reg_bits { 8063 u8 reserved_0[0x8]; 8064 u8 local_port[0x8]; 8065 u8 reserved_1[0x10]; 8066 8067 u8 reserved_2[0x60]; 8068 8069 u8 reserved_3[0x1c]; 8070 u8 wrps_admin[0x4]; 8071 8072 u8 reserved_4[0x1c]; 8073 u8 wrps_status[0x4]; 8074 8075 u8 up_th_vld[0x1]; 8076 u8 down_th_vld[0x1]; 8077 u8 reserved_5[0x6]; 8078 u8 up_threshold[0x8]; 8079 u8 reserved_6[0x8]; 8080 u8 down_threshold[0x8]; 8081 8082 u8 reserved_7[0x20]; 8083 8084 u8 reserved_8[0x1c]; 8085 u8 srps_admin[0x4]; 8086 8087 u8 reserved_9[0x60]; 8088 }; 8089 8090 struct mlx5_ifc_pplr_reg_bits { 8091 u8 reserved_0[0x8]; 8092 u8 local_port[0x8]; 8093 u8 reserved_1[0x10]; 8094 8095 u8 reserved_2[0x8]; 8096 u8 lb_cap[0x8]; 8097 u8 reserved_3[0x8]; 8098 u8 lb_en[0x8]; 8099 }; 8100 8101 struct mlx5_ifc_pplm_reg_bits { 8102 u8 reserved_at_0[0x8]; 8103 u8 local_port[0x8]; 8104 u8 reserved_at_10[0x10]; 8105 8106 u8 reserved_at_20[0x20]; 8107 8108 u8 port_profile_mode[0x8]; 8109 u8 static_port_profile[0x8]; 8110 u8 active_port_profile[0x8]; 8111 u8 reserved_at_58[0x8]; 8112 8113 u8 retransmission_active[0x8]; 8114 u8 fec_mode_active[0x18]; 8115 8116 u8 rs_fec_correction_bypass_cap[0x4]; 8117 u8 reserved_at_84[0x8]; 8118 u8 fec_override_cap_56g[0x4]; 8119 u8 fec_override_cap_100g[0x4]; 8120 u8 fec_override_cap_50g[0x4]; 8121 u8 fec_override_cap_25g[0x4]; 8122 u8 fec_override_cap_10g_40g[0x4]; 8123 8124 u8 rs_fec_correction_bypass_admin[0x4]; 8125 u8 reserved_at_a4[0x8]; 8126 u8 fec_override_admin_56g[0x4]; 8127 u8 fec_override_admin_100g[0x4]; 8128 u8 fec_override_admin_50g[0x4]; 8129 u8 fec_override_admin_25g[0x4]; 8130 u8 fec_override_admin_10g_40g[0x4]; 8131 8132 u8 fec_override_cap_400g_8x[0x10]; 8133 u8 fec_override_cap_200g_4x[0x10]; 8134 u8 fec_override_cap_100g_2x[0x10]; 8135 u8 fec_override_cap_50g_1x[0x10]; 8136 8137 u8 fec_override_admin_400g_8x[0x10]; 8138 u8 fec_override_admin_200g_4x[0x10]; 8139 u8 fec_override_admin_100g_2x[0x10]; 8140 u8 fec_override_admin_50g_1x[0x10]; 8141 8142 u8 reserved_at_140[0xC0]; 8143 }; 8144 8145 struct mlx5_ifc_ppll_reg_bits { 8146 u8 num_pll_groups[0x8]; 8147 u8 pll_group[0x8]; 8148 u8 reserved_0[0x4]; 8149 u8 num_plls[0x4]; 8150 u8 reserved_1[0x8]; 8151 8152 u8 reserved_2[0x1f]; 8153 u8 ae[0x1]; 8154 8155 u8 pll_status[4][0x40]; 8156 }; 8157 8158 struct mlx5_ifc_ppad_reg_bits { 8159 u8 reserved_0[0x3]; 8160 u8 single_mac[0x1]; 8161 u8 reserved_1[0x4]; 8162 u8 local_port[0x8]; 8163 u8 mac_47_32[0x10]; 8164 8165 u8 mac_31_0[0x20]; 8166 8167 u8 reserved_2[0x40]; 8168 }; 8169 8170 struct mlx5_ifc_pmtu_reg_bits { 8171 u8 reserved_0[0x8]; 8172 u8 local_port[0x8]; 8173 u8 reserved_1[0x10]; 8174 8175 u8 max_mtu[0x10]; 8176 u8 reserved_2[0x10]; 8177 8178 u8 admin_mtu[0x10]; 8179 u8 reserved_3[0x10]; 8180 8181 u8 oper_mtu[0x10]; 8182 u8 reserved_4[0x10]; 8183 }; 8184 8185 struct mlx5_ifc_pmpr_reg_bits { 8186 u8 reserved_0[0x8]; 8187 u8 module[0x8]; 8188 u8 reserved_1[0x10]; 8189 8190 u8 reserved_2[0x18]; 8191 u8 attenuation_5g[0x8]; 8192 8193 u8 reserved_3[0x18]; 8194 u8 attenuation_7g[0x8]; 8195 8196 u8 reserved_4[0x18]; 8197 u8 attenuation_12g[0x8]; 8198 }; 8199 8200 struct mlx5_ifc_pmpe_reg_bits { 8201 u8 reserved_0[0x8]; 8202 u8 module[0x8]; 8203 u8 reserved_1[0xc]; 8204 u8 module_status[0x4]; 8205 8206 u8 reserved_2[0x14]; 8207 u8 error_type[0x4]; 8208 u8 reserved_3[0x8]; 8209 8210 u8 reserved_4[0x40]; 8211 }; 8212 8213 struct mlx5_ifc_pmpc_reg_bits { 8214 u8 module_state_updated[32][0x8]; 8215 }; 8216 8217 struct mlx5_ifc_pmlpn_reg_bits { 8218 u8 reserved_0[0x4]; 8219 u8 mlpn_status[0x4]; 8220 u8 local_port[0x8]; 8221 u8 reserved_1[0x10]; 8222 8223 u8 e[0x1]; 8224 u8 reserved_2[0x1f]; 8225 }; 8226 8227 struct mlx5_ifc_pmlp_reg_bits { 8228 u8 rxtx[0x1]; 8229 u8 reserved_0[0x7]; 8230 u8 local_port[0x8]; 8231 u8 reserved_1[0x8]; 8232 u8 width[0x8]; 8233 8234 u8 lane0_module_mapping[0x20]; 8235 8236 u8 lane1_module_mapping[0x20]; 8237 8238 u8 lane2_module_mapping[0x20]; 8239 8240 u8 lane3_module_mapping[0x20]; 8241 8242 u8 reserved_2[0x160]; 8243 }; 8244 8245 struct mlx5_ifc_pmaos_reg_bits { 8246 u8 reserved_0[0x8]; 8247 u8 module[0x8]; 8248 u8 reserved_1[0x4]; 8249 u8 admin_status[0x4]; 8250 u8 reserved_2[0x4]; 8251 u8 oper_status[0x4]; 8252 8253 u8 ase[0x1]; 8254 u8 ee[0x1]; 8255 u8 reserved_3[0x12]; 8256 u8 error_type[0x4]; 8257 u8 reserved_4[0x6]; 8258 u8 e[0x2]; 8259 8260 u8 reserved_5[0x40]; 8261 }; 8262 8263 struct mlx5_ifc_plpc_reg_bits { 8264 u8 reserved_0[0x4]; 8265 u8 profile_id[0xc]; 8266 u8 reserved_1[0x4]; 8267 u8 proto_mask[0x4]; 8268 u8 reserved_2[0x8]; 8269 8270 u8 reserved_3[0x10]; 8271 u8 lane_speed[0x10]; 8272 8273 u8 reserved_4[0x17]; 8274 u8 lpbf[0x1]; 8275 u8 fec_mode_policy[0x8]; 8276 8277 u8 retransmission_capability[0x8]; 8278 u8 fec_mode_capability[0x18]; 8279 8280 u8 retransmission_support_admin[0x8]; 8281 u8 fec_mode_support_admin[0x18]; 8282 8283 u8 retransmission_request_admin[0x8]; 8284 u8 fec_mode_request_admin[0x18]; 8285 8286 u8 reserved_5[0x80]; 8287 }; 8288 8289 struct mlx5_ifc_pll_status_data_bits { 8290 u8 reserved_0[0x1]; 8291 u8 lock_cal[0x1]; 8292 u8 lock_status[0x2]; 8293 u8 reserved_1[0x2]; 8294 u8 algo_f_ctrl[0xa]; 8295 u8 analog_algo_num_var[0x6]; 8296 u8 f_ctrl_measure[0xa]; 8297 8298 u8 reserved_2[0x2]; 8299 u8 analog_var[0x6]; 8300 u8 reserved_3[0x2]; 8301 u8 high_var[0x6]; 8302 u8 reserved_4[0x2]; 8303 u8 low_var[0x6]; 8304 u8 reserved_5[0x2]; 8305 u8 mid_val[0x6]; 8306 }; 8307 8308 struct mlx5_ifc_plib_reg_bits { 8309 u8 reserved_0[0x8]; 8310 u8 local_port[0x8]; 8311 u8 reserved_1[0x8]; 8312 u8 ib_port[0x8]; 8313 8314 u8 reserved_2[0x60]; 8315 }; 8316 8317 struct mlx5_ifc_plbf_reg_bits { 8318 u8 reserved_0[0x8]; 8319 u8 local_port[0x8]; 8320 u8 reserved_1[0xd]; 8321 u8 lbf_mode[0x3]; 8322 8323 u8 reserved_2[0x20]; 8324 }; 8325 8326 struct mlx5_ifc_pipg_reg_bits { 8327 u8 reserved_0[0x8]; 8328 u8 local_port[0x8]; 8329 u8 reserved_1[0x10]; 8330 8331 u8 dic[0x1]; 8332 u8 reserved_2[0x19]; 8333 u8 ipg[0x4]; 8334 u8 reserved_3[0x2]; 8335 }; 8336 8337 struct mlx5_ifc_pifr_reg_bits { 8338 u8 reserved_0[0x8]; 8339 u8 local_port[0x8]; 8340 u8 reserved_1[0x10]; 8341 8342 u8 reserved_2[0xe0]; 8343 8344 u8 port_filter[8][0x20]; 8345 8346 u8 port_filter_update_en[8][0x20]; 8347 }; 8348 8349 struct mlx5_ifc_phys_layer_cntrs_bits { 8350 u8 time_since_last_clear_high[0x20]; 8351 8352 u8 time_since_last_clear_low[0x20]; 8353 8354 u8 symbol_errors_high[0x20]; 8355 8356 u8 symbol_errors_low[0x20]; 8357 8358 u8 sync_headers_errors_high[0x20]; 8359 8360 u8 sync_headers_errors_low[0x20]; 8361 8362 u8 edpl_bip_errors_lane0_high[0x20]; 8363 8364 u8 edpl_bip_errors_lane0_low[0x20]; 8365 8366 u8 edpl_bip_errors_lane1_high[0x20]; 8367 8368 u8 edpl_bip_errors_lane1_low[0x20]; 8369 8370 u8 edpl_bip_errors_lane2_high[0x20]; 8371 8372 u8 edpl_bip_errors_lane2_low[0x20]; 8373 8374 u8 edpl_bip_errors_lane3_high[0x20]; 8375 8376 u8 edpl_bip_errors_lane3_low[0x20]; 8377 8378 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 8379 8380 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 8381 8382 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 8383 8384 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 8385 8386 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 8387 8388 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 8389 8390 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 8391 8392 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 8393 8394 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 8395 8396 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 8397 8398 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 8399 8400 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 8401 8402 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 8403 8404 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 8405 8406 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 8407 8408 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 8409 8410 u8 rs_fec_corrected_blocks_high[0x20]; 8411 8412 u8 rs_fec_corrected_blocks_low[0x20]; 8413 8414 u8 rs_fec_uncorrectable_blocks_high[0x20]; 8415 8416 u8 rs_fec_uncorrectable_blocks_low[0x20]; 8417 8418 u8 rs_fec_no_errors_blocks_high[0x20]; 8419 8420 u8 rs_fec_no_errors_blocks_low[0x20]; 8421 8422 u8 rs_fec_single_error_blocks_high[0x20]; 8423 8424 u8 rs_fec_single_error_blocks_low[0x20]; 8425 8426 u8 rs_fec_corrected_symbols_total_high[0x20]; 8427 8428 u8 rs_fec_corrected_symbols_total_low[0x20]; 8429 8430 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 8431 8432 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 8433 8434 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 8435 8436 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 8437 8438 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 8439 8440 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 8441 8442 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 8443 8444 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 8445 8446 u8 link_down_events[0x20]; 8447 8448 u8 successful_recovery_events[0x20]; 8449 8450 u8 reserved_0[0x180]; 8451 }; 8452 8453 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 8454 u8 symbol_error_counter[0x10]; 8455 8456 u8 link_error_recovery_counter[0x8]; 8457 8458 u8 link_downed_counter[0x8]; 8459 8460 u8 port_rcv_errors[0x10]; 8461 8462 u8 port_rcv_remote_physical_errors[0x10]; 8463 8464 u8 port_rcv_switch_relay_errors[0x10]; 8465 8466 u8 port_xmit_discards[0x10]; 8467 8468 u8 port_xmit_constraint_errors[0x8]; 8469 8470 u8 port_rcv_constraint_errors[0x8]; 8471 8472 u8 reserved_at_70[0x8]; 8473 8474 u8 link_overrun_errors[0x8]; 8475 8476 u8 reserved_at_80[0x10]; 8477 8478 u8 vl_15_dropped[0x10]; 8479 8480 u8 reserved_at_a0[0xa0]; 8481 }; 8482 8483 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 8484 u8 time_since_last_clear_high[0x20]; 8485 8486 u8 time_since_last_clear_low[0x20]; 8487 8488 u8 phy_received_bits_high[0x20]; 8489 8490 u8 phy_received_bits_low[0x20]; 8491 8492 u8 phy_symbol_errors_high[0x20]; 8493 8494 u8 phy_symbol_errors_low[0x20]; 8495 8496 u8 phy_corrected_bits_high[0x20]; 8497 8498 u8 phy_corrected_bits_low[0x20]; 8499 8500 u8 phy_corrected_bits_lane0_high[0x20]; 8501 8502 u8 phy_corrected_bits_lane0_low[0x20]; 8503 8504 u8 phy_corrected_bits_lane1_high[0x20]; 8505 8506 u8 phy_corrected_bits_lane1_low[0x20]; 8507 8508 u8 phy_corrected_bits_lane2_high[0x20]; 8509 8510 u8 phy_corrected_bits_lane2_low[0x20]; 8511 8512 u8 phy_corrected_bits_lane3_high[0x20]; 8513 8514 u8 phy_corrected_bits_lane3_low[0x20]; 8515 8516 u8 reserved_at_200[0x5c0]; 8517 }; 8518 8519 struct mlx5_ifc_infiniband_port_cntrs_bits { 8520 u8 symbol_error_counter[0x10]; 8521 u8 link_error_recovery_counter[0x8]; 8522 u8 link_downed_counter[0x8]; 8523 8524 u8 port_rcv_errors[0x10]; 8525 u8 port_rcv_remote_physical_errors[0x10]; 8526 8527 u8 port_rcv_switch_relay_errors[0x10]; 8528 u8 port_xmit_discards[0x10]; 8529 8530 u8 port_xmit_constraint_errors[0x8]; 8531 u8 port_rcv_constraint_errors[0x8]; 8532 u8 reserved_0[0x8]; 8533 u8 local_link_integrity_errors[0x4]; 8534 u8 excessive_buffer_overrun_errors[0x4]; 8535 8536 u8 reserved_1[0x10]; 8537 u8 vl_15_dropped[0x10]; 8538 8539 u8 port_xmit_data[0x20]; 8540 8541 u8 port_rcv_data[0x20]; 8542 8543 u8 port_xmit_pkts[0x20]; 8544 8545 u8 port_rcv_pkts[0x20]; 8546 8547 u8 port_xmit_wait[0x20]; 8548 8549 u8 reserved_2[0x680]; 8550 }; 8551 8552 struct mlx5_ifc_phrr_reg_bits { 8553 u8 clr[0x1]; 8554 u8 reserved_0[0x7]; 8555 u8 local_port[0x8]; 8556 u8 reserved_1[0x10]; 8557 8558 u8 hist_group[0x8]; 8559 u8 reserved_2[0x10]; 8560 u8 hist_id[0x8]; 8561 8562 u8 reserved_3[0x40]; 8563 8564 u8 time_since_last_clear_high[0x20]; 8565 8566 u8 time_since_last_clear_low[0x20]; 8567 8568 u8 bin[10][0x20]; 8569 }; 8570 8571 struct mlx5_ifc_phbr_for_prio_reg_bits { 8572 u8 reserved_0[0x18]; 8573 u8 prio[0x8]; 8574 }; 8575 8576 struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8577 u8 reserved_0[0x18]; 8578 u8 tclass[0x8]; 8579 }; 8580 8581 struct mlx5_ifc_phbr_binding_reg_bits { 8582 u8 opcode[0x4]; 8583 u8 reserved_0[0x4]; 8584 u8 local_port[0x8]; 8585 u8 pnat[0x2]; 8586 u8 reserved_1[0xe]; 8587 8588 u8 hist_group[0x8]; 8589 u8 reserved_2[0x10]; 8590 u8 hist_id[0x8]; 8591 8592 u8 reserved_3[0x10]; 8593 u8 hist_type[0x10]; 8594 8595 u8 hist_parameters[0x20]; 8596 8597 u8 hist_min_value[0x20]; 8598 8599 u8 hist_max_value[0x20]; 8600 8601 u8 sample_time[0x20]; 8602 }; 8603 8604 enum { 8605 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 8606 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 8607 }; 8608 8609 struct mlx5_ifc_pfcc_reg_bits { 8610 u8 dcbx_operation_type[0x2]; 8611 u8 cap_local_admin[0x1]; 8612 u8 cap_remote_admin[0x1]; 8613 u8 reserved_0[0x4]; 8614 u8 local_port[0x8]; 8615 u8 pnat[0x2]; 8616 u8 reserved_1[0xc]; 8617 u8 shl_cap[0x1]; 8618 u8 shl_opr[0x1]; 8619 8620 u8 ppan[0x4]; 8621 u8 reserved_2[0x4]; 8622 u8 prio_mask_tx[0x8]; 8623 u8 reserved_3[0x8]; 8624 u8 prio_mask_rx[0x8]; 8625 8626 u8 pptx[0x1]; 8627 u8 aptx[0x1]; 8628 u8 reserved_4[0x6]; 8629 u8 pfctx[0x8]; 8630 u8 reserved_5[0x8]; 8631 u8 cbftx[0x8]; 8632 8633 u8 pprx[0x1]; 8634 u8 aprx[0x1]; 8635 u8 reserved_6[0x6]; 8636 u8 pfcrx[0x8]; 8637 u8 reserved_7[0x8]; 8638 u8 cbfrx[0x8]; 8639 8640 u8 device_stall_minor_watermark[0x10]; 8641 u8 device_stall_critical_watermark[0x10]; 8642 8643 u8 reserved_8[0x60]; 8644 }; 8645 8646 struct mlx5_ifc_pelc_reg_bits { 8647 u8 op[0x4]; 8648 u8 reserved_0[0x4]; 8649 u8 local_port[0x8]; 8650 u8 reserved_1[0x10]; 8651 8652 u8 op_admin[0x8]; 8653 u8 op_capability[0x8]; 8654 u8 op_request[0x8]; 8655 u8 op_active[0x8]; 8656 8657 u8 admin[0x40]; 8658 8659 u8 capability[0x40]; 8660 8661 u8 request[0x40]; 8662 8663 u8 active[0x40]; 8664 8665 u8 reserved_2[0x80]; 8666 }; 8667 8668 struct mlx5_ifc_peir_reg_bits { 8669 u8 reserved_0[0x8]; 8670 u8 local_port[0x8]; 8671 u8 reserved_1[0x10]; 8672 8673 u8 reserved_2[0xc]; 8674 u8 error_count[0x4]; 8675 u8 reserved_3[0x10]; 8676 8677 u8 reserved_4[0xc]; 8678 u8 lane[0x4]; 8679 u8 reserved_5[0x8]; 8680 u8 error_type[0x8]; 8681 }; 8682 8683 struct mlx5_ifc_qcam_access_reg_cap_mask { 8684 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8685 u8 qpdpm[0x1]; 8686 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8687 u8 qdpm[0x1]; 8688 u8 qpts[0x1]; 8689 u8 qcap[0x1]; 8690 u8 qcam_access_reg_cap_mask_0[0x1]; 8691 }; 8692 8693 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8694 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8695 u8 qpts_trust_both[0x1]; 8696 }; 8697 8698 struct mlx5_ifc_qcam_reg_bits { 8699 u8 reserved_at_0[0x8]; 8700 u8 feature_group[0x8]; 8701 u8 reserved_at_10[0x8]; 8702 u8 access_reg_group[0x8]; 8703 u8 reserved_at_20[0x20]; 8704 8705 union { 8706 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8707 u8 reserved_at_0[0x80]; 8708 } qos_access_reg_cap_mask; 8709 8710 u8 reserved_at_c0[0x80]; 8711 8712 union { 8713 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8714 u8 reserved_at_0[0x80]; 8715 } qos_feature_cap_mask; 8716 8717 u8 reserved_at_1c0[0x80]; 8718 }; 8719 8720 struct mlx5_ifc_pcam_enhanced_features_bits { 8721 u8 reserved_at_0[0x6d]; 8722 u8 rx_icrc_encapsulated_counter[0x1]; 8723 u8 reserved_at_6e[0x4]; 8724 u8 ptys_extended_ethernet[0x1]; 8725 u8 reserved_at_73[0x3]; 8726 u8 pfcc_mask[0x1]; 8727 u8 reserved_at_77[0x3]; 8728 u8 per_lane_error_counters[0x1]; 8729 u8 rx_buffer_fullness_counters[0x1]; 8730 u8 ptys_connector_type[0x1]; 8731 u8 reserved_at_7d[0x1]; 8732 u8 ppcnt_discard_group[0x1]; 8733 u8 ppcnt_statistical_group[0x1]; 8734 }; 8735 8736 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8737 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8738 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8739 8740 u8 reserved_at_40[0xe]; 8741 u8 pddr[0x1]; 8742 u8 reserved_at_4f[0xd]; 8743 8744 u8 pplm[0x1]; 8745 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8746 8747 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8748 u8 pbmc[0x1]; 8749 u8 pptb[0x1]; 8750 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8751 u8 ppcnt[0x1]; 8752 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8753 }; 8754 8755 struct mlx5_ifc_pcam_reg_bits { 8756 u8 reserved_at_0[0x8]; 8757 u8 feature_group[0x8]; 8758 u8 reserved_at_10[0x8]; 8759 u8 access_reg_group[0x8]; 8760 8761 u8 reserved_at_20[0x20]; 8762 8763 union { 8764 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8765 u8 reserved_at_0[0x80]; 8766 } port_access_reg_cap_mask; 8767 8768 u8 reserved_at_c0[0x80]; 8769 8770 union { 8771 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8772 u8 reserved_at_0[0x80]; 8773 } feature_cap_mask; 8774 8775 u8 reserved_at_1c0[0xc0]; 8776 }; 8777 8778 struct mlx5_ifc_mcam_enhanced_features_bits { 8779 u8 reserved_at_0[0x6e]; 8780 u8 pcie_status_and_power[0x1]; 8781 u8 reserved_at_111[0x10]; 8782 u8 pcie_performance_group[0x1]; 8783 }; 8784 8785 struct mlx5_ifc_mcam_access_reg_bits { 8786 u8 reserved_at_0[0x1c]; 8787 u8 mcda[0x1]; 8788 u8 mcc[0x1]; 8789 u8 mcqi[0x1]; 8790 u8 reserved_at_1f[0x1]; 8791 8792 u8 regs_95_to_64[0x20]; 8793 u8 regs_63_to_32[0x20]; 8794 u8 regs_31_to_0[0x20]; 8795 }; 8796 8797 struct mlx5_ifc_mcam_reg_bits { 8798 u8 reserved_at_0[0x8]; 8799 u8 feature_group[0x8]; 8800 u8 reserved_at_10[0x8]; 8801 u8 access_reg_group[0x8]; 8802 8803 u8 reserved_at_20[0x20]; 8804 8805 union { 8806 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8807 u8 reserved_at_0[0x80]; 8808 } mng_access_reg_cap_mask; 8809 8810 u8 reserved_at_c0[0x80]; 8811 8812 union { 8813 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8814 u8 reserved_at_0[0x80]; 8815 } mng_feature_cap_mask; 8816 8817 u8 reserved_at_1c0[0x80]; 8818 }; 8819 8820 struct mlx5_ifc_pcap_reg_bits { 8821 u8 reserved_0[0x8]; 8822 u8 local_port[0x8]; 8823 u8 reserved_1[0x10]; 8824 8825 u8 port_capability_mask[4][0x20]; 8826 }; 8827 8828 struct mlx5_ifc_pbmc_reg_bits { 8829 u8 reserved_at_0[0x8]; 8830 u8 local_port[0x8]; 8831 u8 reserved_at_10[0x10]; 8832 8833 u8 xoff_timer_value[0x10]; 8834 u8 xoff_refresh[0x10]; 8835 8836 u8 reserved_at_40[0x9]; 8837 u8 fullness_threshold[0x7]; 8838 u8 port_buffer_size[0x10]; 8839 8840 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8841 8842 u8 reserved_at_2e0[0x40]; 8843 }; 8844 8845 struct mlx5_ifc_paos_reg_bits { 8846 u8 swid[0x8]; 8847 u8 local_port[0x8]; 8848 u8 reserved_0[0x4]; 8849 u8 admin_status[0x4]; 8850 u8 reserved_1[0x4]; 8851 u8 oper_status[0x4]; 8852 8853 u8 ase[0x1]; 8854 u8 ee[0x1]; 8855 u8 reserved_2[0x1c]; 8856 u8 e[0x2]; 8857 8858 u8 reserved_3[0x40]; 8859 }; 8860 8861 struct mlx5_ifc_pamp_reg_bits { 8862 u8 reserved_0[0x8]; 8863 u8 opamp_group[0x8]; 8864 u8 reserved_1[0xc]; 8865 u8 opamp_group_type[0x4]; 8866 8867 u8 start_index[0x10]; 8868 u8 reserved_2[0x4]; 8869 u8 num_of_indices[0xc]; 8870 8871 u8 index_data[18][0x10]; 8872 }; 8873 8874 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 8875 u8 llr_rx_cells_high[0x20]; 8876 8877 u8 llr_rx_cells_low[0x20]; 8878 8879 u8 llr_rx_error_high[0x20]; 8880 8881 u8 llr_rx_error_low[0x20]; 8882 8883 u8 llr_rx_crc_error_high[0x20]; 8884 8885 u8 llr_rx_crc_error_low[0x20]; 8886 8887 u8 llr_tx_cells_high[0x20]; 8888 8889 u8 llr_tx_cells_low[0x20]; 8890 8891 u8 llr_tx_ret_cells_high[0x20]; 8892 8893 u8 llr_tx_ret_cells_low[0x20]; 8894 8895 u8 llr_tx_ret_events_high[0x20]; 8896 8897 u8 llr_tx_ret_events_low[0x20]; 8898 8899 u8 reserved_0[0x640]; 8900 }; 8901 8902 struct mlx5_ifc_mtmp_reg_bits { 8903 u8 i[0x1]; 8904 u8 reserved_at_1[0x18]; 8905 u8 sensor_index[0x7]; 8906 8907 u8 reserved_at_20[0x10]; 8908 u8 temperature[0x10]; 8909 8910 u8 mte[0x1]; 8911 u8 mtr[0x1]; 8912 u8 reserved_at_42[0x0e]; 8913 u8 max_temperature[0x10]; 8914 8915 u8 tee[0x2]; 8916 u8 reserved_at_62[0x0e]; 8917 u8 temperature_threshold_hi[0x10]; 8918 8919 u8 reserved_at_80[0x10]; 8920 u8 temperature_threshold_lo[0x10]; 8921 8922 u8 reserved_at_100[0x20]; 8923 8924 u8 sensor_name[0x40]; 8925 }; 8926 8927 struct mlx5_ifc_lane_2_module_mapping_bits { 8928 u8 reserved_0[0x6]; 8929 u8 rx_lane[0x2]; 8930 u8 reserved_1[0x6]; 8931 u8 tx_lane[0x2]; 8932 u8 reserved_2[0x8]; 8933 u8 module[0x8]; 8934 }; 8935 8936 struct mlx5_ifc_eth_per_traffic_class_layout_bits { 8937 u8 transmit_queue_high[0x20]; 8938 8939 u8 transmit_queue_low[0x20]; 8940 8941 u8 reserved_0[0x780]; 8942 }; 8943 8944 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 8945 u8 no_buffer_discard_uc_high[0x20]; 8946 8947 u8 no_buffer_discard_uc_low[0x20]; 8948 8949 u8 wred_discard_high[0x20]; 8950 8951 u8 wred_discard_low[0x20]; 8952 8953 u8 reserved_0[0x740]; 8954 }; 8955 8956 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 8957 u8 rx_octets_high[0x20]; 8958 8959 u8 rx_octets_low[0x20]; 8960 8961 u8 reserved_0[0xc0]; 8962 8963 u8 rx_frames_high[0x20]; 8964 8965 u8 rx_frames_low[0x20]; 8966 8967 u8 tx_octets_high[0x20]; 8968 8969 u8 tx_octets_low[0x20]; 8970 8971 u8 reserved_1[0xc0]; 8972 8973 u8 tx_frames_high[0x20]; 8974 8975 u8 tx_frames_low[0x20]; 8976 8977 u8 rx_pause_high[0x20]; 8978 8979 u8 rx_pause_low[0x20]; 8980 8981 u8 rx_pause_duration_high[0x20]; 8982 8983 u8 rx_pause_duration_low[0x20]; 8984 8985 u8 tx_pause_high[0x20]; 8986 8987 u8 tx_pause_low[0x20]; 8988 8989 u8 tx_pause_duration_high[0x20]; 8990 8991 u8 tx_pause_duration_low[0x20]; 8992 8993 u8 rx_pause_transition_high[0x20]; 8994 8995 u8 rx_pause_transition_low[0x20]; 8996 8997 u8 rx_discards_high[0x20]; 8998 8999 u8 rx_discards_low[0x20]; 9000 9001 u8 device_stall_minor_watermark_cnt_high[0x20]; 9002 9003 u8 device_stall_minor_watermark_cnt_low[0x20]; 9004 9005 u8 device_stall_critical_watermark_cnt_high[0x20]; 9006 9007 u8 device_stall_critical_watermark_cnt_low[0x20]; 9008 9009 u8 reserved_2[0x340]; 9010 }; 9011 9012 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 9013 u8 port_transmit_wait_high[0x20]; 9014 9015 u8 port_transmit_wait_low[0x20]; 9016 9017 u8 ecn_marked_high[0x20]; 9018 9019 u8 ecn_marked_low[0x20]; 9020 9021 u8 no_buffer_discard_mc_high[0x20]; 9022 9023 u8 no_buffer_discard_mc_low[0x20]; 9024 9025 u8 rx_ebp_high[0x20]; 9026 9027 u8 rx_ebp_low[0x20]; 9028 9029 u8 tx_ebp_high[0x20]; 9030 9031 u8 tx_ebp_low[0x20]; 9032 9033 u8 rx_buffer_almost_full_high[0x20]; 9034 9035 u8 rx_buffer_almost_full_low[0x20]; 9036 9037 u8 rx_buffer_full_high[0x20]; 9038 9039 u8 rx_buffer_full_low[0x20]; 9040 9041 u8 rx_icrc_encapsulated_high[0x20]; 9042 9043 u8 rx_icrc_encapsulated_low[0x20]; 9044 9045 u8 reserved_0[0x80]; 9046 9047 u8 tx_stats_pkts64octets_high[0x20]; 9048 9049 u8 tx_stats_pkts64octets_low[0x20]; 9050 9051 u8 tx_stats_pkts65to127octets_high[0x20]; 9052 9053 u8 tx_stats_pkts65to127octets_low[0x20]; 9054 9055 u8 tx_stats_pkts128to255octets_high[0x20]; 9056 9057 u8 tx_stats_pkts128to255octets_low[0x20]; 9058 9059 u8 tx_stats_pkts256to511octets_high[0x20]; 9060 9061 u8 tx_stats_pkts256to511octets_low[0x20]; 9062 9063 u8 tx_stats_pkts512to1023octets_high[0x20]; 9064 9065 u8 tx_stats_pkts512to1023octets_low[0x20]; 9066 9067 u8 tx_stats_pkts1024to1518octets_high[0x20]; 9068 9069 u8 tx_stats_pkts1024to1518octets_low[0x20]; 9070 9071 u8 tx_stats_pkts1519to2047octets_high[0x20]; 9072 9073 u8 tx_stats_pkts1519to2047octets_low[0x20]; 9074 9075 u8 tx_stats_pkts2048to4095octets_high[0x20]; 9076 9077 u8 tx_stats_pkts2048to4095octets_low[0x20]; 9078 9079 u8 tx_stats_pkts4096to8191octets_high[0x20]; 9080 9081 u8 tx_stats_pkts4096to8191octets_low[0x20]; 9082 9083 u8 tx_stats_pkts8192to10239octets_high[0x20]; 9084 9085 u8 tx_stats_pkts8192to10239octets_low[0x20]; 9086 9087 u8 reserved_1[0x2C0]; 9088 }; 9089 9090 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 9091 u8 a_frames_transmitted_ok_high[0x20]; 9092 9093 u8 a_frames_transmitted_ok_low[0x20]; 9094 9095 u8 a_frames_received_ok_high[0x20]; 9096 9097 u8 a_frames_received_ok_low[0x20]; 9098 9099 u8 a_frame_check_sequence_errors_high[0x20]; 9100 9101 u8 a_frame_check_sequence_errors_low[0x20]; 9102 9103 u8 a_alignment_errors_high[0x20]; 9104 9105 u8 a_alignment_errors_low[0x20]; 9106 9107 u8 a_octets_transmitted_ok_high[0x20]; 9108 9109 u8 a_octets_transmitted_ok_low[0x20]; 9110 9111 u8 a_octets_received_ok_high[0x20]; 9112 9113 u8 a_octets_received_ok_low[0x20]; 9114 9115 u8 a_multicast_frames_xmitted_ok_high[0x20]; 9116 9117 u8 a_multicast_frames_xmitted_ok_low[0x20]; 9118 9119 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 9120 9121 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 9122 9123 u8 a_multicast_frames_received_ok_high[0x20]; 9124 9125 u8 a_multicast_frames_received_ok_low[0x20]; 9126 9127 u8 a_broadcast_frames_recieved_ok_high[0x20]; 9128 9129 u8 a_broadcast_frames_recieved_ok_low[0x20]; 9130 9131 u8 a_in_range_length_errors_high[0x20]; 9132 9133 u8 a_in_range_length_errors_low[0x20]; 9134 9135 u8 a_out_of_range_length_field_high[0x20]; 9136 9137 u8 a_out_of_range_length_field_low[0x20]; 9138 9139 u8 a_frame_too_long_errors_high[0x20]; 9140 9141 u8 a_frame_too_long_errors_low[0x20]; 9142 9143 u8 a_symbol_error_during_carrier_high[0x20]; 9144 9145 u8 a_symbol_error_during_carrier_low[0x20]; 9146 9147 u8 a_mac_control_frames_transmitted_high[0x20]; 9148 9149 u8 a_mac_control_frames_transmitted_low[0x20]; 9150 9151 u8 a_mac_control_frames_received_high[0x20]; 9152 9153 u8 a_mac_control_frames_received_low[0x20]; 9154 9155 u8 a_unsupported_opcodes_received_high[0x20]; 9156 9157 u8 a_unsupported_opcodes_received_low[0x20]; 9158 9159 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 9160 9161 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 9162 9163 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 9164 9165 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 9166 9167 u8 reserved_0[0x300]; 9168 }; 9169 9170 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 9171 u8 dot3stats_alignment_errors_high[0x20]; 9172 9173 u8 dot3stats_alignment_errors_low[0x20]; 9174 9175 u8 dot3stats_fcs_errors_high[0x20]; 9176 9177 u8 dot3stats_fcs_errors_low[0x20]; 9178 9179 u8 dot3stats_single_collision_frames_high[0x20]; 9180 9181 u8 dot3stats_single_collision_frames_low[0x20]; 9182 9183 u8 dot3stats_multiple_collision_frames_high[0x20]; 9184 9185 u8 dot3stats_multiple_collision_frames_low[0x20]; 9186 9187 u8 dot3stats_sqe_test_errors_high[0x20]; 9188 9189 u8 dot3stats_sqe_test_errors_low[0x20]; 9190 9191 u8 dot3stats_deferred_transmissions_high[0x20]; 9192 9193 u8 dot3stats_deferred_transmissions_low[0x20]; 9194 9195 u8 dot3stats_late_collisions_high[0x20]; 9196 9197 u8 dot3stats_late_collisions_low[0x20]; 9198 9199 u8 dot3stats_excessive_collisions_high[0x20]; 9200 9201 u8 dot3stats_excessive_collisions_low[0x20]; 9202 9203 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 9204 9205 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 9206 9207 u8 dot3stats_carrier_sense_errors_high[0x20]; 9208 9209 u8 dot3stats_carrier_sense_errors_low[0x20]; 9210 9211 u8 dot3stats_frame_too_longs_high[0x20]; 9212 9213 u8 dot3stats_frame_too_longs_low[0x20]; 9214 9215 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 9216 9217 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 9218 9219 u8 dot3stats_symbol_errors_high[0x20]; 9220 9221 u8 dot3stats_symbol_errors_low[0x20]; 9222 9223 u8 dot3control_in_unknown_opcodes_high[0x20]; 9224 9225 u8 dot3control_in_unknown_opcodes_low[0x20]; 9226 9227 u8 dot3in_pause_frames_high[0x20]; 9228 9229 u8 dot3in_pause_frames_low[0x20]; 9230 9231 u8 dot3out_pause_frames_high[0x20]; 9232 9233 u8 dot3out_pause_frames_low[0x20]; 9234 9235 u8 reserved_0[0x3c0]; 9236 }; 9237 9238 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 9239 u8 if_in_octets_high[0x20]; 9240 9241 u8 if_in_octets_low[0x20]; 9242 9243 u8 if_in_ucast_pkts_high[0x20]; 9244 9245 u8 if_in_ucast_pkts_low[0x20]; 9246 9247 u8 if_in_discards_high[0x20]; 9248 9249 u8 if_in_discards_low[0x20]; 9250 9251 u8 if_in_errors_high[0x20]; 9252 9253 u8 if_in_errors_low[0x20]; 9254 9255 u8 if_in_unknown_protos_high[0x20]; 9256 9257 u8 if_in_unknown_protos_low[0x20]; 9258 9259 u8 if_out_octets_high[0x20]; 9260 9261 u8 if_out_octets_low[0x20]; 9262 9263 u8 if_out_ucast_pkts_high[0x20]; 9264 9265 u8 if_out_ucast_pkts_low[0x20]; 9266 9267 u8 if_out_discards_high[0x20]; 9268 9269 u8 if_out_discards_low[0x20]; 9270 9271 u8 if_out_errors_high[0x20]; 9272 9273 u8 if_out_errors_low[0x20]; 9274 9275 u8 if_in_multicast_pkts_high[0x20]; 9276 9277 u8 if_in_multicast_pkts_low[0x20]; 9278 9279 u8 if_in_broadcast_pkts_high[0x20]; 9280 9281 u8 if_in_broadcast_pkts_low[0x20]; 9282 9283 u8 if_out_multicast_pkts_high[0x20]; 9284 9285 u8 if_out_multicast_pkts_low[0x20]; 9286 9287 u8 if_out_broadcast_pkts_high[0x20]; 9288 9289 u8 if_out_broadcast_pkts_low[0x20]; 9290 9291 u8 reserved_0[0x480]; 9292 }; 9293 9294 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 9295 u8 ether_stats_drop_events_high[0x20]; 9296 9297 u8 ether_stats_drop_events_low[0x20]; 9298 9299 u8 ether_stats_octets_high[0x20]; 9300 9301 u8 ether_stats_octets_low[0x20]; 9302 9303 u8 ether_stats_pkts_high[0x20]; 9304 9305 u8 ether_stats_pkts_low[0x20]; 9306 9307 u8 ether_stats_broadcast_pkts_high[0x20]; 9308 9309 u8 ether_stats_broadcast_pkts_low[0x20]; 9310 9311 u8 ether_stats_multicast_pkts_high[0x20]; 9312 9313 u8 ether_stats_multicast_pkts_low[0x20]; 9314 9315 u8 ether_stats_crc_align_errors_high[0x20]; 9316 9317 u8 ether_stats_crc_align_errors_low[0x20]; 9318 9319 u8 ether_stats_undersize_pkts_high[0x20]; 9320 9321 u8 ether_stats_undersize_pkts_low[0x20]; 9322 9323 u8 ether_stats_oversize_pkts_high[0x20]; 9324 9325 u8 ether_stats_oversize_pkts_low[0x20]; 9326 9327 u8 ether_stats_fragments_high[0x20]; 9328 9329 u8 ether_stats_fragments_low[0x20]; 9330 9331 u8 ether_stats_jabbers_high[0x20]; 9332 9333 u8 ether_stats_jabbers_low[0x20]; 9334 9335 u8 ether_stats_collisions_high[0x20]; 9336 9337 u8 ether_stats_collisions_low[0x20]; 9338 9339 u8 ether_stats_pkts64octets_high[0x20]; 9340 9341 u8 ether_stats_pkts64octets_low[0x20]; 9342 9343 u8 ether_stats_pkts65to127octets_high[0x20]; 9344 9345 u8 ether_stats_pkts65to127octets_low[0x20]; 9346 9347 u8 ether_stats_pkts128to255octets_high[0x20]; 9348 9349 u8 ether_stats_pkts128to255octets_low[0x20]; 9350 9351 u8 ether_stats_pkts256to511octets_high[0x20]; 9352 9353 u8 ether_stats_pkts256to511octets_low[0x20]; 9354 9355 u8 ether_stats_pkts512to1023octets_high[0x20]; 9356 9357 u8 ether_stats_pkts512to1023octets_low[0x20]; 9358 9359 u8 ether_stats_pkts1024to1518octets_high[0x20]; 9360 9361 u8 ether_stats_pkts1024to1518octets_low[0x20]; 9362 9363 u8 ether_stats_pkts1519to2047octets_high[0x20]; 9364 9365 u8 ether_stats_pkts1519to2047octets_low[0x20]; 9366 9367 u8 ether_stats_pkts2048to4095octets_high[0x20]; 9368 9369 u8 ether_stats_pkts2048to4095octets_low[0x20]; 9370 9371 u8 ether_stats_pkts4096to8191octets_high[0x20]; 9372 9373 u8 ether_stats_pkts4096to8191octets_low[0x20]; 9374 9375 u8 ether_stats_pkts8192to10239octets_high[0x20]; 9376 9377 u8 ether_stats_pkts8192to10239octets_low[0x20]; 9378 9379 u8 reserved_0[0x280]; 9380 }; 9381 9382 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 9383 u8 symbol_error_counter[0x10]; 9384 u8 link_error_recovery_counter[0x8]; 9385 u8 link_downed_counter[0x8]; 9386 9387 u8 port_rcv_errors[0x10]; 9388 u8 port_rcv_remote_physical_errors[0x10]; 9389 9390 u8 port_rcv_switch_relay_errors[0x10]; 9391 u8 port_xmit_discards[0x10]; 9392 9393 u8 port_xmit_constraint_errors[0x8]; 9394 u8 port_rcv_constraint_errors[0x8]; 9395 u8 reserved_0[0x8]; 9396 u8 local_link_integrity_errors[0x4]; 9397 u8 excessive_buffer_overrun_errors[0x4]; 9398 9399 u8 reserved_1[0x10]; 9400 u8 vl_15_dropped[0x10]; 9401 9402 u8 port_xmit_data[0x20]; 9403 9404 u8 port_rcv_data[0x20]; 9405 9406 u8 port_xmit_pkts[0x20]; 9407 9408 u8 port_rcv_pkts[0x20]; 9409 9410 u8 port_xmit_wait[0x20]; 9411 9412 u8 reserved_2[0x680]; 9413 }; 9414 9415 struct mlx5_ifc_trc_tlb_reg_bits { 9416 u8 reserved_0[0x80]; 9417 9418 u8 tlb_addr[0][0x40]; 9419 }; 9420 9421 struct mlx5_ifc_trc_read_fifo_reg_bits { 9422 u8 reserved_0[0x10]; 9423 u8 requested_event_num[0x10]; 9424 9425 u8 reserved_1[0x20]; 9426 9427 u8 reserved_2[0x10]; 9428 u8 acual_event_num[0x10]; 9429 9430 u8 reserved_3[0x20]; 9431 9432 u8 event[0][0x40]; 9433 }; 9434 9435 struct mlx5_ifc_trc_lock_reg_bits { 9436 u8 reserved_0[0x1f]; 9437 u8 lock[0x1]; 9438 9439 u8 reserved_1[0x60]; 9440 }; 9441 9442 struct mlx5_ifc_trc_filter_reg_bits { 9443 u8 status[0x1]; 9444 u8 reserved_0[0xf]; 9445 u8 filter_index[0x10]; 9446 9447 u8 reserved_1[0x20]; 9448 9449 u8 filter_val[0x20]; 9450 9451 u8 reserved_2[0x1a0]; 9452 }; 9453 9454 struct mlx5_ifc_trc_event_reg_bits { 9455 u8 status[0x1]; 9456 u8 reserved_0[0xf]; 9457 u8 event_index[0x10]; 9458 9459 u8 reserved_1[0x20]; 9460 9461 u8 event_id[0x20]; 9462 9463 u8 event_selector_val[0x10]; 9464 u8 event_selector_size[0x10]; 9465 9466 u8 reserved_2[0x180]; 9467 }; 9468 9469 struct mlx5_ifc_trc_conf_reg_bits { 9470 u8 limit_en[0x1]; 9471 u8 reserved_0[0x3]; 9472 u8 dump_mode[0x4]; 9473 u8 reserved_1[0x15]; 9474 u8 state[0x3]; 9475 9476 u8 reserved_2[0x20]; 9477 9478 u8 limit_event_index[0x20]; 9479 9480 u8 mkey[0x20]; 9481 9482 u8 fifo_ready_ev_num[0x20]; 9483 9484 u8 reserved_3[0x160]; 9485 }; 9486 9487 struct mlx5_ifc_trc_cap_reg_bits { 9488 u8 reserved_0[0x18]; 9489 u8 dump_mode[0x8]; 9490 9491 u8 reserved_1[0x20]; 9492 9493 u8 num_of_events[0x10]; 9494 u8 num_of_filters[0x10]; 9495 9496 u8 fifo_size[0x20]; 9497 9498 u8 tlb_size[0x10]; 9499 u8 event_size[0x10]; 9500 9501 u8 reserved_2[0x160]; 9502 }; 9503 9504 struct mlx5_ifc_set_node_in_bits { 9505 u8 node_description[64][0x8]; 9506 }; 9507 9508 struct mlx5_ifc_register_power_settings_bits { 9509 u8 reserved_0[0x18]; 9510 u8 power_settings_level[0x8]; 9511 9512 u8 reserved_1[0x60]; 9513 }; 9514 9515 struct mlx5_ifc_register_host_endianess_bits { 9516 u8 he[0x1]; 9517 u8 reserved_0[0x1f]; 9518 9519 u8 reserved_1[0x60]; 9520 }; 9521 9522 struct mlx5_ifc_register_diag_buffer_ctrl_bits { 9523 u8 physical_address[0x40]; 9524 }; 9525 9526 struct mlx5_ifc_qtct_reg_bits { 9527 u8 operation_type[0x2]; 9528 u8 cap_local_admin[0x1]; 9529 u8 cap_remote_admin[0x1]; 9530 u8 reserved_0[0x4]; 9531 u8 port_number[0x8]; 9532 u8 reserved_1[0xd]; 9533 u8 prio[0x3]; 9534 9535 u8 reserved_2[0x1d]; 9536 u8 tclass[0x3]; 9537 }; 9538 9539 struct mlx5_ifc_qpdp_reg_bits { 9540 u8 reserved_0[0x8]; 9541 u8 port_number[0x8]; 9542 u8 reserved_1[0x10]; 9543 9544 u8 reserved_2[0x1d]; 9545 u8 pprio[0x3]; 9546 }; 9547 9548 struct mlx5_ifc_port_info_ro_fields_param_bits { 9549 u8 reserved_0[0x8]; 9550 u8 port[0x8]; 9551 u8 max_gid[0x10]; 9552 9553 u8 reserved_1[0x20]; 9554 9555 u8 port_guid[0x40]; 9556 }; 9557 9558 struct mlx5_ifc_nvqc_reg_bits { 9559 u8 type[0x20]; 9560 9561 u8 reserved_0[0x18]; 9562 u8 version[0x4]; 9563 u8 reserved_1[0x2]; 9564 u8 support_wr[0x1]; 9565 u8 support_rd[0x1]; 9566 }; 9567 9568 struct mlx5_ifc_nvia_reg_bits { 9569 u8 reserved_0[0x1d]; 9570 u8 target[0x3]; 9571 9572 u8 reserved_1[0x20]; 9573 }; 9574 9575 struct mlx5_ifc_nvdi_reg_bits { 9576 struct mlx5_ifc_config_item_bits configuration_item_header; 9577 }; 9578 9579 struct mlx5_ifc_nvda_reg_bits { 9580 struct mlx5_ifc_config_item_bits configuration_item_header; 9581 9582 u8 configuration_item_data[0x20]; 9583 }; 9584 9585 struct mlx5_ifc_node_info_ro_fields_param_bits { 9586 u8 system_image_guid[0x40]; 9587 9588 u8 reserved_0[0x40]; 9589 9590 u8 node_guid[0x40]; 9591 9592 u8 reserved_1[0x10]; 9593 u8 max_pkey[0x10]; 9594 9595 u8 reserved_2[0x20]; 9596 }; 9597 9598 struct mlx5_ifc_ets_tcn_config_reg_bits { 9599 u8 g[0x1]; 9600 u8 b[0x1]; 9601 u8 r[0x1]; 9602 u8 reserved_0[0x9]; 9603 u8 group[0x4]; 9604 u8 reserved_1[0x9]; 9605 u8 bw_allocation[0x7]; 9606 9607 u8 reserved_2[0xc]; 9608 u8 max_bw_units[0x4]; 9609 u8 reserved_3[0x8]; 9610 u8 max_bw_value[0x8]; 9611 }; 9612 9613 struct mlx5_ifc_ets_global_config_reg_bits { 9614 u8 reserved_0[0x2]; 9615 u8 r[0x1]; 9616 u8 reserved_1[0x1d]; 9617 9618 u8 reserved_2[0xc]; 9619 u8 max_bw_units[0x4]; 9620 u8 reserved_3[0x8]; 9621 u8 max_bw_value[0x8]; 9622 }; 9623 9624 struct mlx5_ifc_qetc_reg_bits { 9625 u8 reserved_at_0[0x8]; 9626 u8 port_number[0x8]; 9627 u8 reserved_at_10[0x30]; 9628 9629 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9630 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9631 }; 9632 9633 struct mlx5_ifc_nodnic_mac_filters_bits { 9634 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 9635 9636 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 9637 9638 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 9639 9640 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 9641 9642 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 9643 9644 u8 reserved_0[0xc0]; 9645 }; 9646 9647 struct mlx5_ifc_nodnic_gid_filters_bits { 9648 u8 mgid_filter0[16][0x8]; 9649 9650 u8 mgid_filter1[16][0x8]; 9651 9652 u8 mgid_filter2[16][0x8]; 9653 9654 u8 mgid_filter3[16][0x8]; 9655 }; 9656 9657 enum { 9658 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 9659 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 9660 }; 9661 9662 enum { 9663 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 9664 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 9665 }; 9666 9667 struct mlx5_ifc_nodnic_config_reg_bits { 9668 u8 no_dram_nic_revision[0x8]; 9669 u8 hardware_format[0x8]; 9670 u8 support_receive_filter[0x1]; 9671 u8 support_promisc_filter[0x1]; 9672 u8 support_promisc_multicast_filter[0x1]; 9673 u8 reserved_0[0x2]; 9674 u8 log_working_buffer_size[0x3]; 9675 u8 log_pkey_table_size[0x4]; 9676 u8 reserved_1[0x3]; 9677 u8 num_ports[0x1]; 9678 9679 u8 reserved_2[0x2]; 9680 u8 log_max_ring_size[0x6]; 9681 u8 reserved_3[0x18]; 9682 9683 u8 lkey[0x20]; 9684 9685 u8 cqe_format[0x4]; 9686 u8 reserved_4[0x1c]; 9687 9688 u8 node_guid[0x40]; 9689 9690 u8 reserved_5[0x740]; 9691 9692 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 9693 9694 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 9695 }; 9696 9697 struct mlx5_ifc_vlan_layout_bits { 9698 u8 reserved_0[0x14]; 9699 u8 vlan[0xc]; 9700 9701 u8 reserved_1[0x20]; 9702 }; 9703 9704 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9705 u8 reserved_0[0x20]; 9706 9707 u8 mkey[0x20]; 9708 9709 u8 addressh_63_32[0x20]; 9710 9711 u8 addressl_31_0[0x20]; 9712 }; 9713 9714 struct mlx5_ifc_ud_adrs_vector_bits { 9715 u8 dc_key[0x40]; 9716 9717 u8 ext[0x1]; 9718 u8 reserved_0[0x7]; 9719 u8 destination_qp_dct[0x18]; 9720 9721 u8 static_rate[0x4]; 9722 u8 sl_eth_prio[0x4]; 9723 u8 fl[0x1]; 9724 u8 mlid[0x7]; 9725 u8 rlid_udp_sport[0x10]; 9726 9727 u8 reserved_1[0x20]; 9728 9729 u8 rmac_47_16[0x20]; 9730 9731 u8 rmac_15_0[0x10]; 9732 u8 tclass[0x8]; 9733 u8 hop_limit[0x8]; 9734 9735 u8 reserved_2[0x1]; 9736 u8 grh[0x1]; 9737 u8 reserved_3[0x2]; 9738 u8 src_addr_index[0x8]; 9739 u8 flow_label[0x14]; 9740 9741 u8 rgid_rip[16][0x8]; 9742 }; 9743 9744 struct mlx5_ifc_port_module_event_bits { 9745 u8 reserved_0[0x8]; 9746 u8 module[0x8]; 9747 u8 reserved_1[0xc]; 9748 u8 module_status[0x4]; 9749 9750 u8 reserved_2[0x14]; 9751 u8 error_type[0x4]; 9752 u8 reserved_3[0x8]; 9753 9754 u8 reserved_4[0xa0]; 9755 }; 9756 9757 struct mlx5_ifc_icmd_control_bits { 9758 u8 opcode[0x10]; 9759 u8 status[0x8]; 9760 u8 reserved_0[0x7]; 9761 u8 busy[0x1]; 9762 }; 9763 9764 struct mlx5_ifc_eqe_bits { 9765 u8 reserved_0[0x8]; 9766 u8 event_type[0x8]; 9767 u8 reserved_1[0x8]; 9768 u8 event_sub_type[0x8]; 9769 9770 u8 reserved_2[0xe0]; 9771 9772 union mlx5_ifc_event_auto_bits event_data; 9773 9774 u8 reserved_3[0x10]; 9775 u8 signature[0x8]; 9776 u8 reserved_4[0x7]; 9777 u8 owner[0x1]; 9778 }; 9779 9780 enum { 9781 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9782 }; 9783 9784 struct mlx5_ifc_cmd_queue_entry_bits { 9785 u8 type[0x8]; 9786 u8 reserved_0[0x18]; 9787 9788 u8 input_length[0x20]; 9789 9790 u8 input_mailbox_pointer_63_32[0x20]; 9791 9792 u8 input_mailbox_pointer_31_9[0x17]; 9793 u8 reserved_1[0x9]; 9794 9795 u8 command_input_inline_data[16][0x8]; 9796 9797 u8 command_output_inline_data[16][0x8]; 9798 9799 u8 output_mailbox_pointer_63_32[0x20]; 9800 9801 u8 output_mailbox_pointer_31_9[0x17]; 9802 u8 reserved_2[0x9]; 9803 9804 u8 output_length[0x20]; 9805 9806 u8 token[0x8]; 9807 u8 signature[0x8]; 9808 u8 reserved_3[0x8]; 9809 u8 status[0x7]; 9810 u8 ownership[0x1]; 9811 }; 9812 9813 struct mlx5_ifc_cmd_out_bits { 9814 u8 status[0x8]; 9815 u8 reserved_0[0x18]; 9816 9817 u8 syndrome[0x20]; 9818 9819 u8 command_output[0x20]; 9820 }; 9821 9822 struct mlx5_ifc_cmd_in_bits { 9823 u8 opcode[0x10]; 9824 u8 reserved_0[0x10]; 9825 9826 u8 reserved_1[0x10]; 9827 u8 op_mod[0x10]; 9828 9829 u8 command[0][0x20]; 9830 }; 9831 9832 struct mlx5_ifc_cmd_if_box_bits { 9833 u8 mailbox_data[512][0x8]; 9834 9835 u8 reserved_0[0x180]; 9836 9837 u8 next_pointer_63_32[0x20]; 9838 9839 u8 next_pointer_31_10[0x16]; 9840 u8 reserved_1[0xa]; 9841 9842 u8 block_number[0x20]; 9843 9844 u8 reserved_2[0x8]; 9845 u8 token[0x8]; 9846 u8 ctrl_signature[0x8]; 9847 u8 signature[0x8]; 9848 }; 9849 9850 struct mlx5_ifc_mtt_bits { 9851 u8 ptag_63_32[0x20]; 9852 9853 u8 ptag_31_8[0x18]; 9854 u8 reserved_0[0x6]; 9855 u8 wr_en[0x1]; 9856 u8 rd_en[0x1]; 9857 }; 9858 9859 struct mlx5_ifc_tls_progress_params_bits { 9860 u8 valid[0x1]; 9861 u8 reserved_at_1[0x7]; 9862 u8 pd[0x18]; 9863 9864 u8 next_record_tcp_sn[0x20]; 9865 9866 u8 hw_resync_tcp_sn[0x20]; 9867 9868 u8 record_tracker_state[0x2]; 9869 u8 auth_state[0x2]; 9870 u8 reserved_at_64[0x4]; 9871 u8 hw_offset_record_number[0x18]; 9872 }; 9873 9874 struct mlx5_ifc_tls_static_params_bits { 9875 u8 const_2[0x2]; 9876 u8 tls_version[0x4]; 9877 u8 const_1[0x2]; 9878 u8 reserved_at_8[0x14]; 9879 u8 encryption_standard[0x4]; 9880 9881 u8 reserved_at_20[0x20]; 9882 9883 u8 initial_record_number[0x40]; 9884 9885 u8 resync_tcp_sn[0x20]; 9886 9887 u8 gcm_iv[0x20]; 9888 9889 u8 implicit_iv[0x40]; 9890 9891 u8 reserved_at_100[0x8]; 9892 u8 dek_index[0x18]; 9893 9894 u8 reserved_at_120[0xe0]; 9895 }; 9896 9897 /* Vendor Specific Capabilities, VSC */ 9898 enum { 9899 MLX5_VSC_DOMAIN_ICMD = 0x1, 9900 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 9901 MLX5_VSC_DOMAIN_SCAN_CRSPACE = 0x7, 9902 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 9903 }; 9904 9905 struct mlx5_ifc_vendor_specific_cap_bits { 9906 u8 type[0x8]; 9907 u8 length[0x8]; 9908 u8 next_pointer[0x8]; 9909 u8 capability_id[0x8]; 9910 9911 u8 status[0x3]; 9912 u8 reserved_0[0xd]; 9913 u8 space[0x10]; 9914 9915 u8 counter[0x20]; 9916 9917 u8 semaphore[0x20]; 9918 9919 u8 flag[0x1]; 9920 u8 reserved_1[0x1]; 9921 u8 address[0x1e]; 9922 9923 u8 data[0x20]; 9924 }; 9925 9926 struct mlx5_ifc_vsc_space_bits { 9927 u8 status[0x3]; 9928 u8 reserved0[0xd]; 9929 u8 space[0x10]; 9930 }; 9931 9932 struct mlx5_ifc_vsc_addr_bits { 9933 u8 flag[0x1]; 9934 u8 reserved0[0x1]; 9935 u8 address[0x1e]; 9936 }; 9937 9938 enum { 9939 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9940 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9941 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9942 }; 9943 9944 enum { 9945 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9946 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9947 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9948 }; 9949 9950 enum { 9951 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 9952 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 9953 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 9954 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 9955 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 9956 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 9957 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 9958 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 9959 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 9960 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 9961 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 9962 }; 9963 9964 struct mlx5_ifc_initial_seg_bits { 9965 u8 fw_rev_minor[0x10]; 9966 u8 fw_rev_major[0x10]; 9967 9968 u8 cmd_interface_rev[0x10]; 9969 u8 fw_rev_subminor[0x10]; 9970 9971 u8 reserved_0[0x40]; 9972 9973 u8 cmdq_phy_addr_63_32[0x20]; 9974 9975 u8 cmdq_phy_addr_31_12[0x14]; 9976 u8 reserved_1[0x2]; 9977 u8 nic_interface[0x2]; 9978 u8 log_cmdq_size[0x4]; 9979 u8 log_cmdq_stride[0x4]; 9980 9981 u8 command_doorbell_vector[0x20]; 9982 9983 u8 reserved_2[0xf00]; 9984 9985 u8 initializing[0x1]; 9986 u8 reserved_3[0x4]; 9987 u8 nic_interface_supported[0x3]; 9988 u8 reserved_4[0x18]; 9989 9990 struct mlx5_ifc_health_buffer_bits health_buffer; 9991 9992 u8 no_dram_nic_offset[0x20]; 9993 9994 u8 reserved_5[0x6de0]; 9995 9996 u8 internal_timer_h[0x20]; 9997 9998 u8 internal_timer_l[0x20]; 9999 10000 u8 reserved_6[0x20]; 10001 10002 u8 reserved_7[0x1f]; 10003 u8 clear_int[0x1]; 10004 10005 u8 health_syndrome[0x8]; 10006 u8 health_counter[0x18]; 10007 10008 u8 reserved_8[0x17fc0]; 10009 }; 10010 10011 union mlx5_ifc_icmd_interface_document_bits { 10012 struct mlx5_ifc_fw_version_bits fw_version; 10013 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 10014 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 10015 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 10016 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 10017 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 10018 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 10019 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 10020 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 10021 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 10022 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 10023 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 10024 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 10025 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 10026 u8 reserved_0[0x42c0]; 10027 }; 10028 10029 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 10030 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10031 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10032 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10033 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10034 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10035 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10036 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10037 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10038 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 10039 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 10040 u8 reserved_0[0x7c0]; 10041 }; 10042 10043 struct mlx5_ifc_ppcnt_reg_bits { 10044 u8 swid[0x8]; 10045 u8 local_port[0x8]; 10046 u8 pnat[0x2]; 10047 u8 reserved_0[0x8]; 10048 u8 grp[0x6]; 10049 10050 u8 clr[0x1]; 10051 u8 reserved_1[0x1c]; 10052 u8 prio_tc[0x3]; 10053 10054 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10055 }; 10056 10057 struct mlx5_ifc_pcie_lanes_counters_bits { 10058 u8 life_time_counter_high[0x20]; 10059 10060 u8 life_time_counter_low[0x20]; 10061 10062 u8 error_counter_lane0[0x20]; 10063 10064 u8 error_counter_lane1[0x20]; 10065 10066 u8 error_counter_lane2[0x20]; 10067 10068 u8 error_counter_lane3[0x20]; 10069 10070 u8 error_counter_lane4[0x20]; 10071 10072 u8 error_counter_lane5[0x20]; 10073 10074 u8 error_counter_lane6[0x20]; 10075 10076 u8 error_counter_lane7[0x20]; 10077 10078 u8 error_counter_lane8[0x20]; 10079 10080 u8 error_counter_lane9[0x20]; 10081 10082 u8 error_counter_lane10[0x20]; 10083 10084 u8 error_counter_lane11[0x20]; 10085 10086 u8 error_counter_lane12[0x20]; 10087 10088 u8 error_counter_lane13[0x20]; 10089 10090 u8 error_counter_lane14[0x20]; 10091 10092 u8 error_counter_lane15[0x20]; 10093 10094 u8 reserved_at_240[0x580]; 10095 }; 10096 10097 struct mlx5_ifc_pcie_lanes_counters_ext_bits { 10098 u8 reserved_at_0[0x40]; 10099 10100 u8 error_counter_lane0[0x20]; 10101 10102 u8 error_counter_lane1[0x20]; 10103 10104 u8 error_counter_lane2[0x20]; 10105 10106 u8 error_counter_lane3[0x20]; 10107 10108 u8 error_counter_lane4[0x20]; 10109 10110 u8 error_counter_lane5[0x20]; 10111 10112 u8 error_counter_lane6[0x20]; 10113 10114 u8 error_counter_lane7[0x20]; 10115 10116 u8 error_counter_lane8[0x20]; 10117 10118 u8 error_counter_lane9[0x20]; 10119 10120 u8 error_counter_lane10[0x20]; 10121 10122 u8 error_counter_lane11[0x20]; 10123 10124 u8 error_counter_lane12[0x20]; 10125 10126 u8 error_counter_lane13[0x20]; 10127 10128 u8 error_counter_lane14[0x20]; 10129 10130 u8 error_counter_lane15[0x20]; 10131 10132 u8 reserved_at_240[0x580]; 10133 }; 10134 10135 struct mlx5_ifc_pcie_perf_counters_bits { 10136 u8 life_time_counter_high[0x20]; 10137 10138 u8 life_time_counter_low[0x20]; 10139 10140 u8 rx_errors[0x20]; 10141 10142 u8 tx_errors[0x20]; 10143 10144 u8 l0_to_recovery_eieos[0x20]; 10145 10146 u8 l0_to_recovery_ts[0x20]; 10147 10148 u8 l0_to_recovery_framing[0x20]; 10149 10150 u8 l0_to_recovery_retrain[0x20]; 10151 10152 u8 crc_error_dllp[0x20]; 10153 10154 u8 crc_error_tlp[0x20]; 10155 10156 u8 tx_overflow_buffer_pkt[0x40]; 10157 10158 u8 outbound_stalled_reads[0x20]; 10159 10160 u8 outbound_stalled_writes[0x20]; 10161 10162 u8 outbound_stalled_reads_events[0x20]; 10163 10164 u8 outbound_stalled_writes_events[0x20]; 10165 10166 u8 tx_overflow_buffer_marked_pkt[0x40]; 10167 10168 u8 reserved_at_240[0x580]; 10169 }; 10170 10171 struct mlx5_ifc_pcie_perf_counters_ext_bits { 10172 u8 reserved_at_0[0x40]; 10173 10174 u8 rx_errors[0x20]; 10175 10176 u8 tx_errors[0x20]; 10177 10178 u8 reserved_at_80[0xc0]; 10179 10180 u8 tx_overflow_buffer_pkt[0x40]; 10181 10182 u8 outbound_stalled_reads[0x20]; 10183 10184 u8 outbound_stalled_writes[0x20]; 10185 10186 u8 outbound_stalled_reads_events[0x20]; 10187 10188 u8 outbound_stalled_writes_events[0x20]; 10189 10190 u8 tx_overflow_buffer_marked_pkt[0x40]; 10191 10192 u8 reserved_at_240[0x580]; 10193 }; 10194 10195 struct mlx5_ifc_pcie_timers_states_bits { 10196 u8 life_time_counter_high[0x20]; 10197 10198 u8 life_time_counter_low[0x20]; 10199 10200 u8 time_to_boot_image_start[0x20]; 10201 10202 u8 time_to_link_image[0x20]; 10203 10204 u8 calibration_time[0x20]; 10205 10206 u8 time_to_first_perst[0x20]; 10207 10208 u8 time_to_detect_state[0x20]; 10209 10210 u8 time_to_l0[0x20]; 10211 10212 u8 time_to_crs_en[0x20]; 10213 10214 u8 time_to_plastic_image_start[0x20]; 10215 10216 u8 time_to_iron_image_start[0x20]; 10217 10218 u8 perst_handler[0x20]; 10219 10220 u8 times_in_l1[0x20]; 10221 10222 u8 times_in_l23[0x20]; 10223 10224 u8 dl_down[0x20]; 10225 10226 u8 config_cycle1usec[0x20]; 10227 10228 u8 config_cycle2to7usec[0x20]; 10229 10230 u8 config_cycle8to15usec[0x20]; 10231 10232 u8 config_cycle16to63usec[0x20]; 10233 10234 u8 config_cycle64usec[0x20]; 10235 10236 u8 correctable_err_msg_sent[0x20]; 10237 10238 u8 non_fatal_err_msg_sent[0x20]; 10239 10240 u8 fatal_err_msg_sent[0x20]; 10241 10242 u8 reserved_at_2e0[0x4e0]; 10243 }; 10244 10245 struct mlx5_ifc_pcie_timers_states_ext_bits { 10246 u8 reserved_at_0[0x40]; 10247 10248 u8 time_to_boot_image_start[0x20]; 10249 10250 u8 time_to_link_image[0x20]; 10251 10252 u8 calibration_time[0x20]; 10253 10254 u8 time_to_first_perst[0x20]; 10255 10256 u8 time_to_detect_state[0x20]; 10257 10258 u8 time_to_l0[0x20]; 10259 10260 u8 time_to_crs_en[0x20]; 10261 10262 u8 time_to_plastic_image_start[0x20]; 10263 10264 u8 time_to_iron_image_start[0x20]; 10265 10266 u8 perst_handler[0x20]; 10267 10268 u8 times_in_l1[0x20]; 10269 10270 u8 times_in_l23[0x20]; 10271 10272 u8 dl_down[0x20]; 10273 10274 u8 config_cycle1usec[0x20]; 10275 10276 u8 config_cycle2to7usec[0x20]; 10277 10278 u8 config_cycle8to15usec[0x20]; 10279 10280 u8 config_cycle16to63usec[0x20]; 10281 10282 u8 config_cycle64usec[0x20]; 10283 10284 u8 correctable_err_msg_sent[0x20]; 10285 10286 u8 non_fatal_err_msg_sent[0x20]; 10287 10288 u8 fatal_err_msg_sent[0x20]; 10289 10290 u8 reserved_at_2e0[0x4e0]; 10291 }; 10292 10293 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits { 10294 struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters; 10295 struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters; 10296 struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states; 10297 u8 reserved_at_0[0x7c0]; 10298 }; 10299 10300 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits { 10301 struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext; 10302 struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext; 10303 struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext; 10304 u8 reserved_at_0[0x7c0]; 10305 }; 10306 10307 struct mlx5_ifc_mpcnt_reg_bits { 10308 u8 reserved_at_0[0x2]; 10309 u8 depth[0x6]; 10310 u8 pcie_index[0x8]; 10311 u8 node[0x8]; 10312 u8 reserved_at_18[0x2]; 10313 u8 grp[0x6]; 10314 10315 u8 clr[0x1]; 10316 u8 reserved_at_21[0x1f]; 10317 10318 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set; 10319 }; 10320 10321 struct mlx5_ifc_mpcnt_reg_ext_bits { 10322 u8 reserved_at_0[0x2]; 10323 u8 depth[0x6]; 10324 u8 pcie_index[0x8]; 10325 u8 node[0x8]; 10326 u8 reserved_at_18[0x2]; 10327 u8 grp[0x6]; 10328 10329 u8 clr[0x1]; 10330 u8 reserved_at_21[0x1f]; 10331 10332 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set; 10333 }; 10334 10335 struct mlx5_ifc_monitor_opcodes_layout_bits { 10336 u8 reserved_at_0[0x10]; 10337 u8 monitor_opcode[0x10]; 10338 }; 10339 10340 union mlx5_ifc_pddr_status_opcode_bits { 10341 struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes; 10342 u8 reserved_at_0[0x20]; 10343 }; 10344 10345 struct mlx5_ifc_troubleshooting_info_page_layout_bits { 10346 u8 reserved_at_0[0x10]; 10347 u8 group_opcode[0x10]; 10348 10349 union mlx5_ifc_pddr_status_opcode_bits status_opcode; 10350 10351 u8 user_feedback_data[0x10]; 10352 u8 user_feedback_index[0x10]; 10353 10354 u8 status_message[0x760]; 10355 }; 10356 10357 union mlx5_ifc_pddr_page_data_bits { 10358 struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page; 10359 struct mlx5_ifc_pddr_module_info_bits pddr_module_info; 10360 u8 reserved_at_0[0x7c0]; 10361 }; 10362 10363 struct mlx5_ifc_pddr_reg_bits { 10364 u8 reserved_at_0[0x8]; 10365 u8 local_port[0x8]; 10366 u8 pnat[0x2]; 10367 u8 reserved_at_12[0xe]; 10368 10369 u8 reserved_at_20[0x18]; 10370 u8 page_select[0x8]; 10371 10372 union mlx5_ifc_pddr_page_data_bits page_data; 10373 }; 10374 10375 enum { 10376 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050, 10377 MLX5_MPEIN_PWR_STATUS_INVALID = 0, 10378 MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1, 10379 MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2, 10380 }; 10381 10382 struct mlx5_ifc_mpein_reg_bits { 10383 u8 reserved_at_0[0x2]; 10384 u8 depth[0x6]; 10385 u8 pcie_index[0x8]; 10386 u8 node[0x8]; 10387 u8 reserved_at_18[0x8]; 10388 10389 u8 capability_mask[0x20]; 10390 10391 u8 reserved_at_40[0x8]; 10392 u8 link_width_enabled[0x8]; 10393 u8 link_speed_enabled[0x10]; 10394 10395 u8 lane0_physical_position[0x8]; 10396 u8 link_width_active[0x8]; 10397 u8 link_speed_active[0x10]; 10398 10399 u8 num_of_pfs[0x10]; 10400 u8 num_of_vfs[0x10]; 10401 10402 u8 bdf0[0x10]; 10403 u8 reserved_at_b0[0x10]; 10404 10405 u8 max_read_request_size[0x4]; 10406 u8 max_payload_size[0x4]; 10407 u8 reserved_at_c8[0x5]; 10408 u8 pwr_status[0x3]; 10409 u8 port_type[0x4]; 10410 u8 reserved_at_d4[0xb]; 10411 u8 lane_reversal[0x1]; 10412 10413 u8 reserved_at_e0[0x14]; 10414 u8 pci_power[0xc]; 10415 10416 u8 reserved_at_100[0x20]; 10417 10418 u8 device_status[0x10]; 10419 u8 port_state[0x8]; 10420 u8 reserved_at_138[0x8]; 10421 10422 u8 reserved_at_140[0x10]; 10423 u8 receiver_detect_result[0x10]; 10424 10425 u8 reserved_at_160[0x20]; 10426 }; 10427 10428 struct mlx5_ifc_mpein_reg_ext_bits { 10429 u8 reserved_at_0[0x2]; 10430 u8 depth[0x6]; 10431 u8 pcie_index[0x8]; 10432 u8 node[0x8]; 10433 u8 reserved_at_18[0x8]; 10434 10435 u8 reserved_at_20[0x20]; 10436 10437 u8 reserved_at_40[0x8]; 10438 u8 link_width_enabled[0x8]; 10439 u8 link_speed_enabled[0x10]; 10440 10441 u8 lane0_physical_position[0x8]; 10442 u8 link_width_active[0x8]; 10443 u8 link_speed_active[0x10]; 10444 10445 u8 num_of_pfs[0x10]; 10446 u8 num_of_vfs[0x10]; 10447 10448 u8 bdf0[0x10]; 10449 u8 reserved_at_b0[0x10]; 10450 10451 u8 max_read_request_size[0x4]; 10452 u8 max_payload_size[0x4]; 10453 u8 reserved_at_c8[0x5]; 10454 u8 pwr_status[0x3]; 10455 u8 port_type[0x4]; 10456 u8 reserved_at_d4[0xb]; 10457 u8 lane_reversal[0x1]; 10458 }; 10459 10460 struct mlx5_ifc_mcqi_cap_bits { 10461 u8 supported_info_bitmask[0x20]; 10462 10463 u8 component_size[0x20]; 10464 10465 u8 max_component_size[0x20]; 10466 10467 u8 log_mcda_word_size[0x4]; 10468 u8 reserved_at_64[0xc]; 10469 u8 mcda_max_write_size[0x10]; 10470 10471 u8 rd_en[0x1]; 10472 u8 reserved_at_81[0x1]; 10473 u8 match_chip_id[0x1]; 10474 u8 match_psid[0x1]; 10475 u8 check_user_timestamp[0x1]; 10476 u8 match_base_guid_mac[0x1]; 10477 u8 reserved_at_86[0x1a]; 10478 }; 10479 10480 struct mlx5_ifc_mcqi_reg_bits { 10481 u8 read_pending_component[0x1]; 10482 u8 reserved_at_1[0xf]; 10483 u8 component_index[0x10]; 10484 10485 u8 reserved_at_20[0x20]; 10486 10487 u8 reserved_at_40[0x1b]; 10488 u8 info_type[0x5]; 10489 10490 u8 info_size[0x20]; 10491 10492 u8 offset[0x20]; 10493 10494 u8 reserved_at_a0[0x10]; 10495 u8 data_size[0x10]; 10496 10497 u8 data[0][0x20]; 10498 }; 10499 10500 struct mlx5_ifc_mcc_reg_bits { 10501 u8 reserved_at_0[0x4]; 10502 u8 time_elapsed_since_last_cmd[0xc]; 10503 u8 reserved_at_10[0x8]; 10504 u8 instruction[0x8]; 10505 10506 u8 reserved_at_20[0x10]; 10507 u8 component_index[0x10]; 10508 10509 u8 reserved_at_40[0x8]; 10510 u8 update_handle[0x18]; 10511 10512 u8 handle_owner_type[0x4]; 10513 u8 handle_owner_host_id[0x4]; 10514 u8 reserved_at_68[0x1]; 10515 u8 control_progress[0x7]; 10516 u8 error_code[0x8]; 10517 u8 reserved_at_78[0x4]; 10518 u8 control_state[0x4]; 10519 10520 u8 component_size[0x20]; 10521 10522 u8 reserved_at_a0[0x60]; 10523 }; 10524 10525 struct mlx5_ifc_mcda_reg_bits { 10526 u8 reserved_at_0[0x8]; 10527 u8 update_handle[0x18]; 10528 10529 u8 offset[0x20]; 10530 10531 u8 reserved_at_40[0x10]; 10532 u8 size[0x10]; 10533 10534 u8 reserved_at_60[0x20]; 10535 10536 u8 data[0][0x20]; 10537 }; 10538 10539 union mlx5_ifc_ports_control_registers_document_bits { 10540 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 10541 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10542 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10543 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10544 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10545 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10546 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10547 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10548 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10549 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 10550 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 10551 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10552 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 10553 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10554 struct mlx5_ifc_paos_reg_bits paos_reg; 10555 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 10556 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10557 struct mlx5_ifc_peir_reg_bits peir_reg; 10558 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10559 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10560 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 10561 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 10562 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 10563 struct mlx5_ifc_phrr_reg_bits phrr_reg; 10564 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10565 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10566 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10567 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10568 struct mlx5_ifc_plib_reg_bits plib_reg; 10569 struct mlx5_ifc_pll_status_data_bits pll_status_data; 10570 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10571 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10572 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10573 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10574 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10575 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10576 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10577 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10578 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10579 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10580 struct mlx5_ifc_ppll_reg_bits ppll_reg; 10581 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10582 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10583 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10584 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10585 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10586 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10587 struct mlx5_ifc_pude_reg_bits pude_reg; 10588 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10589 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10590 struct mlx5_ifc_slrp_reg_bits slrp_reg; 10591 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10592 u8 reserved_0[0x7880]; 10593 }; 10594 10595 union mlx5_ifc_debug_enhancements_document_bits { 10596 struct mlx5_ifc_health_buffer_bits health_buffer; 10597 u8 reserved_0[0x200]; 10598 }; 10599 10600 union mlx5_ifc_no_dram_nic_document_bits { 10601 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 10602 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 10603 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 10604 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 10605 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 10606 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 10607 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 10608 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 10609 u8 reserved_0[0x3160]; 10610 }; 10611 10612 union mlx5_ifc_uplink_pci_interface_document_bits { 10613 struct mlx5_ifc_initial_seg_bits initial_seg; 10614 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 10615 u8 reserved_0[0x20120]; 10616 }; 10617 10618 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10619 u8 e[0x1]; 10620 u8 reserved_at_01[0x0b]; 10621 u8 prio[0x04]; 10622 }; 10623 10624 struct mlx5_ifc_qpdpm_reg_bits { 10625 u8 reserved_at_0[0x8]; 10626 u8 local_port[0x8]; 10627 u8 reserved_at_10[0x10]; 10628 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10629 }; 10630 10631 struct mlx5_ifc_qpts_reg_bits { 10632 u8 reserved_at_0[0x8]; 10633 u8 local_port[0x8]; 10634 u8 reserved_at_10[0x2d]; 10635 u8 trust_state[0x3]; 10636 }; 10637 10638 struct mlx5_ifc_mfrl_reg_bits { 10639 u8 reserved_at_0[0x38]; 10640 u8 reset_level[0x8]; 10641 }; 10642 10643 enum { 10644 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP = 0x9009, 10645 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR = 0x9109, 10646 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP = 0x900a, 10647 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE = 0x900b, 10648 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR = 0x900f, 10649 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE = 0x910b, 10650 MLX5_MAX_TEMPERATURE = 16, 10651 }; 10652 10653 struct mlx5_ifc_mtbr_temp_record_bits { 10654 u8 max_temperature[0x10]; 10655 u8 temperature[0x10]; 10656 }; 10657 10658 struct mlx5_ifc_mtbr_reg_bits { 10659 u8 reserved_at_0[0x14]; 10660 u8 base_sensor_index[0xc]; 10661 10662 u8 reserved_at_20[0x18]; 10663 u8 num_rec[0x8]; 10664 10665 u8 reserved_at_40[0x40]; 10666 10667 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 10668 }; 10669 10670 struct mlx5_ifc_mtbr_reg_ext_bits { 10671 u8 reserved_at_0[0x14]; 10672 u8 base_sensor_index[0xc]; 10673 10674 u8 reserved_at_20[0x18]; 10675 u8 num_rec[0x8]; 10676 10677 u8 reserved_at_40[0x40]; 10678 10679 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 10680 }; 10681 10682 struct mlx5_ifc_mtcap_bits { 10683 u8 reserved_at_0[0x19]; 10684 u8 sensor_count[0x7]; 10685 10686 u8 reserved_at_20[0x19]; 10687 u8 internal_sensor_count[0x7]; 10688 10689 u8 sensor_map[0x40]; 10690 }; 10691 10692 struct mlx5_ifc_mtcap_ext_bits { 10693 u8 reserved_at_0[0x19]; 10694 u8 sensor_count[0x7]; 10695 10696 u8 reserved_at_20[0x20]; 10697 10698 u8 sensor_map[0x40]; 10699 }; 10700 10701 struct mlx5_ifc_mtecr_bits { 10702 u8 reserved_at_0[0x4]; 10703 u8 last_sensor[0xc]; 10704 u8 reserved_at_10[0x4]; 10705 u8 sensor_count[0xc]; 10706 10707 u8 reserved_at_20[0x19]; 10708 u8 internal_sensor_count[0x7]; 10709 10710 u8 sensor_map_0[0x20]; 10711 10712 u8 reserved_at_60[0x2a0]; 10713 }; 10714 10715 struct mlx5_ifc_mtecr_ext_bits { 10716 u8 reserved_at_0[0x4]; 10717 u8 last_sensor[0xc]; 10718 u8 reserved_at_10[0x4]; 10719 u8 sensor_count[0xc]; 10720 10721 u8 reserved_at_20[0x20]; 10722 10723 u8 sensor_map_0[0x20]; 10724 10725 u8 reserved_at_60[0x2a0]; 10726 }; 10727 10728 struct mlx5_ifc_mtewe_bits { 10729 u8 reserved_at_0[0x4]; 10730 u8 last_sensor[0xc]; 10731 u8 reserved_at_10[0x4]; 10732 u8 sensor_count[0xc]; 10733 10734 u8 sensor_warning_0[0x20]; 10735 10736 u8 reserved_at_40[0x2a0]; 10737 }; 10738 10739 struct mlx5_ifc_mtewe_ext_bits { 10740 u8 reserved_at_0[0x4]; 10741 u8 last_sensor[0xc]; 10742 u8 reserved_at_10[0x4]; 10743 u8 sensor_count[0xc]; 10744 10745 u8 sensor_warning_0[0x20]; 10746 10747 u8 reserved_at_40[0x2a0]; 10748 }; 10749 10750 struct mlx5_ifc_mtmp_bits { 10751 u8 reserved_at_0[0x14]; 10752 u8 sensor_index[0xc]; 10753 10754 u8 reserved_at_20[0x10]; 10755 u8 temperature[0x10]; 10756 10757 u8 mte[0x1]; 10758 u8 mtr[0x1]; 10759 u8 reserved_at_42[0xe]; 10760 u8 max_temperature[0x10]; 10761 10762 u8 tee[0x2]; 10763 u8 reserved_at_62[0xe]; 10764 u8 temperature_threshold_hi[0x10]; 10765 10766 u8 reserved_at_80[0x10]; 10767 u8 temperature_threshold_lo[0x10]; 10768 10769 u8 reserved_at_a0[0x20]; 10770 10771 u8 sensor_name_hi[0x20]; 10772 10773 u8 sensor_name_lo[0x20]; 10774 }; 10775 10776 struct mlx5_ifc_mtmp_ext_bits { 10777 u8 reserved_at_0[0x14]; 10778 u8 sensor_index[0xc]; 10779 10780 u8 reserved_at_20[0x10]; 10781 u8 temperature[0x10]; 10782 10783 u8 mte[0x1]; 10784 u8 mtr[0x1]; 10785 u8 reserved_at_42[0xe]; 10786 u8 max_temperature[0x10]; 10787 10788 u8 tee[0x2]; 10789 u8 reserved_at_62[0xe]; 10790 u8 temperature_threshold_hi[0x10]; 10791 10792 u8 reserved_at_80[0x10]; 10793 u8 temperature_threshold_lo[0x10]; 10794 10795 u8 reserved_at_a0[0x20]; 10796 10797 u8 sensor_name_hi[0x20]; 10798 10799 u8 sensor_name_lo[0x20]; 10800 }; 10801 10802 #endif /* MLX5_IFC_H */ 10803