1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_IFC_H 29 #define MLX5_IFC_H 30 31 enum { 32 MLX5_EVENT_TYPE_COMP = 0x0, 33 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 34 MLX5_EVENT_TYPE_COMM_EST = 0x2, 35 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 36 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 37 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 38 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 39 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 40 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 41 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 42 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 43 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 44 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 45 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 46 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 47 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 48 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 49 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 50 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 51 MLX5_EVENT_TYPE_CODING_TEMP_WARNING_EVENT = 0x17, 52 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 53 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 54 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 55 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 56 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 57 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 58 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 59 MLX5_EVENT_TYPE_CMD = 0xa, 60 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 61 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd 62 }; 63 64 enum { 65 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 66 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 67 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 68 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 69 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 70 }; 71 72 enum { 73 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 74 }; 75 76 enum { 77 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 78 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 79 }; 80 81 enum { 82 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 83 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 84 MLX5_CMD_OP_INIT_HCA = 0x102, 85 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 86 MLX5_CMD_OP_ENABLE_HCA = 0x104, 87 MLX5_CMD_OP_DISABLE_HCA = 0x105, 88 MLX5_CMD_OP_QUERY_PAGES = 0x107, 89 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 90 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 91 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 92 MLX5_CMD_OP_SET_ISSI = 0x10b, 93 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 94 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 95 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 96 MLX5_CMD_OP_CREATE_MKEY = 0x200, 97 MLX5_CMD_OP_QUERY_MKEY = 0x201, 98 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 99 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 100 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 101 MLX5_CMD_OP_CREATE_EQ = 0x301, 102 MLX5_CMD_OP_DESTROY_EQ = 0x302, 103 MLX5_CMD_OP_QUERY_EQ = 0x303, 104 MLX5_CMD_OP_GEN_EQE = 0x304, 105 MLX5_CMD_OP_CREATE_CQ = 0x400, 106 MLX5_CMD_OP_DESTROY_CQ = 0x401, 107 MLX5_CMD_OP_QUERY_CQ = 0x402, 108 MLX5_CMD_OP_MODIFY_CQ = 0x403, 109 MLX5_CMD_OP_CREATE_QP = 0x500, 110 MLX5_CMD_OP_DESTROY_QP = 0x501, 111 MLX5_CMD_OP_RST2INIT_QP = 0x502, 112 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 113 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 114 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 115 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 116 MLX5_CMD_OP_2ERR_QP = 0x507, 117 MLX5_CMD_OP_2RST_QP = 0x50a, 118 MLX5_CMD_OP_QUERY_QP = 0x50b, 119 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 120 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 121 MLX5_CMD_OP_CREATE_PSV = 0x600, 122 MLX5_CMD_OP_DESTROY_PSV = 0x601, 123 MLX5_CMD_OP_CREATE_SRQ = 0x700, 124 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 125 MLX5_CMD_OP_QUERY_SRQ = 0x702, 126 MLX5_CMD_OP_ARM_RQ = 0x703, 127 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 128 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 129 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 130 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 131 MLX5_CMD_OP_CREATE_DCT = 0x710, 132 MLX5_CMD_OP_DESTROY_DCT = 0x711, 133 MLX5_CMD_OP_DRAIN_DCT = 0x712, 134 MLX5_CMD_OP_QUERY_DCT = 0x713, 135 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 136 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 137 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 138 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 139 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 140 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 141 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 142 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 143 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 144 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 145 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 146 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 147 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 148 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 149 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 150 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 151 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 152 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 153 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 154 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 155 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 156 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 157 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 158 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 159 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 160 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 161 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 162 MLX5_CMD_OP_ALLOC_PD = 0x800, 163 MLX5_CMD_OP_DEALLOC_PD = 0x801, 164 MLX5_CMD_OP_ALLOC_UAR = 0x802, 165 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 166 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 167 MLX5_CMD_OP_ACCESS_REG = 0x805, 168 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 169 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 170 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 171 MLX5_CMD_OP_MAD_IFC = 0x50d, 172 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 173 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 174 MLX5_CMD_OP_NOP = 0x80d, 175 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 176 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 177 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 178 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 179 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 180 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 181 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 182 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 183 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 184 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 185 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 186 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 187 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 188 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 189 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 190 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 191 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 192 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 193 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 194 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 195 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 196 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 197 MLX5_CMD_OP_CREATE_LAG = 0x840, 198 MLX5_CMD_OP_MODIFY_LAG = 0x841, 199 MLX5_CMD_OP_QUERY_LAG = 0x842, 200 MLX5_CMD_OP_DESTROY_LAG = 0x843, 201 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 202 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 203 MLX5_CMD_OP_CREATE_TIR = 0x900, 204 MLX5_CMD_OP_MODIFY_TIR = 0x901, 205 MLX5_CMD_OP_DESTROY_TIR = 0x902, 206 MLX5_CMD_OP_QUERY_TIR = 0x903, 207 MLX5_CMD_OP_CREATE_SQ = 0x904, 208 MLX5_CMD_OP_MODIFY_SQ = 0x905, 209 MLX5_CMD_OP_DESTROY_SQ = 0x906, 210 MLX5_CMD_OP_QUERY_SQ = 0x907, 211 MLX5_CMD_OP_CREATE_RQ = 0x908, 212 MLX5_CMD_OP_MODIFY_RQ = 0x909, 213 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 214 MLX5_CMD_OP_QUERY_RQ = 0x90b, 215 MLX5_CMD_OP_CREATE_RMP = 0x90c, 216 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 217 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 218 MLX5_CMD_OP_QUERY_RMP = 0x90f, 219 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 220 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 221 MLX5_CMD_OP_CREATE_TIS = 0x912, 222 MLX5_CMD_OP_MODIFY_TIS = 0x913, 223 MLX5_CMD_OP_DESTROY_TIS = 0x914, 224 MLX5_CMD_OP_QUERY_TIS = 0x915, 225 MLX5_CMD_OP_CREATE_RQT = 0x916, 226 MLX5_CMD_OP_MODIFY_RQT = 0x917, 227 MLX5_CMD_OP_DESTROY_RQT = 0x918, 228 MLX5_CMD_OP_QUERY_RQT = 0x919, 229 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 230 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 231 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 232 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 233 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 234 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 235 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 236 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 237 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 238 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 239 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 240 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 241 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 242 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 243 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 244 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 245 }; 246 247 enum { 248 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 249 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 250 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 251 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 252 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 253 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 254 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 255 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 256 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 257 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 258 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 259 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 260 }; 261 262 struct mlx5_ifc_flow_table_fields_supported_bits { 263 u8 outer_dmac[0x1]; 264 u8 outer_smac[0x1]; 265 u8 outer_ether_type[0x1]; 266 u8 reserved_0[0x1]; 267 u8 outer_first_prio[0x1]; 268 u8 outer_first_cfi[0x1]; 269 u8 outer_first_vid[0x1]; 270 u8 reserved_1[0x1]; 271 u8 outer_second_prio[0x1]; 272 u8 outer_second_cfi[0x1]; 273 u8 outer_second_vid[0x1]; 274 u8 outer_ipv6_flow_label[0x1]; 275 u8 outer_sip[0x1]; 276 u8 outer_dip[0x1]; 277 u8 outer_frag[0x1]; 278 u8 outer_ip_protocol[0x1]; 279 u8 outer_ip_ecn[0x1]; 280 u8 outer_ip_dscp[0x1]; 281 u8 outer_udp_sport[0x1]; 282 u8 outer_udp_dport[0x1]; 283 u8 outer_tcp_sport[0x1]; 284 u8 outer_tcp_dport[0x1]; 285 u8 outer_tcp_flags[0x1]; 286 u8 outer_gre_protocol[0x1]; 287 u8 outer_gre_key[0x1]; 288 u8 outer_vxlan_vni[0x1]; 289 u8 outer_geneve_vni[0x1]; 290 u8 outer_geneve_oam[0x1]; 291 u8 outer_geneve_protocol_type[0x1]; 292 u8 outer_geneve_opt_len[0x1]; 293 u8 reserved_2[0x1]; 294 u8 source_eswitch_port[0x1]; 295 296 u8 inner_dmac[0x1]; 297 u8 inner_smac[0x1]; 298 u8 inner_ether_type[0x1]; 299 u8 reserved_3[0x1]; 300 u8 inner_first_prio[0x1]; 301 u8 inner_first_cfi[0x1]; 302 u8 inner_first_vid[0x1]; 303 u8 reserved_4[0x1]; 304 u8 inner_second_prio[0x1]; 305 u8 inner_second_cfi[0x1]; 306 u8 inner_second_vid[0x1]; 307 u8 inner_ipv6_flow_label[0x1]; 308 u8 inner_sip[0x1]; 309 u8 inner_dip[0x1]; 310 u8 inner_frag[0x1]; 311 u8 inner_ip_protocol[0x1]; 312 u8 inner_ip_ecn[0x1]; 313 u8 inner_ip_dscp[0x1]; 314 u8 inner_udp_sport[0x1]; 315 u8 inner_udp_dport[0x1]; 316 u8 inner_tcp_sport[0x1]; 317 u8 inner_tcp_dport[0x1]; 318 u8 inner_tcp_flags[0x1]; 319 u8 reserved_5[0x9]; 320 321 u8 reserved_6[0x1a]; 322 u8 bth_dst_qp[0x1]; 323 u8 reserved_7[0x4]; 324 u8 source_sqn[0x1]; 325 326 u8 reserved_8[0x20]; 327 }; 328 329 struct mlx5_ifc_eth_discard_cntrs_grp_bits { 330 u8 ingress_general_high[0x20]; 331 332 u8 ingress_general_low[0x20]; 333 334 u8 ingress_policy_engine_high[0x20]; 335 336 u8 ingress_policy_engine_low[0x20]; 337 338 u8 ingress_vlan_membership_high[0x20]; 339 340 u8 ingress_vlan_membership_low[0x20]; 341 342 u8 ingress_tag_frame_type_high[0x20]; 343 344 u8 ingress_tag_frame_type_low[0x20]; 345 346 u8 egress_vlan_membership_high[0x20]; 347 348 u8 egress_vlan_membership_low[0x20]; 349 350 u8 loopback_filter_high[0x20]; 351 352 u8 loopback_filter_low[0x20]; 353 354 u8 egress_general_high[0x20]; 355 356 u8 egress_general_low[0x20]; 357 358 u8 reserved_at_1c0[0x40]; 359 360 u8 egress_hoq_high[0x20]; 361 362 u8 egress_hoq_low[0x20]; 363 364 u8 port_isolation_high[0x20]; 365 366 u8 port_isolation_low[0x20]; 367 368 u8 egress_policy_engine_high[0x20]; 369 370 u8 egress_policy_engine_low[0x20]; 371 372 u8 ingress_tx_link_down_high[0x20]; 373 374 u8 ingress_tx_link_down_low[0x20]; 375 376 u8 egress_stp_filter_high[0x20]; 377 378 u8 egress_stp_filter_low[0x20]; 379 380 u8 egress_hoq_stall_high[0x20]; 381 382 u8 egress_hoq_stall_low[0x20]; 383 384 u8 reserved_at_340[0x440]; 385 }; 386 struct mlx5_ifc_flow_table_prop_layout_bits { 387 u8 ft_support[0x1]; 388 u8 flow_tag[0x1]; 389 u8 flow_counter[0x1]; 390 u8 flow_modify_en[0x1]; 391 u8 modify_root[0x1]; 392 u8 identified_miss_table[0x1]; 393 u8 flow_table_modify[0x1]; 394 u8 encap[0x1]; 395 u8 decap[0x1]; 396 u8 reset_root_to_default[0x1]; 397 u8 reserved_at_a[0x16]; 398 399 u8 reserved_at_20[0x2]; 400 u8 log_max_ft_size[0x6]; 401 u8 reserved_at_28[0x10]; 402 u8 max_ft_level[0x8]; 403 404 u8 reserved_at_40[0x20]; 405 406 u8 reserved_at_60[0x18]; 407 u8 log_max_ft_num[0x8]; 408 409 u8 reserved_at_80[0x10]; 410 u8 log_max_flow_counter[0x8]; 411 u8 log_max_destination[0x8]; 412 413 u8 reserved_at_a0[0x18]; 414 u8 log_max_flow[0x8]; 415 416 u8 reserved_at_c0[0x40]; 417 418 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 419 420 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 421 }; 422 423 struct mlx5_ifc_odp_per_transport_service_cap_bits { 424 u8 send[0x1]; 425 u8 receive[0x1]; 426 u8 write[0x1]; 427 u8 read[0x1]; 428 u8 atomic[0x1]; 429 u8 srq_receive[0x1]; 430 u8 reserved_0[0x1a]; 431 }; 432 433 struct mlx5_ifc_flow_counter_list_bits { 434 u8 reserved_0[0x10]; 435 u8 flow_counter_id[0x10]; 436 437 u8 reserved_1[0x20]; 438 }; 439 440 enum { 441 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 442 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 443 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 444 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 445 }; 446 447 struct mlx5_ifc_dest_format_struct_bits { 448 u8 destination_type[0x8]; 449 u8 destination_id[0x18]; 450 451 u8 reserved_0[0x20]; 452 }; 453 454 struct mlx5_ifc_ipv4_layout_bits { 455 u8 reserved_at_0[0x60]; 456 457 u8 ipv4[0x20]; 458 }; 459 460 struct mlx5_ifc_ipv6_layout_bits { 461 u8 ipv6[16][0x8]; 462 }; 463 464 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 465 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 466 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 467 u8 reserved_at_0[0x80]; 468 }; 469 470 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 471 u8 smac_47_16[0x20]; 472 473 u8 smac_15_0[0x10]; 474 u8 ethertype[0x10]; 475 476 u8 dmac_47_16[0x20]; 477 478 u8 dmac_15_0[0x10]; 479 u8 first_prio[0x3]; 480 u8 first_cfi[0x1]; 481 u8 first_vid[0xc]; 482 483 u8 ip_protocol[0x8]; 484 u8 ip_dscp[0x6]; 485 u8 ip_ecn[0x2]; 486 u8 cvlan_tag[0x1]; 487 u8 svlan_tag[0x1]; 488 u8 frag[0x1]; 489 u8 reserved_1[0x4]; 490 u8 tcp_flags[0x9]; 491 492 u8 tcp_sport[0x10]; 493 u8 tcp_dport[0x10]; 494 495 u8 reserved_2[0x20]; 496 497 u8 udp_sport[0x10]; 498 u8 udp_dport[0x10]; 499 500 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 501 502 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 503 }; 504 505 struct mlx5_ifc_fte_match_set_misc_bits { 506 u8 reserved_0[0x8]; 507 u8 source_sqn[0x18]; 508 509 u8 reserved_1[0x10]; 510 u8 source_port[0x10]; 511 512 u8 outer_second_prio[0x3]; 513 u8 outer_second_cfi[0x1]; 514 u8 outer_second_vid[0xc]; 515 u8 inner_second_prio[0x3]; 516 u8 inner_second_cfi[0x1]; 517 u8 inner_second_vid[0xc]; 518 519 u8 outer_second_vlan_tag[0x1]; 520 u8 inner_second_vlan_tag[0x1]; 521 u8 reserved_2[0xe]; 522 u8 gre_protocol[0x10]; 523 524 u8 gre_key_h[0x18]; 525 u8 gre_key_l[0x8]; 526 527 u8 vxlan_vni[0x18]; 528 u8 reserved_3[0x8]; 529 530 u8 geneve_vni[0x18]; 531 u8 reserved4[0x7]; 532 u8 geneve_oam[0x1]; 533 534 u8 reserved_5[0xc]; 535 u8 outer_ipv6_flow_label[0x14]; 536 537 u8 reserved_6[0xc]; 538 u8 inner_ipv6_flow_label[0x14]; 539 540 u8 reserved_7[0xa]; 541 u8 geneve_opt_len[0x6]; 542 u8 geneve_protocol_type[0x10]; 543 544 u8 reserved_8[0x8]; 545 u8 bth_dst_qp[0x18]; 546 547 u8 reserved_9[0xa0]; 548 }; 549 550 struct mlx5_ifc_cmd_pas_bits { 551 u8 pa_h[0x20]; 552 553 u8 pa_l[0x14]; 554 u8 reserved_0[0xc]; 555 }; 556 557 struct mlx5_ifc_uint64_bits { 558 u8 hi[0x20]; 559 560 u8 lo[0x20]; 561 }; 562 563 struct mlx5_ifc_application_prio_entry_bits { 564 u8 reserved_0[0x8]; 565 u8 priority[0x3]; 566 u8 reserved_1[0x2]; 567 u8 sel[0x3]; 568 u8 protocol_id[0x10]; 569 }; 570 571 struct mlx5_ifc_nodnic_ring_doorbell_bits { 572 u8 reserved_0[0x8]; 573 u8 ring_pi[0x10]; 574 u8 reserved_1[0x8]; 575 }; 576 577 enum { 578 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 579 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 580 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 581 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 582 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 583 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 584 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 585 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 586 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 587 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 588 }; 589 590 struct mlx5_ifc_ads_bits { 591 u8 fl[0x1]; 592 u8 free_ar[0x1]; 593 u8 reserved_0[0xe]; 594 u8 pkey_index[0x10]; 595 596 u8 reserved_1[0x8]; 597 u8 grh[0x1]; 598 u8 mlid[0x7]; 599 u8 rlid[0x10]; 600 601 u8 ack_timeout[0x5]; 602 u8 reserved_2[0x3]; 603 u8 src_addr_index[0x8]; 604 u8 log_rtm[0x4]; 605 u8 stat_rate[0x4]; 606 u8 hop_limit[0x8]; 607 608 u8 reserved_3[0x4]; 609 u8 tclass[0x8]; 610 u8 flow_label[0x14]; 611 612 u8 rgid_rip[16][0x8]; 613 614 u8 reserved_4[0x4]; 615 u8 f_dscp[0x1]; 616 u8 f_ecn[0x1]; 617 u8 reserved_5[0x1]; 618 u8 f_eth_prio[0x1]; 619 u8 ecn[0x2]; 620 u8 dscp[0x6]; 621 u8 udp_sport[0x10]; 622 623 u8 dei_cfi[0x1]; 624 u8 eth_prio[0x3]; 625 u8 sl[0x4]; 626 u8 port[0x8]; 627 u8 rmac_47_32[0x10]; 628 629 u8 rmac_31_0[0x20]; 630 }; 631 632 struct mlx5_ifc_diagnostic_counter_cap_bits { 633 u8 sync[0x1]; 634 u8 reserved_0[0xf]; 635 u8 counter_id[0x10]; 636 }; 637 638 struct mlx5_ifc_debug_cap_bits { 639 u8 reserved_0[0x18]; 640 u8 log_max_samples[0x8]; 641 642 u8 single[0x1]; 643 u8 repetitive[0x1]; 644 u8 health_mon_rx_activity[0x1]; 645 u8 reserved_1[0x15]; 646 u8 log_min_sample_period[0x8]; 647 648 u8 reserved_2[0x1c0]; 649 650 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 651 }; 652 653 struct mlx5_ifc_qos_cap_bits { 654 u8 packet_pacing[0x1]; 655 u8 esw_scheduling[0x1]; 656 u8 esw_bw_share[0x1]; 657 u8 esw_rate_limit[0x1]; 658 u8 hll[0x1]; 659 u8 packet_pacing_burst_bound[0x1]; 660 u8 reserved_at_6[0x1a]; 661 662 u8 reserved_at_20[0x20]; 663 664 u8 packet_pacing_max_rate[0x20]; 665 666 u8 packet_pacing_min_rate[0x20]; 667 668 u8 reserved_at_80[0x10]; 669 u8 packet_pacing_rate_table_size[0x10]; 670 671 u8 esw_element_type[0x10]; 672 u8 esw_tsar_type[0x10]; 673 674 u8 reserved_at_c0[0x10]; 675 u8 max_qos_para_vport[0x10]; 676 677 u8 max_tsar_bw_share[0x20]; 678 679 u8 reserved_at_100[0x700]; 680 }; 681 682 struct mlx5_ifc_snapshot_cap_bits { 683 u8 reserved_0[0x1d]; 684 u8 suspend_qp_uc[0x1]; 685 u8 suspend_qp_ud[0x1]; 686 u8 suspend_qp_rc[0x1]; 687 688 u8 reserved_1[0x1c]; 689 u8 restore_pd[0x1]; 690 u8 restore_uar[0x1]; 691 u8 restore_mkey[0x1]; 692 u8 restore_qp[0x1]; 693 694 u8 reserved_2[0x1e]; 695 u8 named_mkey[0x1]; 696 u8 named_qp[0x1]; 697 698 u8 reserved_3[0x7a0]; 699 }; 700 701 struct mlx5_ifc_e_switch_cap_bits { 702 u8 vport_svlan_strip[0x1]; 703 u8 vport_cvlan_strip[0x1]; 704 u8 vport_svlan_insert[0x1]; 705 u8 vport_cvlan_insert_if_not_exist[0x1]; 706 u8 vport_cvlan_insert_overwrite[0x1]; 707 708 u8 reserved_0[0x19]; 709 710 u8 nic_vport_node_guid_modify[0x1]; 711 u8 nic_vport_port_guid_modify[0x1]; 712 713 u8 reserved_1[0x7e0]; 714 }; 715 716 struct mlx5_ifc_flow_table_eswitch_cap_bits { 717 u8 reserved_0[0x200]; 718 719 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 720 721 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 722 723 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 724 725 u8 reserved_1[0x7800]; 726 }; 727 728 struct mlx5_ifc_flow_table_nic_cap_bits { 729 u8 nic_rx_multi_path_tirs[0x1]; 730 u8 nic_rx_multi_path_tirs_fts[0x1]; 731 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 732 u8 reserved_at_3[0x1fd]; 733 734 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 735 736 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 737 738 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 739 740 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 741 742 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 743 744 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 745 746 u8 reserved_1[0x7200]; 747 }; 748 749 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 750 u8 csum_cap[0x1]; 751 u8 vlan_cap[0x1]; 752 u8 lro_cap[0x1]; 753 u8 lro_psh_flag[0x1]; 754 u8 lro_time_stamp[0x1]; 755 u8 lro_max_msg_sz_mode[0x2]; 756 u8 wqe_vlan_insert[0x1]; 757 u8 self_lb_en_modifiable[0x1]; 758 u8 self_lb_mc[0x1]; 759 u8 self_lb_uc[0x1]; 760 u8 max_lso_cap[0x5]; 761 u8 multi_pkt_send_wqe[0x2]; 762 u8 wqe_inline_mode[0x2]; 763 u8 rss_ind_tbl_cap[0x4]; 764 u8 scatter_fcs[0x1]; 765 u8 reserved_1[0x2]; 766 u8 tunnel_lso_const_out_ip_id[0x1]; 767 u8 tunnel_lro_gre[0x1]; 768 u8 tunnel_lro_vxlan[0x1]; 769 u8 tunnel_statless_gre[0x1]; 770 u8 tunnel_stateless_vxlan[0x1]; 771 772 u8 swp[0x1]; 773 u8 swp_csum[0x1]; 774 u8 swp_lso[0x1]; 775 u8 reserved_2[0x1b]; 776 u8 max_geneve_opt_len[0x1]; 777 u8 tunnel_stateless_geneve_rx[0x1]; 778 779 u8 reserved_3[0x10]; 780 u8 lro_min_mss_size[0x10]; 781 782 u8 reserved_4[0x120]; 783 784 u8 lro_timer_supported_periods[4][0x20]; 785 786 u8 reserved_5[0x600]; 787 }; 788 789 enum { 790 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 791 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 792 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 793 }; 794 795 struct mlx5_ifc_roce_cap_bits { 796 u8 roce_apm[0x1]; 797 u8 rts2rts_primary_eth_prio[0x1]; 798 u8 roce_rx_allow_untagged[0x1]; 799 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 800 801 u8 reserved_0[0x1c]; 802 803 u8 reserved_1[0x60]; 804 805 u8 reserved_2[0xc]; 806 u8 l3_type[0x4]; 807 u8 reserved_3[0x8]; 808 u8 roce_version[0x8]; 809 810 u8 reserved_4[0x10]; 811 u8 r_roce_dest_udp_port[0x10]; 812 813 u8 r_roce_max_src_udp_port[0x10]; 814 u8 r_roce_min_src_udp_port[0x10]; 815 816 u8 reserved_5[0x10]; 817 u8 roce_address_table_size[0x10]; 818 819 u8 reserved_6[0x700]; 820 }; 821 822 enum { 823 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 824 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 825 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 826 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 827 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 828 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 829 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 830 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 831 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 832 }; 833 834 enum { 835 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 836 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 837 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 838 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 839 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 840 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 841 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 842 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 843 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 844 }; 845 846 struct mlx5_ifc_atomic_caps_bits { 847 u8 reserved_0[0x40]; 848 849 u8 atomic_req_8B_endianess_mode[0x2]; 850 u8 reserved_1[0x4]; 851 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 852 853 u8 reserved_2[0x19]; 854 855 u8 reserved_3[0x20]; 856 857 u8 reserved_4[0x10]; 858 u8 atomic_operations[0x10]; 859 860 u8 reserved_5[0x10]; 861 u8 atomic_size_qp[0x10]; 862 863 u8 reserved_6[0x10]; 864 u8 atomic_size_dc[0x10]; 865 866 u8 reserved_7[0x720]; 867 }; 868 869 struct mlx5_ifc_odp_cap_bits { 870 u8 reserved_0[0x40]; 871 872 u8 sig[0x1]; 873 u8 reserved_1[0x1f]; 874 875 u8 reserved_2[0x20]; 876 877 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 878 879 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 880 881 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 882 883 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 884 885 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 886 887 u8 reserved_3[0x6e0]; 888 }; 889 890 enum { 891 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 892 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 893 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 894 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 895 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 896 }; 897 898 enum { 899 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 900 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 901 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 902 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 903 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 904 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 905 }; 906 907 enum { 908 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 909 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 910 }; 911 912 enum { 913 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 914 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 915 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 916 }; 917 918 struct mlx5_ifc_cmd_hca_cap_bits { 919 u8 reserved_0[0x80]; 920 921 u8 log_max_srq_sz[0x8]; 922 u8 log_max_qp_sz[0x8]; 923 u8 reserved_1[0xb]; 924 u8 log_max_qp[0x5]; 925 926 u8 reserved_2[0xb]; 927 u8 log_max_srq[0x5]; 928 u8 reserved_3[0x10]; 929 930 u8 reserved_4[0x8]; 931 u8 log_max_cq_sz[0x8]; 932 u8 reserved_5[0xb]; 933 u8 log_max_cq[0x5]; 934 935 u8 log_max_eq_sz[0x8]; 936 u8 reserved_6[0x2]; 937 u8 log_max_mkey[0x6]; 938 u8 reserved_7[0xc]; 939 u8 log_max_eq[0x4]; 940 941 u8 max_indirection[0x8]; 942 u8 reserved_8[0x1]; 943 u8 log_max_mrw_sz[0x7]; 944 u8 reserved_9[0x2]; 945 u8 log_max_bsf_list_size[0x6]; 946 u8 reserved_10[0x2]; 947 u8 log_max_klm_list_size[0x6]; 948 949 u8 reserved_11[0xa]; 950 u8 log_max_ra_req_dc[0x6]; 951 u8 reserved_12[0xa]; 952 u8 log_max_ra_res_dc[0x6]; 953 954 u8 reserved_13[0xa]; 955 u8 log_max_ra_req_qp[0x6]; 956 u8 reserved_14[0xa]; 957 u8 log_max_ra_res_qp[0x6]; 958 959 u8 pad_cap[0x1]; 960 u8 cc_query_allowed[0x1]; 961 u8 cc_modify_allowed[0x1]; 962 u8 start_pad[0x1]; 963 u8 cache_line_128byte[0x1]; 964 u8 reserved_15[0xb]; 965 u8 gid_table_size[0x10]; 966 967 u8 out_of_seq_cnt[0x1]; 968 u8 vport_counters[0x1]; 969 u8 retransmission_q_counters[0x1]; 970 u8 debug[0x1]; 971 u8 modify_rq_counters_set_id[0x1]; 972 u8 rq_delay_drop[0x1]; 973 u8 max_qp_cnt[0xa]; 974 u8 pkey_table_size[0x10]; 975 976 u8 vport_group_manager[0x1]; 977 u8 vhca_group_manager[0x1]; 978 u8 ib_virt[0x1]; 979 u8 eth_virt[0x1]; 980 u8 reserved_17[0x1]; 981 u8 ets[0x1]; 982 u8 nic_flow_table[0x1]; 983 u8 eswitch_flow_table[0x1]; 984 u8 reserved_18[0x3]; 985 u8 local_ca_ack_delay[0x5]; 986 u8 port_module_event[0x1]; 987 u8 reserved_19[0x5]; 988 u8 port_type[0x2]; 989 u8 num_ports[0x8]; 990 991 u8 snapshot[0x1]; 992 u8 reserved_20[0x2]; 993 u8 log_max_msg[0x5]; 994 u8 reserved_21[0x4]; 995 u8 max_tc[0x4]; 996 u8 temp_warn_event[0x1]; 997 u8 dcbx[0x1]; 998 u8 reserved_22[0x4]; 999 u8 rol_s[0x1]; 1000 u8 rol_g[0x1]; 1001 u8 reserved_23[0x1]; 1002 u8 wol_s[0x1]; 1003 u8 wol_g[0x1]; 1004 u8 wol_a[0x1]; 1005 u8 wol_b[0x1]; 1006 u8 wol_m[0x1]; 1007 u8 wol_u[0x1]; 1008 u8 wol_p[0x1]; 1009 1010 u8 stat_rate_support[0x10]; 1011 u8 reserved_24[0xc]; 1012 u8 cqe_version[0x4]; 1013 1014 u8 compact_address_vector[0x1]; 1015 u8 striding_rq[0x1]; 1016 u8 reserved_25[0x1]; 1017 u8 ipoib_enhanced_offloads[0x1]; 1018 u8 ipoib_ipoib_offloads[0x1]; 1019 u8 reserved_26[0x8]; 1020 u8 dc_connect_qp[0x1]; 1021 u8 dc_cnak_trace[0x1]; 1022 u8 drain_sigerr[0x1]; 1023 u8 cmdif_checksum[0x2]; 1024 u8 sigerr_cqe[0x1]; 1025 u8 reserved_27[0x1]; 1026 u8 wq_signature[0x1]; 1027 u8 sctr_data_cqe[0x1]; 1028 u8 reserved_28[0x1]; 1029 u8 sho[0x1]; 1030 u8 tph[0x1]; 1031 u8 rf[0x1]; 1032 u8 dct[0x1]; 1033 u8 qos[0x1]; 1034 u8 eth_net_offloads[0x1]; 1035 u8 roce[0x1]; 1036 u8 atomic[0x1]; 1037 u8 reserved_30[0x1]; 1038 1039 u8 cq_oi[0x1]; 1040 u8 cq_resize[0x1]; 1041 u8 cq_moderation[0x1]; 1042 u8 cq_period_mode_modify[0x1]; 1043 u8 cq_invalidate[0x1]; 1044 u8 reserved_at_225[0x1]; 1045 u8 cq_eq_remap[0x1]; 1046 u8 pg[0x1]; 1047 u8 block_lb_mc[0x1]; 1048 u8 exponential_backoff[0x1]; 1049 u8 scqe_break_moderation[0x1]; 1050 u8 cq_period_start_from_cqe[0x1]; 1051 u8 cd[0x1]; 1052 u8 atm[0x1]; 1053 u8 apm[0x1]; 1054 u8 imaicl[0x1]; 1055 u8 reserved_32[0x6]; 1056 u8 qkv[0x1]; 1057 u8 pkv[0x1]; 1058 u8 set_deth_sqpn[0x1]; 1059 u8 reserved_33[0x3]; 1060 u8 xrc[0x1]; 1061 u8 ud[0x1]; 1062 u8 uc[0x1]; 1063 u8 rc[0x1]; 1064 1065 u8 reserved_34[0xa]; 1066 u8 uar_sz[0x6]; 1067 u8 reserved_35[0x8]; 1068 u8 log_pg_sz[0x8]; 1069 1070 u8 bf[0x1]; 1071 u8 driver_version[0x1]; 1072 u8 pad_tx_eth_packet[0x1]; 1073 u8 reserved_36[0x8]; 1074 u8 log_bf_reg_size[0x5]; 1075 u8 reserved_37[0x10]; 1076 1077 u8 num_of_diagnostic_counters[0x10]; 1078 u8 max_wqe_sz_sq[0x10]; 1079 1080 u8 reserved_38[0x10]; 1081 u8 max_wqe_sz_rq[0x10]; 1082 1083 u8 reserved_39[0x10]; 1084 u8 max_wqe_sz_sq_dc[0x10]; 1085 1086 u8 reserved_40[0x7]; 1087 u8 max_qp_mcg[0x19]; 1088 1089 u8 reserved_41[0x18]; 1090 u8 log_max_mcg[0x8]; 1091 1092 u8 reserved_42[0x3]; 1093 u8 log_max_transport_domain[0x5]; 1094 u8 reserved_43[0x3]; 1095 u8 log_max_pd[0x5]; 1096 u8 reserved_44[0xb]; 1097 u8 log_max_xrcd[0x5]; 1098 1099 u8 reserved_45[0x10]; 1100 u8 max_flow_counter[0x10]; 1101 1102 u8 reserved_46[0x3]; 1103 u8 log_max_rq[0x5]; 1104 u8 reserved_47[0x3]; 1105 u8 log_max_sq[0x5]; 1106 u8 reserved_48[0x3]; 1107 u8 log_max_tir[0x5]; 1108 u8 reserved_49[0x3]; 1109 u8 log_max_tis[0x5]; 1110 1111 u8 basic_cyclic_rcv_wqe[0x1]; 1112 u8 reserved_50[0x2]; 1113 u8 log_max_rmp[0x5]; 1114 u8 reserved_51[0x3]; 1115 u8 log_max_rqt[0x5]; 1116 u8 reserved_52[0x3]; 1117 u8 log_max_rqt_size[0x5]; 1118 u8 reserved_53[0x3]; 1119 u8 log_max_tis_per_sq[0x5]; 1120 1121 u8 reserved_54[0x3]; 1122 u8 log_max_stride_sz_rq[0x5]; 1123 u8 reserved_55[0x3]; 1124 u8 log_min_stride_sz_rq[0x5]; 1125 u8 reserved_56[0x3]; 1126 u8 log_max_stride_sz_sq[0x5]; 1127 u8 reserved_57[0x3]; 1128 u8 log_min_stride_sz_sq[0x5]; 1129 1130 u8 reserved_58[0x1b]; 1131 u8 log_max_wq_sz[0x5]; 1132 1133 u8 nic_vport_change_event[0x1]; 1134 u8 disable_local_lb[0x1]; 1135 u8 reserved_59[0x9]; 1136 u8 log_max_vlan_list[0x5]; 1137 u8 reserved_60[0x3]; 1138 u8 log_max_current_mc_list[0x5]; 1139 u8 reserved_61[0x3]; 1140 u8 log_max_current_uc_list[0x5]; 1141 1142 u8 reserved_62[0x80]; 1143 1144 u8 reserved_63[0x3]; 1145 u8 log_max_l2_table[0x5]; 1146 u8 reserved_64[0x8]; 1147 u8 log_uar_page_sz[0x10]; 1148 1149 u8 reserved_65[0x20]; 1150 1151 u8 device_frequency_mhz[0x20]; 1152 1153 u8 device_frequency_khz[0x20]; 1154 1155 u8 reserved_66[0x80]; 1156 1157 u8 log_max_atomic_size_qp[0x8]; 1158 u8 reserved_67[0x10]; 1159 u8 log_max_atomic_size_dc[0x8]; 1160 1161 u8 reserved_68[0x1f]; 1162 u8 cqe_compression[0x1]; 1163 1164 u8 cqe_compression_timeout[0x10]; 1165 u8 cqe_compression_max_num[0x10]; 1166 1167 u8 reserved_69[0x220]; 1168 }; 1169 1170 enum mlx5_flow_destination_type { 1171 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1172 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1173 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1174 }; 1175 1176 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1177 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1178 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1179 u8 reserved_0[0x40]; 1180 }; 1181 1182 struct mlx5_ifc_fte_match_param_bits { 1183 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1184 1185 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1186 1187 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1188 1189 u8 reserved_0[0xa00]; 1190 }; 1191 1192 enum { 1193 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1194 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1195 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1196 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1197 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1198 }; 1199 1200 struct mlx5_ifc_rx_hash_field_select_bits { 1201 u8 l3_prot_type[0x1]; 1202 u8 l4_prot_type[0x1]; 1203 u8 selected_fields[0x1e]; 1204 }; 1205 1206 enum { 1207 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1208 MLX5_WQ_TYPE_CYCLIC = 0x1, 1209 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1210 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1211 }; 1212 1213 enum rq_type { 1214 RQ_TYPE_NONE, 1215 RQ_TYPE_STRIDE, 1216 }; 1217 1218 enum { 1219 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1220 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1221 }; 1222 1223 struct mlx5_ifc_wq_bits { 1224 u8 wq_type[0x4]; 1225 u8 wq_signature[0x1]; 1226 u8 end_padding_mode[0x2]; 1227 u8 cd_slave[0x1]; 1228 u8 reserved_0[0x18]; 1229 1230 u8 hds_skip_first_sge[0x1]; 1231 u8 log2_hds_buf_size[0x3]; 1232 u8 reserved_1[0x7]; 1233 u8 page_offset[0x5]; 1234 u8 lwm[0x10]; 1235 1236 u8 reserved_2[0x8]; 1237 u8 pd[0x18]; 1238 1239 u8 reserved_3[0x8]; 1240 u8 uar_page[0x18]; 1241 1242 u8 dbr_addr[0x40]; 1243 1244 u8 hw_counter[0x20]; 1245 1246 u8 sw_counter[0x20]; 1247 1248 u8 reserved_4[0xc]; 1249 u8 log_wq_stride[0x4]; 1250 u8 reserved_5[0x3]; 1251 u8 log_wq_pg_sz[0x5]; 1252 u8 reserved_6[0x3]; 1253 u8 log_wq_sz[0x5]; 1254 1255 u8 reserved_7[0x15]; 1256 u8 single_wqe_log_num_of_strides[0x3]; 1257 u8 two_byte_shift_en[0x1]; 1258 u8 reserved_8[0x4]; 1259 u8 single_stride_log_num_of_bytes[0x3]; 1260 1261 u8 reserved_9[0x4c0]; 1262 1263 struct mlx5_ifc_cmd_pas_bits pas[0]; 1264 }; 1265 1266 struct mlx5_ifc_rq_num_bits { 1267 u8 reserved_0[0x8]; 1268 u8 rq_num[0x18]; 1269 }; 1270 1271 struct mlx5_ifc_mac_address_layout_bits { 1272 u8 reserved_0[0x10]; 1273 u8 mac_addr_47_32[0x10]; 1274 1275 u8 mac_addr_31_0[0x20]; 1276 }; 1277 1278 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1279 u8 reserved_0[0xa0]; 1280 1281 u8 min_time_between_cnps[0x20]; 1282 1283 u8 reserved_1[0x12]; 1284 u8 cnp_dscp[0x6]; 1285 u8 reserved_2[0x4]; 1286 u8 cnp_prio_mode[0x1]; 1287 u8 cnp_802p_prio[0x3]; 1288 1289 u8 reserved_3[0x720]; 1290 }; 1291 1292 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1293 u8 reserved_0[0x60]; 1294 1295 u8 reserved_1[0x4]; 1296 u8 clamp_tgt_rate[0x1]; 1297 u8 reserved_2[0x3]; 1298 u8 clamp_tgt_rate_after_time_inc[0x1]; 1299 u8 reserved_3[0x17]; 1300 1301 u8 reserved_4[0x20]; 1302 1303 u8 rpg_time_reset[0x20]; 1304 1305 u8 rpg_byte_reset[0x20]; 1306 1307 u8 rpg_threshold[0x20]; 1308 1309 u8 rpg_max_rate[0x20]; 1310 1311 u8 rpg_ai_rate[0x20]; 1312 1313 u8 rpg_hai_rate[0x20]; 1314 1315 u8 rpg_gd[0x20]; 1316 1317 u8 rpg_min_dec_fac[0x20]; 1318 1319 u8 rpg_min_rate[0x20]; 1320 1321 u8 reserved_5[0xe0]; 1322 1323 u8 rate_to_set_on_first_cnp[0x20]; 1324 1325 u8 dce_tcp_g[0x20]; 1326 1327 u8 dce_tcp_rtt[0x20]; 1328 1329 u8 rate_reduce_monitor_period[0x20]; 1330 1331 u8 reserved_6[0x20]; 1332 1333 u8 initial_alpha_value[0x20]; 1334 1335 u8 reserved_7[0x4a0]; 1336 }; 1337 1338 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1339 u8 reserved_0[0x80]; 1340 1341 u8 rppp_max_rps[0x20]; 1342 1343 u8 rpg_time_reset[0x20]; 1344 1345 u8 rpg_byte_reset[0x20]; 1346 1347 u8 rpg_threshold[0x20]; 1348 1349 u8 rpg_max_rate[0x20]; 1350 1351 u8 rpg_ai_rate[0x20]; 1352 1353 u8 rpg_hai_rate[0x20]; 1354 1355 u8 rpg_gd[0x20]; 1356 1357 u8 rpg_min_dec_fac[0x20]; 1358 1359 u8 rpg_min_rate[0x20]; 1360 1361 u8 reserved_1[0x640]; 1362 }; 1363 1364 enum { 1365 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1366 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1367 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1368 }; 1369 1370 struct mlx5_ifc_resize_field_select_bits { 1371 u8 resize_field_select[0x20]; 1372 }; 1373 1374 enum { 1375 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1376 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1377 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1378 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1379 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1380 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1381 }; 1382 1383 struct mlx5_ifc_modify_field_select_bits { 1384 u8 modify_field_select[0x20]; 1385 }; 1386 1387 struct mlx5_ifc_field_select_r_roce_np_bits { 1388 u8 field_select_r_roce_np[0x20]; 1389 }; 1390 1391 enum { 1392 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1393 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1394 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1395 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1396 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1397 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1398 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1399 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1400 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1401 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1402 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1403 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1404 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1405 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1406 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1407 }; 1408 1409 struct mlx5_ifc_field_select_r_roce_rp_bits { 1410 u8 field_select_r_roce_rp[0x20]; 1411 }; 1412 1413 enum { 1414 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1415 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1416 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1417 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1418 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1419 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1420 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1421 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1422 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1423 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1424 }; 1425 1426 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1427 u8 field_select_8021qaurp[0x20]; 1428 }; 1429 1430 struct mlx5_ifc_pptb_reg_bits { 1431 u8 reserved_0[0x2]; 1432 u8 mm[0x2]; 1433 u8 reserved_1[0x4]; 1434 u8 local_port[0x8]; 1435 u8 reserved_2[0x6]; 1436 u8 cm[0x1]; 1437 u8 um[0x1]; 1438 u8 pm[0x8]; 1439 1440 u8 prio7buff[0x4]; 1441 u8 prio6buff[0x4]; 1442 u8 prio5buff[0x4]; 1443 u8 prio4buff[0x4]; 1444 u8 prio3buff[0x4]; 1445 u8 prio2buff[0x4]; 1446 u8 prio1buff[0x4]; 1447 u8 prio0buff[0x4]; 1448 1449 u8 pm_msb[0x8]; 1450 u8 reserved_3[0x10]; 1451 u8 ctrl_buff[0x4]; 1452 u8 untagged_buff[0x4]; 1453 }; 1454 1455 struct mlx5_ifc_dcbx_app_reg_bits { 1456 u8 reserved_0[0x8]; 1457 u8 port_number[0x8]; 1458 u8 reserved_1[0x10]; 1459 1460 u8 reserved_2[0x1a]; 1461 u8 num_app_prio[0x6]; 1462 1463 u8 reserved_3[0x40]; 1464 1465 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1466 }; 1467 1468 struct mlx5_ifc_dcbx_param_reg_bits { 1469 u8 dcbx_cee_cap[0x1]; 1470 u8 dcbx_ieee_cap[0x1]; 1471 u8 dcbx_standby_cap[0x1]; 1472 u8 reserved_0[0x5]; 1473 u8 port_number[0x8]; 1474 u8 reserved_1[0xa]; 1475 u8 max_application_table_size[0x6]; 1476 1477 u8 reserved_2[0x15]; 1478 u8 version_oper[0x3]; 1479 u8 reserved_3[0x5]; 1480 u8 version_admin[0x3]; 1481 1482 u8 willing_admin[0x1]; 1483 u8 reserved_4[0x3]; 1484 u8 pfc_cap_oper[0x4]; 1485 u8 reserved_5[0x4]; 1486 u8 pfc_cap_admin[0x4]; 1487 u8 reserved_6[0x4]; 1488 u8 num_of_tc_oper[0x4]; 1489 u8 reserved_7[0x4]; 1490 u8 num_of_tc_admin[0x4]; 1491 1492 u8 remote_willing[0x1]; 1493 u8 reserved_8[0x3]; 1494 u8 remote_pfc_cap[0x4]; 1495 u8 reserved_9[0x14]; 1496 u8 remote_num_of_tc[0x4]; 1497 1498 u8 reserved_10[0x18]; 1499 u8 error[0x8]; 1500 1501 u8 reserved_11[0x160]; 1502 }; 1503 1504 struct mlx5_ifc_qhll_bits { 1505 u8 reserved_at_0[0x8]; 1506 u8 local_port[0x8]; 1507 u8 reserved_at_10[0x10]; 1508 1509 u8 reserved_at_20[0x1b]; 1510 u8 hll_time[0x5]; 1511 1512 u8 stall_en[0x1]; 1513 u8 reserved_at_41[0x1c]; 1514 u8 stall_cnt[0x3]; 1515 }; 1516 1517 struct mlx5_ifc_qetcr_reg_bits { 1518 u8 operation_type[0x2]; 1519 u8 cap_local_admin[0x1]; 1520 u8 cap_remote_admin[0x1]; 1521 u8 reserved_0[0x4]; 1522 u8 port_number[0x8]; 1523 u8 reserved_1[0x10]; 1524 1525 u8 reserved_2[0x20]; 1526 1527 u8 tc[8][0x40]; 1528 1529 u8 global_configuration[0x40]; 1530 }; 1531 1532 struct mlx5_ifc_nodnic_ring_config_reg_bits { 1533 u8 queue_address_63_32[0x20]; 1534 1535 u8 queue_address_31_12[0x14]; 1536 u8 reserved_0[0x6]; 1537 u8 log_size[0x6]; 1538 1539 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1540 1541 u8 reserved_1[0x8]; 1542 u8 queue_number[0x18]; 1543 1544 u8 q_key[0x20]; 1545 1546 u8 reserved_2[0x10]; 1547 u8 pkey_index[0x10]; 1548 1549 u8 reserved_3[0x40]; 1550 }; 1551 1552 struct mlx5_ifc_nodnic_cq_arming_word_bits { 1553 u8 reserved_0[0x8]; 1554 u8 cq_ci[0x10]; 1555 u8 reserved_1[0x8]; 1556 }; 1557 1558 enum { 1559 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1560 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1561 }; 1562 1563 enum { 1564 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1565 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1566 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1567 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1568 }; 1569 1570 struct mlx5_ifc_nodnic_event_word_bits { 1571 u8 driver_reset_needed[0x1]; 1572 u8 port_management_change_event[0x1]; 1573 u8 reserved_0[0x19]; 1574 u8 link_type[0x1]; 1575 u8 port_state[0x4]; 1576 }; 1577 1578 struct mlx5_ifc_nic_vport_change_event_bits { 1579 u8 reserved_0[0x10]; 1580 u8 vport_num[0x10]; 1581 1582 u8 reserved_1[0xc0]; 1583 }; 1584 1585 struct mlx5_ifc_pages_req_event_bits { 1586 u8 reserved_0[0x10]; 1587 u8 function_id[0x10]; 1588 1589 u8 num_pages[0x20]; 1590 1591 u8 reserved_1[0xa0]; 1592 }; 1593 1594 struct mlx5_ifc_cmd_inter_comp_event_bits { 1595 u8 command_completion_vector[0x20]; 1596 1597 u8 reserved_0[0xc0]; 1598 }; 1599 1600 struct mlx5_ifc_stall_vl_event_bits { 1601 u8 reserved_0[0x18]; 1602 u8 port_num[0x1]; 1603 u8 reserved_1[0x3]; 1604 u8 vl[0x4]; 1605 1606 u8 reserved_2[0xa0]; 1607 }; 1608 1609 struct mlx5_ifc_db_bf_congestion_event_bits { 1610 u8 event_subtype[0x8]; 1611 u8 reserved_0[0x8]; 1612 u8 congestion_level[0x8]; 1613 u8 reserved_1[0x8]; 1614 1615 u8 reserved_2[0xa0]; 1616 }; 1617 1618 struct mlx5_ifc_gpio_event_bits { 1619 u8 reserved_0[0x60]; 1620 1621 u8 gpio_event_hi[0x20]; 1622 1623 u8 gpio_event_lo[0x20]; 1624 1625 u8 reserved_1[0x40]; 1626 }; 1627 1628 struct mlx5_ifc_port_state_change_event_bits { 1629 u8 reserved_0[0x40]; 1630 1631 u8 port_num[0x4]; 1632 u8 reserved_1[0x1c]; 1633 1634 u8 reserved_2[0x80]; 1635 }; 1636 1637 struct mlx5_ifc_dropped_packet_logged_bits { 1638 u8 reserved_0[0xe0]; 1639 }; 1640 1641 enum { 1642 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1643 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1644 }; 1645 1646 struct mlx5_ifc_cq_error_bits { 1647 u8 reserved_0[0x8]; 1648 u8 cqn[0x18]; 1649 1650 u8 reserved_1[0x20]; 1651 1652 u8 reserved_2[0x18]; 1653 u8 syndrome[0x8]; 1654 1655 u8 reserved_3[0x80]; 1656 }; 1657 1658 struct mlx5_ifc_rdma_page_fault_event_bits { 1659 u8 bytes_commited[0x20]; 1660 1661 u8 r_key[0x20]; 1662 1663 u8 reserved_0[0x10]; 1664 u8 packet_len[0x10]; 1665 1666 u8 rdma_op_len[0x20]; 1667 1668 u8 rdma_va[0x40]; 1669 1670 u8 reserved_1[0x5]; 1671 u8 rdma[0x1]; 1672 u8 write[0x1]; 1673 u8 requestor[0x1]; 1674 u8 qp_number[0x18]; 1675 }; 1676 1677 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1678 u8 bytes_committed[0x20]; 1679 1680 u8 reserved_0[0x10]; 1681 u8 wqe_index[0x10]; 1682 1683 u8 reserved_1[0x10]; 1684 u8 len[0x10]; 1685 1686 u8 reserved_2[0x60]; 1687 1688 u8 reserved_3[0x5]; 1689 u8 rdma[0x1]; 1690 u8 write_read[0x1]; 1691 u8 requestor[0x1]; 1692 u8 qpn[0x18]; 1693 }; 1694 1695 enum { 1696 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1697 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1698 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1699 }; 1700 1701 struct mlx5_ifc_qp_events_bits { 1702 u8 reserved_0[0xa0]; 1703 1704 u8 type[0x8]; 1705 u8 reserved_1[0x18]; 1706 1707 u8 reserved_2[0x8]; 1708 u8 qpn_rqn_sqn[0x18]; 1709 }; 1710 1711 struct mlx5_ifc_dct_events_bits { 1712 u8 reserved_0[0xc0]; 1713 1714 u8 reserved_1[0x8]; 1715 u8 dct_number[0x18]; 1716 }; 1717 1718 struct mlx5_ifc_comp_event_bits { 1719 u8 reserved_0[0xc0]; 1720 1721 u8 reserved_1[0x8]; 1722 u8 cq_number[0x18]; 1723 }; 1724 1725 struct mlx5_ifc_fw_version_bits { 1726 u8 major[0x10]; 1727 u8 reserved_0[0x10]; 1728 1729 u8 minor[0x10]; 1730 u8 subminor[0x10]; 1731 1732 u8 second[0x8]; 1733 u8 minute[0x8]; 1734 u8 hour[0x8]; 1735 u8 reserved_1[0x8]; 1736 1737 u8 year[0x10]; 1738 u8 month[0x8]; 1739 u8 day[0x8]; 1740 }; 1741 1742 enum { 1743 MLX5_QPC_STATE_RST = 0x0, 1744 MLX5_QPC_STATE_INIT = 0x1, 1745 MLX5_QPC_STATE_RTR = 0x2, 1746 MLX5_QPC_STATE_RTS = 0x3, 1747 MLX5_QPC_STATE_SQER = 0x4, 1748 MLX5_QPC_STATE_SQD = 0x5, 1749 MLX5_QPC_STATE_ERR = 0x6, 1750 MLX5_QPC_STATE_SUSPENDED = 0x9, 1751 }; 1752 1753 enum { 1754 MLX5_QPC_ST_RC = 0x0, 1755 MLX5_QPC_ST_UC = 0x1, 1756 MLX5_QPC_ST_UD = 0x2, 1757 MLX5_QPC_ST_XRC = 0x3, 1758 MLX5_QPC_ST_DCI = 0x5, 1759 MLX5_QPC_ST_QP0 = 0x7, 1760 MLX5_QPC_ST_QP1 = 0x8, 1761 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1762 MLX5_QPC_ST_REG_UMR = 0xc, 1763 }; 1764 1765 enum { 1766 MLX5_QP_PM_ARMED = 0x0, 1767 MLX5_QP_PM_REARM = 0x1, 1768 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1769 MLX5_QP_PM_MIGRATED = 0x3, 1770 }; 1771 1772 enum { 1773 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1774 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1775 }; 1776 1777 enum { 1778 MLX5_QPC_MTU_256_BYTES = 0x1, 1779 MLX5_QPC_MTU_512_BYTES = 0x2, 1780 MLX5_QPC_MTU_1K_BYTES = 0x3, 1781 MLX5_QPC_MTU_2K_BYTES = 0x4, 1782 MLX5_QPC_MTU_4K_BYTES = 0x5, 1783 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1784 }; 1785 1786 enum { 1787 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1788 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1789 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1790 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1791 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1792 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1793 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1794 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1795 }; 1796 1797 enum { 1798 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1799 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1800 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1801 }; 1802 1803 enum { 1804 MLX5_QPC_CS_RES_DISABLE = 0x0, 1805 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1806 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1807 }; 1808 1809 struct mlx5_ifc_qpc_bits { 1810 u8 state[0x4]; 1811 u8 lag_tx_port_affinity[0x4]; 1812 u8 st[0x8]; 1813 u8 reserved_1[0x3]; 1814 u8 pm_state[0x2]; 1815 u8 reserved_2[0x7]; 1816 u8 end_padding_mode[0x2]; 1817 u8 reserved_3[0x2]; 1818 1819 u8 wq_signature[0x1]; 1820 u8 block_lb_mc[0x1]; 1821 u8 atomic_like_write_en[0x1]; 1822 u8 latency_sensitive[0x1]; 1823 u8 reserved_4[0x1]; 1824 u8 drain_sigerr[0x1]; 1825 u8 reserved_5[0x2]; 1826 u8 pd[0x18]; 1827 1828 u8 mtu[0x3]; 1829 u8 log_msg_max[0x5]; 1830 u8 reserved_6[0x1]; 1831 u8 log_rq_size[0x4]; 1832 u8 log_rq_stride[0x3]; 1833 u8 no_sq[0x1]; 1834 u8 log_sq_size[0x4]; 1835 u8 reserved_7[0x6]; 1836 u8 rlky[0x1]; 1837 u8 ulp_stateless_offload_mode[0x4]; 1838 1839 u8 counter_set_id[0x8]; 1840 u8 uar_page[0x18]; 1841 1842 u8 reserved_8[0x8]; 1843 u8 user_index[0x18]; 1844 1845 u8 reserved_9[0x3]; 1846 u8 log_page_size[0x5]; 1847 u8 remote_qpn[0x18]; 1848 1849 struct mlx5_ifc_ads_bits primary_address_path; 1850 1851 struct mlx5_ifc_ads_bits secondary_address_path; 1852 1853 u8 log_ack_req_freq[0x4]; 1854 u8 reserved_10[0x4]; 1855 u8 log_sra_max[0x3]; 1856 u8 reserved_11[0x2]; 1857 u8 retry_count[0x3]; 1858 u8 rnr_retry[0x3]; 1859 u8 reserved_12[0x1]; 1860 u8 fre[0x1]; 1861 u8 cur_rnr_retry[0x3]; 1862 u8 cur_retry_count[0x3]; 1863 u8 reserved_13[0x5]; 1864 1865 u8 reserved_14[0x20]; 1866 1867 u8 reserved_15[0x8]; 1868 u8 next_send_psn[0x18]; 1869 1870 u8 reserved_16[0x8]; 1871 u8 cqn_snd[0x18]; 1872 1873 u8 reserved_at_400[0x8]; 1874 1875 u8 deth_sqpn[0x18]; 1876 u8 reserved_17[0x20]; 1877 1878 u8 reserved_18[0x8]; 1879 u8 last_acked_psn[0x18]; 1880 1881 u8 reserved_19[0x8]; 1882 u8 ssn[0x18]; 1883 1884 u8 reserved_20[0x8]; 1885 u8 log_rra_max[0x3]; 1886 u8 reserved_21[0x1]; 1887 u8 atomic_mode[0x4]; 1888 u8 rre[0x1]; 1889 u8 rwe[0x1]; 1890 u8 rae[0x1]; 1891 u8 reserved_22[0x1]; 1892 u8 page_offset[0x6]; 1893 u8 reserved_23[0x3]; 1894 u8 cd_slave_receive[0x1]; 1895 u8 cd_slave_send[0x1]; 1896 u8 cd_master[0x1]; 1897 1898 u8 reserved_24[0x3]; 1899 u8 min_rnr_nak[0x5]; 1900 u8 next_rcv_psn[0x18]; 1901 1902 u8 reserved_25[0x8]; 1903 u8 xrcd[0x18]; 1904 1905 u8 reserved_26[0x8]; 1906 u8 cqn_rcv[0x18]; 1907 1908 u8 dbr_addr[0x40]; 1909 1910 u8 q_key[0x20]; 1911 1912 u8 reserved_27[0x5]; 1913 u8 rq_type[0x3]; 1914 u8 srqn_rmpn[0x18]; 1915 1916 u8 reserved_28[0x8]; 1917 u8 rmsn[0x18]; 1918 1919 u8 hw_sq_wqebb_counter[0x10]; 1920 u8 sw_sq_wqebb_counter[0x10]; 1921 1922 u8 hw_rq_counter[0x20]; 1923 1924 u8 sw_rq_counter[0x20]; 1925 1926 u8 reserved_29[0x20]; 1927 1928 u8 reserved_30[0xf]; 1929 u8 cgs[0x1]; 1930 u8 cs_req[0x8]; 1931 u8 cs_res[0x8]; 1932 1933 u8 dc_access_key[0x40]; 1934 1935 u8 rdma_active[0x1]; 1936 u8 comm_est[0x1]; 1937 u8 suspended[0x1]; 1938 u8 reserved_31[0x5]; 1939 u8 send_msg_psn[0x18]; 1940 1941 u8 reserved_32[0x8]; 1942 u8 rcv_msg_psn[0x18]; 1943 1944 u8 rdma_va[0x40]; 1945 1946 u8 rdma_key[0x20]; 1947 1948 u8 reserved_33[0x20]; 1949 }; 1950 1951 struct mlx5_ifc_roce_addr_layout_bits { 1952 u8 source_l3_address[16][0x8]; 1953 1954 u8 reserved_0[0x3]; 1955 u8 vlan_valid[0x1]; 1956 u8 vlan_id[0xc]; 1957 u8 source_mac_47_32[0x10]; 1958 1959 u8 source_mac_31_0[0x20]; 1960 1961 u8 reserved_1[0x14]; 1962 u8 roce_l3_type[0x4]; 1963 u8 roce_version[0x8]; 1964 1965 u8 reserved_2[0x20]; 1966 }; 1967 1968 struct mlx5_ifc_rdbc_bits { 1969 u8 reserved_0[0x1c]; 1970 u8 type[0x4]; 1971 1972 u8 reserved_1[0x20]; 1973 1974 u8 reserved_2[0x8]; 1975 u8 psn[0x18]; 1976 1977 u8 rkey[0x20]; 1978 1979 u8 address[0x40]; 1980 1981 u8 byte_count[0x20]; 1982 1983 u8 reserved_3[0x20]; 1984 1985 u8 atomic_resp[32][0x8]; 1986 }; 1987 1988 enum { 1989 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 1990 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 1991 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 1992 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 1993 }; 1994 1995 struct mlx5_ifc_flow_context_bits { 1996 u8 reserved_0[0x20]; 1997 1998 u8 group_id[0x20]; 1999 2000 u8 reserved_1[0x8]; 2001 u8 flow_tag[0x18]; 2002 2003 u8 reserved_2[0x10]; 2004 u8 action[0x10]; 2005 2006 u8 reserved_3[0x8]; 2007 u8 destination_list_size[0x18]; 2008 2009 u8 reserved_4[0x8]; 2010 u8 flow_counter_list_size[0x18]; 2011 2012 u8 reserved_5[0x140]; 2013 2014 struct mlx5_ifc_fte_match_param_bits match_value; 2015 2016 u8 reserved_6[0x600]; 2017 2018 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2019 }; 2020 2021 enum { 2022 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2023 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2024 }; 2025 2026 struct mlx5_ifc_xrc_srqc_bits { 2027 u8 state[0x4]; 2028 u8 log_xrc_srq_size[0x4]; 2029 u8 reserved_0[0x18]; 2030 2031 u8 wq_signature[0x1]; 2032 u8 cont_srq[0x1]; 2033 u8 reserved_1[0x1]; 2034 u8 rlky[0x1]; 2035 u8 basic_cyclic_rcv_wqe[0x1]; 2036 u8 log_rq_stride[0x3]; 2037 u8 xrcd[0x18]; 2038 2039 u8 page_offset[0x6]; 2040 u8 reserved_2[0x2]; 2041 u8 cqn[0x18]; 2042 2043 u8 reserved_3[0x20]; 2044 2045 u8 reserved_4[0x2]; 2046 u8 log_page_size[0x6]; 2047 u8 user_index[0x18]; 2048 2049 u8 reserved_5[0x20]; 2050 2051 u8 reserved_6[0x8]; 2052 u8 pd[0x18]; 2053 2054 u8 lwm[0x10]; 2055 u8 wqe_cnt[0x10]; 2056 2057 u8 reserved_7[0x40]; 2058 2059 u8 db_record_addr_h[0x20]; 2060 2061 u8 db_record_addr_l[0x1e]; 2062 u8 reserved_8[0x2]; 2063 2064 u8 reserved_9[0x80]; 2065 }; 2066 2067 struct mlx5_ifc_traffic_counter_bits { 2068 u8 packets[0x40]; 2069 2070 u8 octets[0x40]; 2071 }; 2072 2073 struct mlx5_ifc_tisc_bits { 2074 u8 strict_lag_tx_port_affinity[0x1]; 2075 u8 reserved_at_1[0x3]; 2076 u8 lag_tx_port_affinity[0x04]; 2077 2078 u8 reserved_at_8[0x4]; 2079 u8 prio[0x4]; 2080 u8 reserved_1[0x10]; 2081 2082 u8 reserved_2[0x100]; 2083 2084 u8 reserved_3[0x8]; 2085 u8 transport_domain[0x18]; 2086 2087 u8 reserved_4[0x8]; 2088 u8 underlay_qpn[0x18]; 2089 2090 u8 reserved_5[0x3a0]; 2091 }; 2092 2093 enum { 2094 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2095 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2096 }; 2097 2098 enum { 2099 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2100 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2101 }; 2102 2103 enum { 2104 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2105 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2106 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2107 }; 2108 2109 enum { 2110 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2111 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2112 }; 2113 2114 struct mlx5_ifc_tirc_bits { 2115 u8 reserved_0[0x20]; 2116 2117 u8 disp_type[0x4]; 2118 u8 reserved_1[0x1c]; 2119 2120 u8 reserved_2[0x40]; 2121 2122 u8 reserved_3[0x4]; 2123 u8 lro_timeout_period_usecs[0x10]; 2124 u8 lro_enable_mask[0x4]; 2125 u8 lro_max_msg_sz[0x8]; 2126 2127 u8 reserved_4[0x40]; 2128 2129 u8 reserved_5[0x8]; 2130 u8 inline_rqn[0x18]; 2131 2132 u8 rx_hash_symmetric[0x1]; 2133 u8 reserved_6[0x1]; 2134 u8 tunneled_offload_en[0x1]; 2135 u8 reserved_7[0x5]; 2136 u8 indirect_table[0x18]; 2137 2138 u8 rx_hash_fn[0x4]; 2139 u8 reserved_8[0x2]; 2140 u8 self_lb_en[0x2]; 2141 u8 transport_domain[0x18]; 2142 2143 u8 rx_hash_toeplitz_key[10][0x20]; 2144 2145 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2146 2147 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2148 2149 u8 reserved_9[0x4c0]; 2150 }; 2151 2152 enum { 2153 MLX5_SRQC_STATE_GOOD = 0x0, 2154 MLX5_SRQC_STATE_ERROR = 0x1, 2155 }; 2156 2157 struct mlx5_ifc_srqc_bits { 2158 u8 state[0x4]; 2159 u8 log_srq_size[0x4]; 2160 u8 reserved_0[0x18]; 2161 2162 u8 wq_signature[0x1]; 2163 u8 cont_srq[0x1]; 2164 u8 reserved_1[0x1]; 2165 u8 rlky[0x1]; 2166 u8 reserved_2[0x1]; 2167 u8 log_rq_stride[0x3]; 2168 u8 xrcd[0x18]; 2169 2170 u8 page_offset[0x6]; 2171 u8 reserved_3[0x2]; 2172 u8 cqn[0x18]; 2173 2174 u8 reserved_4[0x20]; 2175 2176 u8 reserved_5[0x2]; 2177 u8 log_page_size[0x6]; 2178 u8 reserved_6[0x18]; 2179 2180 u8 reserved_7[0x20]; 2181 2182 u8 reserved_8[0x8]; 2183 u8 pd[0x18]; 2184 2185 u8 lwm[0x10]; 2186 u8 wqe_cnt[0x10]; 2187 2188 u8 reserved_9[0x40]; 2189 2190 u8 db_record_addr_h[0x20]; 2191 2192 u8 db_record_addr_l[0x1e]; 2193 u8 reserved_10[0x2]; 2194 2195 u8 reserved_11[0x80]; 2196 }; 2197 2198 enum { 2199 MLX5_SQC_STATE_RST = 0x0, 2200 MLX5_SQC_STATE_RDY = 0x1, 2201 MLX5_SQC_STATE_ERR = 0x3, 2202 }; 2203 2204 struct mlx5_ifc_sqc_bits { 2205 u8 rlkey[0x1]; 2206 u8 cd_master[0x1]; 2207 u8 fre[0x1]; 2208 u8 flush_in_error_en[0x1]; 2209 u8 allow_multi_pkt_send_wqe[0x1]; 2210 u8 min_wqe_inline_mode[0x3]; 2211 u8 state[0x4]; 2212 u8 reg_umr[0x1]; 2213 u8 allow_swp[0x1]; 2214 u8 reserved_0[0x12]; 2215 2216 u8 reserved_1[0x8]; 2217 u8 user_index[0x18]; 2218 2219 u8 reserved_2[0x8]; 2220 u8 cqn[0x18]; 2221 2222 u8 reserved_3[0x80]; 2223 2224 u8 qos_para_vport_number[0x10]; 2225 u8 packet_pacing_rate_limit_index[0x10]; 2226 2227 u8 tis_lst_sz[0x10]; 2228 u8 reserved_4[0x10]; 2229 2230 u8 reserved_5[0x40]; 2231 2232 u8 reserved_6[0x8]; 2233 u8 tis_num_0[0x18]; 2234 2235 struct mlx5_ifc_wq_bits wq; 2236 }; 2237 2238 enum { 2239 MLX5_TSAR_TYPE_DWRR = 0, 2240 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2241 MLX5_TSAR_TYPE_ETS = 2 2242 }; 2243 2244 struct mlx5_ifc_tsar_element_attributes_bits { 2245 u8 reserved_0[0x8]; 2246 u8 tsar_type[0x8]; 2247 u8 reserved_1[0x10]; 2248 }; 2249 2250 struct mlx5_ifc_vport_element_attributes_bits { 2251 u8 reserved_0[0x10]; 2252 u8 vport_number[0x10]; 2253 }; 2254 2255 struct mlx5_ifc_vport_tc_element_attributes_bits { 2256 u8 traffic_class[0x10]; 2257 u8 vport_number[0x10]; 2258 }; 2259 2260 struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2261 u8 reserved_0[0x0C]; 2262 u8 traffic_class[0x04]; 2263 u8 qos_para_vport_number[0x10]; 2264 }; 2265 2266 enum { 2267 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2268 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2269 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2270 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2271 }; 2272 2273 struct mlx5_ifc_scheduling_context_bits { 2274 u8 element_type[0x8]; 2275 u8 reserved_at_8[0x18]; 2276 2277 u8 element_attributes[0x20]; 2278 2279 u8 parent_element_id[0x20]; 2280 2281 u8 reserved_at_60[0x40]; 2282 2283 u8 bw_share[0x20]; 2284 2285 u8 max_average_bw[0x20]; 2286 2287 u8 reserved_at_e0[0x120]; 2288 }; 2289 2290 struct mlx5_ifc_rqtc_bits { 2291 u8 reserved_0[0xa0]; 2292 2293 u8 reserved_1[0x10]; 2294 u8 rqt_max_size[0x10]; 2295 2296 u8 reserved_2[0x10]; 2297 u8 rqt_actual_size[0x10]; 2298 2299 u8 reserved_3[0x6a0]; 2300 2301 struct mlx5_ifc_rq_num_bits rq_num[0]; 2302 }; 2303 2304 enum { 2305 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2306 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2307 }; 2308 2309 enum { 2310 MLX5_RQC_STATE_RST = 0x0, 2311 MLX5_RQC_STATE_RDY = 0x1, 2312 MLX5_RQC_STATE_ERR = 0x3, 2313 }; 2314 2315 enum { 2316 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2317 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2318 }; 2319 2320 struct mlx5_ifc_rqc_bits { 2321 u8 rlkey[0x1]; 2322 u8 delay_drop_en[0x1]; 2323 u8 scatter_fcs[0x1]; 2324 u8 vlan_strip_disable[0x1]; 2325 u8 mem_rq_type[0x4]; 2326 u8 state[0x4]; 2327 u8 reserved_1[0x1]; 2328 u8 flush_in_error_en[0x1]; 2329 u8 reserved_2[0x12]; 2330 2331 u8 reserved_3[0x8]; 2332 u8 user_index[0x18]; 2333 2334 u8 reserved_4[0x8]; 2335 u8 cqn[0x18]; 2336 2337 u8 counter_set_id[0x8]; 2338 u8 reserved_5[0x18]; 2339 2340 u8 reserved_6[0x8]; 2341 u8 rmpn[0x18]; 2342 2343 u8 reserved_7[0xe0]; 2344 2345 struct mlx5_ifc_wq_bits wq; 2346 }; 2347 2348 enum { 2349 MLX5_RMPC_STATE_RDY = 0x1, 2350 MLX5_RMPC_STATE_ERR = 0x3, 2351 }; 2352 2353 struct mlx5_ifc_rmpc_bits { 2354 u8 reserved_0[0x8]; 2355 u8 state[0x4]; 2356 u8 reserved_1[0x14]; 2357 2358 u8 basic_cyclic_rcv_wqe[0x1]; 2359 u8 reserved_2[0x1f]; 2360 2361 u8 reserved_3[0x140]; 2362 2363 struct mlx5_ifc_wq_bits wq; 2364 }; 2365 2366 enum { 2367 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2368 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2369 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2370 }; 2371 2372 struct mlx5_ifc_nic_vport_context_bits { 2373 u8 reserved_0[0x5]; 2374 u8 min_wqe_inline_mode[0x3]; 2375 u8 reserved_1[0x15]; 2376 u8 disable_mc_local_lb[0x1]; 2377 u8 disable_uc_local_lb[0x1]; 2378 u8 roce_en[0x1]; 2379 2380 u8 arm_change_event[0x1]; 2381 u8 reserved_2[0x1a]; 2382 u8 event_on_mtu[0x1]; 2383 u8 event_on_promisc_change[0x1]; 2384 u8 event_on_vlan_change[0x1]; 2385 u8 event_on_mc_address_change[0x1]; 2386 u8 event_on_uc_address_change[0x1]; 2387 2388 u8 reserved_3[0xe0]; 2389 2390 u8 reserved_4[0x10]; 2391 u8 mtu[0x10]; 2392 2393 u8 system_image_guid[0x40]; 2394 2395 u8 port_guid[0x40]; 2396 2397 u8 node_guid[0x40]; 2398 2399 u8 reserved_5[0x140]; 2400 2401 u8 qkey_violation_counter[0x10]; 2402 u8 reserved_6[0x10]; 2403 2404 u8 reserved_7[0x420]; 2405 2406 u8 promisc_uc[0x1]; 2407 u8 promisc_mc[0x1]; 2408 u8 promisc_all[0x1]; 2409 u8 reserved_8[0x2]; 2410 u8 allowed_list_type[0x3]; 2411 u8 reserved_9[0xc]; 2412 u8 allowed_list_size[0xc]; 2413 2414 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2415 2416 u8 reserved_10[0x20]; 2417 2418 u8 current_uc_mac_address[0][0x40]; 2419 }; 2420 2421 enum { 2422 MLX5_ACCESS_MODE_PA = 0x0, 2423 MLX5_ACCESS_MODE_MTT = 0x1, 2424 MLX5_ACCESS_MODE_KLM = 0x2, 2425 }; 2426 2427 struct mlx5_ifc_mkc_bits { 2428 u8 reserved_0[0x1]; 2429 u8 free[0x1]; 2430 u8 reserved_1[0xd]; 2431 u8 small_fence_on_rdma_read_response[0x1]; 2432 u8 umr_en[0x1]; 2433 u8 a[0x1]; 2434 u8 rw[0x1]; 2435 u8 rr[0x1]; 2436 u8 lw[0x1]; 2437 u8 lr[0x1]; 2438 u8 access_mode[0x2]; 2439 u8 reserved_2[0x8]; 2440 2441 u8 qpn[0x18]; 2442 u8 mkey_7_0[0x8]; 2443 2444 u8 reserved_3[0x20]; 2445 2446 u8 length64[0x1]; 2447 u8 bsf_en[0x1]; 2448 u8 sync_umr[0x1]; 2449 u8 reserved_4[0x2]; 2450 u8 expected_sigerr_count[0x1]; 2451 u8 reserved_5[0x1]; 2452 u8 en_rinval[0x1]; 2453 u8 pd[0x18]; 2454 2455 u8 start_addr[0x40]; 2456 2457 u8 len[0x40]; 2458 2459 u8 bsf_octword_size[0x20]; 2460 2461 u8 reserved_6[0x80]; 2462 2463 u8 translations_octword_size[0x20]; 2464 2465 u8 reserved_7[0x1b]; 2466 u8 log_page_size[0x5]; 2467 2468 u8 reserved_8[0x20]; 2469 }; 2470 2471 struct mlx5_ifc_pkey_bits { 2472 u8 reserved_0[0x10]; 2473 u8 pkey[0x10]; 2474 }; 2475 2476 struct mlx5_ifc_array128_auto_bits { 2477 u8 array128_auto[16][0x8]; 2478 }; 2479 2480 enum { 2481 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2482 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2483 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2484 }; 2485 2486 enum { 2487 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2488 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2489 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2490 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2491 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2492 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2493 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2494 }; 2495 2496 enum { 2497 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2498 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2499 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2500 }; 2501 2502 enum { 2503 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2504 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2505 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2506 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2507 }; 2508 2509 enum { 2510 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2511 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2512 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2513 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2514 }; 2515 2516 struct mlx5_ifc_hca_vport_context_bits { 2517 u8 field_select[0x20]; 2518 2519 u8 reserved_0[0xe0]; 2520 2521 u8 sm_virt_aware[0x1]; 2522 u8 has_smi[0x1]; 2523 u8 has_raw[0x1]; 2524 u8 grh_required[0x1]; 2525 u8 reserved_1[0x1]; 2526 u8 min_wqe_inline_mode[0x3]; 2527 u8 reserved_2[0x8]; 2528 u8 port_physical_state[0x4]; 2529 u8 vport_state_policy[0x4]; 2530 u8 port_state[0x4]; 2531 u8 vport_state[0x4]; 2532 2533 u8 reserved_3[0x20]; 2534 2535 u8 system_image_guid[0x40]; 2536 2537 u8 port_guid[0x40]; 2538 2539 u8 node_guid[0x40]; 2540 2541 u8 cap_mask1[0x20]; 2542 2543 u8 cap_mask1_field_select[0x20]; 2544 2545 u8 cap_mask2[0x20]; 2546 2547 u8 cap_mask2_field_select[0x20]; 2548 2549 u8 reserved_4[0x80]; 2550 2551 u8 lid[0x10]; 2552 u8 reserved_5[0x4]; 2553 u8 init_type_reply[0x4]; 2554 u8 lmc[0x3]; 2555 u8 subnet_timeout[0x5]; 2556 2557 u8 sm_lid[0x10]; 2558 u8 sm_sl[0x4]; 2559 u8 reserved_6[0xc]; 2560 2561 u8 qkey_violation_counter[0x10]; 2562 u8 pkey_violation_counter[0x10]; 2563 2564 u8 reserved_7[0xca0]; 2565 }; 2566 2567 union mlx5_ifc_hca_cap_union_bits { 2568 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2569 struct mlx5_ifc_odp_cap_bits odp_cap; 2570 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2571 struct mlx5_ifc_roce_cap_bits roce_cap; 2572 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2573 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2574 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2575 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2576 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2577 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2578 struct mlx5_ifc_qos_cap_bits qos_cap; 2579 u8 reserved_0[0x8000]; 2580 }; 2581 2582 enum { 2583 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 2584 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 2585 }; 2586 2587 struct mlx5_ifc_flow_table_context_bits { 2588 u8 encap_en[0x1]; 2589 u8 decap_en[0x1]; 2590 u8 reserved_at_2[0x2]; 2591 u8 table_miss_action[0x4]; 2592 u8 level[0x8]; 2593 u8 reserved_at_10[0x8]; 2594 u8 log_size[0x8]; 2595 2596 u8 reserved_at_20[0x8]; 2597 u8 table_miss_id[0x18]; 2598 2599 u8 reserved_at_40[0x8]; 2600 u8 lag_master_next_table_id[0x18]; 2601 2602 u8 reserved_at_60[0xe0]; 2603 }; 2604 2605 struct mlx5_ifc_esw_vport_context_bits { 2606 u8 reserved_0[0x3]; 2607 u8 vport_svlan_strip[0x1]; 2608 u8 vport_cvlan_strip[0x1]; 2609 u8 vport_svlan_insert[0x1]; 2610 u8 vport_cvlan_insert[0x2]; 2611 u8 reserved_1[0x18]; 2612 2613 u8 reserved_2[0x20]; 2614 2615 u8 svlan_cfi[0x1]; 2616 u8 svlan_pcp[0x3]; 2617 u8 svlan_id[0xc]; 2618 u8 cvlan_cfi[0x1]; 2619 u8 cvlan_pcp[0x3]; 2620 u8 cvlan_id[0xc]; 2621 2622 u8 reserved_3[0x7a0]; 2623 }; 2624 2625 enum { 2626 MLX5_EQC_STATUS_OK = 0x0, 2627 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2628 }; 2629 2630 enum { 2631 MLX5_EQ_STATE_ARMED = 0x9, 2632 MLX5_EQ_STATE_FIRED = 0xa, 2633 }; 2634 2635 struct mlx5_ifc_eqc_bits { 2636 u8 status[0x4]; 2637 u8 reserved_0[0x9]; 2638 u8 ec[0x1]; 2639 u8 oi[0x1]; 2640 u8 reserved_1[0x5]; 2641 u8 st[0x4]; 2642 u8 reserved_2[0x8]; 2643 2644 u8 reserved_3[0x20]; 2645 2646 u8 reserved_4[0x14]; 2647 u8 page_offset[0x6]; 2648 u8 reserved_5[0x6]; 2649 2650 u8 reserved_6[0x3]; 2651 u8 log_eq_size[0x5]; 2652 u8 uar_page[0x18]; 2653 2654 u8 reserved_7[0x20]; 2655 2656 u8 reserved_8[0x18]; 2657 u8 intr[0x8]; 2658 2659 u8 reserved_9[0x3]; 2660 u8 log_page_size[0x5]; 2661 u8 reserved_10[0x18]; 2662 2663 u8 reserved_11[0x60]; 2664 2665 u8 reserved_12[0x8]; 2666 u8 consumer_counter[0x18]; 2667 2668 u8 reserved_13[0x8]; 2669 u8 producer_counter[0x18]; 2670 2671 u8 reserved_14[0x80]; 2672 }; 2673 2674 enum { 2675 MLX5_DCTC_STATE_ACTIVE = 0x0, 2676 MLX5_DCTC_STATE_DRAINING = 0x1, 2677 MLX5_DCTC_STATE_DRAINED = 0x2, 2678 }; 2679 2680 enum { 2681 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2682 MLX5_DCTC_CS_RES_NA = 0x1, 2683 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2684 }; 2685 2686 enum { 2687 MLX5_DCTC_MTU_256_BYTES = 0x1, 2688 MLX5_DCTC_MTU_512_BYTES = 0x2, 2689 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2690 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2691 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2692 }; 2693 2694 struct mlx5_ifc_dctc_bits { 2695 u8 reserved_0[0x4]; 2696 u8 state[0x4]; 2697 u8 reserved_1[0x18]; 2698 2699 u8 reserved_2[0x8]; 2700 u8 user_index[0x18]; 2701 2702 u8 reserved_3[0x8]; 2703 u8 cqn[0x18]; 2704 2705 u8 counter_set_id[0x8]; 2706 u8 atomic_mode[0x4]; 2707 u8 rre[0x1]; 2708 u8 rwe[0x1]; 2709 u8 rae[0x1]; 2710 u8 atomic_like_write_en[0x1]; 2711 u8 latency_sensitive[0x1]; 2712 u8 rlky[0x1]; 2713 u8 reserved_4[0xe]; 2714 2715 u8 reserved_5[0x8]; 2716 u8 cs_res[0x8]; 2717 u8 reserved_6[0x3]; 2718 u8 min_rnr_nak[0x5]; 2719 u8 reserved_7[0x8]; 2720 2721 u8 reserved_8[0x8]; 2722 u8 srqn[0x18]; 2723 2724 u8 reserved_9[0x8]; 2725 u8 pd[0x18]; 2726 2727 u8 tclass[0x8]; 2728 u8 reserved_10[0x4]; 2729 u8 flow_label[0x14]; 2730 2731 u8 dc_access_key[0x40]; 2732 2733 u8 reserved_11[0x5]; 2734 u8 mtu[0x3]; 2735 u8 port[0x8]; 2736 u8 pkey_index[0x10]; 2737 2738 u8 reserved_12[0x8]; 2739 u8 my_addr_index[0x8]; 2740 u8 reserved_13[0x8]; 2741 u8 hop_limit[0x8]; 2742 2743 u8 dc_access_key_violation_count[0x20]; 2744 2745 u8 reserved_14[0x14]; 2746 u8 dei_cfi[0x1]; 2747 u8 eth_prio[0x3]; 2748 u8 ecn[0x2]; 2749 u8 dscp[0x6]; 2750 2751 u8 reserved_15[0x40]; 2752 }; 2753 2754 enum { 2755 MLX5_CQC_STATUS_OK = 0x0, 2756 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2757 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2758 }; 2759 2760 enum { 2761 CQE_SIZE_64 = 0x0, 2762 CQE_SIZE_128 = 0x1, 2763 }; 2764 2765 enum { 2766 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2767 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2768 }; 2769 2770 enum { 2771 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 2772 MLX5_CQ_STATE_ARMED = 0x9, 2773 MLX5_CQ_STATE_FIRED = 0xa, 2774 }; 2775 2776 struct mlx5_ifc_cqc_bits { 2777 u8 status[0x4]; 2778 u8 reserved_0[0x4]; 2779 u8 cqe_sz[0x3]; 2780 u8 cc[0x1]; 2781 u8 reserved_1[0x1]; 2782 u8 scqe_break_moderation_en[0x1]; 2783 u8 oi[0x1]; 2784 u8 cq_period_mode[0x2]; 2785 u8 cqe_compression_en[0x1]; 2786 u8 mini_cqe_res_format[0x2]; 2787 u8 st[0x4]; 2788 u8 reserved_2[0x8]; 2789 2790 u8 reserved_3[0x20]; 2791 2792 u8 reserved_4[0x14]; 2793 u8 page_offset[0x6]; 2794 u8 reserved_5[0x6]; 2795 2796 u8 reserved_6[0x3]; 2797 u8 log_cq_size[0x5]; 2798 u8 uar_page[0x18]; 2799 2800 u8 reserved_7[0x4]; 2801 u8 cq_period[0xc]; 2802 u8 cq_max_count[0x10]; 2803 2804 u8 reserved_8[0x18]; 2805 u8 c_eqn[0x8]; 2806 2807 u8 reserved_9[0x3]; 2808 u8 log_page_size[0x5]; 2809 u8 reserved_10[0x18]; 2810 2811 u8 reserved_11[0x20]; 2812 2813 u8 reserved_12[0x8]; 2814 u8 last_notified_index[0x18]; 2815 2816 u8 reserved_13[0x8]; 2817 u8 last_solicit_index[0x18]; 2818 2819 u8 reserved_14[0x8]; 2820 u8 consumer_counter[0x18]; 2821 2822 u8 reserved_15[0x8]; 2823 u8 producer_counter[0x18]; 2824 2825 u8 reserved_16[0x40]; 2826 2827 u8 dbr_addr[0x40]; 2828 }; 2829 2830 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2831 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2832 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2833 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2834 u8 reserved_0[0x800]; 2835 }; 2836 2837 struct mlx5_ifc_query_adapter_param_block_bits { 2838 u8 reserved_0[0xc0]; 2839 2840 u8 reserved_1[0x8]; 2841 u8 ieee_vendor_id[0x18]; 2842 2843 u8 reserved_2[0x10]; 2844 u8 vsd_vendor_id[0x10]; 2845 2846 u8 vsd[208][0x8]; 2847 2848 u8 vsd_contd_psid[16][0x8]; 2849 }; 2850 2851 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2852 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2853 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2854 u8 reserved_0[0x20]; 2855 }; 2856 2857 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2858 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2859 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2860 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2861 u8 reserved_0[0x20]; 2862 }; 2863 2864 struct mlx5_ifc_bufferx_reg_bits { 2865 u8 reserved_0[0x6]; 2866 u8 lossy[0x1]; 2867 u8 epsb[0x1]; 2868 u8 reserved_1[0xc]; 2869 u8 size[0xc]; 2870 2871 u8 xoff_threshold[0x10]; 2872 u8 xon_threshold[0x10]; 2873 }; 2874 2875 struct mlx5_ifc_config_item_bits { 2876 u8 valid[0x2]; 2877 u8 reserved_0[0x2]; 2878 u8 header_type[0x2]; 2879 u8 reserved_1[0x2]; 2880 u8 default_location[0x1]; 2881 u8 reserved_2[0x7]; 2882 u8 version[0x4]; 2883 u8 reserved_3[0x3]; 2884 u8 length[0x9]; 2885 2886 u8 type[0x20]; 2887 2888 u8 reserved_4[0x10]; 2889 u8 crc16[0x10]; 2890 }; 2891 2892 struct mlx5_ifc_nodnic_port_config_reg_bits { 2893 struct mlx5_ifc_nodnic_event_word_bits event; 2894 2895 u8 network_en[0x1]; 2896 u8 dma_en[0x1]; 2897 u8 promisc_en[0x1]; 2898 u8 promisc_multicast_en[0x1]; 2899 u8 reserved_0[0x17]; 2900 u8 receive_filter_en[0x5]; 2901 2902 u8 reserved_1[0x10]; 2903 u8 mac_47_32[0x10]; 2904 2905 u8 mac_31_0[0x20]; 2906 2907 u8 receive_filters_mgid_mac[64][0x8]; 2908 2909 u8 gid[16][0x8]; 2910 2911 u8 reserved_2[0x10]; 2912 u8 lid[0x10]; 2913 2914 u8 reserved_3[0xc]; 2915 u8 sm_sl[0x4]; 2916 u8 sm_lid[0x10]; 2917 2918 u8 completion_address_63_32[0x20]; 2919 2920 u8 completion_address_31_12[0x14]; 2921 u8 reserved_4[0x6]; 2922 u8 log_cq_size[0x6]; 2923 2924 u8 working_buffer_address_63_32[0x20]; 2925 2926 u8 working_buffer_address_31_12[0x14]; 2927 u8 reserved_5[0xc]; 2928 2929 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 2930 2931 u8 pkey_index[0x10]; 2932 u8 pkey[0x10]; 2933 2934 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 2935 2936 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 2937 2938 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 2939 2940 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 2941 2942 u8 reserved_6[0x400]; 2943 }; 2944 2945 union mlx5_ifc_event_auto_bits { 2946 struct mlx5_ifc_comp_event_bits comp_event; 2947 struct mlx5_ifc_dct_events_bits dct_events; 2948 struct mlx5_ifc_qp_events_bits qp_events; 2949 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 2950 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 2951 struct mlx5_ifc_cq_error_bits cq_error; 2952 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 2953 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 2954 struct mlx5_ifc_gpio_event_bits gpio_event; 2955 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 2956 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 2957 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 2958 struct mlx5_ifc_pages_req_event_bits pages_req_event; 2959 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 2960 u8 reserved_0[0xe0]; 2961 }; 2962 2963 struct mlx5_ifc_health_buffer_bits { 2964 u8 reserved_0[0x100]; 2965 2966 u8 assert_existptr[0x20]; 2967 2968 u8 assert_callra[0x20]; 2969 2970 u8 reserved_1[0x40]; 2971 2972 u8 fw_version[0x20]; 2973 2974 u8 hw_id[0x20]; 2975 2976 u8 reserved_2[0x20]; 2977 2978 u8 irisc_index[0x8]; 2979 u8 synd[0x8]; 2980 u8 ext_synd[0x10]; 2981 }; 2982 2983 struct mlx5_ifc_register_loopback_control_bits { 2984 u8 no_lb[0x1]; 2985 u8 reserved_0[0x7]; 2986 u8 port[0x8]; 2987 u8 reserved_1[0x10]; 2988 2989 u8 reserved_2[0x60]; 2990 }; 2991 2992 struct mlx5_ifc_lrh_bits { 2993 u8 vl[4]; 2994 u8 lver[4]; 2995 u8 sl[4]; 2996 u8 reserved2[2]; 2997 u8 lnh[2]; 2998 u8 dlid[16]; 2999 u8 reserved5[5]; 3000 u8 pkt_len[11]; 3001 u8 slid[16]; 3002 }; 3003 3004 struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3005 u8 reserved_0[0x40]; 3006 3007 u8 reserved_1[0x10]; 3008 u8 rol_mode[0x8]; 3009 u8 wol_mode[0x8]; 3010 }; 3011 3012 struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3013 u8 reserved_0[0x40]; 3014 3015 u8 rol_mode_valid[0x1]; 3016 u8 wol_mode_valid[0x1]; 3017 u8 reserved_1[0xe]; 3018 u8 rol_mode[0x8]; 3019 u8 wol_mode[0x8]; 3020 3021 u8 reserved_2[0x7a0]; 3022 }; 3023 3024 struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3025 u8 virtual_mac_en[0x1]; 3026 u8 mac_aux_v[0x1]; 3027 u8 reserved_0[0x1e]; 3028 3029 u8 reserved_1[0x40]; 3030 3031 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3032 3033 u8 reserved_2[0x760]; 3034 }; 3035 3036 struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3037 u8 virtual_mac_en[0x1]; 3038 u8 mac_aux_v[0x1]; 3039 u8 reserved_0[0x1e]; 3040 3041 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3042 3043 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3044 3045 u8 reserved_1[0x760]; 3046 }; 3047 3048 struct mlx5_ifc_icmd_query_fw_info_out_bits { 3049 struct mlx5_ifc_fw_version_bits fw_version; 3050 3051 u8 reserved_0[0x10]; 3052 u8 hash_signature[0x10]; 3053 3054 u8 psid[16][0x8]; 3055 3056 u8 reserved_1[0x6e0]; 3057 }; 3058 3059 struct mlx5_ifc_icmd_query_cap_in_bits { 3060 u8 reserved_0[0x10]; 3061 u8 capability_group[0x10]; 3062 }; 3063 3064 struct mlx5_ifc_icmd_query_cap_general_bits { 3065 u8 nv_access[0x1]; 3066 u8 fw_info_psid[0x1]; 3067 u8 reserved_0[0x1e]; 3068 3069 u8 reserved_1[0x16]; 3070 u8 rol_s[0x1]; 3071 u8 rol_g[0x1]; 3072 u8 reserved_2[0x1]; 3073 u8 wol_s[0x1]; 3074 u8 wol_g[0x1]; 3075 u8 wol_a[0x1]; 3076 u8 wol_b[0x1]; 3077 u8 wol_m[0x1]; 3078 u8 wol_u[0x1]; 3079 u8 wol_p[0x1]; 3080 }; 3081 3082 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3083 u8 status[0x8]; 3084 u8 reserved_0[0x18]; 3085 3086 u8 reserved_1[0x7e0]; 3087 }; 3088 3089 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3090 u8 status[0x8]; 3091 u8 reserved_0[0x18]; 3092 3093 u8 reserved_1[0x7e0]; 3094 }; 3095 3096 struct mlx5_ifc_icmd_ocbb_init_in_bits { 3097 u8 address_hi[0x20]; 3098 3099 u8 address_lo[0x20]; 3100 3101 u8 reserved_0[0x7c0]; 3102 }; 3103 3104 struct mlx5_ifc_icmd_init_ocsd_in_bits { 3105 u8 reserved_0[0x20]; 3106 3107 u8 address_hi[0x20]; 3108 3109 u8 address_lo[0x20]; 3110 3111 u8 reserved_1[0x7a0]; 3112 }; 3113 3114 struct mlx5_ifc_icmd_access_reg_out_bits { 3115 u8 reserved_0[0x11]; 3116 u8 status[0x7]; 3117 u8 reserved_1[0x8]; 3118 3119 u8 register_id[0x10]; 3120 u8 reserved_2[0x10]; 3121 3122 u8 reserved_3[0x40]; 3123 3124 u8 reserved_4[0x5]; 3125 u8 len[0xb]; 3126 u8 reserved_5[0x10]; 3127 3128 u8 register_data[0][0x20]; 3129 }; 3130 3131 enum { 3132 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3133 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3134 }; 3135 3136 struct mlx5_ifc_icmd_access_reg_in_bits { 3137 u8 constant_1[0x5]; 3138 u8 constant_2[0xb]; 3139 u8 reserved_0[0x10]; 3140 3141 u8 register_id[0x10]; 3142 u8 reserved_1[0x1]; 3143 u8 method[0x7]; 3144 u8 constant_3[0x8]; 3145 3146 u8 reserved_2[0x40]; 3147 3148 u8 constant_4[0x5]; 3149 u8 len[0xb]; 3150 u8 reserved_3[0x10]; 3151 3152 u8 register_data[0][0x20]; 3153 }; 3154 3155 struct mlx5_ifc_teardown_hca_out_bits { 3156 u8 status[0x8]; 3157 u8 reserved_0[0x18]; 3158 3159 u8 syndrome[0x20]; 3160 3161 u8 reserved_1[0x40]; 3162 }; 3163 3164 enum { 3165 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3166 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1, 3167 }; 3168 3169 struct mlx5_ifc_teardown_hca_in_bits { 3170 u8 opcode[0x10]; 3171 u8 reserved_0[0x10]; 3172 3173 u8 reserved_1[0x10]; 3174 u8 op_mod[0x10]; 3175 3176 u8 reserved_2[0x10]; 3177 u8 profile[0x10]; 3178 3179 u8 reserved_3[0x20]; 3180 }; 3181 3182 struct mlx5_ifc_set_delay_drop_params_out_bits { 3183 u8 status[0x8]; 3184 u8 reserved_at_8[0x18]; 3185 3186 u8 syndrome[0x20]; 3187 3188 u8 reserved_at_40[0x40]; 3189 }; 3190 3191 struct mlx5_ifc_set_delay_drop_params_in_bits { 3192 u8 opcode[0x10]; 3193 u8 reserved_at_10[0x10]; 3194 3195 u8 reserved_at_20[0x10]; 3196 u8 op_mod[0x10]; 3197 3198 u8 reserved_at_40[0x20]; 3199 3200 u8 reserved_at_60[0x10]; 3201 u8 delay_drop_timeout[0x10]; 3202 }; 3203 3204 struct mlx5_ifc_query_delay_drop_params_out_bits { 3205 u8 status[0x8]; 3206 u8 reserved_at_8[0x18]; 3207 3208 u8 syndrome[0x20]; 3209 3210 u8 reserved_at_40[0x20]; 3211 3212 u8 reserved_at_60[0x10]; 3213 u8 delay_drop_timeout[0x10]; 3214 }; 3215 3216 struct mlx5_ifc_query_delay_drop_params_in_bits { 3217 u8 opcode[0x10]; 3218 u8 reserved_at_10[0x10]; 3219 3220 u8 reserved_at_20[0x10]; 3221 u8 op_mod[0x10]; 3222 3223 u8 reserved_at_40[0x40]; 3224 }; 3225 3226 struct mlx5_ifc_suspend_qp_out_bits { 3227 u8 status[0x8]; 3228 u8 reserved_0[0x18]; 3229 3230 u8 syndrome[0x20]; 3231 3232 u8 reserved_1[0x40]; 3233 }; 3234 3235 struct mlx5_ifc_suspend_qp_in_bits { 3236 u8 opcode[0x10]; 3237 u8 reserved_0[0x10]; 3238 3239 u8 reserved_1[0x10]; 3240 u8 op_mod[0x10]; 3241 3242 u8 reserved_2[0x8]; 3243 u8 qpn[0x18]; 3244 3245 u8 reserved_3[0x20]; 3246 }; 3247 3248 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3249 u8 status[0x8]; 3250 u8 reserved_0[0x18]; 3251 3252 u8 syndrome[0x20]; 3253 3254 u8 reserved_1[0x40]; 3255 }; 3256 3257 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3258 u8 opcode[0x10]; 3259 u8 reserved_0[0x10]; 3260 3261 u8 reserved_1[0x10]; 3262 u8 op_mod[0x10]; 3263 3264 u8 reserved_2[0x8]; 3265 u8 qpn[0x18]; 3266 3267 u8 reserved_3[0x20]; 3268 3269 u8 opt_param_mask[0x20]; 3270 3271 u8 reserved_4[0x20]; 3272 3273 struct mlx5_ifc_qpc_bits qpc; 3274 3275 u8 reserved_5[0x80]; 3276 }; 3277 3278 struct mlx5_ifc_sqd2rts_qp_out_bits { 3279 u8 status[0x8]; 3280 u8 reserved_0[0x18]; 3281 3282 u8 syndrome[0x20]; 3283 3284 u8 reserved_1[0x40]; 3285 }; 3286 3287 struct mlx5_ifc_sqd2rts_qp_in_bits { 3288 u8 opcode[0x10]; 3289 u8 reserved_0[0x10]; 3290 3291 u8 reserved_1[0x10]; 3292 u8 op_mod[0x10]; 3293 3294 u8 reserved_2[0x8]; 3295 u8 qpn[0x18]; 3296 3297 u8 reserved_3[0x20]; 3298 3299 u8 opt_param_mask[0x20]; 3300 3301 u8 reserved_4[0x20]; 3302 3303 struct mlx5_ifc_qpc_bits qpc; 3304 3305 u8 reserved_5[0x80]; 3306 }; 3307 3308 struct mlx5_ifc_set_wol_rol_out_bits { 3309 u8 status[0x8]; 3310 u8 reserved_0[0x18]; 3311 3312 u8 syndrome[0x20]; 3313 3314 u8 reserved_1[0x40]; 3315 }; 3316 3317 struct mlx5_ifc_set_wol_rol_in_bits { 3318 u8 opcode[0x10]; 3319 u8 reserved_0[0x10]; 3320 3321 u8 reserved_1[0x10]; 3322 u8 op_mod[0x10]; 3323 3324 u8 rol_mode_valid[0x1]; 3325 u8 wol_mode_valid[0x1]; 3326 u8 reserved_2[0xe]; 3327 u8 rol_mode[0x8]; 3328 u8 wol_mode[0x8]; 3329 3330 u8 reserved_3[0x20]; 3331 }; 3332 3333 struct mlx5_ifc_set_roce_address_out_bits { 3334 u8 status[0x8]; 3335 u8 reserved_0[0x18]; 3336 3337 u8 syndrome[0x20]; 3338 3339 u8 reserved_1[0x40]; 3340 }; 3341 3342 struct mlx5_ifc_set_roce_address_in_bits { 3343 u8 opcode[0x10]; 3344 u8 reserved_0[0x10]; 3345 3346 u8 reserved_1[0x10]; 3347 u8 op_mod[0x10]; 3348 3349 u8 roce_address_index[0x10]; 3350 u8 reserved_2[0x10]; 3351 3352 u8 reserved_3[0x20]; 3353 3354 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3355 }; 3356 3357 struct mlx5_ifc_set_rdb_out_bits { 3358 u8 status[0x8]; 3359 u8 reserved_0[0x18]; 3360 3361 u8 syndrome[0x20]; 3362 3363 u8 reserved_1[0x40]; 3364 }; 3365 3366 struct mlx5_ifc_set_rdb_in_bits { 3367 u8 opcode[0x10]; 3368 u8 reserved_0[0x10]; 3369 3370 u8 reserved_1[0x10]; 3371 u8 op_mod[0x10]; 3372 3373 u8 reserved_2[0x8]; 3374 u8 qpn[0x18]; 3375 3376 u8 reserved_3[0x18]; 3377 u8 rdb_list_size[0x8]; 3378 3379 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3380 }; 3381 3382 struct mlx5_ifc_set_mad_demux_out_bits { 3383 u8 status[0x8]; 3384 u8 reserved_0[0x18]; 3385 3386 u8 syndrome[0x20]; 3387 3388 u8 reserved_1[0x40]; 3389 }; 3390 3391 enum { 3392 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3393 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3394 }; 3395 3396 struct mlx5_ifc_set_mad_demux_in_bits { 3397 u8 opcode[0x10]; 3398 u8 reserved_0[0x10]; 3399 3400 u8 reserved_1[0x10]; 3401 u8 op_mod[0x10]; 3402 3403 u8 reserved_2[0x20]; 3404 3405 u8 reserved_3[0x6]; 3406 u8 demux_mode[0x2]; 3407 u8 reserved_4[0x18]; 3408 }; 3409 3410 struct mlx5_ifc_set_l2_table_entry_out_bits { 3411 u8 status[0x8]; 3412 u8 reserved_0[0x18]; 3413 3414 u8 syndrome[0x20]; 3415 3416 u8 reserved_1[0x40]; 3417 }; 3418 3419 struct mlx5_ifc_set_l2_table_entry_in_bits { 3420 u8 opcode[0x10]; 3421 u8 reserved_0[0x10]; 3422 3423 u8 reserved_1[0x10]; 3424 u8 op_mod[0x10]; 3425 3426 u8 reserved_2[0x60]; 3427 3428 u8 reserved_3[0x8]; 3429 u8 table_index[0x18]; 3430 3431 u8 reserved_4[0x20]; 3432 3433 u8 reserved_5[0x13]; 3434 u8 vlan_valid[0x1]; 3435 u8 vlan[0xc]; 3436 3437 struct mlx5_ifc_mac_address_layout_bits mac_address; 3438 3439 u8 reserved_6[0xc0]; 3440 }; 3441 3442 struct mlx5_ifc_set_issi_out_bits { 3443 u8 status[0x8]; 3444 u8 reserved_0[0x18]; 3445 3446 u8 syndrome[0x20]; 3447 3448 u8 reserved_1[0x40]; 3449 }; 3450 3451 struct mlx5_ifc_set_issi_in_bits { 3452 u8 opcode[0x10]; 3453 u8 reserved_0[0x10]; 3454 3455 u8 reserved_1[0x10]; 3456 u8 op_mod[0x10]; 3457 3458 u8 reserved_2[0x10]; 3459 u8 current_issi[0x10]; 3460 3461 u8 reserved_3[0x20]; 3462 }; 3463 3464 struct mlx5_ifc_set_hca_cap_out_bits { 3465 u8 status[0x8]; 3466 u8 reserved_0[0x18]; 3467 3468 u8 syndrome[0x20]; 3469 3470 u8 reserved_1[0x40]; 3471 }; 3472 3473 struct mlx5_ifc_set_hca_cap_in_bits { 3474 u8 opcode[0x10]; 3475 u8 reserved_0[0x10]; 3476 3477 u8 reserved_1[0x10]; 3478 u8 op_mod[0x10]; 3479 3480 u8 reserved_2[0x40]; 3481 3482 union mlx5_ifc_hca_cap_union_bits capability; 3483 }; 3484 3485 enum { 3486 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3487 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3488 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3489 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3490 }; 3491 3492 struct mlx5_ifc_set_flow_table_root_out_bits { 3493 u8 status[0x8]; 3494 u8 reserved_0[0x18]; 3495 3496 u8 syndrome[0x20]; 3497 3498 u8 reserved_1[0x40]; 3499 }; 3500 3501 struct mlx5_ifc_set_flow_table_root_in_bits { 3502 u8 opcode[0x10]; 3503 u8 reserved_0[0x10]; 3504 3505 u8 reserved_1[0x10]; 3506 u8 op_mod[0x10]; 3507 3508 u8 other_vport[0x1]; 3509 u8 reserved_2[0xf]; 3510 u8 vport_number[0x10]; 3511 3512 u8 reserved_3[0x20]; 3513 3514 u8 table_type[0x8]; 3515 u8 reserved_4[0x18]; 3516 3517 u8 reserved_5[0x8]; 3518 u8 table_id[0x18]; 3519 3520 u8 reserved_6[0x8]; 3521 u8 underlay_qpn[0x18]; 3522 3523 u8 reserved_7[0x120]; 3524 }; 3525 3526 struct mlx5_ifc_set_fte_out_bits { 3527 u8 status[0x8]; 3528 u8 reserved_0[0x18]; 3529 3530 u8 syndrome[0x20]; 3531 3532 u8 reserved_1[0x40]; 3533 }; 3534 3535 struct mlx5_ifc_set_fte_in_bits { 3536 u8 opcode[0x10]; 3537 u8 reserved_0[0x10]; 3538 3539 u8 reserved_1[0x10]; 3540 u8 op_mod[0x10]; 3541 3542 u8 other_vport[0x1]; 3543 u8 reserved_2[0xf]; 3544 u8 vport_number[0x10]; 3545 3546 u8 reserved_3[0x20]; 3547 3548 u8 table_type[0x8]; 3549 u8 reserved_4[0x18]; 3550 3551 u8 reserved_5[0x8]; 3552 u8 table_id[0x18]; 3553 3554 u8 reserved_6[0x18]; 3555 u8 modify_enable_mask[0x8]; 3556 3557 u8 reserved_7[0x20]; 3558 3559 u8 flow_index[0x20]; 3560 3561 u8 reserved_8[0xe0]; 3562 3563 struct mlx5_ifc_flow_context_bits flow_context; 3564 }; 3565 3566 struct mlx5_ifc_set_driver_version_out_bits { 3567 u8 status[0x8]; 3568 u8 reserved_0[0x18]; 3569 3570 u8 syndrome[0x20]; 3571 3572 u8 reserved_1[0x40]; 3573 }; 3574 3575 struct mlx5_ifc_set_driver_version_in_bits { 3576 u8 opcode[0x10]; 3577 u8 reserved_0[0x10]; 3578 3579 u8 reserved_1[0x10]; 3580 u8 op_mod[0x10]; 3581 3582 u8 reserved_2[0x40]; 3583 3584 u8 driver_version[64][0x8]; 3585 }; 3586 3587 struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3588 u8 status[0x8]; 3589 u8 reserved_0[0x18]; 3590 3591 u8 syndrome[0x20]; 3592 3593 u8 reserved_1[0x40]; 3594 }; 3595 3596 struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3597 u8 opcode[0x10]; 3598 u8 reserved_0[0x10]; 3599 3600 u8 reserved_1[0x10]; 3601 u8 op_mod[0x10]; 3602 3603 u8 enable[0x1]; 3604 u8 reserved_2[0x1f]; 3605 3606 u8 reserved_3[0x160]; 3607 3608 struct mlx5_ifc_cmd_pas_bits pas; 3609 }; 3610 3611 struct mlx5_ifc_set_burst_size_out_bits { 3612 u8 status[0x8]; 3613 u8 reserved_0[0x18]; 3614 3615 u8 syndrome[0x20]; 3616 3617 u8 reserved_1[0x40]; 3618 }; 3619 3620 struct mlx5_ifc_set_burst_size_in_bits { 3621 u8 opcode[0x10]; 3622 u8 reserved_0[0x10]; 3623 3624 u8 reserved_1[0x10]; 3625 u8 op_mod[0x10]; 3626 3627 u8 reserved_2[0x20]; 3628 3629 u8 reserved_3[0x9]; 3630 u8 device_burst_size[0x17]; 3631 }; 3632 3633 struct mlx5_ifc_rts2rts_qp_out_bits { 3634 u8 status[0x8]; 3635 u8 reserved_0[0x18]; 3636 3637 u8 syndrome[0x20]; 3638 3639 u8 reserved_1[0x40]; 3640 }; 3641 3642 struct mlx5_ifc_rts2rts_qp_in_bits { 3643 u8 opcode[0x10]; 3644 u8 reserved_0[0x10]; 3645 3646 u8 reserved_1[0x10]; 3647 u8 op_mod[0x10]; 3648 3649 u8 reserved_2[0x8]; 3650 u8 qpn[0x18]; 3651 3652 u8 reserved_3[0x20]; 3653 3654 u8 opt_param_mask[0x20]; 3655 3656 u8 reserved_4[0x20]; 3657 3658 struct mlx5_ifc_qpc_bits qpc; 3659 3660 u8 reserved_5[0x80]; 3661 }; 3662 3663 struct mlx5_ifc_rtr2rts_qp_out_bits { 3664 u8 status[0x8]; 3665 u8 reserved_0[0x18]; 3666 3667 u8 syndrome[0x20]; 3668 3669 u8 reserved_1[0x40]; 3670 }; 3671 3672 struct mlx5_ifc_rtr2rts_qp_in_bits { 3673 u8 opcode[0x10]; 3674 u8 reserved_0[0x10]; 3675 3676 u8 reserved_1[0x10]; 3677 u8 op_mod[0x10]; 3678 3679 u8 reserved_2[0x8]; 3680 u8 qpn[0x18]; 3681 3682 u8 reserved_3[0x20]; 3683 3684 u8 opt_param_mask[0x20]; 3685 3686 u8 reserved_4[0x20]; 3687 3688 struct mlx5_ifc_qpc_bits qpc; 3689 3690 u8 reserved_5[0x80]; 3691 }; 3692 3693 struct mlx5_ifc_rst2init_qp_out_bits { 3694 u8 status[0x8]; 3695 u8 reserved_0[0x18]; 3696 3697 u8 syndrome[0x20]; 3698 3699 u8 reserved_1[0x40]; 3700 }; 3701 3702 struct mlx5_ifc_rst2init_qp_in_bits { 3703 u8 opcode[0x10]; 3704 u8 reserved_0[0x10]; 3705 3706 u8 reserved_1[0x10]; 3707 u8 op_mod[0x10]; 3708 3709 u8 reserved_2[0x8]; 3710 u8 qpn[0x18]; 3711 3712 u8 reserved_3[0x20]; 3713 3714 u8 opt_param_mask[0x20]; 3715 3716 u8 reserved_4[0x20]; 3717 3718 struct mlx5_ifc_qpc_bits qpc; 3719 3720 u8 reserved_5[0x80]; 3721 }; 3722 3723 struct mlx5_ifc_resume_qp_out_bits { 3724 u8 status[0x8]; 3725 u8 reserved_0[0x18]; 3726 3727 u8 syndrome[0x20]; 3728 3729 u8 reserved_1[0x40]; 3730 }; 3731 3732 struct mlx5_ifc_resume_qp_in_bits { 3733 u8 opcode[0x10]; 3734 u8 reserved_0[0x10]; 3735 3736 u8 reserved_1[0x10]; 3737 u8 op_mod[0x10]; 3738 3739 u8 reserved_2[0x8]; 3740 u8 qpn[0x18]; 3741 3742 u8 reserved_3[0x20]; 3743 }; 3744 3745 struct mlx5_ifc_query_xrc_srq_out_bits { 3746 u8 status[0x8]; 3747 u8 reserved_0[0x18]; 3748 3749 u8 syndrome[0x20]; 3750 3751 u8 reserved_1[0x40]; 3752 3753 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3754 3755 u8 reserved_2[0x600]; 3756 3757 u8 pas[0][0x40]; 3758 }; 3759 3760 struct mlx5_ifc_query_xrc_srq_in_bits { 3761 u8 opcode[0x10]; 3762 u8 reserved_0[0x10]; 3763 3764 u8 reserved_1[0x10]; 3765 u8 op_mod[0x10]; 3766 3767 u8 reserved_2[0x8]; 3768 u8 xrc_srqn[0x18]; 3769 3770 u8 reserved_3[0x20]; 3771 }; 3772 3773 struct mlx5_ifc_query_wol_rol_out_bits { 3774 u8 status[0x8]; 3775 u8 reserved_0[0x18]; 3776 3777 u8 syndrome[0x20]; 3778 3779 u8 reserved_1[0x10]; 3780 u8 rol_mode[0x8]; 3781 u8 wol_mode[0x8]; 3782 3783 u8 reserved_2[0x20]; 3784 }; 3785 3786 struct mlx5_ifc_query_wol_rol_in_bits { 3787 u8 opcode[0x10]; 3788 u8 reserved_0[0x10]; 3789 3790 u8 reserved_1[0x10]; 3791 u8 op_mod[0x10]; 3792 3793 u8 reserved_2[0x40]; 3794 }; 3795 3796 enum { 3797 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3798 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3799 }; 3800 3801 struct mlx5_ifc_query_vport_state_out_bits { 3802 u8 status[0x8]; 3803 u8 reserved_0[0x18]; 3804 3805 u8 syndrome[0x20]; 3806 3807 u8 reserved_1[0x20]; 3808 3809 u8 reserved_2[0x18]; 3810 u8 admin_state[0x4]; 3811 u8 state[0x4]; 3812 }; 3813 3814 enum { 3815 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3816 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3817 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 3818 }; 3819 3820 struct mlx5_ifc_query_vport_state_in_bits { 3821 u8 opcode[0x10]; 3822 u8 reserved_0[0x10]; 3823 3824 u8 reserved_1[0x10]; 3825 u8 op_mod[0x10]; 3826 3827 u8 other_vport[0x1]; 3828 u8 reserved_2[0xf]; 3829 u8 vport_number[0x10]; 3830 3831 u8 reserved_3[0x20]; 3832 }; 3833 3834 struct mlx5_ifc_query_vport_counter_out_bits { 3835 u8 status[0x8]; 3836 u8 reserved_0[0x18]; 3837 3838 u8 syndrome[0x20]; 3839 3840 u8 reserved_1[0x40]; 3841 3842 struct mlx5_ifc_traffic_counter_bits received_errors; 3843 3844 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3845 3846 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3847 3848 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3849 3850 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3851 3852 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3853 3854 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3855 3856 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3857 3858 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3859 3860 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3861 3862 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3863 3864 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3865 3866 u8 reserved_2[0xa00]; 3867 }; 3868 3869 enum { 3870 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3871 }; 3872 3873 struct mlx5_ifc_query_vport_counter_in_bits { 3874 u8 opcode[0x10]; 3875 u8 reserved_0[0x10]; 3876 3877 u8 reserved_1[0x10]; 3878 u8 op_mod[0x10]; 3879 3880 u8 other_vport[0x1]; 3881 u8 reserved_2[0xb]; 3882 u8 port_num[0x4]; 3883 u8 vport_number[0x10]; 3884 3885 u8 reserved_3[0x60]; 3886 3887 u8 clear[0x1]; 3888 u8 reserved_4[0x1f]; 3889 3890 u8 reserved_5[0x20]; 3891 }; 3892 3893 struct mlx5_ifc_query_tis_out_bits { 3894 u8 status[0x8]; 3895 u8 reserved_0[0x18]; 3896 3897 u8 syndrome[0x20]; 3898 3899 u8 reserved_1[0x40]; 3900 3901 struct mlx5_ifc_tisc_bits tis_context; 3902 }; 3903 3904 struct mlx5_ifc_query_tis_in_bits { 3905 u8 opcode[0x10]; 3906 u8 reserved_0[0x10]; 3907 3908 u8 reserved_1[0x10]; 3909 u8 op_mod[0x10]; 3910 3911 u8 reserved_2[0x8]; 3912 u8 tisn[0x18]; 3913 3914 u8 reserved_3[0x20]; 3915 }; 3916 3917 struct mlx5_ifc_query_tir_out_bits { 3918 u8 status[0x8]; 3919 u8 reserved_0[0x18]; 3920 3921 u8 syndrome[0x20]; 3922 3923 u8 reserved_1[0xc0]; 3924 3925 struct mlx5_ifc_tirc_bits tir_context; 3926 }; 3927 3928 struct mlx5_ifc_query_tir_in_bits { 3929 u8 opcode[0x10]; 3930 u8 reserved_0[0x10]; 3931 3932 u8 reserved_1[0x10]; 3933 u8 op_mod[0x10]; 3934 3935 u8 reserved_2[0x8]; 3936 u8 tirn[0x18]; 3937 3938 u8 reserved_3[0x20]; 3939 }; 3940 3941 struct mlx5_ifc_query_srq_out_bits { 3942 u8 status[0x8]; 3943 u8 reserved_0[0x18]; 3944 3945 u8 syndrome[0x20]; 3946 3947 u8 reserved_1[0x40]; 3948 3949 struct mlx5_ifc_srqc_bits srq_context_entry; 3950 3951 u8 reserved_2[0x600]; 3952 3953 u8 pas[0][0x40]; 3954 }; 3955 3956 struct mlx5_ifc_query_srq_in_bits { 3957 u8 opcode[0x10]; 3958 u8 reserved_0[0x10]; 3959 3960 u8 reserved_1[0x10]; 3961 u8 op_mod[0x10]; 3962 3963 u8 reserved_2[0x8]; 3964 u8 srqn[0x18]; 3965 3966 u8 reserved_3[0x20]; 3967 }; 3968 3969 struct mlx5_ifc_query_sq_out_bits { 3970 u8 status[0x8]; 3971 u8 reserved_0[0x18]; 3972 3973 u8 syndrome[0x20]; 3974 3975 u8 reserved_1[0xc0]; 3976 3977 struct mlx5_ifc_sqc_bits sq_context; 3978 }; 3979 3980 struct mlx5_ifc_query_sq_in_bits { 3981 u8 opcode[0x10]; 3982 u8 reserved_0[0x10]; 3983 3984 u8 reserved_1[0x10]; 3985 u8 op_mod[0x10]; 3986 3987 u8 reserved_2[0x8]; 3988 u8 sqn[0x18]; 3989 3990 u8 reserved_3[0x20]; 3991 }; 3992 3993 struct mlx5_ifc_query_special_contexts_out_bits { 3994 u8 status[0x8]; 3995 u8 reserved_0[0x18]; 3996 3997 u8 syndrome[0x20]; 3998 3999 u8 reserved_1[0x20]; 4000 4001 u8 resd_lkey[0x20]; 4002 }; 4003 4004 struct mlx5_ifc_query_special_contexts_in_bits { 4005 u8 opcode[0x10]; 4006 u8 reserved_0[0x10]; 4007 4008 u8 reserved_1[0x10]; 4009 u8 op_mod[0x10]; 4010 4011 u8 reserved_2[0x40]; 4012 }; 4013 4014 struct mlx5_ifc_query_scheduling_element_out_bits { 4015 u8 status[0x8]; 4016 u8 reserved_at_8[0x18]; 4017 4018 u8 syndrome[0x20]; 4019 4020 u8 reserved_at_40[0xc0]; 4021 4022 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4023 4024 u8 reserved_at_300[0x100]; 4025 }; 4026 4027 enum { 4028 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4029 }; 4030 4031 struct mlx5_ifc_query_scheduling_element_in_bits { 4032 u8 opcode[0x10]; 4033 u8 reserved_at_10[0x10]; 4034 4035 u8 reserved_at_20[0x10]; 4036 u8 op_mod[0x10]; 4037 4038 u8 scheduling_hierarchy[0x8]; 4039 u8 reserved_at_48[0x18]; 4040 4041 u8 scheduling_element_id[0x20]; 4042 4043 u8 reserved_at_80[0x180]; 4044 }; 4045 4046 struct mlx5_ifc_query_rqt_out_bits { 4047 u8 status[0x8]; 4048 u8 reserved_0[0x18]; 4049 4050 u8 syndrome[0x20]; 4051 4052 u8 reserved_1[0xc0]; 4053 4054 struct mlx5_ifc_rqtc_bits rqt_context; 4055 }; 4056 4057 struct mlx5_ifc_query_rqt_in_bits { 4058 u8 opcode[0x10]; 4059 u8 reserved_0[0x10]; 4060 4061 u8 reserved_1[0x10]; 4062 u8 op_mod[0x10]; 4063 4064 u8 reserved_2[0x8]; 4065 u8 rqtn[0x18]; 4066 4067 u8 reserved_3[0x20]; 4068 }; 4069 4070 struct mlx5_ifc_query_rq_out_bits { 4071 u8 status[0x8]; 4072 u8 reserved_0[0x18]; 4073 4074 u8 syndrome[0x20]; 4075 4076 u8 reserved_1[0xc0]; 4077 4078 struct mlx5_ifc_rqc_bits rq_context; 4079 }; 4080 4081 struct mlx5_ifc_query_rq_in_bits { 4082 u8 opcode[0x10]; 4083 u8 reserved_0[0x10]; 4084 4085 u8 reserved_1[0x10]; 4086 u8 op_mod[0x10]; 4087 4088 u8 reserved_2[0x8]; 4089 u8 rqn[0x18]; 4090 4091 u8 reserved_3[0x20]; 4092 }; 4093 4094 struct mlx5_ifc_query_roce_address_out_bits { 4095 u8 status[0x8]; 4096 u8 reserved_0[0x18]; 4097 4098 u8 syndrome[0x20]; 4099 4100 u8 reserved_1[0x40]; 4101 4102 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4103 }; 4104 4105 struct mlx5_ifc_query_roce_address_in_bits { 4106 u8 opcode[0x10]; 4107 u8 reserved_0[0x10]; 4108 4109 u8 reserved_1[0x10]; 4110 u8 op_mod[0x10]; 4111 4112 u8 roce_address_index[0x10]; 4113 u8 reserved_2[0x10]; 4114 4115 u8 reserved_3[0x20]; 4116 }; 4117 4118 struct mlx5_ifc_query_rmp_out_bits { 4119 u8 status[0x8]; 4120 u8 reserved_0[0x18]; 4121 4122 u8 syndrome[0x20]; 4123 4124 u8 reserved_1[0xc0]; 4125 4126 struct mlx5_ifc_rmpc_bits rmp_context; 4127 }; 4128 4129 struct mlx5_ifc_query_rmp_in_bits { 4130 u8 opcode[0x10]; 4131 u8 reserved_0[0x10]; 4132 4133 u8 reserved_1[0x10]; 4134 u8 op_mod[0x10]; 4135 4136 u8 reserved_2[0x8]; 4137 u8 rmpn[0x18]; 4138 4139 u8 reserved_3[0x20]; 4140 }; 4141 4142 struct mlx5_ifc_query_rdb_out_bits { 4143 u8 status[0x8]; 4144 u8 reserved_0[0x18]; 4145 4146 u8 syndrome[0x20]; 4147 4148 u8 reserved_1[0x20]; 4149 4150 u8 reserved_2[0x18]; 4151 u8 rdb_list_size[0x8]; 4152 4153 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4154 }; 4155 4156 struct mlx5_ifc_query_rdb_in_bits { 4157 u8 opcode[0x10]; 4158 u8 reserved_0[0x10]; 4159 4160 u8 reserved_1[0x10]; 4161 u8 op_mod[0x10]; 4162 4163 u8 reserved_2[0x8]; 4164 u8 qpn[0x18]; 4165 4166 u8 reserved_3[0x20]; 4167 }; 4168 4169 struct mlx5_ifc_query_qp_out_bits { 4170 u8 status[0x8]; 4171 u8 reserved_0[0x18]; 4172 4173 u8 syndrome[0x20]; 4174 4175 u8 reserved_1[0x40]; 4176 4177 u8 opt_param_mask[0x20]; 4178 4179 u8 reserved_2[0x20]; 4180 4181 struct mlx5_ifc_qpc_bits qpc; 4182 4183 u8 reserved_3[0x80]; 4184 4185 u8 pas[0][0x40]; 4186 }; 4187 4188 struct mlx5_ifc_query_qp_in_bits { 4189 u8 opcode[0x10]; 4190 u8 reserved_0[0x10]; 4191 4192 u8 reserved_1[0x10]; 4193 u8 op_mod[0x10]; 4194 4195 u8 reserved_2[0x8]; 4196 u8 qpn[0x18]; 4197 4198 u8 reserved_3[0x20]; 4199 }; 4200 4201 struct mlx5_ifc_query_q_counter_out_bits { 4202 u8 status[0x8]; 4203 u8 reserved_0[0x18]; 4204 4205 u8 syndrome[0x20]; 4206 4207 u8 reserved_1[0x40]; 4208 4209 u8 rx_write_requests[0x20]; 4210 4211 u8 reserved_2[0x20]; 4212 4213 u8 rx_read_requests[0x20]; 4214 4215 u8 reserved_3[0x20]; 4216 4217 u8 rx_atomic_requests[0x20]; 4218 4219 u8 reserved_4[0x20]; 4220 4221 u8 rx_dct_connect[0x20]; 4222 4223 u8 reserved_5[0x20]; 4224 4225 u8 out_of_buffer[0x20]; 4226 4227 u8 reserved_7[0x20]; 4228 4229 u8 out_of_sequence[0x20]; 4230 4231 u8 reserved_8[0x20]; 4232 4233 u8 duplicate_request[0x20]; 4234 4235 u8 reserved_9[0x20]; 4236 4237 u8 rnr_nak_retry_err[0x20]; 4238 4239 u8 reserved_10[0x20]; 4240 4241 u8 packet_seq_err[0x20]; 4242 4243 u8 reserved_11[0x20]; 4244 4245 u8 implied_nak_seq_err[0x20]; 4246 4247 u8 reserved_12[0x20]; 4248 4249 u8 local_ack_timeout_err[0x20]; 4250 4251 u8 reserved_13[0x20]; 4252 4253 u8 resp_rnr_nak[0x20]; 4254 4255 u8 reserved_14[0x20]; 4256 4257 u8 req_rnr_retries_exceeded[0x20]; 4258 4259 u8 reserved_15[0x460]; 4260 }; 4261 4262 struct mlx5_ifc_query_q_counter_in_bits { 4263 u8 opcode[0x10]; 4264 u8 reserved_0[0x10]; 4265 4266 u8 reserved_1[0x10]; 4267 u8 op_mod[0x10]; 4268 4269 u8 reserved_2[0x80]; 4270 4271 u8 clear[0x1]; 4272 u8 reserved_3[0x1f]; 4273 4274 u8 reserved_4[0x18]; 4275 u8 counter_set_id[0x8]; 4276 }; 4277 4278 struct mlx5_ifc_query_pages_out_bits { 4279 u8 status[0x8]; 4280 u8 reserved_0[0x18]; 4281 4282 u8 syndrome[0x20]; 4283 4284 u8 reserved_1[0x10]; 4285 u8 function_id[0x10]; 4286 4287 u8 num_pages[0x20]; 4288 }; 4289 4290 enum { 4291 MLX5_BOOT_PAGES = 0x1, 4292 MLX5_INIT_PAGES = 0x2, 4293 MLX5_POST_INIT_PAGES = 0x3, 4294 }; 4295 4296 struct mlx5_ifc_query_pages_in_bits { 4297 u8 opcode[0x10]; 4298 u8 reserved_0[0x10]; 4299 4300 u8 reserved_1[0x10]; 4301 u8 op_mod[0x10]; 4302 4303 u8 reserved_2[0x10]; 4304 u8 function_id[0x10]; 4305 4306 u8 reserved_3[0x20]; 4307 }; 4308 4309 struct mlx5_ifc_query_nic_vport_context_out_bits { 4310 u8 status[0x8]; 4311 u8 reserved_0[0x18]; 4312 4313 u8 syndrome[0x20]; 4314 4315 u8 reserved_1[0x40]; 4316 4317 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4318 }; 4319 4320 struct mlx5_ifc_query_nic_vport_context_in_bits { 4321 u8 opcode[0x10]; 4322 u8 reserved_0[0x10]; 4323 4324 u8 reserved_1[0x10]; 4325 u8 op_mod[0x10]; 4326 4327 u8 other_vport[0x1]; 4328 u8 reserved_2[0xf]; 4329 u8 vport_number[0x10]; 4330 4331 u8 reserved_3[0x5]; 4332 u8 allowed_list_type[0x3]; 4333 u8 reserved_4[0x18]; 4334 }; 4335 4336 struct mlx5_ifc_query_mkey_out_bits { 4337 u8 status[0x8]; 4338 u8 reserved_0[0x18]; 4339 4340 u8 syndrome[0x20]; 4341 4342 u8 reserved_1[0x40]; 4343 4344 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4345 4346 u8 reserved_2[0x600]; 4347 4348 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4349 4350 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4351 }; 4352 4353 struct mlx5_ifc_query_mkey_in_bits { 4354 u8 opcode[0x10]; 4355 u8 reserved_0[0x10]; 4356 4357 u8 reserved_1[0x10]; 4358 u8 op_mod[0x10]; 4359 4360 u8 reserved_2[0x8]; 4361 u8 mkey_index[0x18]; 4362 4363 u8 pg_access[0x1]; 4364 u8 reserved_3[0x1f]; 4365 }; 4366 4367 struct mlx5_ifc_query_mad_demux_out_bits { 4368 u8 status[0x8]; 4369 u8 reserved_0[0x18]; 4370 4371 u8 syndrome[0x20]; 4372 4373 u8 reserved_1[0x40]; 4374 4375 u8 mad_dumux_parameters_block[0x20]; 4376 }; 4377 4378 struct mlx5_ifc_query_mad_demux_in_bits { 4379 u8 opcode[0x10]; 4380 u8 reserved_0[0x10]; 4381 4382 u8 reserved_1[0x10]; 4383 u8 op_mod[0x10]; 4384 4385 u8 reserved_2[0x40]; 4386 }; 4387 4388 struct mlx5_ifc_query_l2_table_entry_out_bits { 4389 u8 status[0x8]; 4390 u8 reserved_0[0x18]; 4391 4392 u8 syndrome[0x20]; 4393 4394 u8 reserved_1[0xa0]; 4395 4396 u8 reserved_2[0x13]; 4397 u8 vlan_valid[0x1]; 4398 u8 vlan[0xc]; 4399 4400 struct mlx5_ifc_mac_address_layout_bits mac_address; 4401 4402 u8 reserved_3[0xc0]; 4403 }; 4404 4405 struct mlx5_ifc_query_l2_table_entry_in_bits { 4406 u8 opcode[0x10]; 4407 u8 reserved_0[0x10]; 4408 4409 u8 reserved_1[0x10]; 4410 u8 op_mod[0x10]; 4411 4412 u8 reserved_2[0x60]; 4413 4414 u8 reserved_3[0x8]; 4415 u8 table_index[0x18]; 4416 4417 u8 reserved_4[0x140]; 4418 }; 4419 4420 struct mlx5_ifc_query_issi_out_bits { 4421 u8 status[0x8]; 4422 u8 reserved_0[0x18]; 4423 4424 u8 syndrome[0x20]; 4425 4426 u8 reserved_1[0x10]; 4427 u8 current_issi[0x10]; 4428 4429 u8 reserved_2[0xa0]; 4430 4431 u8 supported_issi_reserved[76][0x8]; 4432 u8 supported_issi_dw0[0x20]; 4433 }; 4434 4435 struct mlx5_ifc_query_issi_in_bits { 4436 u8 opcode[0x10]; 4437 u8 reserved_0[0x10]; 4438 4439 u8 reserved_1[0x10]; 4440 u8 op_mod[0x10]; 4441 4442 u8 reserved_2[0x40]; 4443 }; 4444 4445 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4446 u8 status[0x8]; 4447 u8 reserved_0[0x18]; 4448 4449 u8 syndrome[0x20]; 4450 4451 u8 reserved_1[0x40]; 4452 4453 struct mlx5_ifc_pkey_bits pkey[0]; 4454 }; 4455 4456 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4457 u8 opcode[0x10]; 4458 u8 reserved_0[0x10]; 4459 4460 u8 reserved_1[0x10]; 4461 u8 op_mod[0x10]; 4462 4463 u8 other_vport[0x1]; 4464 u8 reserved_2[0xb]; 4465 u8 port_num[0x4]; 4466 u8 vport_number[0x10]; 4467 4468 u8 reserved_3[0x10]; 4469 u8 pkey_index[0x10]; 4470 }; 4471 4472 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4473 u8 status[0x8]; 4474 u8 reserved_0[0x18]; 4475 4476 u8 syndrome[0x20]; 4477 4478 u8 reserved_1[0x20]; 4479 4480 u8 gids_num[0x10]; 4481 u8 reserved_2[0x10]; 4482 4483 struct mlx5_ifc_array128_auto_bits gid[0]; 4484 }; 4485 4486 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4487 u8 opcode[0x10]; 4488 u8 reserved_0[0x10]; 4489 4490 u8 reserved_1[0x10]; 4491 u8 op_mod[0x10]; 4492 4493 u8 other_vport[0x1]; 4494 u8 reserved_2[0xb]; 4495 u8 port_num[0x4]; 4496 u8 vport_number[0x10]; 4497 4498 u8 reserved_3[0x10]; 4499 u8 gid_index[0x10]; 4500 }; 4501 4502 struct mlx5_ifc_query_hca_vport_context_out_bits { 4503 u8 status[0x8]; 4504 u8 reserved_0[0x18]; 4505 4506 u8 syndrome[0x20]; 4507 4508 u8 reserved_1[0x40]; 4509 4510 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4511 }; 4512 4513 struct mlx5_ifc_query_hca_vport_context_in_bits { 4514 u8 opcode[0x10]; 4515 u8 reserved_0[0x10]; 4516 4517 u8 reserved_1[0x10]; 4518 u8 op_mod[0x10]; 4519 4520 u8 other_vport[0x1]; 4521 u8 reserved_2[0xb]; 4522 u8 port_num[0x4]; 4523 u8 vport_number[0x10]; 4524 4525 u8 reserved_3[0x20]; 4526 }; 4527 4528 struct mlx5_ifc_query_hca_cap_out_bits { 4529 u8 status[0x8]; 4530 u8 reserved_0[0x18]; 4531 4532 u8 syndrome[0x20]; 4533 4534 u8 reserved_1[0x40]; 4535 4536 union mlx5_ifc_hca_cap_union_bits capability; 4537 }; 4538 4539 struct mlx5_ifc_query_hca_cap_in_bits { 4540 u8 opcode[0x10]; 4541 u8 reserved_0[0x10]; 4542 4543 u8 reserved_1[0x10]; 4544 u8 op_mod[0x10]; 4545 4546 u8 reserved_2[0x40]; 4547 }; 4548 4549 struct mlx5_ifc_query_flow_table_out_bits { 4550 u8 status[0x8]; 4551 u8 reserved_at_8[0x18]; 4552 4553 u8 syndrome[0x20]; 4554 4555 u8 reserved_at_40[0x80]; 4556 4557 struct mlx5_ifc_flow_table_context_bits flow_table_context; 4558 }; 4559 4560 struct mlx5_ifc_query_flow_table_in_bits { 4561 u8 opcode[0x10]; 4562 u8 reserved_0[0x10]; 4563 4564 u8 reserved_1[0x10]; 4565 u8 op_mod[0x10]; 4566 4567 u8 other_vport[0x1]; 4568 u8 reserved_2[0xf]; 4569 u8 vport_number[0x10]; 4570 4571 u8 reserved_3[0x20]; 4572 4573 u8 table_type[0x8]; 4574 u8 reserved_4[0x18]; 4575 4576 u8 reserved_5[0x8]; 4577 u8 table_id[0x18]; 4578 4579 u8 reserved_6[0x140]; 4580 }; 4581 4582 struct mlx5_ifc_query_fte_out_bits { 4583 u8 status[0x8]; 4584 u8 reserved_0[0x18]; 4585 4586 u8 syndrome[0x20]; 4587 4588 u8 reserved_1[0x1c0]; 4589 4590 struct mlx5_ifc_flow_context_bits flow_context; 4591 }; 4592 4593 struct mlx5_ifc_query_fte_in_bits { 4594 u8 opcode[0x10]; 4595 u8 reserved_0[0x10]; 4596 4597 u8 reserved_1[0x10]; 4598 u8 op_mod[0x10]; 4599 4600 u8 other_vport[0x1]; 4601 u8 reserved_2[0xf]; 4602 u8 vport_number[0x10]; 4603 4604 u8 reserved_3[0x20]; 4605 4606 u8 table_type[0x8]; 4607 u8 reserved_4[0x18]; 4608 4609 u8 reserved_5[0x8]; 4610 u8 table_id[0x18]; 4611 4612 u8 reserved_6[0x40]; 4613 4614 u8 flow_index[0x20]; 4615 4616 u8 reserved_7[0xe0]; 4617 }; 4618 4619 enum { 4620 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4621 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4622 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4623 }; 4624 4625 struct mlx5_ifc_query_flow_group_out_bits { 4626 u8 status[0x8]; 4627 u8 reserved_0[0x18]; 4628 4629 u8 syndrome[0x20]; 4630 4631 u8 reserved_1[0xa0]; 4632 4633 u8 start_flow_index[0x20]; 4634 4635 u8 reserved_2[0x20]; 4636 4637 u8 end_flow_index[0x20]; 4638 4639 u8 reserved_3[0xa0]; 4640 4641 u8 reserved_4[0x18]; 4642 u8 match_criteria_enable[0x8]; 4643 4644 struct mlx5_ifc_fte_match_param_bits match_criteria; 4645 4646 u8 reserved_5[0xe00]; 4647 }; 4648 4649 struct mlx5_ifc_query_flow_group_in_bits { 4650 u8 opcode[0x10]; 4651 u8 reserved_0[0x10]; 4652 4653 u8 reserved_1[0x10]; 4654 u8 op_mod[0x10]; 4655 4656 u8 other_vport[0x1]; 4657 u8 reserved_2[0xf]; 4658 u8 vport_number[0x10]; 4659 4660 u8 reserved_3[0x20]; 4661 4662 u8 table_type[0x8]; 4663 u8 reserved_4[0x18]; 4664 4665 u8 reserved_5[0x8]; 4666 u8 table_id[0x18]; 4667 4668 u8 group_id[0x20]; 4669 4670 u8 reserved_6[0x120]; 4671 }; 4672 4673 struct mlx5_ifc_query_flow_counter_out_bits { 4674 u8 status[0x8]; 4675 u8 reserved_at_8[0x18]; 4676 4677 u8 syndrome[0x20]; 4678 4679 u8 reserved_at_40[0x40]; 4680 4681 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4682 }; 4683 4684 struct mlx5_ifc_query_flow_counter_in_bits { 4685 u8 opcode[0x10]; 4686 u8 reserved_at_10[0x10]; 4687 4688 u8 reserved_at_20[0x10]; 4689 u8 op_mod[0x10]; 4690 4691 u8 reserved_at_40[0x80]; 4692 4693 u8 clear[0x1]; 4694 u8 reserved_at_c1[0xf]; 4695 u8 num_of_counters[0x10]; 4696 4697 u8 reserved_at_e0[0x10]; 4698 u8 flow_counter_id[0x10]; 4699 }; 4700 4701 struct mlx5_ifc_query_esw_vport_context_out_bits { 4702 u8 status[0x8]; 4703 u8 reserved_0[0x18]; 4704 4705 u8 syndrome[0x20]; 4706 4707 u8 reserved_1[0x40]; 4708 4709 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4710 }; 4711 4712 struct mlx5_ifc_query_esw_vport_context_in_bits { 4713 u8 opcode[0x10]; 4714 u8 reserved_0[0x10]; 4715 4716 u8 reserved_1[0x10]; 4717 u8 op_mod[0x10]; 4718 4719 u8 other_vport[0x1]; 4720 u8 reserved_2[0xf]; 4721 u8 vport_number[0x10]; 4722 4723 u8 reserved_3[0x20]; 4724 }; 4725 4726 struct mlx5_ifc_query_eq_out_bits { 4727 u8 status[0x8]; 4728 u8 reserved_0[0x18]; 4729 4730 u8 syndrome[0x20]; 4731 4732 u8 reserved_1[0x40]; 4733 4734 struct mlx5_ifc_eqc_bits eq_context_entry; 4735 4736 u8 reserved_2[0x40]; 4737 4738 u8 event_bitmask[0x40]; 4739 4740 u8 reserved_3[0x580]; 4741 4742 u8 pas[0][0x40]; 4743 }; 4744 4745 struct mlx5_ifc_query_eq_in_bits { 4746 u8 opcode[0x10]; 4747 u8 reserved_0[0x10]; 4748 4749 u8 reserved_1[0x10]; 4750 u8 op_mod[0x10]; 4751 4752 u8 reserved_2[0x18]; 4753 u8 eq_number[0x8]; 4754 4755 u8 reserved_3[0x20]; 4756 }; 4757 4758 struct mlx5_ifc_query_dct_out_bits { 4759 u8 status[0x8]; 4760 u8 reserved_0[0x18]; 4761 4762 u8 syndrome[0x20]; 4763 4764 u8 reserved_1[0x40]; 4765 4766 struct mlx5_ifc_dctc_bits dct_context_entry; 4767 4768 u8 reserved_2[0x180]; 4769 }; 4770 4771 struct mlx5_ifc_query_dct_in_bits { 4772 u8 opcode[0x10]; 4773 u8 reserved_0[0x10]; 4774 4775 u8 reserved_1[0x10]; 4776 u8 op_mod[0x10]; 4777 4778 u8 reserved_2[0x8]; 4779 u8 dctn[0x18]; 4780 4781 u8 reserved_3[0x20]; 4782 }; 4783 4784 struct mlx5_ifc_query_dc_cnak_trace_out_bits { 4785 u8 status[0x8]; 4786 u8 reserved_0[0x18]; 4787 4788 u8 syndrome[0x20]; 4789 4790 u8 enable[0x1]; 4791 u8 reserved_1[0x1f]; 4792 4793 u8 reserved_2[0x160]; 4794 4795 struct mlx5_ifc_cmd_pas_bits pas; 4796 }; 4797 4798 struct mlx5_ifc_query_dc_cnak_trace_in_bits { 4799 u8 opcode[0x10]; 4800 u8 reserved_0[0x10]; 4801 4802 u8 reserved_1[0x10]; 4803 u8 op_mod[0x10]; 4804 4805 u8 reserved_2[0x40]; 4806 }; 4807 4808 struct mlx5_ifc_query_cq_out_bits { 4809 u8 status[0x8]; 4810 u8 reserved_0[0x18]; 4811 4812 u8 syndrome[0x20]; 4813 4814 u8 reserved_1[0x40]; 4815 4816 struct mlx5_ifc_cqc_bits cq_context; 4817 4818 u8 reserved_2[0x600]; 4819 4820 u8 pas[0][0x40]; 4821 }; 4822 4823 struct mlx5_ifc_query_cq_in_bits { 4824 u8 opcode[0x10]; 4825 u8 reserved_0[0x10]; 4826 4827 u8 reserved_1[0x10]; 4828 u8 op_mod[0x10]; 4829 4830 u8 reserved_2[0x8]; 4831 u8 cqn[0x18]; 4832 4833 u8 reserved_3[0x20]; 4834 }; 4835 4836 struct mlx5_ifc_query_cong_status_out_bits { 4837 u8 status[0x8]; 4838 u8 reserved_0[0x18]; 4839 4840 u8 syndrome[0x20]; 4841 4842 u8 reserved_1[0x20]; 4843 4844 u8 enable[0x1]; 4845 u8 tag_enable[0x1]; 4846 u8 reserved_2[0x1e]; 4847 }; 4848 4849 struct mlx5_ifc_query_cong_status_in_bits { 4850 u8 opcode[0x10]; 4851 u8 reserved_0[0x10]; 4852 4853 u8 reserved_1[0x10]; 4854 u8 op_mod[0x10]; 4855 4856 u8 reserved_2[0x18]; 4857 u8 priority[0x4]; 4858 u8 cong_protocol[0x4]; 4859 4860 u8 reserved_3[0x20]; 4861 }; 4862 4863 struct mlx5_ifc_query_cong_statistics_out_bits { 4864 u8 status[0x8]; 4865 u8 reserved_0[0x18]; 4866 4867 u8 syndrome[0x20]; 4868 4869 u8 reserved_1[0x40]; 4870 4871 u8 cur_flows[0x20]; 4872 4873 u8 sum_flows[0x20]; 4874 4875 u8 cnp_ignored_high[0x20]; 4876 4877 u8 cnp_ignored_low[0x20]; 4878 4879 u8 cnp_handled_high[0x20]; 4880 4881 u8 cnp_handled_low[0x20]; 4882 4883 u8 reserved_2[0x100]; 4884 4885 u8 time_stamp_high[0x20]; 4886 4887 u8 time_stamp_low[0x20]; 4888 4889 u8 accumulators_period[0x20]; 4890 4891 u8 ecn_marked_roce_packets_high[0x20]; 4892 4893 u8 ecn_marked_roce_packets_low[0x20]; 4894 4895 u8 cnps_sent_high[0x20]; 4896 4897 u8 cnps_sent_low[0x20]; 4898 4899 u8 reserved_3[0x560]; 4900 }; 4901 4902 struct mlx5_ifc_query_cong_statistics_in_bits { 4903 u8 opcode[0x10]; 4904 u8 reserved_0[0x10]; 4905 4906 u8 reserved_1[0x10]; 4907 u8 op_mod[0x10]; 4908 4909 u8 clear[0x1]; 4910 u8 reserved_2[0x1f]; 4911 4912 u8 reserved_3[0x20]; 4913 }; 4914 4915 struct mlx5_ifc_query_cong_params_out_bits { 4916 u8 status[0x8]; 4917 u8 reserved_0[0x18]; 4918 4919 u8 syndrome[0x20]; 4920 4921 u8 reserved_1[0x40]; 4922 4923 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4924 }; 4925 4926 struct mlx5_ifc_query_cong_params_in_bits { 4927 u8 opcode[0x10]; 4928 u8 reserved_0[0x10]; 4929 4930 u8 reserved_1[0x10]; 4931 u8 op_mod[0x10]; 4932 4933 u8 reserved_2[0x1c]; 4934 u8 cong_protocol[0x4]; 4935 4936 u8 reserved_3[0x20]; 4937 }; 4938 4939 struct mlx5_ifc_query_burst_size_out_bits { 4940 u8 status[0x8]; 4941 u8 reserved_0[0x18]; 4942 4943 u8 syndrome[0x20]; 4944 4945 u8 reserved_1[0x20]; 4946 4947 u8 reserved_2[0x9]; 4948 u8 device_burst_size[0x17]; 4949 }; 4950 4951 struct mlx5_ifc_query_burst_size_in_bits { 4952 u8 opcode[0x10]; 4953 u8 reserved_0[0x10]; 4954 4955 u8 reserved_1[0x10]; 4956 u8 op_mod[0x10]; 4957 4958 u8 reserved_2[0x40]; 4959 }; 4960 4961 struct mlx5_ifc_query_adapter_out_bits { 4962 u8 status[0x8]; 4963 u8 reserved_0[0x18]; 4964 4965 u8 syndrome[0x20]; 4966 4967 u8 reserved_1[0x40]; 4968 4969 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 4970 }; 4971 4972 struct mlx5_ifc_query_adapter_in_bits { 4973 u8 opcode[0x10]; 4974 u8 reserved_0[0x10]; 4975 4976 u8 reserved_1[0x10]; 4977 u8 op_mod[0x10]; 4978 4979 u8 reserved_2[0x40]; 4980 }; 4981 4982 struct mlx5_ifc_qp_2rst_out_bits { 4983 u8 status[0x8]; 4984 u8 reserved_0[0x18]; 4985 4986 u8 syndrome[0x20]; 4987 4988 u8 reserved_1[0x40]; 4989 }; 4990 4991 struct mlx5_ifc_qp_2rst_in_bits { 4992 u8 opcode[0x10]; 4993 u8 reserved_0[0x10]; 4994 4995 u8 reserved_1[0x10]; 4996 u8 op_mod[0x10]; 4997 4998 u8 reserved_2[0x8]; 4999 u8 qpn[0x18]; 5000 5001 u8 reserved_3[0x20]; 5002 }; 5003 5004 struct mlx5_ifc_qp_2err_out_bits { 5005 u8 status[0x8]; 5006 u8 reserved_0[0x18]; 5007 5008 u8 syndrome[0x20]; 5009 5010 u8 reserved_1[0x40]; 5011 }; 5012 5013 struct mlx5_ifc_qp_2err_in_bits { 5014 u8 opcode[0x10]; 5015 u8 reserved_0[0x10]; 5016 5017 u8 reserved_1[0x10]; 5018 u8 op_mod[0x10]; 5019 5020 u8 reserved_2[0x8]; 5021 u8 qpn[0x18]; 5022 5023 u8 reserved_3[0x20]; 5024 }; 5025 5026 struct mlx5_ifc_para_vport_element_bits { 5027 u8 reserved_at_0[0xc]; 5028 u8 traffic_class[0x4]; 5029 u8 qos_para_vport_number[0x10]; 5030 }; 5031 5032 struct mlx5_ifc_page_fault_resume_out_bits { 5033 u8 status[0x8]; 5034 u8 reserved_0[0x18]; 5035 5036 u8 syndrome[0x20]; 5037 5038 u8 reserved_1[0x40]; 5039 }; 5040 5041 struct mlx5_ifc_page_fault_resume_in_bits { 5042 u8 opcode[0x10]; 5043 u8 reserved_0[0x10]; 5044 5045 u8 reserved_1[0x10]; 5046 u8 op_mod[0x10]; 5047 5048 u8 error[0x1]; 5049 u8 reserved_2[0x4]; 5050 u8 rdma[0x1]; 5051 u8 read_write[0x1]; 5052 u8 req_res[0x1]; 5053 u8 qpn[0x18]; 5054 5055 u8 reserved_3[0x20]; 5056 }; 5057 5058 struct mlx5_ifc_nop_out_bits { 5059 u8 status[0x8]; 5060 u8 reserved_0[0x18]; 5061 5062 u8 syndrome[0x20]; 5063 5064 u8 reserved_1[0x40]; 5065 }; 5066 5067 struct mlx5_ifc_nop_in_bits { 5068 u8 opcode[0x10]; 5069 u8 reserved_0[0x10]; 5070 5071 u8 reserved_1[0x10]; 5072 u8 op_mod[0x10]; 5073 5074 u8 reserved_2[0x40]; 5075 }; 5076 5077 struct mlx5_ifc_modify_vport_state_out_bits { 5078 u8 status[0x8]; 5079 u8 reserved_0[0x18]; 5080 5081 u8 syndrome[0x20]; 5082 5083 u8 reserved_1[0x40]; 5084 }; 5085 5086 enum { 5087 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5088 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5089 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5090 }; 5091 5092 enum { 5093 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5094 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5095 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5096 }; 5097 5098 struct mlx5_ifc_modify_vport_state_in_bits { 5099 u8 opcode[0x10]; 5100 u8 reserved_0[0x10]; 5101 5102 u8 reserved_1[0x10]; 5103 u8 op_mod[0x10]; 5104 5105 u8 other_vport[0x1]; 5106 u8 reserved_2[0xf]; 5107 u8 vport_number[0x10]; 5108 5109 u8 reserved_3[0x18]; 5110 u8 admin_state[0x4]; 5111 u8 reserved_4[0x4]; 5112 }; 5113 5114 struct mlx5_ifc_modify_tis_out_bits { 5115 u8 status[0x8]; 5116 u8 reserved_0[0x18]; 5117 5118 u8 syndrome[0x20]; 5119 5120 u8 reserved_1[0x40]; 5121 }; 5122 5123 struct mlx5_ifc_modify_tis_bitmask_bits { 5124 u8 reserved_at_0[0x20]; 5125 5126 u8 reserved_at_20[0x1d]; 5127 u8 lag_tx_port_affinity[0x1]; 5128 u8 strict_lag_tx_port_affinity[0x1]; 5129 u8 prio[0x1]; 5130 }; 5131 5132 struct mlx5_ifc_modify_tis_in_bits { 5133 u8 opcode[0x10]; 5134 u8 reserved_0[0x10]; 5135 5136 u8 reserved_1[0x10]; 5137 u8 op_mod[0x10]; 5138 5139 u8 reserved_2[0x8]; 5140 u8 tisn[0x18]; 5141 5142 u8 reserved_3[0x20]; 5143 5144 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5145 5146 u8 reserved_4[0x40]; 5147 5148 struct mlx5_ifc_tisc_bits ctx; 5149 }; 5150 5151 struct mlx5_ifc_modify_tir_out_bits { 5152 u8 status[0x8]; 5153 u8 reserved_0[0x18]; 5154 5155 u8 syndrome[0x20]; 5156 5157 u8 reserved_1[0x40]; 5158 }; 5159 5160 enum 5161 { 5162 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5163 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5164 }; 5165 5166 struct mlx5_ifc_modify_tir_in_bits { 5167 u8 opcode[0x10]; 5168 u8 reserved_0[0x10]; 5169 5170 u8 reserved_1[0x10]; 5171 u8 op_mod[0x10]; 5172 5173 u8 reserved_2[0x8]; 5174 u8 tirn[0x18]; 5175 5176 u8 reserved_3[0x20]; 5177 5178 u8 modify_bitmask[0x40]; 5179 5180 u8 reserved_4[0x40]; 5181 5182 struct mlx5_ifc_tirc_bits tir_context; 5183 }; 5184 5185 struct mlx5_ifc_modify_sq_out_bits { 5186 u8 status[0x8]; 5187 u8 reserved_0[0x18]; 5188 5189 u8 syndrome[0x20]; 5190 5191 u8 reserved_1[0x40]; 5192 }; 5193 5194 struct mlx5_ifc_modify_sq_in_bits { 5195 u8 opcode[0x10]; 5196 u8 reserved_0[0x10]; 5197 5198 u8 reserved_1[0x10]; 5199 u8 op_mod[0x10]; 5200 5201 u8 sq_state[0x4]; 5202 u8 reserved_2[0x4]; 5203 u8 sqn[0x18]; 5204 5205 u8 reserved_3[0x20]; 5206 5207 u8 modify_bitmask[0x40]; 5208 5209 u8 reserved_4[0x40]; 5210 5211 struct mlx5_ifc_sqc_bits ctx; 5212 }; 5213 5214 struct mlx5_ifc_modify_scheduling_element_out_bits { 5215 u8 status[0x8]; 5216 u8 reserved_at_8[0x18]; 5217 5218 u8 syndrome[0x20]; 5219 5220 u8 reserved_at_40[0x1c0]; 5221 }; 5222 5223 enum { 5224 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5225 }; 5226 5227 enum { 5228 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5229 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5230 }; 5231 5232 struct mlx5_ifc_modify_scheduling_element_in_bits { 5233 u8 opcode[0x10]; 5234 u8 reserved_at_10[0x10]; 5235 5236 u8 reserved_at_20[0x10]; 5237 u8 op_mod[0x10]; 5238 5239 u8 scheduling_hierarchy[0x8]; 5240 u8 reserved_at_48[0x18]; 5241 5242 u8 scheduling_element_id[0x20]; 5243 5244 u8 reserved_at_80[0x20]; 5245 5246 u8 modify_bitmask[0x20]; 5247 5248 u8 reserved_at_c0[0x40]; 5249 5250 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5251 5252 u8 reserved_at_300[0x100]; 5253 }; 5254 5255 struct mlx5_ifc_modify_rqt_out_bits { 5256 u8 status[0x8]; 5257 u8 reserved_0[0x18]; 5258 5259 u8 syndrome[0x20]; 5260 5261 u8 reserved_1[0x40]; 5262 }; 5263 5264 struct mlx5_ifc_modify_rqt_in_bits { 5265 u8 opcode[0x10]; 5266 u8 reserved_0[0x10]; 5267 5268 u8 reserved_1[0x10]; 5269 u8 op_mod[0x10]; 5270 5271 u8 reserved_2[0x8]; 5272 u8 rqtn[0x18]; 5273 5274 u8 reserved_3[0x20]; 5275 5276 u8 modify_bitmask[0x40]; 5277 5278 u8 reserved_4[0x40]; 5279 5280 struct mlx5_ifc_rqtc_bits ctx; 5281 }; 5282 5283 struct mlx5_ifc_modify_rq_out_bits { 5284 u8 status[0x8]; 5285 u8 reserved_0[0x18]; 5286 5287 u8 syndrome[0x20]; 5288 5289 u8 reserved_1[0x40]; 5290 }; 5291 5292 enum { 5293 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5294 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5295 }; 5296 5297 struct mlx5_ifc_modify_rq_in_bits { 5298 u8 opcode[0x10]; 5299 u8 reserved_0[0x10]; 5300 5301 u8 reserved_1[0x10]; 5302 u8 op_mod[0x10]; 5303 5304 u8 rq_state[0x4]; 5305 u8 reserved_2[0x4]; 5306 u8 rqn[0x18]; 5307 5308 u8 reserved_3[0x20]; 5309 5310 u8 modify_bitmask[0x40]; 5311 5312 u8 reserved_4[0x40]; 5313 5314 struct mlx5_ifc_rqc_bits ctx; 5315 }; 5316 5317 struct mlx5_ifc_modify_rmp_out_bits { 5318 u8 status[0x8]; 5319 u8 reserved_0[0x18]; 5320 5321 u8 syndrome[0x20]; 5322 5323 u8 reserved_1[0x40]; 5324 }; 5325 5326 struct mlx5_ifc_rmp_bitmask_bits { 5327 u8 reserved[0x20]; 5328 5329 u8 reserved1[0x1f]; 5330 u8 lwm[0x1]; 5331 }; 5332 5333 struct mlx5_ifc_modify_rmp_in_bits { 5334 u8 opcode[0x10]; 5335 u8 reserved_0[0x10]; 5336 5337 u8 reserved_1[0x10]; 5338 u8 op_mod[0x10]; 5339 5340 u8 rmp_state[0x4]; 5341 u8 reserved_2[0x4]; 5342 u8 rmpn[0x18]; 5343 5344 u8 reserved_3[0x20]; 5345 5346 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5347 5348 u8 reserved_4[0x40]; 5349 5350 struct mlx5_ifc_rmpc_bits ctx; 5351 }; 5352 5353 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5354 u8 status[0x8]; 5355 u8 reserved_0[0x18]; 5356 5357 u8 syndrome[0x20]; 5358 5359 u8 reserved_1[0x40]; 5360 }; 5361 5362 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5363 u8 reserved_0[0x14]; 5364 u8 disable_uc_local_lb[0x1]; 5365 u8 disable_mc_local_lb[0x1]; 5366 u8 node_guid[0x1]; 5367 u8 port_guid[0x1]; 5368 u8 min_wqe_inline_mode[0x1]; 5369 u8 mtu[0x1]; 5370 u8 change_event[0x1]; 5371 u8 promisc[0x1]; 5372 u8 permanent_address[0x1]; 5373 u8 addresses_list[0x1]; 5374 u8 roce_en[0x1]; 5375 u8 reserved_1[0x1]; 5376 }; 5377 5378 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5379 u8 opcode[0x10]; 5380 u8 reserved_0[0x10]; 5381 5382 u8 reserved_1[0x10]; 5383 u8 op_mod[0x10]; 5384 5385 u8 other_vport[0x1]; 5386 u8 reserved_2[0xf]; 5387 u8 vport_number[0x10]; 5388 5389 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5390 5391 u8 reserved_3[0x780]; 5392 5393 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5394 }; 5395 5396 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5397 u8 status[0x8]; 5398 u8 reserved_0[0x18]; 5399 5400 u8 syndrome[0x20]; 5401 5402 u8 reserved_1[0x40]; 5403 }; 5404 5405 struct mlx5_ifc_grh_bits { 5406 u8 ip_version[4]; 5407 u8 traffic_class[8]; 5408 u8 flow_label[20]; 5409 u8 payload_length[16]; 5410 u8 next_header[8]; 5411 u8 hop_limit[8]; 5412 u8 sgid[128]; 5413 u8 dgid[128]; 5414 }; 5415 5416 struct mlx5_ifc_bth_bits { 5417 u8 opcode[8]; 5418 u8 se[1]; 5419 u8 migreq[1]; 5420 u8 pad_count[2]; 5421 u8 tver[4]; 5422 u8 p_key[16]; 5423 u8 reserved8[8]; 5424 u8 dest_qp[24]; 5425 u8 ack_req[1]; 5426 u8 reserved7[7]; 5427 u8 psn[24]; 5428 }; 5429 5430 struct mlx5_ifc_aeth_bits { 5431 u8 syndrome[8]; 5432 u8 msn[24]; 5433 }; 5434 5435 struct mlx5_ifc_dceth_bits { 5436 u8 reserved0[8]; 5437 u8 session_id[24]; 5438 u8 reserved1[8]; 5439 u8 dci_dct[24]; 5440 }; 5441 5442 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5443 u8 opcode[0x10]; 5444 u8 reserved_0[0x10]; 5445 5446 u8 reserved_1[0x10]; 5447 u8 op_mod[0x10]; 5448 5449 u8 other_vport[0x1]; 5450 u8 reserved_2[0xb]; 5451 u8 port_num[0x4]; 5452 u8 vport_number[0x10]; 5453 5454 u8 reserved_3[0x20]; 5455 5456 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5457 }; 5458 5459 struct mlx5_ifc_modify_flow_table_out_bits { 5460 u8 status[0x8]; 5461 u8 reserved_at_8[0x18]; 5462 5463 u8 syndrome[0x20]; 5464 5465 u8 reserved_at_40[0x40]; 5466 }; 5467 5468 enum { 5469 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 5470 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 5471 }; 5472 5473 struct mlx5_ifc_modify_flow_table_in_bits { 5474 u8 opcode[0x10]; 5475 u8 reserved_at_10[0x10]; 5476 5477 u8 reserved_at_20[0x10]; 5478 u8 op_mod[0x10]; 5479 5480 u8 other_vport[0x1]; 5481 u8 reserved_at_41[0xf]; 5482 u8 vport_number[0x10]; 5483 5484 u8 reserved_at_60[0x10]; 5485 u8 modify_field_select[0x10]; 5486 5487 u8 table_type[0x8]; 5488 u8 reserved_at_88[0x18]; 5489 5490 u8 reserved_at_a0[0x8]; 5491 u8 table_id[0x18]; 5492 5493 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5494 }; 5495 5496 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5497 u8 status[0x8]; 5498 u8 reserved_0[0x18]; 5499 5500 u8 syndrome[0x20]; 5501 5502 u8 reserved_1[0x40]; 5503 }; 5504 5505 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5506 u8 reserved[0x1c]; 5507 u8 vport_cvlan_insert[0x1]; 5508 u8 vport_svlan_insert[0x1]; 5509 u8 vport_cvlan_strip[0x1]; 5510 u8 vport_svlan_strip[0x1]; 5511 }; 5512 5513 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5514 u8 opcode[0x10]; 5515 u8 reserved_0[0x10]; 5516 5517 u8 reserved_1[0x10]; 5518 u8 op_mod[0x10]; 5519 5520 u8 other_vport[0x1]; 5521 u8 reserved_2[0xf]; 5522 u8 vport_number[0x10]; 5523 5524 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5525 5526 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5527 }; 5528 5529 struct mlx5_ifc_modify_cq_out_bits { 5530 u8 status[0x8]; 5531 u8 reserved_0[0x18]; 5532 5533 u8 syndrome[0x20]; 5534 5535 u8 reserved_1[0x40]; 5536 }; 5537 5538 enum { 5539 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5540 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5541 }; 5542 5543 struct mlx5_ifc_modify_cq_in_bits { 5544 u8 opcode[0x10]; 5545 u8 reserved_0[0x10]; 5546 5547 u8 reserved_1[0x10]; 5548 u8 op_mod[0x10]; 5549 5550 u8 reserved_2[0x8]; 5551 u8 cqn[0x18]; 5552 5553 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5554 5555 struct mlx5_ifc_cqc_bits cq_context; 5556 5557 u8 reserved_3[0x600]; 5558 5559 u8 pas[0][0x40]; 5560 }; 5561 5562 struct mlx5_ifc_modify_cong_status_out_bits { 5563 u8 status[0x8]; 5564 u8 reserved_0[0x18]; 5565 5566 u8 syndrome[0x20]; 5567 5568 u8 reserved_1[0x40]; 5569 }; 5570 5571 struct mlx5_ifc_modify_cong_status_in_bits { 5572 u8 opcode[0x10]; 5573 u8 reserved_0[0x10]; 5574 5575 u8 reserved_1[0x10]; 5576 u8 op_mod[0x10]; 5577 5578 u8 reserved_2[0x18]; 5579 u8 priority[0x4]; 5580 u8 cong_protocol[0x4]; 5581 5582 u8 enable[0x1]; 5583 u8 tag_enable[0x1]; 5584 u8 reserved_3[0x1e]; 5585 }; 5586 5587 struct mlx5_ifc_modify_cong_params_out_bits { 5588 u8 status[0x8]; 5589 u8 reserved_0[0x18]; 5590 5591 u8 syndrome[0x20]; 5592 5593 u8 reserved_1[0x40]; 5594 }; 5595 5596 struct mlx5_ifc_modify_cong_params_in_bits { 5597 u8 opcode[0x10]; 5598 u8 reserved_0[0x10]; 5599 5600 u8 reserved_1[0x10]; 5601 u8 op_mod[0x10]; 5602 5603 u8 reserved_2[0x1c]; 5604 u8 cong_protocol[0x4]; 5605 5606 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5607 5608 u8 reserved_3[0x80]; 5609 5610 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5611 }; 5612 5613 struct mlx5_ifc_manage_pages_out_bits { 5614 u8 status[0x8]; 5615 u8 reserved_0[0x18]; 5616 5617 u8 syndrome[0x20]; 5618 5619 u8 output_num_entries[0x20]; 5620 5621 u8 reserved_1[0x20]; 5622 5623 u8 pas[0][0x40]; 5624 }; 5625 5626 enum { 5627 MLX5_PAGES_CANT_GIVE = 0x0, 5628 MLX5_PAGES_GIVE = 0x1, 5629 MLX5_PAGES_TAKE = 0x2, 5630 }; 5631 5632 struct mlx5_ifc_manage_pages_in_bits { 5633 u8 opcode[0x10]; 5634 u8 reserved_0[0x10]; 5635 5636 u8 reserved_1[0x10]; 5637 u8 op_mod[0x10]; 5638 5639 u8 reserved_2[0x10]; 5640 u8 function_id[0x10]; 5641 5642 u8 input_num_entries[0x20]; 5643 5644 u8 pas[0][0x40]; 5645 }; 5646 5647 struct mlx5_ifc_mad_ifc_out_bits { 5648 u8 status[0x8]; 5649 u8 reserved_0[0x18]; 5650 5651 u8 syndrome[0x20]; 5652 5653 u8 reserved_1[0x40]; 5654 5655 u8 response_mad_packet[256][0x8]; 5656 }; 5657 5658 struct mlx5_ifc_mad_ifc_in_bits { 5659 u8 opcode[0x10]; 5660 u8 reserved_0[0x10]; 5661 5662 u8 reserved_1[0x10]; 5663 u8 op_mod[0x10]; 5664 5665 u8 remote_lid[0x10]; 5666 u8 reserved_2[0x8]; 5667 u8 port[0x8]; 5668 5669 u8 reserved_3[0x20]; 5670 5671 u8 mad[256][0x8]; 5672 }; 5673 5674 struct mlx5_ifc_init_hca_out_bits { 5675 u8 status[0x8]; 5676 u8 reserved_0[0x18]; 5677 5678 u8 syndrome[0x20]; 5679 5680 u8 reserved_1[0x40]; 5681 }; 5682 5683 enum { 5684 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 5685 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 5686 }; 5687 5688 struct mlx5_ifc_init_hca_in_bits { 5689 u8 opcode[0x10]; 5690 u8 reserved_0[0x10]; 5691 5692 u8 reserved_1[0x10]; 5693 u8 op_mod[0x10]; 5694 5695 u8 reserved_2[0x40]; 5696 }; 5697 5698 struct mlx5_ifc_init2rtr_qp_out_bits { 5699 u8 status[0x8]; 5700 u8 reserved_0[0x18]; 5701 5702 u8 syndrome[0x20]; 5703 5704 u8 reserved_1[0x40]; 5705 }; 5706 5707 struct mlx5_ifc_init2rtr_qp_in_bits { 5708 u8 opcode[0x10]; 5709 u8 reserved_0[0x10]; 5710 5711 u8 reserved_1[0x10]; 5712 u8 op_mod[0x10]; 5713 5714 u8 reserved_2[0x8]; 5715 u8 qpn[0x18]; 5716 5717 u8 reserved_3[0x20]; 5718 5719 u8 opt_param_mask[0x20]; 5720 5721 u8 reserved_4[0x20]; 5722 5723 struct mlx5_ifc_qpc_bits qpc; 5724 5725 u8 reserved_5[0x80]; 5726 }; 5727 5728 struct mlx5_ifc_init2init_qp_out_bits { 5729 u8 status[0x8]; 5730 u8 reserved_0[0x18]; 5731 5732 u8 syndrome[0x20]; 5733 5734 u8 reserved_1[0x40]; 5735 }; 5736 5737 struct mlx5_ifc_init2init_qp_in_bits { 5738 u8 opcode[0x10]; 5739 u8 reserved_0[0x10]; 5740 5741 u8 reserved_1[0x10]; 5742 u8 op_mod[0x10]; 5743 5744 u8 reserved_2[0x8]; 5745 u8 qpn[0x18]; 5746 5747 u8 reserved_3[0x20]; 5748 5749 u8 opt_param_mask[0x20]; 5750 5751 u8 reserved_4[0x20]; 5752 5753 struct mlx5_ifc_qpc_bits qpc; 5754 5755 u8 reserved_5[0x80]; 5756 }; 5757 5758 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5759 u8 status[0x8]; 5760 u8 reserved_0[0x18]; 5761 5762 u8 syndrome[0x20]; 5763 5764 u8 reserved_1[0x40]; 5765 5766 u8 packet_headers_log[128][0x8]; 5767 5768 u8 packet_syndrome[64][0x8]; 5769 }; 5770 5771 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5772 u8 opcode[0x10]; 5773 u8 reserved_0[0x10]; 5774 5775 u8 reserved_1[0x10]; 5776 u8 op_mod[0x10]; 5777 5778 u8 reserved_2[0x40]; 5779 }; 5780 5781 struct mlx5_ifc_gen_eqe_in_bits { 5782 u8 opcode[0x10]; 5783 u8 reserved_0[0x10]; 5784 5785 u8 reserved_1[0x10]; 5786 u8 op_mod[0x10]; 5787 5788 u8 reserved_2[0x18]; 5789 u8 eq_number[0x8]; 5790 5791 u8 reserved_3[0x20]; 5792 5793 u8 eqe[64][0x8]; 5794 }; 5795 5796 struct mlx5_ifc_gen_eq_out_bits { 5797 u8 status[0x8]; 5798 u8 reserved_0[0x18]; 5799 5800 u8 syndrome[0x20]; 5801 5802 u8 reserved_1[0x40]; 5803 }; 5804 5805 struct mlx5_ifc_enable_hca_out_bits { 5806 u8 status[0x8]; 5807 u8 reserved_0[0x18]; 5808 5809 u8 syndrome[0x20]; 5810 5811 u8 reserved_1[0x20]; 5812 }; 5813 5814 struct mlx5_ifc_enable_hca_in_bits { 5815 u8 opcode[0x10]; 5816 u8 reserved_0[0x10]; 5817 5818 u8 reserved_1[0x10]; 5819 u8 op_mod[0x10]; 5820 5821 u8 reserved_2[0x10]; 5822 u8 function_id[0x10]; 5823 5824 u8 reserved_3[0x20]; 5825 }; 5826 5827 struct mlx5_ifc_drain_dct_out_bits { 5828 u8 status[0x8]; 5829 u8 reserved_0[0x18]; 5830 5831 u8 syndrome[0x20]; 5832 5833 u8 reserved_1[0x40]; 5834 }; 5835 5836 struct mlx5_ifc_drain_dct_in_bits { 5837 u8 opcode[0x10]; 5838 u8 reserved_0[0x10]; 5839 5840 u8 reserved_1[0x10]; 5841 u8 op_mod[0x10]; 5842 5843 u8 reserved_2[0x8]; 5844 u8 dctn[0x18]; 5845 5846 u8 reserved_3[0x20]; 5847 }; 5848 5849 struct mlx5_ifc_disable_hca_out_bits { 5850 u8 status[0x8]; 5851 u8 reserved_0[0x18]; 5852 5853 u8 syndrome[0x20]; 5854 5855 u8 reserved_1[0x20]; 5856 }; 5857 5858 struct mlx5_ifc_disable_hca_in_bits { 5859 u8 opcode[0x10]; 5860 u8 reserved_0[0x10]; 5861 5862 u8 reserved_1[0x10]; 5863 u8 op_mod[0x10]; 5864 5865 u8 reserved_2[0x10]; 5866 u8 function_id[0x10]; 5867 5868 u8 reserved_3[0x20]; 5869 }; 5870 5871 struct mlx5_ifc_detach_from_mcg_out_bits { 5872 u8 status[0x8]; 5873 u8 reserved_0[0x18]; 5874 5875 u8 syndrome[0x20]; 5876 5877 u8 reserved_1[0x40]; 5878 }; 5879 5880 struct mlx5_ifc_detach_from_mcg_in_bits { 5881 u8 opcode[0x10]; 5882 u8 reserved_0[0x10]; 5883 5884 u8 reserved_1[0x10]; 5885 u8 op_mod[0x10]; 5886 5887 u8 reserved_2[0x8]; 5888 u8 qpn[0x18]; 5889 5890 u8 reserved_3[0x20]; 5891 5892 u8 multicast_gid[16][0x8]; 5893 }; 5894 5895 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5896 u8 status[0x8]; 5897 u8 reserved_0[0x18]; 5898 5899 u8 syndrome[0x20]; 5900 5901 u8 reserved_1[0x40]; 5902 }; 5903 5904 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5905 u8 opcode[0x10]; 5906 u8 reserved_0[0x10]; 5907 5908 u8 reserved_1[0x10]; 5909 u8 op_mod[0x10]; 5910 5911 u8 reserved_2[0x8]; 5912 u8 xrc_srqn[0x18]; 5913 5914 u8 reserved_3[0x20]; 5915 }; 5916 5917 struct mlx5_ifc_destroy_tis_out_bits { 5918 u8 status[0x8]; 5919 u8 reserved_0[0x18]; 5920 5921 u8 syndrome[0x20]; 5922 5923 u8 reserved_1[0x40]; 5924 }; 5925 5926 struct mlx5_ifc_destroy_tis_in_bits { 5927 u8 opcode[0x10]; 5928 u8 reserved_0[0x10]; 5929 5930 u8 reserved_1[0x10]; 5931 u8 op_mod[0x10]; 5932 5933 u8 reserved_2[0x8]; 5934 u8 tisn[0x18]; 5935 5936 u8 reserved_3[0x20]; 5937 }; 5938 5939 struct mlx5_ifc_destroy_tir_out_bits { 5940 u8 status[0x8]; 5941 u8 reserved_0[0x18]; 5942 5943 u8 syndrome[0x20]; 5944 5945 u8 reserved_1[0x40]; 5946 }; 5947 5948 struct mlx5_ifc_destroy_tir_in_bits { 5949 u8 opcode[0x10]; 5950 u8 reserved_0[0x10]; 5951 5952 u8 reserved_1[0x10]; 5953 u8 op_mod[0x10]; 5954 5955 u8 reserved_2[0x8]; 5956 u8 tirn[0x18]; 5957 5958 u8 reserved_3[0x20]; 5959 }; 5960 5961 struct mlx5_ifc_destroy_srq_out_bits { 5962 u8 status[0x8]; 5963 u8 reserved_0[0x18]; 5964 5965 u8 syndrome[0x20]; 5966 5967 u8 reserved_1[0x40]; 5968 }; 5969 5970 struct mlx5_ifc_destroy_srq_in_bits { 5971 u8 opcode[0x10]; 5972 u8 reserved_0[0x10]; 5973 5974 u8 reserved_1[0x10]; 5975 u8 op_mod[0x10]; 5976 5977 u8 reserved_2[0x8]; 5978 u8 srqn[0x18]; 5979 5980 u8 reserved_3[0x20]; 5981 }; 5982 5983 struct mlx5_ifc_destroy_sq_out_bits { 5984 u8 status[0x8]; 5985 u8 reserved_0[0x18]; 5986 5987 u8 syndrome[0x20]; 5988 5989 u8 reserved_1[0x40]; 5990 }; 5991 5992 struct mlx5_ifc_destroy_sq_in_bits { 5993 u8 opcode[0x10]; 5994 u8 reserved_0[0x10]; 5995 5996 u8 reserved_1[0x10]; 5997 u8 op_mod[0x10]; 5998 5999 u8 reserved_2[0x8]; 6000 u8 sqn[0x18]; 6001 6002 u8 reserved_3[0x20]; 6003 }; 6004 6005 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6006 u8 status[0x8]; 6007 u8 reserved_at_8[0x18]; 6008 6009 u8 syndrome[0x20]; 6010 6011 u8 reserved_at_40[0x1c0]; 6012 }; 6013 6014 enum { 6015 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6016 }; 6017 6018 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6019 u8 opcode[0x10]; 6020 u8 reserved_at_10[0x10]; 6021 6022 u8 reserved_at_20[0x10]; 6023 u8 op_mod[0x10]; 6024 6025 u8 scheduling_hierarchy[0x8]; 6026 u8 reserved_at_48[0x18]; 6027 6028 u8 scheduling_element_id[0x20]; 6029 6030 u8 reserved_at_80[0x180]; 6031 }; 6032 6033 struct mlx5_ifc_destroy_rqt_out_bits { 6034 u8 status[0x8]; 6035 u8 reserved_0[0x18]; 6036 6037 u8 syndrome[0x20]; 6038 6039 u8 reserved_1[0x40]; 6040 }; 6041 6042 struct mlx5_ifc_destroy_rqt_in_bits { 6043 u8 opcode[0x10]; 6044 u8 reserved_0[0x10]; 6045 6046 u8 reserved_1[0x10]; 6047 u8 op_mod[0x10]; 6048 6049 u8 reserved_2[0x8]; 6050 u8 rqtn[0x18]; 6051 6052 u8 reserved_3[0x20]; 6053 }; 6054 6055 struct mlx5_ifc_destroy_rq_out_bits { 6056 u8 status[0x8]; 6057 u8 reserved_0[0x18]; 6058 6059 u8 syndrome[0x20]; 6060 6061 u8 reserved_1[0x40]; 6062 }; 6063 6064 struct mlx5_ifc_destroy_rq_in_bits { 6065 u8 opcode[0x10]; 6066 u8 reserved_0[0x10]; 6067 6068 u8 reserved_1[0x10]; 6069 u8 op_mod[0x10]; 6070 6071 u8 reserved_2[0x8]; 6072 u8 rqn[0x18]; 6073 6074 u8 reserved_3[0x20]; 6075 }; 6076 6077 struct mlx5_ifc_destroy_rmp_out_bits { 6078 u8 status[0x8]; 6079 u8 reserved_0[0x18]; 6080 6081 u8 syndrome[0x20]; 6082 6083 u8 reserved_1[0x40]; 6084 }; 6085 6086 struct mlx5_ifc_destroy_rmp_in_bits { 6087 u8 opcode[0x10]; 6088 u8 reserved_0[0x10]; 6089 6090 u8 reserved_1[0x10]; 6091 u8 op_mod[0x10]; 6092 6093 u8 reserved_2[0x8]; 6094 u8 rmpn[0x18]; 6095 6096 u8 reserved_3[0x20]; 6097 }; 6098 6099 struct mlx5_ifc_destroy_qp_out_bits { 6100 u8 status[0x8]; 6101 u8 reserved_0[0x18]; 6102 6103 u8 syndrome[0x20]; 6104 6105 u8 reserved_1[0x40]; 6106 }; 6107 6108 struct mlx5_ifc_destroy_qp_in_bits { 6109 u8 opcode[0x10]; 6110 u8 reserved_0[0x10]; 6111 6112 u8 reserved_1[0x10]; 6113 u8 op_mod[0x10]; 6114 6115 u8 reserved_2[0x8]; 6116 u8 qpn[0x18]; 6117 6118 u8 reserved_3[0x20]; 6119 }; 6120 6121 struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6122 u8 status[0x8]; 6123 u8 reserved_at_8[0x18]; 6124 6125 u8 syndrome[0x20]; 6126 6127 u8 reserved_at_40[0x1c0]; 6128 }; 6129 6130 struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6131 u8 opcode[0x10]; 6132 u8 reserved_at_10[0x10]; 6133 6134 u8 reserved_at_20[0x10]; 6135 u8 op_mod[0x10]; 6136 6137 u8 reserved_at_40[0x20]; 6138 6139 u8 reserved_at_60[0x10]; 6140 u8 qos_para_vport_number[0x10]; 6141 6142 u8 reserved_at_80[0x180]; 6143 }; 6144 6145 struct mlx5_ifc_destroy_psv_out_bits { 6146 u8 status[0x8]; 6147 u8 reserved_0[0x18]; 6148 6149 u8 syndrome[0x20]; 6150 6151 u8 reserved_1[0x40]; 6152 }; 6153 6154 struct mlx5_ifc_destroy_psv_in_bits { 6155 u8 opcode[0x10]; 6156 u8 reserved_0[0x10]; 6157 6158 u8 reserved_1[0x10]; 6159 u8 op_mod[0x10]; 6160 6161 u8 reserved_2[0x8]; 6162 u8 psvn[0x18]; 6163 6164 u8 reserved_3[0x20]; 6165 }; 6166 6167 struct mlx5_ifc_destroy_mkey_out_bits { 6168 u8 status[0x8]; 6169 u8 reserved_0[0x18]; 6170 6171 u8 syndrome[0x20]; 6172 6173 u8 reserved_1[0x40]; 6174 }; 6175 6176 struct mlx5_ifc_destroy_mkey_in_bits { 6177 u8 opcode[0x10]; 6178 u8 reserved_0[0x10]; 6179 6180 u8 reserved_1[0x10]; 6181 u8 op_mod[0x10]; 6182 6183 u8 reserved_2[0x8]; 6184 u8 mkey_index[0x18]; 6185 6186 u8 reserved_3[0x20]; 6187 }; 6188 6189 struct mlx5_ifc_destroy_flow_table_out_bits { 6190 u8 status[0x8]; 6191 u8 reserved_0[0x18]; 6192 6193 u8 syndrome[0x20]; 6194 6195 u8 reserved_1[0x40]; 6196 }; 6197 6198 struct mlx5_ifc_destroy_flow_table_in_bits { 6199 u8 opcode[0x10]; 6200 u8 reserved_0[0x10]; 6201 6202 u8 reserved_1[0x10]; 6203 u8 op_mod[0x10]; 6204 6205 u8 other_vport[0x1]; 6206 u8 reserved_2[0xf]; 6207 u8 vport_number[0x10]; 6208 6209 u8 reserved_3[0x20]; 6210 6211 u8 table_type[0x8]; 6212 u8 reserved_4[0x18]; 6213 6214 u8 reserved_5[0x8]; 6215 u8 table_id[0x18]; 6216 6217 u8 reserved_6[0x140]; 6218 }; 6219 6220 struct mlx5_ifc_destroy_flow_group_out_bits { 6221 u8 status[0x8]; 6222 u8 reserved_0[0x18]; 6223 6224 u8 syndrome[0x20]; 6225 6226 u8 reserved_1[0x40]; 6227 }; 6228 6229 struct mlx5_ifc_destroy_flow_group_in_bits { 6230 u8 opcode[0x10]; 6231 u8 reserved_0[0x10]; 6232 6233 u8 reserved_1[0x10]; 6234 u8 op_mod[0x10]; 6235 6236 u8 other_vport[0x1]; 6237 u8 reserved_2[0xf]; 6238 u8 vport_number[0x10]; 6239 6240 u8 reserved_3[0x20]; 6241 6242 u8 table_type[0x8]; 6243 u8 reserved_4[0x18]; 6244 6245 u8 reserved_5[0x8]; 6246 u8 table_id[0x18]; 6247 6248 u8 group_id[0x20]; 6249 6250 u8 reserved_6[0x120]; 6251 }; 6252 6253 struct mlx5_ifc_destroy_eq_out_bits { 6254 u8 status[0x8]; 6255 u8 reserved_0[0x18]; 6256 6257 u8 syndrome[0x20]; 6258 6259 u8 reserved_1[0x40]; 6260 }; 6261 6262 struct mlx5_ifc_destroy_eq_in_bits { 6263 u8 opcode[0x10]; 6264 u8 reserved_0[0x10]; 6265 6266 u8 reserved_1[0x10]; 6267 u8 op_mod[0x10]; 6268 6269 u8 reserved_2[0x18]; 6270 u8 eq_number[0x8]; 6271 6272 u8 reserved_3[0x20]; 6273 }; 6274 6275 struct mlx5_ifc_destroy_dct_out_bits { 6276 u8 status[0x8]; 6277 u8 reserved_0[0x18]; 6278 6279 u8 syndrome[0x20]; 6280 6281 u8 reserved_1[0x40]; 6282 }; 6283 6284 struct mlx5_ifc_destroy_dct_in_bits { 6285 u8 opcode[0x10]; 6286 u8 reserved_0[0x10]; 6287 6288 u8 reserved_1[0x10]; 6289 u8 op_mod[0x10]; 6290 6291 u8 reserved_2[0x8]; 6292 u8 dctn[0x18]; 6293 6294 u8 reserved_3[0x20]; 6295 }; 6296 6297 struct mlx5_ifc_destroy_cq_out_bits { 6298 u8 status[0x8]; 6299 u8 reserved_0[0x18]; 6300 6301 u8 syndrome[0x20]; 6302 6303 u8 reserved_1[0x40]; 6304 }; 6305 6306 struct mlx5_ifc_destroy_cq_in_bits { 6307 u8 opcode[0x10]; 6308 u8 reserved_0[0x10]; 6309 6310 u8 reserved_1[0x10]; 6311 u8 op_mod[0x10]; 6312 6313 u8 reserved_2[0x8]; 6314 u8 cqn[0x18]; 6315 6316 u8 reserved_3[0x20]; 6317 }; 6318 6319 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6320 u8 status[0x8]; 6321 u8 reserved_0[0x18]; 6322 6323 u8 syndrome[0x20]; 6324 6325 u8 reserved_1[0x40]; 6326 }; 6327 6328 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6329 u8 opcode[0x10]; 6330 u8 reserved_0[0x10]; 6331 6332 u8 reserved_1[0x10]; 6333 u8 op_mod[0x10]; 6334 6335 u8 reserved_2[0x20]; 6336 6337 u8 reserved_3[0x10]; 6338 u8 vxlan_udp_port[0x10]; 6339 }; 6340 6341 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6342 u8 status[0x8]; 6343 u8 reserved_0[0x18]; 6344 6345 u8 syndrome[0x20]; 6346 6347 u8 reserved_1[0x40]; 6348 }; 6349 6350 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6351 u8 opcode[0x10]; 6352 u8 reserved_0[0x10]; 6353 6354 u8 reserved_1[0x10]; 6355 u8 op_mod[0x10]; 6356 6357 u8 reserved_2[0x60]; 6358 6359 u8 reserved_3[0x8]; 6360 u8 table_index[0x18]; 6361 6362 u8 reserved_4[0x140]; 6363 }; 6364 6365 struct mlx5_ifc_delete_fte_out_bits { 6366 u8 status[0x8]; 6367 u8 reserved_0[0x18]; 6368 6369 u8 syndrome[0x20]; 6370 6371 u8 reserved_1[0x40]; 6372 }; 6373 6374 struct mlx5_ifc_delete_fte_in_bits { 6375 u8 opcode[0x10]; 6376 u8 reserved_0[0x10]; 6377 6378 u8 reserved_1[0x10]; 6379 u8 op_mod[0x10]; 6380 6381 u8 other_vport[0x1]; 6382 u8 reserved_2[0xf]; 6383 u8 vport_number[0x10]; 6384 6385 u8 reserved_3[0x20]; 6386 6387 u8 table_type[0x8]; 6388 u8 reserved_4[0x18]; 6389 6390 u8 reserved_5[0x8]; 6391 u8 table_id[0x18]; 6392 6393 u8 reserved_6[0x40]; 6394 6395 u8 flow_index[0x20]; 6396 6397 u8 reserved_7[0xe0]; 6398 }; 6399 6400 struct mlx5_ifc_dealloc_xrcd_out_bits { 6401 u8 status[0x8]; 6402 u8 reserved_0[0x18]; 6403 6404 u8 syndrome[0x20]; 6405 6406 u8 reserved_1[0x40]; 6407 }; 6408 6409 struct mlx5_ifc_dealloc_xrcd_in_bits { 6410 u8 opcode[0x10]; 6411 u8 reserved_0[0x10]; 6412 6413 u8 reserved_1[0x10]; 6414 u8 op_mod[0x10]; 6415 6416 u8 reserved_2[0x8]; 6417 u8 xrcd[0x18]; 6418 6419 u8 reserved_3[0x20]; 6420 }; 6421 6422 struct mlx5_ifc_dealloc_uar_out_bits { 6423 u8 status[0x8]; 6424 u8 reserved_0[0x18]; 6425 6426 u8 syndrome[0x20]; 6427 6428 u8 reserved_1[0x40]; 6429 }; 6430 6431 struct mlx5_ifc_dealloc_uar_in_bits { 6432 u8 opcode[0x10]; 6433 u8 reserved_0[0x10]; 6434 6435 u8 reserved_1[0x10]; 6436 u8 op_mod[0x10]; 6437 6438 u8 reserved_2[0x8]; 6439 u8 uar[0x18]; 6440 6441 u8 reserved_3[0x20]; 6442 }; 6443 6444 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6445 u8 status[0x8]; 6446 u8 reserved_0[0x18]; 6447 6448 u8 syndrome[0x20]; 6449 6450 u8 reserved_1[0x40]; 6451 }; 6452 6453 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6454 u8 opcode[0x10]; 6455 u8 reserved_0[0x10]; 6456 6457 u8 reserved_1[0x10]; 6458 u8 op_mod[0x10]; 6459 6460 u8 reserved_2[0x8]; 6461 u8 transport_domain[0x18]; 6462 6463 u8 reserved_3[0x20]; 6464 }; 6465 6466 struct mlx5_ifc_dealloc_q_counter_out_bits { 6467 u8 status[0x8]; 6468 u8 reserved_0[0x18]; 6469 6470 u8 syndrome[0x20]; 6471 6472 u8 reserved_1[0x40]; 6473 }; 6474 6475 struct mlx5_ifc_counter_id_bits { 6476 u8 reserved[0x10]; 6477 u8 counter_id[0x10]; 6478 }; 6479 6480 struct mlx5_ifc_diagnostic_params_context_bits { 6481 u8 num_of_counters[0x10]; 6482 u8 reserved_2[0x8]; 6483 u8 log_num_of_samples[0x8]; 6484 6485 u8 single[0x1]; 6486 u8 repetitive[0x1]; 6487 u8 sync[0x1]; 6488 u8 clear[0x1]; 6489 u8 on_demand[0x1]; 6490 u8 enable[0x1]; 6491 u8 reserved_3[0x12]; 6492 u8 log_sample_period[0x8]; 6493 6494 u8 reserved_4[0x80]; 6495 6496 struct mlx5_ifc_counter_id_bits counter_id[0]; 6497 }; 6498 6499 struct mlx5_ifc_set_diagnostic_params_in_bits { 6500 u8 opcode[0x10]; 6501 u8 reserved_0[0x10]; 6502 6503 u8 reserved_1[0x10]; 6504 u8 op_mod[0x10]; 6505 6506 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 6507 }; 6508 6509 struct mlx5_ifc_set_diagnostic_params_out_bits { 6510 u8 status[0x8]; 6511 u8 reserved_0[0x18]; 6512 6513 u8 syndrome[0x20]; 6514 6515 u8 reserved_1[0x40]; 6516 }; 6517 6518 struct mlx5_ifc_query_diagnostic_counters_in_bits { 6519 u8 opcode[0x10]; 6520 u8 reserved_0[0x10]; 6521 6522 u8 reserved_1[0x10]; 6523 u8 op_mod[0x10]; 6524 6525 u8 num_of_samples[0x10]; 6526 u8 sample_index[0x10]; 6527 6528 u8 reserved_2[0x20]; 6529 }; 6530 6531 struct mlx5_ifc_diagnostic_counter_bits { 6532 u8 counter_id[0x10]; 6533 u8 sample_id[0x10]; 6534 6535 u8 time_stamp_31_0[0x20]; 6536 6537 u8 counter_value_h[0x20]; 6538 6539 u8 counter_value_l[0x20]; 6540 }; 6541 6542 struct mlx5_ifc_query_diagnostic_counters_out_bits { 6543 u8 status[0x8]; 6544 u8 reserved_0[0x18]; 6545 6546 u8 syndrome[0x20]; 6547 6548 u8 reserved_1[0x40]; 6549 6550 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 6551 }; 6552 6553 struct mlx5_ifc_dealloc_q_counter_in_bits { 6554 u8 opcode[0x10]; 6555 u8 reserved_0[0x10]; 6556 6557 u8 reserved_1[0x10]; 6558 u8 op_mod[0x10]; 6559 6560 u8 reserved_2[0x18]; 6561 u8 counter_set_id[0x8]; 6562 6563 u8 reserved_3[0x20]; 6564 }; 6565 6566 struct mlx5_ifc_dealloc_pd_out_bits { 6567 u8 status[0x8]; 6568 u8 reserved_0[0x18]; 6569 6570 u8 syndrome[0x20]; 6571 6572 u8 reserved_1[0x40]; 6573 }; 6574 6575 struct mlx5_ifc_dealloc_pd_in_bits { 6576 u8 opcode[0x10]; 6577 u8 reserved_0[0x10]; 6578 6579 u8 reserved_1[0x10]; 6580 u8 op_mod[0x10]; 6581 6582 u8 reserved_2[0x8]; 6583 u8 pd[0x18]; 6584 6585 u8 reserved_3[0x20]; 6586 }; 6587 6588 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6589 u8 status[0x8]; 6590 u8 reserved_0[0x18]; 6591 6592 u8 syndrome[0x20]; 6593 6594 u8 reserved_1[0x40]; 6595 }; 6596 6597 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6598 u8 opcode[0x10]; 6599 u8 reserved_0[0x10]; 6600 6601 u8 reserved_1[0x10]; 6602 u8 op_mod[0x10]; 6603 6604 u8 reserved_2[0x10]; 6605 u8 flow_counter_id[0x10]; 6606 6607 u8 reserved_3[0x20]; 6608 }; 6609 6610 struct mlx5_ifc_deactivate_tracer_out_bits { 6611 u8 status[0x8]; 6612 u8 reserved_0[0x18]; 6613 6614 u8 syndrome[0x20]; 6615 6616 u8 reserved_1[0x40]; 6617 }; 6618 6619 struct mlx5_ifc_deactivate_tracer_in_bits { 6620 u8 opcode[0x10]; 6621 u8 reserved_0[0x10]; 6622 6623 u8 reserved_1[0x10]; 6624 u8 op_mod[0x10]; 6625 6626 u8 mkey[0x20]; 6627 6628 u8 reserved_2[0x20]; 6629 }; 6630 6631 struct mlx5_ifc_create_xrc_srq_out_bits { 6632 u8 status[0x8]; 6633 u8 reserved_0[0x18]; 6634 6635 u8 syndrome[0x20]; 6636 6637 u8 reserved_1[0x8]; 6638 u8 xrc_srqn[0x18]; 6639 6640 u8 reserved_2[0x20]; 6641 }; 6642 6643 struct mlx5_ifc_create_xrc_srq_in_bits { 6644 u8 opcode[0x10]; 6645 u8 reserved_0[0x10]; 6646 6647 u8 reserved_1[0x10]; 6648 u8 op_mod[0x10]; 6649 6650 u8 reserved_2[0x40]; 6651 6652 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6653 6654 u8 reserved_3[0x600]; 6655 6656 u8 pas[0][0x40]; 6657 }; 6658 6659 struct mlx5_ifc_create_tis_out_bits { 6660 u8 status[0x8]; 6661 u8 reserved_0[0x18]; 6662 6663 u8 syndrome[0x20]; 6664 6665 u8 reserved_1[0x8]; 6666 u8 tisn[0x18]; 6667 6668 u8 reserved_2[0x20]; 6669 }; 6670 6671 struct mlx5_ifc_create_tis_in_bits { 6672 u8 opcode[0x10]; 6673 u8 reserved_0[0x10]; 6674 6675 u8 reserved_1[0x10]; 6676 u8 op_mod[0x10]; 6677 6678 u8 reserved_2[0xc0]; 6679 6680 struct mlx5_ifc_tisc_bits ctx; 6681 }; 6682 6683 struct mlx5_ifc_create_tir_out_bits { 6684 u8 status[0x8]; 6685 u8 reserved_0[0x18]; 6686 6687 u8 syndrome[0x20]; 6688 6689 u8 reserved_1[0x8]; 6690 u8 tirn[0x18]; 6691 6692 u8 reserved_2[0x20]; 6693 }; 6694 6695 struct mlx5_ifc_create_tir_in_bits { 6696 u8 opcode[0x10]; 6697 u8 reserved_0[0x10]; 6698 6699 u8 reserved_1[0x10]; 6700 u8 op_mod[0x10]; 6701 6702 u8 reserved_2[0xc0]; 6703 6704 struct mlx5_ifc_tirc_bits tir_context; 6705 }; 6706 6707 struct mlx5_ifc_create_srq_out_bits { 6708 u8 status[0x8]; 6709 u8 reserved_0[0x18]; 6710 6711 u8 syndrome[0x20]; 6712 6713 u8 reserved_1[0x8]; 6714 u8 srqn[0x18]; 6715 6716 u8 reserved_2[0x20]; 6717 }; 6718 6719 struct mlx5_ifc_create_srq_in_bits { 6720 u8 opcode[0x10]; 6721 u8 reserved_0[0x10]; 6722 6723 u8 reserved_1[0x10]; 6724 u8 op_mod[0x10]; 6725 6726 u8 reserved_2[0x40]; 6727 6728 struct mlx5_ifc_srqc_bits srq_context_entry; 6729 6730 u8 reserved_3[0x600]; 6731 6732 u8 pas[0][0x40]; 6733 }; 6734 6735 struct mlx5_ifc_create_sq_out_bits { 6736 u8 status[0x8]; 6737 u8 reserved_0[0x18]; 6738 6739 u8 syndrome[0x20]; 6740 6741 u8 reserved_1[0x8]; 6742 u8 sqn[0x18]; 6743 6744 u8 reserved_2[0x20]; 6745 }; 6746 6747 struct mlx5_ifc_create_sq_in_bits { 6748 u8 opcode[0x10]; 6749 u8 reserved_0[0x10]; 6750 6751 u8 reserved_1[0x10]; 6752 u8 op_mod[0x10]; 6753 6754 u8 reserved_2[0xc0]; 6755 6756 struct mlx5_ifc_sqc_bits ctx; 6757 }; 6758 6759 struct mlx5_ifc_create_scheduling_element_out_bits { 6760 u8 status[0x8]; 6761 u8 reserved_at_8[0x18]; 6762 6763 u8 syndrome[0x20]; 6764 6765 u8 reserved_at_40[0x40]; 6766 6767 u8 scheduling_element_id[0x20]; 6768 6769 u8 reserved_at_a0[0x160]; 6770 }; 6771 6772 enum { 6773 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6774 }; 6775 6776 struct mlx5_ifc_create_scheduling_element_in_bits { 6777 u8 opcode[0x10]; 6778 u8 reserved_at_10[0x10]; 6779 6780 u8 reserved_at_20[0x10]; 6781 u8 op_mod[0x10]; 6782 6783 u8 scheduling_hierarchy[0x8]; 6784 u8 reserved_at_48[0x18]; 6785 6786 u8 reserved_at_60[0xa0]; 6787 6788 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6789 6790 u8 reserved_at_300[0x100]; 6791 }; 6792 6793 struct mlx5_ifc_create_rqt_out_bits { 6794 u8 status[0x8]; 6795 u8 reserved_0[0x18]; 6796 6797 u8 syndrome[0x20]; 6798 6799 u8 reserved_1[0x8]; 6800 u8 rqtn[0x18]; 6801 6802 u8 reserved_2[0x20]; 6803 }; 6804 6805 struct mlx5_ifc_create_rqt_in_bits { 6806 u8 opcode[0x10]; 6807 u8 reserved_0[0x10]; 6808 6809 u8 reserved_1[0x10]; 6810 u8 op_mod[0x10]; 6811 6812 u8 reserved_2[0xc0]; 6813 6814 struct mlx5_ifc_rqtc_bits rqt_context; 6815 }; 6816 6817 struct mlx5_ifc_create_rq_out_bits { 6818 u8 status[0x8]; 6819 u8 reserved_0[0x18]; 6820 6821 u8 syndrome[0x20]; 6822 6823 u8 reserved_1[0x8]; 6824 u8 rqn[0x18]; 6825 6826 u8 reserved_2[0x20]; 6827 }; 6828 6829 struct mlx5_ifc_create_rq_in_bits { 6830 u8 opcode[0x10]; 6831 u8 reserved_0[0x10]; 6832 6833 u8 reserved_1[0x10]; 6834 u8 op_mod[0x10]; 6835 6836 u8 reserved_2[0xc0]; 6837 6838 struct mlx5_ifc_rqc_bits ctx; 6839 }; 6840 6841 struct mlx5_ifc_create_rmp_out_bits { 6842 u8 status[0x8]; 6843 u8 reserved_0[0x18]; 6844 6845 u8 syndrome[0x20]; 6846 6847 u8 reserved_1[0x8]; 6848 u8 rmpn[0x18]; 6849 6850 u8 reserved_2[0x20]; 6851 }; 6852 6853 struct mlx5_ifc_create_rmp_in_bits { 6854 u8 opcode[0x10]; 6855 u8 reserved_0[0x10]; 6856 6857 u8 reserved_1[0x10]; 6858 u8 op_mod[0x10]; 6859 6860 u8 reserved_2[0xc0]; 6861 6862 struct mlx5_ifc_rmpc_bits ctx; 6863 }; 6864 6865 struct mlx5_ifc_create_qp_out_bits { 6866 u8 status[0x8]; 6867 u8 reserved_0[0x18]; 6868 6869 u8 syndrome[0x20]; 6870 6871 u8 reserved_1[0x8]; 6872 u8 qpn[0x18]; 6873 6874 u8 reserved_2[0x20]; 6875 }; 6876 6877 struct mlx5_ifc_create_qp_in_bits { 6878 u8 opcode[0x10]; 6879 u8 reserved_0[0x10]; 6880 6881 u8 reserved_1[0x10]; 6882 u8 op_mod[0x10]; 6883 6884 u8 reserved_2[0x8]; 6885 u8 input_qpn[0x18]; 6886 6887 u8 reserved_3[0x20]; 6888 6889 u8 opt_param_mask[0x20]; 6890 6891 u8 reserved_4[0x20]; 6892 6893 struct mlx5_ifc_qpc_bits qpc; 6894 6895 u8 reserved_5[0x80]; 6896 6897 u8 pas[0][0x40]; 6898 }; 6899 6900 struct mlx5_ifc_create_qos_para_vport_out_bits { 6901 u8 status[0x8]; 6902 u8 reserved_at_8[0x18]; 6903 6904 u8 syndrome[0x20]; 6905 6906 u8 reserved_at_40[0x20]; 6907 6908 u8 reserved_at_60[0x10]; 6909 u8 qos_para_vport_number[0x10]; 6910 6911 u8 reserved_at_80[0x180]; 6912 }; 6913 6914 struct mlx5_ifc_create_qos_para_vport_in_bits { 6915 u8 opcode[0x10]; 6916 u8 reserved_at_10[0x10]; 6917 6918 u8 reserved_at_20[0x10]; 6919 u8 op_mod[0x10]; 6920 6921 u8 reserved_at_40[0x1c0]; 6922 }; 6923 6924 struct mlx5_ifc_create_psv_out_bits { 6925 u8 status[0x8]; 6926 u8 reserved_0[0x18]; 6927 6928 u8 syndrome[0x20]; 6929 6930 u8 reserved_1[0x40]; 6931 6932 u8 reserved_2[0x8]; 6933 u8 psv0_index[0x18]; 6934 6935 u8 reserved_3[0x8]; 6936 u8 psv1_index[0x18]; 6937 6938 u8 reserved_4[0x8]; 6939 u8 psv2_index[0x18]; 6940 6941 u8 reserved_5[0x8]; 6942 u8 psv3_index[0x18]; 6943 }; 6944 6945 struct mlx5_ifc_create_psv_in_bits { 6946 u8 opcode[0x10]; 6947 u8 reserved_0[0x10]; 6948 6949 u8 reserved_1[0x10]; 6950 u8 op_mod[0x10]; 6951 6952 u8 num_psv[0x4]; 6953 u8 reserved_2[0x4]; 6954 u8 pd[0x18]; 6955 6956 u8 reserved_3[0x20]; 6957 }; 6958 6959 struct mlx5_ifc_create_mkey_out_bits { 6960 u8 status[0x8]; 6961 u8 reserved_0[0x18]; 6962 6963 u8 syndrome[0x20]; 6964 6965 u8 reserved_1[0x8]; 6966 u8 mkey_index[0x18]; 6967 6968 u8 reserved_2[0x20]; 6969 }; 6970 6971 struct mlx5_ifc_create_mkey_in_bits { 6972 u8 opcode[0x10]; 6973 u8 reserved_0[0x10]; 6974 6975 u8 reserved_1[0x10]; 6976 u8 op_mod[0x10]; 6977 6978 u8 reserved_2[0x20]; 6979 6980 u8 pg_access[0x1]; 6981 u8 reserved_3[0x1f]; 6982 6983 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6984 6985 u8 reserved_4[0x80]; 6986 6987 u8 translations_octword_actual_size[0x20]; 6988 6989 u8 reserved_5[0x560]; 6990 6991 u8 klm_pas_mtt[0][0x20]; 6992 }; 6993 6994 struct mlx5_ifc_create_flow_table_out_bits { 6995 u8 status[0x8]; 6996 u8 reserved_0[0x18]; 6997 6998 u8 syndrome[0x20]; 6999 7000 u8 reserved_1[0x8]; 7001 u8 table_id[0x18]; 7002 7003 u8 reserved_2[0x20]; 7004 }; 7005 7006 struct mlx5_ifc_create_flow_table_in_bits { 7007 u8 opcode[0x10]; 7008 u8 reserved_at_10[0x10]; 7009 7010 u8 reserved_at_20[0x10]; 7011 u8 op_mod[0x10]; 7012 7013 u8 other_vport[0x1]; 7014 u8 reserved_at_41[0xf]; 7015 u8 vport_number[0x10]; 7016 7017 u8 reserved_at_60[0x20]; 7018 7019 u8 table_type[0x8]; 7020 u8 reserved_at_88[0x18]; 7021 7022 u8 reserved_at_a0[0x20]; 7023 7024 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7025 }; 7026 7027 struct mlx5_ifc_create_flow_group_out_bits { 7028 u8 status[0x8]; 7029 u8 reserved_0[0x18]; 7030 7031 u8 syndrome[0x20]; 7032 7033 u8 reserved_1[0x8]; 7034 u8 group_id[0x18]; 7035 7036 u8 reserved_2[0x20]; 7037 }; 7038 7039 enum { 7040 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7041 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7042 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7043 }; 7044 7045 struct mlx5_ifc_create_flow_group_in_bits { 7046 u8 opcode[0x10]; 7047 u8 reserved_0[0x10]; 7048 7049 u8 reserved_1[0x10]; 7050 u8 op_mod[0x10]; 7051 7052 u8 other_vport[0x1]; 7053 u8 reserved_2[0xf]; 7054 u8 vport_number[0x10]; 7055 7056 u8 reserved_3[0x20]; 7057 7058 u8 table_type[0x8]; 7059 u8 reserved_4[0x18]; 7060 7061 u8 reserved_5[0x8]; 7062 u8 table_id[0x18]; 7063 7064 u8 reserved_6[0x20]; 7065 7066 u8 start_flow_index[0x20]; 7067 7068 u8 reserved_7[0x20]; 7069 7070 u8 end_flow_index[0x20]; 7071 7072 u8 reserved_8[0xa0]; 7073 7074 u8 reserved_9[0x18]; 7075 u8 match_criteria_enable[0x8]; 7076 7077 struct mlx5_ifc_fte_match_param_bits match_criteria; 7078 7079 u8 reserved_10[0xe00]; 7080 }; 7081 7082 struct mlx5_ifc_create_eq_out_bits { 7083 u8 status[0x8]; 7084 u8 reserved_0[0x18]; 7085 7086 u8 syndrome[0x20]; 7087 7088 u8 reserved_1[0x18]; 7089 u8 eq_number[0x8]; 7090 7091 u8 reserved_2[0x20]; 7092 }; 7093 7094 struct mlx5_ifc_create_eq_in_bits { 7095 u8 opcode[0x10]; 7096 u8 reserved_0[0x10]; 7097 7098 u8 reserved_1[0x10]; 7099 u8 op_mod[0x10]; 7100 7101 u8 reserved_2[0x40]; 7102 7103 struct mlx5_ifc_eqc_bits eq_context_entry; 7104 7105 u8 reserved_3[0x40]; 7106 7107 u8 event_bitmask[0x40]; 7108 7109 u8 reserved_4[0x580]; 7110 7111 u8 pas[0][0x40]; 7112 }; 7113 7114 struct mlx5_ifc_create_dct_out_bits { 7115 u8 status[0x8]; 7116 u8 reserved_0[0x18]; 7117 7118 u8 syndrome[0x20]; 7119 7120 u8 reserved_1[0x8]; 7121 u8 dctn[0x18]; 7122 7123 u8 reserved_2[0x20]; 7124 }; 7125 7126 struct mlx5_ifc_create_dct_in_bits { 7127 u8 opcode[0x10]; 7128 u8 reserved_0[0x10]; 7129 7130 u8 reserved_1[0x10]; 7131 u8 op_mod[0x10]; 7132 7133 u8 reserved_2[0x40]; 7134 7135 struct mlx5_ifc_dctc_bits dct_context_entry; 7136 7137 u8 reserved_3[0x180]; 7138 }; 7139 7140 struct mlx5_ifc_create_cq_out_bits { 7141 u8 status[0x8]; 7142 u8 reserved_0[0x18]; 7143 7144 u8 syndrome[0x20]; 7145 7146 u8 reserved_1[0x8]; 7147 u8 cqn[0x18]; 7148 7149 u8 reserved_2[0x20]; 7150 }; 7151 7152 struct mlx5_ifc_create_cq_in_bits { 7153 u8 opcode[0x10]; 7154 u8 reserved_0[0x10]; 7155 7156 u8 reserved_1[0x10]; 7157 u8 op_mod[0x10]; 7158 7159 u8 reserved_2[0x40]; 7160 7161 struct mlx5_ifc_cqc_bits cq_context; 7162 7163 u8 reserved_3[0x600]; 7164 7165 u8 pas[0][0x40]; 7166 }; 7167 7168 struct mlx5_ifc_config_int_moderation_out_bits { 7169 u8 status[0x8]; 7170 u8 reserved_0[0x18]; 7171 7172 u8 syndrome[0x20]; 7173 7174 u8 reserved_1[0x4]; 7175 u8 min_delay[0xc]; 7176 u8 int_vector[0x10]; 7177 7178 u8 reserved_2[0x20]; 7179 }; 7180 7181 enum { 7182 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7183 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7184 }; 7185 7186 struct mlx5_ifc_config_int_moderation_in_bits { 7187 u8 opcode[0x10]; 7188 u8 reserved_0[0x10]; 7189 7190 u8 reserved_1[0x10]; 7191 u8 op_mod[0x10]; 7192 7193 u8 reserved_2[0x4]; 7194 u8 min_delay[0xc]; 7195 u8 int_vector[0x10]; 7196 7197 u8 reserved_3[0x20]; 7198 }; 7199 7200 struct mlx5_ifc_attach_to_mcg_out_bits { 7201 u8 status[0x8]; 7202 u8 reserved_0[0x18]; 7203 7204 u8 syndrome[0x20]; 7205 7206 u8 reserved_1[0x40]; 7207 }; 7208 7209 struct mlx5_ifc_attach_to_mcg_in_bits { 7210 u8 opcode[0x10]; 7211 u8 reserved_0[0x10]; 7212 7213 u8 reserved_1[0x10]; 7214 u8 op_mod[0x10]; 7215 7216 u8 reserved_2[0x8]; 7217 u8 qpn[0x18]; 7218 7219 u8 reserved_3[0x20]; 7220 7221 u8 multicast_gid[16][0x8]; 7222 }; 7223 7224 struct mlx5_ifc_arm_xrc_srq_out_bits { 7225 u8 status[0x8]; 7226 u8 reserved_0[0x18]; 7227 7228 u8 syndrome[0x20]; 7229 7230 u8 reserved_1[0x40]; 7231 }; 7232 7233 enum { 7234 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7235 }; 7236 7237 struct mlx5_ifc_arm_xrc_srq_in_bits { 7238 u8 opcode[0x10]; 7239 u8 reserved_0[0x10]; 7240 7241 u8 reserved_1[0x10]; 7242 u8 op_mod[0x10]; 7243 7244 u8 reserved_2[0x8]; 7245 u8 xrc_srqn[0x18]; 7246 7247 u8 reserved_3[0x10]; 7248 u8 lwm[0x10]; 7249 }; 7250 7251 struct mlx5_ifc_arm_rq_out_bits { 7252 u8 status[0x8]; 7253 u8 reserved_0[0x18]; 7254 7255 u8 syndrome[0x20]; 7256 7257 u8 reserved_1[0x40]; 7258 }; 7259 7260 enum { 7261 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7262 }; 7263 7264 struct mlx5_ifc_arm_rq_in_bits { 7265 u8 opcode[0x10]; 7266 u8 reserved_0[0x10]; 7267 7268 u8 reserved_1[0x10]; 7269 u8 op_mod[0x10]; 7270 7271 u8 reserved_2[0x8]; 7272 u8 srq_number[0x18]; 7273 7274 u8 reserved_3[0x10]; 7275 u8 lwm[0x10]; 7276 }; 7277 7278 struct mlx5_ifc_arm_dct_out_bits { 7279 u8 status[0x8]; 7280 u8 reserved_0[0x18]; 7281 7282 u8 syndrome[0x20]; 7283 7284 u8 reserved_1[0x40]; 7285 }; 7286 7287 struct mlx5_ifc_arm_dct_in_bits { 7288 u8 opcode[0x10]; 7289 u8 reserved_0[0x10]; 7290 7291 u8 reserved_1[0x10]; 7292 u8 op_mod[0x10]; 7293 7294 u8 reserved_2[0x8]; 7295 u8 dctn[0x18]; 7296 7297 u8 reserved_3[0x20]; 7298 }; 7299 7300 struct mlx5_ifc_alloc_xrcd_out_bits { 7301 u8 status[0x8]; 7302 u8 reserved_0[0x18]; 7303 7304 u8 syndrome[0x20]; 7305 7306 u8 reserved_1[0x8]; 7307 u8 xrcd[0x18]; 7308 7309 u8 reserved_2[0x20]; 7310 }; 7311 7312 struct mlx5_ifc_alloc_xrcd_in_bits { 7313 u8 opcode[0x10]; 7314 u8 reserved_0[0x10]; 7315 7316 u8 reserved_1[0x10]; 7317 u8 op_mod[0x10]; 7318 7319 u8 reserved_2[0x40]; 7320 }; 7321 7322 struct mlx5_ifc_alloc_uar_out_bits { 7323 u8 status[0x8]; 7324 u8 reserved_0[0x18]; 7325 7326 u8 syndrome[0x20]; 7327 7328 u8 reserved_1[0x8]; 7329 u8 uar[0x18]; 7330 7331 u8 reserved_2[0x20]; 7332 }; 7333 7334 struct mlx5_ifc_alloc_uar_in_bits { 7335 u8 opcode[0x10]; 7336 u8 reserved_0[0x10]; 7337 7338 u8 reserved_1[0x10]; 7339 u8 op_mod[0x10]; 7340 7341 u8 reserved_2[0x40]; 7342 }; 7343 7344 struct mlx5_ifc_alloc_transport_domain_out_bits { 7345 u8 status[0x8]; 7346 u8 reserved_0[0x18]; 7347 7348 u8 syndrome[0x20]; 7349 7350 u8 reserved_1[0x8]; 7351 u8 transport_domain[0x18]; 7352 7353 u8 reserved_2[0x20]; 7354 }; 7355 7356 struct mlx5_ifc_alloc_transport_domain_in_bits { 7357 u8 opcode[0x10]; 7358 u8 reserved_0[0x10]; 7359 7360 u8 reserved_1[0x10]; 7361 u8 op_mod[0x10]; 7362 7363 u8 reserved_2[0x40]; 7364 }; 7365 7366 struct mlx5_ifc_alloc_q_counter_out_bits { 7367 u8 status[0x8]; 7368 u8 reserved_0[0x18]; 7369 7370 u8 syndrome[0x20]; 7371 7372 u8 reserved_1[0x18]; 7373 u8 counter_set_id[0x8]; 7374 7375 u8 reserved_2[0x20]; 7376 }; 7377 7378 struct mlx5_ifc_alloc_q_counter_in_bits { 7379 u8 opcode[0x10]; 7380 u8 reserved_0[0x10]; 7381 7382 u8 reserved_1[0x10]; 7383 u8 op_mod[0x10]; 7384 7385 u8 reserved_2[0x40]; 7386 }; 7387 7388 struct mlx5_ifc_alloc_pd_out_bits { 7389 u8 status[0x8]; 7390 u8 reserved_0[0x18]; 7391 7392 u8 syndrome[0x20]; 7393 7394 u8 reserved_1[0x8]; 7395 u8 pd[0x18]; 7396 7397 u8 reserved_2[0x20]; 7398 }; 7399 7400 struct mlx5_ifc_alloc_pd_in_bits { 7401 u8 opcode[0x10]; 7402 u8 reserved_0[0x10]; 7403 7404 u8 reserved_1[0x10]; 7405 u8 op_mod[0x10]; 7406 7407 u8 reserved_2[0x40]; 7408 }; 7409 7410 struct mlx5_ifc_alloc_flow_counter_out_bits { 7411 u8 status[0x8]; 7412 u8 reserved_0[0x18]; 7413 7414 u8 syndrome[0x20]; 7415 7416 u8 reserved_1[0x10]; 7417 u8 flow_counter_id[0x10]; 7418 7419 u8 reserved_2[0x20]; 7420 }; 7421 7422 struct mlx5_ifc_alloc_flow_counter_in_bits { 7423 u8 opcode[0x10]; 7424 u8 reserved_0[0x10]; 7425 7426 u8 reserved_1[0x10]; 7427 u8 op_mod[0x10]; 7428 7429 u8 reserved_2[0x40]; 7430 }; 7431 7432 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7433 u8 status[0x8]; 7434 u8 reserved_0[0x18]; 7435 7436 u8 syndrome[0x20]; 7437 7438 u8 reserved_1[0x40]; 7439 }; 7440 7441 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7442 u8 opcode[0x10]; 7443 u8 reserved_0[0x10]; 7444 7445 u8 reserved_1[0x10]; 7446 u8 op_mod[0x10]; 7447 7448 u8 reserved_2[0x20]; 7449 7450 u8 reserved_3[0x10]; 7451 u8 vxlan_udp_port[0x10]; 7452 }; 7453 7454 struct mlx5_ifc_activate_tracer_out_bits { 7455 u8 status[0x8]; 7456 u8 reserved_0[0x18]; 7457 7458 u8 syndrome[0x20]; 7459 7460 u8 reserved_1[0x40]; 7461 }; 7462 7463 struct mlx5_ifc_activate_tracer_in_bits { 7464 u8 opcode[0x10]; 7465 u8 reserved_0[0x10]; 7466 7467 u8 reserved_1[0x10]; 7468 u8 op_mod[0x10]; 7469 7470 u8 mkey[0x20]; 7471 7472 u8 reserved_2[0x20]; 7473 }; 7474 7475 struct mlx5_ifc_set_rate_limit_out_bits { 7476 u8 status[0x8]; 7477 u8 reserved_at_8[0x18]; 7478 7479 u8 syndrome[0x20]; 7480 7481 u8 reserved_at_40[0x40]; 7482 }; 7483 7484 struct mlx5_ifc_set_rate_limit_in_bits { 7485 u8 opcode[0x10]; 7486 u8 reserved_at_10[0x10]; 7487 7488 u8 reserved_at_20[0x10]; 7489 u8 op_mod[0x10]; 7490 7491 u8 reserved_at_40[0x10]; 7492 u8 rate_limit_index[0x10]; 7493 7494 u8 reserved_at_60[0x20]; 7495 7496 u8 rate_limit[0x20]; 7497 u8 burst_upper_bound[0x20]; 7498 }; 7499 7500 struct mlx5_ifc_access_register_out_bits { 7501 u8 status[0x8]; 7502 u8 reserved_0[0x18]; 7503 7504 u8 syndrome[0x20]; 7505 7506 u8 reserved_1[0x40]; 7507 7508 u8 register_data[0][0x20]; 7509 }; 7510 7511 enum { 7512 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7513 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7514 }; 7515 7516 struct mlx5_ifc_access_register_in_bits { 7517 u8 opcode[0x10]; 7518 u8 reserved_0[0x10]; 7519 7520 u8 reserved_1[0x10]; 7521 u8 op_mod[0x10]; 7522 7523 u8 reserved_2[0x10]; 7524 u8 register_id[0x10]; 7525 7526 u8 argument[0x20]; 7527 7528 u8 register_data[0][0x20]; 7529 }; 7530 7531 struct mlx5_ifc_sltp_reg_bits { 7532 u8 status[0x4]; 7533 u8 version[0x4]; 7534 u8 local_port[0x8]; 7535 u8 pnat[0x2]; 7536 u8 reserved_0[0x2]; 7537 u8 lane[0x4]; 7538 u8 reserved_1[0x8]; 7539 7540 u8 reserved_2[0x20]; 7541 7542 u8 reserved_3[0x7]; 7543 u8 polarity[0x1]; 7544 u8 ob_tap0[0x8]; 7545 u8 ob_tap1[0x8]; 7546 u8 ob_tap2[0x8]; 7547 7548 u8 reserved_4[0xc]; 7549 u8 ob_preemp_mode[0x4]; 7550 u8 ob_reg[0x8]; 7551 u8 ob_bias[0x8]; 7552 7553 u8 reserved_5[0x20]; 7554 }; 7555 7556 struct mlx5_ifc_slrp_reg_bits { 7557 u8 status[0x4]; 7558 u8 version[0x4]; 7559 u8 local_port[0x8]; 7560 u8 pnat[0x2]; 7561 u8 reserved_0[0x2]; 7562 u8 lane[0x4]; 7563 u8 reserved_1[0x8]; 7564 7565 u8 ib_sel[0x2]; 7566 u8 reserved_2[0x11]; 7567 u8 dp_sel[0x1]; 7568 u8 dp90sel[0x4]; 7569 u8 mix90phase[0x8]; 7570 7571 u8 ffe_tap0[0x8]; 7572 u8 ffe_tap1[0x8]; 7573 u8 ffe_tap2[0x8]; 7574 u8 ffe_tap3[0x8]; 7575 7576 u8 ffe_tap4[0x8]; 7577 u8 ffe_tap5[0x8]; 7578 u8 ffe_tap6[0x8]; 7579 u8 ffe_tap7[0x8]; 7580 7581 u8 ffe_tap8[0x8]; 7582 u8 mixerbias_tap_amp[0x8]; 7583 u8 reserved_3[0x7]; 7584 u8 ffe_tap_en[0x9]; 7585 7586 u8 ffe_tap_offset0[0x8]; 7587 u8 ffe_tap_offset1[0x8]; 7588 u8 slicer_offset0[0x10]; 7589 7590 u8 mixer_offset0[0x10]; 7591 u8 mixer_offset1[0x10]; 7592 7593 u8 mixerbgn_inp[0x8]; 7594 u8 mixerbgn_inn[0x8]; 7595 u8 mixerbgn_refp[0x8]; 7596 u8 mixerbgn_refn[0x8]; 7597 7598 u8 sel_slicer_lctrl_h[0x1]; 7599 u8 sel_slicer_lctrl_l[0x1]; 7600 u8 reserved_4[0x1]; 7601 u8 ref_mixer_vreg[0x5]; 7602 u8 slicer_gctrl[0x8]; 7603 u8 lctrl_input[0x8]; 7604 u8 mixer_offset_cm1[0x8]; 7605 7606 u8 common_mode[0x6]; 7607 u8 reserved_5[0x1]; 7608 u8 mixer_offset_cm0[0x9]; 7609 u8 reserved_6[0x7]; 7610 u8 slicer_offset_cm[0x9]; 7611 }; 7612 7613 struct mlx5_ifc_slrg_reg_bits { 7614 u8 status[0x4]; 7615 u8 version[0x4]; 7616 u8 local_port[0x8]; 7617 u8 pnat[0x2]; 7618 u8 reserved_0[0x2]; 7619 u8 lane[0x4]; 7620 u8 reserved_1[0x8]; 7621 7622 u8 time_to_link_up[0x10]; 7623 u8 reserved_2[0xc]; 7624 u8 grade_lane_speed[0x4]; 7625 7626 u8 grade_version[0x8]; 7627 u8 grade[0x18]; 7628 7629 u8 reserved_3[0x4]; 7630 u8 height_grade_type[0x4]; 7631 u8 height_grade[0x18]; 7632 7633 u8 height_dz[0x10]; 7634 u8 height_dv[0x10]; 7635 7636 u8 reserved_4[0x10]; 7637 u8 height_sigma[0x10]; 7638 7639 u8 reserved_5[0x20]; 7640 7641 u8 reserved_6[0x4]; 7642 u8 phase_grade_type[0x4]; 7643 u8 phase_grade[0x18]; 7644 7645 u8 reserved_7[0x8]; 7646 u8 phase_eo_pos[0x8]; 7647 u8 reserved_8[0x8]; 7648 u8 phase_eo_neg[0x8]; 7649 7650 u8 ffe_set_tested[0x10]; 7651 u8 test_errors_per_lane[0x10]; 7652 }; 7653 7654 struct mlx5_ifc_pvlc_reg_bits { 7655 u8 reserved_0[0x8]; 7656 u8 local_port[0x8]; 7657 u8 reserved_1[0x10]; 7658 7659 u8 reserved_2[0x1c]; 7660 u8 vl_hw_cap[0x4]; 7661 7662 u8 reserved_3[0x1c]; 7663 u8 vl_admin[0x4]; 7664 7665 u8 reserved_4[0x1c]; 7666 u8 vl_operational[0x4]; 7667 }; 7668 7669 struct mlx5_ifc_pude_reg_bits { 7670 u8 swid[0x8]; 7671 u8 local_port[0x8]; 7672 u8 reserved_0[0x4]; 7673 u8 admin_status[0x4]; 7674 u8 reserved_1[0x4]; 7675 u8 oper_status[0x4]; 7676 7677 u8 reserved_2[0x60]; 7678 }; 7679 7680 enum { 7681 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 7682 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 7683 }; 7684 7685 struct mlx5_ifc_ptys_reg_bits { 7686 u8 reserved_0[0x1]; 7687 u8 an_disable_admin[0x1]; 7688 u8 an_disable_cap[0x1]; 7689 u8 reserved_1[0x4]; 7690 u8 force_tx_aba_param[0x1]; 7691 u8 local_port[0x8]; 7692 u8 reserved_2[0xd]; 7693 u8 proto_mask[0x3]; 7694 7695 u8 an_status[0x4]; 7696 u8 reserved_3[0xc]; 7697 u8 data_rate_oper[0x10]; 7698 7699 u8 fc_proto_capability[0x20]; 7700 7701 u8 eth_proto_capability[0x20]; 7702 7703 u8 ib_link_width_capability[0x10]; 7704 u8 ib_proto_capability[0x10]; 7705 7706 u8 fc_proto_admin[0x20]; 7707 7708 u8 eth_proto_admin[0x20]; 7709 7710 u8 ib_link_width_admin[0x10]; 7711 u8 ib_proto_admin[0x10]; 7712 7713 u8 fc_proto_oper[0x20]; 7714 7715 u8 eth_proto_oper[0x20]; 7716 7717 u8 ib_link_width_oper[0x10]; 7718 u8 ib_proto_oper[0x10]; 7719 7720 u8 reserved_4[0x20]; 7721 7722 u8 eth_proto_lp_advertise[0x20]; 7723 7724 u8 reserved_5[0x60]; 7725 }; 7726 7727 struct mlx5_ifc_ptas_reg_bits { 7728 u8 reserved_0[0x20]; 7729 7730 u8 algorithm_options[0x10]; 7731 u8 reserved_1[0x4]; 7732 u8 repetitions_mode[0x4]; 7733 u8 num_of_repetitions[0x8]; 7734 7735 u8 grade_version[0x8]; 7736 u8 height_grade_type[0x4]; 7737 u8 phase_grade_type[0x4]; 7738 u8 height_grade_weight[0x8]; 7739 u8 phase_grade_weight[0x8]; 7740 7741 u8 gisim_measure_bits[0x10]; 7742 u8 adaptive_tap_measure_bits[0x10]; 7743 7744 u8 ber_bath_high_error_threshold[0x10]; 7745 u8 ber_bath_mid_error_threshold[0x10]; 7746 7747 u8 ber_bath_low_error_threshold[0x10]; 7748 u8 one_ratio_high_threshold[0x10]; 7749 7750 u8 one_ratio_high_mid_threshold[0x10]; 7751 u8 one_ratio_low_mid_threshold[0x10]; 7752 7753 u8 one_ratio_low_threshold[0x10]; 7754 u8 ndeo_error_threshold[0x10]; 7755 7756 u8 mixer_offset_step_size[0x10]; 7757 u8 reserved_2[0x8]; 7758 u8 mix90_phase_for_voltage_bath[0x8]; 7759 7760 u8 mixer_offset_start[0x10]; 7761 u8 mixer_offset_end[0x10]; 7762 7763 u8 reserved_3[0x15]; 7764 u8 ber_test_time[0xb]; 7765 }; 7766 7767 struct mlx5_ifc_pspa_reg_bits { 7768 u8 swid[0x8]; 7769 u8 local_port[0x8]; 7770 u8 sub_port[0x8]; 7771 u8 reserved_0[0x8]; 7772 7773 u8 reserved_1[0x20]; 7774 }; 7775 7776 struct mlx5_ifc_ppsc_reg_bits { 7777 u8 reserved_0[0x8]; 7778 u8 local_port[0x8]; 7779 u8 reserved_1[0x10]; 7780 7781 u8 reserved_2[0x60]; 7782 7783 u8 reserved_3[0x1c]; 7784 u8 wrps_admin[0x4]; 7785 7786 u8 reserved_4[0x1c]; 7787 u8 wrps_status[0x4]; 7788 7789 u8 up_th_vld[0x1]; 7790 u8 down_th_vld[0x1]; 7791 u8 reserved_5[0x6]; 7792 u8 up_threshold[0x8]; 7793 u8 reserved_6[0x8]; 7794 u8 down_threshold[0x8]; 7795 7796 u8 reserved_7[0x20]; 7797 7798 u8 reserved_8[0x1c]; 7799 u8 srps_admin[0x4]; 7800 7801 u8 reserved_9[0x60]; 7802 }; 7803 7804 struct mlx5_ifc_pplr_reg_bits { 7805 u8 reserved_0[0x8]; 7806 u8 local_port[0x8]; 7807 u8 reserved_1[0x10]; 7808 7809 u8 reserved_2[0x8]; 7810 u8 lb_cap[0x8]; 7811 u8 reserved_3[0x8]; 7812 u8 lb_en[0x8]; 7813 }; 7814 7815 struct mlx5_ifc_pplm_reg_bits { 7816 u8 reserved_0[0x8]; 7817 u8 local_port[0x8]; 7818 u8 reserved_1[0x10]; 7819 7820 u8 reserved_2[0x20]; 7821 7822 u8 port_profile_mode[0x8]; 7823 u8 static_port_profile[0x8]; 7824 u8 active_port_profile[0x8]; 7825 u8 reserved_3[0x8]; 7826 7827 u8 retransmission_active[0x8]; 7828 u8 fec_mode_active[0x18]; 7829 7830 u8 reserved_4[0x10]; 7831 u8 v_100g_fec_override_cap[0x4]; 7832 u8 v_50g_fec_override_cap[0x4]; 7833 u8 v_25g_fec_override_cap[0x4]; 7834 u8 v_10g_40g_fec_override_cap[0x4]; 7835 7836 u8 reserved_5[0x10]; 7837 u8 v_100g_fec_override_admin[0x4]; 7838 u8 v_50g_fec_override_admin[0x4]; 7839 u8 v_25g_fec_override_admin[0x4]; 7840 u8 v_10g_40g_fec_override_admin[0x4]; 7841 }; 7842 7843 struct mlx5_ifc_ppll_reg_bits { 7844 u8 num_pll_groups[0x8]; 7845 u8 pll_group[0x8]; 7846 u8 reserved_0[0x4]; 7847 u8 num_plls[0x4]; 7848 u8 reserved_1[0x8]; 7849 7850 u8 reserved_2[0x1f]; 7851 u8 ae[0x1]; 7852 7853 u8 pll_status[4][0x40]; 7854 }; 7855 7856 struct mlx5_ifc_ppad_reg_bits { 7857 u8 reserved_0[0x3]; 7858 u8 single_mac[0x1]; 7859 u8 reserved_1[0x4]; 7860 u8 local_port[0x8]; 7861 u8 mac_47_32[0x10]; 7862 7863 u8 mac_31_0[0x20]; 7864 7865 u8 reserved_2[0x40]; 7866 }; 7867 7868 struct mlx5_ifc_pmtu_reg_bits { 7869 u8 reserved_0[0x8]; 7870 u8 local_port[0x8]; 7871 u8 reserved_1[0x10]; 7872 7873 u8 max_mtu[0x10]; 7874 u8 reserved_2[0x10]; 7875 7876 u8 admin_mtu[0x10]; 7877 u8 reserved_3[0x10]; 7878 7879 u8 oper_mtu[0x10]; 7880 u8 reserved_4[0x10]; 7881 }; 7882 7883 struct mlx5_ifc_pmpr_reg_bits { 7884 u8 reserved_0[0x8]; 7885 u8 module[0x8]; 7886 u8 reserved_1[0x10]; 7887 7888 u8 reserved_2[0x18]; 7889 u8 attenuation_5g[0x8]; 7890 7891 u8 reserved_3[0x18]; 7892 u8 attenuation_7g[0x8]; 7893 7894 u8 reserved_4[0x18]; 7895 u8 attenuation_12g[0x8]; 7896 }; 7897 7898 struct mlx5_ifc_pmpe_reg_bits { 7899 u8 reserved_0[0x8]; 7900 u8 module[0x8]; 7901 u8 reserved_1[0xc]; 7902 u8 module_status[0x4]; 7903 7904 u8 reserved_2[0x14]; 7905 u8 error_type[0x4]; 7906 u8 reserved_3[0x8]; 7907 7908 u8 reserved_4[0x40]; 7909 }; 7910 7911 struct mlx5_ifc_pmpc_reg_bits { 7912 u8 module_state_updated[32][0x8]; 7913 }; 7914 7915 struct mlx5_ifc_pmlpn_reg_bits { 7916 u8 reserved_0[0x4]; 7917 u8 mlpn_status[0x4]; 7918 u8 local_port[0x8]; 7919 u8 reserved_1[0x10]; 7920 7921 u8 e[0x1]; 7922 u8 reserved_2[0x1f]; 7923 }; 7924 7925 struct mlx5_ifc_pmlp_reg_bits { 7926 u8 rxtx[0x1]; 7927 u8 reserved_0[0x7]; 7928 u8 local_port[0x8]; 7929 u8 reserved_1[0x8]; 7930 u8 width[0x8]; 7931 7932 u8 lane0_module_mapping[0x20]; 7933 7934 u8 lane1_module_mapping[0x20]; 7935 7936 u8 lane2_module_mapping[0x20]; 7937 7938 u8 lane3_module_mapping[0x20]; 7939 7940 u8 reserved_2[0x160]; 7941 }; 7942 7943 struct mlx5_ifc_pmaos_reg_bits { 7944 u8 reserved_0[0x8]; 7945 u8 module[0x8]; 7946 u8 reserved_1[0x4]; 7947 u8 admin_status[0x4]; 7948 u8 reserved_2[0x4]; 7949 u8 oper_status[0x4]; 7950 7951 u8 ase[0x1]; 7952 u8 ee[0x1]; 7953 u8 reserved_3[0x12]; 7954 u8 error_type[0x4]; 7955 u8 reserved_4[0x6]; 7956 u8 e[0x2]; 7957 7958 u8 reserved_5[0x40]; 7959 }; 7960 7961 struct mlx5_ifc_plpc_reg_bits { 7962 u8 reserved_0[0x4]; 7963 u8 profile_id[0xc]; 7964 u8 reserved_1[0x4]; 7965 u8 proto_mask[0x4]; 7966 u8 reserved_2[0x8]; 7967 7968 u8 reserved_3[0x10]; 7969 u8 lane_speed[0x10]; 7970 7971 u8 reserved_4[0x17]; 7972 u8 lpbf[0x1]; 7973 u8 fec_mode_policy[0x8]; 7974 7975 u8 retransmission_capability[0x8]; 7976 u8 fec_mode_capability[0x18]; 7977 7978 u8 retransmission_support_admin[0x8]; 7979 u8 fec_mode_support_admin[0x18]; 7980 7981 u8 retransmission_request_admin[0x8]; 7982 u8 fec_mode_request_admin[0x18]; 7983 7984 u8 reserved_5[0x80]; 7985 }; 7986 7987 struct mlx5_ifc_pll_status_data_bits { 7988 u8 reserved_0[0x1]; 7989 u8 lock_cal[0x1]; 7990 u8 lock_status[0x2]; 7991 u8 reserved_1[0x2]; 7992 u8 algo_f_ctrl[0xa]; 7993 u8 analog_algo_num_var[0x6]; 7994 u8 f_ctrl_measure[0xa]; 7995 7996 u8 reserved_2[0x2]; 7997 u8 analog_var[0x6]; 7998 u8 reserved_3[0x2]; 7999 u8 high_var[0x6]; 8000 u8 reserved_4[0x2]; 8001 u8 low_var[0x6]; 8002 u8 reserved_5[0x2]; 8003 u8 mid_val[0x6]; 8004 }; 8005 8006 struct mlx5_ifc_plib_reg_bits { 8007 u8 reserved_0[0x8]; 8008 u8 local_port[0x8]; 8009 u8 reserved_1[0x8]; 8010 u8 ib_port[0x8]; 8011 8012 u8 reserved_2[0x60]; 8013 }; 8014 8015 struct mlx5_ifc_plbf_reg_bits { 8016 u8 reserved_0[0x8]; 8017 u8 local_port[0x8]; 8018 u8 reserved_1[0xd]; 8019 u8 lbf_mode[0x3]; 8020 8021 u8 reserved_2[0x20]; 8022 }; 8023 8024 struct mlx5_ifc_pipg_reg_bits { 8025 u8 reserved_0[0x8]; 8026 u8 local_port[0x8]; 8027 u8 reserved_1[0x10]; 8028 8029 u8 dic[0x1]; 8030 u8 reserved_2[0x19]; 8031 u8 ipg[0x4]; 8032 u8 reserved_3[0x2]; 8033 }; 8034 8035 struct mlx5_ifc_pifr_reg_bits { 8036 u8 reserved_0[0x8]; 8037 u8 local_port[0x8]; 8038 u8 reserved_1[0x10]; 8039 8040 u8 reserved_2[0xe0]; 8041 8042 u8 port_filter[8][0x20]; 8043 8044 u8 port_filter_update_en[8][0x20]; 8045 }; 8046 8047 struct mlx5_ifc_phys_layer_cntrs_bits { 8048 u8 time_since_last_clear_high[0x20]; 8049 8050 u8 time_since_last_clear_low[0x20]; 8051 8052 u8 symbol_errors_high[0x20]; 8053 8054 u8 symbol_errors_low[0x20]; 8055 8056 u8 sync_headers_errors_high[0x20]; 8057 8058 u8 sync_headers_errors_low[0x20]; 8059 8060 u8 edpl_bip_errors_lane0_high[0x20]; 8061 8062 u8 edpl_bip_errors_lane0_low[0x20]; 8063 8064 u8 edpl_bip_errors_lane1_high[0x20]; 8065 8066 u8 edpl_bip_errors_lane1_low[0x20]; 8067 8068 u8 edpl_bip_errors_lane2_high[0x20]; 8069 8070 u8 edpl_bip_errors_lane2_low[0x20]; 8071 8072 u8 edpl_bip_errors_lane3_high[0x20]; 8073 8074 u8 edpl_bip_errors_lane3_low[0x20]; 8075 8076 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 8077 8078 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 8079 8080 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 8081 8082 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 8083 8084 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 8085 8086 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 8087 8088 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 8089 8090 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 8091 8092 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 8093 8094 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 8095 8096 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 8097 8098 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 8099 8100 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 8101 8102 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 8103 8104 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 8105 8106 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 8107 8108 u8 rs_fec_corrected_blocks_high[0x20]; 8109 8110 u8 rs_fec_corrected_blocks_low[0x20]; 8111 8112 u8 rs_fec_uncorrectable_blocks_high[0x20]; 8113 8114 u8 rs_fec_uncorrectable_blocks_low[0x20]; 8115 8116 u8 rs_fec_no_errors_blocks_high[0x20]; 8117 8118 u8 rs_fec_no_errors_blocks_low[0x20]; 8119 8120 u8 rs_fec_single_error_blocks_high[0x20]; 8121 8122 u8 rs_fec_single_error_blocks_low[0x20]; 8123 8124 u8 rs_fec_corrected_symbols_total_high[0x20]; 8125 8126 u8 rs_fec_corrected_symbols_total_low[0x20]; 8127 8128 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 8129 8130 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 8131 8132 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 8133 8134 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 8135 8136 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 8137 8138 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 8139 8140 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 8141 8142 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 8143 8144 u8 link_down_events[0x20]; 8145 8146 u8 successful_recovery_events[0x20]; 8147 8148 u8 reserved_0[0x180]; 8149 }; 8150 8151 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 8152 u8 symbol_error_counter[0x10]; 8153 8154 u8 link_error_recovery_counter[0x8]; 8155 8156 u8 link_downed_counter[0x8]; 8157 8158 u8 port_rcv_errors[0x10]; 8159 8160 u8 port_rcv_remote_physical_errors[0x10]; 8161 8162 u8 port_rcv_switch_relay_errors[0x10]; 8163 8164 u8 port_xmit_discards[0x10]; 8165 8166 u8 port_xmit_constraint_errors[0x8]; 8167 8168 u8 port_rcv_constraint_errors[0x8]; 8169 8170 u8 reserved_at_70[0x8]; 8171 8172 u8 link_overrun_errors[0x8]; 8173 8174 u8 reserved_at_80[0x10]; 8175 8176 u8 vl_15_dropped[0x10]; 8177 8178 u8 reserved_at_a0[0xa0]; 8179 }; 8180 8181 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 8182 u8 time_since_last_clear_high[0x20]; 8183 8184 u8 time_since_last_clear_low[0x20]; 8185 8186 u8 phy_received_bits_high[0x20]; 8187 8188 u8 phy_received_bits_low[0x20]; 8189 8190 u8 phy_symbol_errors_high[0x20]; 8191 8192 u8 phy_symbol_errors_low[0x20]; 8193 8194 u8 phy_corrected_bits_high[0x20]; 8195 8196 u8 phy_corrected_bits_low[0x20]; 8197 8198 u8 phy_corrected_bits_lane0_high[0x20]; 8199 8200 u8 phy_corrected_bits_lane0_low[0x20]; 8201 8202 u8 phy_corrected_bits_lane1_high[0x20]; 8203 8204 u8 phy_corrected_bits_lane1_low[0x20]; 8205 8206 u8 phy_corrected_bits_lane2_high[0x20]; 8207 8208 u8 phy_corrected_bits_lane2_low[0x20]; 8209 8210 u8 phy_corrected_bits_lane3_high[0x20]; 8211 8212 u8 phy_corrected_bits_lane3_low[0x20]; 8213 8214 u8 reserved_at_200[0x5c0]; 8215 }; 8216 8217 struct mlx5_ifc_infiniband_port_cntrs_bits { 8218 u8 symbol_error_counter[0x10]; 8219 u8 link_error_recovery_counter[0x8]; 8220 u8 link_downed_counter[0x8]; 8221 8222 u8 port_rcv_errors[0x10]; 8223 u8 port_rcv_remote_physical_errors[0x10]; 8224 8225 u8 port_rcv_switch_relay_errors[0x10]; 8226 u8 port_xmit_discards[0x10]; 8227 8228 u8 port_xmit_constraint_errors[0x8]; 8229 u8 port_rcv_constraint_errors[0x8]; 8230 u8 reserved_0[0x8]; 8231 u8 local_link_integrity_errors[0x4]; 8232 u8 excessive_buffer_overrun_errors[0x4]; 8233 8234 u8 reserved_1[0x10]; 8235 u8 vl_15_dropped[0x10]; 8236 8237 u8 port_xmit_data[0x20]; 8238 8239 u8 port_rcv_data[0x20]; 8240 8241 u8 port_xmit_pkts[0x20]; 8242 8243 u8 port_rcv_pkts[0x20]; 8244 8245 u8 port_xmit_wait[0x20]; 8246 8247 u8 reserved_2[0x680]; 8248 }; 8249 8250 struct mlx5_ifc_phrr_reg_bits { 8251 u8 clr[0x1]; 8252 u8 reserved_0[0x7]; 8253 u8 local_port[0x8]; 8254 u8 reserved_1[0x10]; 8255 8256 u8 hist_group[0x8]; 8257 u8 reserved_2[0x10]; 8258 u8 hist_id[0x8]; 8259 8260 u8 reserved_3[0x40]; 8261 8262 u8 time_since_last_clear_high[0x20]; 8263 8264 u8 time_since_last_clear_low[0x20]; 8265 8266 u8 bin[10][0x20]; 8267 }; 8268 8269 struct mlx5_ifc_phbr_for_prio_reg_bits { 8270 u8 reserved_0[0x18]; 8271 u8 prio[0x8]; 8272 }; 8273 8274 struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8275 u8 reserved_0[0x18]; 8276 u8 tclass[0x8]; 8277 }; 8278 8279 struct mlx5_ifc_phbr_binding_reg_bits { 8280 u8 opcode[0x4]; 8281 u8 reserved_0[0x4]; 8282 u8 local_port[0x8]; 8283 u8 pnat[0x2]; 8284 u8 reserved_1[0xe]; 8285 8286 u8 hist_group[0x8]; 8287 u8 reserved_2[0x10]; 8288 u8 hist_id[0x8]; 8289 8290 u8 reserved_3[0x10]; 8291 u8 hist_type[0x10]; 8292 8293 u8 hist_parameters[0x20]; 8294 8295 u8 hist_min_value[0x20]; 8296 8297 u8 hist_max_value[0x20]; 8298 8299 u8 sample_time[0x20]; 8300 }; 8301 8302 enum { 8303 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 8304 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 8305 }; 8306 8307 struct mlx5_ifc_pfcc_reg_bits { 8308 u8 dcbx_operation_type[0x2]; 8309 u8 cap_local_admin[0x1]; 8310 u8 cap_remote_admin[0x1]; 8311 u8 reserved_0[0x4]; 8312 u8 local_port[0x8]; 8313 u8 pnat[0x2]; 8314 u8 reserved_1[0xc]; 8315 u8 shl_cap[0x1]; 8316 u8 shl_opr[0x1]; 8317 8318 u8 ppan[0x4]; 8319 u8 reserved_2[0x4]; 8320 u8 prio_mask_tx[0x8]; 8321 u8 reserved_3[0x8]; 8322 u8 prio_mask_rx[0x8]; 8323 8324 u8 pptx[0x1]; 8325 u8 aptx[0x1]; 8326 u8 reserved_4[0x6]; 8327 u8 pfctx[0x8]; 8328 u8 reserved_5[0x8]; 8329 u8 cbftx[0x8]; 8330 8331 u8 pprx[0x1]; 8332 u8 aprx[0x1]; 8333 u8 reserved_6[0x6]; 8334 u8 pfcrx[0x8]; 8335 u8 reserved_7[0x8]; 8336 u8 cbfrx[0x8]; 8337 8338 u8 device_stall_minor_watermark[0x10]; 8339 u8 device_stall_critical_watermark[0x10]; 8340 8341 u8 reserved_8[0x60]; 8342 }; 8343 8344 struct mlx5_ifc_pelc_reg_bits { 8345 u8 op[0x4]; 8346 u8 reserved_0[0x4]; 8347 u8 local_port[0x8]; 8348 u8 reserved_1[0x10]; 8349 8350 u8 op_admin[0x8]; 8351 u8 op_capability[0x8]; 8352 u8 op_request[0x8]; 8353 u8 op_active[0x8]; 8354 8355 u8 admin[0x40]; 8356 8357 u8 capability[0x40]; 8358 8359 u8 request[0x40]; 8360 8361 u8 active[0x40]; 8362 8363 u8 reserved_2[0x80]; 8364 }; 8365 8366 struct mlx5_ifc_peir_reg_bits { 8367 u8 reserved_0[0x8]; 8368 u8 local_port[0x8]; 8369 u8 reserved_1[0x10]; 8370 8371 u8 reserved_2[0xc]; 8372 u8 error_count[0x4]; 8373 u8 reserved_3[0x10]; 8374 8375 u8 reserved_4[0xc]; 8376 u8 lane[0x4]; 8377 u8 reserved_5[0x8]; 8378 u8 error_type[0x8]; 8379 }; 8380 8381 struct mlx5_ifc_pcap_reg_bits { 8382 u8 reserved_0[0x8]; 8383 u8 local_port[0x8]; 8384 u8 reserved_1[0x10]; 8385 8386 u8 port_capability_mask[4][0x20]; 8387 }; 8388 8389 struct mlx5_ifc_pbmc_reg_bits { 8390 u8 reserved_0[0x8]; 8391 u8 local_port[0x8]; 8392 u8 reserved_1[0x10]; 8393 8394 u8 xoff_timer_value[0x10]; 8395 u8 xoff_refresh[0x10]; 8396 8397 u8 reserved_2[0x10]; 8398 u8 port_buffer_size[0x10]; 8399 8400 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8401 8402 u8 reserved_3[0x40]; 8403 8404 u8 port_shared_buffer[0x40]; 8405 }; 8406 8407 struct mlx5_ifc_paos_reg_bits { 8408 u8 swid[0x8]; 8409 u8 local_port[0x8]; 8410 u8 reserved_0[0x4]; 8411 u8 admin_status[0x4]; 8412 u8 reserved_1[0x4]; 8413 u8 oper_status[0x4]; 8414 8415 u8 ase[0x1]; 8416 u8 ee[0x1]; 8417 u8 reserved_2[0x1c]; 8418 u8 e[0x2]; 8419 8420 u8 reserved_3[0x40]; 8421 }; 8422 8423 struct mlx5_ifc_pamp_reg_bits { 8424 u8 reserved_0[0x8]; 8425 u8 opamp_group[0x8]; 8426 u8 reserved_1[0xc]; 8427 u8 opamp_group_type[0x4]; 8428 8429 u8 start_index[0x10]; 8430 u8 reserved_2[0x4]; 8431 u8 num_of_indices[0xc]; 8432 8433 u8 index_data[18][0x10]; 8434 }; 8435 8436 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 8437 u8 llr_rx_cells_high[0x20]; 8438 8439 u8 llr_rx_cells_low[0x20]; 8440 8441 u8 llr_rx_error_high[0x20]; 8442 8443 u8 llr_rx_error_low[0x20]; 8444 8445 u8 llr_rx_crc_error_high[0x20]; 8446 8447 u8 llr_rx_crc_error_low[0x20]; 8448 8449 u8 llr_tx_cells_high[0x20]; 8450 8451 u8 llr_tx_cells_low[0x20]; 8452 8453 u8 llr_tx_ret_cells_high[0x20]; 8454 8455 u8 llr_tx_ret_cells_low[0x20]; 8456 8457 u8 llr_tx_ret_events_high[0x20]; 8458 8459 u8 llr_tx_ret_events_low[0x20]; 8460 8461 u8 reserved_0[0x640]; 8462 }; 8463 8464 struct mlx5_ifc_lane_2_module_mapping_bits { 8465 u8 reserved_0[0x6]; 8466 u8 rx_lane[0x2]; 8467 u8 reserved_1[0x6]; 8468 u8 tx_lane[0x2]; 8469 u8 reserved_2[0x8]; 8470 u8 module[0x8]; 8471 }; 8472 8473 struct mlx5_ifc_eth_per_traffic_class_layout_bits { 8474 u8 transmit_queue_high[0x20]; 8475 8476 u8 transmit_queue_low[0x20]; 8477 8478 u8 reserved_0[0x780]; 8479 }; 8480 8481 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 8482 u8 no_buffer_discard_uc_high[0x20]; 8483 8484 u8 no_buffer_discard_uc_low[0x20]; 8485 8486 u8 wred_discard_high[0x20]; 8487 8488 u8 wred_discard_low[0x20]; 8489 8490 u8 reserved_0[0x740]; 8491 }; 8492 8493 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 8494 u8 rx_octets_high[0x20]; 8495 8496 u8 rx_octets_low[0x20]; 8497 8498 u8 reserved_0[0xc0]; 8499 8500 u8 rx_frames_high[0x20]; 8501 8502 u8 rx_frames_low[0x20]; 8503 8504 u8 tx_octets_high[0x20]; 8505 8506 u8 tx_octets_low[0x20]; 8507 8508 u8 reserved_1[0xc0]; 8509 8510 u8 tx_frames_high[0x20]; 8511 8512 u8 tx_frames_low[0x20]; 8513 8514 u8 rx_pause_high[0x20]; 8515 8516 u8 rx_pause_low[0x20]; 8517 8518 u8 rx_pause_duration_high[0x20]; 8519 8520 u8 rx_pause_duration_low[0x20]; 8521 8522 u8 tx_pause_high[0x20]; 8523 8524 u8 tx_pause_low[0x20]; 8525 8526 u8 tx_pause_duration_high[0x20]; 8527 8528 u8 tx_pause_duration_low[0x20]; 8529 8530 u8 rx_pause_transition_high[0x20]; 8531 8532 u8 rx_pause_transition_low[0x20]; 8533 8534 u8 rx_discards_high[0x20]; 8535 8536 u8 rx_discards_low[0x20]; 8537 8538 u8 device_stall_minor_watermark_cnt_high[0x20]; 8539 8540 u8 device_stall_minor_watermark_cnt_low[0x20]; 8541 8542 u8 device_stall_critical_watermark_cnt_high[0x20]; 8543 8544 u8 device_stall_critical_watermark_cnt_low[0x20]; 8545 8546 u8 reserved_2[0x340]; 8547 }; 8548 8549 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 8550 u8 port_transmit_wait_high[0x20]; 8551 8552 u8 port_transmit_wait_low[0x20]; 8553 8554 u8 ecn_marked_high[0x20]; 8555 8556 u8 ecn_marked_low[0x20]; 8557 8558 u8 no_buffer_discard_mc_high[0x20]; 8559 8560 u8 no_buffer_discard_mc_low[0x20]; 8561 8562 u8 reserved_0[0x700]; 8563 }; 8564 8565 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 8566 u8 a_frames_transmitted_ok_high[0x20]; 8567 8568 u8 a_frames_transmitted_ok_low[0x20]; 8569 8570 u8 a_frames_received_ok_high[0x20]; 8571 8572 u8 a_frames_received_ok_low[0x20]; 8573 8574 u8 a_frame_check_sequence_errors_high[0x20]; 8575 8576 u8 a_frame_check_sequence_errors_low[0x20]; 8577 8578 u8 a_alignment_errors_high[0x20]; 8579 8580 u8 a_alignment_errors_low[0x20]; 8581 8582 u8 a_octets_transmitted_ok_high[0x20]; 8583 8584 u8 a_octets_transmitted_ok_low[0x20]; 8585 8586 u8 a_octets_received_ok_high[0x20]; 8587 8588 u8 a_octets_received_ok_low[0x20]; 8589 8590 u8 a_multicast_frames_xmitted_ok_high[0x20]; 8591 8592 u8 a_multicast_frames_xmitted_ok_low[0x20]; 8593 8594 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 8595 8596 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 8597 8598 u8 a_multicast_frames_received_ok_high[0x20]; 8599 8600 u8 a_multicast_frames_received_ok_low[0x20]; 8601 8602 u8 a_broadcast_frames_recieved_ok_high[0x20]; 8603 8604 u8 a_broadcast_frames_recieved_ok_low[0x20]; 8605 8606 u8 a_in_range_length_errors_high[0x20]; 8607 8608 u8 a_in_range_length_errors_low[0x20]; 8609 8610 u8 a_out_of_range_length_field_high[0x20]; 8611 8612 u8 a_out_of_range_length_field_low[0x20]; 8613 8614 u8 a_frame_too_long_errors_high[0x20]; 8615 8616 u8 a_frame_too_long_errors_low[0x20]; 8617 8618 u8 a_symbol_error_during_carrier_high[0x20]; 8619 8620 u8 a_symbol_error_during_carrier_low[0x20]; 8621 8622 u8 a_mac_control_frames_transmitted_high[0x20]; 8623 8624 u8 a_mac_control_frames_transmitted_low[0x20]; 8625 8626 u8 a_mac_control_frames_received_high[0x20]; 8627 8628 u8 a_mac_control_frames_received_low[0x20]; 8629 8630 u8 a_unsupported_opcodes_received_high[0x20]; 8631 8632 u8 a_unsupported_opcodes_received_low[0x20]; 8633 8634 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 8635 8636 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 8637 8638 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 8639 8640 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 8641 8642 u8 reserved_0[0x300]; 8643 }; 8644 8645 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 8646 u8 dot3stats_alignment_errors_high[0x20]; 8647 8648 u8 dot3stats_alignment_errors_low[0x20]; 8649 8650 u8 dot3stats_fcs_errors_high[0x20]; 8651 8652 u8 dot3stats_fcs_errors_low[0x20]; 8653 8654 u8 dot3stats_single_collision_frames_high[0x20]; 8655 8656 u8 dot3stats_single_collision_frames_low[0x20]; 8657 8658 u8 dot3stats_multiple_collision_frames_high[0x20]; 8659 8660 u8 dot3stats_multiple_collision_frames_low[0x20]; 8661 8662 u8 dot3stats_sqe_test_errors_high[0x20]; 8663 8664 u8 dot3stats_sqe_test_errors_low[0x20]; 8665 8666 u8 dot3stats_deferred_transmissions_high[0x20]; 8667 8668 u8 dot3stats_deferred_transmissions_low[0x20]; 8669 8670 u8 dot3stats_late_collisions_high[0x20]; 8671 8672 u8 dot3stats_late_collisions_low[0x20]; 8673 8674 u8 dot3stats_excessive_collisions_high[0x20]; 8675 8676 u8 dot3stats_excessive_collisions_low[0x20]; 8677 8678 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 8679 8680 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 8681 8682 u8 dot3stats_carrier_sense_errors_high[0x20]; 8683 8684 u8 dot3stats_carrier_sense_errors_low[0x20]; 8685 8686 u8 dot3stats_frame_too_longs_high[0x20]; 8687 8688 u8 dot3stats_frame_too_longs_low[0x20]; 8689 8690 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 8691 8692 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 8693 8694 u8 dot3stats_symbol_errors_high[0x20]; 8695 8696 u8 dot3stats_symbol_errors_low[0x20]; 8697 8698 u8 dot3control_in_unknown_opcodes_high[0x20]; 8699 8700 u8 dot3control_in_unknown_opcodes_low[0x20]; 8701 8702 u8 dot3in_pause_frames_high[0x20]; 8703 8704 u8 dot3in_pause_frames_low[0x20]; 8705 8706 u8 dot3out_pause_frames_high[0x20]; 8707 8708 u8 dot3out_pause_frames_low[0x20]; 8709 8710 u8 reserved_0[0x3c0]; 8711 }; 8712 8713 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 8714 u8 if_in_octets_high[0x20]; 8715 8716 u8 if_in_octets_low[0x20]; 8717 8718 u8 if_in_ucast_pkts_high[0x20]; 8719 8720 u8 if_in_ucast_pkts_low[0x20]; 8721 8722 u8 if_in_discards_high[0x20]; 8723 8724 u8 if_in_discards_low[0x20]; 8725 8726 u8 if_in_errors_high[0x20]; 8727 8728 u8 if_in_errors_low[0x20]; 8729 8730 u8 if_in_unknown_protos_high[0x20]; 8731 8732 u8 if_in_unknown_protos_low[0x20]; 8733 8734 u8 if_out_octets_high[0x20]; 8735 8736 u8 if_out_octets_low[0x20]; 8737 8738 u8 if_out_ucast_pkts_high[0x20]; 8739 8740 u8 if_out_ucast_pkts_low[0x20]; 8741 8742 u8 if_out_discards_high[0x20]; 8743 8744 u8 if_out_discards_low[0x20]; 8745 8746 u8 if_out_errors_high[0x20]; 8747 8748 u8 if_out_errors_low[0x20]; 8749 8750 u8 if_in_multicast_pkts_high[0x20]; 8751 8752 u8 if_in_multicast_pkts_low[0x20]; 8753 8754 u8 if_in_broadcast_pkts_high[0x20]; 8755 8756 u8 if_in_broadcast_pkts_low[0x20]; 8757 8758 u8 if_out_multicast_pkts_high[0x20]; 8759 8760 u8 if_out_multicast_pkts_low[0x20]; 8761 8762 u8 if_out_broadcast_pkts_high[0x20]; 8763 8764 u8 if_out_broadcast_pkts_low[0x20]; 8765 8766 u8 reserved_0[0x480]; 8767 }; 8768 8769 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 8770 u8 ether_stats_drop_events_high[0x20]; 8771 8772 u8 ether_stats_drop_events_low[0x20]; 8773 8774 u8 ether_stats_octets_high[0x20]; 8775 8776 u8 ether_stats_octets_low[0x20]; 8777 8778 u8 ether_stats_pkts_high[0x20]; 8779 8780 u8 ether_stats_pkts_low[0x20]; 8781 8782 u8 ether_stats_broadcast_pkts_high[0x20]; 8783 8784 u8 ether_stats_broadcast_pkts_low[0x20]; 8785 8786 u8 ether_stats_multicast_pkts_high[0x20]; 8787 8788 u8 ether_stats_multicast_pkts_low[0x20]; 8789 8790 u8 ether_stats_crc_align_errors_high[0x20]; 8791 8792 u8 ether_stats_crc_align_errors_low[0x20]; 8793 8794 u8 ether_stats_undersize_pkts_high[0x20]; 8795 8796 u8 ether_stats_undersize_pkts_low[0x20]; 8797 8798 u8 ether_stats_oversize_pkts_high[0x20]; 8799 8800 u8 ether_stats_oversize_pkts_low[0x20]; 8801 8802 u8 ether_stats_fragments_high[0x20]; 8803 8804 u8 ether_stats_fragments_low[0x20]; 8805 8806 u8 ether_stats_jabbers_high[0x20]; 8807 8808 u8 ether_stats_jabbers_low[0x20]; 8809 8810 u8 ether_stats_collisions_high[0x20]; 8811 8812 u8 ether_stats_collisions_low[0x20]; 8813 8814 u8 ether_stats_pkts64octets_high[0x20]; 8815 8816 u8 ether_stats_pkts64octets_low[0x20]; 8817 8818 u8 ether_stats_pkts65to127octets_high[0x20]; 8819 8820 u8 ether_stats_pkts65to127octets_low[0x20]; 8821 8822 u8 ether_stats_pkts128to255octets_high[0x20]; 8823 8824 u8 ether_stats_pkts128to255octets_low[0x20]; 8825 8826 u8 ether_stats_pkts256to511octets_high[0x20]; 8827 8828 u8 ether_stats_pkts256to511octets_low[0x20]; 8829 8830 u8 ether_stats_pkts512to1023octets_high[0x20]; 8831 8832 u8 ether_stats_pkts512to1023octets_low[0x20]; 8833 8834 u8 ether_stats_pkts1024to1518octets_high[0x20]; 8835 8836 u8 ether_stats_pkts1024to1518octets_low[0x20]; 8837 8838 u8 ether_stats_pkts1519to2047octets_high[0x20]; 8839 8840 u8 ether_stats_pkts1519to2047octets_low[0x20]; 8841 8842 u8 ether_stats_pkts2048to4095octets_high[0x20]; 8843 8844 u8 ether_stats_pkts2048to4095octets_low[0x20]; 8845 8846 u8 ether_stats_pkts4096to8191octets_high[0x20]; 8847 8848 u8 ether_stats_pkts4096to8191octets_low[0x20]; 8849 8850 u8 ether_stats_pkts8192to10239octets_high[0x20]; 8851 8852 u8 ether_stats_pkts8192to10239octets_low[0x20]; 8853 8854 u8 reserved_0[0x280]; 8855 }; 8856 8857 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 8858 u8 symbol_error_counter[0x10]; 8859 u8 link_error_recovery_counter[0x8]; 8860 u8 link_downed_counter[0x8]; 8861 8862 u8 port_rcv_errors[0x10]; 8863 u8 port_rcv_remote_physical_errors[0x10]; 8864 8865 u8 port_rcv_switch_relay_errors[0x10]; 8866 u8 port_xmit_discards[0x10]; 8867 8868 u8 port_xmit_constraint_errors[0x8]; 8869 u8 port_rcv_constraint_errors[0x8]; 8870 u8 reserved_0[0x8]; 8871 u8 local_link_integrity_errors[0x4]; 8872 u8 excessive_buffer_overrun_errors[0x4]; 8873 8874 u8 reserved_1[0x10]; 8875 u8 vl_15_dropped[0x10]; 8876 8877 u8 port_xmit_data[0x20]; 8878 8879 u8 port_rcv_data[0x20]; 8880 8881 u8 port_xmit_pkts[0x20]; 8882 8883 u8 port_rcv_pkts[0x20]; 8884 8885 u8 port_xmit_wait[0x20]; 8886 8887 u8 reserved_2[0x680]; 8888 }; 8889 8890 struct mlx5_ifc_trc_tlb_reg_bits { 8891 u8 reserved_0[0x80]; 8892 8893 u8 tlb_addr[0][0x40]; 8894 }; 8895 8896 struct mlx5_ifc_trc_read_fifo_reg_bits { 8897 u8 reserved_0[0x10]; 8898 u8 requested_event_num[0x10]; 8899 8900 u8 reserved_1[0x20]; 8901 8902 u8 reserved_2[0x10]; 8903 u8 acual_event_num[0x10]; 8904 8905 u8 reserved_3[0x20]; 8906 8907 u8 event[0][0x40]; 8908 }; 8909 8910 struct mlx5_ifc_trc_lock_reg_bits { 8911 u8 reserved_0[0x1f]; 8912 u8 lock[0x1]; 8913 8914 u8 reserved_1[0x60]; 8915 }; 8916 8917 struct mlx5_ifc_trc_filter_reg_bits { 8918 u8 status[0x1]; 8919 u8 reserved_0[0xf]; 8920 u8 filter_index[0x10]; 8921 8922 u8 reserved_1[0x20]; 8923 8924 u8 filter_val[0x20]; 8925 8926 u8 reserved_2[0x1a0]; 8927 }; 8928 8929 struct mlx5_ifc_trc_event_reg_bits { 8930 u8 status[0x1]; 8931 u8 reserved_0[0xf]; 8932 u8 event_index[0x10]; 8933 8934 u8 reserved_1[0x20]; 8935 8936 u8 event_id[0x20]; 8937 8938 u8 event_selector_val[0x10]; 8939 u8 event_selector_size[0x10]; 8940 8941 u8 reserved_2[0x180]; 8942 }; 8943 8944 struct mlx5_ifc_trc_conf_reg_bits { 8945 u8 limit_en[0x1]; 8946 u8 reserved_0[0x3]; 8947 u8 dump_mode[0x4]; 8948 u8 reserved_1[0x15]; 8949 u8 state[0x3]; 8950 8951 u8 reserved_2[0x20]; 8952 8953 u8 limit_event_index[0x20]; 8954 8955 u8 mkey[0x20]; 8956 8957 u8 fifo_ready_ev_num[0x20]; 8958 8959 u8 reserved_3[0x160]; 8960 }; 8961 8962 struct mlx5_ifc_trc_cap_reg_bits { 8963 u8 reserved_0[0x18]; 8964 u8 dump_mode[0x8]; 8965 8966 u8 reserved_1[0x20]; 8967 8968 u8 num_of_events[0x10]; 8969 u8 num_of_filters[0x10]; 8970 8971 u8 fifo_size[0x20]; 8972 8973 u8 tlb_size[0x10]; 8974 u8 event_size[0x10]; 8975 8976 u8 reserved_2[0x160]; 8977 }; 8978 8979 struct mlx5_ifc_set_node_in_bits { 8980 u8 node_description[64][0x8]; 8981 }; 8982 8983 struct mlx5_ifc_register_power_settings_bits { 8984 u8 reserved_0[0x18]; 8985 u8 power_settings_level[0x8]; 8986 8987 u8 reserved_1[0x60]; 8988 }; 8989 8990 struct mlx5_ifc_register_host_endianess_bits { 8991 u8 he[0x1]; 8992 u8 reserved_0[0x1f]; 8993 8994 u8 reserved_1[0x60]; 8995 }; 8996 8997 struct mlx5_ifc_register_diag_buffer_ctrl_bits { 8998 u8 physical_address[0x40]; 8999 }; 9000 9001 struct mlx5_ifc_qtct_reg_bits { 9002 u8 operation_type[0x2]; 9003 u8 cap_local_admin[0x1]; 9004 u8 cap_remote_admin[0x1]; 9005 u8 reserved_0[0x4]; 9006 u8 port_number[0x8]; 9007 u8 reserved_1[0xd]; 9008 u8 prio[0x3]; 9009 9010 u8 reserved_2[0x1d]; 9011 u8 tclass[0x3]; 9012 }; 9013 9014 struct mlx5_ifc_qpdp_reg_bits { 9015 u8 reserved_0[0x8]; 9016 u8 port_number[0x8]; 9017 u8 reserved_1[0x10]; 9018 9019 u8 reserved_2[0x1d]; 9020 u8 pprio[0x3]; 9021 }; 9022 9023 struct mlx5_ifc_port_info_ro_fields_param_bits { 9024 u8 reserved_0[0x8]; 9025 u8 port[0x8]; 9026 u8 max_gid[0x10]; 9027 9028 u8 reserved_1[0x20]; 9029 9030 u8 port_guid[0x40]; 9031 }; 9032 9033 struct mlx5_ifc_nvqc_reg_bits { 9034 u8 type[0x20]; 9035 9036 u8 reserved_0[0x18]; 9037 u8 version[0x4]; 9038 u8 reserved_1[0x2]; 9039 u8 support_wr[0x1]; 9040 u8 support_rd[0x1]; 9041 }; 9042 9043 struct mlx5_ifc_nvia_reg_bits { 9044 u8 reserved_0[0x1d]; 9045 u8 target[0x3]; 9046 9047 u8 reserved_1[0x20]; 9048 }; 9049 9050 struct mlx5_ifc_nvdi_reg_bits { 9051 struct mlx5_ifc_config_item_bits configuration_item_header; 9052 }; 9053 9054 struct mlx5_ifc_nvda_reg_bits { 9055 struct mlx5_ifc_config_item_bits configuration_item_header; 9056 9057 u8 configuration_item_data[0x20]; 9058 }; 9059 9060 struct mlx5_ifc_node_info_ro_fields_param_bits { 9061 u8 system_image_guid[0x40]; 9062 9063 u8 reserved_0[0x40]; 9064 9065 u8 node_guid[0x40]; 9066 9067 u8 reserved_1[0x10]; 9068 u8 max_pkey[0x10]; 9069 9070 u8 reserved_2[0x20]; 9071 }; 9072 9073 struct mlx5_ifc_ets_tcn_config_reg_bits { 9074 u8 g[0x1]; 9075 u8 b[0x1]; 9076 u8 r[0x1]; 9077 u8 reserved_0[0x9]; 9078 u8 group[0x4]; 9079 u8 reserved_1[0x9]; 9080 u8 bw_allocation[0x7]; 9081 9082 u8 reserved_2[0xc]; 9083 u8 max_bw_units[0x4]; 9084 u8 reserved_3[0x8]; 9085 u8 max_bw_value[0x8]; 9086 }; 9087 9088 struct mlx5_ifc_ets_global_config_reg_bits { 9089 u8 reserved_0[0x2]; 9090 u8 r[0x1]; 9091 u8 reserved_1[0x1d]; 9092 9093 u8 reserved_2[0xc]; 9094 u8 max_bw_units[0x4]; 9095 u8 reserved_3[0x8]; 9096 u8 max_bw_value[0x8]; 9097 }; 9098 9099 struct mlx5_ifc_nodnic_mac_filters_bits { 9100 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 9101 9102 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 9103 9104 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 9105 9106 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 9107 9108 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 9109 9110 u8 reserved_0[0xc0]; 9111 }; 9112 9113 struct mlx5_ifc_nodnic_gid_filters_bits { 9114 u8 mgid_filter0[16][0x8]; 9115 9116 u8 mgid_filter1[16][0x8]; 9117 9118 u8 mgid_filter2[16][0x8]; 9119 9120 u8 mgid_filter3[16][0x8]; 9121 }; 9122 9123 enum { 9124 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 9125 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 9126 }; 9127 9128 enum { 9129 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 9130 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 9131 }; 9132 9133 struct mlx5_ifc_nodnic_config_reg_bits { 9134 u8 no_dram_nic_revision[0x8]; 9135 u8 hardware_format[0x8]; 9136 u8 support_receive_filter[0x1]; 9137 u8 support_promisc_filter[0x1]; 9138 u8 support_promisc_multicast_filter[0x1]; 9139 u8 reserved_0[0x2]; 9140 u8 log_working_buffer_size[0x3]; 9141 u8 log_pkey_table_size[0x4]; 9142 u8 reserved_1[0x3]; 9143 u8 num_ports[0x1]; 9144 9145 u8 reserved_2[0x2]; 9146 u8 log_max_ring_size[0x6]; 9147 u8 reserved_3[0x18]; 9148 9149 u8 lkey[0x20]; 9150 9151 u8 cqe_format[0x4]; 9152 u8 reserved_4[0x1c]; 9153 9154 u8 node_guid[0x40]; 9155 9156 u8 reserved_5[0x740]; 9157 9158 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 9159 9160 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 9161 }; 9162 9163 struct mlx5_ifc_vlan_layout_bits { 9164 u8 reserved_0[0x14]; 9165 u8 vlan[0xc]; 9166 9167 u8 reserved_1[0x20]; 9168 }; 9169 9170 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9171 u8 reserved_0[0x20]; 9172 9173 u8 mkey[0x20]; 9174 9175 u8 addressh_63_32[0x20]; 9176 9177 u8 addressl_31_0[0x20]; 9178 }; 9179 9180 struct mlx5_ifc_ud_adrs_vector_bits { 9181 u8 dc_key[0x40]; 9182 9183 u8 ext[0x1]; 9184 u8 reserved_0[0x7]; 9185 u8 destination_qp_dct[0x18]; 9186 9187 u8 static_rate[0x4]; 9188 u8 sl_eth_prio[0x4]; 9189 u8 fl[0x1]; 9190 u8 mlid[0x7]; 9191 u8 rlid_udp_sport[0x10]; 9192 9193 u8 reserved_1[0x20]; 9194 9195 u8 rmac_47_16[0x20]; 9196 9197 u8 rmac_15_0[0x10]; 9198 u8 tclass[0x8]; 9199 u8 hop_limit[0x8]; 9200 9201 u8 reserved_2[0x1]; 9202 u8 grh[0x1]; 9203 u8 reserved_3[0x2]; 9204 u8 src_addr_index[0x8]; 9205 u8 flow_label[0x14]; 9206 9207 u8 rgid_rip[16][0x8]; 9208 }; 9209 9210 struct mlx5_ifc_port_module_event_bits { 9211 u8 reserved_0[0x8]; 9212 u8 module[0x8]; 9213 u8 reserved_1[0xc]; 9214 u8 module_status[0x4]; 9215 9216 u8 reserved_2[0x14]; 9217 u8 error_type[0x4]; 9218 u8 reserved_3[0x8]; 9219 9220 u8 reserved_4[0xa0]; 9221 }; 9222 9223 struct mlx5_ifc_icmd_control_bits { 9224 u8 opcode[0x10]; 9225 u8 status[0x8]; 9226 u8 reserved_0[0x7]; 9227 u8 busy[0x1]; 9228 }; 9229 9230 struct mlx5_ifc_eqe_bits { 9231 u8 reserved_0[0x8]; 9232 u8 event_type[0x8]; 9233 u8 reserved_1[0x8]; 9234 u8 event_sub_type[0x8]; 9235 9236 u8 reserved_2[0xe0]; 9237 9238 union mlx5_ifc_event_auto_bits event_data; 9239 9240 u8 reserved_3[0x10]; 9241 u8 signature[0x8]; 9242 u8 reserved_4[0x7]; 9243 u8 owner[0x1]; 9244 }; 9245 9246 enum { 9247 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9248 }; 9249 9250 struct mlx5_ifc_cmd_queue_entry_bits { 9251 u8 type[0x8]; 9252 u8 reserved_0[0x18]; 9253 9254 u8 input_length[0x20]; 9255 9256 u8 input_mailbox_pointer_63_32[0x20]; 9257 9258 u8 input_mailbox_pointer_31_9[0x17]; 9259 u8 reserved_1[0x9]; 9260 9261 u8 command_input_inline_data[16][0x8]; 9262 9263 u8 command_output_inline_data[16][0x8]; 9264 9265 u8 output_mailbox_pointer_63_32[0x20]; 9266 9267 u8 output_mailbox_pointer_31_9[0x17]; 9268 u8 reserved_2[0x9]; 9269 9270 u8 output_length[0x20]; 9271 9272 u8 token[0x8]; 9273 u8 signature[0x8]; 9274 u8 reserved_3[0x8]; 9275 u8 status[0x7]; 9276 u8 ownership[0x1]; 9277 }; 9278 9279 struct mlx5_ifc_cmd_out_bits { 9280 u8 status[0x8]; 9281 u8 reserved_0[0x18]; 9282 9283 u8 syndrome[0x20]; 9284 9285 u8 command_output[0x20]; 9286 }; 9287 9288 struct mlx5_ifc_cmd_in_bits { 9289 u8 opcode[0x10]; 9290 u8 reserved_0[0x10]; 9291 9292 u8 reserved_1[0x10]; 9293 u8 op_mod[0x10]; 9294 9295 u8 command[0][0x20]; 9296 }; 9297 9298 struct mlx5_ifc_cmd_if_box_bits { 9299 u8 mailbox_data[512][0x8]; 9300 9301 u8 reserved_0[0x180]; 9302 9303 u8 next_pointer_63_32[0x20]; 9304 9305 u8 next_pointer_31_10[0x16]; 9306 u8 reserved_1[0xa]; 9307 9308 u8 block_number[0x20]; 9309 9310 u8 reserved_2[0x8]; 9311 u8 token[0x8]; 9312 u8 ctrl_signature[0x8]; 9313 u8 signature[0x8]; 9314 }; 9315 9316 struct mlx5_ifc_mtt_bits { 9317 u8 ptag_63_32[0x20]; 9318 9319 u8 ptag_31_8[0x18]; 9320 u8 reserved_0[0x6]; 9321 u8 wr_en[0x1]; 9322 u8 rd_en[0x1]; 9323 }; 9324 9325 struct mlx5_ifc_vendor_specific_cap_bits { 9326 u8 type[0x8]; 9327 u8 length[0x8]; 9328 u8 next_pointer[0x8]; 9329 u8 capability_id[0x8]; 9330 9331 u8 status[0x3]; 9332 u8 reserved_0[0xd]; 9333 u8 space[0x10]; 9334 9335 u8 counter[0x20]; 9336 9337 u8 semaphore[0x20]; 9338 9339 u8 flag[0x1]; 9340 u8 reserved_1[0x1]; 9341 u8 address[0x1e]; 9342 9343 u8 data[0x20]; 9344 }; 9345 9346 enum { 9347 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9348 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9349 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9350 }; 9351 9352 enum { 9353 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9354 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9355 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9356 }; 9357 9358 enum { 9359 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 9360 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 9361 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 9362 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 9363 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 9364 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 9365 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 9366 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 9367 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 9368 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 9369 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 9370 }; 9371 9372 struct mlx5_ifc_initial_seg_bits { 9373 u8 fw_rev_minor[0x10]; 9374 u8 fw_rev_major[0x10]; 9375 9376 u8 cmd_interface_rev[0x10]; 9377 u8 fw_rev_subminor[0x10]; 9378 9379 u8 reserved_0[0x40]; 9380 9381 u8 cmdq_phy_addr_63_32[0x20]; 9382 9383 u8 cmdq_phy_addr_31_12[0x14]; 9384 u8 reserved_1[0x2]; 9385 u8 nic_interface[0x2]; 9386 u8 log_cmdq_size[0x4]; 9387 u8 log_cmdq_stride[0x4]; 9388 9389 u8 command_doorbell_vector[0x20]; 9390 9391 u8 reserved_2[0xf00]; 9392 9393 u8 initializing[0x1]; 9394 u8 reserved_3[0x4]; 9395 u8 nic_interface_supported[0x3]; 9396 u8 reserved_4[0x18]; 9397 9398 struct mlx5_ifc_health_buffer_bits health_buffer; 9399 9400 u8 no_dram_nic_offset[0x20]; 9401 9402 u8 reserved_5[0x6de0]; 9403 9404 u8 internal_timer_h[0x20]; 9405 9406 u8 internal_timer_l[0x20]; 9407 9408 u8 reserved_6[0x20]; 9409 9410 u8 reserved_7[0x1f]; 9411 u8 clear_int[0x1]; 9412 9413 u8 health_syndrome[0x8]; 9414 u8 health_counter[0x18]; 9415 9416 u8 reserved_8[0x17fc0]; 9417 }; 9418 9419 union mlx5_ifc_icmd_interface_document_bits { 9420 struct mlx5_ifc_fw_version_bits fw_version; 9421 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 9422 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 9423 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 9424 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 9425 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 9426 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 9427 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 9428 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 9429 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 9430 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 9431 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 9432 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 9433 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 9434 u8 reserved_0[0x42c0]; 9435 }; 9436 9437 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 9438 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9439 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9440 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9441 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9442 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9443 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 9444 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9445 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9446 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 9447 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 9448 u8 reserved_0[0x7c0]; 9449 }; 9450 9451 struct mlx5_ifc_ppcnt_reg_bits { 9452 u8 swid[0x8]; 9453 u8 local_port[0x8]; 9454 u8 pnat[0x2]; 9455 u8 reserved_0[0x8]; 9456 u8 grp[0x6]; 9457 9458 u8 clr[0x1]; 9459 u8 reserved_1[0x1c]; 9460 u8 prio_tc[0x3]; 9461 9462 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9463 }; 9464 9465 struct mlx5_ifc_pcie_performance_counters_data_layout_bits { 9466 u8 life_time_counter_high[0x20]; 9467 9468 u8 life_time_counter_low[0x20]; 9469 9470 u8 rx_errors[0x20]; 9471 9472 u8 tx_errors[0x20]; 9473 9474 u8 l0_to_recovery_eieos[0x20]; 9475 9476 u8 l0_to_recovery_ts[0x20]; 9477 9478 u8 l0_to_recovery_framing[0x20]; 9479 9480 u8 l0_to_recovery_retrain[0x20]; 9481 9482 u8 crc_error_dllp[0x20]; 9483 9484 u8 crc_error_tlp[0x20]; 9485 9486 u8 reserved_0[0x680]; 9487 }; 9488 9489 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits { 9490 u8 life_time_counter_high[0x20]; 9491 9492 u8 life_time_counter_low[0x20]; 9493 9494 u8 time_to_boot_image_start[0x20]; 9495 9496 u8 time_to_link_image[0x20]; 9497 9498 u8 calibration_time[0x20]; 9499 9500 u8 time_to_first_perst[0x20]; 9501 9502 u8 time_to_detect_state[0x20]; 9503 9504 u8 time_to_l0[0x20]; 9505 9506 u8 time_to_crs_en[0x20]; 9507 9508 u8 time_to_plastic_image_start[0x20]; 9509 9510 u8 time_to_iron_image_start[0x20]; 9511 9512 u8 perst_handler[0x20]; 9513 9514 u8 times_in_l1[0x20]; 9515 9516 u8 times_in_l23[0x20]; 9517 9518 u8 dl_down[0x20]; 9519 9520 u8 config_cycle1usec[0x20]; 9521 9522 u8 config_cycle2to7usec[0x20]; 9523 9524 u8 config_cycle8to15usec[0x20]; 9525 9526 u8 config_cycle16to63usec[0x20]; 9527 9528 u8 config_cycle64usec[0x20]; 9529 9530 u8 correctable_err_msg_sent[0x20]; 9531 9532 u8 non_fatal_err_msg_sent[0x20]; 9533 9534 u8 fatal_err_msg_sent[0x20]; 9535 9536 u8 reserved_0[0x4e0]; 9537 }; 9538 9539 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits { 9540 u8 life_time_counter_high[0x20]; 9541 9542 u8 life_time_counter_low[0x20]; 9543 9544 u8 error_counter_lane0[0x20]; 9545 9546 u8 error_counter_lane1[0x20]; 9547 9548 u8 error_counter_lane2[0x20]; 9549 9550 u8 error_counter_lane3[0x20]; 9551 9552 u8 error_counter_lane4[0x20]; 9553 9554 u8 error_counter_lane5[0x20]; 9555 9556 u8 error_counter_lane6[0x20]; 9557 9558 u8 error_counter_lane7[0x20]; 9559 9560 u8 error_counter_lane8[0x20]; 9561 9562 u8 error_counter_lane9[0x20]; 9563 9564 u8 error_counter_lane10[0x20]; 9565 9566 u8 error_counter_lane11[0x20]; 9567 9568 u8 error_counter_lane12[0x20]; 9569 9570 u8 error_counter_lane13[0x20]; 9571 9572 u8 error_counter_lane14[0x20]; 9573 9574 u8 error_counter_lane15[0x20]; 9575 9576 u8 reserved_0[0x580]; 9577 }; 9578 9579 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits { 9580 struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout; 9581 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout; 9582 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout; 9583 u8 reserved_0[0xf8]; 9584 }; 9585 9586 struct mlx5_ifc_mpcnt_reg_bits { 9587 u8 reserved_0[0x8]; 9588 u8 pcie_index[0x8]; 9589 u8 reserved_1[0xa]; 9590 u8 grp[0x6]; 9591 9592 u8 clr[0x1]; 9593 u8 reserved_2[0x1f]; 9594 9595 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set; 9596 }; 9597 9598 union mlx5_ifc_ports_control_registers_document_bits { 9599 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 9600 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9601 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9602 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9603 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9604 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9605 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 9606 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9607 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9608 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 9609 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 9610 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9611 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 9612 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9613 struct mlx5_ifc_paos_reg_bits paos_reg; 9614 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 9615 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9616 struct mlx5_ifc_peir_reg_bits peir_reg; 9617 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9618 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9619 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 9620 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 9621 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 9622 struct mlx5_ifc_phrr_reg_bits phrr_reg; 9623 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9624 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9625 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9626 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9627 struct mlx5_ifc_plib_reg_bits plib_reg; 9628 struct mlx5_ifc_pll_status_data_bits pll_status_data; 9629 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9630 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9631 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9632 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9633 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9634 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9635 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9636 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9637 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9638 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9639 struct mlx5_ifc_ppll_reg_bits ppll_reg; 9640 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9641 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9642 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9643 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9644 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9645 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9646 struct mlx5_ifc_pude_reg_bits pude_reg; 9647 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9648 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9649 struct mlx5_ifc_slrp_reg_bits slrp_reg; 9650 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9651 u8 reserved_0[0x7880]; 9652 }; 9653 9654 union mlx5_ifc_debug_enhancements_document_bits { 9655 struct mlx5_ifc_health_buffer_bits health_buffer; 9656 u8 reserved_0[0x200]; 9657 }; 9658 9659 union mlx5_ifc_no_dram_nic_document_bits { 9660 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 9661 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 9662 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 9663 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 9664 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 9665 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 9666 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 9667 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 9668 u8 reserved_0[0x3160]; 9669 }; 9670 9671 union mlx5_ifc_uplink_pci_interface_document_bits { 9672 struct mlx5_ifc_initial_seg_bits initial_seg; 9673 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 9674 u8 reserved_0[0x20120]; 9675 }; 9676 9677 9678 #endif /* MLX5_IFC_H */ 9679