1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_IFC_H 29 #define MLX5_IFC_H 30 31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> 32 33 enum { 34 MLX5_EVENT_TYPE_COMP = 0x0, 35 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 36 MLX5_EVENT_TYPE_COMM_EST = 0x2, 37 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 38 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 39 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 40 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 41 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 42 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 43 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 44 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 45 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 46 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 47 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 48 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 49 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 50 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 51 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 52 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 53 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 54 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 55 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 56 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 57 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 58 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 59 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 60 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 61 MLX5_EVENT_TYPE_CMD = 0xa, 62 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 63 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 64 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 65 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 66 }; 67 68 enum { 69 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 70 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 71 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 72 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 73 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 74 }; 75 76 enum { 77 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 78 }; 79 80 enum { 81 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 82 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 83 }; 84 85 enum { 86 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 87 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 88 MLX5_CMD_OP_INIT_HCA = 0x102, 89 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 90 MLX5_CMD_OP_ENABLE_HCA = 0x104, 91 MLX5_CMD_OP_DISABLE_HCA = 0x105, 92 MLX5_CMD_OP_QUERY_PAGES = 0x107, 93 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 94 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 95 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 96 MLX5_CMD_OP_SET_ISSI = 0x10b, 97 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 98 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 99 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 100 MLX5_CMD_OP_CREATE_MKEY = 0x200, 101 MLX5_CMD_OP_QUERY_MKEY = 0x201, 102 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 103 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 104 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 105 MLX5_CMD_OP_CREATE_EQ = 0x301, 106 MLX5_CMD_OP_DESTROY_EQ = 0x302, 107 MLX5_CMD_OP_QUERY_EQ = 0x303, 108 MLX5_CMD_OP_GEN_EQE = 0x304, 109 MLX5_CMD_OP_CREATE_CQ = 0x400, 110 MLX5_CMD_OP_DESTROY_CQ = 0x401, 111 MLX5_CMD_OP_QUERY_CQ = 0x402, 112 MLX5_CMD_OP_MODIFY_CQ = 0x403, 113 MLX5_CMD_OP_CREATE_QP = 0x500, 114 MLX5_CMD_OP_DESTROY_QP = 0x501, 115 MLX5_CMD_OP_RST2INIT_QP = 0x502, 116 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 117 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 118 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 119 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 120 MLX5_CMD_OP_2ERR_QP = 0x507, 121 MLX5_CMD_OP_2RST_QP = 0x50a, 122 MLX5_CMD_OP_QUERY_QP = 0x50b, 123 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 124 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 125 MLX5_CMD_OP_CREATE_PSV = 0x600, 126 MLX5_CMD_OP_DESTROY_PSV = 0x601, 127 MLX5_CMD_OP_CREATE_SRQ = 0x700, 128 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 129 MLX5_CMD_OP_QUERY_SRQ = 0x702, 130 MLX5_CMD_OP_ARM_RQ = 0x703, 131 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 132 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 133 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 134 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 135 MLX5_CMD_OP_CREATE_DCT = 0x710, 136 MLX5_CMD_OP_DESTROY_DCT = 0x711, 137 MLX5_CMD_OP_DRAIN_DCT = 0x712, 138 MLX5_CMD_OP_QUERY_DCT = 0x713, 139 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 140 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 141 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 142 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 143 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 144 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 145 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 146 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 147 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 148 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 149 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 150 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 151 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 152 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 153 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 154 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 155 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 156 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 157 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 158 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 159 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 160 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 161 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 162 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 163 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 164 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 165 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 166 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 167 MLX5_CMD_OP_ALLOC_PD = 0x800, 168 MLX5_CMD_OP_DEALLOC_PD = 0x801, 169 MLX5_CMD_OP_ALLOC_UAR = 0x802, 170 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 171 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 172 MLX5_CMD_OP_ACCESS_REG = 0x805, 173 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 174 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 175 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 176 MLX5_CMD_OP_MAD_IFC = 0x50d, 177 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 178 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 179 MLX5_CMD_OP_NOP = 0x80d, 180 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 181 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 182 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 183 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 184 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 185 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 186 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 187 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 188 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 189 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 190 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 191 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 192 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 193 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 194 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 195 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 196 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 197 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 198 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 199 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 200 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 201 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 202 MLX5_CMD_OP_CREATE_LAG = 0x840, 203 MLX5_CMD_OP_MODIFY_LAG = 0x841, 204 MLX5_CMD_OP_QUERY_LAG = 0x842, 205 MLX5_CMD_OP_DESTROY_LAG = 0x843, 206 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 207 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 208 MLX5_CMD_OP_CREATE_TIR = 0x900, 209 MLX5_CMD_OP_MODIFY_TIR = 0x901, 210 MLX5_CMD_OP_DESTROY_TIR = 0x902, 211 MLX5_CMD_OP_QUERY_TIR = 0x903, 212 MLX5_CMD_OP_CREATE_SQ = 0x904, 213 MLX5_CMD_OP_MODIFY_SQ = 0x905, 214 MLX5_CMD_OP_DESTROY_SQ = 0x906, 215 MLX5_CMD_OP_QUERY_SQ = 0x907, 216 MLX5_CMD_OP_CREATE_RQ = 0x908, 217 MLX5_CMD_OP_MODIFY_RQ = 0x909, 218 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 219 MLX5_CMD_OP_QUERY_RQ = 0x90b, 220 MLX5_CMD_OP_CREATE_RMP = 0x90c, 221 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 222 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 223 MLX5_CMD_OP_QUERY_RMP = 0x90f, 224 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 225 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 226 MLX5_CMD_OP_CREATE_TIS = 0x912, 227 MLX5_CMD_OP_MODIFY_TIS = 0x913, 228 MLX5_CMD_OP_DESTROY_TIS = 0x914, 229 MLX5_CMD_OP_QUERY_TIS = 0x915, 230 MLX5_CMD_OP_CREATE_RQT = 0x916, 231 MLX5_CMD_OP_MODIFY_RQT = 0x917, 232 MLX5_CMD_OP_DESTROY_RQT = 0x918, 233 MLX5_CMD_OP_QUERY_RQT = 0x919, 234 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 235 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 236 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 237 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 238 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 239 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 240 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 241 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 242 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 243 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 244 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 245 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 246 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 247 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 248 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 249 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 250 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 251 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 252 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 253 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 254 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 255 }; 256 257 enum { 258 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 259 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 260 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 261 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 262 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 263 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 264 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 265 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 266 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 267 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 268 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 269 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 270 }; 271 272 struct mlx5_ifc_flow_table_fields_supported_bits { 273 u8 outer_dmac[0x1]; 274 u8 outer_smac[0x1]; 275 u8 outer_ether_type[0x1]; 276 u8 reserved_0[0x1]; 277 u8 outer_first_prio[0x1]; 278 u8 outer_first_cfi[0x1]; 279 u8 outer_first_vid[0x1]; 280 u8 reserved_1[0x1]; 281 u8 outer_second_prio[0x1]; 282 u8 outer_second_cfi[0x1]; 283 u8 outer_second_vid[0x1]; 284 u8 outer_ipv6_flow_label[0x1]; 285 u8 outer_sip[0x1]; 286 u8 outer_dip[0x1]; 287 u8 outer_frag[0x1]; 288 u8 outer_ip_protocol[0x1]; 289 u8 outer_ip_ecn[0x1]; 290 u8 outer_ip_dscp[0x1]; 291 u8 outer_udp_sport[0x1]; 292 u8 outer_udp_dport[0x1]; 293 u8 outer_tcp_sport[0x1]; 294 u8 outer_tcp_dport[0x1]; 295 u8 outer_tcp_flags[0x1]; 296 u8 outer_gre_protocol[0x1]; 297 u8 outer_gre_key[0x1]; 298 u8 outer_vxlan_vni[0x1]; 299 u8 outer_geneve_vni[0x1]; 300 u8 outer_geneve_oam[0x1]; 301 u8 outer_geneve_protocol_type[0x1]; 302 u8 outer_geneve_opt_len[0x1]; 303 u8 reserved_2[0x1]; 304 u8 source_eswitch_port[0x1]; 305 306 u8 inner_dmac[0x1]; 307 u8 inner_smac[0x1]; 308 u8 inner_ether_type[0x1]; 309 u8 reserved_3[0x1]; 310 u8 inner_first_prio[0x1]; 311 u8 inner_first_cfi[0x1]; 312 u8 inner_first_vid[0x1]; 313 u8 reserved_4[0x1]; 314 u8 inner_second_prio[0x1]; 315 u8 inner_second_cfi[0x1]; 316 u8 inner_second_vid[0x1]; 317 u8 inner_ipv6_flow_label[0x1]; 318 u8 inner_sip[0x1]; 319 u8 inner_dip[0x1]; 320 u8 inner_frag[0x1]; 321 u8 inner_ip_protocol[0x1]; 322 u8 inner_ip_ecn[0x1]; 323 u8 inner_ip_dscp[0x1]; 324 u8 inner_udp_sport[0x1]; 325 u8 inner_udp_dport[0x1]; 326 u8 inner_tcp_sport[0x1]; 327 u8 inner_tcp_dport[0x1]; 328 u8 inner_tcp_flags[0x1]; 329 u8 reserved_5[0x9]; 330 331 u8 reserved_6[0x1a]; 332 u8 bth_dst_qp[0x1]; 333 u8 reserved_7[0x4]; 334 u8 source_sqn[0x1]; 335 336 u8 reserved_8[0x20]; 337 }; 338 339 struct mlx5_ifc_eth_discard_cntrs_grp_bits { 340 u8 ingress_general_high[0x20]; 341 342 u8 ingress_general_low[0x20]; 343 344 u8 ingress_policy_engine_high[0x20]; 345 346 u8 ingress_policy_engine_low[0x20]; 347 348 u8 ingress_vlan_membership_high[0x20]; 349 350 u8 ingress_vlan_membership_low[0x20]; 351 352 u8 ingress_tag_frame_type_high[0x20]; 353 354 u8 ingress_tag_frame_type_low[0x20]; 355 356 u8 egress_vlan_membership_high[0x20]; 357 358 u8 egress_vlan_membership_low[0x20]; 359 360 u8 loopback_filter_high[0x20]; 361 362 u8 loopback_filter_low[0x20]; 363 364 u8 egress_general_high[0x20]; 365 366 u8 egress_general_low[0x20]; 367 368 u8 reserved_at_1c0[0x40]; 369 370 u8 egress_hoq_high[0x20]; 371 372 u8 egress_hoq_low[0x20]; 373 374 u8 port_isolation_high[0x20]; 375 376 u8 port_isolation_low[0x20]; 377 378 u8 egress_policy_engine_high[0x20]; 379 380 u8 egress_policy_engine_low[0x20]; 381 382 u8 ingress_tx_link_down_high[0x20]; 383 384 u8 ingress_tx_link_down_low[0x20]; 385 386 u8 egress_stp_filter_high[0x20]; 387 388 u8 egress_stp_filter_low[0x20]; 389 390 u8 egress_hoq_stall_high[0x20]; 391 392 u8 egress_hoq_stall_low[0x20]; 393 394 u8 reserved_at_340[0x440]; 395 }; 396 struct mlx5_ifc_flow_table_prop_layout_bits { 397 u8 ft_support[0x1]; 398 u8 flow_tag[0x1]; 399 u8 flow_counter[0x1]; 400 u8 flow_modify_en[0x1]; 401 u8 modify_root[0x1]; 402 u8 identified_miss_table[0x1]; 403 u8 flow_table_modify[0x1]; 404 u8 encap[0x1]; 405 u8 decap[0x1]; 406 u8 reset_root_to_default[0x1]; 407 u8 reserved_at_a[0x16]; 408 409 u8 reserved_at_20[0x2]; 410 u8 log_max_ft_size[0x6]; 411 u8 reserved_at_28[0x10]; 412 u8 max_ft_level[0x8]; 413 414 u8 reserved_at_40[0x20]; 415 416 u8 reserved_at_60[0x18]; 417 u8 log_max_ft_num[0x8]; 418 419 u8 reserved_at_80[0x10]; 420 u8 log_max_flow_counter[0x8]; 421 u8 log_max_destination[0x8]; 422 423 u8 reserved_at_a0[0x18]; 424 u8 log_max_flow[0x8]; 425 426 u8 reserved_at_c0[0x40]; 427 428 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 429 430 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 431 }; 432 433 struct mlx5_ifc_odp_per_transport_service_cap_bits { 434 u8 send[0x1]; 435 u8 receive[0x1]; 436 u8 write[0x1]; 437 u8 read[0x1]; 438 u8 atomic[0x1]; 439 u8 srq_receive[0x1]; 440 u8 reserved_0[0x1a]; 441 }; 442 443 struct mlx5_ifc_flow_counter_list_bits { 444 u8 reserved_0[0x10]; 445 u8 flow_counter_id[0x10]; 446 447 u8 reserved_1[0x20]; 448 }; 449 450 enum { 451 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 452 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 453 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 454 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 455 }; 456 457 struct mlx5_ifc_dest_format_struct_bits { 458 u8 destination_type[0x8]; 459 u8 destination_id[0x18]; 460 461 u8 reserved_0[0x20]; 462 }; 463 464 struct mlx5_ifc_ipv4_layout_bits { 465 u8 reserved_at_0[0x60]; 466 467 u8 ipv4[0x20]; 468 }; 469 470 struct mlx5_ifc_ipv6_layout_bits { 471 u8 ipv6[16][0x8]; 472 }; 473 474 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 475 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 476 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 477 u8 reserved_at_0[0x80]; 478 }; 479 480 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 481 u8 smac_47_16[0x20]; 482 483 u8 smac_15_0[0x10]; 484 u8 ethertype[0x10]; 485 486 u8 dmac_47_16[0x20]; 487 488 u8 dmac_15_0[0x10]; 489 u8 first_prio[0x3]; 490 u8 first_cfi[0x1]; 491 u8 first_vid[0xc]; 492 493 u8 ip_protocol[0x8]; 494 u8 ip_dscp[0x6]; 495 u8 ip_ecn[0x2]; 496 u8 cvlan_tag[0x1]; 497 u8 svlan_tag[0x1]; 498 u8 frag[0x1]; 499 u8 reserved_1[0x4]; 500 u8 tcp_flags[0x9]; 501 502 u8 tcp_sport[0x10]; 503 u8 tcp_dport[0x10]; 504 505 u8 reserved_2[0x20]; 506 507 u8 udp_sport[0x10]; 508 u8 udp_dport[0x10]; 509 510 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 511 512 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 513 }; 514 515 struct mlx5_ifc_fte_match_set_misc_bits { 516 u8 reserved_0[0x8]; 517 u8 source_sqn[0x18]; 518 519 u8 reserved_1[0x10]; 520 u8 source_port[0x10]; 521 522 u8 outer_second_prio[0x3]; 523 u8 outer_second_cfi[0x1]; 524 u8 outer_second_vid[0xc]; 525 u8 inner_second_prio[0x3]; 526 u8 inner_second_cfi[0x1]; 527 u8 inner_second_vid[0xc]; 528 529 u8 outer_second_vlan_tag[0x1]; 530 u8 inner_second_vlan_tag[0x1]; 531 u8 reserved_2[0xe]; 532 u8 gre_protocol[0x10]; 533 534 u8 gre_key_h[0x18]; 535 u8 gre_key_l[0x8]; 536 537 u8 vxlan_vni[0x18]; 538 u8 reserved_3[0x8]; 539 540 u8 geneve_vni[0x18]; 541 u8 reserved4[0x7]; 542 u8 geneve_oam[0x1]; 543 544 u8 reserved_5[0xc]; 545 u8 outer_ipv6_flow_label[0x14]; 546 547 u8 reserved_6[0xc]; 548 u8 inner_ipv6_flow_label[0x14]; 549 550 u8 reserved_7[0xa]; 551 u8 geneve_opt_len[0x6]; 552 u8 geneve_protocol_type[0x10]; 553 554 u8 reserved_8[0x8]; 555 u8 bth_dst_qp[0x18]; 556 557 u8 reserved_9[0xa0]; 558 }; 559 560 struct mlx5_ifc_cmd_pas_bits { 561 u8 pa_h[0x20]; 562 563 u8 pa_l[0x14]; 564 u8 reserved_0[0xc]; 565 }; 566 567 struct mlx5_ifc_uint64_bits { 568 u8 hi[0x20]; 569 570 u8 lo[0x20]; 571 }; 572 573 struct mlx5_ifc_application_prio_entry_bits { 574 u8 reserved_0[0x8]; 575 u8 priority[0x3]; 576 u8 reserved_1[0x2]; 577 u8 sel[0x3]; 578 u8 protocol_id[0x10]; 579 }; 580 581 struct mlx5_ifc_nodnic_ring_doorbell_bits { 582 u8 reserved_0[0x8]; 583 u8 ring_pi[0x10]; 584 u8 reserved_1[0x8]; 585 }; 586 587 enum { 588 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 589 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 590 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 591 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 592 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 593 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 594 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 595 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 596 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 597 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 598 }; 599 600 struct mlx5_ifc_ads_bits { 601 u8 fl[0x1]; 602 u8 free_ar[0x1]; 603 u8 reserved_0[0xe]; 604 u8 pkey_index[0x10]; 605 606 u8 reserved_1[0x8]; 607 u8 grh[0x1]; 608 u8 mlid[0x7]; 609 u8 rlid[0x10]; 610 611 u8 ack_timeout[0x5]; 612 u8 reserved_2[0x3]; 613 u8 src_addr_index[0x8]; 614 u8 log_rtm[0x4]; 615 u8 stat_rate[0x4]; 616 u8 hop_limit[0x8]; 617 618 u8 reserved_3[0x4]; 619 u8 tclass[0x8]; 620 u8 flow_label[0x14]; 621 622 u8 rgid_rip[16][0x8]; 623 624 u8 reserved_4[0x4]; 625 u8 f_dscp[0x1]; 626 u8 f_ecn[0x1]; 627 u8 reserved_5[0x1]; 628 u8 f_eth_prio[0x1]; 629 u8 ecn[0x2]; 630 u8 dscp[0x6]; 631 u8 udp_sport[0x10]; 632 633 u8 dei_cfi[0x1]; 634 u8 eth_prio[0x3]; 635 u8 sl[0x4]; 636 u8 port[0x8]; 637 u8 rmac_47_32[0x10]; 638 639 u8 rmac_31_0[0x20]; 640 }; 641 642 struct mlx5_ifc_diagnostic_counter_cap_bits { 643 u8 sync[0x1]; 644 u8 reserved_0[0xf]; 645 u8 counter_id[0x10]; 646 }; 647 648 struct mlx5_ifc_debug_cap_bits { 649 u8 reserved_0[0x18]; 650 u8 log_max_samples[0x8]; 651 652 u8 single[0x1]; 653 u8 repetitive[0x1]; 654 u8 health_mon_rx_activity[0x1]; 655 u8 reserved_1[0x15]; 656 u8 log_min_sample_period[0x8]; 657 658 u8 reserved_2[0x1c0]; 659 660 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 661 }; 662 663 struct mlx5_ifc_qos_cap_bits { 664 u8 packet_pacing[0x1]; 665 u8 esw_scheduling[0x1]; 666 u8 esw_bw_share[0x1]; 667 u8 esw_rate_limit[0x1]; 668 u8 hll[0x1]; 669 u8 packet_pacing_burst_bound[0x1]; 670 u8 reserved_at_6[0x1a]; 671 672 u8 reserved_at_20[0x20]; 673 674 u8 packet_pacing_max_rate[0x20]; 675 676 u8 packet_pacing_min_rate[0x20]; 677 678 u8 reserved_at_80[0x10]; 679 u8 packet_pacing_rate_table_size[0x10]; 680 681 u8 esw_element_type[0x10]; 682 u8 esw_tsar_type[0x10]; 683 684 u8 reserved_at_c0[0x10]; 685 u8 max_qos_para_vport[0x10]; 686 687 u8 max_tsar_bw_share[0x20]; 688 689 u8 reserved_at_100[0x700]; 690 }; 691 692 struct mlx5_ifc_snapshot_cap_bits { 693 u8 reserved_0[0x1d]; 694 u8 suspend_qp_uc[0x1]; 695 u8 suspend_qp_ud[0x1]; 696 u8 suspend_qp_rc[0x1]; 697 698 u8 reserved_1[0x1c]; 699 u8 restore_pd[0x1]; 700 u8 restore_uar[0x1]; 701 u8 restore_mkey[0x1]; 702 u8 restore_qp[0x1]; 703 704 u8 reserved_2[0x1e]; 705 u8 named_mkey[0x1]; 706 u8 named_qp[0x1]; 707 708 u8 reserved_3[0x7a0]; 709 }; 710 711 struct mlx5_ifc_e_switch_cap_bits { 712 u8 vport_svlan_strip[0x1]; 713 u8 vport_cvlan_strip[0x1]; 714 u8 vport_svlan_insert[0x1]; 715 u8 vport_cvlan_insert_if_not_exist[0x1]; 716 u8 vport_cvlan_insert_overwrite[0x1]; 717 718 u8 reserved_0[0x19]; 719 720 u8 nic_vport_node_guid_modify[0x1]; 721 u8 nic_vport_port_guid_modify[0x1]; 722 723 u8 reserved_1[0x7e0]; 724 }; 725 726 struct mlx5_ifc_flow_table_eswitch_cap_bits { 727 u8 reserved_0[0x200]; 728 729 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 730 731 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 732 733 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 734 735 u8 reserved_1[0x7800]; 736 }; 737 738 struct mlx5_ifc_flow_table_nic_cap_bits { 739 u8 nic_rx_multi_path_tirs[0x1]; 740 u8 nic_rx_multi_path_tirs_fts[0x1]; 741 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 742 u8 reserved_at_3[0x1fd]; 743 744 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 745 746 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 747 748 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 749 750 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 751 752 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 753 754 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 755 756 u8 reserved_1[0x7200]; 757 }; 758 759 enum { 760 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_PDDR = 0x5031, 761 }; 762 763 struct mlx5_ifc_pddr_module_info_bits { 764 u8 cable_technology[0x8]; 765 u8 cable_breakout[0x8]; 766 u8 ext_ethernet_compliance_code[0x8]; 767 u8 ethernet_compliance_code[0x8]; 768 769 u8 cable_type[0x4]; 770 u8 cable_vendor[0x4]; 771 u8 cable_length[0x8]; 772 u8 cable_identifier[0x8]; 773 u8 cable_power_class[0x8]; 774 775 u8 reserved_at_40[0x8]; 776 u8 cable_rx_amp[0x8]; 777 u8 cable_rx_emphasis[0x8]; 778 u8 cable_tx_equalization[0x8]; 779 780 u8 reserved_at_60[0x8]; 781 u8 cable_attenuation_12g[0x8]; 782 u8 cable_attenuation_7g[0x8]; 783 u8 cable_attenuation_5g[0x8]; 784 785 u8 reserved_at_80[0x8]; 786 u8 rx_cdr_cap[0x4]; 787 u8 tx_cdr_cap[0x4]; 788 u8 reserved_at_90[0x4]; 789 u8 rx_cdr_state[0x4]; 790 u8 reserved_at_98[0x4]; 791 u8 tx_cdr_state[0x4]; 792 793 u8 vendor_name[16][0x8]; 794 795 u8 vendor_pn[16][0x8]; 796 797 u8 vendor_rev[0x20]; 798 799 u8 fw_version[0x20]; 800 801 u8 vendor_sn[16][0x8]; 802 803 u8 temperature[0x10]; 804 u8 voltage[0x10]; 805 806 u8 rx_power_lane0[0x10]; 807 u8 rx_power_lane1[0x10]; 808 809 u8 rx_power_lane2[0x10]; 810 u8 rx_power_lane3[0x10]; 811 812 u8 reserved_at_2c0[0x40]; 813 814 u8 tx_power_lane0[0x10]; 815 u8 tx_power_lane1[0x10]; 816 817 u8 tx_power_lane2[0x10]; 818 u8 tx_power_lane3[0x10]; 819 820 u8 reserved_at_340[0x40]; 821 822 u8 tx_bias_lane0[0x10]; 823 u8 tx_bias_lane1[0x10]; 824 825 u8 tx_bias_lane2[0x10]; 826 u8 tx_bias_lane3[0x10]; 827 828 u8 reserved_at_3c0[0x40]; 829 830 u8 temperature_high_th[0x10]; 831 u8 temperature_low_th[0x10]; 832 833 u8 voltage_high_th[0x10]; 834 u8 voltage_low_th[0x10]; 835 836 u8 rx_power_high_th[0x10]; 837 u8 rx_power_low_th[0x10]; 838 839 u8 tx_power_high_th[0x10]; 840 u8 tx_power_low_th[0x10]; 841 842 u8 tx_bias_high_th[0x10]; 843 u8 tx_bias_low_th[0x10]; 844 845 u8 reserved_at_4a0[0x10]; 846 u8 wavelength[0x10]; 847 848 u8 reserved_at_4c0[0x300]; 849 }; 850 851 union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits { 852 struct mlx5_ifc_pddr_module_info_bits pddr_module_info; 853 u8 reserved_at_0[0x7c0]; 854 }; 855 856 struct mlx5_ifc_pddr_reg_bits { 857 u8 reserved_at_0[0x8]; 858 u8 local_port[0x8]; 859 u8 pnat[0x2]; 860 u8 reserved_at_12[0xe]; 861 862 u8 reserved_at_20[0x18]; 863 u8 page_select[0x8]; 864 865 union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits page_data; 866 }; 867 868 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 869 u8 csum_cap[0x1]; 870 u8 vlan_cap[0x1]; 871 u8 lro_cap[0x1]; 872 u8 lro_psh_flag[0x1]; 873 u8 lro_time_stamp[0x1]; 874 u8 lro_max_msg_sz_mode[0x2]; 875 u8 wqe_vlan_insert[0x1]; 876 u8 self_lb_en_modifiable[0x1]; 877 u8 self_lb_mc[0x1]; 878 u8 self_lb_uc[0x1]; 879 u8 max_lso_cap[0x5]; 880 u8 multi_pkt_send_wqe[0x2]; 881 u8 wqe_inline_mode[0x2]; 882 u8 rss_ind_tbl_cap[0x4]; 883 u8 scatter_fcs[0x1]; 884 u8 reserved_1[0x2]; 885 u8 tunnel_lso_const_out_ip_id[0x1]; 886 u8 tunnel_lro_gre[0x1]; 887 u8 tunnel_lro_vxlan[0x1]; 888 u8 tunnel_statless_gre[0x1]; 889 u8 tunnel_stateless_vxlan[0x1]; 890 891 u8 swp[0x1]; 892 u8 swp_csum[0x1]; 893 u8 swp_lso[0x1]; 894 u8 reserved_2[0x1b]; 895 u8 max_geneve_opt_len[0x1]; 896 u8 tunnel_stateless_geneve_rx[0x1]; 897 898 u8 reserved_3[0x10]; 899 u8 lro_min_mss_size[0x10]; 900 901 u8 reserved_4[0x120]; 902 903 u8 lro_timer_supported_periods[4][0x20]; 904 905 u8 reserved_5[0x600]; 906 }; 907 908 enum { 909 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 910 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 911 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 912 }; 913 914 struct mlx5_ifc_roce_cap_bits { 915 u8 roce_apm[0x1]; 916 u8 rts2rts_primary_eth_prio[0x1]; 917 u8 roce_rx_allow_untagged[0x1]; 918 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 919 920 u8 reserved_0[0x1c]; 921 922 u8 reserved_1[0x60]; 923 924 u8 reserved_2[0xc]; 925 u8 l3_type[0x4]; 926 u8 reserved_3[0x8]; 927 u8 roce_version[0x8]; 928 929 u8 reserved_4[0x10]; 930 u8 r_roce_dest_udp_port[0x10]; 931 932 u8 r_roce_max_src_udp_port[0x10]; 933 u8 r_roce_min_src_udp_port[0x10]; 934 935 u8 reserved_5[0x10]; 936 u8 roce_address_table_size[0x10]; 937 938 u8 reserved_6[0x700]; 939 }; 940 941 enum { 942 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 943 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 944 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 945 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 946 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 947 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 948 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 949 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 950 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 951 }; 952 953 enum { 954 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 955 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 956 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 957 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 958 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 959 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 960 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 961 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 962 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 963 }; 964 965 struct mlx5_ifc_atomic_caps_bits { 966 u8 reserved_0[0x40]; 967 968 u8 atomic_req_8B_endianess_mode[0x2]; 969 u8 reserved_1[0x4]; 970 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 971 972 u8 reserved_2[0x19]; 973 974 u8 reserved_3[0x20]; 975 976 u8 reserved_4[0x10]; 977 u8 atomic_operations[0x10]; 978 979 u8 reserved_5[0x10]; 980 u8 atomic_size_qp[0x10]; 981 982 u8 reserved_6[0x10]; 983 u8 atomic_size_dc[0x10]; 984 985 u8 reserved_7[0x720]; 986 }; 987 988 struct mlx5_ifc_odp_cap_bits { 989 u8 reserved_0[0x40]; 990 991 u8 sig[0x1]; 992 u8 reserved_1[0x1f]; 993 994 u8 reserved_2[0x20]; 995 996 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 997 998 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 999 1000 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1001 1002 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1003 1004 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1005 1006 u8 reserved_3[0x6e0]; 1007 }; 1008 1009 enum { 1010 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1011 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1012 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1013 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1014 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1015 }; 1016 1017 enum { 1018 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1019 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1020 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1021 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1022 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1023 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1024 }; 1025 1026 enum { 1027 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1028 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1029 }; 1030 1031 enum { 1032 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1033 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1034 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1035 }; 1036 1037 struct mlx5_ifc_cmd_hca_cap_bits { 1038 u8 reserved_0[0x80]; 1039 1040 u8 log_max_srq_sz[0x8]; 1041 u8 log_max_qp_sz[0x8]; 1042 u8 reserved_1[0xb]; 1043 u8 log_max_qp[0x5]; 1044 1045 u8 reserved_2[0xb]; 1046 u8 log_max_srq[0x5]; 1047 u8 reserved_3[0x10]; 1048 1049 u8 reserved_4[0x8]; 1050 u8 log_max_cq_sz[0x8]; 1051 u8 reserved_5[0xb]; 1052 u8 log_max_cq[0x5]; 1053 1054 u8 log_max_eq_sz[0x8]; 1055 u8 relaxed_ordering_write[1]; 1056 u8 reserved_6[0x1]; 1057 u8 log_max_mkey[0x6]; 1058 u8 reserved_7[0xb]; 1059 u8 fast_teardown[0x1]; 1060 u8 log_max_eq[0x4]; 1061 1062 u8 max_indirection[0x8]; 1063 u8 reserved_8[0x1]; 1064 u8 log_max_mrw_sz[0x7]; 1065 u8 force_teardown[0x1]; 1066 u8 reserved_9[0x1]; 1067 u8 log_max_bsf_list_size[0x6]; 1068 u8 reserved_10[0x2]; 1069 u8 log_max_klm_list_size[0x6]; 1070 1071 u8 reserved_11[0xa]; 1072 u8 log_max_ra_req_dc[0x6]; 1073 u8 reserved_12[0xa]; 1074 u8 log_max_ra_res_dc[0x6]; 1075 1076 u8 reserved_13[0xa]; 1077 u8 log_max_ra_req_qp[0x6]; 1078 u8 reserved_14[0xa]; 1079 u8 log_max_ra_res_qp[0x6]; 1080 1081 u8 pad_cap[0x1]; 1082 u8 cc_query_allowed[0x1]; 1083 u8 cc_modify_allowed[0x1]; 1084 u8 start_pad[0x1]; 1085 u8 cache_line_128byte[0x1]; 1086 u8 reserved_at_165[0xa]; 1087 u8 qcam_reg[0x1]; 1088 u8 gid_table_size[0x10]; 1089 1090 u8 out_of_seq_cnt[0x1]; 1091 u8 vport_counters[0x1]; 1092 u8 retransmission_q_counters[0x1]; 1093 u8 debug[0x1]; 1094 u8 modify_rq_counters_set_id[0x1]; 1095 u8 rq_delay_drop[0x1]; 1096 u8 max_qp_cnt[0xa]; 1097 u8 pkey_table_size[0x10]; 1098 1099 u8 vport_group_manager[0x1]; 1100 u8 vhca_group_manager[0x1]; 1101 u8 ib_virt[0x1]; 1102 u8 eth_virt[0x1]; 1103 u8 reserved_17[0x1]; 1104 u8 ets[0x1]; 1105 u8 nic_flow_table[0x1]; 1106 u8 eswitch_flow_table[0x1]; 1107 u8 reserved_18[0x1]; 1108 u8 mcam_reg[0x1]; 1109 u8 pcam_reg[0x1]; 1110 u8 local_ca_ack_delay[0x5]; 1111 u8 port_module_event[0x1]; 1112 u8 reserved_19[0x5]; 1113 u8 port_type[0x2]; 1114 u8 num_ports[0x8]; 1115 1116 u8 snapshot[0x1]; 1117 u8 reserved_20[0x2]; 1118 u8 log_max_msg[0x5]; 1119 u8 reserved_21[0x4]; 1120 u8 max_tc[0x4]; 1121 u8 temp_warn_event[0x1]; 1122 u8 dcbx[0x1]; 1123 u8 general_notification_event[0x1]; 1124 u8 reserved_at_1d3[0x2]; 1125 u8 fpga[0x1]; 1126 u8 rol_s[0x1]; 1127 u8 rol_g[0x1]; 1128 u8 reserved_23[0x1]; 1129 u8 wol_s[0x1]; 1130 u8 wol_g[0x1]; 1131 u8 wol_a[0x1]; 1132 u8 wol_b[0x1]; 1133 u8 wol_m[0x1]; 1134 u8 wol_u[0x1]; 1135 u8 wol_p[0x1]; 1136 1137 u8 stat_rate_support[0x10]; 1138 u8 reserved_24[0xc]; 1139 u8 cqe_version[0x4]; 1140 1141 u8 compact_address_vector[0x1]; 1142 u8 striding_rq[0x1]; 1143 u8 reserved_25[0x1]; 1144 u8 ipoib_enhanced_offloads[0x1]; 1145 u8 ipoib_ipoib_offloads[0x1]; 1146 u8 reserved_26[0x8]; 1147 u8 dc_connect_qp[0x1]; 1148 u8 dc_cnak_trace[0x1]; 1149 u8 drain_sigerr[0x1]; 1150 u8 cmdif_checksum[0x2]; 1151 u8 sigerr_cqe[0x1]; 1152 u8 reserved_27[0x1]; 1153 u8 wq_signature[0x1]; 1154 u8 sctr_data_cqe[0x1]; 1155 u8 reserved_28[0x1]; 1156 u8 sho[0x1]; 1157 u8 tph[0x1]; 1158 u8 rf[0x1]; 1159 u8 dct[0x1]; 1160 u8 qos[0x1]; 1161 u8 eth_net_offloads[0x1]; 1162 u8 roce[0x1]; 1163 u8 atomic[0x1]; 1164 u8 reserved_30[0x1]; 1165 1166 u8 cq_oi[0x1]; 1167 u8 cq_resize[0x1]; 1168 u8 cq_moderation[0x1]; 1169 u8 cq_period_mode_modify[0x1]; 1170 u8 cq_invalidate[0x1]; 1171 u8 reserved_at_225[0x1]; 1172 u8 cq_eq_remap[0x1]; 1173 u8 pg[0x1]; 1174 u8 block_lb_mc[0x1]; 1175 u8 exponential_backoff[0x1]; 1176 u8 scqe_break_moderation[0x1]; 1177 u8 cq_period_start_from_cqe[0x1]; 1178 u8 cd[0x1]; 1179 u8 atm[0x1]; 1180 u8 apm[0x1]; 1181 u8 imaicl[0x1]; 1182 u8 reserved_32[0x6]; 1183 u8 qkv[0x1]; 1184 u8 pkv[0x1]; 1185 u8 set_deth_sqpn[0x1]; 1186 u8 reserved_33[0x3]; 1187 u8 xrc[0x1]; 1188 u8 ud[0x1]; 1189 u8 uc[0x1]; 1190 u8 rc[0x1]; 1191 1192 u8 reserved_34[0xa]; 1193 u8 uar_sz[0x6]; 1194 u8 reserved_35[0x8]; 1195 u8 log_pg_sz[0x8]; 1196 1197 u8 bf[0x1]; 1198 u8 driver_version[0x1]; 1199 u8 pad_tx_eth_packet[0x1]; 1200 u8 reserved_36[0x8]; 1201 u8 log_bf_reg_size[0x5]; 1202 u8 reserved_37[0x10]; 1203 1204 u8 num_of_diagnostic_counters[0x10]; 1205 u8 max_wqe_sz_sq[0x10]; 1206 1207 u8 reserved_38[0x10]; 1208 u8 max_wqe_sz_rq[0x10]; 1209 1210 u8 reserved_39[0x10]; 1211 u8 max_wqe_sz_sq_dc[0x10]; 1212 1213 u8 reserved_40[0x7]; 1214 u8 max_qp_mcg[0x19]; 1215 1216 u8 reserved_41[0x18]; 1217 u8 log_max_mcg[0x8]; 1218 1219 u8 reserved_42[0x3]; 1220 u8 log_max_transport_domain[0x5]; 1221 u8 reserved_43[0x3]; 1222 u8 log_max_pd[0x5]; 1223 u8 reserved_44[0xb]; 1224 u8 log_max_xrcd[0x5]; 1225 1226 u8 nic_receive_steering_discard[0x1]; 1227 u8 reserved_45[0x7]; 1228 u8 log_max_flow_counter_bulk[0x8]; 1229 u8 max_flow_counter[0x10]; 1230 1231 u8 reserved_46[0x3]; 1232 u8 log_max_rq[0x5]; 1233 u8 reserved_47[0x3]; 1234 u8 log_max_sq[0x5]; 1235 u8 reserved_48[0x3]; 1236 u8 log_max_tir[0x5]; 1237 u8 reserved_49[0x3]; 1238 u8 log_max_tis[0x5]; 1239 1240 u8 basic_cyclic_rcv_wqe[0x1]; 1241 u8 reserved_50[0x2]; 1242 u8 log_max_rmp[0x5]; 1243 u8 reserved_51[0x3]; 1244 u8 log_max_rqt[0x5]; 1245 u8 reserved_52[0x3]; 1246 u8 log_max_rqt_size[0x5]; 1247 u8 reserved_53[0x3]; 1248 u8 log_max_tis_per_sq[0x5]; 1249 1250 u8 reserved_54[0x3]; 1251 u8 log_max_stride_sz_rq[0x5]; 1252 u8 reserved_55[0x3]; 1253 u8 log_min_stride_sz_rq[0x5]; 1254 u8 reserved_56[0x3]; 1255 u8 log_max_stride_sz_sq[0x5]; 1256 u8 reserved_57[0x3]; 1257 u8 log_min_stride_sz_sq[0x5]; 1258 1259 u8 reserved_58[0x1b]; 1260 u8 log_max_wq_sz[0x5]; 1261 1262 u8 nic_vport_change_event[0x1]; 1263 u8 disable_local_lb[0x1]; 1264 u8 reserved_59[0x9]; 1265 u8 log_max_vlan_list[0x5]; 1266 u8 reserved_60[0x3]; 1267 u8 log_max_current_mc_list[0x5]; 1268 u8 reserved_61[0x3]; 1269 u8 log_max_current_uc_list[0x5]; 1270 1271 u8 reserved_62[0x80]; 1272 1273 u8 reserved_63[0x3]; 1274 u8 log_max_l2_table[0x5]; 1275 u8 reserved_64[0x8]; 1276 u8 log_uar_page_sz[0x10]; 1277 1278 u8 reserved_65[0x20]; 1279 1280 u8 device_frequency_mhz[0x20]; 1281 1282 u8 device_frequency_khz[0x20]; 1283 1284 u8 reserved_66[0x80]; 1285 1286 u8 log_max_atomic_size_qp[0x8]; 1287 u8 reserved_67[0x10]; 1288 u8 log_max_atomic_size_dc[0x8]; 1289 1290 u8 reserved_68[0x1f]; 1291 u8 cqe_compression[0x1]; 1292 1293 u8 cqe_compression_timeout[0x10]; 1294 u8 cqe_compression_max_num[0x10]; 1295 1296 u8 reserved_69[0x220]; 1297 }; 1298 1299 enum mlx5_flow_destination_type { 1300 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1301 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1302 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1303 }; 1304 1305 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1306 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1307 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1308 u8 reserved_0[0x40]; 1309 }; 1310 1311 struct mlx5_ifc_fte_match_param_bits { 1312 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1313 1314 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1315 1316 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1317 1318 u8 reserved_0[0xa00]; 1319 }; 1320 1321 enum { 1322 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1323 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1324 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1325 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1326 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1327 }; 1328 1329 struct mlx5_ifc_rx_hash_field_select_bits { 1330 u8 l3_prot_type[0x1]; 1331 u8 l4_prot_type[0x1]; 1332 u8 selected_fields[0x1e]; 1333 }; 1334 1335 enum { 1336 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1337 MLX5_WQ_TYPE_CYCLIC = 0x1, 1338 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1339 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1340 }; 1341 1342 enum rq_type { 1343 RQ_TYPE_NONE, 1344 RQ_TYPE_STRIDE, 1345 }; 1346 1347 enum { 1348 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1349 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1350 }; 1351 1352 struct mlx5_ifc_wq_bits { 1353 u8 wq_type[0x4]; 1354 u8 wq_signature[0x1]; 1355 u8 end_padding_mode[0x2]; 1356 u8 cd_slave[0x1]; 1357 u8 reserved_0[0x18]; 1358 1359 u8 hds_skip_first_sge[0x1]; 1360 u8 log2_hds_buf_size[0x3]; 1361 u8 reserved_1[0x7]; 1362 u8 page_offset[0x5]; 1363 u8 lwm[0x10]; 1364 1365 u8 reserved_2[0x8]; 1366 u8 pd[0x18]; 1367 1368 u8 reserved_3[0x8]; 1369 u8 uar_page[0x18]; 1370 1371 u8 dbr_addr[0x40]; 1372 1373 u8 hw_counter[0x20]; 1374 1375 u8 sw_counter[0x20]; 1376 1377 u8 reserved_4[0xc]; 1378 u8 log_wq_stride[0x4]; 1379 u8 reserved_5[0x3]; 1380 u8 log_wq_pg_sz[0x5]; 1381 u8 reserved_6[0x3]; 1382 u8 log_wq_sz[0x5]; 1383 1384 u8 reserved_7[0x15]; 1385 u8 single_wqe_log_num_of_strides[0x3]; 1386 u8 two_byte_shift_en[0x1]; 1387 u8 reserved_8[0x4]; 1388 u8 single_stride_log_num_of_bytes[0x3]; 1389 1390 u8 reserved_9[0x4c0]; 1391 1392 struct mlx5_ifc_cmd_pas_bits pas[0]; 1393 }; 1394 1395 struct mlx5_ifc_rq_num_bits { 1396 u8 reserved_0[0x8]; 1397 u8 rq_num[0x18]; 1398 }; 1399 1400 struct mlx5_ifc_mac_address_layout_bits { 1401 u8 reserved_0[0x10]; 1402 u8 mac_addr_47_32[0x10]; 1403 1404 u8 mac_addr_31_0[0x20]; 1405 }; 1406 1407 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1408 u8 reserved_0[0xa0]; 1409 1410 u8 min_time_between_cnps[0x20]; 1411 1412 u8 reserved_1[0x12]; 1413 u8 cnp_dscp[0x6]; 1414 u8 reserved_2[0x4]; 1415 u8 cnp_prio_mode[0x1]; 1416 u8 cnp_802p_prio[0x3]; 1417 1418 u8 reserved_3[0x720]; 1419 }; 1420 1421 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1422 u8 reserved_0[0x60]; 1423 1424 u8 reserved_1[0x4]; 1425 u8 clamp_tgt_rate[0x1]; 1426 u8 reserved_2[0x3]; 1427 u8 clamp_tgt_rate_after_time_inc[0x1]; 1428 u8 reserved_3[0x17]; 1429 1430 u8 reserved_4[0x20]; 1431 1432 u8 rpg_time_reset[0x20]; 1433 1434 u8 rpg_byte_reset[0x20]; 1435 1436 u8 rpg_threshold[0x20]; 1437 1438 u8 rpg_max_rate[0x20]; 1439 1440 u8 rpg_ai_rate[0x20]; 1441 1442 u8 rpg_hai_rate[0x20]; 1443 1444 u8 rpg_gd[0x20]; 1445 1446 u8 rpg_min_dec_fac[0x20]; 1447 1448 u8 rpg_min_rate[0x20]; 1449 1450 u8 reserved_5[0xe0]; 1451 1452 u8 rate_to_set_on_first_cnp[0x20]; 1453 1454 u8 dce_tcp_g[0x20]; 1455 1456 u8 dce_tcp_rtt[0x20]; 1457 1458 u8 rate_reduce_monitor_period[0x20]; 1459 1460 u8 reserved_6[0x20]; 1461 1462 u8 initial_alpha_value[0x20]; 1463 1464 u8 reserved_7[0x4a0]; 1465 }; 1466 1467 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1468 u8 reserved_0[0x80]; 1469 1470 u8 rppp_max_rps[0x20]; 1471 1472 u8 rpg_time_reset[0x20]; 1473 1474 u8 rpg_byte_reset[0x20]; 1475 1476 u8 rpg_threshold[0x20]; 1477 1478 u8 rpg_max_rate[0x20]; 1479 1480 u8 rpg_ai_rate[0x20]; 1481 1482 u8 rpg_hai_rate[0x20]; 1483 1484 u8 rpg_gd[0x20]; 1485 1486 u8 rpg_min_dec_fac[0x20]; 1487 1488 u8 rpg_min_rate[0x20]; 1489 1490 u8 reserved_1[0x640]; 1491 }; 1492 1493 enum { 1494 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1495 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1496 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1497 }; 1498 1499 struct mlx5_ifc_resize_field_select_bits { 1500 u8 resize_field_select[0x20]; 1501 }; 1502 1503 enum { 1504 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1505 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1506 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1507 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1508 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1509 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1510 }; 1511 1512 struct mlx5_ifc_modify_field_select_bits { 1513 u8 modify_field_select[0x20]; 1514 }; 1515 1516 struct mlx5_ifc_field_select_r_roce_np_bits { 1517 u8 field_select_r_roce_np[0x20]; 1518 }; 1519 1520 enum { 1521 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1522 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1523 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1524 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1525 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1526 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1527 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1528 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1529 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1530 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1531 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1532 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1533 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1534 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1535 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1536 }; 1537 1538 struct mlx5_ifc_field_select_r_roce_rp_bits { 1539 u8 field_select_r_roce_rp[0x20]; 1540 }; 1541 1542 enum { 1543 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1544 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1545 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1546 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1547 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1548 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1549 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1550 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1551 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1552 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1553 }; 1554 1555 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1556 u8 field_select_8021qaurp[0x20]; 1557 }; 1558 1559 struct mlx5_ifc_pptb_reg_bits { 1560 u8 reserved_0[0x2]; 1561 u8 mm[0x2]; 1562 u8 reserved_1[0x4]; 1563 u8 local_port[0x8]; 1564 u8 reserved_2[0x6]; 1565 u8 cm[0x1]; 1566 u8 um[0x1]; 1567 u8 pm[0x8]; 1568 1569 u8 prio7buff[0x4]; 1570 u8 prio6buff[0x4]; 1571 u8 prio5buff[0x4]; 1572 u8 prio4buff[0x4]; 1573 u8 prio3buff[0x4]; 1574 u8 prio2buff[0x4]; 1575 u8 prio1buff[0x4]; 1576 u8 prio0buff[0x4]; 1577 1578 u8 pm_msb[0x8]; 1579 u8 reserved_3[0x10]; 1580 u8 ctrl_buff[0x4]; 1581 u8 untagged_buff[0x4]; 1582 }; 1583 1584 struct mlx5_ifc_dcbx_app_reg_bits { 1585 u8 reserved_0[0x8]; 1586 u8 port_number[0x8]; 1587 u8 reserved_1[0x10]; 1588 1589 u8 reserved_2[0x1a]; 1590 u8 num_app_prio[0x6]; 1591 1592 u8 reserved_3[0x40]; 1593 1594 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1595 }; 1596 1597 struct mlx5_ifc_dcbx_param_reg_bits { 1598 u8 dcbx_cee_cap[0x1]; 1599 u8 dcbx_ieee_cap[0x1]; 1600 u8 dcbx_standby_cap[0x1]; 1601 u8 reserved_0[0x5]; 1602 u8 port_number[0x8]; 1603 u8 reserved_1[0xa]; 1604 u8 max_application_table_size[0x6]; 1605 1606 u8 reserved_2[0x15]; 1607 u8 version_oper[0x3]; 1608 u8 reserved_3[0x5]; 1609 u8 version_admin[0x3]; 1610 1611 u8 willing_admin[0x1]; 1612 u8 reserved_4[0x3]; 1613 u8 pfc_cap_oper[0x4]; 1614 u8 reserved_5[0x4]; 1615 u8 pfc_cap_admin[0x4]; 1616 u8 reserved_6[0x4]; 1617 u8 num_of_tc_oper[0x4]; 1618 u8 reserved_7[0x4]; 1619 u8 num_of_tc_admin[0x4]; 1620 1621 u8 remote_willing[0x1]; 1622 u8 reserved_8[0x3]; 1623 u8 remote_pfc_cap[0x4]; 1624 u8 reserved_9[0x14]; 1625 u8 remote_num_of_tc[0x4]; 1626 1627 u8 reserved_10[0x18]; 1628 u8 error[0x8]; 1629 1630 u8 reserved_11[0x160]; 1631 }; 1632 1633 struct mlx5_ifc_qhll_bits { 1634 u8 reserved_at_0[0x8]; 1635 u8 local_port[0x8]; 1636 u8 reserved_at_10[0x10]; 1637 1638 u8 reserved_at_20[0x1b]; 1639 u8 hll_time[0x5]; 1640 1641 u8 stall_en[0x1]; 1642 u8 reserved_at_41[0x1c]; 1643 u8 stall_cnt[0x3]; 1644 }; 1645 1646 struct mlx5_ifc_qetcr_reg_bits { 1647 u8 operation_type[0x2]; 1648 u8 cap_local_admin[0x1]; 1649 u8 cap_remote_admin[0x1]; 1650 u8 reserved_0[0x4]; 1651 u8 port_number[0x8]; 1652 u8 reserved_1[0x10]; 1653 1654 u8 reserved_2[0x20]; 1655 1656 u8 tc[8][0x40]; 1657 1658 u8 global_configuration[0x40]; 1659 }; 1660 1661 struct mlx5_ifc_nodnic_ring_config_reg_bits { 1662 u8 queue_address_63_32[0x20]; 1663 1664 u8 queue_address_31_12[0x14]; 1665 u8 reserved_0[0x6]; 1666 u8 log_size[0x6]; 1667 1668 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1669 1670 u8 reserved_1[0x8]; 1671 u8 queue_number[0x18]; 1672 1673 u8 q_key[0x20]; 1674 1675 u8 reserved_2[0x10]; 1676 u8 pkey_index[0x10]; 1677 1678 u8 reserved_3[0x40]; 1679 }; 1680 1681 struct mlx5_ifc_nodnic_cq_arming_word_bits { 1682 u8 reserved_0[0x8]; 1683 u8 cq_ci[0x10]; 1684 u8 reserved_1[0x8]; 1685 }; 1686 1687 enum { 1688 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1689 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1690 }; 1691 1692 enum { 1693 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1694 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1695 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1696 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1697 }; 1698 1699 struct mlx5_ifc_nodnic_event_word_bits { 1700 u8 driver_reset_needed[0x1]; 1701 u8 port_management_change_event[0x1]; 1702 u8 reserved_0[0x19]; 1703 u8 link_type[0x1]; 1704 u8 port_state[0x4]; 1705 }; 1706 1707 struct mlx5_ifc_nic_vport_change_event_bits { 1708 u8 reserved_0[0x10]; 1709 u8 vport_num[0x10]; 1710 1711 u8 reserved_1[0xc0]; 1712 }; 1713 1714 struct mlx5_ifc_pages_req_event_bits { 1715 u8 reserved_0[0x10]; 1716 u8 function_id[0x10]; 1717 1718 u8 num_pages[0x20]; 1719 1720 u8 reserved_1[0xa0]; 1721 }; 1722 1723 struct mlx5_ifc_cmd_inter_comp_event_bits { 1724 u8 command_completion_vector[0x20]; 1725 1726 u8 reserved_0[0xc0]; 1727 }; 1728 1729 struct mlx5_ifc_stall_vl_event_bits { 1730 u8 reserved_0[0x18]; 1731 u8 port_num[0x1]; 1732 u8 reserved_1[0x3]; 1733 u8 vl[0x4]; 1734 1735 u8 reserved_2[0xa0]; 1736 }; 1737 1738 struct mlx5_ifc_db_bf_congestion_event_bits { 1739 u8 event_subtype[0x8]; 1740 u8 reserved_0[0x8]; 1741 u8 congestion_level[0x8]; 1742 u8 reserved_1[0x8]; 1743 1744 u8 reserved_2[0xa0]; 1745 }; 1746 1747 struct mlx5_ifc_gpio_event_bits { 1748 u8 reserved_0[0x60]; 1749 1750 u8 gpio_event_hi[0x20]; 1751 1752 u8 gpio_event_lo[0x20]; 1753 1754 u8 reserved_1[0x40]; 1755 }; 1756 1757 struct mlx5_ifc_port_state_change_event_bits { 1758 u8 reserved_0[0x40]; 1759 1760 u8 port_num[0x4]; 1761 u8 reserved_1[0x1c]; 1762 1763 u8 reserved_2[0x80]; 1764 }; 1765 1766 struct mlx5_ifc_dropped_packet_logged_bits { 1767 u8 reserved_0[0xe0]; 1768 }; 1769 1770 enum { 1771 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1772 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1773 }; 1774 1775 struct mlx5_ifc_cq_error_bits { 1776 u8 reserved_0[0x8]; 1777 u8 cqn[0x18]; 1778 1779 u8 reserved_1[0x20]; 1780 1781 u8 reserved_2[0x18]; 1782 u8 syndrome[0x8]; 1783 1784 u8 reserved_3[0x80]; 1785 }; 1786 1787 struct mlx5_ifc_rdma_page_fault_event_bits { 1788 u8 bytes_commited[0x20]; 1789 1790 u8 r_key[0x20]; 1791 1792 u8 reserved_0[0x10]; 1793 u8 packet_len[0x10]; 1794 1795 u8 rdma_op_len[0x20]; 1796 1797 u8 rdma_va[0x40]; 1798 1799 u8 reserved_1[0x5]; 1800 u8 rdma[0x1]; 1801 u8 write[0x1]; 1802 u8 requestor[0x1]; 1803 u8 qp_number[0x18]; 1804 }; 1805 1806 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1807 u8 bytes_committed[0x20]; 1808 1809 u8 reserved_0[0x10]; 1810 u8 wqe_index[0x10]; 1811 1812 u8 reserved_1[0x10]; 1813 u8 len[0x10]; 1814 1815 u8 reserved_2[0x60]; 1816 1817 u8 reserved_3[0x5]; 1818 u8 rdma[0x1]; 1819 u8 write_read[0x1]; 1820 u8 requestor[0x1]; 1821 u8 qpn[0x18]; 1822 }; 1823 1824 enum { 1825 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1826 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1827 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1828 }; 1829 1830 struct mlx5_ifc_qp_events_bits { 1831 u8 reserved_0[0xa0]; 1832 1833 u8 type[0x8]; 1834 u8 reserved_1[0x18]; 1835 1836 u8 reserved_2[0x8]; 1837 u8 qpn_rqn_sqn[0x18]; 1838 }; 1839 1840 struct mlx5_ifc_dct_events_bits { 1841 u8 reserved_0[0xc0]; 1842 1843 u8 reserved_1[0x8]; 1844 u8 dct_number[0x18]; 1845 }; 1846 1847 struct mlx5_ifc_comp_event_bits { 1848 u8 reserved_0[0xc0]; 1849 1850 u8 reserved_1[0x8]; 1851 u8 cq_number[0x18]; 1852 }; 1853 1854 struct mlx5_ifc_fw_version_bits { 1855 u8 major[0x10]; 1856 u8 reserved_0[0x10]; 1857 1858 u8 minor[0x10]; 1859 u8 subminor[0x10]; 1860 1861 u8 second[0x8]; 1862 u8 minute[0x8]; 1863 u8 hour[0x8]; 1864 u8 reserved_1[0x8]; 1865 1866 u8 year[0x10]; 1867 u8 month[0x8]; 1868 u8 day[0x8]; 1869 }; 1870 1871 enum { 1872 MLX5_QPC_STATE_RST = 0x0, 1873 MLX5_QPC_STATE_INIT = 0x1, 1874 MLX5_QPC_STATE_RTR = 0x2, 1875 MLX5_QPC_STATE_RTS = 0x3, 1876 MLX5_QPC_STATE_SQER = 0x4, 1877 MLX5_QPC_STATE_SQD = 0x5, 1878 MLX5_QPC_STATE_ERR = 0x6, 1879 MLX5_QPC_STATE_SUSPENDED = 0x9, 1880 }; 1881 1882 enum { 1883 MLX5_QPC_ST_RC = 0x0, 1884 MLX5_QPC_ST_UC = 0x1, 1885 MLX5_QPC_ST_UD = 0x2, 1886 MLX5_QPC_ST_XRC = 0x3, 1887 MLX5_QPC_ST_DCI = 0x5, 1888 MLX5_QPC_ST_QP0 = 0x7, 1889 MLX5_QPC_ST_QP1 = 0x8, 1890 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1891 MLX5_QPC_ST_REG_UMR = 0xc, 1892 }; 1893 1894 enum { 1895 MLX5_QP_PM_ARMED = 0x0, 1896 MLX5_QP_PM_REARM = 0x1, 1897 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1898 MLX5_QP_PM_MIGRATED = 0x3, 1899 }; 1900 1901 enum { 1902 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1903 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1904 }; 1905 1906 enum { 1907 MLX5_QPC_MTU_256_BYTES = 0x1, 1908 MLX5_QPC_MTU_512_BYTES = 0x2, 1909 MLX5_QPC_MTU_1K_BYTES = 0x3, 1910 MLX5_QPC_MTU_2K_BYTES = 0x4, 1911 MLX5_QPC_MTU_4K_BYTES = 0x5, 1912 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1913 }; 1914 1915 enum { 1916 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1917 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1918 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1919 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1920 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1921 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1922 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1923 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1924 }; 1925 1926 enum { 1927 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1928 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1929 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1930 }; 1931 1932 enum { 1933 MLX5_QPC_CS_RES_DISABLE = 0x0, 1934 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1935 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1936 }; 1937 1938 struct mlx5_ifc_qpc_bits { 1939 u8 state[0x4]; 1940 u8 lag_tx_port_affinity[0x4]; 1941 u8 st[0x8]; 1942 u8 reserved_1[0x3]; 1943 u8 pm_state[0x2]; 1944 u8 reserved_2[0x7]; 1945 u8 end_padding_mode[0x2]; 1946 u8 reserved_3[0x2]; 1947 1948 u8 wq_signature[0x1]; 1949 u8 block_lb_mc[0x1]; 1950 u8 atomic_like_write_en[0x1]; 1951 u8 latency_sensitive[0x1]; 1952 u8 reserved_4[0x1]; 1953 u8 drain_sigerr[0x1]; 1954 u8 reserved_5[0x2]; 1955 u8 pd[0x18]; 1956 1957 u8 mtu[0x3]; 1958 u8 log_msg_max[0x5]; 1959 u8 reserved_6[0x1]; 1960 u8 log_rq_size[0x4]; 1961 u8 log_rq_stride[0x3]; 1962 u8 no_sq[0x1]; 1963 u8 log_sq_size[0x4]; 1964 u8 reserved_7[0x6]; 1965 u8 rlky[0x1]; 1966 u8 ulp_stateless_offload_mode[0x4]; 1967 1968 u8 counter_set_id[0x8]; 1969 u8 uar_page[0x18]; 1970 1971 u8 reserved_8[0x8]; 1972 u8 user_index[0x18]; 1973 1974 u8 reserved_9[0x3]; 1975 u8 log_page_size[0x5]; 1976 u8 remote_qpn[0x18]; 1977 1978 struct mlx5_ifc_ads_bits primary_address_path; 1979 1980 struct mlx5_ifc_ads_bits secondary_address_path; 1981 1982 u8 log_ack_req_freq[0x4]; 1983 u8 reserved_10[0x4]; 1984 u8 log_sra_max[0x3]; 1985 u8 reserved_11[0x2]; 1986 u8 retry_count[0x3]; 1987 u8 rnr_retry[0x3]; 1988 u8 reserved_12[0x1]; 1989 u8 fre[0x1]; 1990 u8 cur_rnr_retry[0x3]; 1991 u8 cur_retry_count[0x3]; 1992 u8 reserved_13[0x5]; 1993 1994 u8 reserved_14[0x20]; 1995 1996 u8 reserved_15[0x8]; 1997 u8 next_send_psn[0x18]; 1998 1999 u8 reserved_16[0x8]; 2000 u8 cqn_snd[0x18]; 2001 2002 u8 reserved_at_400[0x8]; 2003 2004 u8 deth_sqpn[0x18]; 2005 u8 reserved_17[0x20]; 2006 2007 u8 reserved_18[0x8]; 2008 u8 last_acked_psn[0x18]; 2009 2010 u8 reserved_19[0x8]; 2011 u8 ssn[0x18]; 2012 2013 u8 reserved_20[0x8]; 2014 u8 log_rra_max[0x3]; 2015 u8 reserved_21[0x1]; 2016 u8 atomic_mode[0x4]; 2017 u8 rre[0x1]; 2018 u8 rwe[0x1]; 2019 u8 rae[0x1]; 2020 u8 reserved_22[0x1]; 2021 u8 page_offset[0x6]; 2022 u8 reserved_23[0x3]; 2023 u8 cd_slave_receive[0x1]; 2024 u8 cd_slave_send[0x1]; 2025 u8 cd_master[0x1]; 2026 2027 u8 reserved_24[0x3]; 2028 u8 min_rnr_nak[0x5]; 2029 u8 next_rcv_psn[0x18]; 2030 2031 u8 reserved_25[0x8]; 2032 u8 xrcd[0x18]; 2033 2034 u8 reserved_26[0x8]; 2035 u8 cqn_rcv[0x18]; 2036 2037 u8 dbr_addr[0x40]; 2038 2039 u8 q_key[0x20]; 2040 2041 u8 reserved_27[0x5]; 2042 u8 rq_type[0x3]; 2043 u8 srqn_rmpn[0x18]; 2044 2045 u8 reserved_28[0x8]; 2046 u8 rmsn[0x18]; 2047 2048 u8 hw_sq_wqebb_counter[0x10]; 2049 u8 sw_sq_wqebb_counter[0x10]; 2050 2051 u8 hw_rq_counter[0x20]; 2052 2053 u8 sw_rq_counter[0x20]; 2054 2055 u8 reserved_29[0x20]; 2056 2057 u8 reserved_30[0xf]; 2058 u8 cgs[0x1]; 2059 u8 cs_req[0x8]; 2060 u8 cs_res[0x8]; 2061 2062 u8 dc_access_key[0x40]; 2063 2064 u8 rdma_active[0x1]; 2065 u8 comm_est[0x1]; 2066 u8 suspended[0x1]; 2067 u8 reserved_31[0x5]; 2068 u8 send_msg_psn[0x18]; 2069 2070 u8 reserved_32[0x8]; 2071 u8 rcv_msg_psn[0x18]; 2072 2073 u8 rdma_va[0x40]; 2074 2075 u8 rdma_key[0x20]; 2076 2077 u8 reserved_33[0x20]; 2078 }; 2079 2080 struct mlx5_ifc_roce_addr_layout_bits { 2081 u8 source_l3_address[16][0x8]; 2082 2083 u8 reserved_0[0x3]; 2084 u8 vlan_valid[0x1]; 2085 u8 vlan_id[0xc]; 2086 u8 source_mac_47_32[0x10]; 2087 2088 u8 source_mac_31_0[0x20]; 2089 2090 u8 reserved_1[0x14]; 2091 u8 roce_l3_type[0x4]; 2092 u8 roce_version[0x8]; 2093 2094 u8 reserved_2[0x20]; 2095 }; 2096 2097 struct mlx5_ifc_rdbc_bits { 2098 u8 reserved_0[0x1c]; 2099 u8 type[0x4]; 2100 2101 u8 reserved_1[0x20]; 2102 2103 u8 reserved_2[0x8]; 2104 u8 psn[0x18]; 2105 2106 u8 rkey[0x20]; 2107 2108 u8 address[0x40]; 2109 2110 u8 byte_count[0x20]; 2111 2112 u8 reserved_3[0x20]; 2113 2114 u8 atomic_resp[32][0x8]; 2115 }; 2116 2117 enum { 2118 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2119 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2120 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2121 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2122 }; 2123 2124 struct mlx5_ifc_flow_context_bits { 2125 u8 reserved_0[0x20]; 2126 2127 u8 group_id[0x20]; 2128 2129 u8 reserved_1[0x8]; 2130 u8 flow_tag[0x18]; 2131 2132 u8 reserved_2[0x10]; 2133 u8 action[0x10]; 2134 2135 u8 reserved_3[0x8]; 2136 u8 destination_list_size[0x18]; 2137 2138 u8 reserved_4[0x8]; 2139 u8 flow_counter_list_size[0x18]; 2140 2141 u8 reserved_5[0x140]; 2142 2143 struct mlx5_ifc_fte_match_param_bits match_value; 2144 2145 u8 reserved_6[0x600]; 2146 2147 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2148 }; 2149 2150 enum { 2151 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2152 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2153 }; 2154 2155 struct mlx5_ifc_xrc_srqc_bits { 2156 u8 state[0x4]; 2157 u8 log_xrc_srq_size[0x4]; 2158 u8 reserved_0[0x18]; 2159 2160 u8 wq_signature[0x1]; 2161 u8 cont_srq[0x1]; 2162 u8 reserved_1[0x1]; 2163 u8 rlky[0x1]; 2164 u8 basic_cyclic_rcv_wqe[0x1]; 2165 u8 log_rq_stride[0x3]; 2166 u8 xrcd[0x18]; 2167 2168 u8 page_offset[0x6]; 2169 u8 reserved_2[0x2]; 2170 u8 cqn[0x18]; 2171 2172 u8 reserved_3[0x20]; 2173 2174 u8 reserved_4[0x2]; 2175 u8 log_page_size[0x6]; 2176 u8 user_index[0x18]; 2177 2178 u8 reserved_5[0x20]; 2179 2180 u8 reserved_6[0x8]; 2181 u8 pd[0x18]; 2182 2183 u8 lwm[0x10]; 2184 u8 wqe_cnt[0x10]; 2185 2186 u8 reserved_7[0x40]; 2187 2188 u8 db_record_addr_h[0x20]; 2189 2190 u8 db_record_addr_l[0x1e]; 2191 u8 reserved_8[0x2]; 2192 2193 u8 reserved_9[0x80]; 2194 }; 2195 2196 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2197 u8 counter_error_queues[0x20]; 2198 2199 u8 total_error_queues[0x20]; 2200 2201 u8 send_queue_priority_update_flow[0x20]; 2202 2203 u8 reserved_at_60[0x20]; 2204 2205 u8 nic_receive_steering_discard[0x40]; 2206 2207 u8 receive_discard_vport_down[0x40]; 2208 2209 u8 transmit_discard_vport_down[0x40]; 2210 2211 u8 reserved_at_140[0xec0]; 2212 }; 2213 2214 struct mlx5_ifc_traffic_counter_bits { 2215 u8 packets[0x40]; 2216 2217 u8 octets[0x40]; 2218 }; 2219 2220 struct mlx5_ifc_tisc_bits { 2221 u8 strict_lag_tx_port_affinity[0x1]; 2222 u8 reserved_at_1[0x3]; 2223 u8 lag_tx_port_affinity[0x04]; 2224 2225 u8 reserved_at_8[0x4]; 2226 u8 prio[0x4]; 2227 u8 reserved_1[0x10]; 2228 2229 u8 reserved_2[0x100]; 2230 2231 u8 reserved_3[0x8]; 2232 u8 transport_domain[0x18]; 2233 2234 u8 reserved_4[0x8]; 2235 u8 underlay_qpn[0x18]; 2236 2237 u8 reserved_5[0x3a0]; 2238 }; 2239 2240 enum { 2241 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2242 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2243 }; 2244 2245 enum { 2246 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2247 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2248 }; 2249 2250 enum { 2251 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2252 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2253 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2254 }; 2255 2256 enum { 2257 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2258 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2259 }; 2260 2261 struct mlx5_ifc_tirc_bits { 2262 u8 reserved_0[0x20]; 2263 2264 u8 disp_type[0x4]; 2265 u8 reserved_1[0x1c]; 2266 2267 u8 reserved_2[0x40]; 2268 2269 u8 reserved_3[0x4]; 2270 u8 lro_timeout_period_usecs[0x10]; 2271 u8 lro_enable_mask[0x4]; 2272 u8 lro_max_msg_sz[0x8]; 2273 2274 u8 reserved_4[0x40]; 2275 2276 u8 reserved_5[0x8]; 2277 u8 inline_rqn[0x18]; 2278 2279 u8 rx_hash_symmetric[0x1]; 2280 u8 reserved_6[0x1]; 2281 u8 tunneled_offload_en[0x1]; 2282 u8 reserved_7[0x5]; 2283 u8 indirect_table[0x18]; 2284 2285 u8 rx_hash_fn[0x4]; 2286 u8 reserved_8[0x2]; 2287 u8 self_lb_en[0x2]; 2288 u8 transport_domain[0x18]; 2289 2290 u8 rx_hash_toeplitz_key[10][0x20]; 2291 2292 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2293 2294 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2295 2296 u8 reserved_9[0x4c0]; 2297 }; 2298 2299 enum { 2300 MLX5_SRQC_STATE_GOOD = 0x0, 2301 MLX5_SRQC_STATE_ERROR = 0x1, 2302 }; 2303 2304 struct mlx5_ifc_srqc_bits { 2305 u8 state[0x4]; 2306 u8 log_srq_size[0x4]; 2307 u8 reserved_0[0x18]; 2308 2309 u8 wq_signature[0x1]; 2310 u8 cont_srq[0x1]; 2311 u8 reserved_1[0x1]; 2312 u8 rlky[0x1]; 2313 u8 reserved_2[0x1]; 2314 u8 log_rq_stride[0x3]; 2315 u8 xrcd[0x18]; 2316 2317 u8 page_offset[0x6]; 2318 u8 reserved_3[0x2]; 2319 u8 cqn[0x18]; 2320 2321 u8 reserved_4[0x20]; 2322 2323 u8 reserved_5[0x2]; 2324 u8 log_page_size[0x6]; 2325 u8 reserved_6[0x18]; 2326 2327 u8 reserved_7[0x20]; 2328 2329 u8 reserved_8[0x8]; 2330 u8 pd[0x18]; 2331 2332 u8 lwm[0x10]; 2333 u8 wqe_cnt[0x10]; 2334 2335 u8 reserved_9[0x40]; 2336 2337 u8 dbr_addr[0x40]; 2338 2339 u8 reserved_10[0x80]; 2340 }; 2341 2342 enum { 2343 MLX5_SQC_STATE_RST = 0x0, 2344 MLX5_SQC_STATE_RDY = 0x1, 2345 MLX5_SQC_STATE_ERR = 0x3, 2346 }; 2347 2348 struct mlx5_ifc_sqc_bits { 2349 u8 rlkey[0x1]; 2350 u8 cd_master[0x1]; 2351 u8 fre[0x1]; 2352 u8 flush_in_error_en[0x1]; 2353 u8 allow_multi_pkt_send_wqe[0x1]; 2354 u8 min_wqe_inline_mode[0x3]; 2355 u8 state[0x4]; 2356 u8 reg_umr[0x1]; 2357 u8 allow_swp[0x1]; 2358 u8 reserved_0[0x12]; 2359 2360 u8 reserved_1[0x8]; 2361 u8 user_index[0x18]; 2362 2363 u8 reserved_2[0x8]; 2364 u8 cqn[0x18]; 2365 2366 u8 reserved_3[0x80]; 2367 2368 u8 qos_para_vport_number[0x10]; 2369 u8 packet_pacing_rate_limit_index[0x10]; 2370 2371 u8 tis_lst_sz[0x10]; 2372 u8 reserved_4[0x10]; 2373 2374 u8 reserved_5[0x40]; 2375 2376 u8 reserved_6[0x8]; 2377 u8 tis_num_0[0x18]; 2378 2379 struct mlx5_ifc_wq_bits wq; 2380 }; 2381 2382 enum { 2383 MLX5_TSAR_TYPE_DWRR = 0, 2384 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2385 MLX5_TSAR_TYPE_ETS = 2 2386 }; 2387 2388 struct mlx5_ifc_tsar_element_attributes_bits { 2389 u8 reserved_0[0x8]; 2390 u8 tsar_type[0x8]; 2391 u8 reserved_1[0x10]; 2392 }; 2393 2394 struct mlx5_ifc_vport_element_attributes_bits { 2395 u8 reserved_0[0x10]; 2396 u8 vport_number[0x10]; 2397 }; 2398 2399 struct mlx5_ifc_vport_tc_element_attributes_bits { 2400 u8 traffic_class[0x10]; 2401 u8 vport_number[0x10]; 2402 }; 2403 2404 struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2405 u8 reserved_0[0x0C]; 2406 u8 traffic_class[0x04]; 2407 u8 qos_para_vport_number[0x10]; 2408 }; 2409 2410 enum { 2411 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2412 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2413 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2414 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2415 }; 2416 2417 struct mlx5_ifc_scheduling_context_bits { 2418 u8 element_type[0x8]; 2419 u8 reserved_at_8[0x18]; 2420 2421 u8 element_attributes[0x20]; 2422 2423 u8 parent_element_id[0x20]; 2424 2425 u8 reserved_at_60[0x40]; 2426 2427 u8 bw_share[0x20]; 2428 2429 u8 max_average_bw[0x20]; 2430 2431 u8 reserved_at_e0[0x120]; 2432 }; 2433 2434 struct mlx5_ifc_rqtc_bits { 2435 u8 reserved_0[0xa0]; 2436 2437 u8 reserved_1[0x10]; 2438 u8 rqt_max_size[0x10]; 2439 2440 u8 reserved_2[0x10]; 2441 u8 rqt_actual_size[0x10]; 2442 2443 u8 reserved_3[0x6a0]; 2444 2445 struct mlx5_ifc_rq_num_bits rq_num[0]; 2446 }; 2447 2448 enum { 2449 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2450 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2451 }; 2452 2453 enum { 2454 MLX5_RQC_STATE_RST = 0x0, 2455 MLX5_RQC_STATE_RDY = 0x1, 2456 MLX5_RQC_STATE_ERR = 0x3, 2457 }; 2458 2459 enum { 2460 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2461 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2462 }; 2463 2464 struct mlx5_ifc_rqc_bits { 2465 u8 rlkey[0x1]; 2466 u8 delay_drop_en[0x1]; 2467 u8 scatter_fcs[0x1]; 2468 u8 vlan_strip_disable[0x1]; 2469 u8 mem_rq_type[0x4]; 2470 u8 state[0x4]; 2471 u8 reserved_1[0x1]; 2472 u8 flush_in_error_en[0x1]; 2473 u8 reserved_2[0x12]; 2474 2475 u8 reserved_3[0x8]; 2476 u8 user_index[0x18]; 2477 2478 u8 reserved_4[0x8]; 2479 u8 cqn[0x18]; 2480 2481 u8 counter_set_id[0x8]; 2482 u8 reserved_5[0x18]; 2483 2484 u8 reserved_6[0x8]; 2485 u8 rmpn[0x18]; 2486 2487 u8 reserved_7[0xe0]; 2488 2489 struct mlx5_ifc_wq_bits wq; 2490 }; 2491 2492 enum { 2493 MLX5_RMPC_STATE_RDY = 0x1, 2494 MLX5_RMPC_STATE_ERR = 0x3, 2495 }; 2496 2497 struct mlx5_ifc_rmpc_bits { 2498 u8 reserved_0[0x8]; 2499 u8 state[0x4]; 2500 u8 reserved_1[0x14]; 2501 2502 u8 basic_cyclic_rcv_wqe[0x1]; 2503 u8 reserved_2[0x1f]; 2504 2505 u8 reserved_3[0x140]; 2506 2507 struct mlx5_ifc_wq_bits wq; 2508 }; 2509 2510 enum { 2511 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2512 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2513 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2514 }; 2515 2516 struct mlx5_ifc_nic_vport_context_bits { 2517 u8 reserved_0[0x5]; 2518 u8 min_wqe_inline_mode[0x3]; 2519 u8 reserved_1[0x15]; 2520 u8 disable_mc_local_lb[0x1]; 2521 u8 disable_uc_local_lb[0x1]; 2522 u8 roce_en[0x1]; 2523 2524 u8 arm_change_event[0x1]; 2525 u8 reserved_2[0x1a]; 2526 u8 event_on_mtu[0x1]; 2527 u8 event_on_promisc_change[0x1]; 2528 u8 event_on_vlan_change[0x1]; 2529 u8 event_on_mc_address_change[0x1]; 2530 u8 event_on_uc_address_change[0x1]; 2531 2532 u8 reserved_3[0xe0]; 2533 2534 u8 reserved_4[0x10]; 2535 u8 mtu[0x10]; 2536 2537 u8 system_image_guid[0x40]; 2538 2539 u8 port_guid[0x40]; 2540 2541 u8 node_guid[0x40]; 2542 2543 u8 reserved_5[0x140]; 2544 2545 u8 qkey_violation_counter[0x10]; 2546 u8 reserved_6[0x10]; 2547 2548 u8 reserved_7[0x420]; 2549 2550 u8 promisc_uc[0x1]; 2551 u8 promisc_mc[0x1]; 2552 u8 promisc_all[0x1]; 2553 u8 reserved_8[0x2]; 2554 u8 allowed_list_type[0x3]; 2555 u8 reserved_9[0xc]; 2556 u8 allowed_list_size[0xc]; 2557 2558 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2559 2560 u8 reserved_10[0x20]; 2561 2562 u8 current_uc_mac_address[0][0x40]; 2563 }; 2564 2565 enum { 2566 MLX5_ACCESS_MODE_PA = 0x0, 2567 MLX5_ACCESS_MODE_MTT = 0x1, 2568 MLX5_ACCESS_MODE_KLM = 0x2, 2569 }; 2570 2571 struct mlx5_ifc_mkc_bits { 2572 u8 reserved_at_0[0x1]; 2573 u8 free[0x1]; 2574 u8 reserved_at_2[0x1]; 2575 u8 access_mode_4_2[0x3]; 2576 u8 reserved_at_6[0x7]; 2577 u8 relaxed_ordering_write[0x1]; 2578 u8 reserved_at_e[0x1]; 2579 u8 small_fence_on_rdma_read_response[0x1]; 2580 u8 umr_en[0x1]; 2581 u8 a[0x1]; 2582 u8 rw[0x1]; 2583 u8 rr[0x1]; 2584 u8 lw[0x1]; 2585 u8 lr[0x1]; 2586 u8 access_mode[0x2]; 2587 u8 reserved_2[0x8]; 2588 2589 u8 qpn[0x18]; 2590 u8 mkey_7_0[0x8]; 2591 2592 u8 reserved_3[0x20]; 2593 2594 u8 length64[0x1]; 2595 u8 bsf_en[0x1]; 2596 u8 sync_umr[0x1]; 2597 u8 reserved_4[0x2]; 2598 u8 expected_sigerr_count[0x1]; 2599 u8 reserved_5[0x1]; 2600 u8 en_rinval[0x1]; 2601 u8 pd[0x18]; 2602 2603 u8 start_addr[0x40]; 2604 2605 u8 len[0x40]; 2606 2607 u8 bsf_octword_size[0x20]; 2608 2609 u8 reserved_6[0x80]; 2610 2611 u8 translations_octword_size[0x20]; 2612 2613 u8 reserved_7[0x1b]; 2614 u8 log_page_size[0x5]; 2615 2616 u8 reserved_8[0x20]; 2617 }; 2618 2619 struct mlx5_ifc_pkey_bits { 2620 u8 reserved_0[0x10]; 2621 u8 pkey[0x10]; 2622 }; 2623 2624 struct mlx5_ifc_array128_auto_bits { 2625 u8 array128_auto[16][0x8]; 2626 }; 2627 2628 enum { 2629 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2630 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2631 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2632 }; 2633 2634 enum { 2635 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2636 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2637 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2638 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2639 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2640 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2641 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2642 }; 2643 2644 enum { 2645 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2646 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2647 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2648 }; 2649 2650 enum { 2651 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2652 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2653 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2654 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2655 }; 2656 2657 enum { 2658 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2659 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2660 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2661 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2662 }; 2663 2664 struct mlx5_ifc_hca_vport_context_bits { 2665 u8 field_select[0x20]; 2666 2667 u8 reserved_0[0xe0]; 2668 2669 u8 sm_virt_aware[0x1]; 2670 u8 has_smi[0x1]; 2671 u8 has_raw[0x1]; 2672 u8 grh_required[0x1]; 2673 u8 reserved_1[0x1]; 2674 u8 min_wqe_inline_mode[0x3]; 2675 u8 reserved_2[0x8]; 2676 u8 port_physical_state[0x4]; 2677 u8 vport_state_policy[0x4]; 2678 u8 port_state[0x4]; 2679 u8 vport_state[0x4]; 2680 2681 u8 reserved_3[0x20]; 2682 2683 u8 system_image_guid[0x40]; 2684 2685 u8 port_guid[0x40]; 2686 2687 u8 node_guid[0x40]; 2688 2689 u8 cap_mask1[0x20]; 2690 2691 u8 cap_mask1_field_select[0x20]; 2692 2693 u8 cap_mask2[0x20]; 2694 2695 u8 cap_mask2_field_select[0x20]; 2696 2697 u8 reserved_4[0x80]; 2698 2699 u8 lid[0x10]; 2700 u8 reserved_5[0x4]; 2701 u8 init_type_reply[0x4]; 2702 u8 lmc[0x3]; 2703 u8 subnet_timeout[0x5]; 2704 2705 u8 sm_lid[0x10]; 2706 u8 sm_sl[0x4]; 2707 u8 reserved_6[0xc]; 2708 2709 u8 qkey_violation_counter[0x10]; 2710 u8 pkey_violation_counter[0x10]; 2711 2712 u8 reserved_7[0xca0]; 2713 }; 2714 2715 union mlx5_ifc_hca_cap_union_bits { 2716 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2717 struct mlx5_ifc_odp_cap_bits odp_cap; 2718 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2719 struct mlx5_ifc_roce_cap_bits roce_cap; 2720 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2721 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2722 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2723 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2724 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2725 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2726 struct mlx5_ifc_qos_cap_bits qos_cap; 2727 u8 reserved_0[0x8000]; 2728 }; 2729 2730 enum { 2731 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 2732 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 2733 }; 2734 2735 struct mlx5_ifc_flow_table_context_bits { 2736 u8 encap_en[0x1]; 2737 u8 decap_en[0x1]; 2738 u8 reserved_at_2[0x2]; 2739 u8 table_miss_action[0x4]; 2740 u8 level[0x8]; 2741 u8 reserved_at_10[0x8]; 2742 u8 log_size[0x8]; 2743 2744 u8 reserved_at_20[0x8]; 2745 u8 table_miss_id[0x18]; 2746 2747 u8 reserved_at_40[0x8]; 2748 u8 lag_master_next_table_id[0x18]; 2749 2750 u8 reserved_at_60[0xe0]; 2751 }; 2752 2753 struct mlx5_ifc_esw_vport_context_bits { 2754 u8 reserved_0[0x3]; 2755 u8 vport_svlan_strip[0x1]; 2756 u8 vport_cvlan_strip[0x1]; 2757 u8 vport_svlan_insert[0x1]; 2758 u8 vport_cvlan_insert[0x2]; 2759 u8 reserved_1[0x18]; 2760 2761 u8 reserved_2[0x20]; 2762 2763 u8 svlan_cfi[0x1]; 2764 u8 svlan_pcp[0x3]; 2765 u8 svlan_id[0xc]; 2766 u8 cvlan_cfi[0x1]; 2767 u8 cvlan_pcp[0x3]; 2768 u8 cvlan_id[0xc]; 2769 2770 u8 reserved_3[0x7a0]; 2771 }; 2772 2773 enum { 2774 MLX5_EQC_STATUS_OK = 0x0, 2775 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2776 }; 2777 2778 enum { 2779 MLX5_EQ_STATE_ARMED = 0x9, 2780 MLX5_EQ_STATE_FIRED = 0xa, 2781 }; 2782 2783 struct mlx5_ifc_eqc_bits { 2784 u8 status[0x4]; 2785 u8 reserved_0[0x9]; 2786 u8 ec[0x1]; 2787 u8 oi[0x1]; 2788 u8 reserved_1[0x5]; 2789 u8 st[0x4]; 2790 u8 reserved_2[0x8]; 2791 2792 u8 reserved_3[0x20]; 2793 2794 u8 reserved_4[0x14]; 2795 u8 page_offset[0x6]; 2796 u8 reserved_5[0x6]; 2797 2798 u8 reserved_6[0x3]; 2799 u8 log_eq_size[0x5]; 2800 u8 uar_page[0x18]; 2801 2802 u8 reserved_7[0x20]; 2803 2804 u8 reserved_8[0x18]; 2805 u8 intr[0x8]; 2806 2807 u8 reserved_9[0x3]; 2808 u8 log_page_size[0x5]; 2809 u8 reserved_10[0x18]; 2810 2811 u8 reserved_11[0x60]; 2812 2813 u8 reserved_12[0x8]; 2814 u8 consumer_counter[0x18]; 2815 2816 u8 reserved_13[0x8]; 2817 u8 producer_counter[0x18]; 2818 2819 u8 reserved_14[0x80]; 2820 }; 2821 2822 enum { 2823 MLX5_DCTC_STATE_ACTIVE = 0x0, 2824 MLX5_DCTC_STATE_DRAINING = 0x1, 2825 MLX5_DCTC_STATE_DRAINED = 0x2, 2826 }; 2827 2828 enum { 2829 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2830 MLX5_DCTC_CS_RES_NA = 0x1, 2831 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2832 }; 2833 2834 enum { 2835 MLX5_DCTC_MTU_256_BYTES = 0x1, 2836 MLX5_DCTC_MTU_512_BYTES = 0x2, 2837 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2838 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2839 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2840 }; 2841 2842 struct mlx5_ifc_dctc_bits { 2843 u8 reserved_0[0x4]; 2844 u8 state[0x4]; 2845 u8 reserved_1[0x18]; 2846 2847 u8 reserved_2[0x8]; 2848 u8 user_index[0x18]; 2849 2850 u8 reserved_3[0x8]; 2851 u8 cqn[0x18]; 2852 2853 u8 counter_set_id[0x8]; 2854 u8 atomic_mode[0x4]; 2855 u8 rre[0x1]; 2856 u8 rwe[0x1]; 2857 u8 rae[0x1]; 2858 u8 atomic_like_write_en[0x1]; 2859 u8 latency_sensitive[0x1]; 2860 u8 rlky[0x1]; 2861 u8 reserved_4[0xe]; 2862 2863 u8 reserved_5[0x8]; 2864 u8 cs_res[0x8]; 2865 u8 reserved_6[0x3]; 2866 u8 min_rnr_nak[0x5]; 2867 u8 reserved_7[0x8]; 2868 2869 u8 reserved_8[0x8]; 2870 u8 srqn[0x18]; 2871 2872 u8 reserved_9[0x8]; 2873 u8 pd[0x18]; 2874 2875 u8 tclass[0x8]; 2876 u8 reserved_10[0x4]; 2877 u8 flow_label[0x14]; 2878 2879 u8 dc_access_key[0x40]; 2880 2881 u8 reserved_11[0x5]; 2882 u8 mtu[0x3]; 2883 u8 port[0x8]; 2884 u8 pkey_index[0x10]; 2885 2886 u8 reserved_12[0x8]; 2887 u8 my_addr_index[0x8]; 2888 u8 reserved_13[0x8]; 2889 u8 hop_limit[0x8]; 2890 2891 u8 dc_access_key_violation_count[0x20]; 2892 2893 u8 reserved_14[0x14]; 2894 u8 dei_cfi[0x1]; 2895 u8 eth_prio[0x3]; 2896 u8 ecn[0x2]; 2897 u8 dscp[0x6]; 2898 2899 u8 reserved_15[0x40]; 2900 }; 2901 2902 enum { 2903 MLX5_CQC_STATUS_OK = 0x0, 2904 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2905 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2906 }; 2907 2908 enum { 2909 CQE_SIZE_64 = 0x0, 2910 CQE_SIZE_128 = 0x1, 2911 }; 2912 2913 enum { 2914 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2915 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2916 }; 2917 2918 enum { 2919 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 2920 MLX5_CQ_STATE_ARMED = 0x9, 2921 MLX5_CQ_STATE_FIRED = 0xa, 2922 }; 2923 2924 struct mlx5_ifc_cqc_bits { 2925 u8 status[0x4]; 2926 u8 reserved_0[0x4]; 2927 u8 cqe_sz[0x3]; 2928 u8 cc[0x1]; 2929 u8 reserved_1[0x1]; 2930 u8 scqe_break_moderation_en[0x1]; 2931 u8 oi[0x1]; 2932 u8 cq_period_mode[0x2]; 2933 u8 cqe_compression_en[0x1]; 2934 u8 mini_cqe_res_format[0x2]; 2935 u8 st[0x4]; 2936 u8 reserved_2[0x8]; 2937 2938 u8 reserved_3[0x20]; 2939 2940 u8 reserved_4[0x14]; 2941 u8 page_offset[0x6]; 2942 u8 reserved_5[0x6]; 2943 2944 u8 reserved_6[0x3]; 2945 u8 log_cq_size[0x5]; 2946 u8 uar_page[0x18]; 2947 2948 u8 reserved_7[0x4]; 2949 u8 cq_period[0xc]; 2950 u8 cq_max_count[0x10]; 2951 2952 u8 reserved_8[0x18]; 2953 u8 c_eqn[0x8]; 2954 2955 u8 reserved_9[0x3]; 2956 u8 log_page_size[0x5]; 2957 u8 reserved_10[0x18]; 2958 2959 u8 reserved_11[0x20]; 2960 2961 u8 reserved_12[0x8]; 2962 u8 last_notified_index[0x18]; 2963 2964 u8 reserved_13[0x8]; 2965 u8 last_solicit_index[0x18]; 2966 2967 u8 reserved_14[0x8]; 2968 u8 consumer_counter[0x18]; 2969 2970 u8 reserved_15[0x8]; 2971 u8 producer_counter[0x18]; 2972 2973 u8 reserved_16[0x40]; 2974 2975 u8 dbr_addr[0x40]; 2976 }; 2977 2978 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2979 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2980 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2981 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2982 u8 reserved_0[0x800]; 2983 }; 2984 2985 struct mlx5_ifc_query_adapter_param_block_bits { 2986 u8 reserved_0[0xc0]; 2987 2988 u8 reserved_1[0x8]; 2989 u8 ieee_vendor_id[0x18]; 2990 2991 u8 reserved_2[0x10]; 2992 u8 vsd_vendor_id[0x10]; 2993 2994 u8 vsd[208][0x8]; 2995 2996 u8 vsd_contd_psid[16][0x8]; 2997 }; 2998 2999 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3000 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3001 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3002 u8 reserved_0[0x20]; 3003 }; 3004 3005 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3006 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3007 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3008 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3009 u8 reserved_0[0x20]; 3010 }; 3011 3012 struct mlx5_ifc_bufferx_reg_bits { 3013 u8 reserved_0[0x6]; 3014 u8 lossy[0x1]; 3015 u8 epsb[0x1]; 3016 u8 reserved_1[0xc]; 3017 u8 size[0xc]; 3018 3019 u8 xoff_threshold[0x10]; 3020 u8 xon_threshold[0x10]; 3021 }; 3022 3023 struct mlx5_ifc_config_item_bits { 3024 u8 valid[0x2]; 3025 u8 reserved_0[0x2]; 3026 u8 header_type[0x2]; 3027 u8 reserved_1[0x2]; 3028 u8 default_location[0x1]; 3029 u8 reserved_2[0x7]; 3030 u8 version[0x4]; 3031 u8 reserved_3[0x3]; 3032 u8 length[0x9]; 3033 3034 u8 type[0x20]; 3035 3036 u8 reserved_4[0x10]; 3037 u8 crc16[0x10]; 3038 }; 3039 3040 struct mlx5_ifc_nodnic_port_config_reg_bits { 3041 struct mlx5_ifc_nodnic_event_word_bits event; 3042 3043 u8 network_en[0x1]; 3044 u8 dma_en[0x1]; 3045 u8 promisc_en[0x1]; 3046 u8 promisc_multicast_en[0x1]; 3047 u8 reserved_0[0x17]; 3048 u8 receive_filter_en[0x5]; 3049 3050 u8 reserved_1[0x10]; 3051 u8 mac_47_32[0x10]; 3052 3053 u8 mac_31_0[0x20]; 3054 3055 u8 receive_filters_mgid_mac[64][0x8]; 3056 3057 u8 gid[16][0x8]; 3058 3059 u8 reserved_2[0x10]; 3060 u8 lid[0x10]; 3061 3062 u8 reserved_3[0xc]; 3063 u8 sm_sl[0x4]; 3064 u8 sm_lid[0x10]; 3065 3066 u8 completion_address_63_32[0x20]; 3067 3068 u8 completion_address_31_12[0x14]; 3069 u8 reserved_4[0x6]; 3070 u8 log_cq_size[0x6]; 3071 3072 u8 working_buffer_address_63_32[0x20]; 3073 3074 u8 working_buffer_address_31_12[0x14]; 3075 u8 reserved_5[0xc]; 3076 3077 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 3078 3079 u8 pkey_index[0x10]; 3080 u8 pkey[0x10]; 3081 3082 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 3083 3084 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 3085 3086 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 3087 3088 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 3089 3090 u8 reserved_6[0x400]; 3091 }; 3092 3093 union mlx5_ifc_event_auto_bits { 3094 struct mlx5_ifc_comp_event_bits comp_event; 3095 struct mlx5_ifc_dct_events_bits dct_events; 3096 struct mlx5_ifc_qp_events_bits qp_events; 3097 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3098 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3099 struct mlx5_ifc_cq_error_bits cq_error; 3100 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3101 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3102 struct mlx5_ifc_gpio_event_bits gpio_event; 3103 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3104 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3105 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3106 struct mlx5_ifc_pages_req_event_bits pages_req_event; 3107 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 3108 u8 reserved_0[0xe0]; 3109 }; 3110 3111 struct mlx5_ifc_health_buffer_bits { 3112 u8 reserved_0[0x100]; 3113 3114 u8 assert_existptr[0x20]; 3115 3116 u8 assert_callra[0x20]; 3117 3118 u8 reserved_1[0x40]; 3119 3120 u8 fw_version[0x20]; 3121 3122 u8 hw_id[0x20]; 3123 3124 u8 reserved_2[0x20]; 3125 3126 u8 irisc_index[0x8]; 3127 u8 synd[0x8]; 3128 u8 ext_synd[0x10]; 3129 }; 3130 3131 struct mlx5_ifc_register_loopback_control_bits { 3132 u8 no_lb[0x1]; 3133 u8 reserved_0[0x7]; 3134 u8 port[0x8]; 3135 u8 reserved_1[0x10]; 3136 3137 u8 reserved_2[0x60]; 3138 }; 3139 3140 struct mlx5_ifc_lrh_bits { 3141 u8 vl[4]; 3142 u8 lver[4]; 3143 u8 sl[4]; 3144 u8 reserved2[2]; 3145 u8 lnh[2]; 3146 u8 dlid[16]; 3147 u8 reserved5[5]; 3148 u8 pkt_len[11]; 3149 u8 slid[16]; 3150 }; 3151 3152 struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3153 u8 reserved_0[0x40]; 3154 3155 u8 reserved_1[0x10]; 3156 u8 rol_mode[0x8]; 3157 u8 wol_mode[0x8]; 3158 }; 3159 3160 struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3161 u8 reserved_0[0x40]; 3162 3163 u8 rol_mode_valid[0x1]; 3164 u8 wol_mode_valid[0x1]; 3165 u8 reserved_1[0xe]; 3166 u8 rol_mode[0x8]; 3167 u8 wol_mode[0x8]; 3168 3169 u8 reserved_2[0x7a0]; 3170 }; 3171 3172 struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3173 u8 virtual_mac_en[0x1]; 3174 u8 mac_aux_v[0x1]; 3175 u8 reserved_0[0x1e]; 3176 3177 u8 reserved_1[0x40]; 3178 3179 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3180 3181 u8 reserved_2[0x760]; 3182 }; 3183 3184 struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3185 u8 virtual_mac_en[0x1]; 3186 u8 mac_aux_v[0x1]; 3187 u8 reserved_0[0x1e]; 3188 3189 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3190 3191 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3192 3193 u8 reserved_1[0x760]; 3194 }; 3195 3196 struct mlx5_ifc_icmd_query_fw_info_out_bits { 3197 struct mlx5_ifc_fw_version_bits fw_version; 3198 3199 u8 reserved_0[0x10]; 3200 u8 hash_signature[0x10]; 3201 3202 u8 psid[16][0x8]; 3203 3204 u8 reserved_1[0x6e0]; 3205 }; 3206 3207 struct mlx5_ifc_icmd_query_cap_in_bits { 3208 u8 reserved_0[0x10]; 3209 u8 capability_group[0x10]; 3210 }; 3211 3212 struct mlx5_ifc_icmd_query_cap_general_bits { 3213 u8 nv_access[0x1]; 3214 u8 fw_info_psid[0x1]; 3215 u8 reserved_0[0x1e]; 3216 3217 u8 reserved_1[0x16]; 3218 u8 rol_s[0x1]; 3219 u8 rol_g[0x1]; 3220 u8 reserved_2[0x1]; 3221 u8 wol_s[0x1]; 3222 u8 wol_g[0x1]; 3223 u8 wol_a[0x1]; 3224 u8 wol_b[0x1]; 3225 u8 wol_m[0x1]; 3226 u8 wol_u[0x1]; 3227 u8 wol_p[0x1]; 3228 }; 3229 3230 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3231 u8 status[0x8]; 3232 u8 reserved_0[0x18]; 3233 3234 u8 reserved_1[0x7e0]; 3235 }; 3236 3237 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3238 u8 status[0x8]; 3239 u8 reserved_0[0x18]; 3240 3241 u8 reserved_1[0x7e0]; 3242 }; 3243 3244 struct mlx5_ifc_icmd_ocbb_init_in_bits { 3245 u8 address_hi[0x20]; 3246 3247 u8 address_lo[0x20]; 3248 3249 u8 reserved_0[0x7c0]; 3250 }; 3251 3252 struct mlx5_ifc_icmd_init_ocsd_in_bits { 3253 u8 reserved_0[0x20]; 3254 3255 u8 address_hi[0x20]; 3256 3257 u8 address_lo[0x20]; 3258 3259 u8 reserved_1[0x7a0]; 3260 }; 3261 3262 struct mlx5_ifc_icmd_access_reg_out_bits { 3263 u8 reserved_0[0x11]; 3264 u8 status[0x7]; 3265 u8 reserved_1[0x8]; 3266 3267 u8 register_id[0x10]; 3268 u8 reserved_2[0x10]; 3269 3270 u8 reserved_3[0x40]; 3271 3272 u8 reserved_4[0x5]; 3273 u8 len[0xb]; 3274 u8 reserved_5[0x10]; 3275 3276 u8 register_data[0][0x20]; 3277 }; 3278 3279 enum { 3280 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3281 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3282 }; 3283 3284 struct mlx5_ifc_icmd_access_reg_in_bits { 3285 u8 constant_1[0x5]; 3286 u8 constant_2[0xb]; 3287 u8 reserved_0[0x10]; 3288 3289 u8 register_id[0x10]; 3290 u8 reserved_1[0x1]; 3291 u8 method[0x7]; 3292 u8 constant_3[0x8]; 3293 3294 u8 reserved_2[0x40]; 3295 3296 u8 constant_4[0x5]; 3297 u8 len[0xb]; 3298 u8 reserved_3[0x10]; 3299 3300 u8 register_data[0][0x20]; 3301 }; 3302 3303 enum { 3304 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3305 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3306 }; 3307 3308 struct mlx5_ifc_teardown_hca_out_bits { 3309 u8 status[0x8]; 3310 u8 reserved_0[0x18]; 3311 3312 u8 syndrome[0x20]; 3313 3314 u8 reserved_1[0x3f]; 3315 3316 u8 state[0x1]; 3317 }; 3318 3319 enum { 3320 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3321 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3322 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3323 }; 3324 3325 struct mlx5_ifc_teardown_hca_in_bits { 3326 u8 opcode[0x10]; 3327 u8 reserved_0[0x10]; 3328 3329 u8 reserved_1[0x10]; 3330 u8 op_mod[0x10]; 3331 3332 u8 reserved_2[0x10]; 3333 u8 profile[0x10]; 3334 3335 u8 reserved_3[0x20]; 3336 }; 3337 3338 struct mlx5_ifc_set_delay_drop_params_out_bits { 3339 u8 status[0x8]; 3340 u8 reserved_at_8[0x18]; 3341 3342 u8 syndrome[0x20]; 3343 3344 u8 reserved_at_40[0x40]; 3345 }; 3346 3347 struct mlx5_ifc_set_delay_drop_params_in_bits { 3348 u8 opcode[0x10]; 3349 u8 reserved_at_10[0x10]; 3350 3351 u8 reserved_at_20[0x10]; 3352 u8 op_mod[0x10]; 3353 3354 u8 reserved_at_40[0x20]; 3355 3356 u8 reserved_at_60[0x10]; 3357 u8 delay_drop_timeout[0x10]; 3358 }; 3359 3360 struct mlx5_ifc_query_delay_drop_params_out_bits { 3361 u8 status[0x8]; 3362 u8 reserved_at_8[0x18]; 3363 3364 u8 syndrome[0x20]; 3365 3366 u8 reserved_at_40[0x20]; 3367 3368 u8 reserved_at_60[0x10]; 3369 u8 delay_drop_timeout[0x10]; 3370 }; 3371 3372 struct mlx5_ifc_query_delay_drop_params_in_bits { 3373 u8 opcode[0x10]; 3374 u8 reserved_at_10[0x10]; 3375 3376 u8 reserved_at_20[0x10]; 3377 u8 op_mod[0x10]; 3378 3379 u8 reserved_at_40[0x40]; 3380 }; 3381 3382 struct mlx5_ifc_suspend_qp_out_bits { 3383 u8 status[0x8]; 3384 u8 reserved_0[0x18]; 3385 3386 u8 syndrome[0x20]; 3387 3388 u8 reserved_1[0x40]; 3389 }; 3390 3391 struct mlx5_ifc_suspend_qp_in_bits { 3392 u8 opcode[0x10]; 3393 u8 reserved_0[0x10]; 3394 3395 u8 reserved_1[0x10]; 3396 u8 op_mod[0x10]; 3397 3398 u8 reserved_2[0x8]; 3399 u8 qpn[0x18]; 3400 3401 u8 reserved_3[0x20]; 3402 }; 3403 3404 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3405 u8 status[0x8]; 3406 u8 reserved_0[0x18]; 3407 3408 u8 syndrome[0x20]; 3409 3410 u8 reserved_1[0x40]; 3411 }; 3412 3413 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3414 u8 opcode[0x10]; 3415 u8 reserved_0[0x10]; 3416 3417 u8 reserved_1[0x10]; 3418 u8 op_mod[0x10]; 3419 3420 u8 reserved_2[0x8]; 3421 u8 qpn[0x18]; 3422 3423 u8 reserved_3[0x20]; 3424 3425 u8 opt_param_mask[0x20]; 3426 3427 u8 reserved_4[0x20]; 3428 3429 struct mlx5_ifc_qpc_bits qpc; 3430 3431 u8 reserved_5[0x80]; 3432 }; 3433 3434 struct mlx5_ifc_sqd2rts_qp_out_bits { 3435 u8 status[0x8]; 3436 u8 reserved_0[0x18]; 3437 3438 u8 syndrome[0x20]; 3439 3440 u8 reserved_1[0x40]; 3441 }; 3442 3443 struct mlx5_ifc_sqd2rts_qp_in_bits { 3444 u8 opcode[0x10]; 3445 u8 reserved_0[0x10]; 3446 3447 u8 reserved_1[0x10]; 3448 u8 op_mod[0x10]; 3449 3450 u8 reserved_2[0x8]; 3451 u8 qpn[0x18]; 3452 3453 u8 reserved_3[0x20]; 3454 3455 u8 opt_param_mask[0x20]; 3456 3457 u8 reserved_4[0x20]; 3458 3459 struct mlx5_ifc_qpc_bits qpc; 3460 3461 u8 reserved_5[0x80]; 3462 }; 3463 3464 struct mlx5_ifc_set_wol_rol_out_bits { 3465 u8 status[0x8]; 3466 u8 reserved_0[0x18]; 3467 3468 u8 syndrome[0x20]; 3469 3470 u8 reserved_1[0x40]; 3471 }; 3472 3473 struct mlx5_ifc_set_wol_rol_in_bits { 3474 u8 opcode[0x10]; 3475 u8 reserved_0[0x10]; 3476 3477 u8 reserved_1[0x10]; 3478 u8 op_mod[0x10]; 3479 3480 u8 rol_mode_valid[0x1]; 3481 u8 wol_mode_valid[0x1]; 3482 u8 reserved_2[0xe]; 3483 u8 rol_mode[0x8]; 3484 u8 wol_mode[0x8]; 3485 3486 u8 reserved_3[0x20]; 3487 }; 3488 3489 struct mlx5_ifc_set_roce_address_out_bits { 3490 u8 status[0x8]; 3491 u8 reserved_0[0x18]; 3492 3493 u8 syndrome[0x20]; 3494 3495 u8 reserved_1[0x40]; 3496 }; 3497 3498 struct mlx5_ifc_set_roce_address_in_bits { 3499 u8 opcode[0x10]; 3500 u8 reserved_0[0x10]; 3501 3502 u8 reserved_1[0x10]; 3503 u8 op_mod[0x10]; 3504 3505 u8 roce_address_index[0x10]; 3506 u8 reserved_2[0x10]; 3507 3508 u8 reserved_3[0x20]; 3509 3510 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3511 }; 3512 3513 struct mlx5_ifc_set_rdb_out_bits { 3514 u8 status[0x8]; 3515 u8 reserved_0[0x18]; 3516 3517 u8 syndrome[0x20]; 3518 3519 u8 reserved_1[0x40]; 3520 }; 3521 3522 struct mlx5_ifc_set_rdb_in_bits { 3523 u8 opcode[0x10]; 3524 u8 reserved_0[0x10]; 3525 3526 u8 reserved_1[0x10]; 3527 u8 op_mod[0x10]; 3528 3529 u8 reserved_2[0x8]; 3530 u8 qpn[0x18]; 3531 3532 u8 reserved_3[0x18]; 3533 u8 rdb_list_size[0x8]; 3534 3535 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3536 }; 3537 3538 struct mlx5_ifc_set_mad_demux_out_bits { 3539 u8 status[0x8]; 3540 u8 reserved_0[0x18]; 3541 3542 u8 syndrome[0x20]; 3543 3544 u8 reserved_1[0x40]; 3545 }; 3546 3547 enum { 3548 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3549 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3550 }; 3551 3552 struct mlx5_ifc_set_mad_demux_in_bits { 3553 u8 opcode[0x10]; 3554 u8 reserved_0[0x10]; 3555 3556 u8 reserved_1[0x10]; 3557 u8 op_mod[0x10]; 3558 3559 u8 reserved_2[0x20]; 3560 3561 u8 reserved_3[0x6]; 3562 u8 demux_mode[0x2]; 3563 u8 reserved_4[0x18]; 3564 }; 3565 3566 struct mlx5_ifc_set_l2_table_entry_out_bits { 3567 u8 status[0x8]; 3568 u8 reserved_0[0x18]; 3569 3570 u8 syndrome[0x20]; 3571 3572 u8 reserved_1[0x40]; 3573 }; 3574 3575 struct mlx5_ifc_set_l2_table_entry_in_bits { 3576 u8 opcode[0x10]; 3577 u8 reserved_0[0x10]; 3578 3579 u8 reserved_1[0x10]; 3580 u8 op_mod[0x10]; 3581 3582 u8 reserved_2[0x60]; 3583 3584 u8 reserved_3[0x8]; 3585 u8 table_index[0x18]; 3586 3587 u8 reserved_4[0x20]; 3588 3589 u8 reserved_5[0x13]; 3590 u8 vlan_valid[0x1]; 3591 u8 vlan[0xc]; 3592 3593 struct mlx5_ifc_mac_address_layout_bits mac_address; 3594 3595 u8 reserved_6[0xc0]; 3596 }; 3597 3598 struct mlx5_ifc_set_issi_out_bits { 3599 u8 status[0x8]; 3600 u8 reserved_0[0x18]; 3601 3602 u8 syndrome[0x20]; 3603 3604 u8 reserved_1[0x40]; 3605 }; 3606 3607 struct mlx5_ifc_set_issi_in_bits { 3608 u8 opcode[0x10]; 3609 u8 reserved_0[0x10]; 3610 3611 u8 reserved_1[0x10]; 3612 u8 op_mod[0x10]; 3613 3614 u8 reserved_2[0x10]; 3615 u8 current_issi[0x10]; 3616 3617 u8 reserved_3[0x20]; 3618 }; 3619 3620 struct mlx5_ifc_set_hca_cap_out_bits { 3621 u8 status[0x8]; 3622 u8 reserved_0[0x18]; 3623 3624 u8 syndrome[0x20]; 3625 3626 u8 reserved_1[0x40]; 3627 }; 3628 3629 struct mlx5_ifc_set_hca_cap_in_bits { 3630 u8 opcode[0x10]; 3631 u8 reserved_0[0x10]; 3632 3633 u8 reserved_1[0x10]; 3634 u8 op_mod[0x10]; 3635 3636 u8 reserved_2[0x40]; 3637 3638 union mlx5_ifc_hca_cap_union_bits capability; 3639 }; 3640 3641 enum { 3642 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3643 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3644 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3645 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3646 }; 3647 3648 struct mlx5_ifc_set_flow_table_root_out_bits { 3649 u8 status[0x8]; 3650 u8 reserved_0[0x18]; 3651 3652 u8 syndrome[0x20]; 3653 3654 u8 reserved_1[0x40]; 3655 }; 3656 3657 struct mlx5_ifc_set_flow_table_root_in_bits { 3658 u8 opcode[0x10]; 3659 u8 reserved_0[0x10]; 3660 3661 u8 reserved_1[0x10]; 3662 u8 op_mod[0x10]; 3663 3664 u8 other_vport[0x1]; 3665 u8 reserved_2[0xf]; 3666 u8 vport_number[0x10]; 3667 3668 u8 reserved_3[0x20]; 3669 3670 u8 table_type[0x8]; 3671 u8 reserved_4[0x18]; 3672 3673 u8 reserved_5[0x8]; 3674 u8 table_id[0x18]; 3675 3676 u8 reserved_6[0x8]; 3677 u8 underlay_qpn[0x18]; 3678 3679 u8 reserved_7[0x120]; 3680 }; 3681 3682 struct mlx5_ifc_set_fte_out_bits { 3683 u8 status[0x8]; 3684 u8 reserved_0[0x18]; 3685 3686 u8 syndrome[0x20]; 3687 3688 u8 reserved_1[0x40]; 3689 }; 3690 3691 struct mlx5_ifc_set_fte_in_bits { 3692 u8 opcode[0x10]; 3693 u8 reserved_0[0x10]; 3694 3695 u8 reserved_1[0x10]; 3696 u8 op_mod[0x10]; 3697 3698 u8 other_vport[0x1]; 3699 u8 reserved_2[0xf]; 3700 u8 vport_number[0x10]; 3701 3702 u8 reserved_3[0x20]; 3703 3704 u8 table_type[0x8]; 3705 u8 reserved_4[0x18]; 3706 3707 u8 reserved_5[0x8]; 3708 u8 table_id[0x18]; 3709 3710 u8 reserved_6[0x18]; 3711 u8 modify_enable_mask[0x8]; 3712 3713 u8 reserved_7[0x20]; 3714 3715 u8 flow_index[0x20]; 3716 3717 u8 reserved_8[0xe0]; 3718 3719 struct mlx5_ifc_flow_context_bits flow_context; 3720 }; 3721 3722 struct mlx5_ifc_set_driver_version_out_bits { 3723 u8 status[0x8]; 3724 u8 reserved_0[0x18]; 3725 3726 u8 syndrome[0x20]; 3727 3728 u8 reserved_1[0x40]; 3729 }; 3730 3731 struct mlx5_ifc_set_driver_version_in_bits { 3732 u8 opcode[0x10]; 3733 u8 reserved_0[0x10]; 3734 3735 u8 reserved_1[0x10]; 3736 u8 op_mod[0x10]; 3737 3738 u8 reserved_2[0x40]; 3739 3740 u8 driver_version[64][0x8]; 3741 }; 3742 3743 struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3744 u8 status[0x8]; 3745 u8 reserved_0[0x18]; 3746 3747 u8 syndrome[0x20]; 3748 3749 u8 reserved_1[0x40]; 3750 }; 3751 3752 struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3753 u8 opcode[0x10]; 3754 u8 reserved_0[0x10]; 3755 3756 u8 reserved_1[0x10]; 3757 u8 op_mod[0x10]; 3758 3759 u8 enable[0x1]; 3760 u8 reserved_2[0x1f]; 3761 3762 u8 reserved_3[0x160]; 3763 3764 struct mlx5_ifc_cmd_pas_bits pas; 3765 }; 3766 3767 struct mlx5_ifc_set_burst_size_out_bits { 3768 u8 status[0x8]; 3769 u8 reserved_0[0x18]; 3770 3771 u8 syndrome[0x20]; 3772 3773 u8 reserved_1[0x40]; 3774 }; 3775 3776 struct mlx5_ifc_set_burst_size_in_bits { 3777 u8 opcode[0x10]; 3778 u8 reserved_0[0x10]; 3779 3780 u8 reserved_1[0x10]; 3781 u8 op_mod[0x10]; 3782 3783 u8 reserved_2[0x20]; 3784 3785 u8 reserved_3[0x9]; 3786 u8 device_burst_size[0x17]; 3787 }; 3788 3789 struct mlx5_ifc_rts2rts_qp_out_bits { 3790 u8 status[0x8]; 3791 u8 reserved_0[0x18]; 3792 3793 u8 syndrome[0x20]; 3794 3795 u8 reserved_1[0x40]; 3796 }; 3797 3798 struct mlx5_ifc_rts2rts_qp_in_bits { 3799 u8 opcode[0x10]; 3800 u8 reserved_0[0x10]; 3801 3802 u8 reserved_1[0x10]; 3803 u8 op_mod[0x10]; 3804 3805 u8 reserved_2[0x8]; 3806 u8 qpn[0x18]; 3807 3808 u8 reserved_3[0x20]; 3809 3810 u8 opt_param_mask[0x20]; 3811 3812 u8 reserved_4[0x20]; 3813 3814 struct mlx5_ifc_qpc_bits qpc; 3815 3816 u8 reserved_5[0x80]; 3817 }; 3818 3819 struct mlx5_ifc_rtr2rts_qp_out_bits { 3820 u8 status[0x8]; 3821 u8 reserved_0[0x18]; 3822 3823 u8 syndrome[0x20]; 3824 3825 u8 reserved_1[0x40]; 3826 }; 3827 3828 struct mlx5_ifc_rtr2rts_qp_in_bits { 3829 u8 opcode[0x10]; 3830 u8 reserved_0[0x10]; 3831 3832 u8 reserved_1[0x10]; 3833 u8 op_mod[0x10]; 3834 3835 u8 reserved_2[0x8]; 3836 u8 qpn[0x18]; 3837 3838 u8 reserved_3[0x20]; 3839 3840 u8 opt_param_mask[0x20]; 3841 3842 u8 reserved_4[0x20]; 3843 3844 struct mlx5_ifc_qpc_bits qpc; 3845 3846 u8 reserved_5[0x80]; 3847 }; 3848 3849 struct mlx5_ifc_rst2init_qp_out_bits { 3850 u8 status[0x8]; 3851 u8 reserved_0[0x18]; 3852 3853 u8 syndrome[0x20]; 3854 3855 u8 reserved_1[0x40]; 3856 }; 3857 3858 struct mlx5_ifc_rst2init_qp_in_bits { 3859 u8 opcode[0x10]; 3860 u8 reserved_0[0x10]; 3861 3862 u8 reserved_1[0x10]; 3863 u8 op_mod[0x10]; 3864 3865 u8 reserved_2[0x8]; 3866 u8 qpn[0x18]; 3867 3868 u8 reserved_3[0x20]; 3869 3870 u8 opt_param_mask[0x20]; 3871 3872 u8 reserved_4[0x20]; 3873 3874 struct mlx5_ifc_qpc_bits qpc; 3875 3876 u8 reserved_5[0x80]; 3877 }; 3878 3879 struct mlx5_ifc_resume_qp_out_bits { 3880 u8 status[0x8]; 3881 u8 reserved_0[0x18]; 3882 3883 u8 syndrome[0x20]; 3884 3885 u8 reserved_1[0x40]; 3886 }; 3887 3888 struct mlx5_ifc_resume_qp_in_bits { 3889 u8 opcode[0x10]; 3890 u8 reserved_0[0x10]; 3891 3892 u8 reserved_1[0x10]; 3893 u8 op_mod[0x10]; 3894 3895 u8 reserved_2[0x8]; 3896 u8 qpn[0x18]; 3897 3898 u8 reserved_3[0x20]; 3899 }; 3900 3901 struct mlx5_ifc_query_xrc_srq_out_bits { 3902 u8 status[0x8]; 3903 u8 reserved_0[0x18]; 3904 3905 u8 syndrome[0x20]; 3906 3907 u8 reserved_1[0x40]; 3908 3909 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3910 3911 u8 reserved_2[0x600]; 3912 3913 u8 pas[0][0x40]; 3914 }; 3915 3916 struct mlx5_ifc_query_xrc_srq_in_bits { 3917 u8 opcode[0x10]; 3918 u8 reserved_0[0x10]; 3919 3920 u8 reserved_1[0x10]; 3921 u8 op_mod[0x10]; 3922 3923 u8 reserved_2[0x8]; 3924 u8 xrc_srqn[0x18]; 3925 3926 u8 reserved_3[0x20]; 3927 }; 3928 3929 struct mlx5_ifc_query_wol_rol_out_bits { 3930 u8 status[0x8]; 3931 u8 reserved_0[0x18]; 3932 3933 u8 syndrome[0x20]; 3934 3935 u8 reserved_1[0x10]; 3936 u8 rol_mode[0x8]; 3937 u8 wol_mode[0x8]; 3938 3939 u8 reserved_2[0x20]; 3940 }; 3941 3942 struct mlx5_ifc_query_wol_rol_in_bits { 3943 u8 opcode[0x10]; 3944 u8 reserved_0[0x10]; 3945 3946 u8 reserved_1[0x10]; 3947 u8 op_mod[0x10]; 3948 3949 u8 reserved_2[0x40]; 3950 }; 3951 3952 enum { 3953 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3954 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3955 }; 3956 3957 struct mlx5_ifc_query_vport_state_out_bits { 3958 u8 status[0x8]; 3959 u8 reserved_0[0x18]; 3960 3961 u8 syndrome[0x20]; 3962 3963 u8 reserved_1[0x20]; 3964 3965 u8 reserved_2[0x18]; 3966 u8 admin_state[0x4]; 3967 u8 state[0x4]; 3968 }; 3969 3970 enum { 3971 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3972 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3973 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 3974 }; 3975 3976 struct mlx5_ifc_query_vport_state_in_bits { 3977 u8 opcode[0x10]; 3978 u8 reserved_0[0x10]; 3979 3980 u8 reserved_1[0x10]; 3981 u8 op_mod[0x10]; 3982 3983 u8 other_vport[0x1]; 3984 u8 reserved_2[0xf]; 3985 u8 vport_number[0x10]; 3986 3987 u8 reserved_3[0x20]; 3988 }; 3989 3990 struct mlx5_ifc_query_vnic_env_out_bits { 3991 u8 status[0x8]; 3992 u8 reserved_at_8[0x18]; 3993 3994 u8 syndrome[0x20]; 3995 3996 u8 reserved_at_40[0x40]; 3997 3998 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3999 }; 4000 4001 enum { 4002 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4003 }; 4004 4005 struct mlx5_ifc_query_vnic_env_in_bits { 4006 u8 opcode[0x10]; 4007 u8 reserved_at_10[0x10]; 4008 4009 u8 reserved_at_20[0x10]; 4010 u8 op_mod[0x10]; 4011 4012 u8 other_vport[0x1]; 4013 u8 reserved_at_41[0xf]; 4014 u8 vport_number[0x10]; 4015 4016 u8 reserved_at_60[0x20]; 4017 }; 4018 4019 struct mlx5_ifc_query_vport_counter_out_bits { 4020 u8 status[0x8]; 4021 u8 reserved_0[0x18]; 4022 4023 u8 syndrome[0x20]; 4024 4025 u8 reserved_1[0x40]; 4026 4027 struct mlx5_ifc_traffic_counter_bits received_errors; 4028 4029 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4030 4031 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4032 4033 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4034 4035 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4036 4037 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4038 4039 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4040 4041 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4042 4043 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4044 4045 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4046 4047 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4048 4049 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4050 4051 u8 reserved_2[0xa00]; 4052 }; 4053 4054 enum { 4055 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4056 }; 4057 4058 struct mlx5_ifc_query_vport_counter_in_bits { 4059 u8 opcode[0x10]; 4060 u8 reserved_0[0x10]; 4061 4062 u8 reserved_1[0x10]; 4063 u8 op_mod[0x10]; 4064 4065 u8 other_vport[0x1]; 4066 u8 reserved_2[0xb]; 4067 u8 port_num[0x4]; 4068 u8 vport_number[0x10]; 4069 4070 u8 reserved_3[0x60]; 4071 4072 u8 clear[0x1]; 4073 u8 reserved_4[0x1f]; 4074 4075 u8 reserved_5[0x20]; 4076 }; 4077 4078 struct mlx5_ifc_query_tis_out_bits { 4079 u8 status[0x8]; 4080 u8 reserved_0[0x18]; 4081 4082 u8 syndrome[0x20]; 4083 4084 u8 reserved_1[0x40]; 4085 4086 struct mlx5_ifc_tisc_bits tis_context; 4087 }; 4088 4089 struct mlx5_ifc_query_tis_in_bits { 4090 u8 opcode[0x10]; 4091 u8 reserved_0[0x10]; 4092 4093 u8 reserved_1[0x10]; 4094 u8 op_mod[0x10]; 4095 4096 u8 reserved_2[0x8]; 4097 u8 tisn[0x18]; 4098 4099 u8 reserved_3[0x20]; 4100 }; 4101 4102 struct mlx5_ifc_query_tir_out_bits { 4103 u8 status[0x8]; 4104 u8 reserved_0[0x18]; 4105 4106 u8 syndrome[0x20]; 4107 4108 u8 reserved_1[0xc0]; 4109 4110 struct mlx5_ifc_tirc_bits tir_context; 4111 }; 4112 4113 struct mlx5_ifc_query_tir_in_bits { 4114 u8 opcode[0x10]; 4115 u8 reserved_0[0x10]; 4116 4117 u8 reserved_1[0x10]; 4118 u8 op_mod[0x10]; 4119 4120 u8 reserved_2[0x8]; 4121 u8 tirn[0x18]; 4122 4123 u8 reserved_3[0x20]; 4124 }; 4125 4126 struct mlx5_ifc_query_srq_out_bits { 4127 u8 status[0x8]; 4128 u8 reserved_0[0x18]; 4129 4130 u8 syndrome[0x20]; 4131 4132 u8 reserved_1[0x40]; 4133 4134 struct mlx5_ifc_srqc_bits srq_context_entry; 4135 4136 u8 reserved_2[0x600]; 4137 4138 u8 pas[0][0x40]; 4139 }; 4140 4141 struct mlx5_ifc_query_srq_in_bits { 4142 u8 opcode[0x10]; 4143 u8 reserved_0[0x10]; 4144 4145 u8 reserved_1[0x10]; 4146 u8 op_mod[0x10]; 4147 4148 u8 reserved_2[0x8]; 4149 u8 srqn[0x18]; 4150 4151 u8 reserved_3[0x20]; 4152 }; 4153 4154 struct mlx5_ifc_query_sq_out_bits { 4155 u8 status[0x8]; 4156 u8 reserved_0[0x18]; 4157 4158 u8 syndrome[0x20]; 4159 4160 u8 reserved_1[0xc0]; 4161 4162 struct mlx5_ifc_sqc_bits sq_context; 4163 }; 4164 4165 struct mlx5_ifc_query_sq_in_bits { 4166 u8 opcode[0x10]; 4167 u8 reserved_0[0x10]; 4168 4169 u8 reserved_1[0x10]; 4170 u8 op_mod[0x10]; 4171 4172 u8 reserved_2[0x8]; 4173 u8 sqn[0x18]; 4174 4175 u8 reserved_3[0x20]; 4176 }; 4177 4178 struct mlx5_ifc_query_special_contexts_out_bits { 4179 u8 status[0x8]; 4180 u8 reserved_0[0x18]; 4181 4182 u8 syndrome[0x20]; 4183 4184 u8 dump_fill_mkey[0x20]; 4185 4186 u8 resd_lkey[0x20]; 4187 }; 4188 4189 struct mlx5_ifc_query_special_contexts_in_bits { 4190 u8 opcode[0x10]; 4191 u8 reserved_0[0x10]; 4192 4193 u8 reserved_1[0x10]; 4194 u8 op_mod[0x10]; 4195 4196 u8 reserved_2[0x40]; 4197 }; 4198 4199 struct mlx5_ifc_query_scheduling_element_out_bits { 4200 u8 status[0x8]; 4201 u8 reserved_at_8[0x18]; 4202 4203 u8 syndrome[0x20]; 4204 4205 u8 reserved_at_40[0xc0]; 4206 4207 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4208 4209 u8 reserved_at_300[0x100]; 4210 }; 4211 4212 enum { 4213 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4214 }; 4215 4216 struct mlx5_ifc_query_scheduling_element_in_bits { 4217 u8 opcode[0x10]; 4218 u8 reserved_at_10[0x10]; 4219 4220 u8 reserved_at_20[0x10]; 4221 u8 op_mod[0x10]; 4222 4223 u8 scheduling_hierarchy[0x8]; 4224 u8 reserved_at_48[0x18]; 4225 4226 u8 scheduling_element_id[0x20]; 4227 4228 u8 reserved_at_80[0x180]; 4229 }; 4230 4231 struct mlx5_ifc_query_rqt_out_bits { 4232 u8 status[0x8]; 4233 u8 reserved_0[0x18]; 4234 4235 u8 syndrome[0x20]; 4236 4237 u8 reserved_1[0xc0]; 4238 4239 struct mlx5_ifc_rqtc_bits rqt_context; 4240 }; 4241 4242 struct mlx5_ifc_query_rqt_in_bits { 4243 u8 opcode[0x10]; 4244 u8 reserved_0[0x10]; 4245 4246 u8 reserved_1[0x10]; 4247 u8 op_mod[0x10]; 4248 4249 u8 reserved_2[0x8]; 4250 u8 rqtn[0x18]; 4251 4252 u8 reserved_3[0x20]; 4253 }; 4254 4255 struct mlx5_ifc_query_rq_out_bits { 4256 u8 status[0x8]; 4257 u8 reserved_0[0x18]; 4258 4259 u8 syndrome[0x20]; 4260 4261 u8 reserved_1[0xc0]; 4262 4263 struct mlx5_ifc_rqc_bits rq_context; 4264 }; 4265 4266 struct mlx5_ifc_query_rq_in_bits { 4267 u8 opcode[0x10]; 4268 u8 reserved_0[0x10]; 4269 4270 u8 reserved_1[0x10]; 4271 u8 op_mod[0x10]; 4272 4273 u8 reserved_2[0x8]; 4274 u8 rqn[0x18]; 4275 4276 u8 reserved_3[0x20]; 4277 }; 4278 4279 struct mlx5_ifc_query_roce_address_out_bits { 4280 u8 status[0x8]; 4281 u8 reserved_0[0x18]; 4282 4283 u8 syndrome[0x20]; 4284 4285 u8 reserved_1[0x40]; 4286 4287 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4288 }; 4289 4290 struct mlx5_ifc_query_roce_address_in_bits { 4291 u8 opcode[0x10]; 4292 u8 reserved_0[0x10]; 4293 4294 u8 reserved_1[0x10]; 4295 u8 op_mod[0x10]; 4296 4297 u8 roce_address_index[0x10]; 4298 u8 reserved_2[0x10]; 4299 4300 u8 reserved_3[0x20]; 4301 }; 4302 4303 struct mlx5_ifc_query_rmp_out_bits { 4304 u8 status[0x8]; 4305 u8 reserved_0[0x18]; 4306 4307 u8 syndrome[0x20]; 4308 4309 u8 reserved_1[0xc0]; 4310 4311 struct mlx5_ifc_rmpc_bits rmp_context; 4312 }; 4313 4314 struct mlx5_ifc_query_rmp_in_bits { 4315 u8 opcode[0x10]; 4316 u8 reserved_0[0x10]; 4317 4318 u8 reserved_1[0x10]; 4319 u8 op_mod[0x10]; 4320 4321 u8 reserved_2[0x8]; 4322 u8 rmpn[0x18]; 4323 4324 u8 reserved_3[0x20]; 4325 }; 4326 4327 struct mlx5_ifc_query_rdb_out_bits { 4328 u8 status[0x8]; 4329 u8 reserved_0[0x18]; 4330 4331 u8 syndrome[0x20]; 4332 4333 u8 reserved_1[0x20]; 4334 4335 u8 reserved_2[0x18]; 4336 u8 rdb_list_size[0x8]; 4337 4338 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4339 }; 4340 4341 struct mlx5_ifc_query_rdb_in_bits { 4342 u8 opcode[0x10]; 4343 u8 reserved_0[0x10]; 4344 4345 u8 reserved_1[0x10]; 4346 u8 op_mod[0x10]; 4347 4348 u8 reserved_2[0x8]; 4349 u8 qpn[0x18]; 4350 4351 u8 reserved_3[0x20]; 4352 }; 4353 4354 struct mlx5_ifc_query_qp_out_bits { 4355 u8 status[0x8]; 4356 u8 reserved_0[0x18]; 4357 4358 u8 syndrome[0x20]; 4359 4360 u8 reserved_1[0x40]; 4361 4362 u8 opt_param_mask[0x20]; 4363 4364 u8 reserved_2[0x20]; 4365 4366 struct mlx5_ifc_qpc_bits qpc; 4367 4368 u8 reserved_3[0x80]; 4369 4370 u8 pas[0][0x40]; 4371 }; 4372 4373 struct mlx5_ifc_query_qp_in_bits { 4374 u8 opcode[0x10]; 4375 u8 reserved_0[0x10]; 4376 4377 u8 reserved_1[0x10]; 4378 u8 op_mod[0x10]; 4379 4380 u8 reserved_2[0x8]; 4381 u8 qpn[0x18]; 4382 4383 u8 reserved_3[0x20]; 4384 }; 4385 4386 struct mlx5_ifc_query_q_counter_out_bits { 4387 u8 status[0x8]; 4388 u8 reserved_0[0x18]; 4389 4390 u8 syndrome[0x20]; 4391 4392 u8 reserved_1[0x40]; 4393 4394 u8 rx_write_requests[0x20]; 4395 4396 u8 reserved_2[0x20]; 4397 4398 u8 rx_read_requests[0x20]; 4399 4400 u8 reserved_3[0x20]; 4401 4402 u8 rx_atomic_requests[0x20]; 4403 4404 u8 reserved_4[0x20]; 4405 4406 u8 rx_dct_connect[0x20]; 4407 4408 u8 reserved_5[0x20]; 4409 4410 u8 out_of_buffer[0x20]; 4411 4412 u8 reserved_7[0x20]; 4413 4414 u8 out_of_sequence[0x20]; 4415 4416 u8 reserved_8[0x20]; 4417 4418 u8 duplicate_request[0x20]; 4419 4420 u8 reserved_9[0x20]; 4421 4422 u8 rnr_nak_retry_err[0x20]; 4423 4424 u8 reserved_10[0x20]; 4425 4426 u8 packet_seq_err[0x20]; 4427 4428 u8 reserved_11[0x20]; 4429 4430 u8 implied_nak_seq_err[0x20]; 4431 4432 u8 reserved_12[0x20]; 4433 4434 u8 local_ack_timeout_err[0x20]; 4435 4436 u8 reserved_13[0x20]; 4437 4438 u8 resp_rnr_nak[0x20]; 4439 4440 u8 reserved_14[0x20]; 4441 4442 u8 req_rnr_retries_exceeded[0x20]; 4443 4444 u8 reserved_15[0x460]; 4445 }; 4446 4447 struct mlx5_ifc_query_q_counter_in_bits { 4448 u8 opcode[0x10]; 4449 u8 reserved_0[0x10]; 4450 4451 u8 reserved_1[0x10]; 4452 u8 op_mod[0x10]; 4453 4454 u8 reserved_2[0x80]; 4455 4456 u8 clear[0x1]; 4457 u8 reserved_3[0x1f]; 4458 4459 u8 reserved_4[0x18]; 4460 u8 counter_set_id[0x8]; 4461 }; 4462 4463 struct mlx5_ifc_query_pages_out_bits { 4464 u8 status[0x8]; 4465 u8 reserved_0[0x18]; 4466 4467 u8 syndrome[0x20]; 4468 4469 u8 reserved_1[0x10]; 4470 u8 function_id[0x10]; 4471 4472 u8 num_pages[0x20]; 4473 }; 4474 4475 enum { 4476 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4477 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4478 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4479 }; 4480 4481 struct mlx5_ifc_query_pages_in_bits { 4482 u8 opcode[0x10]; 4483 u8 reserved_0[0x10]; 4484 4485 u8 reserved_1[0x10]; 4486 u8 op_mod[0x10]; 4487 4488 u8 reserved_2[0x10]; 4489 u8 function_id[0x10]; 4490 4491 u8 reserved_3[0x20]; 4492 }; 4493 4494 struct mlx5_ifc_query_nic_vport_context_out_bits { 4495 u8 status[0x8]; 4496 u8 reserved_0[0x18]; 4497 4498 u8 syndrome[0x20]; 4499 4500 u8 reserved_1[0x40]; 4501 4502 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4503 }; 4504 4505 struct mlx5_ifc_query_nic_vport_context_in_bits { 4506 u8 opcode[0x10]; 4507 u8 reserved_0[0x10]; 4508 4509 u8 reserved_1[0x10]; 4510 u8 op_mod[0x10]; 4511 4512 u8 other_vport[0x1]; 4513 u8 reserved_2[0xf]; 4514 u8 vport_number[0x10]; 4515 4516 u8 reserved_3[0x5]; 4517 u8 allowed_list_type[0x3]; 4518 u8 reserved_4[0x18]; 4519 }; 4520 4521 struct mlx5_ifc_query_mkey_out_bits { 4522 u8 status[0x8]; 4523 u8 reserved_0[0x18]; 4524 4525 u8 syndrome[0x20]; 4526 4527 u8 reserved_1[0x40]; 4528 4529 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4530 4531 u8 reserved_2[0x600]; 4532 4533 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4534 4535 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4536 }; 4537 4538 struct mlx5_ifc_query_mkey_in_bits { 4539 u8 opcode[0x10]; 4540 u8 reserved_0[0x10]; 4541 4542 u8 reserved_1[0x10]; 4543 u8 op_mod[0x10]; 4544 4545 u8 reserved_2[0x8]; 4546 u8 mkey_index[0x18]; 4547 4548 u8 pg_access[0x1]; 4549 u8 reserved_3[0x1f]; 4550 }; 4551 4552 struct mlx5_ifc_query_mad_demux_out_bits { 4553 u8 status[0x8]; 4554 u8 reserved_0[0x18]; 4555 4556 u8 syndrome[0x20]; 4557 4558 u8 reserved_1[0x40]; 4559 4560 u8 mad_dumux_parameters_block[0x20]; 4561 }; 4562 4563 struct mlx5_ifc_query_mad_demux_in_bits { 4564 u8 opcode[0x10]; 4565 u8 reserved_0[0x10]; 4566 4567 u8 reserved_1[0x10]; 4568 u8 op_mod[0x10]; 4569 4570 u8 reserved_2[0x40]; 4571 }; 4572 4573 struct mlx5_ifc_query_l2_table_entry_out_bits { 4574 u8 status[0x8]; 4575 u8 reserved_0[0x18]; 4576 4577 u8 syndrome[0x20]; 4578 4579 u8 reserved_1[0xa0]; 4580 4581 u8 reserved_2[0x13]; 4582 u8 vlan_valid[0x1]; 4583 u8 vlan[0xc]; 4584 4585 struct mlx5_ifc_mac_address_layout_bits mac_address; 4586 4587 u8 reserved_3[0xc0]; 4588 }; 4589 4590 struct mlx5_ifc_query_l2_table_entry_in_bits { 4591 u8 opcode[0x10]; 4592 u8 reserved_0[0x10]; 4593 4594 u8 reserved_1[0x10]; 4595 u8 op_mod[0x10]; 4596 4597 u8 reserved_2[0x60]; 4598 4599 u8 reserved_3[0x8]; 4600 u8 table_index[0x18]; 4601 4602 u8 reserved_4[0x140]; 4603 }; 4604 4605 struct mlx5_ifc_query_issi_out_bits { 4606 u8 status[0x8]; 4607 u8 reserved_0[0x18]; 4608 4609 u8 syndrome[0x20]; 4610 4611 u8 reserved_1[0x10]; 4612 u8 current_issi[0x10]; 4613 4614 u8 reserved_2[0xa0]; 4615 4616 u8 supported_issi_reserved[76][0x8]; 4617 u8 supported_issi_dw0[0x20]; 4618 }; 4619 4620 struct mlx5_ifc_query_issi_in_bits { 4621 u8 opcode[0x10]; 4622 u8 reserved_0[0x10]; 4623 4624 u8 reserved_1[0x10]; 4625 u8 op_mod[0x10]; 4626 4627 u8 reserved_2[0x40]; 4628 }; 4629 4630 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4631 u8 status[0x8]; 4632 u8 reserved_0[0x18]; 4633 4634 u8 syndrome[0x20]; 4635 4636 u8 reserved_1[0x40]; 4637 4638 struct mlx5_ifc_pkey_bits pkey[0]; 4639 }; 4640 4641 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4642 u8 opcode[0x10]; 4643 u8 reserved_0[0x10]; 4644 4645 u8 reserved_1[0x10]; 4646 u8 op_mod[0x10]; 4647 4648 u8 other_vport[0x1]; 4649 u8 reserved_2[0xb]; 4650 u8 port_num[0x4]; 4651 u8 vport_number[0x10]; 4652 4653 u8 reserved_3[0x10]; 4654 u8 pkey_index[0x10]; 4655 }; 4656 4657 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4658 u8 status[0x8]; 4659 u8 reserved_0[0x18]; 4660 4661 u8 syndrome[0x20]; 4662 4663 u8 reserved_1[0x20]; 4664 4665 u8 gids_num[0x10]; 4666 u8 reserved_2[0x10]; 4667 4668 struct mlx5_ifc_array128_auto_bits gid[0]; 4669 }; 4670 4671 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4672 u8 opcode[0x10]; 4673 u8 reserved_0[0x10]; 4674 4675 u8 reserved_1[0x10]; 4676 u8 op_mod[0x10]; 4677 4678 u8 other_vport[0x1]; 4679 u8 reserved_2[0xb]; 4680 u8 port_num[0x4]; 4681 u8 vport_number[0x10]; 4682 4683 u8 reserved_3[0x10]; 4684 u8 gid_index[0x10]; 4685 }; 4686 4687 struct mlx5_ifc_query_hca_vport_context_out_bits { 4688 u8 status[0x8]; 4689 u8 reserved_0[0x18]; 4690 4691 u8 syndrome[0x20]; 4692 4693 u8 reserved_1[0x40]; 4694 4695 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4696 }; 4697 4698 struct mlx5_ifc_query_hca_vport_context_in_bits { 4699 u8 opcode[0x10]; 4700 u8 reserved_0[0x10]; 4701 4702 u8 reserved_1[0x10]; 4703 u8 op_mod[0x10]; 4704 4705 u8 other_vport[0x1]; 4706 u8 reserved_2[0xb]; 4707 u8 port_num[0x4]; 4708 u8 vport_number[0x10]; 4709 4710 u8 reserved_3[0x20]; 4711 }; 4712 4713 struct mlx5_ifc_query_hca_cap_out_bits { 4714 u8 status[0x8]; 4715 u8 reserved_0[0x18]; 4716 4717 u8 syndrome[0x20]; 4718 4719 u8 reserved_1[0x40]; 4720 4721 union mlx5_ifc_hca_cap_union_bits capability; 4722 }; 4723 4724 struct mlx5_ifc_query_hca_cap_in_bits { 4725 u8 opcode[0x10]; 4726 u8 reserved_0[0x10]; 4727 4728 u8 reserved_1[0x10]; 4729 u8 op_mod[0x10]; 4730 4731 u8 reserved_2[0x40]; 4732 }; 4733 4734 struct mlx5_ifc_query_flow_table_out_bits { 4735 u8 status[0x8]; 4736 u8 reserved_at_8[0x18]; 4737 4738 u8 syndrome[0x20]; 4739 4740 u8 reserved_at_40[0x80]; 4741 4742 struct mlx5_ifc_flow_table_context_bits flow_table_context; 4743 }; 4744 4745 struct mlx5_ifc_query_flow_table_in_bits { 4746 u8 opcode[0x10]; 4747 u8 reserved_0[0x10]; 4748 4749 u8 reserved_1[0x10]; 4750 u8 op_mod[0x10]; 4751 4752 u8 other_vport[0x1]; 4753 u8 reserved_2[0xf]; 4754 u8 vport_number[0x10]; 4755 4756 u8 reserved_3[0x20]; 4757 4758 u8 table_type[0x8]; 4759 u8 reserved_4[0x18]; 4760 4761 u8 reserved_5[0x8]; 4762 u8 table_id[0x18]; 4763 4764 u8 reserved_6[0x140]; 4765 }; 4766 4767 struct mlx5_ifc_query_fte_out_bits { 4768 u8 status[0x8]; 4769 u8 reserved_0[0x18]; 4770 4771 u8 syndrome[0x20]; 4772 4773 u8 reserved_1[0x1c0]; 4774 4775 struct mlx5_ifc_flow_context_bits flow_context; 4776 }; 4777 4778 struct mlx5_ifc_query_fte_in_bits { 4779 u8 opcode[0x10]; 4780 u8 reserved_0[0x10]; 4781 4782 u8 reserved_1[0x10]; 4783 u8 op_mod[0x10]; 4784 4785 u8 other_vport[0x1]; 4786 u8 reserved_2[0xf]; 4787 u8 vport_number[0x10]; 4788 4789 u8 reserved_3[0x20]; 4790 4791 u8 table_type[0x8]; 4792 u8 reserved_4[0x18]; 4793 4794 u8 reserved_5[0x8]; 4795 u8 table_id[0x18]; 4796 4797 u8 reserved_6[0x40]; 4798 4799 u8 flow_index[0x20]; 4800 4801 u8 reserved_7[0xe0]; 4802 }; 4803 4804 enum { 4805 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4806 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4807 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4808 }; 4809 4810 struct mlx5_ifc_query_flow_group_out_bits { 4811 u8 status[0x8]; 4812 u8 reserved_0[0x18]; 4813 4814 u8 syndrome[0x20]; 4815 4816 u8 reserved_1[0xa0]; 4817 4818 u8 start_flow_index[0x20]; 4819 4820 u8 reserved_2[0x20]; 4821 4822 u8 end_flow_index[0x20]; 4823 4824 u8 reserved_3[0xa0]; 4825 4826 u8 reserved_4[0x18]; 4827 u8 match_criteria_enable[0x8]; 4828 4829 struct mlx5_ifc_fte_match_param_bits match_criteria; 4830 4831 u8 reserved_5[0xe00]; 4832 }; 4833 4834 struct mlx5_ifc_query_flow_group_in_bits { 4835 u8 opcode[0x10]; 4836 u8 reserved_0[0x10]; 4837 4838 u8 reserved_1[0x10]; 4839 u8 op_mod[0x10]; 4840 4841 u8 other_vport[0x1]; 4842 u8 reserved_2[0xf]; 4843 u8 vport_number[0x10]; 4844 4845 u8 reserved_3[0x20]; 4846 4847 u8 table_type[0x8]; 4848 u8 reserved_4[0x18]; 4849 4850 u8 reserved_5[0x8]; 4851 u8 table_id[0x18]; 4852 4853 u8 group_id[0x20]; 4854 4855 u8 reserved_6[0x120]; 4856 }; 4857 4858 struct mlx5_ifc_query_flow_counter_out_bits { 4859 u8 status[0x8]; 4860 u8 reserved_at_8[0x18]; 4861 4862 u8 syndrome[0x20]; 4863 4864 u8 reserved_at_40[0x40]; 4865 4866 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4867 }; 4868 4869 struct mlx5_ifc_query_flow_counter_in_bits { 4870 u8 opcode[0x10]; 4871 u8 reserved_at_10[0x10]; 4872 4873 u8 reserved_at_20[0x10]; 4874 u8 op_mod[0x10]; 4875 4876 u8 reserved_at_40[0x80]; 4877 4878 u8 clear[0x1]; 4879 u8 reserved_at_c1[0xf]; 4880 u8 num_of_counters[0x10]; 4881 4882 u8 reserved_at_e0[0x10]; 4883 u8 flow_counter_id[0x10]; 4884 }; 4885 4886 struct mlx5_ifc_query_esw_vport_context_out_bits { 4887 u8 status[0x8]; 4888 u8 reserved_0[0x18]; 4889 4890 u8 syndrome[0x20]; 4891 4892 u8 reserved_1[0x40]; 4893 4894 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4895 }; 4896 4897 struct mlx5_ifc_query_esw_vport_context_in_bits { 4898 u8 opcode[0x10]; 4899 u8 reserved_0[0x10]; 4900 4901 u8 reserved_1[0x10]; 4902 u8 op_mod[0x10]; 4903 4904 u8 other_vport[0x1]; 4905 u8 reserved_2[0xf]; 4906 u8 vport_number[0x10]; 4907 4908 u8 reserved_3[0x20]; 4909 }; 4910 4911 struct mlx5_ifc_query_eq_out_bits { 4912 u8 status[0x8]; 4913 u8 reserved_0[0x18]; 4914 4915 u8 syndrome[0x20]; 4916 4917 u8 reserved_1[0x40]; 4918 4919 struct mlx5_ifc_eqc_bits eq_context_entry; 4920 4921 u8 reserved_2[0x40]; 4922 4923 u8 event_bitmask[0x40]; 4924 4925 u8 reserved_3[0x580]; 4926 4927 u8 pas[0][0x40]; 4928 }; 4929 4930 struct mlx5_ifc_query_eq_in_bits { 4931 u8 opcode[0x10]; 4932 u8 reserved_0[0x10]; 4933 4934 u8 reserved_1[0x10]; 4935 u8 op_mod[0x10]; 4936 4937 u8 reserved_2[0x18]; 4938 u8 eq_number[0x8]; 4939 4940 u8 reserved_3[0x20]; 4941 }; 4942 4943 struct mlx5_ifc_query_dct_out_bits { 4944 u8 status[0x8]; 4945 u8 reserved_0[0x18]; 4946 4947 u8 syndrome[0x20]; 4948 4949 u8 reserved_1[0x40]; 4950 4951 struct mlx5_ifc_dctc_bits dct_context_entry; 4952 4953 u8 reserved_2[0x180]; 4954 }; 4955 4956 struct mlx5_ifc_query_dct_in_bits { 4957 u8 opcode[0x10]; 4958 u8 reserved_0[0x10]; 4959 4960 u8 reserved_1[0x10]; 4961 u8 op_mod[0x10]; 4962 4963 u8 reserved_2[0x8]; 4964 u8 dctn[0x18]; 4965 4966 u8 reserved_3[0x20]; 4967 }; 4968 4969 struct mlx5_ifc_query_dc_cnak_trace_out_bits { 4970 u8 status[0x8]; 4971 u8 reserved_0[0x18]; 4972 4973 u8 syndrome[0x20]; 4974 4975 u8 enable[0x1]; 4976 u8 reserved_1[0x1f]; 4977 4978 u8 reserved_2[0x160]; 4979 4980 struct mlx5_ifc_cmd_pas_bits pas; 4981 }; 4982 4983 struct mlx5_ifc_query_dc_cnak_trace_in_bits { 4984 u8 opcode[0x10]; 4985 u8 reserved_0[0x10]; 4986 4987 u8 reserved_1[0x10]; 4988 u8 op_mod[0x10]; 4989 4990 u8 reserved_2[0x40]; 4991 }; 4992 4993 struct mlx5_ifc_query_cq_out_bits { 4994 u8 status[0x8]; 4995 u8 reserved_0[0x18]; 4996 4997 u8 syndrome[0x20]; 4998 4999 u8 reserved_1[0x40]; 5000 5001 struct mlx5_ifc_cqc_bits cq_context; 5002 5003 u8 reserved_2[0x600]; 5004 5005 u8 pas[0][0x40]; 5006 }; 5007 5008 struct mlx5_ifc_query_cq_in_bits { 5009 u8 opcode[0x10]; 5010 u8 reserved_0[0x10]; 5011 5012 u8 reserved_1[0x10]; 5013 u8 op_mod[0x10]; 5014 5015 u8 reserved_2[0x8]; 5016 u8 cqn[0x18]; 5017 5018 u8 reserved_3[0x20]; 5019 }; 5020 5021 struct mlx5_ifc_query_cong_status_out_bits { 5022 u8 status[0x8]; 5023 u8 reserved_0[0x18]; 5024 5025 u8 syndrome[0x20]; 5026 5027 u8 reserved_1[0x20]; 5028 5029 u8 enable[0x1]; 5030 u8 tag_enable[0x1]; 5031 u8 reserved_2[0x1e]; 5032 }; 5033 5034 struct mlx5_ifc_query_cong_status_in_bits { 5035 u8 opcode[0x10]; 5036 u8 reserved_0[0x10]; 5037 5038 u8 reserved_1[0x10]; 5039 u8 op_mod[0x10]; 5040 5041 u8 reserved_2[0x18]; 5042 u8 priority[0x4]; 5043 u8 cong_protocol[0x4]; 5044 5045 u8 reserved_3[0x20]; 5046 }; 5047 5048 struct mlx5_ifc_query_cong_statistics_out_bits { 5049 u8 status[0x8]; 5050 u8 reserved_0[0x18]; 5051 5052 u8 syndrome[0x20]; 5053 5054 u8 reserved_1[0x40]; 5055 5056 u8 rp_cur_flows[0x20]; 5057 5058 u8 sum_flows[0x20]; 5059 5060 u8 rp_cnp_ignored_high[0x20]; 5061 5062 u8 rp_cnp_ignored_low[0x20]; 5063 5064 u8 rp_cnp_handled_high[0x20]; 5065 5066 u8 rp_cnp_handled_low[0x20]; 5067 5068 u8 reserved_2[0x100]; 5069 5070 u8 time_stamp_high[0x20]; 5071 5072 u8 time_stamp_low[0x20]; 5073 5074 u8 accumulators_period[0x20]; 5075 5076 u8 np_ecn_marked_roce_packets_high[0x20]; 5077 5078 u8 np_ecn_marked_roce_packets_low[0x20]; 5079 5080 u8 np_cnp_sent_high[0x20]; 5081 5082 u8 np_cnp_sent_low[0x20]; 5083 5084 u8 reserved_3[0x560]; 5085 }; 5086 5087 struct mlx5_ifc_query_cong_statistics_in_bits { 5088 u8 opcode[0x10]; 5089 u8 reserved_0[0x10]; 5090 5091 u8 reserved_1[0x10]; 5092 u8 op_mod[0x10]; 5093 5094 u8 clear[0x1]; 5095 u8 reserved_2[0x1f]; 5096 5097 u8 reserved_3[0x20]; 5098 }; 5099 5100 struct mlx5_ifc_query_cong_params_out_bits { 5101 u8 status[0x8]; 5102 u8 reserved_0[0x18]; 5103 5104 u8 syndrome[0x20]; 5105 5106 u8 reserved_1[0x40]; 5107 5108 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5109 }; 5110 5111 struct mlx5_ifc_query_cong_params_in_bits { 5112 u8 opcode[0x10]; 5113 u8 reserved_0[0x10]; 5114 5115 u8 reserved_1[0x10]; 5116 u8 op_mod[0x10]; 5117 5118 u8 reserved_2[0x1c]; 5119 u8 cong_protocol[0x4]; 5120 5121 u8 reserved_3[0x20]; 5122 }; 5123 5124 struct mlx5_ifc_query_burst_size_out_bits { 5125 u8 status[0x8]; 5126 u8 reserved_0[0x18]; 5127 5128 u8 syndrome[0x20]; 5129 5130 u8 reserved_1[0x20]; 5131 5132 u8 reserved_2[0x9]; 5133 u8 device_burst_size[0x17]; 5134 }; 5135 5136 struct mlx5_ifc_query_burst_size_in_bits { 5137 u8 opcode[0x10]; 5138 u8 reserved_0[0x10]; 5139 5140 u8 reserved_1[0x10]; 5141 u8 op_mod[0x10]; 5142 5143 u8 reserved_2[0x40]; 5144 }; 5145 5146 struct mlx5_ifc_query_adapter_out_bits { 5147 u8 status[0x8]; 5148 u8 reserved_0[0x18]; 5149 5150 u8 syndrome[0x20]; 5151 5152 u8 reserved_1[0x40]; 5153 5154 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5155 }; 5156 5157 struct mlx5_ifc_query_adapter_in_bits { 5158 u8 opcode[0x10]; 5159 u8 reserved_0[0x10]; 5160 5161 u8 reserved_1[0x10]; 5162 u8 op_mod[0x10]; 5163 5164 u8 reserved_2[0x40]; 5165 }; 5166 5167 struct mlx5_ifc_qp_2rst_out_bits { 5168 u8 status[0x8]; 5169 u8 reserved_0[0x18]; 5170 5171 u8 syndrome[0x20]; 5172 5173 u8 reserved_1[0x40]; 5174 }; 5175 5176 struct mlx5_ifc_qp_2rst_in_bits { 5177 u8 opcode[0x10]; 5178 u8 reserved_0[0x10]; 5179 5180 u8 reserved_1[0x10]; 5181 u8 op_mod[0x10]; 5182 5183 u8 reserved_2[0x8]; 5184 u8 qpn[0x18]; 5185 5186 u8 reserved_3[0x20]; 5187 }; 5188 5189 struct mlx5_ifc_qp_2err_out_bits { 5190 u8 status[0x8]; 5191 u8 reserved_0[0x18]; 5192 5193 u8 syndrome[0x20]; 5194 5195 u8 reserved_1[0x40]; 5196 }; 5197 5198 struct mlx5_ifc_qp_2err_in_bits { 5199 u8 opcode[0x10]; 5200 u8 reserved_0[0x10]; 5201 5202 u8 reserved_1[0x10]; 5203 u8 op_mod[0x10]; 5204 5205 u8 reserved_2[0x8]; 5206 u8 qpn[0x18]; 5207 5208 u8 reserved_3[0x20]; 5209 }; 5210 5211 struct mlx5_ifc_para_vport_element_bits { 5212 u8 reserved_at_0[0xc]; 5213 u8 traffic_class[0x4]; 5214 u8 qos_para_vport_number[0x10]; 5215 }; 5216 5217 struct mlx5_ifc_page_fault_resume_out_bits { 5218 u8 status[0x8]; 5219 u8 reserved_0[0x18]; 5220 5221 u8 syndrome[0x20]; 5222 5223 u8 reserved_1[0x40]; 5224 }; 5225 5226 struct mlx5_ifc_page_fault_resume_in_bits { 5227 u8 opcode[0x10]; 5228 u8 reserved_0[0x10]; 5229 5230 u8 reserved_1[0x10]; 5231 u8 op_mod[0x10]; 5232 5233 u8 error[0x1]; 5234 u8 reserved_2[0x4]; 5235 u8 rdma[0x1]; 5236 u8 read_write[0x1]; 5237 u8 req_res[0x1]; 5238 u8 qpn[0x18]; 5239 5240 u8 reserved_3[0x20]; 5241 }; 5242 5243 struct mlx5_ifc_nop_out_bits { 5244 u8 status[0x8]; 5245 u8 reserved_0[0x18]; 5246 5247 u8 syndrome[0x20]; 5248 5249 u8 reserved_1[0x40]; 5250 }; 5251 5252 struct mlx5_ifc_nop_in_bits { 5253 u8 opcode[0x10]; 5254 u8 reserved_0[0x10]; 5255 5256 u8 reserved_1[0x10]; 5257 u8 op_mod[0x10]; 5258 5259 u8 reserved_2[0x40]; 5260 }; 5261 5262 struct mlx5_ifc_modify_vport_state_out_bits { 5263 u8 status[0x8]; 5264 u8 reserved_0[0x18]; 5265 5266 u8 syndrome[0x20]; 5267 5268 u8 reserved_1[0x40]; 5269 }; 5270 5271 enum { 5272 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5273 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5274 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5275 }; 5276 5277 enum { 5278 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5279 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5280 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5281 }; 5282 5283 struct mlx5_ifc_modify_vport_state_in_bits { 5284 u8 opcode[0x10]; 5285 u8 reserved_0[0x10]; 5286 5287 u8 reserved_1[0x10]; 5288 u8 op_mod[0x10]; 5289 5290 u8 other_vport[0x1]; 5291 u8 reserved_2[0xf]; 5292 u8 vport_number[0x10]; 5293 5294 u8 reserved_3[0x18]; 5295 u8 admin_state[0x4]; 5296 u8 reserved_4[0x4]; 5297 }; 5298 5299 struct mlx5_ifc_modify_tis_out_bits { 5300 u8 status[0x8]; 5301 u8 reserved_0[0x18]; 5302 5303 u8 syndrome[0x20]; 5304 5305 u8 reserved_1[0x40]; 5306 }; 5307 5308 struct mlx5_ifc_modify_tis_bitmask_bits { 5309 u8 reserved_at_0[0x20]; 5310 5311 u8 reserved_at_20[0x1d]; 5312 u8 lag_tx_port_affinity[0x1]; 5313 u8 strict_lag_tx_port_affinity[0x1]; 5314 u8 prio[0x1]; 5315 }; 5316 5317 struct mlx5_ifc_modify_tis_in_bits { 5318 u8 opcode[0x10]; 5319 u8 reserved_0[0x10]; 5320 5321 u8 reserved_1[0x10]; 5322 u8 op_mod[0x10]; 5323 5324 u8 reserved_2[0x8]; 5325 u8 tisn[0x18]; 5326 5327 u8 reserved_3[0x20]; 5328 5329 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5330 5331 u8 reserved_4[0x40]; 5332 5333 struct mlx5_ifc_tisc_bits ctx; 5334 }; 5335 5336 struct mlx5_ifc_modify_tir_out_bits { 5337 u8 status[0x8]; 5338 u8 reserved_0[0x18]; 5339 5340 u8 syndrome[0x20]; 5341 5342 u8 reserved_1[0x40]; 5343 }; 5344 5345 enum 5346 { 5347 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5348 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5349 }; 5350 5351 struct mlx5_ifc_modify_tir_in_bits { 5352 u8 opcode[0x10]; 5353 u8 reserved_0[0x10]; 5354 5355 u8 reserved_1[0x10]; 5356 u8 op_mod[0x10]; 5357 5358 u8 reserved_2[0x8]; 5359 u8 tirn[0x18]; 5360 5361 u8 reserved_3[0x20]; 5362 5363 u8 modify_bitmask[0x40]; 5364 5365 u8 reserved_4[0x40]; 5366 5367 struct mlx5_ifc_tirc_bits tir_context; 5368 }; 5369 5370 struct mlx5_ifc_modify_sq_out_bits { 5371 u8 status[0x8]; 5372 u8 reserved_0[0x18]; 5373 5374 u8 syndrome[0x20]; 5375 5376 u8 reserved_1[0x40]; 5377 }; 5378 5379 struct mlx5_ifc_modify_sq_in_bits { 5380 u8 opcode[0x10]; 5381 u8 reserved_0[0x10]; 5382 5383 u8 reserved_1[0x10]; 5384 u8 op_mod[0x10]; 5385 5386 u8 sq_state[0x4]; 5387 u8 reserved_2[0x4]; 5388 u8 sqn[0x18]; 5389 5390 u8 reserved_3[0x20]; 5391 5392 u8 modify_bitmask[0x40]; 5393 5394 u8 reserved_4[0x40]; 5395 5396 struct mlx5_ifc_sqc_bits ctx; 5397 }; 5398 5399 struct mlx5_ifc_modify_scheduling_element_out_bits { 5400 u8 status[0x8]; 5401 u8 reserved_at_8[0x18]; 5402 5403 u8 syndrome[0x20]; 5404 5405 u8 reserved_at_40[0x1c0]; 5406 }; 5407 5408 enum { 5409 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5410 }; 5411 5412 enum { 5413 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5414 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5415 }; 5416 5417 struct mlx5_ifc_modify_scheduling_element_in_bits { 5418 u8 opcode[0x10]; 5419 u8 reserved_at_10[0x10]; 5420 5421 u8 reserved_at_20[0x10]; 5422 u8 op_mod[0x10]; 5423 5424 u8 scheduling_hierarchy[0x8]; 5425 u8 reserved_at_48[0x18]; 5426 5427 u8 scheduling_element_id[0x20]; 5428 5429 u8 reserved_at_80[0x20]; 5430 5431 u8 modify_bitmask[0x20]; 5432 5433 u8 reserved_at_c0[0x40]; 5434 5435 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5436 5437 u8 reserved_at_300[0x100]; 5438 }; 5439 5440 struct mlx5_ifc_modify_rqt_out_bits { 5441 u8 status[0x8]; 5442 u8 reserved_0[0x18]; 5443 5444 u8 syndrome[0x20]; 5445 5446 u8 reserved_1[0x40]; 5447 }; 5448 5449 struct mlx5_ifc_modify_rqt_in_bits { 5450 u8 opcode[0x10]; 5451 u8 reserved_0[0x10]; 5452 5453 u8 reserved_1[0x10]; 5454 u8 op_mod[0x10]; 5455 5456 u8 reserved_2[0x8]; 5457 u8 rqtn[0x18]; 5458 5459 u8 reserved_3[0x20]; 5460 5461 u8 modify_bitmask[0x40]; 5462 5463 u8 reserved_4[0x40]; 5464 5465 struct mlx5_ifc_rqtc_bits ctx; 5466 }; 5467 5468 struct mlx5_ifc_modify_rq_out_bits { 5469 u8 status[0x8]; 5470 u8 reserved_0[0x18]; 5471 5472 u8 syndrome[0x20]; 5473 5474 u8 reserved_1[0x40]; 5475 }; 5476 5477 enum { 5478 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5479 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5480 }; 5481 5482 struct mlx5_ifc_modify_rq_in_bits { 5483 u8 opcode[0x10]; 5484 u8 reserved_0[0x10]; 5485 5486 u8 reserved_1[0x10]; 5487 u8 op_mod[0x10]; 5488 5489 u8 rq_state[0x4]; 5490 u8 reserved_2[0x4]; 5491 u8 rqn[0x18]; 5492 5493 u8 reserved_3[0x20]; 5494 5495 u8 modify_bitmask[0x40]; 5496 5497 u8 reserved_4[0x40]; 5498 5499 struct mlx5_ifc_rqc_bits ctx; 5500 }; 5501 5502 struct mlx5_ifc_modify_rmp_out_bits { 5503 u8 status[0x8]; 5504 u8 reserved_0[0x18]; 5505 5506 u8 syndrome[0x20]; 5507 5508 u8 reserved_1[0x40]; 5509 }; 5510 5511 struct mlx5_ifc_rmp_bitmask_bits { 5512 u8 reserved[0x20]; 5513 5514 u8 reserved1[0x1f]; 5515 u8 lwm[0x1]; 5516 }; 5517 5518 struct mlx5_ifc_modify_rmp_in_bits { 5519 u8 opcode[0x10]; 5520 u8 reserved_0[0x10]; 5521 5522 u8 reserved_1[0x10]; 5523 u8 op_mod[0x10]; 5524 5525 u8 rmp_state[0x4]; 5526 u8 reserved_2[0x4]; 5527 u8 rmpn[0x18]; 5528 5529 u8 reserved_3[0x20]; 5530 5531 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5532 5533 u8 reserved_4[0x40]; 5534 5535 struct mlx5_ifc_rmpc_bits ctx; 5536 }; 5537 5538 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5539 u8 status[0x8]; 5540 u8 reserved_0[0x18]; 5541 5542 u8 syndrome[0x20]; 5543 5544 u8 reserved_1[0x40]; 5545 }; 5546 5547 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5548 u8 reserved_0[0x14]; 5549 u8 disable_uc_local_lb[0x1]; 5550 u8 disable_mc_local_lb[0x1]; 5551 u8 node_guid[0x1]; 5552 u8 port_guid[0x1]; 5553 u8 min_wqe_inline_mode[0x1]; 5554 u8 mtu[0x1]; 5555 u8 change_event[0x1]; 5556 u8 promisc[0x1]; 5557 u8 permanent_address[0x1]; 5558 u8 addresses_list[0x1]; 5559 u8 roce_en[0x1]; 5560 u8 reserved_1[0x1]; 5561 }; 5562 5563 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5564 u8 opcode[0x10]; 5565 u8 reserved_0[0x10]; 5566 5567 u8 reserved_1[0x10]; 5568 u8 op_mod[0x10]; 5569 5570 u8 other_vport[0x1]; 5571 u8 reserved_2[0xf]; 5572 u8 vport_number[0x10]; 5573 5574 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5575 5576 u8 reserved_3[0x780]; 5577 5578 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5579 }; 5580 5581 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5582 u8 status[0x8]; 5583 u8 reserved_0[0x18]; 5584 5585 u8 syndrome[0x20]; 5586 5587 u8 reserved_1[0x40]; 5588 }; 5589 5590 struct mlx5_ifc_grh_bits { 5591 u8 ip_version[4]; 5592 u8 traffic_class[8]; 5593 u8 flow_label[20]; 5594 u8 payload_length[16]; 5595 u8 next_header[8]; 5596 u8 hop_limit[8]; 5597 u8 sgid[128]; 5598 u8 dgid[128]; 5599 }; 5600 5601 struct mlx5_ifc_bth_bits { 5602 u8 opcode[8]; 5603 u8 se[1]; 5604 u8 migreq[1]; 5605 u8 pad_count[2]; 5606 u8 tver[4]; 5607 u8 p_key[16]; 5608 u8 reserved8[8]; 5609 u8 dest_qp[24]; 5610 u8 ack_req[1]; 5611 u8 reserved7[7]; 5612 u8 psn[24]; 5613 }; 5614 5615 struct mlx5_ifc_aeth_bits { 5616 u8 syndrome[8]; 5617 u8 msn[24]; 5618 }; 5619 5620 struct mlx5_ifc_dceth_bits { 5621 u8 reserved0[8]; 5622 u8 session_id[24]; 5623 u8 reserved1[8]; 5624 u8 dci_dct[24]; 5625 }; 5626 5627 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5628 u8 opcode[0x10]; 5629 u8 reserved_0[0x10]; 5630 5631 u8 reserved_1[0x10]; 5632 u8 op_mod[0x10]; 5633 5634 u8 other_vport[0x1]; 5635 u8 reserved_2[0xb]; 5636 u8 port_num[0x4]; 5637 u8 vport_number[0x10]; 5638 5639 u8 reserved_3[0x20]; 5640 5641 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5642 }; 5643 5644 struct mlx5_ifc_modify_flow_table_out_bits { 5645 u8 status[0x8]; 5646 u8 reserved_at_8[0x18]; 5647 5648 u8 syndrome[0x20]; 5649 5650 u8 reserved_at_40[0x40]; 5651 }; 5652 5653 enum { 5654 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 5655 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 5656 }; 5657 5658 struct mlx5_ifc_modify_flow_table_in_bits { 5659 u8 opcode[0x10]; 5660 u8 reserved_at_10[0x10]; 5661 5662 u8 reserved_at_20[0x10]; 5663 u8 op_mod[0x10]; 5664 5665 u8 other_vport[0x1]; 5666 u8 reserved_at_41[0xf]; 5667 u8 vport_number[0x10]; 5668 5669 u8 reserved_at_60[0x10]; 5670 u8 modify_field_select[0x10]; 5671 5672 u8 table_type[0x8]; 5673 u8 reserved_at_88[0x18]; 5674 5675 u8 reserved_at_a0[0x8]; 5676 u8 table_id[0x18]; 5677 5678 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5679 }; 5680 5681 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5682 u8 status[0x8]; 5683 u8 reserved_0[0x18]; 5684 5685 u8 syndrome[0x20]; 5686 5687 u8 reserved_1[0x40]; 5688 }; 5689 5690 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5691 u8 reserved[0x1c]; 5692 u8 vport_cvlan_insert[0x1]; 5693 u8 vport_svlan_insert[0x1]; 5694 u8 vport_cvlan_strip[0x1]; 5695 u8 vport_svlan_strip[0x1]; 5696 }; 5697 5698 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5699 u8 opcode[0x10]; 5700 u8 reserved_0[0x10]; 5701 5702 u8 reserved_1[0x10]; 5703 u8 op_mod[0x10]; 5704 5705 u8 other_vport[0x1]; 5706 u8 reserved_2[0xf]; 5707 u8 vport_number[0x10]; 5708 5709 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5710 5711 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5712 }; 5713 5714 struct mlx5_ifc_modify_cq_out_bits { 5715 u8 status[0x8]; 5716 u8 reserved_0[0x18]; 5717 5718 u8 syndrome[0x20]; 5719 5720 u8 reserved_1[0x40]; 5721 }; 5722 5723 enum { 5724 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5725 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5726 }; 5727 5728 struct mlx5_ifc_modify_cq_in_bits { 5729 u8 opcode[0x10]; 5730 u8 reserved_0[0x10]; 5731 5732 u8 reserved_1[0x10]; 5733 u8 op_mod[0x10]; 5734 5735 u8 reserved_2[0x8]; 5736 u8 cqn[0x18]; 5737 5738 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5739 5740 struct mlx5_ifc_cqc_bits cq_context; 5741 5742 u8 reserved_3[0x600]; 5743 5744 u8 pas[0][0x40]; 5745 }; 5746 5747 struct mlx5_ifc_modify_cong_status_out_bits { 5748 u8 status[0x8]; 5749 u8 reserved_0[0x18]; 5750 5751 u8 syndrome[0x20]; 5752 5753 u8 reserved_1[0x40]; 5754 }; 5755 5756 struct mlx5_ifc_modify_cong_status_in_bits { 5757 u8 opcode[0x10]; 5758 u8 reserved_0[0x10]; 5759 5760 u8 reserved_1[0x10]; 5761 u8 op_mod[0x10]; 5762 5763 u8 reserved_2[0x18]; 5764 u8 priority[0x4]; 5765 u8 cong_protocol[0x4]; 5766 5767 u8 enable[0x1]; 5768 u8 tag_enable[0x1]; 5769 u8 reserved_3[0x1e]; 5770 }; 5771 5772 struct mlx5_ifc_modify_cong_params_out_bits { 5773 u8 status[0x8]; 5774 u8 reserved_0[0x18]; 5775 5776 u8 syndrome[0x20]; 5777 5778 u8 reserved_1[0x40]; 5779 }; 5780 5781 struct mlx5_ifc_modify_cong_params_in_bits { 5782 u8 opcode[0x10]; 5783 u8 reserved_0[0x10]; 5784 5785 u8 reserved_1[0x10]; 5786 u8 op_mod[0x10]; 5787 5788 u8 reserved_2[0x1c]; 5789 u8 cong_protocol[0x4]; 5790 5791 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5792 5793 u8 reserved_3[0x80]; 5794 5795 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5796 }; 5797 5798 struct mlx5_ifc_manage_pages_out_bits { 5799 u8 status[0x8]; 5800 u8 reserved_0[0x18]; 5801 5802 u8 syndrome[0x20]; 5803 5804 u8 output_num_entries[0x20]; 5805 5806 u8 reserved_1[0x20]; 5807 5808 u8 pas[0][0x40]; 5809 }; 5810 5811 enum { 5812 MLX5_PAGES_CANT_GIVE = 0x0, 5813 MLX5_PAGES_GIVE = 0x1, 5814 MLX5_PAGES_TAKE = 0x2, 5815 }; 5816 5817 struct mlx5_ifc_manage_pages_in_bits { 5818 u8 opcode[0x10]; 5819 u8 reserved_0[0x10]; 5820 5821 u8 reserved_1[0x10]; 5822 u8 op_mod[0x10]; 5823 5824 u8 reserved_2[0x10]; 5825 u8 function_id[0x10]; 5826 5827 u8 input_num_entries[0x20]; 5828 5829 u8 pas[0][0x40]; 5830 }; 5831 5832 struct mlx5_ifc_mad_ifc_out_bits { 5833 u8 status[0x8]; 5834 u8 reserved_0[0x18]; 5835 5836 u8 syndrome[0x20]; 5837 5838 u8 reserved_1[0x40]; 5839 5840 u8 response_mad_packet[256][0x8]; 5841 }; 5842 5843 struct mlx5_ifc_mad_ifc_in_bits { 5844 u8 opcode[0x10]; 5845 u8 reserved_0[0x10]; 5846 5847 u8 reserved_1[0x10]; 5848 u8 op_mod[0x10]; 5849 5850 u8 remote_lid[0x10]; 5851 u8 reserved_2[0x8]; 5852 u8 port[0x8]; 5853 5854 u8 reserved_3[0x20]; 5855 5856 u8 mad[256][0x8]; 5857 }; 5858 5859 struct mlx5_ifc_init_hca_out_bits { 5860 u8 status[0x8]; 5861 u8 reserved_0[0x18]; 5862 5863 u8 syndrome[0x20]; 5864 5865 u8 reserved_1[0x40]; 5866 }; 5867 5868 enum { 5869 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 5870 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 5871 }; 5872 5873 struct mlx5_ifc_init_hca_in_bits { 5874 u8 opcode[0x10]; 5875 u8 reserved_0[0x10]; 5876 5877 u8 reserved_1[0x10]; 5878 u8 op_mod[0x10]; 5879 5880 u8 reserved_2[0x40]; 5881 }; 5882 5883 struct mlx5_ifc_init2rtr_qp_out_bits { 5884 u8 status[0x8]; 5885 u8 reserved_0[0x18]; 5886 5887 u8 syndrome[0x20]; 5888 5889 u8 reserved_1[0x40]; 5890 }; 5891 5892 struct mlx5_ifc_init2rtr_qp_in_bits { 5893 u8 opcode[0x10]; 5894 u8 reserved_0[0x10]; 5895 5896 u8 reserved_1[0x10]; 5897 u8 op_mod[0x10]; 5898 5899 u8 reserved_2[0x8]; 5900 u8 qpn[0x18]; 5901 5902 u8 reserved_3[0x20]; 5903 5904 u8 opt_param_mask[0x20]; 5905 5906 u8 reserved_4[0x20]; 5907 5908 struct mlx5_ifc_qpc_bits qpc; 5909 5910 u8 reserved_5[0x80]; 5911 }; 5912 5913 struct mlx5_ifc_init2init_qp_out_bits { 5914 u8 status[0x8]; 5915 u8 reserved_0[0x18]; 5916 5917 u8 syndrome[0x20]; 5918 5919 u8 reserved_1[0x40]; 5920 }; 5921 5922 struct mlx5_ifc_init2init_qp_in_bits { 5923 u8 opcode[0x10]; 5924 u8 reserved_0[0x10]; 5925 5926 u8 reserved_1[0x10]; 5927 u8 op_mod[0x10]; 5928 5929 u8 reserved_2[0x8]; 5930 u8 qpn[0x18]; 5931 5932 u8 reserved_3[0x20]; 5933 5934 u8 opt_param_mask[0x20]; 5935 5936 u8 reserved_4[0x20]; 5937 5938 struct mlx5_ifc_qpc_bits qpc; 5939 5940 u8 reserved_5[0x80]; 5941 }; 5942 5943 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5944 u8 status[0x8]; 5945 u8 reserved_0[0x18]; 5946 5947 u8 syndrome[0x20]; 5948 5949 u8 reserved_1[0x40]; 5950 5951 u8 packet_headers_log[128][0x8]; 5952 5953 u8 packet_syndrome[64][0x8]; 5954 }; 5955 5956 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5957 u8 opcode[0x10]; 5958 u8 reserved_0[0x10]; 5959 5960 u8 reserved_1[0x10]; 5961 u8 op_mod[0x10]; 5962 5963 u8 reserved_2[0x40]; 5964 }; 5965 5966 struct mlx5_ifc_gen_eqe_in_bits { 5967 u8 opcode[0x10]; 5968 u8 reserved_0[0x10]; 5969 5970 u8 reserved_1[0x10]; 5971 u8 op_mod[0x10]; 5972 5973 u8 reserved_2[0x18]; 5974 u8 eq_number[0x8]; 5975 5976 u8 reserved_3[0x20]; 5977 5978 u8 eqe[64][0x8]; 5979 }; 5980 5981 struct mlx5_ifc_gen_eq_out_bits { 5982 u8 status[0x8]; 5983 u8 reserved_0[0x18]; 5984 5985 u8 syndrome[0x20]; 5986 5987 u8 reserved_1[0x40]; 5988 }; 5989 5990 struct mlx5_ifc_enable_hca_out_bits { 5991 u8 status[0x8]; 5992 u8 reserved_0[0x18]; 5993 5994 u8 syndrome[0x20]; 5995 5996 u8 reserved_1[0x20]; 5997 }; 5998 5999 struct mlx5_ifc_enable_hca_in_bits { 6000 u8 opcode[0x10]; 6001 u8 reserved_0[0x10]; 6002 6003 u8 reserved_1[0x10]; 6004 u8 op_mod[0x10]; 6005 6006 u8 reserved_2[0x10]; 6007 u8 function_id[0x10]; 6008 6009 u8 reserved_3[0x20]; 6010 }; 6011 6012 struct mlx5_ifc_drain_dct_out_bits { 6013 u8 status[0x8]; 6014 u8 reserved_0[0x18]; 6015 6016 u8 syndrome[0x20]; 6017 6018 u8 reserved_1[0x40]; 6019 }; 6020 6021 struct mlx5_ifc_drain_dct_in_bits { 6022 u8 opcode[0x10]; 6023 u8 reserved_0[0x10]; 6024 6025 u8 reserved_1[0x10]; 6026 u8 op_mod[0x10]; 6027 6028 u8 reserved_2[0x8]; 6029 u8 dctn[0x18]; 6030 6031 u8 reserved_3[0x20]; 6032 }; 6033 6034 struct mlx5_ifc_disable_hca_out_bits { 6035 u8 status[0x8]; 6036 u8 reserved_0[0x18]; 6037 6038 u8 syndrome[0x20]; 6039 6040 u8 reserved_1[0x20]; 6041 }; 6042 6043 struct mlx5_ifc_disable_hca_in_bits { 6044 u8 opcode[0x10]; 6045 u8 reserved_0[0x10]; 6046 6047 u8 reserved_1[0x10]; 6048 u8 op_mod[0x10]; 6049 6050 u8 reserved_2[0x10]; 6051 u8 function_id[0x10]; 6052 6053 u8 reserved_3[0x20]; 6054 }; 6055 6056 struct mlx5_ifc_detach_from_mcg_out_bits { 6057 u8 status[0x8]; 6058 u8 reserved_0[0x18]; 6059 6060 u8 syndrome[0x20]; 6061 6062 u8 reserved_1[0x40]; 6063 }; 6064 6065 struct mlx5_ifc_detach_from_mcg_in_bits { 6066 u8 opcode[0x10]; 6067 u8 reserved_0[0x10]; 6068 6069 u8 reserved_1[0x10]; 6070 u8 op_mod[0x10]; 6071 6072 u8 reserved_2[0x8]; 6073 u8 qpn[0x18]; 6074 6075 u8 reserved_3[0x20]; 6076 6077 u8 multicast_gid[16][0x8]; 6078 }; 6079 6080 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6081 u8 status[0x8]; 6082 u8 reserved_0[0x18]; 6083 6084 u8 syndrome[0x20]; 6085 6086 u8 reserved_1[0x40]; 6087 }; 6088 6089 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6090 u8 opcode[0x10]; 6091 u8 reserved_0[0x10]; 6092 6093 u8 reserved_1[0x10]; 6094 u8 op_mod[0x10]; 6095 6096 u8 reserved_2[0x8]; 6097 u8 xrc_srqn[0x18]; 6098 6099 u8 reserved_3[0x20]; 6100 }; 6101 6102 struct mlx5_ifc_destroy_tis_out_bits { 6103 u8 status[0x8]; 6104 u8 reserved_0[0x18]; 6105 6106 u8 syndrome[0x20]; 6107 6108 u8 reserved_1[0x40]; 6109 }; 6110 6111 struct mlx5_ifc_destroy_tis_in_bits { 6112 u8 opcode[0x10]; 6113 u8 reserved_0[0x10]; 6114 6115 u8 reserved_1[0x10]; 6116 u8 op_mod[0x10]; 6117 6118 u8 reserved_2[0x8]; 6119 u8 tisn[0x18]; 6120 6121 u8 reserved_3[0x20]; 6122 }; 6123 6124 struct mlx5_ifc_destroy_tir_out_bits { 6125 u8 status[0x8]; 6126 u8 reserved_0[0x18]; 6127 6128 u8 syndrome[0x20]; 6129 6130 u8 reserved_1[0x40]; 6131 }; 6132 6133 struct mlx5_ifc_destroy_tir_in_bits { 6134 u8 opcode[0x10]; 6135 u8 reserved_0[0x10]; 6136 6137 u8 reserved_1[0x10]; 6138 u8 op_mod[0x10]; 6139 6140 u8 reserved_2[0x8]; 6141 u8 tirn[0x18]; 6142 6143 u8 reserved_3[0x20]; 6144 }; 6145 6146 struct mlx5_ifc_destroy_srq_out_bits { 6147 u8 status[0x8]; 6148 u8 reserved_0[0x18]; 6149 6150 u8 syndrome[0x20]; 6151 6152 u8 reserved_1[0x40]; 6153 }; 6154 6155 struct mlx5_ifc_destroy_srq_in_bits { 6156 u8 opcode[0x10]; 6157 u8 reserved_0[0x10]; 6158 6159 u8 reserved_1[0x10]; 6160 u8 op_mod[0x10]; 6161 6162 u8 reserved_2[0x8]; 6163 u8 srqn[0x18]; 6164 6165 u8 reserved_3[0x20]; 6166 }; 6167 6168 struct mlx5_ifc_destroy_sq_out_bits { 6169 u8 status[0x8]; 6170 u8 reserved_0[0x18]; 6171 6172 u8 syndrome[0x20]; 6173 6174 u8 reserved_1[0x40]; 6175 }; 6176 6177 struct mlx5_ifc_destroy_sq_in_bits { 6178 u8 opcode[0x10]; 6179 u8 reserved_0[0x10]; 6180 6181 u8 reserved_1[0x10]; 6182 u8 op_mod[0x10]; 6183 6184 u8 reserved_2[0x8]; 6185 u8 sqn[0x18]; 6186 6187 u8 reserved_3[0x20]; 6188 }; 6189 6190 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6191 u8 status[0x8]; 6192 u8 reserved_at_8[0x18]; 6193 6194 u8 syndrome[0x20]; 6195 6196 u8 reserved_at_40[0x1c0]; 6197 }; 6198 6199 enum { 6200 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6201 }; 6202 6203 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6204 u8 opcode[0x10]; 6205 u8 reserved_at_10[0x10]; 6206 6207 u8 reserved_at_20[0x10]; 6208 u8 op_mod[0x10]; 6209 6210 u8 scheduling_hierarchy[0x8]; 6211 u8 reserved_at_48[0x18]; 6212 6213 u8 scheduling_element_id[0x20]; 6214 6215 u8 reserved_at_80[0x180]; 6216 }; 6217 6218 struct mlx5_ifc_destroy_rqt_out_bits { 6219 u8 status[0x8]; 6220 u8 reserved_0[0x18]; 6221 6222 u8 syndrome[0x20]; 6223 6224 u8 reserved_1[0x40]; 6225 }; 6226 6227 struct mlx5_ifc_destroy_rqt_in_bits { 6228 u8 opcode[0x10]; 6229 u8 reserved_0[0x10]; 6230 6231 u8 reserved_1[0x10]; 6232 u8 op_mod[0x10]; 6233 6234 u8 reserved_2[0x8]; 6235 u8 rqtn[0x18]; 6236 6237 u8 reserved_3[0x20]; 6238 }; 6239 6240 struct mlx5_ifc_destroy_rq_out_bits { 6241 u8 status[0x8]; 6242 u8 reserved_0[0x18]; 6243 6244 u8 syndrome[0x20]; 6245 6246 u8 reserved_1[0x40]; 6247 }; 6248 6249 struct mlx5_ifc_destroy_rq_in_bits { 6250 u8 opcode[0x10]; 6251 u8 reserved_0[0x10]; 6252 6253 u8 reserved_1[0x10]; 6254 u8 op_mod[0x10]; 6255 6256 u8 reserved_2[0x8]; 6257 u8 rqn[0x18]; 6258 6259 u8 reserved_3[0x20]; 6260 }; 6261 6262 struct mlx5_ifc_destroy_rmp_out_bits { 6263 u8 status[0x8]; 6264 u8 reserved_0[0x18]; 6265 6266 u8 syndrome[0x20]; 6267 6268 u8 reserved_1[0x40]; 6269 }; 6270 6271 struct mlx5_ifc_destroy_rmp_in_bits { 6272 u8 opcode[0x10]; 6273 u8 reserved_0[0x10]; 6274 6275 u8 reserved_1[0x10]; 6276 u8 op_mod[0x10]; 6277 6278 u8 reserved_2[0x8]; 6279 u8 rmpn[0x18]; 6280 6281 u8 reserved_3[0x20]; 6282 }; 6283 6284 struct mlx5_ifc_destroy_qp_out_bits { 6285 u8 status[0x8]; 6286 u8 reserved_0[0x18]; 6287 6288 u8 syndrome[0x20]; 6289 6290 u8 reserved_1[0x40]; 6291 }; 6292 6293 struct mlx5_ifc_destroy_qp_in_bits { 6294 u8 opcode[0x10]; 6295 u8 reserved_0[0x10]; 6296 6297 u8 reserved_1[0x10]; 6298 u8 op_mod[0x10]; 6299 6300 u8 reserved_2[0x8]; 6301 u8 qpn[0x18]; 6302 6303 u8 reserved_3[0x20]; 6304 }; 6305 6306 struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6307 u8 status[0x8]; 6308 u8 reserved_at_8[0x18]; 6309 6310 u8 syndrome[0x20]; 6311 6312 u8 reserved_at_40[0x1c0]; 6313 }; 6314 6315 struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6316 u8 opcode[0x10]; 6317 u8 reserved_at_10[0x10]; 6318 6319 u8 reserved_at_20[0x10]; 6320 u8 op_mod[0x10]; 6321 6322 u8 reserved_at_40[0x20]; 6323 6324 u8 reserved_at_60[0x10]; 6325 u8 qos_para_vport_number[0x10]; 6326 6327 u8 reserved_at_80[0x180]; 6328 }; 6329 6330 struct mlx5_ifc_destroy_psv_out_bits { 6331 u8 status[0x8]; 6332 u8 reserved_0[0x18]; 6333 6334 u8 syndrome[0x20]; 6335 6336 u8 reserved_1[0x40]; 6337 }; 6338 6339 struct mlx5_ifc_destroy_psv_in_bits { 6340 u8 opcode[0x10]; 6341 u8 reserved_0[0x10]; 6342 6343 u8 reserved_1[0x10]; 6344 u8 op_mod[0x10]; 6345 6346 u8 reserved_2[0x8]; 6347 u8 psvn[0x18]; 6348 6349 u8 reserved_3[0x20]; 6350 }; 6351 6352 struct mlx5_ifc_destroy_mkey_out_bits { 6353 u8 status[0x8]; 6354 u8 reserved_0[0x18]; 6355 6356 u8 syndrome[0x20]; 6357 6358 u8 reserved_1[0x40]; 6359 }; 6360 6361 struct mlx5_ifc_destroy_mkey_in_bits { 6362 u8 opcode[0x10]; 6363 u8 reserved_0[0x10]; 6364 6365 u8 reserved_1[0x10]; 6366 u8 op_mod[0x10]; 6367 6368 u8 reserved_2[0x8]; 6369 u8 mkey_index[0x18]; 6370 6371 u8 reserved_3[0x20]; 6372 }; 6373 6374 struct mlx5_ifc_destroy_flow_table_out_bits { 6375 u8 status[0x8]; 6376 u8 reserved_0[0x18]; 6377 6378 u8 syndrome[0x20]; 6379 6380 u8 reserved_1[0x40]; 6381 }; 6382 6383 struct mlx5_ifc_destroy_flow_table_in_bits { 6384 u8 opcode[0x10]; 6385 u8 reserved_0[0x10]; 6386 6387 u8 reserved_1[0x10]; 6388 u8 op_mod[0x10]; 6389 6390 u8 other_vport[0x1]; 6391 u8 reserved_2[0xf]; 6392 u8 vport_number[0x10]; 6393 6394 u8 reserved_3[0x20]; 6395 6396 u8 table_type[0x8]; 6397 u8 reserved_4[0x18]; 6398 6399 u8 reserved_5[0x8]; 6400 u8 table_id[0x18]; 6401 6402 u8 reserved_6[0x140]; 6403 }; 6404 6405 struct mlx5_ifc_destroy_flow_group_out_bits { 6406 u8 status[0x8]; 6407 u8 reserved_0[0x18]; 6408 6409 u8 syndrome[0x20]; 6410 6411 u8 reserved_1[0x40]; 6412 }; 6413 6414 struct mlx5_ifc_destroy_flow_group_in_bits { 6415 u8 opcode[0x10]; 6416 u8 reserved_0[0x10]; 6417 6418 u8 reserved_1[0x10]; 6419 u8 op_mod[0x10]; 6420 6421 u8 other_vport[0x1]; 6422 u8 reserved_2[0xf]; 6423 u8 vport_number[0x10]; 6424 6425 u8 reserved_3[0x20]; 6426 6427 u8 table_type[0x8]; 6428 u8 reserved_4[0x18]; 6429 6430 u8 reserved_5[0x8]; 6431 u8 table_id[0x18]; 6432 6433 u8 group_id[0x20]; 6434 6435 u8 reserved_6[0x120]; 6436 }; 6437 6438 struct mlx5_ifc_destroy_eq_out_bits { 6439 u8 status[0x8]; 6440 u8 reserved_0[0x18]; 6441 6442 u8 syndrome[0x20]; 6443 6444 u8 reserved_1[0x40]; 6445 }; 6446 6447 struct mlx5_ifc_destroy_eq_in_bits { 6448 u8 opcode[0x10]; 6449 u8 reserved_0[0x10]; 6450 6451 u8 reserved_1[0x10]; 6452 u8 op_mod[0x10]; 6453 6454 u8 reserved_2[0x18]; 6455 u8 eq_number[0x8]; 6456 6457 u8 reserved_3[0x20]; 6458 }; 6459 6460 struct mlx5_ifc_destroy_dct_out_bits { 6461 u8 status[0x8]; 6462 u8 reserved_0[0x18]; 6463 6464 u8 syndrome[0x20]; 6465 6466 u8 reserved_1[0x40]; 6467 }; 6468 6469 struct mlx5_ifc_destroy_dct_in_bits { 6470 u8 opcode[0x10]; 6471 u8 reserved_0[0x10]; 6472 6473 u8 reserved_1[0x10]; 6474 u8 op_mod[0x10]; 6475 6476 u8 reserved_2[0x8]; 6477 u8 dctn[0x18]; 6478 6479 u8 reserved_3[0x20]; 6480 }; 6481 6482 struct mlx5_ifc_destroy_cq_out_bits { 6483 u8 status[0x8]; 6484 u8 reserved_0[0x18]; 6485 6486 u8 syndrome[0x20]; 6487 6488 u8 reserved_1[0x40]; 6489 }; 6490 6491 struct mlx5_ifc_destroy_cq_in_bits { 6492 u8 opcode[0x10]; 6493 u8 reserved_0[0x10]; 6494 6495 u8 reserved_1[0x10]; 6496 u8 op_mod[0x10]; 6497 6498 u8 reserved_2[0x8]; 6499 u8 cqn[0x18]; 6500 6501 u8 reserved_3[0x20]; 6502 }; 6503 6504 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6505 u8 status[0x8]; 6506 u8 reserved_0[0x18]; 6507 6508 u8 syndrome[0x20]; 6509 6510 u8 reserved_1[0x40]; 6511 }; 6512 6513 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6514 u8 opcode[0x10]; 6515 u8 reserved_0[0x10]; 6516 6517 u8 reserved_1[0x10]; 6518 u8 op_mod[0x10]; 6519 6520 u8 reserved_2[0x20]; 6521 6522 u8 reserved_3[0x10]; 6523 u8 vxlan_udp_port[0x10]; 6524 }; 6525 6526 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6527 u8 status[0x8]; 6528 u8 reserved_0[0x18]; 6529 6530 u8 syndrome[0x20]; 6531 6532 u8 reserved_1[0x40]; 6533 }; 6534 6535 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6536 u8 opcode[0x10]; 6537 u8 reserved_0[0x10]; 6538 6539 u8 reserved_1[0x10]; 6540 u8 op_mod[0x10]; 6541 6542 u8 reserved_2[0x60]; 6543 6544 u8 reserved_3[0x8]; 6545 u8 table_index[0x18]; 6546 6547 u8 reserved_4[0x140]; 6548 }; 6549 6550 struct mlx5_ifc_delete_fte_out_bits { 6551 u8 status[0x8]; 6552 u8 reserved_0[0x18]; 6553 6554 u8 syndrome[0x20]; 6555 6556 u8 reserved_1[0x40]; 6557 }; 6558 6559 struct mlx5_ifc_delete_fte_in_bits { 6560 u8 opcode[0x10]; 6561 u8 reserved_0[0x10]; 6562 6563 u8 reserved_1[0x10]; 6564 u8 op_mod[0x10]; 6565 6566 u8 other_vport[0x1]; 6567 u8 reserved_2[0xf]; 6568 u8 vport_number[0x10]; 6569 6570 u8 reserved_3[0x20]; 6571 6572 u8 table_type[0x8]; 6573 u8 reserved_4[0x18]; 6574 6575 u8 reserved_5[0x8]; 6576 u8 table_id[0x18]; 6577 6578 u8 reserved_6[0x40]; 6579 6580 u8 flow_index[0x20]; 6581 6582 u8 reserved_7[0xe0]; 6583 }; 6584 6585 struct mlx5_ifc_dealloc_xrcd_out_bits { 6586 u8 status[0x8]; 6587 u8 reserved_0[0x18]; 6588 6589 u8 syndrome[0x20]; 6590 6591 u8 reserved_1[0x40]; 6592 }; 6593 6594 struct mlx5_ifc_dealloc_xrcd_in_bits { 6595 u8 opcode[0x10]; 6596 u8 reserved_0[0x10]; 6597 6598 u8 reserved_1[0x10]; 6599 u8 op_mod[0x10]; 6600 6601 u8 reserved_2[0x8]; 6602 u8 xrcd[0x18]; 6603 6604 u8 reserved_3[0x20]; 6605 }; 6606 6607 struct mlx5_ifc_dealloc_uar_out_bits { 6608 u8 status[0x8]; 6609 u8 reserved_0[0x18]; 6610 6611 u8 syndrome[0x20]; 6612 6613 u8 reserved_1[0x40]; 6614 }; 6615 6616 struct mlx5_ifc_dealloc_uar_in_bits { 6617 u8 opcode[0x10]; 6618 u8 reserved_0[0x10]; 6619 6620 u8 reserved_1[0x10]; 6621 u8 op_mod[0x10]; 6622 6623 u8 reserved_2[0x8]; 6624 u8 uar[0x18]; 6625 6626 u8 reserved_3[0x20]; 6627 }; 6628 6629 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6630 u8 status[0x8]; 6631 u8 reserved_0[0x18]; 6632 6633 u8 syndrome[0x20]; 6634 6635 u8 reserved_1[0x40]; 6636 }; 6637 6638 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6639 u8 opcode[0x10]; 6640 u8 reserved_0[0x10]; 6641 6642 u8 reserved_1[0x10]; 6643 u8 op_mod[0x10]; 6644 6645 u8 reserved_2[0x8]; 6646 u8 transport_domain[0x18]; 6647 6648 u8 reserved_3[0x20]; 6649 }; 6650 6651 struct mlx5_ifc_dealloc_q_counter_out_bits { 6652 u8 status[0x8]; 6653 u8 reserved_0[0x18]; 6654 6655 u8 syndrome[0x20]; 6656 6657 u8 reserved_1[0x40]; 6658 }; 6659 6660 struct mlx5_ifc_counter_id_bits { 6661 u8 reserved[0x10]; 6662 u8 counter_id[0x10]; 6663 }; 6664 6665 struct mlx5_ifc_diagnostic_params_context_bits { 6666 u8 num_of_counters[0x10]; 6667 u8 reserved_2[0x8]; 6668 u8 log_num_of_samples[0x8]; 6669 6670 u8 single[0x1]; 6671 u8 repetitive[0x1]; 6672 u8 sync[0x1]; 6673 u8 clear[0x1]; 6674 u8 on_demand[0x1]; 6675 u8 enable[0x1]; 6676 u8 reserved_3[0x12]; 6677 u8 log_sample_period[0x8]; 6678 6679 u8 reserved_4[0x80]; 6680 6681 struct mlx5_ifc_counter_id_bits counter_id[0]; 6682 }; 6683 6684 struct mlx5_ifc_set_diagnostic_params_in_bits { 6685 u8 opcode[0x10]; 6686 u8 reserved_0[0x10]; 6687 6688 u8 reserved_1[0x10]; 6689 u8 op_mod[0x10]; 6690 6691 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 6692 }; 6693 6694 struct mlx5_ifc_set_diagnostic_params_out_bits { 6695 u8 status[0x8]; 6696 u8 reserved_0[0x18]; 6697 6698 u8 syndrome[0x20]; 6699 6700 u8 reserved_1[0x40]; 6701 }; 6702 6703 struct mlx5_ifc_query_diagnostic_counters_in_bits { 6704 u8 opcode[0x10]; 6705 u8 reserved_0[0x10]; 6706 6707 u8 reserved_1[0x10]; 6708 u8 op_mod[0x10]; 6709 6710 u8 num_of_samples[0x10]; 6711 u8 sample_index[0x10]; 6712 6713 u8 reserved_2[0x20]; 6714 }; 6715 6716 struct mlx5_ifc_diagnostic_counter_bits { 6717 u8 counter_id[0x10]; 6718 u8 sample_id[0x10]; 6719 6720 u8 time_stamp_31_0[0x20]; 6721 6722 u8 counter_value_h[0x20]; 6723 6724 u8 counter_value_l[0x20]; 6725 }; 6726 6727 struct mlx5_ifc_query_diagnostic_counters_out_bits { 6728 u8 status[0x8]; 6729 u8 reserved_0[0x18]; 6730 6731 u8 syndrome[0x20]; 6732 6733 u8 reserved_1[0x40]; 6734 6735 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 6736 }; 6737 6738 struct mlx5_ifc_dealloc_q_counter_in_bits { 6739 u8 opcode[0x10]; 6740 u8 reserved_0[0x10]; 6741 6742 u8 reserved_1[0x10]; 6743 u8 op_mod[0x10]; 6744 6745 u8 reserved_2[0x18]; 6746 u8 counter_set_id[0x8]; 6747 6748 u8 reserved_3[0x20]; 6749 }; 6750 6751 struct mlx5_ifc_dealloc_pd_out_bits { 6752 u8 status[0x8]; 6753 u8 reserved_0[0x18]; 6754 6755 u8 syndrome[0x20]; 6756 6757 u8 reserved_1[0x40]; 6758 }; 6759 6760 struct mlx5_ifc_dealloc_pd_in_bits { 6761 u8 opcode[0x10]; 6762 u8 reserved_0[0x10]; 6763 6764 u8 reserved_1[0x10]; 6765 u8 op_mod[0x10]; 6766 6767 u8 reserved_2[0x8]; 6768 u8 pd[0x18]; 6769 6770 u8 reserved_3[0x20]; 6771 }; 6772 6773 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6774 u8 status[0x8]; 6775 u8 reserved_0[0x18]; 6776 6777 u8 syndrome[0x20]; 6778 6779 u8 reserved_1[0x40]; 6780 }; 6781 6782 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6783 u8 opcode[0x10]; 6784 u8 reserved_0[0x10]; 6785 6786 u8 reserved_1[0x10]; 6787 u8 op_mod[0x10]; 6788 6789 u8 reserved_2[0x10]; 6790 u8 flow_counter_id[0x10]; 6791 6792 u8 reserved_3[0x20]; 6793 }; 6794 6795 struct mlx5_ifc_deactivate_tracer_out_bits { 6796 u8 status[0x8]; 6797 u8 reserved_0[0x18]; 6798 6799 u8 syndrome[0x20]; 6800 6801 u8 reserved_1[0x40]; 6802 }; 6803 6804 struct mlx5_ifc_deactivate_tracer_in_bits { 6805 u8 opcode[0x10]; 6806 u8 reserved_0[0x10]; 6807 6808 u8 reserved_1[0x10]; 6809 u8 op_mod[0x10]; 6810 6811 u8 mkey[0x20]; 6812 6813 u8 reserved_2[0x20]; 6814 }; 6815 6816 struct mlx5_ifc_create_xrc_srq_out_bits { 6817 u8 status[0x8]; 6818 u8 reserved_0[0x18]; 6819 6820 u8 syndrome[0x20]; 6821 6822 u8 reserved_1[0x8]; 6823 u8 xrc_srqn[0x18]; 6824 6825 u8 reserved_2[0x20]; 6826 }; 6827 6828 struct mlx5_ifc_create_xrc_srq_in_bits { 6829 u8 opcode[0x10]; 6830 u8 reserved_0[0x10]; 6831 6832 u8 reserved_1[0x10]; 6833 u8 op_mod[0x10]; 6834 6835 u8 reserved_2[0x40]; 6836 6837 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6838 6839 u8 reserved_3[0x600]; 6840 6841 u8 pas[0][0x40]; 6842 }; 6843 6844 struct mlx5_ifc_create_tis_out_bits { 6845 u8 status[0x8]; 6846 u8 reserved_0[0x18]; 6847 6848 u8 syndrome[0x20]; 6849 6850 u8 reserved_1[0x8]; 6851 u8 tisn[0x18]; 6852 6853 u8 reserved_2[0x20]; 6854 }; 6855 6856 struct mlx5_ifc_create_tis_in_bits { 6857 u8 opcode[0x10]; 6858 u8 reserved_0[0x10]; 6859 6860 u8 reserved_1[0x10]; 6861 u8 op_mod[0x10]; 6862 6863 u8 reserved_2[0xc0]; 6864 6865 struct mlx5_ifc_tisc_bits ctx; 6866 }; 6867 6868 struct mlx5_ifc_create_tir_out_bits { 6869 u8 status[0x8]; 6870 u8 reserved_0[0x18]; 6871 6872 u8 syndrome[0x20]; 6873 6874 u8 reserved_1[0x8]; 6875 u8 tirn[0x18]; 6876 6877 u8 reserved_2[0x20]; 6878 }; 6879 6880 struct mlx5_ifc_create_tir_in_bits { 6881 u8 opcode[0x10]; 6882 u8 reserved_0[0x10]; 6883 6884 u8 reserved_1[0x10]; 6885 u8 op_mod[0x10]; 6886 6887 u8 reserved_2[0xc0]; 6888 6889 struct mlx5_ifc_tirc_bits tir_context; 6890 }; 6891 6892 struct mlx5_ifc_create_srq_out_bits { 6893 u8 status[0x8]; 6894 u8 reserved_0[0x18]; 6895 6896 u8 syndrome[0x20]; 6897 6898 u8 reserved_1[0x8]; 6899 u8 srqn[0x18]; 6900 6901 u8 reserved_2[0x20]; 6902 }; 6903 6904 struct mlx5_ifc_create_srq_in_bits { 6905 u8 opcode[0x10]; 6906 u8 reserved_0[0x10]; 6907 6908 u8 reserved_1[0x10]; 6909 u8 op_mod[0x10]; 6910 6911 u8 reserved_2[0x40]; 6912 6913 struct mlx5_ifc_srqc_bits srq_context_entry; 6914 6915 u8 reserved_3[0x600]; 6916 6917 u8 pas[0][0x40]; 6918 }; 6919 6920 struct mlx5_ifc_create_sq_out_bits { 6921 u8 status[0x8]; 6922 u8 reserved_0[0x18]; 6923 6924 u8 syndrome[0x20]; 6925 6926 u8 reserved_1[0x8]; 6927 u8 sqn[0x18]; 6928 6929 u8 reserved_2[0x20]; 6930 }; 6931 6932 struct mlx5_ifc_create_sq_in_bits { 6933 u8 opcode[0x10]; 6934 u8 reserved_0[0x10]; 6935 6936 u8 reserved_1[0x10]; 6937 u8 op_mod[0x10]; 6938 6939 u8 reserved_2[0xc0]; 6940 6941 struct mlx5_ifc_sqc_bits ctx; 6942 }; 6943 6944 struct mlx5_ifc_create_scheduling_element_out_bits { 6945 u8 status[0x8]; 6946 u8 reserved_at_8[0x18]; 6947 6948 u8 syndrome[0x20]; 6949 6950 u8 reserved_at_40[0x40]; 6951 6952 u8 scheduling_element_id[0x20]; 6953 6954 u8 reserved_at_a0[0x160]; 6955 }; 6956 6957 enum { 6958 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6959 }; 6960 6961 struct mlx5_ifc_create_scheduling_element_in_bits { 6962 u8 opcode[0x10]; 6963 u8 reserved_at_10[0x10]; 6964 6965 u8 reserved_at_20[0x10]; 6966 u8 op_mod[0x10]; 6967 6968 u8 scheduling_hierarchy[0x8]; 6969 u8 reserved_at_48[0x18]; 6970 6971 u8 reserved_at_60[0xa0]; 6972 6973 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6974 6975 u8 reserved_at_300[0x100]; 6976 }; 6977 6978 struct mlx5_ifc_create_rqt_out_bits { 6979 u8 status[0x8]; 6980 u8 reserved_0[0x18]; 6981 6982 u8 syndrome[0x20]; 6983 6984 u8 reserved_1[0x8]; 6985 u8 rqtn[0x18]; 6986 6987 u8 reserved_2[0x20]; 6988 }; 6989 6990 struct mlx5_ifc_create_rqt_in_bits { 6991 u8 opcode[0x10]; 6992 u8 reserved_0[0x10]; 6993 6994 u8 reserved_1[0x10]; 6995 u8 op_mod[0x10]; 6996 6997 u8 reserved_2[0xc0]; 6998 6999 struct mlx5_ifc_rqtc_bits rqt_context; 7000 }; 7001 7002 struct mlx5_ifc_create_rq_out_bits { 7003 u8 status[0x8]; 7004 u8 reserved_0[0x18]; 7005 7006 u8 syndrome[0x20]; 7007 7008 u8 reserved_1[0x8]; 7009 u8 rqn[0x18]; 7010 7011 u8 reserved_2[0x20]; 7012 }; 7013 7014 struct mlx5_ifc_create_rq_in_bits { 7015 u8 opcode[0x10]; 7016 u8 reserved_0[0x10]; 7017 7018 u8 reserved_1[0x10]; 7019 u8 op_mod[0x10]; 7020 7021 u8 reserved_2[0xc0]; 7022 7023 struct mlx5_ifc_rqc_bits ctx; 7024 }; 7025 7026 struct mlx5_ifc_create_rmp_out_bits { 7027 u8 status[0x8]; 7028 u8 reserved_0[0x18]; 7029 7030 u8 syndrome[0x20]; 7031 7032 u8 reserved_1[0x8]; 7033 u8 rmpn[0x18]; 7034 7035 u8 reserved_2[0x20]; 7036 }; 7037 7038 struct mlx5_ifc_create_rmp_in_bits { 7039 u8 opcode[0x10]; 7040 u8 reserved_0[0x10]; 7041 7042 u8 reserved_1[0x10]; 7043 u8 op_mod[0x10]; 7044 7045 u8 reserved_2[0xc0]; 7046 7047 struct mlx5_ifc_rmpc_bits ctx; 7048 }; 7049 7050 struct mlx5_ifc_create_qp_out_bits { 7051 u8 status[0x8]; 7052 u8 reserved_0[0x18]; 7053 7054 u8 syndrome[0x20]; 7055 7056 u8 reserved_1[0x8]; 7057 u8 qpn[0x18]; 7058 7059 u8 reserved_2[0x20]; 7060 }; 7061 7062 struct mlx5_ifc_create_qp_in_bits { 7063 u8 opcode[0x10]; 7064 u8 reserved_0[0x10]; 7065 7066 u8 reserved_1[0x10]; 7067 u8 op_mod[0x10]; 7068 7069 u8 reserved_2[0x8]; 7070 u8 input_qpn[0x18]; 7071 7072 u8 reserved_3[0x20]; 7073 7074 u8 opt_param_mask[0x20]; 7075 7076 u8 reserved_4[0x20]; 7077 7078 struct mlx5_ifc_qpc_bits qpc; 7079 7080 u8 reserved_5[0x80]; 7081 7082 u8 pas[0][0x40]; 7083 }; 7084 7085 struct mlx5_ifc_create_qos_para_vport_out_bits { 7086 u8 status[0x8]; 7087 u8 reserved_at_8[0x18]; 7088 7089 u8 syndrome[0x20]; 7090 7091 u8 reserved_at_40[0x20]; 7092 7093 u8 reserved_at_60[0x10]; 7094 u8 qos_para_vport_number[0x10]; 7095 7096 u8 reserved_at_80[0x180]; 7097 }; 7098 7099 struct mlx5_ifc_create_qos_para_vport_in_bits { 7100 u8 opcode[0x10]; 7101 u8 reserved_at_10[0x10]; 7102 7103 u8 reserved_at_20[0x10]; 7104 u8 op_mod[0x10]; 7105 7106 u8 reserved_at_40[0x1c0]; 7107 }; 7108 7109 struct mlx5_ifc_create_psv_out_bits { 7110 u8 status[0x8]; 7111 u8 reserved_0[0x18]; 7112 7113 u8 syndrome[0x20]; 7114 7115 u8 reserved_1[0x40]; 7116 7117 u8 reserved_2[0x8]; 7118 u8 psv0_index[0x18]; 7119 7120 u8 reserved_3[0x8]; 7121 u8 psv1_index[0x18]; 7122 7123 u8 reserved_4[0x8]; 7124 u8 psv2_index[0x18]; 7125 7126 u8 reserved_5[0x8]; 7127 u8 psv3_index[0x18]; 7128 }; 7129 7130 struct mlx5_ifc_create_psv_in_bits { 7131 u8 opcode[0x10]; 7132 u8 reserved_0[0x10]; 7133 7134 u8 reserved_1[0x10]; 7135 u8 op_mod[0x10]; 7136 7137 u8 num_psv[0x4]; 7138 u8 reserved_2[0x4]; 7139 u8 pd[0x18]; 7140 7141 u8 reserved_3[0x20]; 7142 }; 7143 7144 struct mlx5_ifc_create_mkey_out_bits { 7145 u8 status[0x8]; 7146 u8 reserved_0[0x18]; 7147 7148 u8 syndrome[0x20]; 7149 7150 u8 reserved_1[0x8]; 7151 u8 mkey_index[0x18]; 7152 7153 u8 reserved_2[0x20]; 7154 }; 7155 7156 struct mlx5_ifc_create_mkey_in_bits { 7157 u8 opcode[0x10]; 7158 u8 reserved_0[0x10]; 7159 7160 u8 reserved_1[0x10]; 7161 u8 op_mod[0x10]; 7162 7163 u8 reserved_2[0x20]; 7164 7165 u8 pg_access[0x1]; 7166 u8 reserved_3[0x1f]; 7167 7168 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7169 7170 u8 reserved_4[0x80]; 7171 7172 u8 translations_octword_actual_size[0x20]; 7173 7174 u8 reserved_5[0x560]; 7175 7176 u8 klm_pas_mtt[0][0x20]; 7177 }; 7178 7179 struct mlx5_ifc_create_flow_table_out_bits { 7180 u8 status[0x8]; 7181 u8 reserved_0[0x18]; 7182 7183 u8 syndrome[0x20]; 7184 7185 u8 reserved_1[0x8]; 7186 u8 table_id[0x18]; 7187 7188 u8 reserved_2[0x20]; 7189 }; 7190 7191 struct mlx5_ifc_create_flow_table_in_bits { 7192 u8 opcode[0x10]; 7193 u8 reserved_at_10[0x10]; 7194 7195 u8 reserved_at_20[0x10]; 7196 u8 op_mod[0x10]; 7197 7198 u8 other_vport[0x1]; 7199 u8 reserved_at_41[0xf]; 7200 u8 vport_number[0x10]; 7201 7202 u8 reserved_at_60[0x20]; 7203 7204 u8 table_type[0x8]; 7205 u8 reserved_at_88[0x18]; 7206 7207 u8 reserved_at_a0[0x20]; 7208 7209 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7210 }; 7211 7212 struct mlx5_ifc_create_flow_group_out_bits { 7213 u8 status[0x8]; 7214 u8 reserved_0[0x18]; 7215 7216 u8 syndrome[0x20]; 7217 7218 u8 reserved_1[0x8]; 7219 u8 group_id[0x18]; 7220 7221 u8 reserved_2[0x20]; 7222 }; 7223 7224 enum { 7225 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7226 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7227 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7228 }; 7229 7230 struct mlx5_ifc_create_flow_group_in_bits { 7231 u8 opcode[0x10]; 7232 u8 reserved_0[0x10]; 7233 7234 u8 reserved_1[0x10]; 7235 u8 op_mod[0x10]; 7236 7237 u8 other_vport[0x1]; 7238 u8 reserved_2[0xf]; 7239 u8 vport_number[0x10]; 7240 7241 u8 reserved_3[0x20]; 7242 7243 u8 table_type[0x8]; 7244 u8 reserved_4[0x18]; 7245 7246 u8 reserved_5[0x8]; 7247 u8 table_id[0x18]; 7248 7249 u8 reserved_6[0x20]; 7250 7251 u8 start_flow_index[0x20]; 7252 7253 u8 reserved_7[0x20]; 7254 7255 u8 end_flow_index[0x20]; 7256 7257 u8 reserved_8[0xa0]; 7258 7259 u8 reserved_9[0x18]; 7260 u8 match_criteria_enable[0x8]; 7261 7262 struct mlx5_ifc_fte_match_param_bits match_criteria; 7263 7264 u8 reserved_10[0xe00]; 7265 }; 7266 7267 struct mlx5_ifc_create_eq_out_bits { 7268 u8 status[0x8]; 7269 u8 reserved_0[0x18]; 7270 7271 u8 syndrome[0x20]; 7272 7273 u8 reserved_1[0x18]; 7274 u8 eq_number[0x8]; 7275 7276 u8 reserved_2[0x20]; 7277 }; 7278 7279 struct mlx5_ifc_create_eq_in_bits { 7280 u8 opcode[0x10]; 7281 u8 reserved_0[0x10]; 7282 7283 u8 reserved_1[0x10]; 7284 u8 op_mod[0x10]; 7285 7286 u8 reserved_2[0x40]; 7287 7288 struct mlx5_ifc_eqc_bits eq_context_entry; 7289 7290 u8 reserved_3[0x40]; 7291 7292 u8 event_bitmask[0x40]; 7293 7294 u8 reserved_4[0x580]; 7295 7296 u8 pas[0][0x40]; 7297 }; 7298 7299 struct mlx5_ifc_create_dct_out_bits { 7300 u8 status[0x8]; 7301 u8 reserved_0[0x18]; 7302 7303 u8 syndrome[0x20]; 7304 7305 u8 reserved_1[0x8]; 7306 u8 dctn[0x18]; 7307 7308 u8 reserved_2[0x20]; 7309 }; 7310 7311 struct mlx5_ifc_create_dct_in_bits { 7312 u8 opcode[0x10]; 7313 u8 reserved_0[0x10]; 7314 7315 u8 reserved_1[0x10]; 7316 u8 op_mod[0x10]; 7317 7318 u8 reserved_2[0x40]; 7319 7320 struct mlx5_ifc_dctc_bits dct_context_entry; 7321 7322 u8 reserved_3[0x180]; 7323 }; 7324 7325 struct mlx5_ifc_create_cq_out_bits { 7326 u8 status[0x8]; 7327 u8 reserved_0[0x18]; 7328 7329 u8 syndrome[0x20]; 7330 7331 u8 reserved_1[0x8]; 7332 u8 cqn[0x18]; 7333 7334 u8 reserved_2[0x20]; 7335 }; 7336 7337 struct mlx5_ifc_create_cq_in_bits { 7338 u8 opcode[0x10]; 7339 u8 reserved_0[0x10]; 7340 7341 u8 reserved_1[0x10]; 7342 u8 op_mod[0x10]; 7343 7344 u8 reserved_2[0x40]; 7345 7346 struct mlx5_ifc_cqc_bits cq_context; 7347 7348 u8 reserved_3[0x600]; 7349 7350 u8 pas[0][0x40]; 7351 }; 7352 7353 struct mlx5_ifc_config_int_moderation_out_bits { 7354 u8 status[0x8]; 7355 u8 reserved_0[0x18]; 7356 7357 u8 syndrome[0x20]; 7358 7359 u8 reserved_1[0x4]; 7360 u8 min_delay[0xc]; 7361 u8 int_vector[0x10]; 7362 7363 u8 reserved_2[0x20]; 7364 }; 7365 7366 enum { 7367 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7368 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7369 }; 7370 7371 struct mlx5_ifc_config_int_moderation_in_bits { 7372 u8 opcode[0x10]; 7373 u8 reserved_0[0x10]; 7374 7375 u8 reserved_1[0x10]; 7376 u8 op_mod[0x10]; 7377 7378 u8 reserved_2[0x4]; 7379 u8 min_delay[0xc]; 7380 u8 int_vector[0x10]; 7381 7382 u8 reserved_3[0x20]; 7383 }; 7384 7385 struct mlx5_ifc_attach_to_mcg_out_bits { 7386 u8 status[0x8]; 7387 u8 reserved_0[0x18]; 7388 7389 u8 syndrome[0x20]; 7390 7391 u8 reserved_1[0x40]; 7392 }; 7393 7394 struct mlx5_ifc_attach_to_mcg_in_bits { 7395 u8 opcode[0x10]; 7396 u8 reserved_0[0x10]; 7397 7398 u8 reserved_1[0x10]; 7399 u8 op_mod[0x10]; 7400 7401 u8 reserved_2[0x8]; 7402 u8 qpn[0x18]; 7403 7404 u8 reserved_3[0x20]; 7405 7406 u8 multicast_gid[16][0x8]; 7407 }; 7408 7409 struct mlx5_ifc_arm_xrc_srq_out_bits { 7410 u8 status[0x8]; 7411 u8 reserved_0[0x18]; 7412 7413 u8 syndrome[0x20]; 7414 7415 u8 reserved_1[0x40]; 7416 }; 7417 7418 enum { 7419 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7420 }; 7421 7422 struct mlx5_ifc_arm_xrc_srq_in_bits { 7423 u8 opcode[0x10]; 7424 u8 reserved_0[0x10]; 7425 7426 u8 reserved_1[0x10]; 7427 u8 op_mod[0x10]; 7428 7429 u8 reserved_2[0x8]; 7430 u8 xrc_srqn[0x18]; 7431 7432 u8 reserved_3[0x10]; 7433 u8 lwm[0x10]; 7434 }; 7435 7436 struct mlx5_ifc_arm_rq_out_bits { 7437 u8 status[0x8]; 7438 u8 reserved_0[0x18]; 7439 7440 u8 syndrome[0x20]; 7441 7442 u8 reserved_1[0x40]; 7443 }; 7444 7445 enum { 7446 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7447 }; 7448 7449 struct mlx5_ifc_arm_rq_in_bits { 7450 u8 opcode[0x10]; 7451 u8 reserved_0[0x10]; 7452 7453 u8 reserved_1[0x10]; 7454 u8 op_mod[0x10]; 7455 7456 u8 reserved_2[0x8]; 7457 u8 srq_number[0x18]; 7458 7459 u8 reserved_3[0x10]; 7460 u8 lwm[0x10]; 7461 }; 7462 7463 struct mlx5_ifc_arm_dct_out_bits { 7464 u8 status[0x8]; 7465 u8 reserved_0[0x18]; 7466 7467 u8 syndrome[0x20]; 7468 7469 u8 reserved_1[0x40]; 7470 }; 7471 7472 struct mlx5_ifc_arm_dct_in_bits { 7473 u8 opcode[0x10]; 7474 u8 reserved_0[0x10]; 7475 7476 u8 reserved_1[0x10]; 7477 u8 op_mod[0x10]; 7478 7479 u8 reserved_2[0x8]; 7480 u8 dctn[0x18]; 7481 7482 u8 reserved_3[0x20]; 7483 }; 7484 7485 struct mlx5_ifc_alloc_xrcd_out_bits { 7486 u8 status[0x8]; 7487 u8 reserved_0[0x18]; 7488 7489 u8 syndrome[0x20]; 7490 7491 u8 reserved_1[0x8]; 7492 u8 xrcd[0x18]; 7493 7494 u8 reserved_2[0x20]; 7495 }; 7496 7497 struct mlx5_ifc_alloc_xrcd_in_bits { 7498 u8 opcode[0x10]; 7499 u8 reserved_0[0x10]; 7500 7501 u8 reserved_1[0x10]; 7502 u8 op_mod[0x10]; 7503 7504 u8 reserved_2[0x40]; 7505 }; 7506 7507 struct mlx5_ifc_alloc_uar_out_bits { 7508 u8 status[0x8]; 7509 u8 reserved_0[0x18]; 7510 7511 u8 syndrome[0x20]; 7512 7513 u8 reserved_1[0x8]; 7514 u8 uar[0x18]; 7515 7516 u8 reserved_2[0x20]; 7517 }; 7518 7519 struct mlx5_ifc_alloc_uar_in_bits { 7520 u8 opcode[0x10]; 7521 u8 reserved_0[0x10]; 7522 7523 u8 reserved_1[0x10]; 7524 u8 op_mod[0x10]; 7525 7526 u8 reserved_2[0x40]; 7527 }; 7528 7529 struct mlx5_ifc_alloc_transport_domain_out_bits { 7530 u8 status[0x8]; 7531 u8 reserved_0[0x18]; 7532 7533 u8 syndrome[0x20]; 7534 7535 u8 reserved_1[0x8]; 7536 u8 transport_domain[0x18]; 7537 7538 u8 reserved_2[0x20]; 7539 }; 7540 7541 struct mlx5_ifc_alloc_transport_domain_in_bits { 7542 u8 opcode[0x10]; 7543 u8 reserved_0[0x10]; 7544 7545 u8 reserved_1[0x10]; 7546 u8 op_mod[0x10]; 7547 7548 u8 reserved_2[0x40]; 7549 }; 7550 7551 struct mlx5_ifc_alloc_q_counter_out_bits { 7552 u8 status[0x8]; 7553 u8 reserved_0[0x18]; 7554 7555 u8 syndrome[0x20]; 7556 7557 u8 reserved_1[0x18]; 7558 u8 counter_set_id[0x8]; 7559 7560 u8 reserved_2[0x20]; 7561 }; 7562 7563 struct mlx5_ifc_alloc_q_counter_in_bits { 7564 u8 opcode[0x10]; 7565 u8 reserved_0[0x10]; 7566 7567 u8 reserved_1[0x10]; 7568 u8 op_mod[0x10]; 7569 7570 u8 reserved_2[0x40]; 7571 }; 7572 7573 struct mlx5_ifc_alloc_pd_out_bits { 7574 u8 status[0x8]; 7575 u8 reserved_0[0x18]; 7576 7577 u8 syndrome[0x20]; 7578 7579 u8 reserved_1[0x8]; 7580 u8 pd[0x18]; 7581 7582 u8 reserved_2[0x20]; 7583 }; 7584 7585 struct mlx5_ifc_alloc_pd_in_bits { 7586 u8 opcode[0x10]; 7587 u8 reserved_0[0x10]; 7588 7589 u8 reserved_1[0x10]; 7590 u8 op_mod[0x10]; 7591 7592 u8 reserved_2[0x40]; 7593 }; 7594 7595 struct mlx5_ifc_alloc_flow_counter_out_bits { 7596 u8 status[0x8]; 7597 u8 reserved_0[0x18]; 7598 7599 u8 syndrome[0x20]; 7600 7601 u8 reserved_1[0x10]; 7602 u8 flow_counter_id[0x10]; 7603 7604 u8 reserved_2[0x20]; 7605 }; 7606 7607 struct mlx5_ifc_alloc_flow_counter_in_bits { 7608 u8 opcode[0x10]; 7609 u8 reserved_0[0x10]; 7610 7611 u8 reserved_1[0x10]; 7612 u8 op_mod[0x10]; 7613 7614 u8 reserved_2[0x40]; 7615 }; 7616 7617 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7618 u8 status[0x8]; 7619 u8 reserved_0[0x18]; 7620 7621 u8 syndrome[0x20]; 7622 7623 u8 reserved_1[0x40]; 7624 }; 7625 7626 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7627 u8 opcode[0x10]; 7628 u8 reserved_0[0x10]; 7629 7630 u8 reserved_1[0x10]; 7631 u8 op_mod[0x10]; 7632 7633 u8 reserved_2[0x20]; 7634 7635 u8 reserved_3[0x10]; 7636 u8 vxlan_udp_port[0x10]; 7637 }; 7638 7639 struct mlx5_ifc_activate_tracer_out_bits { 7640 u8 status[0x8]; 7641 u8 reserved_0[0x18]; 7642 7643 u8 syndrome[0x20]; 7644 7645 u8 reserved_1[0x40]; 7646 }; 7647 7648 struct mlx5_ifc_activate_tracer_in_bits { 7649 u8 opcode[0x10]; 7650 u8 reserved_0[0x10]; 7651 7652 u8 reserved_1[0x10]; 7653 u8 op_mod[0x10]; 7654 7655 u8 mkey[0x20]; 7656 7657 u8 reserved_2[0x20]; 7658 }; 7659 7660 struct mlx5_ifc_set_rate_limit_out_bits { 7661 u8 status[0x8]; 7662 u8 reserved_at_8[0x18]; 7663 7664 u8 syndrome[0x20]; 7665 7666 u8 reserved_at_40[0x40]; 7667 }; 7668 7669 struct mlx5_ifc_set_rate_limit_in_bits { 7670 u8 opcode[0x10]; 7671 u8 reserved_at_10[0x10]; 7672 7673 u8 reserved_at_20[0x10]; 7674 u8 op_mod[0x10]; 7675 7676 u8 reserved_at_40[0x10]; 7677 u8 rate_limit_index[0x10]; 7678 7679 u8 reserved_at_60[0x20]; 7680 7681 u8 rate_limit[0x20]; 7682 u8 burst_upper_bound[0x20]; 7683 }; 7684 7685 struct mlx5_ifc_access_register_out_bits { 7686 u8 status[0x8]; 7687 u8 reserved_0[0x18]; 7688 7689 u8 syndrome[0x20]; 7690 7691 u8 reserved_1[0x40]; 7692 7693 u8 register_data[0][0x20]; 7694 }; 7695 7696 enum { 7697 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7698 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7699 }; 7700 7701 struct mlx5_ifc_access_register_in_bits { 7702 u8 opcode[0x10]; 7703 u8 reserved_0[0x10]; 7704 7705 u8 reserved_1[0x10]; 7706 u8 op_mod[0x10]; 7707 7708 u8 reserved_2[0x10]; 7709 u8 register_id[0x10]; 7710 7711 u8 argument[0x20]; 7712 7713 u8 register_data[0][0x20]; 7714 }; 7715 7716 struct mlx5_ifc_sltp_reg_bits { 7717 u8 status[0x4]; 7718 u8 version[0x4]; 7719 u8 local_port[0x8]; 7720 u8 pnat[0x2]; 7721 u8 reserved_0[0x2]; 7722 u8 lane[0x4]; 7723 u8 reserved_1[0x8]; 7724 7725 u8 reserved_2[0x20]; 7726 7727 u8 reserved_3[0x7]; 7728 u8 polarity[0x1]; 7729 u8 ob_tap0[0x8]; 7730 u8 ob_tap1[0x8]; 7731 u8 ob_tap2[0x8]; 7732 7733 u8 reserved_4[0xc]; 7734 u8 ob_preemp_mode[0x4]; 7735 u8 ob_reg[0x8]; 7736 u8 ob_bias[0x8]; 7737 7738 u8 reserved_5[0x20]; 7739 }; 7740 7741 struct mlx5_ifc_slrp_reg_bits { 7742 u8 status[0x4]; 7743 u8 version[0x4]; 7744 u8 local_port[0x8]; 7745 u8 pnat[0x2]; 7746 u8 reserved_0[0x2]; 7747 u8 lane[0x4]; 7748 u8 reserved_1[0x8]; 7749 7750 u8 ib_sel[0x2]; 7751 u8 reserved_2[0x11]; 7752 u8 dp_sel[0x1]; 7753 u8 dp90sel[0x4]; 7754 u8 mix90phase[0x8]; 7755 7756 u8 ffe_tap0[0x8]; 7757 u8 ffe_tap1[0x8]; 7758 u8 ffe_tap2[0x8]; 7759 u8 ffe_tap3[0x8]; 7760 7761 u8 ffe_tap4[0x8]; 7762 u8 ffe_tap5[0x8]; 7763 u8 ffe_tap6[0x8]; 7764 u8 ffe_tap7[0x8]; 7765 7766 u8 ffe_tap8[0x8]; 7767 u8 mixerbias_tap_amp[0x8]; 7768 u8 reserved_3[0x7]; 7769 u8 ffe_tap_en[0x9]; 7770 7771 u8 ffe_tap_offset0[0x8]; 7772 u8 ffe_tap_offset1[0x8]; 7773 u8 slicer_offset0[0x10]; 7774 7775 u8 mixer_offset0[0x10]; 7776 u8 mixer_offset1[0x10]; 7777 7778 u8 mixerbgn_inp[0x8]; 7779 u8 mixerbgn_inn[0x8]; 7780 u8 mixerbgn_refp[0x8]; 7781 u8 mixerbgn_refn[0x8]; 7782 7783 u8 sel_slicer_lctrl_h[0x1]; 7784 u8 sel_slicer_lctrl_l[0x1]; 7785 u8 reserved_4[0x1]; 7786 u8 ref_mixer_vreg[0x5]; 7787 u8 slicer_gctrl[0x8]; 7788 u8 lctrl_input[0x8]; 7789 u8 mixer_offset_cm1[0x8]; 7790 7791 u8 common_mode[0x6]; 7792 u8 reserved_5[0x1]; 7793 u8 mixer_offset_cm0[0x9]; 7794 u8 reserved_6[0x7]; 7795 u8 slicer_offset_cm[0x9]; 7796 }; 7797 7798 struct mlx5_ifc_slrg_reg_bits { 7799 u8 status[0x4]; 7800 u8 version[0x4]; 7801 u8 local_port[0x8]; 7802 u8 pnat[0x2]; 7803 u8 reserved_0[0x2]; 7804 u8 lane[0x4]; 7805 u8 reserved_1[0x8]; 7806 7807 u8 time_to_link_up[0x10]; 7808 u8 reserved_2[0xc]; 7809 u8 grade_lane_speed[0x4]; 7810 7811 u8 grade_version[0x8]; 7812 u8 grade[0x18]; 7813 7814 u8 reserved_3[0x4]; 7815 u8 height_grade_type[0x4]; 7816 u8 height_grade[0x18]; 7817 7818 u8 height_dz[0x10]; 7819 u8 height_dv[0x10]; 7820 7821 u8 reserved_4[0x10]; 7822 u8 height_sigma[0x10]; 7823 7824 u8 reserved_5[0x20]; 7825 7826 u8 reserved_6[0x4]; 7827 u8 phase_grade_type[0x4]; 7828 u8 phase_grade[0x18]; 7829 7830 u8 reserved_7[0x8]; 7831 u8 phase_eo_pos[0x8]; 7832 u8 reserved_8[0x8]; 7833 u8 phase_eo_neg[0x8]; 7834 7835 u8 ffe_set_tested[0x10]; 7836 u8 test_errors_per_lane[0x10]; 7837 }; 7838 7839 struct mlx5_ifc_pvlc_reg_bits { 7840 u8 reserved_0[0x8]; 7841 u8 local_port[0x8]; 7842 u8 reserved_1[0x10]; 7843 7844 u8 reserved_2[0x1c]; 7845 u8 vl_hw_cap[0x4]; 7846 7847 u8 reserved_3[0x1c]; 7848 u8 vl_admin[0x4]; 7849 7850 u8 reserved_4[0x1c]; 7851 u8 vl_operational[0x4]; 7852 }; 7853 7854 struct mlx5_ifc_pude_reg_bits { 7855 u8 swid[0x8]; 7856 u8 local_port[0x8]; 7857 u8 reserved_0[0x4]; 7858 u8 admin_status[0x4]; 7859 u8 reserved_1[0x4]; 7860 u8 oper_status[0x4]; 7861 7862 u8 reserved_2[0x60]; 7863 }; 7864 7865 enum { 7866 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 7867 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 7868 }; 7869 7870 struct mlx5_ifc_ptys_reg_bits { 7871 u8 reserved_0[0x1]; 7872 u8 an_disable_admin[0x1]; 7873 u8 an_disable_cap[0x1]; 7874 u8 reserved_1[0x4]; 7875 u8 force_tx_aba_param[0x1]; 7876 u8 local_port[0x8]; 7877 u8 reserved_2[0xd]; 7878 u8 proto_mask[0x3]; 7879 7880 u8 an_status[0x4]; 7881 u8 reserved_3[0xc]; 7882 u8 data_rate_oper[0x10]; 7883 7884 u8 ext_eth_proto_capability[0x20]; 7885 7886 u8 eth_proto_capability[0x20]; 7887 7888 u8 ib_link_width_capability[0x10]; 7889 u8 ib_proto_capability[0x10]; 7890 7891 u8 ext_eth_proto_admin[0x20]; 7892 7893 u8 eth_proto_admin[0x20]; 7894 7895 u8 ib_link_width_admin[0x10]; 7896 u8 ib_proto_admin[0x10]; 7897 7898 u8 ext_eth_proto_oper[0x20]; 7899 7900 u8 eth_proto_oper[0x20]; 7901 7902 u8 ib_link_width_oper[0x10]; 7903 u8 ib_proto_oper[0x10]; 7904 7905 u8 reserved_4[0x1c]; 7906 u8 connector_type[0x4]; 7907 7908 u8 eth_proto_lp_advertise[0x20]; 7909 7910 u8 reserved_5[0x60]; 7911 }; 7912 7913 struct mlx5_ifc_ptas_reg_bits { 7914 u8 reserved_0[0x20]; 7915 7916 u8 algorithm_options[0x10]; 7917 u8 reserved_1[0x4]; 7918 u8 repetitions_mode[0x4]; 7919 u8 num_of_repetitions[0x8]; 7920 7921 u8 grade_version[0x8]; 7922 u8 height_grade_type[0x4]; 7923 u8 phase_grade_type[0x4]; 7924 u8 height_grade_weight[0x8]; 7925 u8 phase_grade_weight[0x8]; 7926 7927 u8 gisim_measure_bits[0x10]; 7928 u8 adaptive_tap_measure_bits[0x10]; 7929 7930 u8 ber_bath_high_error_threshold[0x10]; 7931 u8 ber_bath_mid_error_threshold[0x10]; 7932 7933 u8 ber_bath_low_error_threshold[0x10]; 7934 u8 one_ratio_high_threshold[0x10]; 7935 7936 u8 one_ratio_high_mid_threshold[0x10]; 7937 u8 one_ratio_low_mid_threshold[0x10]; 7938 7939 u8 one_ratio_low_threshold[0x10]; 7940 u8 ndeo_error_threshold[0x10]; 7941 7942 u8 mixer_offset_step_size[0x10]; 7943 u8 reserved_2[0x8]; 7944 u8 mix90_phase_for_voltage_bath[0x8]; 7945 7946 u8 mixer_offset_start[0x10]; 7947 u8 mixer_offset_end[0x10]; 7948 7949 u8 reserved_3[0x15]; 7950 u8 ber_test_time[0xb]; 7951 }; 7952 7953 struct mlx5_ifc_pspa_reg_bits { 7954 u8 swid[0x8]; 7955 u8 local_port[0x8]; 7956 u8 sub_port[0x8]; 7957 u8 reserved_0[0x8]; 7958 7959 u8 reserved_1[0x20]; 7960 }; 7961 7962 struct mlx5_ifc_ppsc_reg_bits { 7963 u8 reserved_0[0x8]; 7964 u8 local_port[0x8]; 7965 u8 reserved_1[0x10]; 7966 7967 u8 reserved_2[0x60]; 7968 7969 u8 reserved_3[0x1c]; 7970 u8 wrps_admin[0x4]; 7971 7972 u8 reserved_4[0x1c]; 7973 u8 wrps_status[0x4]; 7974 7975 u8 up_th_vld[0x1]; 7976 u8 down_th_vld[0x1]; 7977 u8 reserved_5[0x6]; 7978 u8 up_threshold[0x8]; 7979 u8 reserved_6[0x8]; 7980 u8 down_threshold[0x8]; 7981 7982 u8 reserved_7[0x20]; 7983 7984 u8 reserved_8[0x1c]; 7985 u8 srps_admin[0x4]; 7986 7987 u8 reserved_9[0x60]; 7988 }; 7989 7990 struct mlx5_ifc_pplr_reg_bits { 7991 u8 reserved_0[0x8]; 7992 u8 local_port[0x8]; 7993 u8 reserved_1[0x10]; 7994 7995 u8 reserved_2[0x8]; 7996 u8 lb_cap[0x8]; 7997 u8 reserved_3[0x8]; 7998 u8 lb_en[0x8]; 7999 }; 8000 8001 struct mlx5_ifc_pplm_reg_bits { 8002 u8 reserved_0[0x8]; 8003 u8 local_port[0x8]; 8004 u8 reserved_1[0x10]; 8005 8006 u8 reserved_2[0x20]; 8007 8008 u8 port_profile_mode[0x8]; 8009 u8 static_port_profile[0x8]; 8010 u8 active_port_profile[0x8]; 8011 u8 reserved_3[0x8]; 8012 8013 u8 retransmission_active[0x8]; 8014 u8 fec_mode_active[0x18]; 8015 8016 u8 reserved_4[0x10]; 8017 u8 v_100g_fec_override_cap[0x4]; 8018 u8 v_50g_fec_override_cap[0x4]; 8019 u8 v_25g_fec_override_cap[0x4]; 8020 u8 v_10g_40g_fec_override_cap[0x4]; 8021 8022 u8 reserved_5[0x10]; 8023 u8 v_100g_fec_override_admin[0x4]; 8024 u8 v_50g_fec_override_admin[0x4]; 8025 u8 v_25g_fec_override_admin[0x4]; 8026 u8 v_10g_40g_fec_override_admin[0x4]; 8027 }; 8028 8029 struct mlx5_ifc_ppll_reg_bits { 8030 u8 num_pll_groups[0x8]; 8031 u8 pll_group[0x8]; 8032 u8 reserved_0[0x4]; 8033 u8 num_plls[0x4]; 8034 u8 reserved_1[0x8]; 8035 8036 u8 reserved_2[0x1f]; 8037 u8 ae[0x1]; 8038 8039 u8 pll_status[4][0x40]; 8040 }; 8041 8042 struct mlx5_ifc_ppad_reg_bits { 8043 u8 reserved_0[0x3]; 8044 u8 single_mac[0x1]; 8045 u8 reserved_1[0x4]; 8046 u8 local_port[0x8]; 8047 u8 mac_47_32[0x10]; 8048 8049 u8 mac_31_0[0x20]; 8050 8051 u8 reserved_2[0x40]; 8052 }; 8053 8054 struct mlx5_ifc_pmtu_reg_bits { 8055 u8 reserved_0[0x8]; 8056 u8 local_port[0x8]; 8057 u8 reserved_1[0x10]; 8058 8059 u8 max_mtu[0x10]; 8060 u8 reserved_2[0x10]; 8061 8062 u8 admin_mtu[0x10]; 8063 u8 reserved_3[0x10]; 8064 8065 u8 oper_mtu[0x10]; 8066 u8 reserved_4[0x10]; 8067 }; 8068 8069 struct mlx5_ifc_pmpr_reg_bits { 8070 u8 reserved_0[0x8]; 8071 u8 module[0x8]; 8072 u8 reserved_1[0x10]; 8073 8074 u8 reserved_2[0x18]; 8075 u8 attenuation_5g[0x8]; 8076 8077 u8 reserved_3[0x18]; 8078 u8 attenuation_7g[0x8]; 8079 8080 u8 reserved_4[0x18]; 8081 u8 attenuation_12g[0x8]; 8082 }; 8083 8084 struct mlx5_ifc_pmpe_reg_bits { 8085 u8 reserved_0[0x8]; 8086 u8 module[0x8]; 8087 u8 reserved_1[0xc]; 8088 u8 module_status[0x4]; 8089 8090 u8 reserved_2[0x14]; 8091 u8 error_type[0x4]; 8092 u8 reserved_3[0x8]; 8093 8094 u8 reserved_4[0x40]; 8095 }; 8096 8097 struct mlx5_ifc_pmpc_reg_bits { 8098 u8 module_state_updated[32][0x8]; 8099 }; 8100 8101 struct mlx5_ifc_pmlpn_reg_bits { 8102 u8 reserved_0[0x4]; 8103 u8 mlpn_status[0x4]; 8104 u8 local_port[0x8]; 8105 u8 reserved_1[0x10]; 8106 8107 u8 e[0x1]; 8108 u8 reserved_2[0x1f]; 8109 }; 8110 8111 struct mlx5_ifc_pmlp_reg_bits { 8112 u8 rxtx[0x1]; 8113 u8 reserved_0[0x7]; 8114 u8 local_port[0x8]; 8115 u8 reserved_1[0x8]; 8116 u8 width[0x8]; 8117 8118 u8 lane0_module_mapping[0x20]; 8119 8120 u8 lane1_module_mapping[0x20]; 8121 8122 u8 lane2_module_mapping[0x20]; 8123 8124 u8 lane3_module_mapping[0x20]; 8125 8126 u8 reserved_2[0x160]; 8127 }; 8128 8129 struct mlx5_ifc_pmaos_reg_bits { 8130 u8 reserved_0[0x8]; 8131 u8 module[0x8]; 8132 u8 reserved_1[0x4]; 8133 u8 admin_status[0x4]; 8134 u8 reserved_2[0x4]; 8135 u8 oper_status[0x4]; 8136 8137 u8 ase[0x1]; 8138 u8 ee[0x1]; 8139 u8 reserved_3[0x12]; 8140 u8 error_type[0x4]; 8141 u8 reserved_4[0x6]; 8142 u8 e[0x2]; 8143 8144 u8 reserved_5[0x40]; 8145 }; 8146 8147 struct mlx5_ifc_plpc_reg_bits { 8148 u8 reserved_0[0x4]; 8149 u8 profile_id[0xc]; 8150 u8 reserved_1[0x4]; 8151 u8 proto_mask[0x4]; 8152 u8 reserved_2[0x8]; 8153 8154 u8 reserved_3[0x10]; 8155 u8 lane_speed[0x10]; 8156 8157 u8 reserved_4[0x17]; 8158 u8 lpbf[0x1]; 8159 u8 fec_mode_policy[0x8]; 8160 8161 u8 retransmission_capability[0x8]; 8162 u8 fec_mode_capability[0x18]; 8163 8164 u8 retransmission_support_admin[0x8]; 8165 u8 fec_mode_support_admin[0x18]; 8166 8167 u8 retransmission_request_admin[0x8]; 8168 u8 fec_mode_request_admin[0x18]; 8169 8170 u8 reserved_5[0x80]; 8171 }; 8172 8173 struct mlx5_ifc_pll_status_data_bits { 8174 u8 reserved_0[0x1]; 8175 u8 lock_cal[0x1]; 8176 u8 lock_status[0x2]; 8177 u8 reserved_1[0x2]; 8178 u8 algo_f_ctrl[0xa]; 8179 u8 analog_algo_num_var[0x6]; 8180 u8 f_ctrl_measure[0xa]; 8181 8182 u8 reserved_2[0x2]; 8183 u8 analog_var[0x6]; 8184 u8 reserved_3[0x2]; 8185 u8 high_var[0x6]; 8186 u8 reserved_4[0x2]; 8187 u8 low_var[0x6]; 8188 u8 reserved_5[0x2]; 8189 u8 mid_val[0x6]; 8190 }; 8191 8192 struct mlx5_ifc_plib_reg_bits { 8193 u8 reserved_0[0x8]; 8194 u8 local_port[0x8]; 8195 u8 reserved_1[0x8]; 8196 u8 ib_port[0x8]; 8197 8198 u8 reserved_2[0x60]; 8199 }; 8200 8201 struct mlx5_ifc_plbf_reg_bits { 8202 u8 reserved_0[0x8]; 8203 u8 local_port[0x8]; 8204 u8 reserved_1[0xd]; 8205 u8 lbf_mode[0x3]; 8206 8207 u8 reserved_2[0x20]; 8208 }; 8209 8210 struct mlx5_ifc_pipg_reg_bits { 8211 u8 reserved_0[0x8]; 8212 u8 local_port[0x8]; 8213 u8 reserved_1[0x10]; 8214 8215 u8 dic[0x1]; 8216 u8 reserved_2[0x19]; 8217 u8 ipg[0x4]; 8218 u8 reserved_3[0x2]; 8219 }; 8220 8221 struct mlx5_ifc_pifr_reg_bits { 8222 u8 reserved_0[0x8]; 8223 u8 local_port[0x8]; 8224 u8 reserved_1[0x10]; 8225 8226 u8 reserved_2[0xe0]; 8227 8228 u8 port_filter[8][0x20]; 8229 8230 u8 port_filter_update_en[8][0x20]; 8231 }; 8232 8233 struct mlx5_ifc_phys_layer_cntrs_bits { 8234 u8 time_since_last_clear_high[0x20]; 8235 8236 u8 time_since_last_clear_low[0x20]; 8237 8238 u8 symbol_errors_high[0x20]; 8239 8240 u8 symbol_errors_low[0x20]; 8241 8242 u8 sync_headers_errors_high[0x20]; 8243 8244 u8 sync_headers_errors_low[0x20]; 8245 8246 u8 edpl_bip_errors_lane0_high[0x20]; 8247 8248 u8 edpl_bip_errors_lane0_low[0x20]; 8249 8250 u8 edpl_bip_errors_lane1_high[0x20]; 8251 8252 u8 edpl_bip_errors_lane1_low[0x20]; 8253 8254 u8 edpl_bip_errors_lane2_high[0x20]; 8255 8256 u8 edpl_bip_errors_lane2_low[0x20]; 8257 8258 u8 edpl_bip_errors_lane3_high[0x20]; 8259 8260 u8 edpl_bip_errors_lane3_low[0x20]; 8261 8262 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 8263 8264 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 8265 8266 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 8267 8268 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 8269 8270 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 8271 8272 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 8273 8274 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 8275 8276 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 8277 8278 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 8279 8280 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 8281 8282 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 8283 8284 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 8285 8286 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 8287 8288 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 8289 8290 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 8291 8292 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 8293 8294 u8 rs_fec_corrected_blocks_high[0x20]; 8295 8296 u8 rs_fec_corrected_blocks_low[0x20]; 8297 8298 u8 rs_fec_uncorrectable_blocks_high[0x20]; 8299 8300 u8 rs_fec_uncorrectable_blocks_low[0x20]; 8301 8302 u8 rs_fec_no_errors_blocks_high[0x20]; 8303 8304 u8 rs_fec_no_errors_blocks_low[0x20]; 8305 8306 u8 rs_fec_single_error_blocks_high[0x20]; 8307 8308 u8 rs_fec_single_error_blocks_low[0x20]; 8309 8310 u8 rs_fec_corrected_symbols_total_high[0x20]; 8311 8312 u8 rs_fec_corrected_symbols_total_low[0x20]; 8313 8314 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 8315 8316 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 8317 8318 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 8319 8320 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 8321 8322 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 8323 8324 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 8325 8326 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 8327 8328 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 8329 8330 u8 link_down_events[0x20]; 8331 8332 u8 successful_recovery_events[0x20]; 8333 8334 u8 reserved_0[0x180]; 8335 }; 8336 8337 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 8338 u8 symbol_error_counter[0x10]; 8339 8340 u8 link_error_recovery_counter[0x8]; 8341 8342 u8 link_downed_counter[0x8]; 8343 8344 u8 port_rcv_errors[0x10]; 8345 8346 u8 port_rcv_remote_physical_errors[0x10]; 8347 8348 u8 port_rcv_switch_relay_errors[0x10]; 8349 8350 u8 port_xmit_discards[0x10]; 8351 8352 u8 port_xmit_constraint_errors[0x8]; 8353 8354 u8 port_rcv_constraint_errors[0x8]; 8355 8356 u8 reserved_at_70[0x8]; 8357 8358 u8 link_overrun_errors[0x8]; 8359 8360 u8 reserved_at_80[0x10]; 8361 8362 u8 vl_15_dropped[0x10]; 8363 8364 u8 reserved_at_a0[0xa0]; 8365 }; 8366 8367 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 8368 u8 time_since_last_clear_high[0x20]; 8369 8370 u8 time_since_last_clear_low[0x20]; 8371 8372 u8 phy_received_bits_high[0x20]; 8373 8374 u8 phy_received_bits_low[0x20]; 8375 8376 u8 phy_symbol_errors_high[0x20]; 8377 8378 u8 phy_symbol_errors_low[0x20]; 8379 8380 u8 phy_corrected_bits_high[0x20]; 8381 8382 u8 phy_corrected_bits_low[0x20]; 8383 8384 u8 phy_corrected_bits_lane0_high[0x20]; 8385 8386 u8 phy_corrected_bits_lane0_low[0x20]; 8387 8388 u8 phy_corrected_bits_lane1_high[0x20]; 8389 8390 u8 phy_corrected_bits_lane1_low[0x20]; 8391 8392 u8 phy_corrected_bits_lane2_high[0x20]; 8393 8394 u8 phy_corrected_bits_lane2_low[0x20]; 8395 8396 u8 phy_corrected_bits_lane3_high[0x20]; 8397 8398 u8 phy_corrected_bits_lane3_low[0x20]; 8399 8400 u8 reserved_at_200[0x5c0]; 8401 }; 8402 8403 struct mlx5_ifc_infiniband_port_cntrs_bits { 8404 u8 symbol_error_counter[0x10]; 8405 u8 link_error_recovery_counter[0x8]; 8406 u8 link_downed_counter[0x8]; 8407 8408 u8 port_rcv_errors[0x10]; 8409 u8 port_rcv_remote_physical_errors[0x10]; 8410 8411 u8 port_rcv_switch_relay_errors[0x10]; 8412 u8 port_xmit_discards[0x10]; 8413 8414 u8 port_xmit_constraint_errors[0x8]; 8415 u8 port_rcv_constraint_errors[0x8]; 8416 u8 reserved_0[0x8]; 8417 u8 local_link_integrity_errors[0x4]; 8418 u8 excessive_buffer_overrun_errors[0x4]; 8419 8420 u8 reserved_1[0x10]; 8421 u8 vl_15_dropped[0x10]; 8422 8423 u8 port_xmit_data[0x20]; 8424 8425 u8 port_rcv_data[0x20]; 8426 8427 u8 port_xmit_pkts[0x20]; 8428 8429 u8 port_rcv_pkts[0x20]; 8430 8431 u8 port_xmit_wait[0x20]; 8432 8433 u8 reserved_2[0x680]; 8434 }; 8435 8436 struct mlx5_ifc_phrr_reg_bits { 8437 u8 clr[0x1]; 8438 u8 reserved_0[0x7]; 8439 u8 local_port[0x8]; 8440 u8 reserved_1[0x10]; 8441 8442 u8 hist_group[0x8]; 8443 u8 reserved_2[0x10]; 8444 u8 hist_id[0x8]; 8445 8446 u8 reserved_3[0x40]; 8447 8448 u8 time_since_last_clear_high[0x20]; 8449 8450 u8 time_since_last_clear_low[0x20]; 8451 8452 u8 bin[10][0x20]; 8453 }; 8454 8455 struct mlx5_ifc_phbr_for_prio_reg_bits { 8456 u8 reserved_0[0x18]; 8457 u8 prio[0x8]; 8458 }; 8459 8460 struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8461 u8 reserved_0[0x18]; 8462 u8 tclass[0x8]; 8463 }; 8464 8465 struct mlx5_ifc_phbr_binding_reg_bits { 8466 u8 opcode[0x4]; 8467 u8 reserved_0[0x4]; 8468 u8 local_port[0x8]; 8469 u8 pnat[0x2]; 8470 u8 reserved_1[0xe]; 8471 8472 u8 hist_group[0x8]; 8473 u8 reserved_2[0x10]; 8474 u8 hist_id[0x8]; 8475 8476 u8 reserved_3[0x10]; 8477 u8 hist_type[0x10]; 8478 8479 u8 hist_parameters[0x20]; 8480 8481 u8 hist_min_value[0x20]; 8482 8483 u8 hist_max_value[0x20]; 8484 8485 u8 sample_time[0x20]; 8486 }; 8487 8488 enum { 8489 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 8490 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 8491 }; 8492 8493 struct mlx5_ifc_pfcc_reg_bits { 8494 u8 dcbx_operation_type[0x2]; 8495 u8 cap_local_admin[0x1]; 8496 u8 cap_remote_admin[0x1]; 8497 u8 reserved_0[0x4]; 8498 u8 local_port[0x8]; 8499 u8 pnat[0x2]; 8500 u8 reserved_1[0xc]; 8501 u8 shl_cap[0x1]; 8502 u8 shl_opr[0x1]; 8503 8504 u8 ppan[0x4]; 8505 u8 reserved_2[0x4]; 8506 u8 prio_mask_tx[0x8]; 8507 u8 reserved_3[0x8]; 8508 u8 prio_mask_rx[0x8]; 8509 8510 u8 pptx[0x1]; 8511 u8 aptx[0x1]; 8512 u8 reserved_4[0x6]; 8513 u8 pfctx[0x8]; 8514 u8 reserved_5[0x8]; 8515 u8 cbftx[0x8]; 8516 8517 u8 pprx[0x1]; 8518 u8 aprx[0x1]; 8519 u8 reserved_6[0x6]; 8520 u8 pfcrx[0x8]; 8521 u8 reserved_7[0x8]; 8522 u8 cbfrx[0x8]; 8523 8524 u8 device_stall_minor_watermark[0x10]; 8525 u8 device_stall_critical_watermark[0x10]; 8526 8527 u8 reserved_8[0x60]; 8528 }; 8529 8530 struct mlx5_ifc_pelc_reg_bits { 8531 u8 op[0x4]; 8532 u8 reserved_0[0x4]; 8533 u8 local_port[0x8]; 8534 u8 reserved_1[0x10]; 8535 8536 u8 op_admin[0x8]; 8537 u8 op_capability[0x8]; 8538 u8 op_request[0x8]; 8539 u8 op_active[0x8]; 8540 8541 u8 admin[0x40]; 8542 8543 u8 capability[0x40]; 8544 8545 u8 request[0x40]; 8546 8547 u8 active[0x40]; 8548 8549 u8 reserved_2[0x80]; 8550 }; 8551 8552 struct mlx5_ifc_peir_reg_bits { 8553 u8 reserved_0[0x8]; 8554 u8 local_port[0x8]; 8555 u8 reserved_1[0x10]; 8556 8557 u8 reserved_2[0xc]; 8558 u8 error_count[0x4]; 8559 u8 reserved_3[0x10]; 8560 8561 u8 reserved_4[0xc]; 8562 u8 lane[0x4]; 8563 u8 reserved_5[0x8]; 8564 u8 error_type[0x8]; 8565 }; 8566 8567 struct mlx5_ifc_qcam_access_reg_cap_mask { 8568 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8569 u8 qpdpm[0x1]; 8570 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8571 u8 qdpm[0x1]; 8572 u8 qpts[0x1]; 8573 u8 qcap[0x1]; 8574 u8 qcam_access_reg_cap_mask_0[0x1]; 8575 }; 8576 8577 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8578 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8579 u8 qpts_trust_both[0x1]; 8580 }; 8581 8582 struct mlx5_ifc_qcam_reg_bits { 8583 u8 reserved_at_0[0x8]; 8584 u8 feature_group[0x8]; 8585 u8 reserved_at_10[0x8]; 8586 u8 access_reg_group[0x8]; 8587 u8 reserved_at_20[0x20]; 8588 8589 union { 8590 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8591 u8 reserved_at_0[0x80]; 8592 } qos_access_reg_cap_mask; 8593 8594 u8 reserved_at_c0[0x80]; 8595 8596 union { 8597 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8598 u8 reserved_at_0[0x80]; 8599 } qos_feature_cap_mask; 8600 8601 u8 reserved_at_1c0[0x80]; 8602 }; 8603 8604 struct mlx5_ifc_pcam_enhanced_features_bits { 8605 u8 reserved_at_0[0x6d]; 8606 u8 rx_icrc_encapsulated_counter[0x1]; 8607 u8 reserved_at_6e[0x4]; 8608 u8 ptys_extended_ethernet[0x1]; 8609 u8 reserved_at_73[0x3]; 8610 u8 pfcc_mask[0x1]; 8611 u8 reserved_at_77[0x3]; 8612 u8 per_lane_error_counters[0x1]; 8613 u8 rx_buffer_fullness_counters[0x1]; 8614 u8 ptys_connector_type[0x1]; 8615 u8 reserved_at_7d[0x1]; 8616 u8 ppcnt_discard_group[0x1]; 8617 u8 ppcnt_statistical_group[0x1]; 8618 }; 8619 8620 struct mlx5_ifc_pcam_reg_bits { 8621 u8 reserved_at_0[0x8]; 8622 u8 feature_group[0x8]; 8623 u8 reserved_at_10[0x8]; 8624 u8 access_reg_group[0x8]; 8625 8626 u8 reserved_at_20[0x20]; 8627 8628 union { 8629 u8 reserved_at_0[0x80]; 8630 } port_access_reg_cap_mask; 8631 8632 u8 reserved_at_c0[0x80]; 8633 8634 union { 8635 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8636 u8 reserved_at_0[0x80]; 8637 } feature_cap_mask; 8638 8639 u8 reserved_at_1c0[0xc0]; 8640 }; 8641 8642 struct mlx5_ifc_mcam_enhanced_features_bits { 8643 u8 reserved_at_0[0x6e]; 8644 u8 pcie_status_and_power[0x1]; 8645 u8 reserved_at_111[0x10]; 8646 u8 pcie_performance_group[0x1]; 8647 }; 8648 8649 struct mlx5_ifc_mcam_access_reg_bits { 8650 u8 reserved_at_0[0x1c]; 8651 u8 mcda[0x1]; 8652 u8 mcc[0x1]; 8653 u8 mcqi[0x1]; 8654 u8 reserved_at_1f[0x1]; 8655 8656 u8 regs_95_to_64[0x20]; 8657 u8 regs_63_to_32[0x20]; 8658 u8 regs_31_to_0[0x20]; 8659 }; 8660 8661 struct mlx5_ifc_mcam_reg_bits { 8662 u8 reserved_at_0[0x8]; 8663 u8 feature_group[0x8]; 8664 u8 reserved_at_10[0x8]; 8665 u8 access_reg_group[0x8]; 8666 8667 u8 reserved_at_20[0x20]; 8668 8669 union { 8670 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8671 u8 reserved_at_0[0x80]; 8672 } mng_access_reg_cap_mask; 8673 8674 u8 reserved_at_c0[0x80]; 8675 8676 union { 8677 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8678 u8 reserved_at_0[0x80]; 8679 } mng_feature_cap_mask; 8680 8681 u8 reserved_at_1c0[0x80]; 8682 }; 8683 8684 struct mlx5_ifc_pcap_reg_bits { 8685 u8 reserved_0[0x8]; 8686 u8 local_port[0x8]; 8687 u8 reserved_1[0x10]; 8688 8689 u8 port_capability_mask[4][0x20]; 8690 }; 8691 8692 struct mlx5_ifc_pbmc_reg_bits { 8693 u8 reserved_0[0x8]; 8694 u8 local_port[0x8]; 8695 u8 reserved_1[0x10]; 8696 8697 u8 xoff_timer_value[0x10]; 8698 u8 xoff_refresh[0x10]; 8699 8700 u8 reserved_2[0x10]; 8701 u8 port_buffer_size[0x10]; 8702 8703 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8704 8705 u8 reserved_3[0x40]; 8706 8707 u8 port_shared_buffer[0x40]; 8708 }; 8709 8710 struct mlx5_ifc_paos_reg_bits { 8711 u8 swid[0x8]; 8712 u8 local_port[0x8]; 8713 u8 reserved_0[0x4]; 8714 u8 admin_status[0x4]; 8715 u8 reserved_1[0x4]; 8716 u8 oper_status[0x4]; 8717 8718 u8 ase[0x1]; 8719 u8 ee[0x1]; 8720 u8 reserved_2[0x1c]; 8721 u8 e[0x2]; 8722 8723 u8 reserved_3[0x40]; 8724 }; 8725 8726 struct mlx5_ifc_pamp_reg_bits { 8727 u8 reserved_0[0x8]; 8728 u8 opamp_group[0x8]; 8729 u8 reserved_1[0xc]; 8730 u8 opamp_group_type[0x4]; 8731 8732 u8 start_index[0x10]; 8733 u8 reserved_2[0x4]; 8734 u8 num_of_indices[0xc]; 8735 8736 u8 index_data[18][0x10]; 8737 }; 8738 8739 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 8740 u8 llr_rx_cells_high[0x20]; 8741 8742 u8 llr_rx_cells_low[0x20]; 8743 8744 u8 llr_rx_error_high[0x20]; 8745 8746 u8 llr_rx_error_low[0x20]; 8747 8748 u8 llr_rx_crc_error_high[0x20]; 8749 8750 u8 llr_rx_crc_error_low[0x20]; 8751 8752 u8 llr_tx_cells_high[0x20]; 8753 8754 u8 llr_tx_cells_low[0x20]; 8755 8756 u8 llr_tx_ret_cells_high[0x20]; 8757 8758 u8 llr_tx_ret_cells_low[0x20]; 8759 8760 u8 llr_tx_ret_events_high[0x20]; 8761 8762 u8 llr_tx_ret_events_low[0x20]; 8763 8764 u8 reserved_0[0x640]; 8765 }; 8766 8767 struct mlx5_ifc_mtmp_reg_bits { 8768 u8 i[0x1]; 8769 u8 reserved_at_1[0x18]; 8770 u8 sensor_index[0x7]; 8771 8772 u8 reserved_at_20[0x10]; 8773 u8 temperature[0x10]; 8774 8775 u8 mte[0x1]; 8776 u8 mtr[0x1]; 8777 u8 reserved_at_42[0x0e]; 8778 u8 max_temperature[0x10]; 8779 8780 u8 tee[0x2]; 8781 u8 reserved_at_62[0x0e]; 8782 u8 temperature_threshold_hi[0x10]; 8783 8784 u8 reserved_at_80[0x10]; 8785 u8 temperature_threshold_lo[0x10]; 8786 8787 u8 reserved_at_100[0x20]; 8788 8789 u8 sensor_name[0x40]; 8790 }; 8791 8792 struct mlx5_ifc_lane_2_module_mapping_bits { 8793 u8 reserved_0[0x6]; 8794 u8 rx_lane[0x2]; 8795 u8 reserved_1[0x6]; 8796 u8 tx_lane[0x2]; 8797 u8 reserved_2[0x8]; 8798 u8 module[0x8]; 8799 }; 8800 8801 struct mlx5_ifc_eth_per_traffic_class_layout_bits { 8802 u8 transmit_queue_high[0x20]; 8803 8804 u8 transmit_queue_low[0x20]; 8805 8806 u8 reserved_0[0x780]; 8807 }; 8808 8809 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 8810 u8 no_buffer_discard_uc_high[0x20]; 8811 8812 u8 no_buffer_discard_uc_low[0x20]; 8813 8814 u8 wred_discard_high[0x20]; 8815 8816 u8 wred_discard_low[0x20]; 8817 8818 u8 reserved_0[0x740]; 8819 }; 8820 8821 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 8822 u8 rx_octets_high[0x20]; 8823 8824 u8 rx_octets_low[0x20]; 8825 8826 u8 reserved_0[0xc0]; 8827 8828 u8 rx_frames_high[0x20]; 8829 8830 u8 rx_frames_low[0x20]; 8831 8832 u8 tx_octets_high[0x20]; 8833 8834 u8 tx_octets_low[0x20]; 8835 8836 u8 reserved_1[0xc0]; 8837 8838 u8 tx_frames_high[0x20]; 8839 8840 u8 tx_frames_low[0x20]; 8841 8842 u8 rx_pause_high[0x20]; 8843 8844 u8 rx_pause_low[0x20]; 8845 8846 u8 rx_pause_duration_high[0x20]; 8847 8848 u8 rx_pause_duration_low[0x20]; 8849 8850 u8 tx_pause_high[0x20]; 8851 8852 u8 tx_pause_low[0x20]; 8853 8854 u8 tx_pause_duration_high[0x20]; 8855 8856 u8 tx_pause_duration_low[0x20]; 8857 8858 u8 rx_pause_transition_high[0x20]; 8859 8860 u8 rx_pause_transition_low[0x20]; 8861 8862 u8 rx_discards_high[0x20]; 8863 8864 u8 rx_discards_low[0x20]; 8865 8866 u8 device_stall_minor_watermark_cnt_high[0x20]; 8867 8868 u8 device_stall_minor_watermark_cnt_low[0x20]; 8869 8870 u8 device_stall_critical_watermark_cnt_high[0x20]; 8871 8872 u8 device_stall_critical_watermark_cnt_low[0x20]; 8873 8874 u8 reserved_2[0x340]; 8875 }; 8876 8877 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 8878 u8 port_transmit_wait_high[0x20]; 8879 8880 u8 port_transmit_wait_low[0x20]; 8881 8882 u8 ecn_marked_high[0x20]; 8883 8884 u8 ecn_marked_low[0x20]; 8885 8886 u8 no_buffer_discard_mc_high[0x20]; 8887 8888 u8 no_buffer_discard_mc_low[0x20]; 8889 8890 u8 rx_ebp_high[0x20]; 8891 8892 u8 rx_ebp_low[0x20]; 8893 8894 u8 tx_ebp_high[0x20]; 8895 8896 u8 tx_ebp_low[0x20]; 8897 8898 u8 rx_buffer_almost_full_high[0x20]; 8899 8900 u8 rx_buffer_almost_full_low[0x20]; 8901 8902 u8 rx_buffer_full_high[0x20]; 8903 8904 u8 rx_buffer_full_low[0x20]; 8905 8906 u8 rx_icrc_encapsulated_high[0x20]; 8907 8908 u8 rx_icrc_encapsulated_low[0x20]; 8909 8910 u8 reserved_0[0x80]; 8911 8912 u8 tx_stats_pkts64octets_high[0x20]; 8913 8914 u8 tx_stats_pkts64octets_low[0x20]; 8915 8916 u8 tx_stats_pkts65to127octets_high[0x20]; 8917 8918 u8 tx_stats_pkts65to127octets_low[0x20]; 8919 8920 u8 tx_stats_pkts128to255octets_high[0x20]; 8921 8922 u8 tx_stats_pkts128to255octets_low[0x20]; 8923 8924 u8 tx_stats_pkts256to511octets_high[0x20]; 8925 8926 u8 tx_stats_pkts256to511octets_low[0x20]; 8927 8928 u8 tx_stats_pkts512to1023octets_high[0x20]; 8929 8930 u8 tx_stats_pkts512to1023octets_low[0x20]; 8931 8932 u8 tx_stats_pkts1024to1518octets_high[0x20]; 8933 8934 u8 tx_stats_pkts1024to1518octets_low[0x20]; 8935 8936 u8 tx_stats_pkts1519to2047octets_high[0x20]; 8937 8938 u8 tx_stats_pkts1519to2047octets_low[0x20]; 8939 8940 u8 tx_stats_pkts2048to4095octets_high[0x20]; 8941 8942 u8 tx_stats_pkts2048to4095octets_low[0x20]; 8943 8944 u8 tx_stats_pkts4096to8191octets_high[0x20]; 8945 8946 u8 tx_stats_pkts4096to8191octets_low[0x20]; 8947 8948 u8 tx_stats_pkts8192to10239octets_high[0x20]; 8949 8950 u8 tx_stats_pkts8192to10239octets_low[0x20]; 8951 8952 u8 reserved_1[0x2C0]; 8953 }; 8954 8955 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 8956 u8 a_frames_transmitted_ok_high[0x20]; 8957 8958 u8 a_frames_transmitted_ok_low[0x20]; 8959 8960 u8 a_frames_received_ok_high[0x20]; 8961 8962 u8 a_frames_received_ok_low[0x20]; 8963 8964 u8 a_frame_check_sequence_errors_high[0x20]; 8965 8966 u8 a_frame_check_sequence_errors_low[0x20]; 8967 8968 u8 a_alignment_errors_high[0x20]; 8969 8970 u8 a_alignment_errors_low[0x20]; 8971 8972 u8 a_octets_transmitted_ok_high[0x20]; 8973 8974 u8 a_octets_transmitted_ok_low[0x20]; 8975 8976 u8 a_octets_received_ok_high[0x20]; 8977 8978 u8 a_octets_received_ok_low[0x20]; 8979 8980 u8 a_multicast_frames_xmitted_ok_high[0x20]; 8981 8982 u8 a_multicast_frames_xmitted_ok_low[0x20]; 8983 8984 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 8985 8986 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 8987 8988 u8 a_multicast_frames_received_ok_high[0x20]; 8989 8990 u8 a_multicast_frames_received_ok_low[0x20]; 8991 8992 u8 a_broadcast_frames_recieved_ok_high[0x20]; 8993 8994 u8 a_broadcast_frames_recieved_ok_low[0x20]; 8995 8996 u8 a_in_range_length_errors_high[0x20]; 8997 8998 u8 a_in_range_length_errors_low[0x20]; 8999 9000 u8 a_out_of_range_length_field_high[0x20]; 9001 9002 u8 a_out_of_range_length_field_low[0x20]; 9003 9004 u8 a_frame_too_long_errors_high[0x20]; 9005 9006 u8 a_frame_too_long_errors_low[0x20]; 9007 9008 u8 a_symbol_error_during_carrier_high[0x20]; 9009 9010 u8 a_symbol_error_during_carrier_low[0x20]; 9011 9012 u8 a_mac_control_frames_transmitted_high[0x20]; 9013 9014 u8 a_mac_control_frames_transmitted_low[0x20]; 9015 9016 u8 a_mac_control_frames_received_high[0x20]; 9017 9018 u8 a_mac_control_frames_received_low[0x20]; 9019 9020 u8 a_unsupported_opcodes_received_high[0x20]; 9021 9022 u8 a_unsupported_opcodes_received_low[0x20]; 9023 9024 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 9025 9026 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 9027 9028 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 9029 9030 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 9031 9032 u8 reserved_0[0x300]; 9033 }; 9034 9035 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 9036 u8 dot3stats_alignment_errors_high[0x20]; 9037 9038 u8 dot3stats_alignment_errors_low[0x20]; 9039 9040 u8 dot3stats_fcs_errors_high[0x20]; 9041 9042 u8 dot3stats_fcs_errors_low[0x20]; 9043 9044 u8 dot3stats_single_collision_frames_high[0x20]; 9045 9046 u8 dot3stats_single_collision_frames_low[0x20]; 9047 9048 u8 dot3stats_multiple_collision_frames_high[0x20]; 9049 9050 u8 dot3stats_multiple_collision_frames_low[0x20]; 9051 9052 u8 dot3stats_sqe_test_errors_high[0x20]; 9053 9054 u8 dot3stats_sqe_test_errors_low[0x20]; 9055 9056 u8 dot3stats_deferred_transmissions_high[0x20]; 9057 9058 u8 dot3stats_deferred_transmissions_low[0x20]; 9059 9060 u8 dot3stats_late_collisions_high[0x20]; 9061 9062 u8 dot3stats_late_collisions_low[0x20]; 9063 9064 u8 dot3stats_excessive_collisions_high[0x20]; 9065 9066 u8 dot3stats_excessive_collisions_low[0x20]; 9067 9068 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 9069 9070 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 9071 9072 u8 dot3stats_carrier_sense_errors_high[0x20]; 9073 9074 u8 dot3stats_carrier_sense_errors_low[0x20]; 9075 9076 u8 dot3stats_frame_too_longs_high[0x20]; 9077 9078 u8 dot3stats_frame_too_longs_low[0x20]; 9079 9080 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 9081 9082 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 9083 9084 u8 dot3stats_symbol_errors_high[0x20]; 9085 9086 u8 dot3stats_symbol_errors_low[0x20]; 9087 9088 u8 dot3control_in_unknown_opcodes_high[0x20]; 9089 9090 u8 dot3control_in_unknown_opcodes_low[0x20]; 9091 9092 u8 dot3in_pause_frames_high[0x20]; 9093 9094 u8 dot3in_pause_frames_low[0x20]; 9095 9096 u8 dot3out_pause_frames_high[0x20]; 9097 9098 u8 dot3out_pause_frames_low[0x20]; 9099 9100 u8 reserved_0[0x3c0]; 9101 }; 9102 9103 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 9104 u8 if_in_octets_high[0x20]; 9105 9106 u8 if_in_octets_low[0x20]; 9107 9108 u8 if_in_ucast_pkts_high[0x20]; 9109 9110 u8 if_in_ucast_pkts_low[0x20]; 9111 9112 u8 if_in_discards_high[0x20]; 9113 9114 u8 if_in_discards_low[0x20]; 9115 9116 u8 if_in_errors_high[0x20]; 9117 9118 u8 if_in_errors_low[0x20]; 9119 9120 u8 if_in_unknown_protos_high[0x20]; 9121 9122 u8 if_in_unknown_protos_low[0x20]; 9123 9124 u8 if_out_octets_high[0x20]; 9125 9126 u8 if_out_octets_low[0x20]; 9127 9128 u8 if_out_ucast_pkts_high[0x20]; 9129 9130 u8 if_out_ucast_pkts_low[0x20]; 9131 9132 u8 if_out_discards_high[0x20]; 9133 9134 u8 if_out_discards_low[0x20]; 9135 9136 u8 if_out_errors_high[0x20]; 9137 9138 u8 if_out_errors_low[0x20]; 9139 9140 u8 if_in_multicast_pkts_high[0x20]; 9141 9142 u8 if_in_multicast_pkts_low[0x20]; 9143 9144 u8 if_in_broadcast_pkts_high[0x20]; 9145 9146 u8 if_in_broadcast_pkts_low[0x20]; 9147 9148 u8 if_out_multicast_pkts_high[0x20]; 9149 9150 u8 if_out_multicast_pkts_low[0x20]; 9151 9152 u8 if_out_broadcast_pkts_high[0x20]; 9153 9154 u8 if_out_broadcast_pkts_low[0x20]; 9155 9156 u8 reserved_0[0x480]; 9157 }; 9158 9159 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 9160 u8 ether_stats_drop_events_high[0x20]; 9161 9162 u8 ether_stats_drop_events_low[0x20]; 9163 9164 u8 ether_stats_octets_high[0x20]; 9165 9166 u8 ether_stats_octets_low[0x20]; 9167 9168 u8 ether_stats_pkts_high[0x20]; 9169 9170 u8 ether_stats_pkts_low[0x20]; 9171 9172 u8 ether_stats_broadcast_pkts_high[0x20]; 9173 9174 u8 ether_stats_broadcast_pkts_low[0x20]; 9175 9176 u8 ether_stats_multicast_pkts_high[0x20]; 9177 9178 u8 ether_stats_multicast_pkts_low[0x20]; 9179 9180 u8 ether_stats_crc_align_errors_high[0x20]; 9181 9182 u8 ether_stats_crc_align_errors_low[0x20]; 9183 9184 u8 ether_stats_undersize_pkts_high[0x20]; 9185 9186 u8 ether_stats_undersize_pkts_low[0x20]; 9187 9188 u8 ether_stats_oversize_pkts_high[0x20]; 9189 9190 u8 ether_stats_oversize_pkts_low[0x20]; 9191 9192 u8 ether_stats_fragments_high[0x20]; 9193 9194 u8 ether_stats_fragments_low[0x20]; 9195 9196 u8 ether_stats_jabbers_high[0x20]; 9197 9198 u8 ether_stats_jabbers_low[0x20]; 9199 9200 u8 ether_stats_collisions_high[0x20]; 9201 9202 u8 ether_stats_collisions_low[0x20]; 9203 9204 u8 ether_stats_pkts64octets_high[0x20]; 9205 9206 u8 ether_stats_pkts64octets_low[0x20]; 9207 9208 u8 ether_stats_pkts65to127octets_high[0x20]; 9209 9210 u8 ether_stats_pkts65to127octets_low[0x20]; 9211 9212 u8 ether_stats_pkts128to255octets_high[0x20]; 9213 9214 u8 ether_stats_pkts128to255octets_low[0x20]; 9215 9216 u8 ether_stats_pkts256to511octets_high[0x20]; 9217 9218 u8 ether_stats_pkts256to511octets_low[0x20]; 9219 9220 u8 ether_stats_pkts512to1023octets_high[0x20]; 9221 9222 u8 ether_stats_pkts512to1023octets_low[0x20]; 9223 9224 u8 ether_stats_pkts1024to1518octets_high[0x20]; 9225 9226 u8 ether_stats_pkts1024to1518octets_low[0x20]; 9227 9228 u8 ether_stats_pkts1519to2047octets_high[0x20]; 9229 9230 u8 ether_stats_pkts1519to2047octets_low[0x20]; 9231 9232 u8 ether_stats_pkts2048to4095octets_high[0x20]; 9233 9234 u8 ether_stats_pkts2048to4095octets_low[0x20]; 9235 9236 u8 ether_stats_pkts4096to8191octets_high[0x20]; 9237 9238 u8 ether_stats_pkts4096to8191octets_low[0x20]; 9239 9240 u8 ether_stats_pkts8192to10239octets_high[0x20]; 9241 9242 u8 ether_stats_pkts8192to10239octets_low[0x20]; 9243 9244 u8 reserved_0[0x280]; 9245 }; 9246 9247 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 9248 u8 symbol_error_counter[0x10]; 9249 u8 link_error_recovery_counter[0x8]; 9250 u8 link_downed_counter[0x8]; 9251 9252 u8 port_rcv_errors[0x10]; 9253 u8 port_rcv_remote_physical_errors[0x10]; 9254 9255 u8 port_rcv_switch_relay_errors[0x10]; 9256 u8 port_xmit_discards[0x10]; 9257 9258 u8 port_xmit_constraint_errors[0x8]; 9259 u8 port_rcv_constraint_errors[0x8]; 9260 u8 reserved_0[0x8]; 9261 u8 local_link_integrity_errors[0x4]; 9262 u8 excessive_buffer_overrun_errors[0x4]; 9263 9264 u8 reserved_1[0x10]; 9265 u8 vl_15_dropped[0x10]; 9266 9267 u8 port_xmit_data[0x20]; 9268 9269 u8 port_rcv_data[0x20]; 9270 9271 u8 port_xmit_pkts[0x20]; 9272 9273 u8 port_rcv_pkts[0x20]; 9274 9275 u8 port_xmit_wait[0x20]; 9276 9277 u8 reserved_2[0x680]; 9278 }; 9279 9280 struct mlx5_ifc_trc_tlb_reg_bits { 9281 u8 reserved_0[0x80]; 9282 9283 u8 tlb_addr[0][0x40]; 9284 }; 9285 9286 struct mlx5_ifc_trc_read_fifo_reg_bits { 9287 u8 reserved_0[0x10]; 9288 u8 requested_event_num[0x10]; 9289 9290 u8 reserved_1[0x20]; 9291 9292 u8 reserved_2[0x10]; 9293 u8 acual_event_num[0x10]; 9294 9295 u8 reserved_3[0x20]; 9296 9297 u8 event[0][0x40]; 9298 }; 9299 9300 struct mlx5_ifc_trc_lock_reg_bits { 9301 u8 reserved_0[0x1f]; 9302 u8 lock[0x1]; 9303 9304 u8 reserved_1[0x60]; 9305 }; 9306 9307 struct mlx5_ifc_trc_filter_reg_bits { 9308 u8 status[0x1]; 9309 u8 reserved_0[0xf]; 9310 u8 filter_index[0x10]; 9311 9312 u8 reserved_1[0x20]; 9313 9314 u8 filter_val[0x20]; 9315 9316 u8 reserved_2[0x1a0]; 9317 }; 9318 9319 struct mlx5_ifc_trc_event_reg_bits { 9320 u8 status[0x1]; 9321 u8 reserved_0[0xf]; 9322 u8 event_index[0x10]; 9323 9324 u8 reserved_1[0x20]; 9325 9326 u8 event_id[0x20]; 9327 9328 u8 event_selector_val[0x10]; 9329 u8 event_selector_size[0x10]; 9330 9331 u8 reserved_2[0x180]; 9332 }; 9333 9334 struct mlx5_ifc_trc_conf_reg_bits { 9335 u8 limit_en[0x1]; 9336 u8 reserved_0[0x3]; 9337 u8 dump_mode[0x4]; 9338 u8 reserved_1[0x15]; 9339 u8 state[0x3]; 9340 9341 u8 reserved_2[0x20]; 9342 9343 u8 limit_event_index[0x20]; 9344 9345 u8 mkey[0x20]; 9346 9347 u8 fifo_ready_ev_num[0x20]; 9348 9349 u8 reserved_3[0x160]; 9350 }; 9351 9352 struct mlx5_ifc_trc_cap_reg_bits { 9353 u8 reserved_0[0x18]; 9354 u8 dump_mode[0x8]; 9355 9356 u8 reserved_1[0x20]; 9357 9358 u8 num_of_events[0x10]; 9359 u8 num_of_filters[0x10]; 9360 9361 u8 fifo_size[0x20]; 9362 9363 u8 tlb_size[0x10]; 9364 u8 event_size[0x10]; 9365 9366 u8 reserved_2[0x160]; 9367 }; 9368 9369 struct mlx5_ifc_set_node_in_bits { 9370 u8 node_description[64][0x8]; 9371 }; 9372 9373 struct mlx5_ifc_register_power_settings_bits { 9374 u8 reserved_0[0x18]; 9375 u8 power_settings_level[0x8]; 9376 9377 u8 reserved_1[0x60]; 9378 }; 9379 9380 struct mlx5_ifc_register_host_endianess_bits { 9381 u8 he[0x1]; 9382 u8 reserved_0[0x1f]; 9383 9384 u8 reserved_1[0x60]; 9385 }; 9386 9387 struct mlx5_ifc_register_diag_buffer_ctrl_bits { 9388 u8 physical_address[0x40]; 9389 }; 9390 9391 struct mlx5_ifc_qtct_reg_bits { 9392 u8 operation_type[0x2]; 9393 u8 cap_local_admin[0x1]; 9394 u8 cap_remote_admin[0x1]; 9395 u8 reserved_0[0x4]; 9396 u8 port_number[0x8]; 9397 u8 reserved_1[0xd]; 9398 u8 prio[0x3]; 9399 9400 u8 reserved_2[0x1d]; 9401 u8 tclass[0x3]; 9402 }; 9403 9404 struct mlx5_ifc_qpdp_reg_bits { 9405 u8 reserved_0[0x8]; 9406 u8 port_number[0x8]; 9407 u8 reserved_1[0x10]; 9408 9409 u8 reserved_2[0x1d]; 9410 u8 pprio[0x3]; 9411 }; 9412 9413 struct mlx5_ifc_port_info_ro_fields_param_bits { 9414 u8 reserved_0[0x8]; 9415 u8 port[0x8]; 9416 u8 max_gid[0x10]; 9417 9418 u8 reserved_1[0x20]; 9419 9420 u8 port_guid[0x40]; 9421 }; 9422 9423 struct mlx5_ifc_nvqc_reg_bits { 9424 u8 type[0x20]; 9425 9426 u8 reserved_0[0x18]; 9427 u8 version[0x4]; 9428 u8 reserved_1[0x2]; 9429 u8 support_wr[0x1]; 9430 u8 support_rd[0x1]; 9431 }; 9432 9433 struct mlx5_ifc_nvia_reg_bits { 9434 u8 reserved_0[0x1d]; 9435 u8 target[0x3]; 9436 9437 u8 reserved_1[0x20]; 9438 }; 9439 9440 struct mlx5_ifc_nvdi_reg_bits { 9441 struct mlx5_ifc_config_item_bits configuration_item_header; 9442 }; 9443 9444 struct mlx5_ifc_nvda_reg_bits { 9445 struct mlx5_ifc_config_item_bits configuration_item_header; 9446 9447 u8 configuration_item_data[0x20]; 9448 }; 9449 9450 struct mlx5_ifc_node_info_ro_fields_param_bits { 9451 u8 system_image_guid[0x40]; 9452 9453 u8 reserved_0[0x40]; 9454 9455 u8 node_guid[0x40]; 9456 9457 u8 reserved_1[0x10]; 9458 u8 max_pkey[0x10]; 9459 9460 u8 reserved_2[0x20]; 9461 }; 9462 9463 struct mlx5_ifc_ets_tcn_config_reg_bits { 9464 u8 g[0x1]; 9465 u8 b[0x1]; 9466 u8 r[0x1]; 9467 u8 reserved_0[0x9]; 9468 u8 group[0x4]; 9469 u8 reserved_1[0x9]; 9470 u8 bw_allocation[0x7]; 9471 9472 u8 reserved_2[0xc]; 9473 u8 max_bw_units[0x4]; 9474 u8 reserved_3[0x8]; 9475 u8 max_bw_value[0x8]; 9476 }; 9477 9478 struct mlx5_ifc_ets_global_config_reg_bits { 9479 u8 reserved_0[0x2]; 9480 u8 r[0x1]; 9481 u8 reserved_1[0x1d]; 9482 9483 u8 reserved_2[0xc]; 9484 u8 max_bw_units[0x4]; 9485 u8 reserved_3[0x8]; 9486 u8 max_bw_value[0x8]; 9487 }; 9488 9489 struct mlx5_ifc_qetc_reg_bits { 9490 u8 reserved_at_0[0x8]; 9491 u8 port_number[0x8]; 9492 u8 reserved_at_10[0x30]; 9493 9494 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9495 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9496 }; 9497 9498 struct mlx5_ifc_nodnic_mac_filters_bits { 9499 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 9500 9501 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 9502 9503 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 9504 9505 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 9506 9507 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 9508 9509 u8 reserved_0[0xc0]; 9510 }; 9511 9512 struct mlx5_ifc_nodnic_gid_filters_bits { 9513 u8 mgid_filter0[16][0x8]; 9514 9515 u8 mgid_filter1[16][0x8]; 9516 9517 u8 mgid_filter2[16][0x8]; 9518 9519 u8 mgid_filter3[16][0x8]; 9520 }; 9521 9522 enum { 9523 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 9524 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 9525 }; 9526 9527 enum { 9528 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 9529 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 9530 }; 9531 9532 struct mlx5_ifc_nodnic_config_reg_bits { 9533 u8 no_dram_nic_revision[0x8]; 9534 u8 hardware_format[0x8]; 9535 u8 support_receive_filter[0x1]; 9536 u8 support_promisc_filter[0x1]; 9537 u8 support_promisc_multicast_filter[0x1]; 9538 u8 reserved_0[0x2]; 9539 u8 log_working_buffer_size[0x3]; 9540 u8 log_pkey_table_size[0x4]; 9541 u8 reserved_1[0x3]; 9542 u8 num_ports[0x1]; 9543 9544 u8 reserved_2[0x2]; 9545 u8 log_max_ring_size[0x6]; 9546 u8 reserved_3[0x18]; 9547 9548 u8 lkey[0x20]; 9549 9550 u8 cqe_format[0x4]; 9551 u8 reserved_4[0x1c]; 9552 9553 u8 node_guid[0x40]; 9554 9555 u8 reserved_5[0x740]; 9556 9557 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 9558 9559 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 9560 }; 9561 9562 struct mlx5_ifc_vlan_layout_bits { 9563 u8 reserved_0[0x14]; 9564 u8 vlan[0xc]; 9565 9566 u8 reserved_1[0x20]; 9567 }; 9568 9569 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9570 u8 reserved_0[0x20]; 9571 9572 u8 mkey[0x20]; 9573 9574 u8 addressh_63_32[0x20]; 9575 9576 u8 addressl_31_0[0x20]; 9577 }; 9578 9579 struct mlx5_ifc_ud_adrs_vector_bits { 9580 u8 dc_key[0x40]; 9581 9582 u8 ext[0x1]; 9583 u8 reserved_0[0x7]; 9584 u8 destination_qp_dct[0x18]; 9585 9586 u8 static_rate[0x4]; 9587 u8 sl_eth_prio[0x4]; 9588 u8 fl[0x1]; 9589 u8 mlid[0x7]; 9590 u8 rlid_udp_sport[0x10]; 9591 9592 u8 reserved_1[0x20]; 9593 9594 u8 rmac_47_16[0x20]; 9595 9596 u8 rmac_15_0[0x10]; 9597 u8 tclass[0x8]; 9598 u8 hop_limit[0x8]; 9599 9600 u8 reserved_2[0x1]; 9601 u8 grh[0x1]; 9602 u8 reserved_3[0x2]; 9603 u8 src_addr_index[0x8]; 9604 u8 flow_label[0x14]; 9605 9606 u8 rgid_rip[16][0x8]; 9607 }; 9608 9609 struct mlx5_ifc_port_module_event_bits { 9610 u8 reserved_0[0x8]; 9611 u8 module[0x8]; 9612 u8 reserved_1[0xc]; 9613 u8 module_status[0x4]; 9614 9615 u8 reserved_2[0x14]; 9616 u8 error_type[0x4]; 9617 u8 reserved_3[0x8]; 9618 9619 u8 reserved_4[0xa0]; 9620 }; 9621 9622 struct mlx5_ifc_icmd_control_bits { 9623 u8 opcode[0x10]; 9624 u8 status[0x8]; 9625 u8 reserved_0[0x7]; 9626 u8 busy[0x1]; 9627 }; 9628 9629 struct mlx5_ifc_eqe_bits { 9630 u8 reserved_0[0x8]; 9631 u8 event_type[0x8]; 9632 u8 reserved_1[0x8]; 9633 u8 event_sub_type[0x8]; 9634 9635 u8 reserved_2[0xe0]; 9636 9637 union mlx5_ifc_event_auto_bits event_data; 9638 9639 u8 reserved_3[0x10]; 9640 u8 signature[0x8]; 9641 u8 reserved_4[0x7]; 9642 u8 owner[0x1]; 9643 }; 9644 9645 enum { 9646 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9647 }; 9648 9649 struct mlx5_ifc_cmd_queue_entry_bits { 9650 u8 type[0x8]; 9651 u8 reserved_0[0x18]; 9652 9653 u8 input_length[0x20]; 9654 9655 u8 input_mailbox_pointer_63_32[0x20]; 9656 9657 u8 input_mailbox_pointer_31_9[0x17]; 9658 u8 reserved_1[0x9]; 9659 9660 u8 command_input_inline_data[16][0x8]; 9661 9662 u8 command_output_inline_data[16][0x8]; 9663 9664 u8 output_mailbox_pointer_63_32[0x20]; 9665 9666 u8 output_mailbox_pointer_31_9[0x17]; 9667 u8 reserved_2[0x9]; 9668 9669 u8 output_length[0x20]; 9670 9671 u8 token[0x8]; 9672 u8 signature[0x8]; 9673 u8 reserved_3[0x8]; 9674 u8 status[0x7]; 9675 u8 ownership[0x1]; 9676 }; 9677 9678 struct mlx5_ifc_cmd_out_bits { 9679 u8 status[0x8]; 9680 u8 reserved_0[0x18]; 9681 9682 u8 syndrome[0x20]; 9683 9684 u8 command_output[0x20]; 9685 }; 9686 9687 struct mlx5_ifc_cmd_in_bits { 9688 u8 opcode[0x10]; 9689 u8 reserved_0[0x10]; 9690 9691 u8 reserved_1[0x10]; 9692 u8 op_mod[0x10]; 9693 9694 u8 command[0][0x20]; 9695 }; 9696 9697 struct mlx5_ifc_cmd_if_box_bits { 9698 u8 mailbox_data[512][0x8]; 9699 9700 u8 reserved_0[0x180]; 9701 9702 u8 next_pointer_63_32[0x20]; 9703 9704 u8 next_pointer_31_10[0x16]; 9705 u8 reserved_1[0xa]; 9706 9707 u8 block_number[0x20]; 9708 9709 u8 reserved_2[0x8]; 9710 u8 token[0x8]; 9711 u8 ctrl_signature[0x8]; 9712 u8 signature[0x8]; 9713 }; 9714 9715 struct mlx5_ifc_mtt_bits { 9716 u8 ptag_63_32[0x20]; 9717 9718 u8 ptag_31_8[0x18]; 9719 u8 reserved_0[0x6]; 9720 u8 wr_en[0x1]; 9721 u8 rd_en[0x1]; 9722 }; 9723 9724 /* Vendor Specific Capabilities, VSC */ 9725 enum { 9726 MLX5_VSC_DOMAIN_ICMD = 0x1, 9727 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 9728 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 9729 }; 9730 9731 struct mlx5_ifc_vendor_specific_cap_bits { 9732 u8 type[0x8]; 9733 u8 length[0x8]; 9734 u8 next_pointer[0x8]; 9735 u8 capability_id[0x8]; 9736 9737 u8 status[0x3]; 9738 u8 reserved_0[0xd]; 9739 u8 space[0x10]; 9740 9741 u8 counter[0x20]; 9742 9743 u8 semaphore[0x20]; 9744 9745 u8 flag[0x1]; 9746 u8 reserved_1[0x1]; 9747 u8 address[0x1e]; 9748 9749 u8 data[0x20]; 9750 }; 9751 9752 enum { 9753 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9754 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9755 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9756 }; 9757 9758 enum { 9759 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9760 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9761 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9762 }; 9763 9764 enum { 9765 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 9766 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 9767 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 9768 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 9769 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 9770 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 9771 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 9772 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 9773 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 9774 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 9775 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 9776 }; 9777 9778 struct mlx5_ifc_initial_seg_bits { 9779 u8 fw_rev_minor[0x10]; 9780 u8 fw_rev_major[0x10]; 9781 9782 u8 cmd_interface_rev[0x10]; 9783 u8 fw_rev_subminor[0x10]; 9784 9785 u8 reserved_0[0x40]; 9786 9787 u8 cmdq_phy_addr_63_32[0x20]; 9788 9789 u8 cmdq_phy_addr_31_12[0x14]; 9790 u8 reserved_1[0x2]; 9791 u8 nic_interface[0x2]; 9792 u8 log_cmdq_size[0x4]; 9793 u8 log_cmdq_stride[0x4]; 9794 9795 u8 command_doorbell_vector[0x20]; 9796 9797 u8 reserved_2[0xf00]; 9798 9799 u8 initializing[0x1]; 9800 u8 reserved_3[0x4]; 9801 u8 nic_interface_supported[0x3]; 9802 u8 reserved_4[0x18]; 9803 9804 struct mlx5_ifc_health_buffer_bits health_buffer; 9805 9806 u8 no_dram_nic_offset[0x20]; 9807 9808 u8 reserved_5[0x6de0]; 9809 9810 u8 internal_timer_h[0x20]; 9811 9812 u8 internal_timer_l[0x20]; 9813 9814 u8 reserved_6[0x20]; 9815 9816 u8 reserved_7[0x1f]; 9817 u8 clear_int[0x1]; 9818 9819 u8 health_syndrome[0x8]; 9820 u8 health_counter[0x18]; 9821 9822 u8 reserved_8[0x17fc0]; 9823 }; 9824 9825 union mlx5_ifc_icmd_interface_document_bits { 9826 struct mlx5_ifc_fw_version_bits fw_version; 9827 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 9828 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 9829 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 9830 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 9831 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 9832 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 9833 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 9834 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 9835 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 9836 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 9837 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 9838 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 9839 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 9840 u8 reserved_0[0x42c0]; 9841 }; 9842 9843 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 9844 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9845 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9846 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9847 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9848 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9849 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 9850 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9851 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9852 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 9853 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 9854 u8 reserved_0[0x7c0]; 9855 }; 9856 9857 struct mlx5_ifc_ppcnt_reg_bits { 9858 u8 swid[0x8]; 9859 u8 local_port[0x8]; 9860 u8 pnat[0x2]; 9861 u8 reserved_0[0x8]; 9862 u8 grp[0x6]; 9863 9864 u8 clr[0x1]; 9865 u8 reserved_1[0x1c]; 9866 u8 prio_tc[0x3]; 9867 9868 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9869 }; 9870 9871 struct mlx5_ifc_pcie_lanes_counters_bits { 9872 u8 life_time_counter_high[0x20]; 9873 9874 u8 life_time_counter_low[0x20]; 9875 9876 u8 error_counter_lane0[0x20]; 9877 9878 u8 error_counter_lane1[0x20]; 9879 9880 u8 error_counter_lane2[0x20]; 9881 9882 u8 error_counter_lane3[0x20]; 9883 9884 u8 error_counter_lane4[0x20]; 9885 9886 u8 error_counter_lane5[0x20]; 9887 9888 u8 error_counter_lane6[0x20]; 9889 9890 u8 error_counter_lane7[0x20]; 9891 9892 u8 error_counter_lane8[0x20]; 9893 9894 u8 error_counter_lane9[0x20]; 9895 9896 u8 error_counter_lane10[0x20]; 9897 9898 u8 error_counter_lane11[0x20]; 9899 9900 u8 error_counter_lane12[0x20]; 9901 9902 u8 error_counter_lane13[0x20]; 9903 9904 u8 error_counter_lane14[0x20]; 9905 9906 u8 error_counter_lane15[0x20]; 9907 9908 u8 reserved_at_240[0x580]; 9909 }; 9910 9911 struct mlx5_ifc_pcie_lanes_counters_ext_bits { 9912 u8 reserved_at_0[0x40]; 9913 9914 u8 error_counter_lane0[0x20]; 9915 9916 u8 error_counter_lane1[0x20]; 9917 9918 u8 error_counter_lane2[0x20]; 9919 9920 u8 error_counter_lane3[0x20]; 9921 9922 u8 error_counter_lane4[0x20]; 9923 9924 u8 error_counter_lane5[0x20]; 9925 9926 u8 error_counter_lane6[0x20]; 9927 9928 u8 error_counter_lane7[0x20]; 9929 9930 u8 error_counter_lane8[0x20]; 9931 9932 u8 error_counter_lane9[0x20]; 9933 9934 u8 error_counter_lane10[0x20]; 9935 9936 u8 error_counter_lane11[0x20]; 9937 9938 u8 error_counter_lane12[0x20]; 9939 9940 u8 error_counter_lane13[0x20]; 9941 9942 u8 error_counter_lane14[0x20]; 9943 9944 u8 error_counter_lane15[0x20]; 9945 9946 u8 reserved_at_240[0x580]; 9947 }; 9948 9949 struct mlx5_ifc_pcie_perf_counters_bits { 9950 u8 life_time_counter_high[0x20]; 9951 9952 u8 life_time_counter_low[0x20]; 9953 9954 u8 rx_errors[0x20]; 9955 9956 u8 tx_errors[0x20]; 9957 9958 u8 l0_to_recovery_eieos[0x20]; 9959 9960 u8 l0_to_recovery_ts[0x20]; 9961 9962 u8 l0_to_recovery_framing[0x20]; 9963 9964 u8 l0_to_recovery_retrain[0x20]; 9965 9966 u8 crc_error_dllp[0x20]; 9967 9968 u8 crc_error_tlp[0x20]; 9969 9970 u8 tx_overflow_buffer_pkt[0x40]; 9971 9972 u8 outbound_stalled_reads[0x20]; 9973 9974 u8 outbound_stalled_writes[0x20]; 9975 9976 u8 outbound_stalled_reads_events[0x20]; 9977 9978 u8 outbound_stalled_writes_events[0x20]; 9979 9980 u8 tx_overflow_buffer_marked_pkt[0x40]; 9981 9982 u8 reserved_at_240[0x580]; 9983 }; 9984 9985 struct mlx5_ifc_pcie_perf_counters_ext_bits { 9986 u8 reserved_at_0[0x40]; 9987 9988 u8 rx_errors[0x20]; 9989 9990 u8 tx_errors[0x20]; 9991 9992 u8 reserved_at_80[0xc0]; 9993 9994 u8 tx_overflow_buffer_pkt[0x40]; 9995 9996 u8 outbound_stalled_reads[0x20]; 9997 9998 u8 outbound_stalled_writes[0x20]; 9999 10000 u8 outbound_stalled_reads_events[0x20]; 10001 10002 u8 outbound_stalled_writes_events[0x20]; 10003 10004 u8 tx_overflow_buffer_marked_pkt[0x40]; 10005 10006 u8 reserved_at_240[0x580]; 10007 }; 10008 10009 struct mlx5_ifc_pcie_timers_states_bits { 10010 u8 life_time_counter_high[0x20]; 10011 10012 u8 life_time_counter_low[0x20]; 10013 10014 u8 time_to_boot_image_start[0x20]; 10015 10016 u8 time_to_link_image[0x20]; 10017 10018 u8 calibration_time[0x20]; 10019 10020 u8 time_to_first_perst[0x20]; 10021 10022 u8 time_to_detect_state[0x20]; 10023 10024 u8 time_to_l0[0x20]; 10025 10026 u8 time_to_crs_en[0x20]; 10027 10028 u8 time_to_plastic_image_start[0x20]; 10029 10030 u8 time_to_iron_image_start[0x20]; 10031 10032 u8 perst_handler[0x20]; 10033 10034 u8 times_in_l1[0x20]; 10035 10036 u8 times_in_l23[0x20]; 10037 10038 u8 dl_down[0x20]; 10039 10040 u8 config_cycle1usec[0x20]; 10041 10042 u8 config_cycle2to7usec[0x20]; 10043 10044 u8 config_cycle8to15usec[0x20]; 10045 10046 u8 config_cycle16to63usec[0x20]; 10047 10048 u8 config_cycle64usec[0x20]; 10049 10050 u8 correctable_err_msg_sent[0x20]; 10051 10052 u8 non_fatal_err_msg_sent[0x20]; 10053 10054 u8 fatal_err_msg_sent[0x20]; 10055 10056 u8 reserved_at_2e0[0x4e0]; 10057 }; 10058 10059 struct mlx5_ifc_pcie_timers_states_ext_bits { 10060 u8 reserved_at_0[0x40]; 10061 10062 u8 time_to_boot_image_start[0x20]; 10063 10064 u8 time_to_link_image[0x20]; 10065 10066 u8 calibration_time[0x20]; 10067 10068 u8 time_to_first_perst[0x20]; 10069 10070 u8 time_to_detect_state[0x20]; 10071 10072 u8 time_to_l0[0x20]; 10073 10074 u8 time_to_crs_en[0x20]; 10075 10076 u8 time_to_plastic_image_start[0x20]; 10077 10078 u8 time_to_iron_image_start[0x20]; 10079 10080 u8 perst_handler[0x20]; 10081 10082 u8 times_in_l1[0x20]; 10083 10084 u8 times_in_l23[0x20]; 10085 10086 u8 dl_down[0x20]; 10087 10088 u8 config_cycle1usec[0x20]; 10089 10090 u8 config_cycle2to7usec[0x20]; 10091 10092 u8 config_cycle8to15usec[0x20]; 10093 10094 u8 config_cycle16to63usec[0x20]; 10095 10096 u8 config_cycle64usec[0x20]; 10097 10098 u8 correctable_err_msg_sent[0x20]; 10099 10100 u8 non_fatal_err_msg_sent[0x20]; 10101 10102 u8 fatal_err_msg_sent[0x20]; 10103 10104 u8 reserved_at_2e0[0x4e0]; 10105 }; 10106 10107 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits { 10108 struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters; 10109 struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters; 10110 struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states; 10111 u8 reserved_at_0[0x7c0]; 10112 }; 10113 10114 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits { 10115 struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext; 10116 struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext; 10117 struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext; 10118 u8 reserved_at_0[0x7c0]; 10119 }; 10120 10121 struct mlx5_ifc_mpcnt_reg_bits { 10122 u8 reserved_at_0[0x2]; 10123 u8 depth[0x6]; 10124 u8 pcie_index[0x8]; 10125 u8 node[0x8]; 10126 u8 reserved_at_18[0x2]; 10127 u8 grp[0x6]; 10128 10129 u8 clr[0x1]; 10130 u8 reserved_at_21[0x1f]; 10131 10132 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set; 10133 }; 10134 10135 struct mlx5_ifc_mpcnt_reg_ext_bits { 10136 u8 reserved_at_0[0x2]; 10137 u8 depth[0x6]; 10138 u8 pcie_index[0x8]; 10139 u8 node[0x8]; 10140 u8 reserved_at_18[0x2]; 10141 u8 grp[0x6]; 10142 10143 u8 clr[0x1]; 10144 u8 reserved_at_21[0x1f]; 10145 10146 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set; 10147 }; 10148 10149 enum { 10150 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050, 10151 MLX5_MPEIN_PWR_STATUS_INVALID = 0, 10152 MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1, 10153 MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2, 10154 }; 10155 10156 struct mlx5_ifc_mpein_reg_bits { 10157 u8 reserved_at_0[0x2]; 10158 u8 depth[0x6]; 10159 u8 pcie_index[0x8]; 10160 u8 node[0x8]; 10161 u8 reserved_at_18[0x8]; 10162 10163 u8 capability_mask[0x20]; 10164 10165 u8 reserved_at_40[0x8]; 10166 u8 link_width_enabled[0x8]; 10167 u8 link_speed_enabled[0x10]; 10168 10169 u8 lane0_physical_position[0x8]; 10170 u8 link_width_active[0x8]; 10171 u8 link_speed_active[0x10]; 10172 10173 u8 num_of_pfs[0x10]; 10174 u8 num_of_vfs[0x10]; 10175 10176 u8 bdf0[0x10]; 10177 u8 reserved_at_b0[0x10]; 10178 10179 u8 max_read_request_size[0x4]; 10180 u8 max_payload_size[0x4]; 10181 u8 reserved_at_c8[0x5]; 10182 u8 pwr_status[0x3]; 10183 u8 port_type[0x4]; 10184 u8 reserved_at_d4[0xb]; 10185 u8 lane_reversal[0x1]; 10186 10187 u8 reserved_at_e0[0x14]; 10188 u8 pci_power[0xc]; 10189 10190 u8 reserved_at_100[0x20]; 10191 10192 u8 device_status[0x10]; 10193 u8 port_state[0x8]; 10194 u8 reserved_at_138[0x8]; 10195 10196 u8 reserved_at_140[0x10]; 10197 u8 receiver_detect_result[0x10]; 10198 10199 u8 reserved_at_160[0x20]; 10200 }; 10201 10202 struct mlx5_ifc_mpein_reg_ext_bits { 10203 u8 reserved_at_0[0x2]; 10204 u8 depth[0x6]; 10205 u8 pcie_index[0x8]; 10206 u8 node[0x8]; 10207 u8 reserved_at_18[0x8]; 10208 10209 u8 reserved_at_20[0x20]; 10210 10211 u8 reserved_at_40[0x8]; 10212 u8 link_width_enabled[0x8]; 10213 u8 link_speed_enabled[0x10]; 10214 10215 u8 lane0_physical_position[0x8]; 10216 u8 link_width_active[0x8]; 10217 u8 link_speed_active[0x10]; 10218 10219 u8 num_of_pfs[0x10]; 10220 u8 num_of_vfs[0x10]; 10221 10222 u8 bdf0[0x10]; 10223 u8 reserved_at_b0[0x10]; 10224 10225 u8 max_read_request_size[0x4]; 10226 u8 max_payload_size[0x4]; 10227 u8 reserved_at_c8[0x5]; 10228 u8 pwr_status[0x3]; 10229 u8 port_type[0x4]; 10230 u8 reserved_at_d4[0xb]; 10231 u8 lane_reversal[0x1]; 10232 }; 10233 10234 struct mlx5_ifc_mcqi_cap_bits { 10235 u8 supported_info_bitmask[0x20]; 10236 10237 u8 component_size[0x20]; 10238 10239 u8 max_component_size[0x20]; 10240 10241 u8 log_mcda_word_size[0x4]; 10242 u8 reserved_at_64[0xc]; 10243 u8 mcda_max_write_size[0x10]; 10244 10245 u8 rd_en[0x1]; 10246 u8 reserved_at_81[0x1]; 10247 u8 match_chip_id[0x1]; 10248 u8 match_psid[0x1]; 10249 u8 check_user_timestamp[0x1]; 10250 u8 match_base_guid_mac[0x1]; 10251 u8 reserved_at_86[0x1a]; 10252 }; 10253 10254 struct mlx5_ifc_mcqi_reg_bits { 10255 u8 read_pending_component[0x1]; 10256 u8 reserved_at_1[0xf]; 10257 u8 component_index[0x10]; 10258 10259 u8 reserved_at_20[0x20]; 10260 10261 u8 reserved_at_40[0x1b]; 10262 u8 info_type[0x5]; 10263 10264 u8 info_size[0x20]; 10265 10266 u8 offset[0x20]; 10267 10268 u8 reserved_at_a0[0x10]; 10269 u8 data_size[0x10]; 10270 10271 u8 data[0][0x20]; 10272 }; 10273 10274 struct mlx5_ifc_mcc_reg_bits { 10275 u8 reserved_at_0[0x4]; 10276 u8 time_elapsed_since_last_cmd[0xc]; 10277 u8 reserved_at_10[0x8]; 10278 u8 instruction[0x8]; 10279 10280 u8 reserved_at_20[0x10]; 10281 u8 component_index[0x10]; 10282 10283 u8 reserved_at_40[0x8]; 10284 u8 update_handle[0x18]; 10285 10286 u8 handle_owner_type[0x4]; 10287 u8 handle_owner_host_id[0x4]; 10288 u8 reserved_at_68[0x1]; 10289 u8 control_progress[0x7]; 10290 u8 error_code[0x8]; 10291 u8 reserved_at_78[0x4]; 10292 u8 control_state[0x4]; 10293 10294 u8 component_size[0x20]; 10295 10296 u8 reserved_at_a0[0x60]; 10297 }; 10298 10299 struct mlx5_ifc_mcda_reg_bits { 10300 u8 reserved_at_0[0x8]; 10301 u8 update_handle[0x18]; 10302 10303 u8 offset[0x20]; 10304 10305 u8 reserved_at_40[0x10]; 10306 u8 size[0x10]; 10307 10308 u8 reserved_at_60[0x20]; 10309 10310 u8 data[0][0x20]; 10311 }; 10312 10313 union mlx5_ifc_ports_control_registers_document_bits { 10314 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 10315 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10316 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10317 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10318 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10319 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10320 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10321 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10322 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10323 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 10324 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 10325 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10326 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 10327 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10328 struct mlx5_ifc_paos_reg_bits paos_reg; 10329 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 10330 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10331 struct mlx5_ifc_peir_reg_bits peir_reg; 10332 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10333 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10334 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 10335 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 10336 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 10337 struct mlx5_ifc_phrr_reg_bits phrr_reg; 10338 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10339 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10340 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10341 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10342 struct mlx5_ifc_plib_reg_bits plib_reg; 10343 struct mlx5_ifc_pll_status_data_bits pll_status_data; 10344 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10345 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10346 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10347 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10348 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10349 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10350 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10351 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10352 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10353 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10354 struct mlx5_ifc_ppll_reg_bits ppll_reg; 10355 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10356 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10357 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10358 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10359 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10360 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10361 struct mlx5_ifc_pude_reg_bits pude_reg; 10362 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10363 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10364 struct mlx5_ifc_slrp_reg_bits slrp_reg; 10365 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10366 u8 reserved_0[0x7880]; 10367 }; 10368 10369 union mlx5_ifc_debug_enhancements_document_bits { 10370 struct mlx5_ifc_health_buffer_bits health_buffer; 10371 u8 reserved_0[0x200]; 10372 }; 10373 10374 union mlx5_ifc_no_dram_nic_document_bits { 10375 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 10376 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 10377 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 10378 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 10379 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 10380 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 10381 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 10382 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 10383 u8 reserved_0[0x3160]; 10384 }; 10385 10386 union mlx5_ifc_uplink_pci_interface_document_bits { 10387 struct mlx5_ifc_initial_seg_bits initial_seg; 10388 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 10389 u8 reserved_0[0x20120]; 10390 }; 10391 10392 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10393 u8 e[0x1]; 10394 u8 reserved_at_01[0x0b]; 10395 u8 prio[0x04]; 10396 }; 10397 10398 struct mlx5_ifc_qpdpm_reg_bits { 10399 u8 reserved_at_0[0x8]; 10400 u8 local_port[0x8]; 10401 u8 reserved_at_10[0x10]; 10402 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10403 }; 10404 10405 struct mlx5_ifc_qpts_reg_bits { 10406 u8 reserved_at_0[0x8]; 10407 u8 local_port[0x8]; 10408 u8 reserved_at_10[0x2d]; 10409 u8 trust_state[0x3]; 10410 }; 10411 10412 struct mlx5_ifc_mfrl_reg_bits { 10413 u8 reserved_at_0[0x38]; 10414 u8 reset_level[0x8]; 10415 }; 10416 10417 #endif /* MLX5_IFC_H */ 10418