xref: /freebsd/sys/dev/mlx5/mlx5_ifc.h (revision 7ef62cebc2f965b0f640263e179276928885e33d)
1 /*-
2  * Copyright (c) 2013-2020, Mellanox Technologies.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #ifndef MLX5_IFC_H
29 #define MLX5_IFC_H
30 
31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h>
32 
33 enum {
34 	MLX5_EVENT_TYPE_NOTIFY_ANY				   = 0x0,
35 	MLX5_EVENT_TYPE_COMP                                       = 0x0,
36 	MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
37 	MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
38 	MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
39 	MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
40 	MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
41 	MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
42 	MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
43 	MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
44 	MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
45 	MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
46 	MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
47 	MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
48 	MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
49 	MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
50 	MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
51 	MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
52 	MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
53 	MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
54 	MLX5_EVENT_TYPE_TEMP_WARN_EVENT                            = 0x17,
55 	MLX5_EVENT_TYPE_XRQ_ERROR				   = 0x18,
56 	MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
57 	MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
58 	MLX5_EVENT_TYPE_CODING_PPS_EVENT                           = 0x25,
59 	MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT          = 0x22,
60 	MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
61 	MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
62 	MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
63 	MLX5_EVENT_TYPE_CMD                                        = 0xa,
64 	MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
65 	MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd,
66 	MLX5_EVENT_TYPE_FPGA_ERROR                                 = 0x20,
67 	MLX5_EVENT_TYPE_FPGA_QP_ERROR                              = 0x21,
68 	MLX5_EVENT_TYPE_CODING_GENERAL_OBJ_EVENT                   = 0x27,
69 };
70 
71 enum {
72 	MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
73 	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
74 	MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
75 	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
76 	MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
77 };
78 
79 enum {
80 	MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
81 };
82 
83 enum {
84 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
85 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
86 };
87 
88 enum {
89 	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
90 	MLX5_OBJ_TYPE_MKEY = 0xff01,
91 	MLX5_OBJ_TYPE_QP = 0xff02,
92 	MLX5_OBJ_TYPE_PSV = 0xff03,
93 	MLX5_OBJ_TYPE_RMP = 0xff04,
94 	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
95 	MLX5_OBJ_TYPE_RQ = 0xff06,
96 	MLX5_OBJ_TYPE_SQ = 0xff07,
97 	MLX5_OBJ_TYPE_TIR = 0xff08,
98 	MLX5_OBJ_TYPE_TIS = 0xff09,
99 	MLX5_OBJ_TYPE_DCT = 0xff0a,
100 	MLX5_OBJ_TYPE_XRQ = 0xff0b,
101 	MLX5_OBJ_TYPE_RQT = 0xff0e,
102 	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
103 	MLX5_OBJ_TYPE_CQ = 0xff10,
104 };
105 
106 enum {
107 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
108 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
109 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
110 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
111 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
112 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
113 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
114 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
115 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
116 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
117 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
118 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
119 	MLX5_CMD_OP_QUERY_OTHER_HCA_CAP           = 0x10e,
120 	MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP          = 0x10f,
121 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
122 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
123 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
124 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
125 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
126 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
127 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
128 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
129 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
130 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
131 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
132 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
133 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
134 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
135 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
136 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
137 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
138 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
139 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
140 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
141 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
142 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
143 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
144 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
145 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
146 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
147 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
148 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
149 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
150 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
151 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
152 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
153 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
154 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
155 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
156 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
157 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
158 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
159 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
160 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
161 	MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
162 	MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
163 	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
164 	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
165 	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
166 	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
167 	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
168 	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
169 	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
170 	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
171 	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
172 
173 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
174 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
175 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
176 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
177 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
178 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
179 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
180 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
181 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
182 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
183 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
184 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
185 	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
186 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
187 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
188 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
189 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
190 	MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
191 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
192 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT     = 0x782,
193 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT    = 0x783,
194 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT      = 0x784,
195 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT     = 0x785,
196 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
197 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
198 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
199 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
200 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
201 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
202 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
203 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
204 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
205 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
206 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
207 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
208 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
209 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
210 	MLX5_CMD_OP_NOP                           = 0x80d,
211 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
212 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
213 	MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
214 	MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
215 	MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
216 	MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
217 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
218 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
219 	MLX5_CMD_OP_QUERY_DIAGNOSTIC_PARAMS       = 0x819,
220 	MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
221 	MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
222 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
223 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
224 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
225 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
226 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
227 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
228 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
229 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
230 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
231 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
232 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
233 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
234 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
235 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
236 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
237 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
238 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
239 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
240 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
241 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
242 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
243 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
244 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
245 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
246 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
247 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
248 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
249 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
250 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
251 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
252 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
253 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
254 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
255 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
256 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
257 	MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS       = 0x911,
258 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
259 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
260 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
261 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
262 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
263 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
264 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
265 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
266 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
267 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
268 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
269 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
270 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
271 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
272 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
273 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
274 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
275 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
276 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
277 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
278 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
279 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
280 	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
281 	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
282 	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
283 	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
284 	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
285 	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
286 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
287 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
288 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
289 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
290 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
291 	MLX5_CMD_OP_CREATE_GENERAL_OBJ            = 0xa00,
292 	MLX5_CMD_OP_MODIFY_GENERAL_OBJ            = 0xa01,
293 	MLX5_CMD_OP_QUERY_GENERAL_OBJ             = 0xa02,
294 	MLX5_CMD_OP_DESTROY_GENERAL_OBJ           = 0xa03,
295 	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
296 	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
297 	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
298 	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
299 };
300 
301 /* Valid range for general commands that don't work over an object */
302 enum {
303 	MLX5_CMD_OP_GENERAL_START = 0xb00,
304 	MLX5_CMD_OP_GENERAL_END = 0xd00,
305 };
306 
307 enum {
308 	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
309 	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
310 	MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
311 	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
312 	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
313 	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
314 	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
315 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
316 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
317 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
318 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
319 	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
320 };
321 
322 enum {
323 	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
324 };
325 
326 enum {
327 	MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc,
328 };
329 
330 enum {
331 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
332 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
333 };
334 
335 enum {
336 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
337 };
338 
339 struct mlx5_ifc_flow_table_fields_supported_bits {
340 	u8         outer_dmac[0x1];
341 	u8         outer_smac[0x1];
342 	u8         outer_ether_type[0x1];
343 	u8         outer_ip_version[0x1];
344 	u8         outer_first_prio[0x1];
345 	u8         outer_first_cfi[0x1];
346 	u8         outer_first_vid[0x1];
347 	u8         reserved_1[0x1];
348 	u8         outer_second_prio[0x1];
349 	u8         outer_second_cfi[0x1];
350 	u8         outer_second_vid[0x1];
351 	u8         outer_ipv6_flow_label[0x1];
352 	u8         outer_sip[0x1];
353 	u8         outer_dip[0x1];
354 	u8         outer_frag[0x1];
355 	u8         outer_ip_protocol[0x1];
356 	u8         outer_ip_ecn[0x1];
357 	u8         outer_ip_dscp[0x1];
358 	u8         outer_udp_sport[0x1];
359 	u8         outer_udp_dport[0x1];
360 	u8         outer_tcp_sport[0x1];
361 	u8         outer_tcp_dport[0x1];
362 	u8         outer_tcp_flags[0x1];
363 	u8         outer_gre_protocol[0x1];
364 	u8         outer_gre_key[0x1];
365 	u8         outer_vxlan_vni[0x1];
366 	u8         outer_geneve_vni[0x1];
367 	u8         outer_geneve_oam[0x1];
368 	u8         outer_geneve_protocol_type[0x1];
369 	u8         outer_geneve_opt_len[0x1];
370 	u8         reserved_2[0x1];
371 	u8         source_eswitch_port[0x1];
372 
373 	u8         inner_dmac[0x1];
374 	u8         inner_smac[0x1];
375 	u8         inner_ether_type[0x1];
376 	u8         inner_ip_version[0x1];
377 	u8         inner_first_prio[0x1];
378 	u8         inner_first_cfi[0x1];
379 	u8         inner_first_vid[0x1];
380 	u8         reserved_4[0x1];
381 	u8         inner_second_prio[0x1];
382 	u8         inner_second_cfi[0x1];
383 	u8         inner_second_vid[0x1];
384 	u8         inner_ipv6_flow_label[0x1];
385 	u8         inner_sip[0x1];
386 	u8         inner_dip[0x1];
387 	u8         inner_frag[0x1];
388 	u8         inner_ip_protocol[0x1];
389 	u8         inner_ip_ecn[0x1];
390 	u8         inner_ip_dscp[0x1];
391 	u8         inner_udp_sport[0x1];
392 	u8         inner_udp_dport[0x1];
393 	u8         inner_tcp_sport[0x1];
394 	u8         inner_tcp_dport[0x1];
395 	u8         inner_tcp_flags[0x1];
396 	u8         reserved_5[0x9];
397 
398 	u8         reserved_6[0x1a];
399 	u8         bth_dst_qp[0x1];
400 	u8         reserved_7[0x4];
401 	u8         source_sqn[0x1];
402 
403 	u8         reserved_8[0x20];
404 };
405 
406 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
407 	u8         ingress_general_high[0x20];
408 
409 	u8         ingress_general_low[0x20];
410 
411 	u8         ingress_policy_engine_high[0x20];
412 
413 	u8         ingress_policy_engine_low[0x20];
414 
415 	u8         ingress_vlan_membership_high[0x20];
416 
417 	u8         ingress_vlan_membership_low[0x20];
418 
419 	u8         ingress_tag_frame_type_high[0x20];
420 
421 	u8         ingress_tag_frame_type_low[0x20];
422 
423 	u8         egress_vlan_membership_high[0x20];
424 
425 	u8         egress_vlan_membership_low[0x20];
426 
427 	u8         loopback_filter_high[0x20];
428 
429 	u8         loopback_filter_low[0x20];
430 
431 	u8         egress_general_high[0x20];
432 
433 	u8         egress_general_low[0x20];
434 
435 	u8         reserved_at_1c0[0x40];
436 
437 	u8         egress_hoq_high[0x20];
438 
439 	u8         egress_hoq_low[0x20];
440 
441 	u8         port_isolation_high[0x20];
442 
443 	u8         port_isolation_low[0x20];
444 
445 	u8         egress_policy_engine_high[0x20];
446 
447 	u8         egress_policy_engine_low[0x20];
448 
449 	u8         ingress_tx_link_down_high[0x20];
450 
451 	u8         ingress_tx_link_down_low[0x20];
452 
453 	u8         egress_stp_filter_high[0x20];
454 
455 	u8         egress_stp_filter_low[0x20];
456 
457 	u8         egress_hoq_stall_high[0x20];
458 
459 	u8         egress_hoq_stall_low[0x20];
460 
461 	u8         reserved_at_340[0x440];
462 };
463 struct mlx5_ifc_flow_table_prop_layout_bits {
464 	u8         ft_support[0x1];
465 	u8         flow_tag[0x1];
466 	u8         flow_counter[0x1];
467 	u8         flow_modify_en[0x1];
468 	u8         modify_root[0x1];
469 	u8         identified_miss_table[0x1];
470 	u8         flow_table_modify[0x1];
471 	u8         encap[0x1];
472 	u8         decap[0x1];
473 	u8         reset_root_to_default[0x1];
474 	u8         reserved_at_a[0x16];
475 
476 	u8         reserved_at_20[0x2];
477 	u8         log_max_ft_size[0x6];
478 	u8         reserved_at_28[0x10];
479 	u8         max_ft_level[0x8];
480 
481 	u8         reserved_at_40[0x20];
482 
483 	u8         reserved_at_60[0x18];
484 	u8         log_max_ft_num[0x8];
485 
486 	u8         reserved_at_80[0x10];
487 	u8         log_max_flow_counter[0x8];
488 	u8         log_max_destination[0x8];
489 
490 	u8         reserved_at_a0[0x18];
491 	u8         log_max_flow[0x8];
492 
493 	u8         reserved_at_c0[0x40];
494 
495 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
496 
497 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
498 };
499 
500 struct mlx5_ifc_odp_per_transport_service_cap_bits {
501 	u8         send[0x1];
502 	u8         receive[0x1];
503 	u8         write[0x1];
504 	u8         read[0x1];
505 	u8         atomic[0x1];
506 	u8         srq_receive[0x1];
507 	u8         reserved_0[0x1a];
508 };
509 
510 struct mlx5_ifc_flow_counter_list_bits {
511 	u8         reserved_0[0x10];
512 	u8         flow_counter_id[0x10];
513 
514 	u8         reserved_1[0x20];
515 };
516 
517 enum {
518 	MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
519 	MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
520 	MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
521 	MLX5_FLOW_CONTEXT_DEST_TYPE_QP                       = 0x3,
522 };
523 
524 struct mlx5_ifc_dest_format_struct_bits {
525 	u8         destination_type[0x8];
526 	u8         destination_id[0x18];
527 
528 	u8         reserved_0[0x20];
529 };
530 
531 struct mlx5_ifc_ipv4_layout_bits {
532 	u8         reserved_at_0[0x60];
533 
534 	u8         ipv4[0x20];
535 };
536 
537 struct mlx5_ifc_ipv6_layout_bits {
538 	u8         ipv6[16][0x8];
539 };
540 
541 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
542 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
543 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
544 	u8         reserved_at_0[0x80];
545 };
546 
547 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
548 	u8         smac_47_16[0x20];
549 
550 	u8         smac_15_0[0x10];
551 	u8         ethertype[0x10];
552 
553 	u8         dmac_47_16[0x20];
554 
555 	u8         dmac_15_0[0x10];
556 	u8         first_prio[0x3];
557 	u8         first_cfi[0x1];
558 	u8         first_vid[0xc];
559 
560 	u8         ip_protocol[0x8];
561 	u8         ip_dscp[0x6];
562 	u8         ip_ecn[0x2];
563 	u8         cvlan_tag[0x1];
564 	u8         svlan_tag[0x1];
565 	u8         frag[0x1];
566 	u8         ip_version[0x4];
567 	u8         tcp_flags[0x9];
568 
569 	u8         tcp_sport[0x10];
570 	u8         tcp_dport[0x10];
571 
572 	u8         reserved_2[0x20];
573 
574 	u8         udp_sport[0x10];
575 	u8         udp_dport[0x10];
576 
577 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
578 
579 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
580 };
581 
582 struct mlx5_ifc_fte_match_set_misc_bits {
583 	u8         reserved_0[0x8];
584 	u8         source_sqn[0x18];
585 
586 	u8         reserved_1[0x10];
587 	u8         source_port[0x10];
588 
589 	u8         outer_second_prio[0x3];
590 	u8         outer_second_cfi[0x1];
591 	u8         outer_second_vid[0xc];
592 	u8         inner_second_prio[0x3];
593 	u8         inner_second_cfi[0x1];
594 	u8         inner_second_vid[0xc];
595 
596 	u8         outer_second_vlan_tag[0x1];
597 	u8         inner_second_vlan_tag[0x1];
598 	u8         reserved_2[0xe];
599 	u8         gre_protocol[0x10];
600 
601 	u8         gre_key_h[0x18];
602 	u8         gre_key_l[0x8];
603 
604 	u8         vxlan_vni[0x18];
605 	u8         reserved_3[0x8];
606 
607 	u8         geneve_vni[0x18];
608 	u8         reserved4[0x7];
609 	u8         geneve_oam[0x1];
610 
611 	u8         reserved_5[0xc];
612 	u8         outer_ipv6_flow_label[0x14];
613 
614 	u8         reserved_6[0xc];
615 	u8         inner_ipv6_flow_label[0x14];
616 
617 	u8         reserved_7[0xa];
618 	u8         geneve_opt_len[0x6];
619 	u8         geneve_protocol_type[0x10];
620 
621 	u8         reserved_8[0x8];
622 	u8         bth_dst_qp[0x18];
623 
624 	u8         reserved_9[0xa0];
625 };
626 
627 struct mlx5_ifc_cmd_pas_bits {
628 	u8         pa_h[0x20];
629 
630 	u8         pa_l[0x14];
631 	u8         reserved_0[0xc];
632 };
633 
634 struct mlx5_ifc_uint64_bits {
635 	u8         hi[0x20];
636 
637 	u8         lo[0x20];
638 };
639 
640 struct mlx5_ifc_application_prio_entry_bits {
641 	u8         reserved_0[0x8];
642 	u8         priority[0x3];
643 	u8         reserved_1[0x2];
644 	u8         sel[0x3];
645 	u8         protocol_id[0x10];
646 };
647 
648 struct mlx5_ifc_nodnic_ring_doorbell_bits {
649 	u8         reserved_0[0x8];
650 	u8         ring_pi[0x10];
651 	u8         reserved_1[0x8];
652 };
653 
654 enum {
655 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
656 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
657 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
658 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
659 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
660 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
661 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
662 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
663 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
664 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
665 };
666 
667 struct mlx5_ifc_ads_bits {
668 	u8         fl[0x1];
669 	u8         free_ar[0x1];
670 	u8         reserved_0[0xe];
671 	u8         pkey_index[0x10];
672 
673 	u8         reserved_1[0x8];
674 	u8         grh[0x1];
675 	u8         mlid[0x7];
676 	u8         rlid[0x10];
677 
678 	u8         ack_timeout[0x5];
679 	u8         reserved_2[0x3];
680 	u8         src_addr_index[0x8];
681 	u8         log_rtm[0x4];
682 	u8         stat_rate[0x4];
683 	u8         hop_limit[0x8];
684 
685 	u8         reserved_3[0x4];
686 	u8         tclass[0x8];
687 	u8         flow_label[0x14];
688 
689 	u8         rgid_rip[16][0x8];
690 
691 	u8         reserved_4[0x4];
692 	u8         f_dscp[0x1];
693 	u8         f_ecn[0x1];
694 	u8         reserved_5[0x1];
695 	u8         f_eth_prio[0x1];
696 	u8         ecn[0x2];
697 	u8         dscp[0x6];
698 	u8         udp_sport[0x10];
699 
700 	u8         dei_cfi[0x1];
701 	u8         eth_prio[0x3];
702 	u8         sl[0x4];
703 	u8         port[0x8];
704 	u8         rmac_47_32[0x10];
705 
706 	u8         rmac_31_0[0x20];
707 };
708 
709 struct mlx5_ifc_diagnostic_counter_cap_bits {
710 	u8         sync[0x1];
711 	u8         reserved_0[0xf];
712 	u8         counter_id[0x10];
713 };
714 
715 struct mlx5_ifc_debug_cap_bits {
716 	u8         reserved_0[0x18];
717 	u8         log_max_samples[0x8];
718 
719 	u8         single[0x1];
720 	u8         repetitive[0x1];
721 	u8         health_mon_rx_activity[0x1];
722 	u8         reserved_1[0x15];
723 	u8         log_min_sample_period[0x8];
724 
725 	u8         reserved_2[0x1c0];
726 
727 	struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
728 };
729 
730 struct mlx5_ifc_qos_cap_bits {
731 	u8         packet_pacing[0x1];
732 	u8         esw_scheduling[0x1];
733 	u8         esw_bw_share[0x1];
734 	u8         esw_rate_limit[0x1];
735 	u8         hll[0x1];
736 	u8         packet_pacing_burst_bound[0x1];
737 	u8         packet_pacing_typical_size[0x1];
738 	u8         reserved_at_7[0x19];
739 
740 	u8 	   reserved_at_20[0xA];
741 	u8	   qos_remap_pp[0x1];
742 	u8         reserved_at_2b[0x15];
743 
744 	u8         packet_pacing_max_rate[0x20];
745 
746 	u8         packet_pacing_min_rate[0x20];
747 
748 	u8         reserved_at_80[0x10];
749 	u8         packet_pacing_rate_table_size[0x10];
750 
751 	u8         esw_element_type[0x10];
752 	u8         esw_tsar_type[0x10];
753 
754 	u8         reserved_at_c0[0x10];
755 	u8         max_qos_para_vport[0x10];
756 
757 	u8         max_tsar_bw_share[0x20];
758 
759 	u8         reserved_at_100[0x700];
760 };
761 
762 struct mlx5_ifc_snapshot_cap_bits {
763 	u8         reserved_0[0x1d];
764 	u8         suspend_qp_uc[0x1];
765 	u8         suspend_qp_ud[0x1];
766 	u8         suspend_qp_rc[0x1];
767 
768 	u8         reserved_1[0x1c];
769 	u8         restore_pd[0x1];
770 	u8         restore_uar[0x1];
771 	u8         restore_mkey[0x1];
772 	u8         restore_qp[0x1];
773 
774 	u8         reserved_2[0x1e];
775 	u8         named_mkey[0x1];
776 	u8         named_qp[0x1];
777 
778 	u8         reserved_3[0x7a0];
779 };
780 
781 struct mlx5_ifc_e_switch_cap_bits {
782 	u8         vport_svlan_strip[0x1];
783 	u8         vport_cvlan_strip[0x1];
784 	u8         vport_svlan_insert[0x1];
785 	u8         vport_cvlan_insert_if_not_exist[0x1];
786 	u8         vport_cvlan_insert_overwrite[0x1];
787 
788 	u8         reserved_0[0x19];
789 
790 	u8         nic_vport_node_guid_modify[0x1];
791 	u8         nic_vport_port_guid_modify[0x1];
792 
793 	u8         reserved_1[0x7e0];
794 };
795 
796 struct mlx5_ifc_flow_table_eswitch_cap_bits {
797 	u8         reserved_0[0x200];
798 
799 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
800 
801 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
802 
803 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
804 
805 	u8         reserved_1[0x7800];
806 };
807 
808 struct mlx5_ifc_flow_table_nic_cap_bits {
809 	u8         nic_rx_multi_path_tirs[0x1];
810 	u8         nic_rx_multi_path_tirs_fts[0x1];
811 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
812 	u8         reserved_at_3[0x1fd];
813 
814 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
815 
816 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
817 
818 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
819 
820 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
821 
822 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
823 
824 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
825 
826 	u8         reserved_1[0x7200];
827 };
828 
829 struct mlx5_ifc_pddr_module_info_bits {
830 	u8         cable_technology[0x8];
831 	u8         cable_breakout[0x8];
832 	u8         ext_ethernet_compliance_code[0x8];
833 	u8         ethernet_compliance_code[0x8];
834 
835 	u8         cable_type[0x4];
836 	u8         cable_vendor[0x4];
837 	u8         cable_length[0x8];
838 	u8         cable_identifier[0x8];
839 	u8         cable_power_class[0x8];
840 
841 	u8         reserved_at_40[0x8];
842 	u8         cable_rx_amp[0x8];
843 	u8         cable_rx_emphasis[0x8];
844 	u8         cable_tx_equalization[0x8];
845 
846 	u8         reserved_at_60[0x8];
847 	u8         cable_attenuation_12g[0x8];
848 	u8         cable_attenuation_7g[0x8];
849 	u8         cable_attenuation_5g[0x8];
850 
851 	u8         reserved_at_80[0x8];
852 	u8         rx_cdr_cap[0x4];
853 	u8         tx_cdr_cap[0x4];
854 	u8         reserved_at_90[0x4];
855 	u8         rx_cdr_state[0x4];
856 	u8         reserved_at_98[0x4];
857 	u8         tx_cdr_state[0x4];
858 
859 	u8         vendor_name[16][0x8];
860 
861 	u8         vendor_pn[16][0x8];
862 
863 	u8         vendor_rev[0x20];
864 
865 	u8         fw_version[0x20];
866 
867 	u8         vendor_sn[16][0x8];
868 
869 	u8         temperature[0x10];
870 	u8         voltage[0x10];
871 
872 	u8         rx_power_lane0[0x10];
873 	u8         rx_power_lane1[0x10];
874 
875 	u8         rx_power_lane2[0x10];
876 	u8         rx_power_lane3[0x10];
877 
878 	u8         reserved_at_2c0[0x40];
879 
880 	u8         tx_power_lane0[0x10];
881 	u8         tx_power_lane1[0x10];
882 
883 	u8         tx_power_lane2[0x10];
884 	u8         tx_power_lane3[0x10];
885 
886 	u8         reserved_at_340[0x40];
887 
888 	u8         tx_bias_lane0[0x10];
889 	u8         tx_bias_lane1[0x10];
890 
891 	u8         tx_bias_lane2[0x10];
892 	u8         tx_bias_lane3[0x10];
893 
894 	u8         reserved_at_3c0[0x40];
895 
896 	u8         temperature_high_th[0x10];
897 	u8         temperature_low_th[0x10];
898 
899 	u8         voltage_high_th[0x10];
900 	u8         voltage_low_th[0x10];
901 
902 	u8         rx_power_high_th[0x10];
903 	u8         rx_power_low_th[0x10];
904 
905 	u8         tx_power_high_th[0x10];
906 	u8         tx_power_low_th[0x10];
907 
908 	u8         tx_bias_high_th[0x10];
909 	u8         tx_bias_low_th[0x10];
910 
911 	u8         reserved_at_4a0[0x10];
912 	u8         wavelength[0x10];
913 
914 	u8         reserved_at_4c0[0x300];
915 };
916 
917 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
918 	u8         csum_cap[0x1];
919 	u8         vlan_cap[0x1];
920 	u8         lro_cap[0x1];
921 	u8         lro_psh_flag[0x1];
922 	u8         lro_time_stamp[0x1];
923 	u8         lro_max_msg_sz_mode[0x2];
924 	u8         wqe_vlan_insert[0x1];
925 	u8         self_lb_en_modifiable[0x1];
926 	u8         self_lb_mc[0x1];
927 	u8         self_lb_uc[0x1];
928 	u8         max_lso_cap[0x5];
929 	u8         multi_pkt_send_wqe[0x2];
930 	u8         wqe_inline_mode[0x2];
931 	u8         rss_ind_tbl_cap[0x4];
932 	u8	   reg_umr_sq[0x1];
933 	u8         scatter_fcs[0x1];
934 	u8	   enhanced_multi_pkt_send_wqe[0x1];
935 	u8         tunnel_lso_const_out_ip_id[0x1];
936 	u8         tunnel_lro_gre[0x1];
937 	u8         tunnel_lro_vxlan[0x1];
938 	u8         tunnel_statless_gre[0x1];
939 	u8         tunnel_stateless_vxlan[0x1];
940 
941 	u8         swp[0x1];
942 	u8         swp_csum[0x1];
943 	u8         swp_lso[0x1];
944 	u8         reserved_2[0x1b];
945 	u8         max_geneve_opt_len[0x1];
946 	u8         tunnel_stateless_geneve_rx[0x1];
947 
948 	u8         reserved_3[0x10];
949 	u8         lro_min_mss_size[0x10];
950 
951 	u8         reserved_4[0x120];
952 
953 	u8         lro_timer_supported_periods[4][0x20];
954 
955 	u8         reserved_5[0x600];
956 };
957 
958 enum {
959 	MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
960 	MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
961 	MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
962 };
963 
964 enum {
965 	MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
966 	MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
967 	MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
968 };
969 
970 struct mlx5_ifc_roce_cap_bits {
971 	u8         roce_apm[0x1];
972 	u8         rts2rts_primary_eth_prio[0x1];
973 	u8         roce_rx_allow_untagged[0x1];
974 	u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
975 	u8         reserved_at_4[0x1a];
976 	u8         qp_ts_format[0x2];
977 
978 	u8         reserved_1[0x60];
979 
980 	u8         reserved_2[0xc];
981 	u8         l3_type[0x4];
982 	u8         reserved_3[0x8];
983 	u8         roce_version[0x8];
984 
985 	u8         reserved_4[0x10];
986 	u8         r_roce_dest_udp_port[0x10];
987 
988 	u8         r_roce_max_src_udp_port[0x10];
989 	u8         r_roce_min_src_udp_port[0x10];
990 
991 	u8         reserved_5[0x10];
992 	u8         roce_address_table_size[0x10];
993 
994 	u8         reserved_6[0x700];
995 };
996 
997 struct mlx5_ifc_device_event_cap_bits {
998 	u8         user_affiliated_events[4][0x40];
999 
1000 	u8         user_unaffiliated_events[4][0x40];
1001 };
1002 
1003 enum {
1004 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
1005 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1006 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1007 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1008 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1009 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1010 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1011 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1012 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1013 };
1014 
1015 enum {
1016 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1017 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1018 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1019 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1020 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1021 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1022 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1023 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1024 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1025 };
1026 
1027 struct mlx5_ifc_atomic_caps_bits {
1028 	u8         reserved_0[0x40];
1029 
1030 	u8         atomic_req_8B_endianess_mode[0x2];
1031 	u8         reserved_1[0x4];
1032 	u8         supported_atomic_req_8B_endianess_mode_1[0x1];
1033 
1034 	u8         reserved_2[0x19];
1035 
1036 	u8         reserved_3[0x20];
1037 
1038 	u8         reserved_4[0x10];
1039 	u8         atomic_operations[0x10];
1040 
1041 	u8         reserved_5[0x10];
1042 	u8         atomic_size_qp[0x10];
1043 
1044 	u8         reserved_6[0x10];
1045 	u8         atomic_size_dc[0x10];
1046 
1047 	u8         reserved_7[0x720];
1048 };
1049 
1050 struct mlx5_ifc_odp_cap_bits {
1051 	u8         reserved_0[0x40];
1052 
1053 	u8         sig[0x1];
1054 	u8         reserved_1[0x1f];
1055 
1056 	u8         reserved_2[0x20];
1057 
1058 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1059 
1060 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1061 
1062 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1063 
1064 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1065 
1066 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1067 
1068 	u8         reserved_3[0x6e0];
1069 };
1070 
1071 enum {
1072 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1073 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1074 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1075 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1076 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1077 };
1078 
1079 enum {
1080 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1081 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1082 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1083 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1084 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1085 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1086 };
1087 
1088 enum {
1089 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1090 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1091 };
1092 
1093 enum {
1094 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1095 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1096 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1097 };
1098 
1099 enum {
1100 	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1101 	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1102 };
1103 
1104 enum {
1105 	MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1106 	MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1107 	MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1108 };
1109 
1110 enum {
1111 	MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1112 	MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1113 	MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1114 };
1115 
1116 struct mlx5_ifc_cmd_hca_cap_bits {
1117 	u8         reserved_0[0x80];
1118 
1119 	u8         log_max_srq_sz[0x8];
1120 	u8         log_max_qp_sz[0x8];
1121 	u8         event_cap[0x1];
1122 	u8         reserved_1[0xa];
1123 	u8         log_max_qp[0x5];
1124 
1125 	u8         reserved_2[0xb];
1126 	u8         log_max_srq[0x5];
1127 	u8         reserved_3[0x10];
1128 
1129 	u8         reserved_4[0x8];
1130 	u8         log_max_cq_sz[0x8];
1131 	u8         relaxed_ordering_write_umr[0x1];
1132 	u8         relaxed_ordering_read_umr[0x1];
1133 	u8         reserved_5[0x9];
1134 	u8         log_max_cq[0x5];
1135 
1136 	u8         log_max_eq_sz[0x8];
1137 	u8         relaxed_ordering_write[0x1];
1138 	u8         relaxed_ordering_read[0x1];
1139 	u8         log_max_mkey[0x6];
1140 	u8         reserved_7[0xb];
1141 	u8         fast_teardown[0x1];
1142 	u8         log_max_eq[0x4];
1143 
1144 	u8         max_indirection[0x8];
1145 	u8         reserved_8[0x1];
1146 	u8         log_max_mrw_sz[0x7];
1147 	u8	   force_teardown[0x1];
1148 	u8         reserved_9[0x1];
1149 	u8         log_max_bsf_list_size[0x6];
1150 	u8         reserved_10[0x2];
1151 	u8         log_max_klm_list_size[0x6];
1152 
1153 	u8         reserved_11[0xa];
1154 	u8         log_max_ra_req_dc[0x6];
1155 	u8         reserved_12[0xa];
1156 	u8         log_max_ra_res_dc[0x6];
1157 
1158 	u8         reserved_13[0xa];
1159 	u8         log_max_ra_req_qp[0x6];
1160 	u8         reserved_14[0xa];
1161 	u8         log_max_ra_res_qp[0x6];
1162 
1163 	u8         pad_cap[0x1];
1164 	u8         cc_query_allowed[0x1];
1165 	u8         cc_modify_allowed[0x1];
1166 	u8         start_pad[0x1];
1167 	u8         cache_line_128byte[0x1];
1168 	u8         reserved_at_165[0xa];
1169 	u8         qcam_reg[0x1];
1170 	u8         gid_table_size[0x10];
1171 
1172 	u8         out_of_seq_cnt[0x1];
1173 	u8         vport_counters[0x1];
1174 	u8         retransmission_q_counters[0x1];
1175 	u8         debug[0x1];
1176 	u8         modify_rq_counters_set_id[0x1];
1177 	u8         rq_delay_drop[0x1];
1178 	u8         max_qp_cnt[0xa];
1179 	u8         pkey_table_size[0x10];
1180 
1181 	u8         vport_group_manager[0x1];
1182 	u8         vhca_group_manager[0x1];
1183 	u8         ib_virt[0x1];
1184 	u8         eth_virt[0x1];
1185 	u8         reserved_17[0x1];
1186 	u8         ets[0x1];
1187 	u8         nic_flow_table[0x1];
1188 	u8         eswitch_flow_table[0x1];
1189 	u8         reserved_18[0x1];
1190 	u8         mcam_reg[0x1];
1191 	u8         pcam_reg[0x1];
1192 	u8         local_ca_ack_delay[0x5];
1193 	u8         port_module_event[0x1];
1194 	u8         reserved_19[0x5];
1195 	u8         port_type[0x2];
1196 	u8         num_ports[0x8];
1197 
1198 	u8         snapshot[0x1];
1199 	u8         reserved_20[0x2];
1200 	u8         log_max_msg[0x5];
1201 	u8         reserved_21[0x4];
1202 	u8         max_tc[0x4];
1203 	u8         temp_warn_event[0x1];
1204 	u8         dcbx[0x1];
1205 	u8         general_notification_event[0x1];
1206 	u8         reserved_at_1d3[0x2];
1207 	u8         fpga[0x1];
1208 	u8         rol_s[0x1];
1209 	u8         rol_g[0x1];
1210 	u8         reserved_23[0x1];
1211 	u8         wol_s[0x1];
1212 	u8         wol_g[0x1];
1213 	u8         wol_a[0x1];
1214 	u8         wol_b[0x1];
1215 	u8         wol_m[0x1];
1216 	u8         wol_u[0x1];
1217 	u8         wol_p[0x1];
1218 
1219 	u8         stat_rate_support[0x10];
1220 	u8         reserved_24[0xc];
1221 	u8         cqe_version[0x4];
1222 
1223 	u8         compact_address_vector[0x1];
1224 	u8         striding_rq[0x1];
1225 	u8         reserved_25[0x1];
1226 	u8         ipoib_enhanced_offloads[0x1];
1227 	u8         ipoib_ipoib_offloads[0x1];
1228 	u8         reserved_26[0x8];
1229 	u8         dc_connect_qp[0x1];
1230 	u8         dc_cnak_trace[0x1];
1231 	u8         drain_sigerr[0x1];
1232 	u8         cmdif_checksum[0x2];
1233 	u8         sigerr_cqe[0x1];
1234 	u8         reserved_27[0x1];
1235 	u8         wq_signature[0x1];
1236 	u8         sctr_data_cqe[0x1];
1237 	u8         reserved_28[0x1];
1238 	u8         sho[0x1];
1239 	u8         tph[0x1];
1240 	u8         rf[0x1];
1241 	u8         dct[0x1];
1242 	u8         qos[0x1];
1243 	u8         eth_net_offloads[0x1];
1244 	u8         roce[0x1];
1245 	u8         atomic[0x1];
1246 	u8         reserved_30[0x1];
1247 
1248 	u8         cq_oi[0x1];
1249 	u8         cq_resize[0x1];
1250 	u8         cq_moderation[0x1];
1251 	u8         cq_period_mode_modify[0x1];
1252 	u8         cq_invalidate[0x1];
1253 	u8         reserved_at_225[0x1];
1254 	u8         cq_eq_remap[0x1];
1255 	u8         pg[0x1];
1256 	u8         block_lb_mc[0x1];
1257 	u8         exponential_backoff[0x1];
1258 	u8         scqe_break_moderation[0x1];
1259 	u8         cq_period_start_from_cqe[0x1];
1260 	u8         cd[0x1];
1261 	u8         atm[0x1];
1262 	u8         apm[0x1];
1263 	u8	   imaicl[0x1];
1264 	u8         reserved_32[0x6];
1265 	u8         qkv[0x1];
1266 	u8         pkv[0x1];
1267 	u8	   set_deth_sqpn[0x1];
1268 	u8         reserved_33[0x3];
1269 	u8         xrc[0x1];
1270 	u8         ud[0x1];
1271 	u8         uc[0x1];
1272 	u8         rc[0x1];
1273 
1274 	u8         uar_4k[0x1];
1275 	u8         reserved_at_241[0x9];
1276 	u8         uar_sz[0x6];
1277 	u8         reserved_35[0x8];
1278 	u8         log_pg_sz[0x8];
1279 
1280 	u8         bf[0x1];
1281 	u8         driver_version[0x1];
1282 	u8         pad_tx_eth_packet[0x1];
1283 	u8         reserved_36[0x8];
1284 	u8         log_bf_reg_size[0x5];
1285 	u8         reserved_37[0x10];
1286 
1287 	u8         num_of_diagnostic_counters[0x10];
1288 	u8         max_wqe_sz_sq[0x10];
1289 
1290 	u8         reserved_38[0x10];
1291 	u8         max_wqe_sz_rq[0x10];
1292 
1293 	u8         reserved_39[0x10];
1294 	u8         max_wqe_sz_sq_dc[0x10];
1295 
1296 	u8         reserved_40[0x7];
1297 	u8         max_qp_mcg[0x19];
1298 
1299 	u8         reserved_41[0x18];
1300 	u8         log_max_mcg[0x8];
1301 
1302 	u8         reserved_42[0x3];
1303 	u8         log_max_transport_domain[0x5];
1304 	u8         reserved_43[0x3];
1305 	u8         log_max_pd[0x5];
1306 	u8         reserved_44[0xb];
1307 	u8         log_max_xrcd[0x5];
1308 
1309 	u8         nic_receive_steering_discard[0x1];
1310 	u8	   reserved_45[0x7];
1311 	u8         log_max_flow_counter_bulk[0x8];
1312 	u8         max_flow_counter[0x10];
1313 
1314 	u8         reserved_46[0x3];
1315 	u8         log_max_rq[0x5];
1316 	u8         reserved_47[0x3];
1317 	u8         log_max_sq[0x5];
1318 	u8         reserved_48[0x3];
1319 	u8         log_max_tir[0x5];
1320 	u8         reserved_49[0x3];
1321 	u8         log_max_tis[0x5];
1322 
1323 	u8         basic_cyclic_rcv_wqe[0x1];
1324 	u8         reserved_50[0x2];
1325 	u8         log_max_rmp[0x5];
1326 	u8         reserved_51[0x3];
1327 	u8         log_max_rqt[0x5];
1328 	u8         reserved_52[0x3];
1329 	u8         log_max_rqt_size[0x5];
1330 	u8         reserved_53[0x3];
1331 	u8         log_max_tis_per_sq[0x5];
1332 
1333 	u8         reserved_54[0x3];
1334 	u8         log_max_stride_sz_rq[0x5];
1335 	u8         reserved_55[0x3];
1336 	u8         log_min_stride_sz_rq[0x5];
1337 	u8         reserved_56[0x3];
1338 	u8         log_max_stride_sz_sq[0x5];
1339 	u8         reserved_57[0x3];
1340 	u8         log_min_stride_sz_sq[0x5];
1341 
1342 	u8         reserved_58[0x1b];
1343 	u8         log_max_wq_sz[0x5];
1344 
1345 	u8         nic_vport_change_event[0x1];
1346 	u8         disable_local_lb_uc[0x1];
1347 	u8         disable_local_lb_mc[0x1];
1348 	u8         reserved_59[0x8];
1349 	u8         log_max_vlan_list[0x5];
1350 	u8         reserved_60[0x3];
1351 	u8         log_max_current_mc_list[0x5];
1352 	u8         reserved_61[0x3];
1353 	u8         log_max_current_uc_list[0x5];
1354 
1355 	u8         general_obj_types[0x40];
1356 
1357 	u8         sq_ts_format[0x2];
1358 	u8         rq_ts_format[0x2];
1359 	u8         reserved_at_444[0x4];
1360 	u8         create_qp_start_hint[0x18];
1361 
1362 	u8         reserved_at_460[0x3];
1363 	u8         log_max_uctx[0x5];
1364 	u8         reserved_at_468[0x3];
1365 	u8         log_max_umem[0x5];
1366 	u8         max_num_eqs[0x10];
1367 
1368 	u8         reserved_at_480[0x1];
1369 	u8         tls_tx[0x1];
1370 	u8         tls_rx[0x1];
1371 	u8         log_max_l2_table[0x5];
1372 	u8         reserved_64[0x8];
1373 	u8         log_uar_page_sz[0x10];
1374 
1375 	u8         reserved_65[0x20];
1376 
1377 	u8         device_frequency_mhz[0x20];
1378 
1379 	u8         device_frequency_khz[0x20];
1380 
1381 	u8         reserved_at_500[0x20];
1382 	u8	   num_of_uars_per_page[0x20];
1383 	u8         reserved_at_540[0x40];
1384 
1385 	u8         log_max_atomic_size_qp[0x8];
1386 	u8         reserved_67[0x10];
1387 	u8         log_max_atomic_size_dc[0x8];
1388 
1389 	u8         reserved_at_5a0[0x13];
1390 	u8         log_max_dek[0x5];
1391 	u8         reserved_at_5b8[0x4];
1392 	u8         mini_cqe_resp_stride_index[0x1];
1393 	u8         cqe_128_always[0x1];
1394 	u8         cqe_compression_128b[0x1];
1395 
1396 	u8         cqe_compression[0x1];
1397 
1398 	u8         cqe_compression_timeout[0x10];
1399 	u8         cqe_compression_max_num[0x10];
1400 
1401 	u8         reserved_5e0[0xc0];
1402 
1403 	u8         uctx_cap[0x20];
1404 
1405 	u8         reserved_6c0[0xc0];
1406 
1407 	u8	   vhca_tunnel_commands[0x40];
1408 	u8	   reserved_at_7c0[0x40];
1409 };
1410 
1411 enum mlx5_flow_destination_type {
1412 	MLX5_FLOW_DESTINATION_TYPE_VPORT	= 0x0,
1413 	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE	= 0x1,
1414 	MLX5_FLOW_DESTINATION_TYPE_TIR		= 0x2,
1415 };
1416 
1417 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1418 	struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1419 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1420 	u8         reserved_0[0x40];
1421 };
1422 
1423 struct mlx5_ifc_fte_match_param_bits {
1424 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1425 
1426 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1427 
1428 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1429 
1430 	u8         reserved_0[0xa00];
1431 };
1432 
1433 enum {
1434 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1435 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1436 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1437 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1438 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1439 };
1440 
1441 struct mlx5_ifc_rx_hash_field_select_bits {
1442 	u8         l3_prot_type[0x1];
1443 	u8         l4_prot_type[0x1];
1444 	u8         selected_fields[0x1e];
1445 };
1446 
1447 struct mlx5_ifc_tls_capabilities_bits {
1448 	u8         tls_1_2_aes_gcm_128[0x1];
1449 	u8         tls_1_3_aes_gcm_128[0x1];
1450 	u8         tls_1_2_aes_gcm_256[0x1];
1451 	u8         tls_1_3_aes_gcm_256[0x1];
1452 	u8         reserved_at_4[0x1c];
1453 
1454 	u8         reserved_at_20[0x7e0];
1455 };
1456 
1457 enum {
1458 	MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
1459 	MLX5_WQ_TYPE_CYCLIC                      = 0x1,
1460 	MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
1461 	MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
1462 };
1463 
1464 enum rq_type {
1465 	RQ_TYPE_NONE,
1466 	RQ_TYPE_STRIDE,
1467 };
1468 
1469 enum {
1470 	MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
1471 	MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
1472 };
1473 
1474 struct mlx5_ifc_wq_bits {
1475 	u8         wq_type[0x4];
1476 	u8         wq_signature[0x1];
1477 	u8         end_padding_mode[0x2];
1478 	u8         cd_slave[0x1];
1479 	u8         reserved_0[0x18];
1480 
1481 	u8         hds_skip_first_sge[0x1];
1482 	u8         log2_hds_buf_size[0x3];
1483 	u8         reserved_1[0x7];
1484 	u8         page_offset[0x5];
1485 	u8         lwm[0x10];
1486 
1487 	u8         reserved_2[0x8];
1488 	u8         pd[0x18];
1489 
1490 	u8         reserved_3[0x8];
1491 	u8         uar_page[0x18];
1492 
1493 	u8         dbr_addr[0x40];
1494 
1495 	u8         hw_counter[0x20];
1496 
1497 	u8         sw_counter[0x20];
1498 
1499 	u8         reserved_4[0xc];
1500 	u8         log_wq_stride[0x4];
1501 	u8         reserved_5[0x3];
1502 	u8         log_wq_pg_sz[0x5];
1503 	u8         reserved_6[0x3];
1504 	u8         log_wq_sz[0x5];
1505 
1506 	u8         dbr_umem_valid[0x1];
1507 	u8         wq_umem_valid[0x1];
1508 	u8         reserved_7[0x13];
1509 	u8         single_wqe_log_num_of_strides[0x3];
1510 	u8         two_byte_shift_en[0x1];
1511 	u8         reserved_8[0x4];
1512 	u8         single_stride_log_num_of_bytes[0x3];
1513 
1514 	u8         reserved_9[0x4c0];
1515 
1516 	struct mlx5_ifc_cmd_pas_bits pas[0];
1517 };
1518 
1519 struct mlx5_ifc_rq_num_bits {
1520 	u8         reserved_0[0x8];
1521 	u8         rq_num[0x18];
1522 };
1523 
1524 struct mlx5_ifc_mac_address_layout_bits {
1525 	u8         reserved_0[0x10];
1526 	u8         mac_addr_47_32[0x10];
1527 
1528 	u8         mac_addr_31_0[0x20];
1529 };
1530 
1531 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1532 	u8         reserved_0[0xa0];
1533 
1534 	u8         min_time_between_cnps[0x20];
1535 
1536 	u8         reserved_1[0x12];
1537 	u8         cnp_dscp[0x6];
1538 	u8         reserved_2[0x4];
1539 	u8         cnp_prio_mode[0x1];
1540 	u8         cnp_802p_prio[0x3];
1541 
1542 	u8         reserved_3[0x720];
1543 };
1544 
1545 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1546 	u8         reserved_0[0x60];
1547 
1548 	u8         reserved_1[0x4];
1549 	u8         clamp_tgt_rate[0x1];
1550 	u8         reserved_2[0x3];
1551 	u8         clamp_tgt_rate_after_time_inc[0x1];
1552 	u8         reserved_3[0x17];
1553 
1554 	u8         reserved_4[0x20];
1555 
1556 	u8         rpg_time_reset[0x20];
1557 
1558 	u8         rpg_byte_reset[0x20];
1559 
1560 	u8         rpg_threshold[0x20];
1561 
1562 	u8         rpg_max_rate[0x20];
1563 
1564 	u8         rpg_ai_rate[0x20];
1565 
1566 	u8         rpg_hai_rate[0x20];
1567 
1568 	u8         rpg_gd[0x20];
1569 
1570 	u8         rpg_min_dec_fac[0x20];
1571 
1572 	u8         rpg_min_rate[0x20];
1573 
1574 	u8         reserved_5[0xe0];
1575 
1576 	u8         rate_to_set_on_first_cnp[0x20];
1577 
1578 	u8         dce_tcp_g[0x20];
1579 
1580 	u8         dce_tcp_rtt[0x20];
1581 
1582 	u8         rate_reduce_monitor_period[0x20];
1583 
1584 	u8         reserved_6[0x20];
1585 
1586 	u8         initial_alpha_value[0x20];
1587 
1588 	u8         reserved_7[0x4a0];
1589 };
1590 
1591 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1592 	u8         reserved_0[0x80];
1593 
1594 	u8         rppp_max_rps[0x20];
1595 
1596 	u8         rpg_time_reset[0x20];
1597 
1598 	u8         rpg_byte_reset[0x20];
1599 
1600 	u8         rpg_threshold[0x20];
1601 
1602 	u8         rpg_max_rate[0x20];
1603 
1604 	u8         rpg_ai_rate[0x20];
1605 
1606 	u8         rpg_hai_rate[0x20];
1607 
1608 	u8         rpg_gd[0x20];
1609 
1610 	u8         rpg_min_dec_fac[0x20];
1611 
1612 	u8         rpg_min_rate[0x20];
1613 
1614 	u8         reserved_1[0x640];
1615 };
1616 
1617 enum {
1618 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1619 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1620 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1621 };
1622 
1623 struct mlx5_ifc_resize_field_select_bits {
1624 	u8         resize_field_select[0x20];
1625 };
1626 
1627 enum {
1628 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1629 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1630 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1631 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1632 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE  = 0x10,
1633 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS          = 0x20,
1634 };
1635 
1636 struct mlx5_ifc_modify_field_select_bits {
1637 	u8         modify_field_select[0x20];
1638 };
1639 
1640 struct mlx5_ifc_field_select_r_roce_np_bits {
1641 	u8         field_select_r_roce_np[0x20];
1642 };
1643 
1644 enum {
1645 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1646 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1647 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1648 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1649 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1650 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1651 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1652 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1653 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1654 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1655 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1656 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1657 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1658 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1659 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1660 };
1661 
1662 struct mlx5_ifc_field_select_r_roce_rp_bits {
1663 	u8         field_select_r_roce_rp[0x20];
1664 };
1665 
1666 enum {
1667 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1668 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1669 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1670 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1671 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1672 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1673 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1674 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1675 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1676 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1677 };
1678 
1679 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1680 	u8         field_select_8021qaurp[0x20];
1681 };
1682 
1683 struct mlx5_ifc_pptb_reg_bits {
1684 	u8         reserved_at_0[0x2];
1685 	u8         mm[0x2];
1686 	u8         reserved_at_4[0x4];
1687 	u8         local_port[0x8];
1688 	u8         reserved_at_10[0x6];
1689 	u8         cm[0x1];
1690 	u8         um[0x1];
1691 	u8         pm[0x8];
1692 
1693 	u8         prio_x_buff[0x20];
1694 
1695 	u8         pm_msb[0x8];
1696 	u8         reserved_at_48[0x10];
1697 	u8         ctrl_buff[0x4];
1698 	u8         untagged_buff[0x4];
1699 };
1700 
1701 struct mlx5_ifc_dcbx_app_reg_bits {
1702 	u8         reserved_0[0x8];
1703 	u8         port_number[0x8];
1704 	u8         reserved_1[0x10];
1705 
1706 	u8         reserved_2[0x1a];
1707 	u8         num_app_prio[0x6];
1708 
1709 	u8         reserved_3[0x40];
1710 
1711 	struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1712 };
1713 
1714 struct mlx5_ifc_dcbx_param_reg_bits {
1715 	u8         dcbx_cee_cap[0x1];
1716 	u8         dcbx_ieee_cap[0x1];
1717 	u8         dcbx_standby_cap[0x1];
1718 	u8         reserved_0[0x5];
1719 	u8         port_number[0x8];
1720 	u8         reserved_1[0xa];
1721 	u8         max_application_table_size[0x6];
1722 
1723 	u8         reserved_2[0x15];
1724 	u8         version_oper[0x3];
1725 	u8         reserved_3[0x5];
1726 	u8         version_admin[0x3];
1727 
1728 	u8         willing_admin[0x1];
1729 	u8         reserved_4[0x3];
1730 	u8         pfc_cap_oper[0x4];
1731 	u8         reserved_5[0x4];
1732 	u8         pfc_cap_admin[0x4];
1733 	u8         reserved_6[0x4];
1734 	u8         num_of_tc_oper[0x4];
1735 	u8         reserved_7[0x4];
1736 	u8         num_of_tc_admin[0x4];
1737 
1738 	u8         remote_willing[0x1];
1739 	u8         reserved_8[0x3];
1740 	u8         remote_pfc_cap[0x4];
1741 	u8         reserved_9[0x14];
1742 	u8         remote_num_of_tc[0x4];
1743 
1744 	u8         reserved_10[0x18];
1745 	u8         error[0x8];
1746 
1747 	u8         reserved_11[0x160];
1748 };
1749 
1750 struct mlx5_ifc_qhll_bits {
1751 	u8         reserved_at_0[0x8];
1752 	u8         local_port[0x8];
1753 	u8         reserved_at_10[0x10];
1754 
1755 	u8         reserved_at_20[0x1b];
1756 	u8         hll_time[0x5];
1757 
1758 	u8         stall_en[0x1];
1759 	u8         reserved_at_41[0x1c];
1760 	u8         stall_cnt[0x3];
1761 };
1762 
1763 struct mlx5_ifc_qetcr_reg_bits {
1764 	u8         operation_type[0x2];
1765 	u8         cap_local_admin[0x1];
1766 	u8         cap_remote_admin[0x1];
1767 	u8         reserved_0[0x4];
1768 	u8         port_number[0x8];
1769 	u8         reserved_1[0x10];
1770 
1771 	u8         reserved_2[0x20];
1772 
1773 	u8         tc[8][0x40];
1774 
1775 	u8         global_configuration[0x40];
1776 };
1777 
1778 struct mlx5_ifc_nodnic_ring_config_reg_bits {
1779 	u8         queue_address_63_32[0x20];
1780 
1781 	u8         queue_address_31_12[0x14];
1782 	u8         reserved_0[0x6];
1783 	u8         log_size[0x6];
1784 
1785 	struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1786 
1787 	u8         reserved_1[0x8];
1788 	u8         queue_number[0x18];
1789 
1790 	u8         q_key[0x20];
1791 
1792 	u8         reserved_2[0x10];
1793 	u8         pkey_index[0x10];
1794 
1795 	u8         reserved_3[0x40];
1796 };
1797 
1798 struct mlx5_ifc_nodnic_cq_arming_word_bits {
1799 	u8         reserved_0[0x8];
1800 	u8         cq_ci[0x10];
1801 	u8         reserved_1[0x8];
1802 };
1803 
1804 enum {
1805 	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
1806 	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
1807 };
1808 
1809 enum {
1810 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
1811 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
1812 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
1813 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
1814 };
1815 
1816 struct mlx5_ifc_nodnic_event_word_bits {
1817 	u8         driver_reset_needed[0x1];
1818 	u8         port_management_change_event[0x1];
1819 	u8         reserved_0[0x19];
1820 	u8         link_type[0x1];
1821 	u8         port_state[0x4];
1822 };
1823 
1824 struct mlx5_ifc_nic_vport_change_event_bits {
1825 	u8         reserved_0[0x10];
1826 	u8         vport_num[0x10];
1827 
1828 	u8         reserved_1[0xc0];
1829 };
1830 
1831 struct mlx5_ifc_pages_req_event_bits {
1832 	u8         reserved_0[0x10];
1833 	u8         function_id[0x10];
1834 
1835 	u8         num_pages[0x20];
1836 
1837 	u8         reserved_1[0xa0];
1838 };
1839 
1840 struct mlx5_ifc_cmd_inter_comp_event_bits {
1841 	u8         command_completion_vector[0x20];
1842 
1843 	u8         reserved_0[0xc0];
1844 };
1845 
1846 struct mlx5_ifc_stall_vl_event_bits {
1847 	u8         reserved_0[0x18];
1848 	u8         port_num[0x1];
1849 	u8         reserved_1[0x3];
1850 	u8         vl[0x4];
1851 
1852 	u8         reserved_2[0xa0];
1853 };
1854 
1855 struct mlx5_ifc_db_bf_congestion_event_bits {
1856 	u8         event_subtype[0x8];
1857 	u8         reserved_0[0x8];
1858 	u8         congestion_level[0x8];
1859 	u8         reserved_1[0x8];
1860 
1861 	u8         reserved_2[0xa0];
1862 };
1863 
1864 struct mlx5_ifc_gpio_event_bits {
1865 	u8         reserved_0[0x60];
1866 
1867 	u8         gpio_event_hi[0x20];
1868 
1869 	u8         gpio_event_lo[0x20];
1870 
1871 	u8         reserved_1[0x40];
1872 };
1873 
1874 struct mlx5_ifc_port_state_change_event_bits {
1875 	u8         reserved_0[0x40];
1876 
1877 	u8         port_num[0x4];
1878 	u8         reserved_1[0x1c];
1879 
1880 	u8         reserved_2[0x80];
1881 };
1882 
1883 struct mlx5_ifc_dropped_packet_logged_bits {
1884 	u8         reserved_0[0xe0];
1885 };
1886 
1887 enum {
1888 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1889 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1890 };
1891 
1892 struct mlx5_ifc_cq_error_bits {
1893 	u8         reserved_0[0x8];
1894 	u8         cqn[0x18];
1895 
1896 	u8         reserved_1[0x20];
1897 
1898 	u8         reserved_2[0x18];
1899 	u8         syndrome[0x8];
1900 
1901 	u8         reserved_3[0x80];
1902 };
1903 
1904 struct mlx5_ifc_rdma_page_fault_event_bits {
1905 	u8         bytes_commited[0x20];
1906 
1907 	u8         r_key[0x20];
1908 
1909 	u8         reserved_0[0x10];
1910 	u8         packet_len[0x10];
1911 
1912 	u8         rdma_op_len[0x20];
1913 
1914 	u8         rdma_va[0x40];
1915 
1916 	u8         reserved_1[0x5];
1917 	u8         rdma[0x1];
1918 	u8         write[0x1];
1919 	u8         requestor[0x1];
1920 	u8         qp_number[0x18];
1921 };
1922 
1923 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1924 	u8         bytes_committed[0x20];
1925 
1926 	u8         reserved_0[0x10];
1927 	u8         wqe_index[0x10];
1928 
1929 	u8         reserved_1[0x10];
1930 	u8         len[0x10];
1931 
1932 	u8         reserved_2[0x60];
1933 
1934 	u8         reserved_3[0x5];
1935 	u8         rdma[0x1];
1936 	u8         write_read[0x1];
1937 	u8         requestor[0x1];
1938 	u8         qpn[0x18];
1939 };
1940 
1941 enum {
1942 	MLX5_QP_EVENTS_TYPE_QP  = 0x0,
1943 	MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
1944 	MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
1945 };
1946 
1947 struct mlx5_ifc_qp_events_bits {
1948 	u8         reserved_0[0xa0];
1949 
1950 	u8         type[0x8];
1951 	u8         reserved_1[0x18];
1952 
1953 	u8         reserved_2[0x8];
1954 	u8         qpn_rqn_sqn[0x18];
1955 };
1956 
1957 struct mlx5_ifc_dct_events_bits {
1958 	u8         reserved_0[0xc0];
1959 
1960 	u8         reserved_1[0x8];
1961 	u8         dct_number[0x18];
1962 };
1963 
1964 struct mlx5_ifc_comp_event_bits {
1965 	u8         reserved_0[0xc0];
1966 
1967 	u8         reserved_1[0x8];
1968 	u8         cq_number[0x18];
1969 };
1970 
1971 struct mlx5_ifc_fw_version_bits {
1972 	u8         major[0x10];
1973 	u8         reserved_0[0x10];
1974 
1975 	u8         minor[0x10];
1976 	u8         subminor[0x10];
1977 
1978 	u8         second[0x8];
1979 	u8         minute[0x8];
1980 	u8         hour[0x8];
1981 	u8         reserved_1[0x8];
1982 
1983 	u8         year[0x10];
1984 	u8         month[0x8];
1985 	u8         day[0x8];
1986 };
1987 
1988 enum {
1989 	MLX5_QPC_STATE_RST        = 0x0,
1990 	MLX5_QPC_STATE_INIT       = 0x1,
1991 	MLX5_QPC_STATE_RTR        = 0x2,
1992 	MLX5_QPC_STATE_RTS        = 0x3,
1993 	MLX5_QPC_STATE_SQER       = 0x4,
1994 	MLX5_QPC_STATE_SQD        = 0x5,
1995 	MLX5_QPC_STATE_ERR        = 0x6,
1996 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
1997 };
1998 
1999 enum {
2000 	MLX5_QPC_ST_RC            = 0x0,
2001 	MLX5_QPC_ST_UC            = 0x1,
2002 	MLX5_QPC_ST_UD            = 0x2,
2003 	MLX5_QPC_ST_XRC           = 0x3,
2004 	MLX5_QPC_ST_DCI           = 0x5,
2005 	MLX5_QPC_ST_QP0           = 0x7,
2006 	MLX5_QPC_ST_QP1           = 0x8,
2007 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2008 	MLX5_QPC_ST_REG_UMR       = 0xc,
2009 };
2010 
2011 enum {
2012 	MLX5_QP_PM_ARMED            = 0x0,
2013 	MLX5_QP_PM_REARM            = 0x1,
2014 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2015 	MLX5_QP_PM_MIGRATED         = 0x3,
2016 };
2017 
2018 enum {
2019 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2020 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2021 };
2022 
2023 enum {
2024 	MLX5_QPC_MTU_256_BYTES        = 0x1,
2025 	MLX5_QPC_MTU_512_BYTES        = 0x2,
2026 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
2027 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
2028 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
2029 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2030 };
2031 
2032 enum {
2033 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2034 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2035 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2036 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2037 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2038 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2039 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2040 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2041 };
2042 
2043 enum {
2044 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2045 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2046 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2047 };
2048 
2049 enum {
2050 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
2051 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2052 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2053 };
2054 
2055 enum {
2056 	MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2057 	MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
2058 	MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
2059 };
2060 
2061 struct mlx5_ifc_qpc_bits {
2062 	u8         state[0x4];
2063 	u8         lag_tx_port_affinity[0x4];
2064 	u8         st[0x8];
2065 	u8         reserved_1[0x3];
2066 	u8         pm_state[0x2];
2067 	u8         reserved_2[0x7];
2068 	u8         end_padding_mode[0x2];
2069 	u8         reserved_3[0x2];
2070 
2071 	u8         wq_signature[0x1];
2072 	u8         block_lb_mc[0x1];
2073 	u8         atomic_like_write_en[0x1];
2074 	u8         latency_sensitive[0x1];
2075 	u8         reserved_4[0x1];
2076 	u8         drain_sigerr[0x1];
2077 	u8         reserved_5[0x2];
2078 	u8         pd[0x18];
2079 
2080 	u8         mtu[0x3];
2081 	u8         log_msg_max[0x5];
2082 	u8         reserved_6[0x1];
2083 	u8         log_rq_size[0x4];
2084 	u8         log_rq_stride[0x3];
2085 	u8         no_sq[0x1];
2086 	u8         log_sq_size[0x4];
2087 	u8         reserved_at_55[0x3];
2088 	u8         ts_format[0x2];
2089 	u8         reserved_at_5a[0x1];
2090 	u8         rlky[0x1];
2091 	u8         ulp_stateless_offload_mode[0x4];
2092 
2093 	u8         counter_set_id[0x8];
2094 	u8         uar_page[0x18];
2095 
2096 	u8         reserved_8[0x8];
2097 	u8         user_index[0x18];
2098 
2099 	u8         reserved_9[0x3];
2100 	u8         log_page_size[0x5];
2101 	u8         remote_qpn[0x18];
2102 
2103 	struct mlx5_ifc_ads_bits primary_address_path;
2104 
2105 	struct mlx5_ifc_ads_bits secondary_address_path;
2106 
2107 	u8         log_ack_req_freq[0x4];
2108 	u8         reserved_10[0x4];
2109 	u8         log_sra_max[0x3];
2110 	u8         reserved_11[0x2];
2111 	u8         retry_count[0x3];
2112 	u8         rnr_retry[0x3];
2113 	u8         reserved_12[0x1];
2114 	u8         fre[0x1];
2115 	u8         cur_rnr_retry[0x3];
2116 	u8         cur_retry_count[0x3];
2117 	u8         reserved_13[0x5];
2118 
2119 	u8         reserved_14[0x20];
2120 
2121 	u8         reserved_15[0x8];
2122 	u8         next_send_psn[0x18];
2123 
2124 	u8         reserved_16[0x8];
2125 	u8         cqn_snd[0x18];
2126 
2127 	u8         reserved_at_400[0x8];
2128 
2129 	u8         deth_sqpn[0x18];
2130 	u8         reserved_17[0x20];
2131 
2132 	u8         reserved_18[0x8];
2133 	u8         last_acked_psn[0x18];
2134 
2135 	u8         reserved_19[0x8];
2136 	u8         ssn[0x18];
2137 
2138 	u8         reserved_20[0x8];
2139 	u8         log_rra_max[0x3];
2140 	u8         reserved_21[0x1];
2141 	u8         atomic_mode[0x4];
2142 	u8         rre[0x1];
2143 	u8         rwe[0x1];
2144 	u8         rae[0x1];
2145 	u8         reserved_22[0x1];
2146 	u8         page_offset[0x6];
2147 	u8         reserved_23[0x3];
2148 	u8         cd_slave_receive[0x1];
2149 	u8         cd_slave_send[0x1];
2150 	u8         cd_master[0x1];
2151 
2152 	u8         reserved_24[0x3];
2153 	u8         min_rnr_nak[0x5];
2154 	u8         next_rcv_psn[0x18];
2155 
2156 	u8         reserved_25[0x8];
2157 	u8         xrcd[0x18];
2158 
2159 	u8         reserved_26[0x8];
2160 	u8         cqn_rcv[0x18];
2161 
2162 	u8         dbr_addr[0x40];
2163 
2164 	u8         q_key[0x20];
2165 
2166 	u8         reserved_27[0x5];
2167 	u8         rq_type[0x3];
2168 	u8         srqn_rmpn[0x18];
2169 
2170 	u8         reserved_28[0x8];
2171 	u8         rmsn[0x18];
2172 
2173 	u8         hw_sq_wqebb_counter[0x10];
2174 	u8         sw_sq_wqebb_counter[0x10];
2175 
2176 	u8         hw_rq_counter[0x20];
2177 
2178 	u8         sw_rq_counter[0x20];
2179 
2180 	u8         reserved_29[0x20];
2181 
2182 	u8         reserved_30[0xf];
2183 	u8         cgs[0x1];
2184 	u8         cs_req[0x8];
2185 	u8         cs_res[0x8];
2186 
2187 	u8         dc_access_key[0x40];
2188 
2189 	u8         reserved_at_680[0x3];
2190 	u8         dbr_umem_valid[0x1];
2191 
2192 	u8         reserved_at_684[0xbc];
2193 };
2194 
2195 struct mlx5_ifc_roce_addr_layout_bits {
2196 	u8         source_l3_address[16][0x8];
2197 
2198 	u8         reserved_0[0x3];
2199 	u8         vlan_valid[0x1];
2200 	u8         vlan_id[0xc];
2201 	u8         source_mac_47_32[0x10];
2202 
2203 	u8         source_mac_31_0[0x20];
2204 
2205 	u8         reserved_1[0x14];
2206 	u8         roce_l3_type[0x4];
2207 	u8         roce_version[0x8];
2208 
2209 	u8         reserved_2[0x20];
2210 };
2211 
2212 struct mlx5_ifc_rdbc_bits {
2213 	u8         reserved_0[0x1c];
2214 	u8         type[0x4];
2215 
2216 	u8         reserved_1[0x20];
2217 
2218 	u8         reserved_2[0x8];
2219 	u8         psn[0x18];
2220 
2221 	u8         rkey[0x20];
2222 
2223 	u8         address[0x40];
2224 
2225 	u8         byte_count[0x20];
2226 
2227 	u8         reserved_3[0x20];
2228 
2229 	u8         atomic_resp[32][0x8];
2230 };
2231 
2232 enum {
2233 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2234 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2235 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2236 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2237 };
2238 
2239 struct mlx5_ifc_flow_context_bits {
2240 	u8         reserved_0[0x20];
2241 
2242 	u8         group_id[0x20];
2243 
2244 	u8         reserved_1[0x8];
2245 	u8         flow_tag[0x18];
2246 
2247 	u8         reserved_2[0x10];
2248 	u8         action[0x10];
2249 
2250 	u8         reserved_3[0x8];
2251 	u8         destination_list_size[0x18];
2252 
2253 	u8         reserved_4[0x8];
2254 	u8         flow_counter_list_size[0x18];
2255 
2256 	u8         reserved_5[0x140];
2257 
2258 	struct mlx5_ifc_fte_match_param_bits match_value;
2259 
2260 	u8         reserved_6[0x600];
2261 
2262 	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2263 };
2264 
2265 enum {
2266 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2267 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2268 };
2269 
2270 struct mlx5_ifc_xrc_srqc_bits {
2271 	u8         state[0x4];
2272 	u8         log_xrc_srq_size[0x4];
2273 	u8         reserved_0[0x18];
2274 
2275 	u8         wq_signature[0x1];
2276 	u8         cont_srq[0x1];
2277 	u8         reserved_1[0x1];
2278 	u8         rlky[0x1];
2279 	u8         basic_cyclic_rcv_wqe[0x1];
2280 	u8         log_rq_stride[0x3];
2281 	u8         xrcd[0x18];
2282 
2283 	u8         page_offset[0x6];
2284 	u8         reserved_at_46[0x1];
2285 	u8         dbr_umem_valid[0x1];
2286 	u8         cqn[0x18];
2287 
2288 	u8         reserved_3[0x20];
2289 
2290 	u8         reserved_4[0x2];
2291 	u8         log_page_size[0x6];
2292 	u8         user_index[0x18];
2293 
2294 	u8         reserved_5[0x20];
2295 
2296 	u8         reserved_6[0x8];
2297 	u8         pd[0x18];
2298 
2299 	u8         lwm[0x10];
2300 	u8         wqe_cnt[0x10];
2301 
2302 	u8         reserved_7[0x40];
2303 
2304 	u8         db_record_addr_h[0x20];
2305 
2306 	u8         db_record_addr_l[0x1e];
2307 	u8         reserved_8[0x2];
2308 
2309 	u8         reserved_9[0x80];
2310 };
2311 
2312 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2313 	u8         counter_error_queues[0x20];
2314 
2315 	u8         total_error_queues[0x20];
2316 
2317 	u8         send_queue_priority_update_flow[0x20];
2318 
2319 	u8         reserved_at_60[0x20];
2320 
2321 	u8         nic_receive_steering_discard[0x40];
2322 
2323 	u8         receive_discard_vport_down[0x40];
2324 
2325 	u8         transmit_discard_vport_down[0x40];
2326 
2327 	u8         reserved_at_140[0xec0];
2328 };
2329 
2330 struct mlx5_ifc_traffic_counter_bits {
2331 	u8         packets[0x40];
2332 
2333 	u8         octets[0x40];
2334 };
2335 
2336 struct mlx5_ifc_tisc_bits {
2337 	u8         strict_lag_tx_port_affinity[0x1];
2338 	u8         tls_en[0x1];
2339 	u8         reserved_at_2[0x2];
2340 	u8         lag_tx_port_affinity[0x04];
2341 
2342 	u8         reserved_at_8[0x4];
2343 	u8         prio[0x4];
2344 	u8         reserved_1[0x10];
2345 
2346 	u8         reserved_2[0x100];
2347 
2348 	u8         reserved_3[0x8];
2349 	u8         transport_domain[0x18];
2350 
2351 	u8         reserved_4[0x8];
2352 	u8         underlay_qpn[0x18];
2353 
2354 	u8         reserved_5[0x8];
2355 	u8         pd[0x18];
2356 
2357 	u8         reserved_6[0x380];
2358 };
2359 
2360 enum {
2361 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2362 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2363 };
2364 
2365 enum {
2366 	MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2367 	MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2368 };
2369 
2370 enum {
2371 	MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
2372 	MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
2373 	MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
2374 };
2375 
2376 enum {
2377 	MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
2378 	MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
2379 };
2380 
2381 struct mlx5_ifc_tirc_bits {
2382 	u8         reserved_0[0x20];
2383 
2384 	u8         disp_type[0x4];
2385 	u8         tls_en[0x1];
2386 	u8         reserved_at_25[0x1b];
2387 
2388 	u8         reserved_2[0x40];
2389 
2390 	u8         reserved_3[0x4];
2391 	u8         lro_timeout_period_usecs[0x10];
2392 	u8         lro_enable_mask[0x4];
2393 	u8         lro_max_msg_sz[0x8];
2394 
2395 	u8         reserved_4[0x40];
2396 
2397 	u8         reserved_5[0x8];
2398 	u8         inline_rqn[0x18];
2399 
2400 	u8         rx_hash_symmetric[0x1];
2401 	u8         reserved_6[0x1];
2402 	u8         tunneled_offload_en[0x1];
2403 	u8         reserved_7[0x5];
2404 	u8         indirect_table[0x18];
2405 
2406 	u8         rx_hash_fn[0x4];
2407 	u8         reserved_8[0x2];
2408 	u8         self_lb_en[0x2];
2409 	u8         transport_domain[0x18];
2410 
2411 	u8         rx_hash_toeplitz_key[10][0x20];
2412 
2413 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2414 
2415 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2416 
2417 	u8         reserved_9[0x4c0];
2418 };
2419 
2420 enum {
2421 	MLX5_SRQC_STATE_GOOD   = 0x0,
2422 	MLX5_SRQC_STATE_ERROR  = 0x1,
2423 };
2424 
2425 struct mlx5_ifc_srqc_bits {
2426 	u8         state[0x4];
2427 	u8         log_srq_size[0x4];
2428 	u8         reserved_0[0x18];
2429 
2430 	u8         wq_signature[0x1];
2431 	u8         cont_srq[0x1];
2432 	u8         reserved_1[0x1];
2433 	u8         rlky[0x1];
2434 	u8         reserved_2[0x1];
2435 	u8         log_rq_stride[0x3];
2436 	u8         xrcd[0x18];
2437 
2438 	u8         page_offset[0x6];
2439 	u8         reserved_3[0x2];
2440 	u8         cqn[0x18];
2441 
2442 	u8         reserved_4[0x20];
2443 
2444 	u8         reserved_5[0x2];
2445 	u8         log_page_size[0x6];
2446 	u8         reserved_6[0x18];
2447 
2448 	u8         reserved_7[0x20];
2449 
2450 	u8         reserved_8[0x8];
2451 	u8         pd[0x18];
2452 
2453 	u8         lwm[0x10];
2454 	u8         wqe_cnt[0x10];
2455 
2456 	u8         reserved_9[0x40];
2457 
2458 	u8	   dbr_addr[0x40];
2459 
2460 	u8	   reserved_10[0x80];
2461 };
2462 
2463 enum {
2464 	MLX5_SQC_STATE_RST  = 0x0,
2465 	MLX5_SQC_STATE_RDY  = 0x1,
2466 	MLX5_SQC_STATE_ERR  = 0x3,
2467 };
2468 
2469 enum {
2470 	MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2471 	MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
2472 	MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
2473 };
2474 
2475 struct mlx5_ifc_sqc_bits {
2476 	u8         rlkey[0x1];
2477 	u8         cd_master[0x1];
2478 	u8         fre[0x1];
2479 	u8         flush_in_error_en[0x1];
2480 	u8         allow_multi_pkt_send_wqe[0x1];
2481 	u8         min_wqe_inline_mode[0x3];
2482 	u8         state[0x4];
2483 	u8         reg_umr[0x1];
2484 	u8         allow_swp[0x1];
2485 	u8         reserved_at_e[0x4];
2486 	u8	   qos_remap_en[0x1];
2487 	u8	   reserved_at_d[0x7];
2488 	u8         ts_format[0x2];
2489 	u8         reserved_at_1c[0x4];
2490 
2491 	u8         reserved_1[0x8];
2492 	u8         user_index[0x18];
2493 
2494 	u8         reserved_2[0x8];
2495 	u8         cqn[0x18];
2496 
2497 	u8         reserved_3[0x80];
2498 
2499 	u8         qos_para_vport_number[0x10];
2500 	u8         packet_pacing_rate_limit_index[0x10];
2501 
2502 	u8         tis_lst_sz[0x10];
2503 	u8         qos_queue_group_id[0x10];
2504 
2505 	u8	   reserved_4[0x8];
2506 	u8	   queue_handle[0x18];
2507 
2508 	u8         reserved_5[0x20];
2509 
2510 	u8         reserved_6[0x8];
2511 	u8         tis_num_0[0x18];
2512 
2513 	struct mlx5_ifc_wq_bits wq;
2514 };
2515 
2516 struct mlx5_ifc_query_pp_rate_limit_in_bits {
2517 	u8	   opcode[0x10];
2518 	u8	   uid[0x10];
2519 
2520 	u8	   reserved1[0x10];
2521 	u8         op_mod[0x10];
2522 
2523 	u8         reserved2[0x10];
2524         u8         rate_limit_index[0x10];
2525 
2526 	u8         reserved_3[0x20];
2527 };
2528 
2529 struct mlx5_ifc_pp_context_bits {
2530 	u8	   rate_limit[0x20];
2531 
2532 	u8	   burst_upper_bound[0x20];
2533 
2534 	u8	   reserved_1[0xc];
2535 	u8	   rate_mode[0x4];
2536 	u8	   typical_packet_size[0x10];
2537 
2538 	u8	   reserved_2[0x8];
2539 	u8	   qos_handle[0x18];
2540 
2541 	u8	   reserved_3[0x40];
2542 };
2543 
2544 struct mlx5_ifc_query_pp_rate_limit_out_bits {
2545         u8	   status[0x8];
2546 	u8         reserved_1[0x18];
2547 
2548         u8         syndrome[0x20];
2549 
2550         u8         reserved_2[0x40];
2551 
2552 	struct mlx5_ifc_pp_context_bits pp_context;
2553 };
2554 
2555 enum {
2556 	MLX5_TSAR_TYPE_DWRR = 0,
2557 	MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2558 	MLX5_TSAR_TYPE_ETS = 2
2559 };
2560 
2561 struct mlx5_ifc_tsar_element_attributes_bits {
2562 	u8         reserved_0[0x8];
2563 	u8         tsar_type[0x8];
2564 	u8	   reserved_1[0x10];
2565 };
2566 
2567 struct mlx5_ifc_vport_element_attributes_bits {
2568 	u8         reserved_0[0x10];
2569 	u8         vport_number[0x10];
2570 };
2571 
2572 struct mlx5_ifc_vport_tc_element_attributes_bits {
2573 	u8         traffic_class[0x10];
2574 	u8         vport_number[0x10];
2575 };
2576 
2577 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2578 	u8         reserved_0[0x0C];
2579 	u8         traffic_class[0x04];
2580 	u8         qos_para_vport_number[0x10];
2581 };
2582 
2583 enum {
2584 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR           = 0x0,
2585 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT          = 0x1,
2586 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC       = 0x2,
2587 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC  = 0x3,
2588 };
2589 
2590 struct mlx5_ifc_scheduling_context_bits {
2591 	u8         element_type[0x8];
2592 	u8         reserved_at_8[0x18];
2593 
2594 	u8         element_attributes[0x20];
2595 
2596 	u8         parent_element_id[0x20];
2597 
2598 	u8         reserved_at_60[0x40];
2599 
2600 	u8         bw_share[0x20];
2601 
2602 	u8         max_average_bw[0x20];
2603 
2604 	u8         reserved_at_e0[0x120];
2605 };
2606 
2607 struct mlx5_ifc_rqtc_bits {
2608 	u8         reserved_0[0xa0];
2609 
2610 	u8         reserved_1[0x10];
2611 	u8         rqt_max_size[0x10];
2612 
2613 	u8         reserved_2[0x10];
2614 	u8         rqt_actual_size[0x10];
2615 
2616 	u8         reserved_3[0x6a0];
2617 
2618 	struct mlx5_ifc_rq_num_bits rq_num[0];
2619 };
2620 
2621 enum {
2622 	MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
2623 	MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
2624 };
2625 
2626 enum {
2627 	MLX5_RQC_STATE_RST  = 0x0,
2628 	MLX5_RQC_STATE_RDY  = 0x1,
2629 	MLX5_RQC_STATE_ERR  = 0x3,
2630 };
2631 
2632 enum {
2633 	MLX5_RQC_DROPLESS_MODE_DISABLE        = 0x0,
2634 	MLX5_RQC_DROPLESS_MODE_ENABLE         = 0x1,
2635 };
2636 
2637 enum {
2638 	MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2639 	MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
2640 	MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
2641 };
2642 
2643 struct mlx5_ifc_rqc_bits {
2644 	u8         rlkey[0x1];
2645 	u8         delay_drop_en[0x1];
2646 	u8         scatter_fcs[0x1];
2647 	u8         vlan_strip_disable[0x1];
2648 	u8         mem_rq_type[0x4];
2649 	u8         state[0x4];
2650 	u8         reserved_1[0x1];
2651 	u8         flush_in_error_en[0x1];
2652 	u8         reserved_at_e[0xc];
2653 	u8         ts_format[0x2];
2654 	u8         reserved_at_1c[0x4];
2655 
2656 	u8         reserved_3[0x8];
2657 	u8         user_index[0x18];
2658 
2659 	u8         reserved_4[0x8];
2660 	u8         cqn[0x18];
2661 
2662 	u8         counter_set_id[0x8];
2663 	u8         reserved_5[0x18];
2664 
2665 	u8         reserved_6[0x8];
2666 	u8         rmpn[0x18];
2667 
2668 	u8         reserved_7[0xe0];
2669 
2670 	struct mlx5_ifc_wq_bits wq;
2671 };
2672 
2673 enum {
2674 	MLX5_RMPC_STATE_RDY  = 0x1,
2675 	MLX5_RMPC_STATE_ERR  = 0x3,
2676 };
2677 
2678 struct mlx5_ifc_rmpc_bits {
2679 	u8         reserved_0[0x8];
2680 	u8         state[0x4];
2681 	u8         reserved_1[0x14];
2682 
2683 	u8         basic_cyclic_rcv_wqe[0x1];
2684 	u8         reserved_2[0x1f];
2685 
2686 	u8         reserved_3[0x140];
2687 
2688 	struct mlx5_ifc_wq_bits wq;
2689 };
2690 
2691 enum {
2692 	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
2693 	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
2694 	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
2695 };
2696 
2697 struct mlx5_ifc_nic_vport_context_bits {
2698 	u8         reserved_0[0x5];
2699 	u8         min_wqe_inline_mode[0x3];
2700 	u8         reserved_1[0x15];
2701 	u8         disable_mc_local_lb[0x1];
2702 	u8         disable_uc_local_lb[0x1];
2703 	u8         roce_en[0x1];
2704 
2705 	u8         arm_change_event[0x1];
2706 	u8         reserved_2[0x1a];
2707 	u8         event_on_mtu[0x1];
2708 	u8         event_on_promisc_change[0x1];
2709 	u8         event_on_vlan_change[0x1];
2710 	u8         event_on_mc_address_change[0x1];
2711 	u8         event_on_uc_address_change[0x1];
2712 
2713 	u8         reserved_3[0xe0];
2714 
2715 	u8         reserved_4[0x10];
2716 	u8         mtu[0x10];
2717 
2718 	u8         system_image_guid[0x40];
2719 
2720 	u8         port_guid[0x40];
2721 
2722 	u8         node_guid[0x40];
2723 
2724 	u8         reserved_5[0x140];
2725 
2726 	u8         qkey_violation_counter[0x10];
2727 	u8         reserved_6[0x10];
2728 
2729 	u8         reserved_7[0x420];
2730 
2731 	u8         promisc_uc[0x1];
2732 	u8         promisc_mc[0x1];
2733 	u8         promisc_all[0x1];
2734 	u8         reserved_8[0x2];
2735 	u8         allowed_list_type[0x3];
2736 	u8         reserved_9[0xc];
2737 	u8         allowed_list_size[0xc];
2738 
2739 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
2740 
2741 	u8         reserved_10[0x20];
2742 
2743 	u8         current_uc_mac_address[0][0x40];
2744 };
2745 
2746 enum {
2747 	MLX5_ACCESS_MODE_PA        = 0x0,
2748 	MLX5_ACCESS_MODE_MTT       = 0x1,
2749 	MLX5_ACCESS_MODE_KLM       = 0x2,
2750 	MLX5_ACCESS_MODE_KSM       = 0x3,
2751 	MLX5_ACCESS_MODE_SW_ICM    = 0x4,
2752 	MLX5_ACCESS_MODE_MEMIC     = 0x5,
2753 };
2754 
2755 struct mlx5_ifc_mkc_bits {
2756 	u8         reserved_at_0[0x1];
2757 	u8         free[0x1];
2758 	u8         reserved_at_2[0x1];
2759 	u8         access_mode_4_2[0x3];
2760 	u8         reserved_at_6[0x7];
2761 	u8         relaxed_ordering_write[0x1];
2762 	u8         reserved_at_e[0x1];
2763 	u8         small_fence_on_rdma_read_response[0x1];
2764 	u8         umr_en[0x1];
2765 	u8         a[0x1];
2766 	u8         rw[0x1];
2767 	u8         rr[0x1];
2768 	u8         lw[0x1];
2769 	u8         lr[0x1];
2770 	u8         access_mode[0x2];
2771 	u8         reserved_2[0x8];
2772 
2773 	u8         qpn[0x18];
2774 	u8         mkey_7_0[0x8];
2775 
2776 	u8         reserved_3[0x20];
2777 
2778 	u8         length64[0x1];
2779 	u8         bsf_en[0x1];
2780 	u8         sync_umr[0x1];
2781 	u8         reserved_4[0x2];
2782 	u8         expected_sigerr_count[0x1];
2783 	u8         reserved_5[0x1];
2784 	u8         en_rinval[0x1];
2785 	u8         pd[0x18];
2786 
2787 	u8         start_addr[0x40];
2788 
2789 	u8         len[0x40];
2790 
2791 	u8         bsf_octword_size[0x20];
2792 
2793 	u8         reserved_6[0x80];
2794 
2795 	u8         translations_octword_size[0x20];
2796 
2797 	u8         reserved_at_1c0[0x19];
2798 	u8         relaxed_ordering_read[0x1];
2799 	u8         reserved_at_1d9[0x1];
2800 	u8         log_page_size[0x5];
2801 
2802 	u8         reserved_8[0x20];
2803 };
2804 
2805 struct mlx5_ifc_pkey_bits {
2806 	u8         reserved_0[0x10];
2807 	u8         pkey[0x10];
2808 };
2809 
2810 struct mlx5_ifc_array128_auto_bits {
2811 	u8         array128_auto[16][0x8];
2812 };
2813 
2814 enum {
2815 	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
2816 	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
2817 	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
2818 };
2819 
2820 enum {
2821 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
2822 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
2823 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
2824 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
2825 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
2826 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
2827 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
2828 };
2829 
2830 enum {
2831 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
2832 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
2833 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
2834 };
2835 
2836 enum {
2837 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
2838 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
2839 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
2840 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
2841 };
2842 
2843 enum {
2844 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
2845 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
2846 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
2847 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
2848 };
2849 
2850 struct mlx5_ifc_hca_vport_context_bits {
2851 	u8         field_select[0x20];
2852 
2853 	u8         reserved_0[0xe0];
2854 
2855 	u8         sm_virt_aware[0x1];
2856 	u8         has_smi[0x1];
2857 	u8         has_raw[0x1];
2858 	u8         grh_required[0x1];
2859 	u8         reserved_1[0x1];
2860 	u8         min_wqe_inline_mode[0x3];
2861 	u8         reserved_2[0x8];
2862 	u8         port_physical_state[0x4];
2863 	u8         vport_state_policy[0x4];
2864 	u8         port_state[0x4];
2865 	u8         vport_state[0x4];
2866 
2867 	u8         reserved_3[0x20];
2868 
2869 	u8         system_image_guid[0x40];
2870 
2871 	u8         port_guid[0x40];
2872 
2873 	u8         node_guid[0x40];
2874 
2875 	u8         cap_mask1[0x20];
2876 
2877 	u8         cap_mask1_field_select[0x20];
2878 
2879 	u8         cap_mask2[0x20];
2880 
2881 	u8         cap_mask2_field_select[0x20];
2882 
2883 	u8         reserved_4[0x80];
2884 
2885 	u8         lid[0x10];
2886 	u8         reserved_5[0x4];
2887 	u8         init_type_reply[0x4];
2888 	u8         lmc[0x3];
2889 	u8         subnet_timeout[0x5];
2890 
2891 	u8         sm_lid[0x10];
2892 	u8         sm_sl[0x4];
2893 	u8         reserved_6[0xc];
2894 
2895 	u8         qkey_violation_counter[0x10];
2896 	u8         pkey_violation_counter[0x10];
2897 
2898 	u8         reserved_7[0xca0];
2899 };
2900 
2901 union mlx5_ifc_hca_cap_union_bits {
2902 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2903 	struct mlx5_ifc_odp_cap_bits odp_cap;
2904 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
2905 	struct mlx5_ifc_roce_cap_bits roce_cap;
2906 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2907 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2908 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2909 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2910 	struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2911 	struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2912 	struct mlx5_ifc_qos_cap_bits qos_cap;
2913 	struct mlx5_ifc_tls_capabilities_bits tls_capabilities;
2914 	u8         reserved_0[0x8000];
2915 };
2916 
2917 enum {
2918 	MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
2919 	MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
2920 };
2921 
2922 struct mlx5_ifc_flow_table_context_bits {
2923 	u8         encap_en[0x1];
2924 	u8         decap_en[0x1];
2925 	u8         reserved_at_2[0x2];
2926 	u8         table_miss_action[0x4];
2927 	u8         level[0x8];
2928 	u8         reserved_at_10[0x8];
2929 	u8         log_size[0x8];
2930 
2931 	u8         reserved_at_20[0x8];
2932 	u8         table_miss_id[0x18];
2933 
2934 	u8         reserved_at_40[0x8];
2935 	u8         lag_master_next_table_id[0x18];
2936 
2937 	u8         reserved_at_60[0xe0];
2938 };
2939 
2940 struct mlx5_ifc_esw_vport_context_bits {
2941 	u8         reserved_0[0x3];
2942 	u8         vport_svlan_strip[0x1];
2943 	u8         vport_cvlan_strip[0x1];
2944 	u8         vport_svlan_insert[0x1];
2945 	u8         vport_cvlan_insert[0x2];
2946 	u8         reserved_1[0x18];
2947 
2948 	u8         reserved_2[0x20];
2949 
2950 	u8         svlan_cfi[0x1];
2951 	u8         svlan_pcp[0x3];
2952 	u8         svlan_id[0xc];
2953 	u8         cvlan_cfi[0x1];
2954 	u8         cvlan_pcp[0x3];
2955 	u8         cvlan_id[0xc];
2956 
2957 	u8         reserved_3[0x7a0];
2958 };
2959 
2960 enum {
2961 	MLX5_EQC_STATUS_OK                = 0x0,
2962 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2963 };
2964 
2965 enum {
2966 	MLX5_EQ_STATE_ARMED = 0x9,
2967 	MLX5_EQ_STATE_FIRED = 0xa,
2968 };
2969 
2970 struct mlx5_ifc_eqc_bits {
2971 	u8         status[0x4];
2972 	u8         reserved_0[0x9];
2973 	u8         ec[0x1];
2974 	u8         oi[0x1];
2975 	u8         reserved_1[0x5];
2976 	u8         st[0x4];
2977 	u8         reserved_2[0x8];
2978 
2979 	u8         reserved_3[0x20];
2980 
2981 	u8         reserved_4[0x14];
2982 	u8         page_offset[0x6];
2983 	u8         reserved_5[0x6];
2984 
2985 	u8         reserved_6[0x3];
2986 	u8         log_eq_size[0x5];
2987 	u8         uar_page[0x18];
2988 
2989 	u8         reserved_7[0x20];
2990 
2991 	u8         reserved_8[0x18];
2992 	u8         intr[0x8];
2993 
2994 	u8         reserved_9[0x3];
2995 	u8         log_page_size[0x5];
2996 	u8         reserved_10[0x18];
2997 
2998 	u8         reserved_11[0x60];
2999 
3000 	u8         reserved_12[0x8];
3001 	u8         consumer_counter[0x18];
3002 
3003 	u8         reserved_13[0x8];
3004 	u8         producer_counter[0x18];
3005 
3006 	u8         reserved_14[0x80];
3007 };
3008 
3009 enum {
3010 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
3011 	MLX5_DCTC_STATE_DRAINING  = 0x1,
3012 	MLX5_DCTC_STATE_DRAINED   = 0x2,
3013 };
3014 
3015 enum {
3016 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3017 	MLX5_DCTC_CS_RES_NA         = 0x1,
3018 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3019 };
3020 
3021 enum {
3022 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
3023 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
3024 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3025 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3026 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3027 };
3028 
3029 struct mlx5_ifc_dctc_bits {
3030 	u8         reserved_0[0x4];
3031 	u8         state[0x4];
3032 	u8         reserved_1[0x18];
3033 
3034 	u8         reserved_2[0x8];
3035 	u8         user_index[0x18];
3036 
3037 	u8         reserved_3[0x8];
3038 	u8         cqn[0x18];
3039 
3040 	u8         counter_set_id[0x8];
3041 	u8         atomic_mode[0x4];
3042 	u8         rre[0x1];
3043 	u8         rwe[0x1];
3044 	u8         rae[0x1];
3045 	u8         atomic_like_write_en[0x1];
3046 	u8         latency_sensitive[0x1];
3047 	u8         rlky[0x1];
3048 	u8         reserved_4[0xe];
3049 
3050 	u8         reserved_5[0x8];
3051 	u8         cs_res[0x8];
3052 	u8         reserved_6[0x3];
3053 	u8         min_rnr_nak[0x5];
3054 	u8         reserved_7[0x8];
3055 
3056 	u8         reserved_8[0x8];
3057 	u8         srqn[0x18];
3058 
3059 	u8         reserved_9[0x8];
3060 	u8         pd[0x18];
3061 
3062 	u8         tclass[0x8];
3063 	u8         reserved_10[0x4];
3064 	u8         flow_label[0x14];
3065 
3066 	u8         dc_access_key[0x40];
3067 
3068 	u8         reserved_11[0x5];
3069 	u8         mtu[0x3];
3070 	u8         port[0x8];
3071 	u8         pkey_index[0x10];
3072 
3073 	u8         reserved_12[0x8];
3074 	u8         my_addr_index[0x8];
3075 	u8         reserved_13[0x8];
3076 	u8         hop_limit[0x8];
3077 
3078 	u8         dc_access_key_violation_count[0x20];
3079 
3080 	u8         reserved_14[0x14];
3081 	u8         dei_cfi[0x1];
3082 	u8         eth_prio[0x3];
3083 	u8         ecn[0x2];
3084 	u8         dscp[0x6];
3085 
3086 	u8         reserved_15[0x40];
3087 };
3088 
3089 enum {
3090 	MLX5_CQC_STATUS_OK             = 0x0,
3091 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3092 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3093 };
3094 
3095 enum {
3096 	CQE_SIZE_64                = 0x0,
3097 	CQE_SIZE_128               = 0x1,
3098 };
3099 
3100 enum {
3101 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
3102 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
3103 };
3104 
3105 enum {
3106 	MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
3107 	MLX5_CQ_STATE_ARMED                               = 0x9,
3108 	MLX5_CQ_STATE_FIRED                               = 0xa,
3109 };
3110 
3111 struct mlx5_ifc_cqc_bits {
3112 	u8         status[0x4];
3113 	u8         reserved_at_4[0x2];
3114 	u8         dbr_umem_valid[0x1];
3115 	u8         reserved_at_7[0x1];
3116 	u8         cqe_sz[0x3];
3117 	u8         cc[0x1];
3118 	u8         reserved_1[0x1];
3119 	u8         scqe_break_moderation_en[0x1];
3120 	u8         oi[0x1];
3121 	u8         cq_period_mode[0x2];
3122 	u8         cqe_compression_en[0x1];
3123 	u8         mini_cqe_res_format[0x2];
3124 	u8         st[0x4];
3125 	u8         reserved_2[0x8];
3126 
3127 	u8         reserved_3[0x20];
3128 
3129 	u8         reserved_4[0x14];
3130 	u8         page_offset[0x6];
3131 	u8         reserved_5[0x6];
3132 
3133 	u8         reserved_6[0x3];
3134 	u8         log_cq_size[0x5];
3135 	u8         uar_page[0x18];
3136 
3137 	u8         reserved_7[0x4];
3138 	u8         cq_period[0xc];
3139 	u8         cq_max_count[0x10];
3140 
3141 	u8         reserved_8[0x18];
3142 	u8         c_eqn[0x8];
3143 
3144 	u8         reserved_9[0x3];
3145 	u8         log_page_size[0x5];
3146 	u8         reserved_10[0x18];
3147 
3148 	u8         reserved_11[0x20];
3149 
3150 	u8         reserved_12[0x8];
3151 	u8         last_notified_index[0x18];
3152 
3153 	u8         reserved_13[0x8];
3154 	u8         last_solicit_index[0x18];
3155 
3156 	u8         reserved_14[0x8];
3157 	u8         consumer_counter[0x18];
3158 
3159 	u8         reserved_15[0x8];
3160 	u8         producer_counter[0x18];
3161 
3162 	u8         reserved_16[0x40];
3163 
3164 	u8         dbr_addr[0x40];
3165 };
3166 
3167 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3168 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3169 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3170 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3171 	u8         reserved_0[0x800];
3172 };
3173 
3174 struct mlx5_ifc_query_adapter_param_block_bits {
3175 	u8         reserved_0[0xc0];
3176 
3177 	u8         reserved_1[0x8];
3178 	u8         ieee_vendor_id[0x18];
3179 
3180 	u8         reserved_2[0x10];
3181 	u8         vsd_vendor_id[0x10];
3182 
3183 	u8         vsd[208][0x8];
3184 
3185 	u8         vsd_contd_psid[16][0x8];
3186 };
3187 
3188 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3189 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
3190 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
3191 	u8         reserved_0[0x20];
3192 };
3193 
3194 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3195 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3196 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3197 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3198 	u8         reserved_0[0x20];
3199 };
3200 
3201 struct mlx5_ifc_bufferx_reg_bits {
3202 	u8         reserved_0[0x6];
3203 	u8         lossy[0x1];
3204 	u8         epsb[0x1];
3205 	u8         reserved_1[0xc];
3206 	u8         size[0xc];
3207 
3208 	u8         xoff_threshold[0x10];
3209 	u8         xon_threshold[0x10];
3210 };
3211 
3212 struct mlx5_ifc_config_item_bits {
3213 	u8         valid[0x2];
3214 	u8         reserved_0[0x2];
3215 	u8         header_type[0x2];
3216 	u8         reserved_1[0x2];
3217 	u8         default_location[0x1];
3218 	u8         reserved_2[0x7];
3219 	u8         version[0x4];
3220 	u8         reserved_3[0x3];
3221 	u8         length[0x9];
3222 
3223 	u8         type[0x20];
3224 
3225 	u8         reserved_4[0x10];
3226 	u8         crc16[0x10];
3227 };
3228 
3229 enum {
3230 	MLX5_XRQC_STATE_GOOD   = 0x0,
3231 	MLX5_XRQC_STATE_ERROR  = 0x1,
3232 };
3233 
3234 enum {
3235 	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3236 	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3237 };
3238 
3239 enum {
3240 	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3241 };
3242 
3243 struct mlx5_ifc_tag_matching_topology_context_bits {
3244 	u8         log_matching_list_sz[0x4];
3245 	u8         reserved_at_4[0xc];
3246 	u8         append_next_index[0x10];
3247 
3248 	u8         sw_phase_cnt[0x10];
3249 	u8         hw_phase_cnt[0x10];
3250 
3251 	u8         reserved_at_40[0x40];
3252 };
3253 
3254 struct mlx5_ifc_xrqc_bits {
3255 	u8         state[0x4];
3256 	u8         rlkey[0x1];
3257 	u8         reserved_at_5[0xf];
3258 	u8         topology[0x4];
3259 	u8         reserved_at_18[0x4];
3260 	u8         offload[0x4];
3261 
3262 	u8         reserved_at_20[0x8];
3263 	u8         user_index[0x18];
3264 
3265 	u8         reserved_at_40[0x8];
3266 	u8         cqn[0x18];
3267 
3268 	u8         reserved_at_60[0xa0];
3269 
3270 	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3271 
3272 	u8         reserved_at_180[0x280];
3273 
3274 	struct mlx5_ifc_wq_bits wq;
3275 };
3276 
3277 struct mlx5_ifc_nodnic_port_config_reg_bits {
3278 	struct mlx5_ifc_nodnic_event_word_bits event;
3279 
3280 	u8         network_en[0x1];
3281 	u8         dma_en[0x1];
3282 	u8         promisc_en[0x1];
3283 	u8         promisc_multicast_en[0x1];
3284 	u8         reserved_0[0x17];
3285 	u8         receive_filter_en[0x5];
3286 
3287 	u8         reserved_1[0x10];
3288 	u8         mac_47_32[0x10];
3289 
3290 	u8         mac_31_0[0x20];
3291 
3292 	u8         receive_filters_mgid_mac[64][0x8];
3293 
3294 	u8         gid[16][0x8];
3295 
3296 	u8         reserved_2[0x10];
3297 	u8         lid[0x10];
3298 
3299 	u8         reserved_3[0xc];
3300 	u8         sm_sl[0x4];
3301 	u8         sm_lid[0x10];
3302 
3303 	u8         completion_address_63_32[0x20];
3304 
3305 	u8         completion_address_31_12[0x14];
3306 	u8         reserved_4[0x6];
3307 	u8         log_cq_size[0x6];
3308 
3309 	u8         working_buffer_address_63_32[0x20];
3310 
3311 	u8         working_buffer_address_31_12[0x14];
3312 	u8         reserved_5[0xc];
3313 
3314 	struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
3315 
3316 	u8         pkey_index[0x10];
3317 	u8         pkey[0x10];
3318 
3319 	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
3320 
3321 	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
3322 
3323 	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
3324 
3325 	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
3326 
3327 	u8         reserved_6[0x400];
3328 };
3329 
3330 union mlx5_ifc_event_auto_bits {
3331 	struct mlx5_ifc_comp_event_bits comp_event;
3332 	struct mlx5_ifc_dct_events_bits dct_events;
3333 	struct mlx5_ifc_qp_events_bits qp_events;
3334 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3335 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3336 	struct mlx5_ifc_cq_error_bits cq_error;
3337 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3338 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3339 	struct mlx5_ifc_gpio_event_bits gpio_event;
3340 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3341 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3342 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3343 	struct mlx5_ifc_pages_req_event_bits pages_req_event;
3344 	struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
3345 	u8         reserved_0[0xe0];
3346 };
3347 
3348 struct mlx5_ifc_health_buffer_bits {
3349 	u8         reserved_0[0x100];
3350 
3351 	u8         assert_existptr[0x20];
3352 
3353 	u8         assert_callra[0x20];
3354 
3355 	u8         reserved_1[0x40];
3356 
3357 	u8         fw_version[0x20];
3358 
3359 	u8         hw_id[0x20];
3360 
3361 	u8         reserved_2[0x20];
3362 
3363 	u8         irisc_index[0x8];
3364 	u8         synd[0x8];
3365 	u8         ext_synd[0x10];
3366 };
3367 
3368 struct mlx5_ifc_register_loopback_control_bits {
3369 	u8         no_lb[0x1];
3370 	u8         reserved_0[0x7];
3371 	u8         port[0x8];
3372 	u8         reserved_1[0x10];
3373 
3374 	u8         reserved_2[0x60];
3375 };
3376 
3377 struct mlx5_ifc_lrh_bits {
3378 	u8	vl[4];
3379 	u8	lver[4];
3380 	u8	sl[4];
3381 	u8	reserved2[2];
3382 	u8	lnh[2];
3383 	u8	dlid[16];
3384 	u8	reserved5[5];
3385 	u8	pkt_len[11];
3386 	u8	slid[16];
3387 };
3388 
3389 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
3390 	u8         reserved_0[0x40];
3391 
3392 	u8         reserved_1[0x10];
3393 	u8         rol_mode[0x8];
3394 	u8         wol_mode[0x8];
3395 };
3396 
3397 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3398 	u8         reserved_0[0x40];
3399 
3400 	u8         rol_mode_valid[0x1];
3401 	u8         wol_mode_valid[0x1];
3402 	u8         reserved_1[0xe];
3403 	u8         rol_mode[0x8];
3404 	u8         wol_mode[0x8];
3405 
3406 	u8         reserved_2[0x7a0];
3407 };
3408 
3409 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3410 	u8         virtual_mac_en[0x1];
3411 	u8         mac_aux_v[0x1];
3412 	u8         reserved_0[0x1e];
3413 
3414 	u8         reserved_1[0x40];
3415 
3416 	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3417 
3418 	u8         reserved_2[0x760];
3419 };
3420 
3421 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3422 	u8         virtual_mac_en[0x1];
3423 	u8         mac_aux_v[0x1];
3424 	u8         reserved_0[0x1e];
3425 
3426 	struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3427 
3428 	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3429 
3430 	u8         reserved_1[0x760];
3431 };
3432 
3433 struct mlx5_ifc_icmd_query_fw_info_out_bits {
3434 	struct mlx5_ifc_fw_version_bits fw_version;
3435 
3436 	u8         reserved_0[0x10];
3437 	u8         hash_signature[0x10];
3438 
3439 	u8         psid[16][0x8];
3440 
3441 	u8         reserved_1[0x6e0];
3442 };
3443 
3444 struct mlx5_ifc_icmd_query_cap_in_bits {
3445 	u8         reserved_0[0x10];
3446 	u8         capability_group[0x10];
3447 };
3448 
3449 struct mlx5_ifc_icmd_query_cap_general_bits {
3450 	u8         nv_access[0x1];
3451 	u8         fw_info_psid[0x1];
3452 	u8         reserved_0[0x1e];
3453 
3454 	u8         reserved_1[0x16];
3455 	u8         rol_s[0x1];
3456 	u8         rol_g[0x1];
3457 	u8         reserved_2[0x1];
3458 	u8         wol_s[0x1];
3459 	u8         wol_g[0x1];
3460 	u8         wol_a[0x1];
3461 	u8         wol_b[0x1];
3462 	u8         wol_m[0x1];
3463 	u8         wol_u[0x1];
3464 	u8         wol_p[0x1];
3465 };
3466 
3467 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3468 	u8         status[0x8];
3469 	u8         reserved_0[0x18];
3470 
3471 	u8         reserved_1[0x7e0];
3472 };
3473 
3474 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3475 	u8         status[0x8];
3476 	u8         reserved_0[0x18];
3477 
3478 	u8         reserved_1[0x7e0];
3479 };
3480 
3481 struct mlx5_ifc_icmd_ocbb_init_in_bits {
3482 	u8         address_hi[0x20];
3483 
3484 	u8         address_lo[0x20];
3485 
3486 	u8         reserved_0[0x7c0];
3487 };
3488 
3489 struct mlx5_ifc_icmd_init_ocsd_in_bits {
3490 	u8         reserved_0[0x20];
3491 
3492 	u8         address_hi[0x20];
3493 
3494 	u8         address_lo[0x20];
3495 
3496 	u8         reserved_1[0x7a0];
3497 };
3498 
3499 struct mlx5_ifc_icmd_access_reg_out_bits {
3500 	u8         reserved_0[0x11];
3501 	u8         status[0x7];
3502 	u8         reserved_1[0x8];
3503 
3504 	u8         register_id[0x10];
3505 	u8         reserved_2[0x10];
3506 
3507 	u8         reserved_3[0x40];
3508 
3509 	u8         reserved_4[0x5];
3510 	u8         len[0xb];
3511 	u8         reserved_5[0x10];
3512 
3513 	u8         register_data[0][0x20];
3514 };
3515 
3516 enum {
3517 	MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
3518 	MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
3519 };
3520 
3521 struct mlx5_ifc_icmd_access_reg_in_bits {
3522 	u8         constant_1[0x5];
3523 	u8         constant_2[0xb];
3524 	u8         reserved_0[0x10];
3525 
3526 	u8         register_id[0x10];
3527 	u8         reserved_1[0x1];
3528 	u8         method[0x7];
3529 	u8         constant_3[0x8];
3530 
3531 	u8         reserved_2[0x40];
3532 
3533 	u8         constant_4[0x5];
3534 	u8         len[0xb];
3535 	u8         reserved_3[0x10];
3536 
3537 	u8         register_data[0][0x20];
3538 };
3539 
3540 enum {
3541 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3542 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3543 };
3544 
3545 struct mlx5_ifc_teardown_hca_out_bits {
3546 	u8         status[0x8];
3547 	u8         reserved_0[0x18];
3548 
3549 	u8         syndrome[0x20];
3550 
3551 	u8         reserved_1[0x3f];
3552 
3553 	u8	   state[0x1];
3554 };
3555 
3556 enum {
3557 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3558 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3559 	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3560 };
3561 
3562 struct mlx5_ifc_teardown_hca_in_bits {
3563 	u8         opcode[0x10];
3564 	u8         reserved_0[0x10];
3565 
3566 	u8         reserved_1[0x10];
3567 	u8         op_mod[0x10];
3568 
3569 	u8         reserved_2[0x10];
3570 	u8         profile[0x10];
3571 
3572 	u8         reserved_3[0x20];
3573 };
3574 
3575 struct mlx5_ifc_set_delay_drop_params_out_bits {
3576 	u8         status[0x8];
3577 	u8         reserved_at_8[0x18];
3578 
3579 	u8         syndrome[0x20];
3580 
3581 	u8         reserved_at_40[0x40];
3582 };
3583 
3584 struct mlx5_ifc_set_delay_drop_params_in_bits {
3585 	u8         opcode[0x10];
3586 	u8         reserved_at_10[0x10];
3587 
3588 	u8         reserved_at_20[0x10];
3589 	u8         op_mod[0x10];
3590 
3591 	u8         reserved_at_40[0x20];
3592 
3593 	u8         reserved_at_60[0x10];
3594 	u8         delay_drop_timeout[0x10];
3595 };
3596 
3597 struct mlx5_ifc_query_delay_drop_params_out_bits {
3598 	u8         status[0x8];
3599 	u8         reserved_at_8[0x18];
3600 
3601 	u8         syndrome[0x20];
3602 
3603 	u8         reserved_at_40[0x20];
3604 
3605 	u8         reserved_at_60[0x10];
3606 	u8         delay_drop_timeout[0x10];
3607 };
3608 
3609 struct mlx5_ifc_query_delay_drop_params_in_bits {
3610 	u8         opcode[0x10];
3611 	u8         reserved_at_10[0x10];
3612 
3613 	u8         reserved_at_20[0x10];
3614 	u8         op_mod[0x10];
3615 
3616 	u8         reserved_at_40[0x40];
3617 };
3618 
3619 struct mlx5_ifc_suspend_qp_out_bits {
3620 	u8         status[0x8];
3621 	u8         reserved_0[0x18];
3622 
3623 	u8         syndrome[0x20];
3624 
3625 	u8         reserved_1[0x40];
3626 };
3627 
3628 struct mlx5_ifc_suspend_qp_in_bits {
3629 	u8         opcode[0x10];
3630 	u8         reserved_0[0x10];
3631 
3632 	u8         reserved_1[0x10];
3633 	u8         op_mod[0x10];
3634 
3635 	u8         reserved_2[0x8];
3636 	u8         qpn[0x18];
3637 
3638 	u8         reserved_3[0x20];
3639 };
3640 
3641 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3642 	u8         status[0x8];
3643 	u8         reserved_0[0x18];
3644 
3645 	u8         syndrome[0x20];
3646 
3647 	u8         reserved_1[0x40];
3648 };
3649 
3650 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3651 	u8         opcode[0x10];
3652 	u8         uid[0x10];
3653 
3654 	u8         reserved_1[0x10];
3655 	u8         op_mod[0x10];
3656 
3657 	u8         reserved_2[0x8];
3658 	u8         qpn[0x18];
3659 
3660 	u8         reserved_3[0x20];
3661 
3662 	u8         opt_param_mask[0x20];
3663 
3664 	u8         reserved_4[0x20];
3665 
3666 	struct mlx5_ifc_qpc_bits qpc;
3667 
3668 	u8         reserved_5[0x80];
3669 };
3670 
3671 struct mlx5_ifc_sqd2rts_qp_out_bits {
3672 	u8         status[0x8];
3673 	u8         reserved_0[0x18];
3674 
3675 	u8         syndrome[0x20];
3676 
3677 	u8         reserved_1[0x40];
3678 };
3679 
3680 struct mlx5_ifc_sqd2rts_qp_in_bits {
3681 	u8         opcode[0x10];
3682 	u8         uid[0x10];
3683 
3684 	u8         reserved_1[0x10];
3685 	u8         op_mod[0x10];
3686 
3687 	u8         reserved_2[0x8];
3688 	u8         qpn[0x18];
3689 
3690 	u8         reserved_3[0x20];
3691 
3692 	u8         opt_param_mask[0x20];
3693 
3694 	u8         reserved_4[0x20];
3695 
3696 	struct mlx5_ifc_qpc_bits qpc;
3697 
3698 	u8         reserved_5[0x80];
3699 };
3700 
3701 struct mlx5_ifc_set_wol_rol_out_bits {
3702 	u8         status[0x8];
3703 	u8         reserved_0[0x18];
3704 
3705 	u8         syndrome[0x20];
3706 
3707 	u8         reserved_1[0x40];
3708 };
3709 
3710 struct mlx5_ifc_set_wol_rol_in_bits {
3711 	u8         opcode[0x10];
3712 	u8         reserved_0[0x10];
3713 
3714 	u8         reserved_1[0x10];
3715 	u8         op_mod[0x10];
3716 
3717 	u8         rol_mode_valid[0x1];
3718 	u8         wol_mode_valid[0x1];
3719 	u8         reserved_2[0xe];
3720 	u8         rol_mode[0x8];
3721 	u8         wol_mode[0x8];
3722 
3723 	u8         reserved_3[0x20];
3724 };
3725 
3726 struct mlx5_ifc_set_roce_address_out_bits {
3727 	u8         status[0x8];
3728 	u8         reserved_0[0x18];
3729 
3730 	u8         syndrome[0x20];
3731 
3732 	u8         reserved_1[0x40];
3733 };
3734 
3735 struct mlx5_ifc_set_roce_address_in_bits {
3736 	u8         opcode[0x10];
3737 	u8         reserved_0[0x10];
3738 
3739 	u8         reserved_1[0x10];
3740 	u8         op_mod[0x10];
3741 
3742 	u8         roce_address_index[0x10];
3743 	u8         reserved_2[0x10];
3744 
3745 	u8         reserved_3[0x20];
3746 
3747 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
3748 };
3749 
3750 struct mlx5_ifc_set_rdb_out_bits {
3751 	u8         status[0x8];
3752 	u8         reserved_0[0x18];
3753 
3754 	u8         syndrome[0x20];
3755 
3756 	u8         reserved_1[0x40];
3757 };
3758 
3759 struct mlx5_ifc_set_rdb_in_bits {
3760 	u8         opcode[0x10];
3761 	u8         reserved_0[0x10];
3762 
3763 	u8         reserved_1[0x10];
3764 	u8         op_mod[0x10];
3765 
3766 	u8         reserved_2[0x8];
3767 	u8         qpn[0x18];
3768 
3769 	u8         reserved_3[0x18];
3770 	u8         rdb_list_size[0x8];
3771 
3772 	struct mlx5_ifc_rdbc_bits rdb_context[0];
3773 };
3774 
3775 struct mlx5_ifc_set_mad_demux_out_bits {
3776 	u8         status[0x8];
3777 	u8         reserved_0[0x18];
3778 
3779 	u8         syndrome[0x20];
3780 
3781 	u8         reserved_1[0x40];
3782 };
3783 
3784 enum {
3785 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3786 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3787 };
3788 
3789 struct mlx5_ifc_set_mad_demux_in_bits {
3790 	u8         opcode[0x10];
3791 	u8         reserved_0[0x10];
3792 
3793 	u8         reserved_1[0x10];
3794 	u8         op_mod[0x10];
3795 
3796 	u8         reserved_2[0x20];
3797 
3798 	u8         reserved_3[0x6];
3799 	u8         demux_mode[0x2];
3800 	u8         reserved_4[0x18];
3801 };
3802 
3803 struct mlx5_ifc_set_l2_table_entry_out_bits {
3804 	u8         status[0x8];
3805 	u8         reserved_0[0x18];
3806 
3807 	u8         syndrome[0x20];
3808 
3809 	u8         reserved_1[0x40];
3810 };
3811 
3812 struct mlx5_ifc_set_l2_table_entry_in_bits {
3813 	u8         opcode[0x10];
3814 	u8         reserved_0[0x10];
3815 
3816 	u8         reserved_1[0x10];
3817 	u8         op_mod[0x10];
3818 
3819 	u8         reserved_2[0x60];
3820 
3821 	u8         reserved_3[0x8];
3822 	u8         table_index[0x18];
3823 
3824 	u8         reserved_4[0x20];
3825 
3826 	u8         reserved_5[0x13];
3827 	u8         vlan_valid[0x1];
3828 	u8         vlan[0xc];
3829 
3830 	struct mlx5_ifc_mac_address_layout_bits mac_address;
3831 
3832 	u8         reserved_6[0xc0];
3833 };
3834 
3835 struct mlx5_ifc_set_issi_out_bits {
3836 	u8         status[0x8];
3837 	u8         reserved_0[0x18];
3838 
3839 	u8         syndrome[0x20];
3840 
3841 	u8         reserved_1[0x40];
3842 };
3843 
3844 struct mlx5_ifc_set_issi_in_bits {
3845 	u8         opcode[0x10];
3846 	u8         reserved_0[0x10];
3847 
3848 	u8         reserved_1[0x10];
3849 	u8         op_mod[0x10];
3850 
3851 	u8         reserved_2[0x10];
3852 	u8         current_issi[0x10];
3853 
3854 	u8         reserved_3[0x20];
3855 };
3856 
3857 struct mlx5_ifc_set_hca_cap_out_bits {
3858 	u8         status[0x8];
3859 	u8         reserved_0[0x18];
3860 
3861 	u8         syndrome[0x20];
3862 
3863 	u8         reserved_1[0x40];
3864 };
3865 
3866 struct mlx5_ifc_set_hca_cap_in_bits {
3867 	u8         opcode[0x10];
3868 	u8         reserved_0[0x10];
3869 
3870 	u8         reserved_1[0x10];
3871 	u8         op_mod[0x10];
3872 
3873 	u8         reserved_2[0x40];
3874 
3875 	union mlx5_ifc_hca_cap_union_bits capability;
3876 };
3877 
3878 enum {
3879 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION			= 0x0,
3880 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG		= 0x1,
3881 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST	= 0x2,
3882 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS		= 0x3
3883 };
3884 
3885 struct mlx5_ifc_set_flow_table_root_out_bits {
3886 	u8         status[0x8];
3887 	u8         reserved_0[0x18];
3888 
3889 	u8         syndrome[0x20];
3890 
3891 	u8         reserved_1[0x40];
3892 };
3893 
3894 struct mlx5_ifc_set_flow_table_root_in_bits {
3895 	u8         opcode[0x10];
3896 	u8         reserved_0[0x10];
3897 
3898 	u8         reserved_1[0x10];
3899 	u8         op_mod[0x10];
3900 
3901 	u8         other_vport[0x1];
3902 	u8         reserved_2[0xf];
3903 	u8         vport_number[0x10];
3904 
3905 	u8         reserved_3[0x20];
3906 
3907 	u8         table_type[0x8];
3908 	u8         reserved_4[0x18];
3909 
3910 	u8         reserved_5[0x8];
3911 	u8         table_id[0x18];
3912 
3913 	u8         reserved_6[0x8];
3914 	u8         underlay_qpn[0x18];
3915 
3916 	u8         reserved_7[0x120];
3917 };
3918 
3919 struct mlx5_ifc_set_fte_out_bits {
3920 	u8         status[0x8];
3921 	u8         reserved_0[0x18];
3922 
3923 	u8         syndrome[0x20];
3924 
3925 	u8         reserved_1[0x40];
3926 };
3927 
3928 struct mlx5_ifc_set_fte_in_bits {
3929 	u8         opcode[0x10];
3930 	u8         reserved_0[0x10];
3931 
3932 	u8         reserved_1[0x10];
3933 	u8         op_mod[0x10];
3934 
3935 	u8         other_vport[0x1];
3936 	u8         reserved_2[0xf];
3937 	u8         vport_number[0x10];
3938 
3939 	u8         reserved_3[0x20];
3940 
3941 	u8         table_type[0x8];
3942 	u8         reserved_4[0x18];
3943 
3944 	u8         reserved_5[0x8];
3945 	u8         table_id[0x18];
3946 
3947 	u8         reserved_6[0x18];
3948 	u8         modify_enable_mask[0x8];
3949 
3950 	u8         reserved_7[0x20];
3951 
3952 	u8         flow_index[0x20];
3953 
3954 	u8         reserved_8[0xe0];
3955 
3956 	struct mlx5_ifc_flow_context_bits flow_context;
3957 };
3958 
3959 struct mlx5_ifc_set_driver_version_out_bits {
3960 	u8         status[0x8];
3961 	u8         reserved_0[0x18];
3962 
3963 	u8         syndrome[0x20];
3964 
3965 	u8         reserved_1[0x40];
3966 };
3967 
3968 struct mlx5_ifc_set_driver_version_in_bits {
3969 	u8         opcode[0x10];
3970 	u8         reserved_0[0x10];
3971 
3972 	u8         reserved_1[0x10];
3973 	u8         op_mod[0x10];
3974 
3975 	u8         reserved_2[0x40];
3976 
3977 	u8         driver_version[64][0x8];
3978 };
3979 
3980 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3981 	u8         status[0x8];
3982 	u8         reserved_0[0x18];
3983 
3984 	u8         syndrome[0x20];
3985 
3986 	u8         reserved_1[0x40];
3987 };
3988 
3989 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3990 	u8         opcode[0x10];
3991 	u8         reserved_0[0x10];
3992 
3993 	u8         reserved_1[0x10];
3994 	u8         op_mod[0x10];
3995 
3996 	u8         enable[0x1];
3997 	u8         reserved_2[0x1f];
3998 
3999 	u8         reserved_3[0x160];
4000 
4001 	struct mlx5_ifc_cmd_pas_bits pas;
4002 };
4003 
4004 struct mlx5_ifc_set_burst_size_out_bits {
4005 	u8         status[0x8];
4006 	u8         reserved_0[0x18];
4007 
4008 	u8         syndrome[0x20];
4009 
4010 	u8         reserved_1[0x40];
4011 };
4012 
4013 struct mlx5_ifc_set_burst_size_in_bits {
4014 	u8         opcode[0x10];
4015 	u8         reserved_0[0x10];
4016 
4017 	u8         reserved_1[0x10];
4018 	u8         op_mod[0x10];
4019 
4020 	u8         reserved_2[0x20];
4021 
4022 	u8         reserved_3[0x9];
4023 	u8         device_burst_size[0x17];
4024 };
4025 
4026 struct mlx5_ifc_rts2rts_qp_out_bits {
4027 	u8         status[0x8];
4028 	u8         reserved_0[0x18];
4029 
4030 	u8         syndrome[0x20];
4031 
4032 	u8         reserved_1[0x40];
4033 };
4034 
4035 struct mlx5_ifc_rts2rts_qp_in_bits {
4036 	u8         opcode[0x10];
4037 	u8         uid[0x10];
4038 
4039 	u8         reserved_1[0x10];
4040 	u8         op_mod[0x10];
4041 
4042 	u8         reserved_2[0x8];
4043 	u8         qpn[0x18];
4044 
4045 	u8         reserved_3[0x20];
4046 
4047 	u8         opt_param_mask[0x20];
4048 
4049 	u8         reserved_4[0x20];
4050 
4051 	struct mlx5_ifc_qpc_bits qpc;
4052 
4053 	u8         reserved_5[0x80];
4054 };
4055 
4056 struct mlx5_ifc_rtr2rts_qp_out_bits {
4057 	u8         status[0x8];
4058 	u8         reserved_0[0x18];
4059 
4060 	u8         syndrome[0x20];
4061 
4062 	u8         reserved_1[0x40];
4063 };
4064 
4065 struct mlx5_ifc_rtr2rts_qp_in_bits {
4066 	u8         opcode[0x10];
4067 	u8         uid[0x10];
4068 
4069 	u8         reserved_1[0x10];
4070 	u8         op_mod[0x10];
4071 
4072 	u8         reserved_2[0x8];
4073 	u8         qpn[0x18];
4074 
4075 	u8         reserved_3[0x20];
4076 
4077 	u8         opt_param_mask[0x20];
4078 
4079 	u8         reserved_4[0x20];
4080 
4081 	struct mlx5_ifc_qpc_bits qpc;
4082 
4083 	u8         reserved_5[0x80];
4084 };
4085 
4086 struct mlx5_ifc_rst2init_qp_out_bits {
4087 	u8         status[0x8];
4088 	u8         reserved_0[0x18];
4089 
4090 	u8         syndrome[0x20];
4091 
4092 	u8         reserved_1[0x40];
4093 };
4094 
4095 struct mlx5_ifc_rst2init_qp_in_bits {
4096 	u8         opcode[0x10];
4097 	u8         uid[0x10];
4098 
4099 	u8         reserved_1[0x10];
4100 	u8         op_mod[0x10];
4101 
4102 	u8         reserved_2[0x8];
4103 	u8         qpn[0x18];
4104 
4105 	u8         reserved_3[0x20];
4106 
4107 	u8         opt_param_mask[0x20];
4108 
4109 	u8         reserved_4[0x20];
4110 
4111 	struct mlx5_ifc_qpc_bits qpc;
4112 
4113 	u8         reserved_5[0x80];
4114 };
4115 
4116 struct mlx5_ifc_query_xrq_out_bits {
4117 	u8         status[0x8];
4118 	u8         reserved_at_8[0x18];
4119 
4120 	u8         syndrome[0x20];
4121 
4122 	u8         reserved_at_40[0x40];
4123 
4124 	struct mlx5_ifc_xrqc_bits xrq_context;
4125 };
4126 
4127 struct mlx5_ifc_query_xrq_in_bits {
4128 	u8         opcode[0x10];
4129 	u8         reserved_at_10[0x10];
4130 
4131 	u8         reserved_at_20[0x10];
4132 	u8         op_mod[0x10];
4133 
4134 	u8         reserved_at_40[0x8];
4135 	u8         xrqn[0x18];
4136 
4137 	u8         reserved_at_60[0x20];
4138 };
4139 
4140 struct mlx5_ifc_resume_qp_out_bits {
4141 	u8         status[0x8];
4142 	u8         reserved_0[0x18];
4143 
4144 	u8         syndrome[0x20];
4145 
4146 	u8         reserved_1[0x40];
4147 };
4148 
4149 struct mlx5_ifc_resume_qp_in_bits {
4150 	u8         opcode[0x10];
4151 	u8         reserved_0[0x10];
4152 
4153 	u8         reserved_1[0x10];
4154 	u8         op_mod[0x10];
4155 
4156 	u8         reserved_2[0x8];
4157 	u8         qpn[0x18];
4158 
4159 	u8         reserved_3[0x20];
4160 };
4161 
4162 struct mlx5_ifc_query_xrc_srq_out_bits {
4163 	u8         status[0x8];
4164 	u8         reserved_0[0x18];
4165 
4166 	u8         syndrome[0x20];
4167 
4168 	u8         reserved_1[0x40];
4169 
4170 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4171 
4172 	u8         reserved_2[0x600];
4173 
4174 	u8         pas[0][0x40];
4175 };
4176 
4177 struct mlx5_ifc_query_xrc_srq_in_bits {
4178 	u8         opcode[0x10];
4179 	u8         uid[0x10];
4180 
4181 	u8         reserved_1[0x10];
4182 	u8         op_mod[0x10];
4183 
4184 	u8         reserved_2[0x8];
4185 	u8         xrc_srqn[0x18];
4186 
4187 	u8         reserved_3[0x20];
4188 };
4189 
4190 struct mlx5_ifc_query_wol_rol_out_bits {
4191 	u8         status[0x8];
4192 	u8         reserved_0[0x18];
4193 
4194 	u8         syndrome[0x20];
4195 
4196 	u8         reserved_1[0x10];
4197 	u8         rol_mode[0x8];
4198 	u8         wol_mode[0x8];
4199 
4200 	u8         reserved_2[0x20];
4201 };
4202 
4203 struct mlx5_ifc_query_wol_rol_in_bits {
4204 	u8         opcode[0x10];
4205 	u8         reserved_0[0x10];
4206 
4207 	u8         reserved_1[0x10];
4208 	u8         op_mod[0x10];
4209 
4210 	u8         reserved_2[0x40];
4211 };
4212 
4213 enum {
4214 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4215 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4216 };
4217 
4218 struct mlx5_ifc_query_vport_state_out_bits {
4219 	u8         status[0x8];
4220 	u8         reserved_0[0x18];
4221 
4222 	u8         syndrome[0x20];
4223 
4224 	u8         reserved_1[0x20];
4225 
4226 	u8         reserved_2[0x18];
4227 	u8         admin_state[0x4];
4228 	u8         state[0x4];
4229 };
4230 
4231 enum {
4232 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
4233 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
4234 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
4235 };
4236 
4237 struct mlx5_ifc_query_vport_state_in_bits {
4238 	u8         opcode[0x10];
4239 	u8         reserved_0[0x10];
4240 
4241 	u8         reserved_1[0x10];
4242 	u8         op_mod[0x10];
4243 
4244 	u8         other_vport[0x1];
4245 	u8         reserved_2[0xf];
4246 	u8         vport_number[0x10];
4247 
4248 	u8         reserved_3[0x20];
4249 };
4250 
4251 struct mlx5_ifc_query_vnic_env_out_bits {
4252 	u8         status[0x8];
4253 	u8         reserved_at_8[0x18];
4254 
4255 	u8         syndrome[0x20];
4256 
4257 	u8         reserved_at_40[0x40];
4258 
4259 	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4260 };
4261 
4262 enum {
4263 	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4264 };
4265 
4266 struct mlx5_ifc_query_vnic_env_in_bits {
4267 	u8         opcode[0x10];
4268 	u8         reserved_at_10[0x10];
4269 
4270 	u8         reserved_at_20[0x10];
4271 	u8         op_mod[0x10];
4272 
4273 	u8         other_vport[0x1];
4274 	u8         reserved_at_41[0xf];
4275 	u8         vport_number[0x10];
4276 
4277 	u8         reserved_at_60[0x20];
4278 };
4279 
4280 struct mlx5_ifc_query_vport_counter_out_bits {
4281 	u8         status[0x8];
4282 	u8         reserved_0[0x18];
4283 
4284 	u8         syndrome[0x20];
4285 
4286 	u8         reserved_1[0x40];
4287 
4288 	struct mlx5_ifc_traffic_counter_bits received_errors;
4289 
4290 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
4291 
4292 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4293 
4294 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4295 
4296 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4297 
4298 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4299 
4300 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4301 
4302 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4303 
4304 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4305 
4306 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4307 
4308 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4309 
4310 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4311 
4312 	u8         reserved_2[0xa00];
4313 };
4314 
4315 enum {
4316 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4317 };
4318 
4319 struct mlx5_ifc_query_vport_counter_in_bits {
4320 	u8         opcode[0x10];
4321 	u8         reserved_0[0x10];
4322 
4323 	u8         reserved_1[0x10];
4324 	u8         op_mod[0x10];
4325 
4326 	u8         other_vport[0x1];
4327 	u8         reserved_2[0xb];
4328 	u8         port_num[0x4];
4329 	u8         vport_number[0x10];
4330 
4331 	u8         reserved_3[0x60];
4332 
4333 	u8         clear[0x1];
4334 	u8         reserved_4[0x1f];
4335 
4336 	u8         reserved_5[0x20];
4337 };
4338 
4339 struct mlx5_ifc_query_tis_out_bits {
4340 	u8         status[0x8];
4341 	u8         reserved_0[0x18];
4342 
4343 	u8         syndrome[0x20];
4344 
4345 	u8         reserved_1[0x40];
4346 
4347 	struct mlx5_ifc_tisc_bits tis_context;
4348 };
4349 
4350 struct mlx5_ifc_query_tis_in_bits {
4351 	u8         opcode[0x10];
4352 	u8         reserved_0[0x10];
4353 
4354 	u8         reserved_1[0x10];
4355 	u8         op_mod[0x10];
4356 
4357 	u8         reserved_2[0x8];
4358 	u8         tisn[0x18];
4359 
4360 	u8         reserved_3[0x20];
4361 };
4362 
4363 struct mlx5_ifc_query_tir_out_bits {
4364 	u8         status[0x8];
4365 	u8         reserved_0[0x18];
4366 
4367 	u8         syndrome[0x20];
4368 
4369 	u8         reserved_1[0xc0];
4370 
4371 	struct mlx5_ifc_tirc_bits tir_context;
4372 };
4373 
4374 struct mlx5_ifc_query_tir_in_bits {
4375 	u8         opcode[0x10];
4376 	u8         reserved_0[0x10];
4377 
4378 	u8         reserved_1[0x10];
4379 	u8         op_mod[0x10];
4380 
4381 	u8         reserved_2[0x8];
4382 	u8         tirn[0x18];
4383 
4384 	u8         reserved_3[0x20];
4385 };
4386 
4387 struct mlx5_ifc_query_srq_out_bits {
4388 	u8         status[0x8];
4389 	u8         reserved_0[0x18];
4390 
4391 	u8         syndrome[0x20];
4392 
4393 	u8         reserved_1[0x40];
4394 
4395 	struct mlx5_ifc_srqc_bits srq_context_entry;
4396 
4397 	u8         reserved_2[0x600];
4398 
4399 	u8         pas[0][0x40];
4400 };
4401 
4402 struct mlx5_ifc_query_srq_in_bits {
4403 	u8         opcode[0x10];
4404 	u8         reserved_0[0x10];
4405 
4406 	u8         reserved_1[0x10];
4407 	u8         op_mod[0x10];
4408 
4409 	u8         reserved_2[0x8];
4410 	u8         srqn[0x18];
4411 
4412 	u8         reserved_3[0x20];
4413 };
4414 
4415 struct mlx5_ifc_query_sq_out_bits {
4416 	u8         status[0x8];
4417 	u8         reserved_0[0x18];
4418 
4419 	u8         syndrome[0x20];
4420 
4421 	u8         reserved_1[0xc0];
4422 
4423 	struct mlx5_ifc_sqc_bits sq_context;
4424 };
4425 
4426 struct mlx5_ifc_query_sq_in_bits {
4427 	u8         opcode[0x10];
4428 	u8         reserved_0[0x10];
4429 
4430 	u8         reserved_1[0x10];
4431 	u8         op_mod[0x10];
4432 
4433 	u8         reserved_2[0x8];
4434 	u8         sqn[0x18];
4435 
4436 	u8         reserved_3[0x20];
4437 };
4438 
4439 struct mlx5_ifc_query_special_contexts_out_bits {
4440 	u8         status[0x8];
4441 	u8         reserved_0[0x18];
4442 
4443 	u8         syndrome[0x20];
4444 
4445 	u8	   dump_fill_mkey[0x20];
4446 
4447 	u8         resd_lkey[0x20];
4448 };
4449 
4450 struct mlx5_ifc_query_special_contexts_in_bits {
4451 	u8         opcode[0x10];
4452 	u8         reserved_0[0x10];
4453 
4454 	u8         reserved_1[0x10];
4455 	u8         op_mod[0x10];
4456 
4457 	u8         reserved_2[0x40];
4458 };
4459 
4460 struct mlx5_ifc_query_scheduling_element_out_bits {
4461 	u8         status[0x8];
4462 	u8         reserved_at_8[0x18];
4463 
4464 	u8         syndrome[0x20];
4465 
4466 	u8         reserved_at_40[0xc0];
4467 
4468 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
4469 
4470 	u8         reserved_at_300[0x100];
4471 };
4472 
4473 enum {
4474 	MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4475 };
4476 
4477 struct mlx5_ifc_query_scheduling_element_in_bits {
4478 	u8         opcode[0x10];
4479 	u8         reserved_at_10[0x10];
4480 
4481 	u8         reserved_at_20[0x10];
4482 	u8         op_mod[0x10];
4483 
4484 	u8         scheduling_hierarchy[0x8];
4485 	u8         reserved_at_48[0x18];
4486 
4487 	u8         scheduling_element_id[0x20];
4488 
4489 	u8         reserved_at_80[0x180];
4490 };
4491 
4492 struct mlx5_ifc_query_rqt_out_bits {
4493 	u8         status[0x8];
4494 	u8         reserved_0[0x18];
4495 
4496 	u8         syndrome[0x20];
4497 
4498 	u8         reserved_1[0xc0];
4499 
4500 	struct mlx5_ifc_rqtc_bits rqt_context;
4501 };
4502 
4503 struct mlx5_ifc_query_rqt_in_bits {
4504 	u8         opcode[0x10];
4505 	u8         reserved_0[0x10];
4506 
4507 	u8         reserved_1[0x10];
4508 	u8         op_mod[0x10];
4509 
4510 	u8         reserved_2[0x8];
4511 	u8         rqtn[0x18];
4512 
4513 	u8         reserved_3[0x20];
4514 };
4515 
4516 struct mlx5_ifc_query_rq_out_bits {
4517 	u8         status[0x8];
4518 	u8         reserved_0[0x18];
4519 
4520 	u8         syndrome[0x20];
4521 
4522 	u8         reserved_1[0xc0];
4523 
4524 	struct mlx5_ifc_rqc_bits rq_context;
4525 };
4526 
4527 struct mlx5_ifc_query_rq_in_bits {
4528 	u8         opcode[0x10];
4529 	u8         reserved_0[0x10];
4530 
4531 	u8         reserved_1[0x10];
4532 	u8         op_mod[0x10];
4533 
4534 	u8         reserved_2[0x8];
4535 	u8         rqn[0x18];
4536 
4537 	u8         reserved_3[0x20];
4538 };
4539 
4540 struct mlx5_ifc_query_roce_address_out_bits {
4541 	u8         status[0x8];
4542 	u8         reserved_0[0x18];
4543 
4544 	u8         syndrome[0x20];
4545 
4546 	u8         reserved_1[0x40];
4547 
4548 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4549 };
4550 
4551 struct mlx5_ifc_query_roce_address_in_bits {
4552 	u8         opcode[0x10];
4553 	u8         reserved_0[0x10];
4554 
4555 	u8         reserved_1[0x10];
4556 	u8         op_mod[0x10];
4557 
4558 	u8         roce_address_index[0x10];
4559 	u8         reserved_2[0x10];
4560 
4561 	u8         reserved_3[0x20];
4562 };
4563 
4564 struct mlx5_ifc_query_rmp_out_bits {
4565 	u8         status[0x8];
4566 	u8         reserved_0[0x18];
4567 
4568 	u8         syndrome[0x20];
4569 
4570 	u8         reserved_1[0xc0];
4571 
4572 	struct mlx5_ifc_rmpc_bits rmp_context;
4573 };
4574 
4575 struct mlx5_ifc_query_rmp_in_bits {
4576 	u8         opcode[0x10];
4577 	u8         reserved_0[0x10];
4578 
4579 	u8         reserved_1[0x10];
4580 	u8         op_mod[0x10];
4581 
4582 	u8         reserved_2[0x8];
4583 	u8         rmpn[0x18];
4584 
4585 	u8         reserved_3[0x20];
4586 };
4587 
4588 struct mlx5_ifc_query_rdb_out_bits {
4589 	u8         status[0x8];
4590 	u8         reserved_0[0x18];
4591 
4592 	u8         syndrome[0x20];
4593 
4594 	u8         reserved_1[0x20];
4595 
4596 	u8         reserved_2[0x18];
4597 	u8         rdb_list_size[0x8];
4598 
4599 	struct mlx5_ifc_rdbc_bits rdb_context[0];
4600 };
4601 
4602 struct mlx5_ifc_query_rdb_in_bits {
4603 	u8         opcode[0x10];
4604 	u8         reserved_0[0x10];
4605 
4606 	u8         reserved_1[0x10];
4607 	u8         op_mod[0x10];
4608 
4609 	u8         reserved_2[0x8];
4610 	u8         qpn[0x18];
4611 
4612 	u8         reserved_3[0x20];
4613 };
4614 
4615 struct mlx5_ifc_query_qp_out_bits {
4616 	u8         status[0x8];
4617 	u8         reserved_0[0x18];
4618 
4619 	u8         syndrome[0x20];
4620 
4621 	u8         reserved_1[0x40];
4622 
4623 	u8         opt_param_mask[0x20];
4624 
4625 	u8         reserved_2[0x20];
4626 
4627 	struct mlx5_ifc_qpc_bits qpc;
4628 
4629 	u8         reserved_3[0x80];
4630 
4631 	u8         pas[0][0x40];
4632 };
4633 
4634 struct mlx5_ifc_query_qp_in_bits {
4635 	u8         opcode[0x10];
4636 	u8         reserved_0[0x10];
4637 
4638 	u8         reserved_1[0x10];
4639 	u8         op_mod[0x10];
4640 
4641 	u8         reserved_2[0x8];
4642 	u8         qpn[0x18];
4643 
4644 	u8         reserved_3[0x20];
4645 };
4646 
4647 struct mlx5_ifc_query_q_counter_out_bits {
4648 	u8         status[0x8];
4649 	u8         reserved_0[0x18];
4650 
4651 	u8         syndrome[0x20];
4652 
4653 	u8         reserved_1[0x40];
4654 
4655 	u8         rx_write_requests[0x20];
4656 
4657 	u8         reserved_2[0x20];
4658 
4659 	u8         rx_read_requests[0x20];
4660 
4661 	u8         reserved_3[0x20];
4662 
4663 	u8         rx_atomic_requests[0x20];
4664 
4665 	u8         reserved_4[0x20];
4666 
4667 	u8         rx_dct_connect[0x20];
4668 
4669 	u8         reserved_5[0x20];
4670 
4671 	u8         out_of_buffer[0x20];
4672 
4673 	u8         reserved_7[0x20];
4674 
4675 	u8         out_of_sequence[0x20];
4676 
4677 	u8         reserved_8[0x20];
4678 
4679 	u8         duplicate_request[0x20];
4680 
4681 	u8         reserved_9[0x20];
4682 
4683 	u8         rnr_nak_retry_err[0x20];
4684 
4685 	u8         reserved_10[0x20];
4686 
4687 	u8         packet_seq_err[0x20];
4688 
4689 	u8         reserved_11[0x20];
4690 
4691 	u8         implied_nak_seq_err[0x20];
4692 
4693 	u8         reserved_12[0x20];
4694 
4695 	u8         local_ack_timeout_err[0x20];
4696 
4697 	u8         reserved_13[0x20];
4698 
4699 	u8         resp_rnr_nak[0x20];
4700 
4701 	u8         reserved_14[0x20];
4702 
4703 	u8         req_rnr_retries_exceeded[0x20];
4704 
4705 	u8         reserved_15[0x460];
4706 };
4707 
4708 struct mlx5_ifc_query_q_counter_in_bits {
4709 	u8         opcode[0x10];
4710 	u8         reserved_0[0x10];
4711 
4712 	u8         reserved_1[0x10];
4713 	u8         op_mod[0x10];
4714 
4715 	u8         reserved_2[0x80];
4716 
4717 	u8         clear[0x1];
4718 	u8         reserved_3[0x1f];
4719 
4720 	u8         reserved_4[0x18];
4721 	u8         counter_set_id[0x8];
4722 };
4723 
4724 struct mlx5_ifc_query_pages_out_bits {
4725 	u8         status[0x8];
4726 	u8         reserved_0[0x18];
4727 
4728 	u8         syndrome[0x20];
4729 
4730 	u8         reserved_1[0x10];
4731 	u8         function_id[0x10];
4732 
4733 	u8         num_pages[0x20];
4734 };
4735 
4736 enum {
4737 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES	  = 0x1,
4738 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES	  = 0x2,
4739 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4740 };
4741 
4742 struct mlx5_ifc_query_pages_in_bits {
4743 	u8         opcode[0x10];
4744 	u8         reserved_0[0x10];
4745 
4746 	u8         reserved_1[0x10];
4747 	u8         op_mod[0x10];
4748 
4749 	u8         reserved_2[0x10];
4750 	u8         function_id[0x10];
4751 
4752 	u8         reserved_3[0x20];
4753 };
4754 
4755 struct mlx5_ifc_query_nic_vport_context_out_bits {
4756 	u8         status[0x8];
4757 	u8         reserved_0[0x18];
4758 
4759 	u8         syndrome[0x20];
4760 
4761 	u8         reserved_1[0x40];
4762 
4763 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4764 };
4765 
4766 struct mlx5_ifc_query_nic_vport_context_in_bits {
4767 	u8         opcode[0x10];
4768 	u8         reserved_0[0x10];
4769 
4770 	u8         reserved_1[0x10];
4771 	u8         op_mod[0x10];
4772 
4773 	u8         other_vport[0x1];
4774 	u8         reserved_2[0xf];
4775 	u8         vport_number[0x10];
4776 
4777 	u8         reserved_3[0x5];
4778 	u8         allowed_list_type[0x3];
4779 	u8         reserved_4[0x18];
4780 };
4781 
4782 struct mlx5_ifc_query_mkey_out_bits {
4783 	u8         status[0x8];
4784 	u8         reserved_0[0x18];
4785 
4786 	u8         syndrome[0x20];
4787 
4788 	u8         reserved_1[0x40];
4789 
4790 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4791 
4792 	u8         reserved_2[0x600];
4793 
4794 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4795 
4796 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4797 };
4798 
4799 struct mlx5_ifc_query_mkey_in_bits {
4800 	u8         opcode[0x10];
4801 	u8         reserved_0[0x10];
4802 
4803 	u8         reserved_1[0x10];
4804 	u8         op_mod[0x10];
4805 
4806 	u8         reserved_2[0x8];
4807 	u8         mkey_index[0x18];
4808 
4809 	u8         pg_access[0x1];
4810 	u8         reserved_3[0x1f];
4811 };
4812 
4813 struct mlx5_ifc_query_mad_demux_out_bits {
4814 	u8         status[0x8];
4815 	u8         reserved_0[0x18];
4816 
4817 	u8         syndrome[0x20];
4818 
4819 	u8         reserved_1[0x40];
4820 
4821 	u8         mad_dumux_parameters_block[0x20];
4822 };
4823 
4824 struct mlx5_ifc_query_mad_demux_in_bits {
4825 	u8         opcode[0x10];
4826 	u8         reserved_0[0x10];
4827 
4828 	u8         reserved_1[0x10];
4829 	u8         op_mod[0x10];
4830 
4831 	u8         reserved_2[0x40];
4832 };
4833 
4834 struct mlx5_ifc_query_l2_table_entry_out_bits {
4835 	u8         status[0x8];
4836 	u8         reserved_0[0x18];
4837 
4838 	u8         syndrome[0x20];
4839 
4840 	u8         reserved_1[0xa0];
4841 
4842 	u8         reserved_2[0x13];
4843 	u8         vlan_valid[0x1];
4844 	u8         vlan[0xc];
4845 
4846 	struct mlx5_ifc_mac_address_layout_bits mac_address;
4847 
4848 	u8         reserved_3[0xc0];
4849 };
4850 
4851 struct mlx5_ifc_query_l2_table_entry_in_bits {
4852 	u8         opcode[0x10];
4853 	u8         reserved_0[0x10];
4854 
4855 	u8         reserved_1[0x10];
4856 	u8         op_mod[0x10];
4857 
4858 	u8         reserved_2[0x60];
4859 
4860 	u8         reserved_3[0x8];
4861 	u8         table_index[0x18];
4862 
4863 	u8         reserved_4[0x140];
4864 };
4865 
4866 struct mlx5_ifc_query_issi_out_bits {
4867 	u8         status[0x8];
4868 	u8         reserved_0[0x18];
4869 
4870 	u8         syndrome[0x20];
4871 
4872 	u8         reserved_1[0x10];
4873 	u8         current_issi[0x10];
4874 
4875 	u8         reserved_2[0xa0];
4876 
4877 	u8         supported_issi_reserved[76][0x8];
4878 	u8         supported_issi_dw0[0x20];
4879 };
4880 
4881 struct mlx5_ifc_query_issi_in_bits {
4882 	u8         opcode[0x10];
4883 	u8         reserved_0[0x10];
4884 
4885 	u8         reserved_1[0x10];
4886 	u8         op_mod[0x10];
4887 
4888 	u8         reserved_2[0x40];
4889 };
4890 
4891 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4892 	u8         status[0x8];
4893 	u8         reserved_0[0x18];
4894 
4895 	u8         syndrome[0x20];
4896 
4897 	u8         reserved_1[0x40];
4898 
4899 	struct mlx5_ifc_pkey_bits pkey[0];
4900 };
4901 
4902 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4903 	u8         opcode[0x10];
4904 	u8         reserved_0[0x10];
4905 
4906 	u8         reserved_1[0x10];
4907 	u8         op_mod[0x10];
4908 
4909 	u8         other_vport[0x1];
4910 	u8         reserved_2[0xb];
4911 	u8         port_num[0x4];
4912 	u8         vport_number[0x10];
4913 
4914 	u8         reserved_3[0x10];
4915 	u8         pkey_index[0x10];
4916 };
4917 
4918 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4919 	u8         status[0x8];
4920 	u8         reserved_0[0x18];
4921 
4922 	u8         syndrome[0x20];
4923 
4924 	u8         reserved_1[0x20];
4925 
4926 	u8         gids_num[0x10];
4927 	u8         reserved_2[0x10];
4928 
4929 	struct mlx5_ifc_array128_auto_bits gid[0];
4930 };
4931 
4932 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4933 	u8         opcode[0x10];
4934 	u8         reserved_0[0x10];
4935 
4936 	u8         reserved_1[0x10];
4937 	u8         op_mod[0x10];
4938 
4939 	u8         other_vport[0x1];
4940 	u8         reserved_2[0xb];
4941 	u8         port_num[0x4];
4942 	u8         vport_number[0x10];
4943 
4944 	u8         reserved_3[0x10];
4945 	u8         gid_index[0x10];
4946 };
4947 
4948 struct mlx5_ifc_query_hca_vport_context_out_bits {
4949 	u8         status[0x8];
4950 	u8         reserved_0[0x18];
4951 
4952 	u8         syndrome[0x20];
4953 
4954 	u8         reserved_1[0x40];
4955 
4956 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4957 };
4958 
4959 struct mlx5_ifc_query_hca_vport_context_in_bits {
4960 	u8         opcode[0x10];
4961 	u8         reserved_0[0x10];
4962 
4963 	u8         reserved_1[0x10];
4964 	u8         op_mod[0x10];
4965 
4966 	u8         other_vport[0x1];
4967 	u8         reserved_2[0xb];
4968 	u8         port_num[0x4];
4969 	u8         vport_number[0x10];
4970 
4971 	u8         reserved_3[0x20];
4972 };
4973 
4974 struct mlx5_ifc_query_hca_cap_out_bits {
4975 	u8         status[0x8];
4976 	u8         reserved_0[0x18];
4977 
4978 	u8         syndrome[0x20];
4979 
4980 	u8         reserved_1[0x40];
4981 
4982 	union mlx5_ifc_hca_cap_union_bits capability;
4983 };
4984 
4985 struct mlx5_ifc_query_hca_cap_in_bits {
4986 	u8         opcode[0x10];
4987 	u8         reserved_0[0x10];
4988 
4989 	u8         reserved_1[0x10];
4990 	u8         op_mod[0x10];
4991 
4992 	u8         reserved_2[0x40];
4993 };
4994 
4995 struct mlx5_ifc_query_flow_table_out_bits {
4996 	u8         status[0x8];
4997 	u8         reserved_at_8[0x18];
4998 
4999 	u8         syndrome[0x20];
5000 
5001 	u8         reserved_at_40[0x80];
5002 
5003 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
5004 };
5005 
5006 struct mlx5_ifc_query_flow_table_in_bits {
5007 	u8         opcode[0x10];
5008 	u8         reserved_0[0x10];
5009 
5010 	u8         reserved_1[0x10];
5011 	u8         op_mod[0x10];
5012 
5013 	u8         other_vport[0x1];
5014 	u8         reserved_2[0xf];
5015 	u8         vport_number[0x10];
5016 
5017 	u8         reserved_3[0x20];
5018 
5019 	u8         table_type[0x8];
5020 	u8         reserved_4[0x18];
5021 
5022 	u8         reserved_5[0x8];
5023 	u8         table_id[0x18];
5024 
5025 	u8         reserved_6[0x140];
5026 };
5027 
5028 struct mlx5_ifc_query_fte_out_bits {
5029 	u8         status[0x8];
5030 	u8         reserved_0[0x18];
5031 
5032 	u8         syndrome[0x20];
5033 
5034 	u8         reserved_1[0x1c0];
5035 
5036 	struct mlx5_ifc_flow_context_bits flow_context;
5037 };
5038 
5039 struct mlx5_ifc_query_fte_in_bits {
5040 	u8         opcode[0x10];
5041 	u8         reserved_0[0x10];
5042 
5043 	u8         reserved_1[0x10];
5044 	u8         op_mod[0x10];
5045 
5046 	u8         other_vport[0x1];
5047 	u8         reserved_2[0xf];
5048 	u8         vport_number[0x10];
5049 
5050 	u8         reserved_3[0x20];
5051 
5052 	u8         table_type[0x8];
5053 	u8         reserved_4[0x18];
5054 
5055 	u8         reserved_5[0x8];
5056 	u8         table_id[0x18];
5057 
5058 	u8         reserved_6[0x40];
5059 
5060 	u8         flow_index[0x20];
5061 
5062 	u8         reserved_7[0xe0];
5063 };
5064 
5065 enum {
5066 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5067 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5068 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5069 };
5070 
5071 struct mlx5_ifc_query_flow_group_out_bits {
5072 	u8         status[0x8];
5073 	u8         reserved_0[0x18];
5074 
5075 	u8         syndrome[0x20];
5076 
5077 	u8         reserved_1[0xa0];
5078 
5079 	u8         start_flow_index[0x20];
5080 
5081 	u8         reserved_2[0x20];
5082 
5083 	u8         end_flow_index[0x20];
5084 
5085 	u8         reserved_3[0xa0];
5086 
5087 	u8         reserved_4[0x18];
5088 	u8         match_criteria_enable[0x8];
5089 
5090 	struct mlx5_ifc_fte_match_param_bits match_criteria;
5091 
5092 	u8         reserved_5[0xe00];
5093 };
5094 
5095 struct mlx5_ifc_query_flow_group_in_bits {
5096 	u8         opcode[0x10];
5097 	u8         reserved_0[0x10];
5098 
5099 	u8         reserved_1[0x10];
5100 	u8         op_mod[0x10];
5101 
5102 	u8         other_vport[0x1];
5103 	u8         reserved_2[0xf];
5104 	u8         vport_number[0x10];
5105 
5106 	u8         reserved_3[0x20];
5107 
5108 	u8         table_type[0x8];
5109 	u8         reserved_4[0x18];
5110 
5111 	u8         reserved_5[0x8];
5112 	u8         table_id[0x18];
5113 
5114 	u8         group_id[0x20];
5115 
5116 	u8         reserved_6[0x120];
5117 };
5118 
5119 struct mlx5_ifc_query_flow_counter_out_bits {
5120 	u8         status[0x8];
5121 	u8         reserved_at_8[0x18];
5122 
5123 	u8         syndrome[0x20];
5124 
5125 	u8         reserved_at_40[0x40];
5126 
5127 	struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5128 };
5129 
5130 struct mlx5_ifc_query_flow_counter_in_bits {
5131 	u8         opcode[0x10];
5132 	u8         reserved_at_10[0x10];
5133 
5134 	u8         reserved_at_20[0x10];
5135 	u8         op_mod[0x10];
5136 
5137 	u8         reserved_at_40[0x80];
5138 
5139 	u8         clear[0x1];
5140 	u8         reserved_at_c1[0xf];
5141 	u8         num_of_counters[0x10];
5142 
5143 	u8         reserved_at_e0[0x10];
5144 	u8         flow_counter_id[0x10];
5145 };
5146 
5147 struct mlx5_ifc_query_esw_vport_context_out_bits {
5148 	u8         status[0x8];
5149 	u8         reserved_0[0x18];
5150 
5151 	u8         syndrome[0x20];
5152 
5153 	u8         reserved_1[0x40];
5154 
5155 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5156 };
5157 
5158 struct mlx5_ifc_query_esw_vport_context_in_bits {
5159 	u8         opcode[0x10];
5160 	u8         reserved_0[0x10];
5161 
5162 	u8         reserved_1[0x10];
5163 	u8         op_mod[0x10];
5164 
5165 	u8         other_vport[0x1];
5166 	u8         reserved_2[0xf];
5167 	u8         vport_number[0x10];
5168 
5169 	u8         reserved_3[0x20];
5170 };
5171 
5172 struct mlx5_ifc_query_eq_out_bits {
5173 	u8         status[0x8];
5174 	u8         reserved_0[0x18];
5175 
5176 	u8         syndrome[0x20];
5177 
5178 	u8         reserved_1[0x40];
5179 
5180 	struct mlx5_ifc_eqc_bits eq_context_entry;
5181 
5182 	u8         reserved_2[0x40];
5183 
5184 	u8         event_bitmask[0x40];
5185 
5186 	u8         reserved_3[0x580];
5187 
5188 	u8         pas[0][0x40];
5189 };
5190 
5191 struct mlx5_ifc_query_eq_in_bits {
5192 	u8         opcode[0x10];
5193 	u8         reserved_0[0x10];
5194 
5195 	u8         reserved_1[0x10];
5196 	u8         op_mod[0x10];
5197 
5198 	u8         reserved_2[0x18];
5199 	u8         eq_number[0x8];
5200 
5201 	u8         reserved_3[0x20];
5202 };
5203 
5204 struct mlx5_ifc_query_dct_out_bits {
5205 	u8         status[0x8];
5206 	u8         reserved_0[0x18];
5207 
5208 	u8         syndrome[0x20];
5209 
5210 	u8         reserved_1[0x40];
5211 
5212 	struct mlx5_ifc_dctc_bits dct_context_entry;
5213 
5214 	u8         reserved_2[0x180];
5215 };
5216 
5217 struct mlx5_ifc_query_dct_in_bits {
5218 	u8         opcode[0x10];
5219 	u8         reserved_0[0x10];
5220 
5221 	u8         reserved_1[0x10];
5222 	u8         op_mod[0x10];
5223 
5224 	u8         reserved_2[0x8];
5225 	u8         dctn[0x18];
5226 
5227 	u8         reserved_3[0x20];
5228 };
5229 
5230 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
5231 	u8         status[0x8];
5232 	u8         reserved_0[0x18];
5233 
5234 	u8         syndrome[0x20];
5235 
5236 	u8         enable[0x1];
5237 	u8         reserved_1[0x1f];
5238 
5239 	u8         reserved_2[0x160];
5240 
5241 	struct mlx5_ifc_cmd_pas_bits pas;
5242 };
5243 
5244 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
5245 	u8         opcode[0x10];
5246 	u8         reserved_0[0x10];
5247 
5248 	u8         reserved_1[0x10];
5249 	u8         op_mod[0x10];
5250 
5251 	u8         reserved_2[0x40];
5252 };
5253 
5254 struct mlx5_ifc_packet_reformat_context_in_bits {
5255 	u8         reserved_at_0[0x5];
5256 	u8         reformat_type[0x3];
5257 	u8         reserved_at_8[0xe];
5258 	u8         reformat_data_size[0xa];
5259 
5260 	u8         reserved_at_20[0x10];
5261 	u8         reformat_data[2][0x8];
5262 
5263 	u8         more_reformat_data[0][0x8];
5264 };
5265 
5266 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5267 	u8         status[0x8];
5268 	u8         reserved_at_8[0x18];
5269 
5270 	u8         syndrome[0x20];
5271 
5272 	u8         reserved_at_40[0xa0];
5273 
5274 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5275 };
5276 
5277 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5278 	u8         opcode[0x10];
5279 	u8         reserved_at_10[0x10];
5280 
5281 	u8         reserved_at_20[0x10];
5282 	u8         op_mod[0x10];
5283 
5284 	u8         packet_reformat_id[0x20];
5285 
5286 	u8         reserved_at_60[0xa0];
5287 };
5288 
5289 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5290 	u8         status[0x8];
5291 	u8         reserved_at_8[0x18];
5292 
5293 	u8         syndrome[0x20];
5294 
5295 	u8         packet_reformat_id[0x20];
5296 
5297 	u8         reserved_at_60[0x20];
5298 };
5299 
5300 enum mlx5_reformat_ctx_type {
5301 	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5302 	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5303 	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5304 	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5305 	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5306 };
5307 
5308 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5309 	u8         opcode[0x10];
5310 	u8         reserved_at_10[0x10];
5311 
5312 	u8         reserved_at_20[0x10];
5313 	u8         op_mod[0x10];
5314 
5315 	u8         reserved_at_40[0xa0];
5316 
5317 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5318 };
5319 
5320 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5321 	u8         status[0x8];
5322 	u8         reserved_at_8[0x18];
5323 
5324 	u8         syndrome[0x20];
5325 
5326 	u8         reserved_at_40[0x40];
5327 };
5328 
5329 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5330 	u8         opcode[0x10];
5331 	u8         reserved_at_10[0x10];
5332 
5333 	u8         reserved_20[0x10];
5334 	u8         op_mod[0x10];
5335 
5336 	u8         packet_reformat_id[0x20];
5337 
5338 	u8         reserved_60[0x20];
5339 };
5340 
5341 struct mlx5_ifc_diagnostic_cntr_struct_bits {
5342 	u8         counter_id[0x10];
5343 	u8         sample_id[0x10];
5344 
5345 	u8         time_stamp_31_0[0x20];
5346 
5347 	u8         counter_value_h[0x20];
5348 
5349 	u8         counter_value_l[0x20];
5350 };
5351 
5352 enum {
5353 	MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_ENABLE   = 0x1,
5354 	MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_DISABLE  = 0x0,
5355 };
5356 
5357 struct mlx5_ifc_query_cq_out_bits {
5358 	u8         status[0x8];
5359 	u8         reserved_0[0x18];
5360 
5361 	u8         syndrome[0x20];
5362 
5363 	u8         reserved_1[0x40];
5364 
5365 	struct mlx5_ifc_cqc_bits cq_context;
5366 
5367 	u8         reserved_2[0x600];
5368 
5369 	u8         pas[0][0x40];
5370 };
5371 
5372 struct mlx5_ifc_query_cq_in_bits {
5373 	u8         opcode[0x10];
5374 	u8         reserved_0[0x10];
5375 
5376 	u8         reserved_1[0x10];
5377 	u8         op_mod[0x10];
5378 
5379 	u8         reserved_2[0x8];
5380 	u8         cqn[0x18];
5381 
5382 	u8         reserved_3[0x20];
5383 };
5384 
5385 struct mlx5_ifc_query_cong_status_out_bits {
5386 	u8         status[0x8];
5387 	u8         reserved_0[0x18];
5388 
5389 	u8         syndrome[0x20];
5390 
5391 	u8         reserved_1[0x20];
5392 
5393 	u8         enable[0x1];
5394 	u8         tag_enable[0x1];
5395 	u8         reserved_2[0x1e];
5396 };
5397 
5398 struct mlx5_ifc_query_cong_status_in_bits {
5399 	u8         opcode[0x10];
5400 	u8         reserved_0[0x10];
5401 
5402 	u8         reserved_1[0x10];
5403 	u8         op_mod[0x10];
5404 
5405 	u8         reserved_2[0x18];
5406 	u8         priority[0x4];
5407 	u8         cong_protocol[0x4];
5408 
5409 	u8         reserved_3[0x20];
5410 };
5411 
5412 struct mlx5_ifc_query_cong_statistics_out_bits {
5413 	u8         status[0x8];
5414 	u8         reserved_0[0x18];
5415 
5416 	u8         syndrome[0x20];
5417 
5418 	u8         reserved_1[0x40];
5419 
5420 	u8         rp_cur_flows[0x20];
5421 
5422 	u8         sum_flows[0x20];
5423 
5424 	u8         rp_cnp_ignored_high[0x20];
5425 
5426 	u8         rp_cnp_ignored_low[0x20];
5427 
5428 	u8         rp_cnp_handled_high[0x20];
5429 
5430 	u8         rp_cnp_handled_low[0x20];
5431 
5432 	u8         reserved_2[0x100];
5433 
5434 	u8         time_stamp_high[0x20];
5435 
5436 	u8         time_stamp_low[0x20];
5437 
5438 	u8         accumulators_period[0x20];
5439 
5440 	u8         np_ecn_marked_roce_packets_high[0x20];
5441 
5442 	u8         np_ecn_marked_roce_packets_low[0x20];
5443 
5444 	u8         np_cnp_sent_high[0x20];
5445 
5446 	u8         np_cnp_sent_low[0x20];
5447 
5448 	u8         reserved_3[0x560];
5449 };
5450 
5451 struct mlx5_ifc_query_cong_statistics_in_bits {
5452 	u8         opcode[0x10];
5453 	u8         reserved_0[0x10];
5454 
5455 	u8         reserved_1[0x10];
5456 	u8         op_mod[0x10];
5457 
5458 	u8         clear[0x1];
5459 	u8         reserved_2[0x1f];
5460 
5461 	u8         reserved_3[0x20];
5462 };
5463 
5464 struct mlx5_ifc_query_cong_params_out_bits {
5465 	u8         status[0x8];
5466 	u8         reserved_0[0x18];
5467 
5468 	u8         syndrome[0x20];
5469 
5470 	u8         reserved_1[0x40];
5471 
5472 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5473 };
5474 
5475 struct mlx5_ifc_query_cong_params_in_bits {
5476 	u8         opcode[0x10];
5477 	u8         reserved_0[0x10];
5478 
5479 	u8         reserved_1[0x10];
5480 	u8         op_mod[0x10];
5481 
5482 	u8         reserved_2[0x1c];
5483 	u8         cong_protocol[0x4];
5484 
5485 	u8         reserved_3[0x20];
5486 };
5487 
5488 struct mlx5_ifc_query_burst_size_out_bits {
5489 	u8         status[0x8];
5490 	u8         reserved_0[0x18];
5491 
5492 	u8         syndrome[0x20];
5493 
5494 	u8         reserved_1[0x20];
5495 
5496 	u8         reserved_2[0x9];
5497 	u8         device_burst_size[0x17];
5498 };
5499 
5500 struct mlx5_ifc_query_burst_size_in_bits {
5501 	u8         opcode[0x10];
5502 	u8         reserved_0[0x10];
5503 
5504 	u8         reserved_1[0x10];
5505 	u8         op_mod[0x10];
5506 
5507 	u8         reserved_2[0x40];
5508 };
5509 
5510 struct mlx5_ifc_query_adapter_out_bits {
5511 	u8         status[0x8];
5512 	u8         reserved_0[0x18];
5513 
5514 	u8         syndrome[0x20];
5515 
5516 	u8         reserved_1[0x40];
5517 
5518 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5519 };
5520 
5521 struct mlx5_ifc_query_adapter_in_bits {
5522 	u8         opcode[0x10];
5523 	u8         reserved_0[0x10];
5524 
5525 	u8         reserved_1[0x10];
5526 	u8         op_mod[0x10];
5527 
5528 	u8         reserved_2[0x40];
5529 };
5530 
5531 struct mlx5_ifc_qp_2rst_out_bits {
5532 	u8         status[0x8];
5533 	u8         reserved_0[0x18];
5534 
5535 	u8         syndrome[0x20];
5536 
5537 	u8         reserved_1[0x40];
5538 };
5539 
5540 struct mlx5_ifc_qp_2rst_in_bits {
5541 	u8         opcode[0x10];
5542 	u8         uid[0x10];
5543 
5544 	u8         reserved_1[0x10];
5545 	u8         op_mod[0x10];
5546 
5547 	u8         reserved_2[0x8];
5548 	u8         qpn[0x18];
5549 
5550 	u8         reserved_3[0x20];
5551 };
5552 
5553 struct mlx5_ifc_qp_2err_out_bits {
5554 	u8         status[0x8];
5555 	u8         reserved_0[0x18];
5556 
5557 	u8         syndrome[0x20];
5558 
5559 	u8         reserved_1[0x40];
5560 };
5561 
5562 struct mlx5_ifc_qp_2err_in_bits {
5563 	u8         opcode[0x10];
5564 	u8         uid[0x10];
5565 
5566 	u8         reserved_1[0x10];
5567 	u8         op_mod[0x10];
5568 
5569 	u8         reserved_2[0x8];
5570 	u8         qpn[0x18];
5571 
5572 	u8         reserved_3[0x20];
5573 };
5574 
5575 struct mlx5_ifc_para_vport_element_bits {
5576 	u8         reserved_at_0[0xc];
5577 	u8         traffic_class[0x4];
5578 	u8         qos_para_vport_number[0x10];
5579 };
5580 
5581 struct mlx5_ifc_page_fault_resume_out_bits {
5582 	u8         status[0x8];
5583 	u8         reserved_0[0x18];
5584 
5585 	u8         syndrome[0x20];
5586 
5587 	u8         reserved_1[0x40];
5588 };
5589 
5590 struct mlx5_ifc_page_fault_resume_in_bits {
5591 	u8         opcode[0x10];
5592 	u8         reserved_0[0x10];
5593 
5594 	u8         reserved_1[0x10];
5595 	u8         op_mod[0x10];
5596 
5597 	u8         error[0x1];
5598 	u8         reserved_2[0x4];
5599 	u8         rdma[0x1];
5600 	u8         read_write[0x1];
5601 	u8         req_res[0x1];
5602 	u8         qpn[0x18];
5603 
5604 	u8         reserved_3[0x20];
5605 };
5606 
5607 struct mlx5_ifc_nop_out_bits {
5608 	u8         status[0x8];
5609 	u8         reserved_0[0x18];
5610 
5611 	u8         syndrome[0x20];
5612 
5613 	u8         reserved_1[0x40];
5614 };
5615 
5616 struct mlx5_ifc_nop_in_bits {
5617 	u8         opcode[0x10];
5618 	u8         reserved_0[0x10];
5619 
5620 	u8         reserved_1[0x10];
5621 	u8         op_mod[0x10];
5622 
5623 	u8         reserved_2[0x40];
5624 };
5625 
5626 struct mlx5_ifc_modify_vport_state_out_bits {
5627 	u8         status[0x8];
5628 	u8         reserved_0[0x18];
5629 
5630 	u8         syndrome[0x20];
5631 
5632 	u8         reserved_1[0x40];
5633 };
5634 
5635 enum {
5636 	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
5637 	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
5638 	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
5639 };
5640 
5641 enum {
5642 	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
5643 	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
5644 	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
5645 };
5646 
5647 struct mlx5_ifc_modify_vport_state_in_bits {
5648 	u8         opcode[0x10];
5649 	u8         reserved_0[0x10];
5650 
5651 	u8         reserved_1[0x10];
5652 	u8         op_mod[0x10];
5653 
5654 	u8         other_vport[0x1];
5655 	u8         reserved_2[0xf];
5656 	u8         vport_number[0x10];
5657 
5658 	u8         reserved_3[0x18];
5659 	u8         admin_state[0x4];
5660 	u8         reserved_4[0x4];
5661 };
5662 
5663 struct mlx5_ifc_modify_tis_out_bits {
5664 	u8         status[0x8];
5665 	u8         reserved_0[0x18];
5666 
5667 	u8         syndrome[0x20];
5668 
5669 	u8         reserved_1[0x40];
5670 };
5671 
5672 struct mlx5_ifc_modify_tis_bitmask_bits {
5673 	u8         reserved_at_0[0x20];
5674 
5675 	u8         reserved_at_20[0x1d];
5676 	u8         lag_tx_port_affinity[0x1];
5677 	u8         strict_lag_tx_port_affinity[0x1];
5678 	u8         prio[0x1];
5679 };
5680 
5681 struct mlx5_ifc_modify_tis_in_bits {
5682 	u8         opcode[0x10];
5683 	u8         uid[0x10];
5684 
5685 	u8         reserved_1[0x10];
5686 	u8         op_mod[0x10];
5687 
5688 	u8         reserved_2[0x8];
5689 	u8         tisn[0x18];
5690 
5691 	u8         reserved_3[0x20];
5692 
5693 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5694 
5695 	u8         reserved_4[0x40];
5696 
5697 	struct mlx5_ifc_tisc_bits ctx;
5698 };
5699 
5700 struct mlx5_ifc_modify_tir_out_bits {
5701 	u8         status[0x8];
5702 	u8         reserved_0[0x18];
5703 
5704 	u8         syndrome[0x20];
5705 
5706 	u8         reserved_1[0x40];
5707 };
5708 
5709 enum
5710 {
5711 	MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5712 	MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER =		0x1 << 1
5713 };
5714 
5715 struct mlx5_ifc_modify_tir_in_bits {
5716 	u8         opcode[0x10];
5717 	u8         uid[0x10];
5718 
5719 	u8         reserved_1[0x10];
5720 	u8         op_mod[0x10];
5721 
5722 	u8         reserved_2[0x8];
5723 	u8         tirn[0x18];
5724 
5725 	u8         reserved_3[0x20];
5726 
5727 	u8         modify_bitmask[0x40];
5728 
5729 	u8         reserved_4[0x40];
5730 
5731 	struct mlx5_ifc_tirc_bits tir_context;
5732 };
5733 
5734 struct mlx5_ifc_modify_sq_out_bits {
5735 	u8         status[0x8];
5736 	u8         reserved_0[0x18];
5737 
5738 	u8         syndrome[0x20];
5739 
5740 	u8         reserved_1[0x40];
5741 };
5742 
5743 struct mlx5_ifc_modify_sq_in_bits {
5744 	u8         opcode[0x10];
5745 	u8         uid[0x10];
5746 
5747 	u8         reserved_1[0x10];
5748 	u8         op_mod[0x10];
5749 
5750 	u8         sq_state[0x4];
5751 	u8         reserved_2[0x4];
5752 	u8         sqn[0x18];
5753 
5754 	u8         reserved_3[0x20];
5755 
5756 	u8         modify_bitmask[0x40];
5757 
5758 	u8         reserved_4[0x40];
5759 
5760 	struct mlx5_ifc_sqc_bits ctx;
5761 };
5762 
5763 struct mlx5_ifc_modify_scheduling_element_out_bits {
5764 	u8         status[0x8];
5765 	u8         reserved_at_8[0x18];
5766 
5767 	u8         syndrome[0x20];
5768 
5769 	u8         reserved_at_40[0x1c0];
5770 };
5771 
5772 enum {
5773 	MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
5774 };
5775 
5776 enum {
5777 	MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE        = 0x1,
5778 	MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW  = 0x2,
5779 };
5780 
5781 struct mlx5_ifc_modify_scheduling_element_in_bits {
5782 	u8         opcode[0x10];
5783 	u8         reserved_at_10[0x10];
5784 
5785 	u8         reserved_at_20[0x10];
5786 	u8         op_mod[0x10];
5787 
5788 	u8         scheduling_hierarchy[0x8];
5789 	u8         reserved_at_48[0x18];
5790 
5791 	u8         scheduling_element_id[0x20];
5792 
5793 	u8         reserved_at_80[0x20];
5794 
5795 	u8         modify_bitmask[0x20];
5796 
5797 	u8         reserved_at_c0[0x40];
5798 
5799 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5800 
5801 	u8         reserved_at_300[0x100];
5802 };
5803 
5804 struct mlx5_ifc_modify_rqt_out_bits {
5805 	u8         status[0x8];
5806 	u8         reserved_0[0x18];
5807 
5808 	u8         syndrome[0x20];
5809 
5810 	u8         reserved_1[0x40];
5811 };
5812 
5813 struct mlx5_ifc_rqt_bitmask_bits {
5814 	u8         reserved_at_0[0x20];
5815 
5816 	u8         reserved_at_20[0x1f];
5817 	u8         rqn_list[0x1];
5818 };
5819 
5820 
5821 struct mlx5_ifc_modify_rqt_in_bits {
5822 	u8         opcode[0x10];
5823 	u8         uid[0x10];
5824 
5825 	u8         reserved_1[0x10];
5826 	u8         op_mod[0x10];
5827 
5828 	u8         reserved_2[0x8];
5829 	u8         rqtn[0x18];
5830 
5831 	u8         reserved_3[0x20];
5832 
5833 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
5834 
5835 	u8         reserved_4[0x40];
5836 
5837 	struct mlx5_ifc_rqtc_bits ctx;
5838 };
5839 
5840 struct mlx5_ifc_modify_rq_out_bits {
5841 	u8         status[0x8];
5842 	u8         reserved_0[0x18];
5843 
5844 	u8         syndrome[0x20];
5845 
5846 	u8         reserved_1[0x40];
5847 };
5848 
5849 enum {
5850 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5851 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5852 };
5853 
5854 struct mlx5_ifc_modify_rq_in_bits {
5855 	u8         opcode[0x10];
5856 	u8         uid[0x10];
5857 
5858 	u8         reserved_1[0x10];
5859 	u8         op_mod[0x10];
5860 
5861 	u8         rq_state[0x4];
5862 	u8         reserved_2[0x4];
5863 	u8         rqn[0x18];
5864 
5865 	u8         reserved_3[0x20];
5866 
5867 	u8         modify_bitmask[0x40];
5868 
5869 	u8         reserved_4[0x40];
5870 
5871 	struct mlx5_ifc_rqc_bits ctx;
5872 };
5873 
5874 struct mlx5_ifc_modify_rmp_out_bits {
5875 	u8         status[0x8];
5876 	u8         reserved_0[0x18];
5877 
5878 	u8         syndrome[0x20];
5879 
5880 	u8         reserved_1[0x40];
5881 };
5882 
5883 struct mlx5_ifc_rmp_bitmask_bits {
5884 	u8	   reserved[0x20];
5885 
5886 	u8         reserved1[0x1f];
5887 	u8         lwm[0x1];
5888 };
5889 
5890 struct mlx5_ifc_modify_rmp_in_bits {
5891 	u8         opcode[0x10];
5892 	u8         uid[0x10];
5893 
5894 	u8         reserved_1[0x10];
5895 	u8         op_mod[0x10];
5896 
5897 	u8         rmp_state[0x4];
5898 	u8         reserved_2[0x4];
5899 	u8         rmpn[0x18];
5900 
5901 	u8         reserved_3[0x20];
5902 
5903 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
5904 
5905 	u8         reserved_4[0x40];
5906 
5907 	struct mlx5_ifc_rmpc_bits ctx;
5908 };
5909 
5910 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5911 	u8         status[0x8];
5912 	u8         reserved_0[0x18];
5913 
5914 	u8         syndrome[0x20];
5915 
5916 	u8         reserved_1[0x40];
5917 };
5918 
5919 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5920 	u8         reserved_0[0x14];
5921 	u8         disable_uc_local_lb[0x1];
5922 	u8         disable_mc_local_lb[0x1];
5923 	u8         node_guid[0x1];
5924 	u8         port_guid[0x1];
5925 	u8         min_wqe_inline_mode[0x1];
5926 	u8         mtu[0x1];
5927 	u8         change_event[0x1];
5928 	u8         promisc[0x1];
5929 	u8         permanent_address[0x1];
5930 	u8         addresses_list[0x1];
5931 	u8         roce_en[0x1];
5932 	u8         reserved_1[0x1];
5933 };
5934 
5935 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5936 	u8         opcode[0x10];
5937 	u8         reserved_0[0x10];
5938 
5939 	u8         reserved_1[0x10];
5940 	u8         op_mod[0x10];
5941 
5942 	u8         other_vport[0x1];
5943 	u8         reserved_2[0xf];
5944 	u8         vport_number[0x10];
5945 
5946 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5947 
5948 	u8         reserved_3[0x780];
5949 
5950 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5951 };
5952 
5953 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5954 	u8         status[0x8];
5955 	u8         reserved_0[0x18];
5956 
5957 	u8         syndrome[0x20];
5958 
5959 	u8         reserved_1[0x40];
5960 };
5961 
5962 struct mlx5_ifc_grh_bits {
5963 	u8	ip_version[4];
5964 	u8	traffic_class[8];
5965 	u8	flow_label[20];
5966 	u8	payload_length[16];
5967 	u8	next_header[8];
5968 	u8	hop_limit[8];
5969 	u8	sgid[128];
5970 	u8	dgid[128];
5971 };
5972 
5973 struct mlx5_ifc_bth_bits {
5974 	u8	opcode[8];
5975 	u8	se[1];
5976 	u8	migreq[1];
5977 	u8	pad_count[2];
5978 	u8	tver[4];
5979 	u8	p_key[16];
5980 	u8	reserved8[8];
5981 	u8	dest_qp[24];
5982 	u8	ack_req[1];
5983 	u8	reserved7[7];
5984 	u8	psn[24];
5985 };
5986 
5987 struct mlx5_ifc_aeth_bits {
5988 	u8	syndrome[8];
5989 	u8	msn[24];
5990 };
5991 
5992 struct mlx5_ifc_dceth_bits {
5993 	u8	reserved0[8];
5994 	u8	session_id[24];
5995 	u8	reserved1[8];
5996 	u8	dci_dct[24];
5997 };
5998 
5999 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6000 	u8         opcode[0x10];
6001 	u8         reserved_0[0x10];
6002 
6003 	u8         reserved_1[0x10];
6004 	u8         op_mod[0x10];
6005 
6006 	u8         other_vport[0x1];
6007 	u8         reserved_2[0xb];
6008 	u8         port_num[0x4];
6009 	u8         vport_number[0x10];
6010 
6011 	u8         reserved_3[0x20];
6012 
6013 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6014 };
6015 
6016 struct mlx5_ifc_modify_flow_table_out_bits {
6017 	u8         status[0x8];
6018 	u8         reserved_at_8[0x18];
6019 
6020 	u8         syndrome[0x20];
6021 
6022 	u8         reserved_at_40[0x40];
6023 };
6024 
6025 enum {
6026 	MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
6027 	MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
6028 };
6029 
6030 struct mlx5_ifc_modify_flow_table_in_bits {
6031 	u8         opcode[0x10];
6032 	u8         reserved_at_10[0x10];
6033 
6034 	u8         reserved_at_20[0x10];
6035 	u8         op_mod[0x10];
6036 
6037 	u8         other_vport[0x1];
6038 	u8         reserved_at_41[0xf];
6039 	u8         vport_number[0x10];
6040 
6041 	u8         reserved_at_60[0x10];
6042 	u8         modify_field_select[0x10];
6043 
6044 	u8         table_type[0x8];
6045 	u8         reserved_at_88[0x18];
6046 
6047 	u8         reserved_at_a0[0x8];
6048 	u8         table_id[0x18];
6049 
6050 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6051 };
6052 
6053 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6054 	u8         status[0x8];
6055 	u8         reserved_0[0x18];
6056 
6057 	u8         syndrome[0x20];
6058 
6059 	u8         reserved_1[0x40];
6060 };
6061 
6062 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6063 	u8         reserved[0x1c];
6064 	u8         vport_cvlan_insert[0x1];
6065 	u8         vport_svlan_insert[0x1];
6066 	u8         vport_cvlan_strip[0x1];
6067 	u8         vport_svlan_strip[0x1];
6068 };
6069 
6070 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6071 	u8         opcode[0x10];
6072 	u8         reserved_0[0x10];
6073 
6074 	u8         reserved_1[0x10];
6075 	u8         op_mod[0x10];
6076 
6077 	u8         other_vport[0x1];
6078 	u8         reserved_2[0xf];
6079 	u8         vport_number[0x10];
6080 
6081 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6082 
6083 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6084 };
6085 
6086 struct mlx5_ifc_modify_cq_out_bits {
6087 	u8         status[0x8];
6088 	u8         reserved_0[0x18];
6089 
6090 	u8         syndrome[0x20];
6091 
6092 	u8         reserved_1[0x40];
6093 };
6094 
6095 enum {
6096 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6097 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6098 };
6099 
6100 struct mlx5_ifc_modify_cq_in_bits {
6101 	u8         opcode[0x10];
6102 	u8         uid[0x10];
6103 
6104 	u8         reserved_1[0x10];
6105 	u8         op_mod[0x10];
6106 
6107 	u8         reserved_2[0x8];
6108 	u8         cqn[0x18];
6109 
6110 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6111 
6112 	struct mlx5_ifc_cqc_bits cq_context;
6113 
6114 	u8         reserved_at_280[0x60];
6115 
6116 	u8         cq_umem_valid[0x1];
6117 	u8         reserved_at_2e1[0x1f];
6118 
6119 	u8         reserved_at_300[0x580];
6120 
6121 	u8         pas[0][0x40];
6122 };
6123 
6124 struct mlx5_ifc_modify_cong_status_out_bits {
6125 	u8         status[0x8];
6126 	u8         reserved_0[0x18];
6127 
6128 	u8         syndrome[0x20];
6129 
6130 	u8         reserved_1[0x40];
6131 };
6132 
6133 struct mlx5_ifc_modify_cong_status_in_bits {
6134 	u8         opcode[0x10];
6135 	u8         reserved_0[0x10];
6136 
6137 	u8         reserved_1[0x10];
6138 	u8         op_mod[0x10];
6139 
6140 	u8         reserved_2[0x18];
6141 	u8         priority[0x4];
6142 	u8         cong_protocol[0x4];
6143 
6144 	u8         enable[0x1];
6145 	u8         tag_enable[0x1];
6146 	u8         reserved_3[0x1e];
6147 };
6148 
6149 struct mlx5_ifc_modify_cong_params_out_bits {
6150 	u8         status[0x8];
6151 	u8         reserved_0[0x18];
6152 
6153 	u8         syndrome[0x20];
6154 
6155 	u8         reserved_1[0x40];
6156 };
6157 
6158 struct mlx5_ifc_modify_cong_params_in_bits {
6159 	u8         opcode[0x10];
6160 	u8         reserved_0[0x10];
6161 
6162 	u8         reserved_1[0x10];
6163 	u8         op_mod[0x10];
6164 
6165 	u8         reserved_2[0x1c];
6166 	u8         cong_protocol[0x4];
6167 
6168 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6169 
6170 	u8         reserved_3[0x80];
6171 
6172 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6173 };
6174 
6175 struct mlx5_ifc_manage_pages_out_bits {
6176 	u8         status[0x8];
6177 	u8         reserved_0[0x18];
6178 
6179 	u8         syndrome[0x20];
6180 
6181 	u8         output_num_entries[0x20];
6182 
6183 	u8         reserved_1[0x20];
6184 
6185 	u8         pas[0][0x40];
6186 };
6187 
6188 enum {
6189 	MLX5_PAGES_CANT_GIVE                            = 0x0,
6190 	MLX5_PAGES_GIVE                                 = 0x1,
6191 	MLX5_PAGES_TAKE                                 = 0x2,
6192 };
6193 
6194 struct mlx5_ifc_manage_pages_in_bits {
6195 	u8         opcode[0x10];
6196 	u8         reserved_0[0x10];
6197 
6198 	u8         reserved_1[0x10];
6199 	u8         op_mod[0x10];
6200 
6201 	u8         reserved_2[0x10];
6202 	u8         function_id[0x10];
6203 
6204 	u8         input_num_entries[0x20];
6205 
6206 	u8         pas[0][0x40];
6207 };
6208 
6209 struct mlx5_ifc_mad_ifc_out_bits {
6210 	u8         status[0x8];
6211 	u8         reserved_0[0x18];
6212 
6213 	u8         syndrome[0x20];
6214 
6215 	u8         reserved_1[0x40];
6216 
6217 	u8         response_mad_packet[256][0x8];
6218 };
6219 
6220 struct mlx5_ifc_mad_ifc_in_bits {
6221 	u8         opcode[0x10];
6222 	u8         reserved_0[0x10];
6223 
6224 	u8         reserved_1[0x10];
6225 	u8         op_mod[0x10];
6226 
6227 	u8         remote_lid[0x10];
6228 	u8         reserved_2[0x8];
6229 	u8         port[0x8];
6230 
6231 	u8         reserved_3[0x20];
6232 
6233 	u8         mad[256][0x8];
6234 };
6235 
6236 struct mlx5_ifc_init_hca_out_bits {
6237 	u8         status[0x8];
6238 	u8         reserved_0[0x18];
6239 
6240 	u8         syndrome[0x20];
6241 
6242 	u8         reserved_1[0x40];
6243 };
6244 
6245 enum {
6246 	MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
6247 	MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
6248 };
6249 
6250 struct mlx5_ifc_init_hca_in_bits {
6251 	u8         opcode[0x10];
6252 	u8         reserved_0[0x10];
6253 
6254 	u8         reserved_1[0x10];
6255 	u8         op_mod[0x10];
6256 
6257 	u8         reserved_2[0x40];
6258 };
6259 
6260 struct mlx5_ifc_init2rtr_qp_out_bits {
6261 	u8         status[0x8];
6262 	u8         reserved_0[0x18];
6263 
6264 	u8         syndrome[0x20];
6265 
6266 	u8         reserved_1[0x40];
6267 };
6268 
6269 struct mlx5_ifc_init2rtr_qp_in_bits {
6270 	u8         opcode[0x10];
6271 	u8         uid[0x10];
6272 
6273 	u8         reserved_1[0x10];
6274 	u8         op_mod[0x10];
6275 
6276 	u8         reserved_2[0x8];
6277 	u8         qpn[0x18];
6278 
6279 	u8         reserved_3[0x20];
6280 
6281 	u8         opt_param_mask[0x20];
6282 
6283 	u8         reserved_4[0x20];
6284 
6285 	struct mlx5_ifc_qpc_bits qpc;
6286 
6287 	u8         reserved_5[0x80];
6288 };
6289 
6290 struct mlx5_ifc_init2init_qp_out_bits {
6291 	u8         status[0x8];
6292 	u8         reserved_0[0x18];
6293 
6294 	u8         syndrome[0x20];
6295 
6296 	u8         reserved_1[0x40];
6297 };
6298 
6299 struct mlx5_ifc_init2init_qp_in_bits {
6300 	u8         opcode[0x10];
6301 	u8         uid[0x10];
6302 
6303 	u8         reserved_1[0x10];
6304 	u8         op_mod[0x10];
6305 
6306 	u8         reserved_2[0x8];
6307 	u8         qpn[0x18];
6308 
6309 	u8         reserved_3[0x20];
6310 
6311 	u8         opt_param_mask[0x20];
6312 
6313 	u8         reserved_4[0x20];
6314 
6315 	struct mlx5_ifc_qpc_bits qpc;
6316 
6317 	u8         reserved_5[0x80];
6318 };
6319 
6320 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6321 	u8         status[0x8];
6322 	u8         reserved_0[0x18];
6323 
6324 	u8         syndrome[0x20];
6325 
6326 	u8         reserved_1[0x40];
6327 
6328 	u8         packet_headers_log[128][0x8];
6329 
6330 	u8         packet_syndrome[64][0x8];
6331 };
6332 
6333 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6334 	u8         opcode[0x10];
6335 	u8         reserved_0[0x10];
6336 
6337 	u8         reserved_1[0x10];
6338 	u8         op_mod[0x10];
6339 
6340 	u8         reserved_2[0x40];
6341 };
6342 
6343 struct mlx5_ifc_encryption_key_obj_bits {
6344 	u8         modify_field_select[0x40];
6345 
6346 	u8         reserved_at_40[0x14];
6347 	u8         key_size[0x4];
6348 	u8         reserved_at_58[0x4];
6349 	u8         key_type[0x4];
6350 
6351 	u8         reserved_at_60[0x8];
6352 	u8         pd[0x18];
6353 
6354 	u8         reserved_at_80[0x180];
6355 
6356 	u8         key[8][0x20];
6357 
6358 	u8         reserved_at_300[0x500];
6359 };
6360 
6361 struct mlx5_ifc_gen_eqe_in_bits {
6362 	u8         opcode[0x10];
6363 	u8         reserved_0[0x10];
6364 
6365 	u8         reserved_1[0x10];
6366 	u8         op_mod[0x10];
6367 
6368 	u8         reserved_2[0x18];
6369 	u8         eq_number[0x8];
6370 
6371 	u8         reserved_3[0x20];
6372 
6373 	u8         eqe[64][0x8];
6374 };
6375 
6376 struct mlx5_ifc_gen_eq_out_bits {
6377 	u8         status[0x8];
6378 	u8         reserved_0[0x18];
6379 
6380 	u8         syndrome[0x20];
6381 
6382 	u8         reserved_1[0x40];
6383 };
6384 
6385 struct mlx5_ifc_enable_hca_out_bits {
6386 	u8         status[0x8];
6387 	u8         reserved_0[0x18];
6388 
6389 	u8         syndrome[0x20];
6390 
6391 	u8         reserved_1[0x20];
6392 };
6393 
6394 struct mlx5_ifc_enable_hca_in_bits {
6395 	u8         opcode[0x10];
6396 	u8         reserved_0[0x10];
6397 
6398 	u8         reserved_1[0x10];
6399 	u8         op_mod[0x10];
6400 
6401 	u8         reserved_2[0x10];
6402 	u8         function_id[0x10];
6403 
6404 	u8         reserved_3[0x20];
6405 };
6406 
6407 struct mlx5_ifc_drain_dct_out_bits {
6408 	u8         status[0x8];
6409 	u8         reserved_0[0x18];
6410 
6411 	u8         syndrome[0x20];
6412 
6413 	u8         reserved_1[0x40];
6414 };
6415 
6416 struct mlx5_ifc_drain_dct_in_bits {
6417 	u8         opcode[0x10];
6418 	u8         uid[0x10];
6419 
6420 	u8         reserved_1[0x10];
6421 	u8         op_mod[0x10];
6422 
6423 	u8         reserved_2[0x8];
6424 	u8         dctn[0x18];
6425 
6426 	u8         reserved_3[0x20];
6427 };
6428 
6429 struct mlx5_ifc_disable_hca_out_bits {
6430 	u8         status[0x8];
6431 	u8         reserved_0[0x18];
6432 
6433 	u8         syndrome[0x20];
6434 
6435 	u8         reserved_1[0x20];
6436 };
6437 
6438 struct mlx5_ifc_disable_hca_in_bits {
6439 	u8         opcode[0x10];
6440 	u8         reserved_0[0x10];
6441 
6442 	u8         reserved_1[0x10];
6443 	u8         op_mod[0x10];
6444 
6445 	u8         reserved_2[0x10];
6446 	u8         function_id[0x10];
6447 
6448 	u8         reserved_3[0x20];
6449 };
6450 
6451 struct mlx5_ifc_detach_from_mcg_out_bits {
6452 	u8         status[0x8];
6453 	u8         reserved_0[0x18];
6454 
6455 	u8         syndrome[0x20];
6456 
6457 	u8         reserved_1[0x40];
6458 };
6459 
6460 struct mlx5_ifc_detach_from_mcg_in_bits {
6461 	u8         opcode[0x10];
6462 	u8         uid[0x10];
6463 
6464 	u8         reserved_1[0x10];
6465 	u8         op_mod[0x10];
6466 
6467 	u8         reserved_2[0x8];
6468 	u8         qpn[0x18];
6469 
6470 	u8         reserved_3[0x20];
6471 
6472 	u8         multicast_gid[16][0x8];
6473 };
6474 
6475 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6476 	u8         status[0x8];
6477 	u8         reserved_0[0x18];
6478 
6479 	u8         syndrome[0x20];
6480 
6481 	u8         reserved_1[0x40];
6482 };
6483 
6484 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6485 	u8         opcode[0x10];
6486 	u8         uid[0x10];
6487 
6488 	u8         reserved_1[0x10];
6489 	u8         op_mod[0x10];
6490 
6491 	u8         reserved_2[0x8];
6492 	u8         xrc_srqn[0x18];
6493 
6494 	u8         reserved_3[0x20];
6495 };
6496 
6497 struct mlx5_ifc_destroy_tis_out_bits {
6498 	u8         status[0x8];
6499 	u8         reserved_0[0x18];
6500 
6501 	u8         syndrome[0x20];
6502 
6503 	u8         reserved_1[0x40];
6504 };
6505 
6506 struct mlx5_ifc_destroy_tis_in_bits {
6507 	u8         opcode[0x10];
6508 	u8         uid[0x10];
6509 
6510 	u8         reserved_1[0x10];
6511 	u8         op_mod[0x10];
6512 
6513 	u8         reserved_2[0x8];
6514 	u8         tisn[0x18];
6515 
6516 	u8         reserved_3[0x20];
6517 };
6518 
6519 struct mlx5_ifc_destroy_tir_out_bits {
6520 	u8         status[0x8];
6521 	u8         reserved_0[0x18];
6522 
6523 	u8         syndrome[0x20];
6524 
6525 	u8         reserved_1[0x40];
6526 };
6527 
6528 struct mlx5_ifc_destroy_tir_in_bits {
6529 	u8         opcode[0x10];
6530 	u8         uid[0x10];
6531 
6532 	u8         reserved_1[0x10];
6533 	u8         op_mod[0x10];
6534 
6535 	u8         reserved_2[0x8];
6536 	u8         tirn[0x18];
6537 
6538 	u8         reserved_3[0x20];
6539 };
6540 
6541 struct mlx5_ifc_destroy_srq_out_bits {
6542 	u8         status[0x8];
6543 	u8         reserved_0[0x18];
6544 
6545 	u8         syndrome[0x20];
6546 
6547 	u8         reserved_1[0x40];
6548 };
6549 
6550 struct mlx5_ifc_destroy_srq_in_bits {
6551 	u8         opcode[0x10];
6552 	u8         uid[0x10];
6553 
6554 	u8         reserved_1[0x10];
6555 	u8         op_mod[0x10];
6556 
6557 	u8         reserved_2[0x8];
6558 	u8         srqn[0x18];
6559 
6560 	u8         reserved_3[0x20];
6561 };
6562 
6563 struct mlx5_ifc_destroy_sq_out_bits {
6564 	u8         status[0x8];
6565 	u8         reserved_0[0x18];
6566 
6567 	u8         syndrome[0x20];
6568 
6569 	u8         reserved_1[0x40];
6570 };
6571 
6572 struct mlx5_ifc_destroy_sq_in_bits {
6573 	u8         opcode[0x10];
6574 	u8         uid[0x10];
6575 
6576 	u8         reserved_1[0x10];
6577 	u8         op_mod[0x10];
6578 
6579 	u8         reserved_2[0x8];
6580 	u8         sqn[0x18];
6581 
6582 	u8         reserved_3[0x20];
6583 };
6584 
6585 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6586 	u8         status[0x8];
6587 	u8         reserved_at_8[0x18];
6588 
6589 	u8         syndrome[0x20];
6590 
6591 	u8         reserved_at_40[0x1c0];
6592 };
6593 
6594 enum {
6595 	MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6596 };
6597 
6598 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6599 	u8         opcode[0x10];
6600 	u8         reserved_at_10[0x10];
6601 
6602 	u8         reserved_at_20[0x10];
6603 	u8         op_mod[0x10];
6604 
6605 	u8         scheduling_hierarchy[0x8];
6606 	u8         reserved_at_48[0x18];
6607 
6608 	u8         scheduling_element_id[0x20];
6609 
6610 	u8         reserved_at_80[0x180];
6611 };
6612 
6613 struct mlx5_ifc_destroy_rqt_out_bits {
6614 	u8         status[0x8];
6615 	u8         reserved_0[0x18];
6616 
6617 	u8         syndrome[0x20];
6618 
6619 	u8         reserved_1[0x40];
6620 };
6621 
6622 struct mlx5_ifc_destroy_rqt_in_bits {
6623 	u8         opcode[0x10];
6624 	u8         uid[0x10];
6625 
6626 	u8         reserved_1[0x10];
6627 	u8         op_mod[0x10];
6628 
6629 	u8         reserved_2[0x8];
6630 	u8         rqtn[0x18];
6631 
6632 	u8         reserved_3[0x20];
6633 };
6634 
6635 struct mlx5_ifc_destroy_rq_out_bits {
6636 	u8         status[0x8];
6637 	u8         reserved_0[0x18];
6638 
6639 	u8         syndrome[0x20];
6640 
6641 	u8         reserved_1[0x40];
6642 };
6643 
6644 struct mlx5_ifc_destroy_rq_in_bits {
6645 	u8         opcode[0x10];
6646 	u8         uid[0x10];
6647 
6648 	u8         reserved_1[0x10];
6649 	u8         op_mod[0x10];
6650 
6651 	u8         reserved_2[0x8];
6652 	u8         rqn[0x18];
6653 
6654 	u8         reserved_3[0x20];
6655 };
6656 
6657 struct mlx5_ifc_destroy_rmp_out_bits {
6658 	u8         status[0x8];
6659 	u8         reserved_0[0x18];
6660 
6661 	u8         syndrome[0x20];
6662 
6663 	u8         reserved_1[0x40];
6664 };
6665 
6666 struct mlx5_ifc_destroy_rmp_in_bits {
6667 	u8         opcode[0x10];
6668 	u8         reserved_0[0x10];
6669 
6670 	u8         reserved_1[0x10];
6671 	u8         op_mod[0x10];
6672 
6673 	u8         reserved_2[0x8];
6674 	u8         rmpn[0x18];
6675 
6676 	u8         reserved_3[0x20];
6677 };
6678 
6679 struct mlx5_ifc_destroy_qp_out_bits {
6680 	u8         status[0x8];
6681 	u8         reserved_0[0x18];
6682 
6683 	u8         syndrome[0x20];
6684 
6685 	u8         reserved_1[0x40];
6686 };
6687 
6688 struct mlx5_ifc_destroy_qp_in_bits {
6689 	u8         opcode[0x10];
6690 	u8         uid[0x10];
6691 
6692 	u8         reserved_1[0x10];
6693 	u8         op_mod[0x10];
6694 
6695 	u8         reserved_2[0x8];
6696 	u8         qpn[0x18];
6697 
6698 	u8         reserved_3[0x20];
6699 };
6700 
6701 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6702 	u8         status[0x8];
6703 	u8         reserved_at_8[0x18];
6704 
6705 	u8         syndrome[0x20];
6706 
6707 	u8         reserved_at_40[0x1c0];
6708 };
6709 
6710 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6711 	u8         opcode[0x10];
6712 	u8         reserved_at_10[0x10];
6713 
6714 	u8         reserved_at_20[0x10];
6715 	u8         op_mod[0x10];
6716 
6717 	u8         reserved_at_40[0x20];
6718 
6719 	u8         reserved_at_60[0x10];
6720 	u8         qos_para_vport_number[0x10];
6721 
6722 	u8         reserved_at_80[0x180];
6723 };
6724 
6725 struct mlx5_ifc_destroy_psv_out_bits {
6726 	u8         status[0x8];
6727 	u8         reserved_0[0x18];
6728 
6729 	u8         syndrome[0x20];
6730 
6731 	u8         reserved_1[0x40];
6732 };
6733 
6734 struct mlx5_ifc_destroy_psv_in_bits {
6735 	u8         opcode[0x10];
6736 	u8         reserved_0[0x10];
6737 
6738 	u8         reserved_1[0x10];
6739 	u8         op_mod[0x10];
6740 
6741 	u8         reserved_2[0x8];
6742 	u8         psvn[0x18];
6743 
6744 	u8         reserved_3[0x20];
6745 };
6746 
6747 struct mlx5_ifc_destroy_mkey_out_bits {
6748 	u8         status[0x8];
6749 	u8         reserved_0[0x18];
6750 
6751 	u8         syndrome[0x20];
6752 
6753 	u8         reserved_1[0x40];
6754 };
6755 
6756 struct mlx5_ifc_destroy_mkey_in_bits {
6757 	u8         opcode[0x10];
6758 	u8         reserved_0[0x10];
6759 
6760 	u8         reserved_1[0x10];
6761 	u8         op_mod[0x10];
6762 
6763 	u8         reserved_2[0x8];
6764 	u8         mkey_index[0x18];
6765 
6766 	u8         reserved_3[0x20];
6767 };
6768 
6769 struct mlx5_ifc_destroy_flow_table_out_bits {
6770 	u8         status[0x8];
6771 	u8         reserved_0[0x18];
6772 
6773 	u8         syndrome[0x20];
6774 
6775 	u8         reserved_1[0x40];
6776 };
6777 
6778 struct mlx5_ifc_destroy_flow_table_in_bits {
6779 	u8         opcode[0x10];
6780 	u8         reserved_0[0x10];
6781 
6782 	u8         reserved_1[0x10];
6783 	u8         op_mod[0x10];
6784 
6785 	u8         other_vport[0x1];
6786 	u8         reserved_2[0xf];
6787 	u8         vport_number[0x10];
6788 
6789 	u8         reserved_3[0x20];
6790 
6791 	u8         table_type[0x8];
6792 	u8         reserved_4[0x18];
6793 
6794 	u8         reserved_5[0x8];
6795 	u8         table_id[0x18];
6796 
6797 	u8         reserved_6[0x140];
6798 };
6799 
6800 struct mlx5_ifc_destroy_flow_group_out_bits {
6801 	u8         status[0x8];
6802 	u8         reserved_0[0x18];
6803 
6804 	u8         syndrome[0x20];
6805 
6806 	u8         reserved_1[0x40];
6807 };
6808 
6809 struct mlx5_ifc_destroy_flow_group_in_bits {
6810 	u8         opcode[0x10];
6811 	u8         reserved_0[0x10];
6812 
6813 	u8         reserved_1[0x10];
6814 	u8         op_mod[0x10];
6815 
6816 	u8         other_vport[0x1];
6817 	u8         reserved_2[0xf];
6818 	u8         vport_number[0x10];
6819 
6820 	u8         reserved_3[0x20];
6821 
6822 	u8         table_type[0x8];
6823 	u8         reserved_4[0x18];
6824 
6825 	u8         reserved_5[0x8];
6826 	u8         table_id[0x18];
6827 
6828 	u8         group_id[0x20];
6829 
6830 	u8         reserved_6[0x120];
6831 };
6832 
6833 struct mlx5_ifc_destroy_encryption_key_out_bits {
6834 	u8         status[0x8];
6835 	u8         reserved_at_8[0x18];
6836 
6837 	u8         syndrome[0x20];
6838 
6839 	u8         reserved_at_40[0x40];
6840 };
6841 
6842 struct mlx5_ifc_destroy_encryption_key_in_bits {
6843 	u8         opcode[0x10];
6844 	u8         reserved_at_10[0x10];
6845 
6846 	u8         reserved_at_20[0x10];
6847 	u8         obj_type[0x10];
6848 
6849 	u8         obj_id[0x20];
6850 
6851 	u8         reserved_at_60[0x20];
6852 };
6853 
6854 struct mlx5_ifc_destroy_eq_out_bits {
6855 	u8         status[0x8];
6856 	u8         reserved_0[0x18];
6857 
6858 	u8         syndrome[0x20];
6859 
6860 	u8         reserved_1[0x40];
6861 };
6862 
6863 struct mlx5_ifc_destroy_eq_in_bits {
6864 	u8         opcode[0x10];
6865 	u8         reserved_0[0x10];
6866 
6867 	u8         reserved_1[0x10];
6868 	u8         op_mod[0x10];
6869 
6870 	u8         reserved_2[0x18];
6871 	u8         eq_number[0x8];
6872 
6873 	u8         reserved_3[0x20];
6874 };
6875 
6876 struct mlx5_ifc_destroy_dct_out_bits {
6877 	u8         status[0x8];
6878 	u8         reserved_0[0x18];
6879 
6880 	u8         syndrome[0x20];
6881 
6882 	u8         reserved_1[0x40];
6883 };
6884 
6885 struct mlx5_ifc_destroy_dct_in_bits {
6886 	u8         opcode[0x10];
6887 	u8         uid[0x10];
6888 
6889 	u8         reserved_1[0x10];
6890 	u8         op_mod[0x10];
6891 
6892 	u8         reserved_2[0x8];
6893 	u8         dctn[0x18];
6894 
6895 	u8         reserved_3[0x20];
6896 };
6897 
6898 struct mlx5_ifc_destroy_cq_out_bits {
6899 	u8         status[0x8];
6900 	u8         reserved_0[0x18];
6901 
6902 	u8         syndrome[0x20];
6903 
6904 	u8         reserved_1[0x40];
6905 };
6906 
6907 struct mlx5_ifc_destroy_cq_in_bits {
6908 	u8         opcode[0x10];
6909 	u8         uid[0x10];
6910 
6911 	u8         reserved_1[0x10];
6912 	u8         op_mod[0x10];
6913 
6914 	u8         reserved_2[0x8];
6915 	u8         cqn[0x18];
6916 
6917 	u8         reserved_3[0x20];
6918 };
6919 
6920 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6921 	u8         status[0x8];
6922 	u8         reserved_0[0x18];
6923 
6924 	u8         syndrome[0x20];
6925 
6926 	u8         reserved_1[0x40];
6927 };
6928 
6929 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6930 	u8         opcode[0x10];
6931 	u8         reserved_0[0x10];
6932 
6933 	u8         reserved_1[0x10];
6934 	u8         op_mod[0x10];
6935 
6936 	u8         reserved_2[0x20];
6937 
6938 	u8         reserved_3[0x10];
6939 	u8         vxlan_udp_port[0x10];
6940 };
6941 
6942 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6943 	u8         status[0x8];
6944 	u8         reserved_0[0x18];
6945 
6946 	u8         syndrome[0x20];
6947 
6948 	u8         reserved_1[0x40];
6949 };
6950 
6951 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6952 	u8         opcode[0x10];
6953 	u8         reserved_0[0x10];
6954 
6955 	u8         reserved_1[0x10];
6956 	u8         op_mod[0x10];
6957 
6958 	u8         reserved_2[0x60];
6959 
6960 	u8         reserved_3[0x8];
6961 	u8         table_index[0x18];
6962 
6963 	u8         reserved_4[0x140];
6964 };
6965 
6966 struct mlx5_ifc_delete_fte_out_bits {
6967 	u8         status[0x8];
6968 	u8         reserved_0[0x18];
6969 
6970 	u8         syndrome[0x20];
6971 
6972 	u8         reserved_1[0x40];
6973 };
6974 
6975 struct mlx5_ifc_delete_fte_in_bits {
6976 	u8         opcode[0x10];
6977 	u8         reserved_0[0x10];
6978 
6979 	u8         reserved_1[0x10];
6980 	u8         op_mod[0x10];
6981 
6982 	u8         other_vport[0x1];
6983 	u8         reserved_2[0xf];
6984 	u8         vport_number[0x10];
6985 
6986 	u8         reserved_3[0x20];
6987 
6988 	u8         table_type[0x8];
6989 	u8         reserved_4[0x18];
6990 
6991 	u8         reserved_5[0x8];
6992 	u8         table_id[0x18];
6993 
6994 	u8         reserved_6[0x40];
6995 
6996 	u8         flow_index[0x20];
6997 
6998 	u8         reserved_7[0xe0];
6999 };
7000 
7001 struct mlx5_ifc_dealloc_xrcd_out_bits {
7002 	u8         status[0x8];
7003 	u8         reserved_0[0x18];
7004 
7005 	u8         syndrome[0x20];
7006 
7007 	u8         reserved_1[0x40];
7008 };
7009 
7010 struct mlx5_ifc_dealloc_xrcd_in_bits {
7011 	u8         opcode[0x10];
7012 	u8         uid[0x10];
7013 
7014 	u8         reserved_1[0x10];
7015 	u8         op_mod[0x10];
7016 
7017 	u8         reserved_2[0x8];
7018 	u8         xrcd[0x18];
7019 
7020 	u8         reserved_3[0x20];
7021 };
7022 
7023 struct mlx5_ifc_dealloc_uar_out_bits {
7024 	u8         status[0x8];
7025 	u8         reserved_0[0x18];
7026 
7027 	u8         syndrome[0x20];
7028 
7029 	u8         reserved_1[0x40];
7030 };
7031 
7032 struct mlx5_ifc_dealloc_uar_in_bits {
7033 	u8         opcode[0x10];
7034 	u8         reserved_0[0x10];
7035 
7036 	u8         reserved_1[0x10];
7037 	u8         op_mod[0x10];
7038 
7039 	u8         reserved_2[0x8];
7040 	u8         uar[0x18];
7041 
7042 	u8         reserved_3[0x20];
7043 };
7044 
7045 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7046 	u8         status[0x8];
7047 	u8         reserved_0[0x18];
7048 
7049 	u8         syndrome[0x20];
7050 
7051 	u8         reserved_1[0x40];
7052 };
7053 
7054 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7055 	u8         opcode[0x10];
7056 	u8         uid[0x10];
7057 
7058 	u8         reserved_1[0x10];
7059 	u8         op_mod[0x10];
7060 
7061 	u8         reserved_2[0x8];
7062 	u8         transport_domain[0x18];
7063 
7064 	u8         reserved_3[0x20];
7065 };
7066 
7067 struct mlx5_ifc_dealloc_q_counter_out_bits {
7068 	u8         status[0x8];
7069 	u8         reserved_0[0x18];
7070 
7071 	u8         syndrome[0x20];
7072 
7073 	u8         reserved_1[0x40];
7074 };
7075 
7076 struct mlx5_ifc_counter_id_bits {
7077 	u8         reserved[0x10];
7078 	u8         counter_id[0x10];
7079 };
7080 
7081 struct mlx5_ifc_diagnostic_params_context_bits {
7082 	u8         num_of_counters[0x10];
7083 	u8         reserved_2[0x8];
7084 	u8         log_num_of_samples[0x8];
7085 
7086 	u8         single[0x1];
7087 	u8         repetitive[0x1];
7088 	u8         sync[0x1];
7089 	u8         clear[0x1];
7090 	u8         on_demand[0x1];
7091 	u8         enable[0x1];
7092 	u8         reserved_3[0x12];
7093 	u8         log_sample_period[0x8];
7094 
7095 	u8         reserved_4[0x80];
7096 
7097 	struct mlx5_ifc_counter_id_bits counter_id[0];
7098 };
7099 
7100 struct mlx5_ifc_query_diagnostic_params_in_bits {
7101 	u8         opcode[0x10];
7102 	u8         reserved_at_10[0x10];
7103 
7104 	u8         reserved_at_20[0x10];
7105 	u8         op_mod[0x10];
7106 
7107 	u8         reserved_at_40[0x40];
7108 };
7109 
7110 struct mlx5_ifc_query_diagnostic_params_out_bits {
7111 	u8         status[0x8];
7112 	u8         reserved_at_8[0x18];
7113 
7114 	u8         syndrome[0x20];
7115 
7116 	struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
7117 };
7118 
7119 struct mlx5_ifc_set_diagnostic_params_in_bits {
7120 	u8         opcode[0x10];
7121 	u8         reserved_0[0x10];
7122 
7123 	u8         reserved_1[0x10];
7124 	u8         op_mod[0x10];
7125 
7126 	struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
7127 };
7128 
7129 struct mlx5_ifc_set_diagnostic_params_out_bits {
7130 	u8         status[0x8];
7131 	u8         reserved_0[0x18];
7132 
7133 	u8         syndrome[0x20];
7134 
7135 	u8         reserved_1[0x40];
7136 };
7137 
7138 struct mlx5_ifc_query_diagnostic_counters_in_bits {
7139 	u8         opcode[0x10];
7140 	u8         reserved_0[0x10];
7141 
7142 	u8         reserved_1[0x10];
7143 	u8         op_mod[0x10];
7144 
7145 	u8         num_of_samples[0x10];
7146 	u8         sample_index[0x10];
7147 
7148 	u8         reserved_2[0x20];
7149 };
7150 
7151 struct mlx5_ifc_diagnostic_counter_bits {
7152 	u8         counter_id[0x10];
7153 	u8         sample_id[0x10];
7154 
7155 	u8         time_stamp_31_0[0x20];
7156 
7157 	u8         counter_value_h[0x20];
7158 
7159 	u8         counter_value_l[0x20];
7160 };
7161 
7162 struct mlx5_ifc_query_diagnostic_counters_out_bits {
7163 	u8         status[0x8];
7164 	u8         reserved_0[0x18];
7165 
7166 	u8         syndrome[0x20];
7167 
7168 	u8         reserved_1[0x40];
7169 
7170 	struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
7171 };
7172 
7173 struct mlx5_ifc_dealloc_q_counter_in_bits {
7174 	u8         opcode[0x10];
7175 	u8         reserved_0[0x10];
7176 
7177 	u8         reserved_1[0x10];
7178 	u8         op_mod[0x10];
7179 
7180 	u8         reserved_2[0x18];
7181 	u8         counter_set_id[0x8];
7182 
7183 	u8         reserved_3[0x20];
7184 };
7185 
7186 struct mlx5_ifc_dealloc_pd_out_bits {
7187 	u8         status[0x8];
7188 	u8         reserved_0[0x18];
7189 
7190 	u8         syndrome[0x20];
7191 
7192 	u8         reserved_1[0x40];
7193 };
7194 
7195 struct mlx5_ifc_dealloc_pd_in_bits {
7196 	u8         opcode[0x10];
7197 	u8         uid[0x10];
7198 
7199 	u8         reserved_1[0x10];
7200 	u8         op_mod[0x10];
7201 
7202 	u8         reserved_2[0x8];
7203 	u8         pd[0x18];
7204 
7205 	u8         reserved_3[0x20];
7206 };
7207 
7208 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7209 	u8         status[0x8];
7210 	u8         reserved_0[0x18];
7211 
7212 	u8         syndrome[0x20];
7213 
7214 	u8         reserved_1[0x40];
7215 };
7216 
7217 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7218 	u8         opcode[0x10];
7219 	u8         reserved_0[0x10];
7220 
7221 	u8         reserved_1[0x10];
7222 	u8         op_mod[0x10];
7223 
7224 	u8         reserved_2[0x10];
7225 	u8         flow_counter_id[0x10];
7226 
7227 	u8         reserved_3[0x20];
7228 };
7229 
7230 struct mlx5_ifc_create_xrq_out_bits {
7231 	u8         status[0x8];
7232 	u8         reserved_at_8[0x18];
7233 
7234 	u8         syndrome[0x20];
7235 
7236 	u8         reserved_at_40[0x8];
7237 	u8         xrqn[0x18];
7238 
7239 	u8         reserved_at_60[0x20];
7240 };
7241 
7242 struct mlx5_ifc_create_xrq_in_bits {
7243 	u8         opcode[0x10];
7244 	u8         uid[0x10];
7245 
7246 	u8         reserved_at_20[0x10];
7247 	u8         op_mod[0x10];
7248 
7249 	u8         reserved_at_40[0x40];
7250 
7251 	struct mlx5_ifc_xrqc_bits xrq_context;
7252 };
7253 
7254 struct mlx5_ifc_deactivate_tracer_out_bits {
7255 	u8         status[0x8];
7256 	u8         reserved_0[0x18];
7257 
7258 	u8         syndrome[0x20];
7259 
7260 	u8         reserved_1[0x40];
7261 };
7262 
7263 struct mlx5_ifc_deactivate_tracer_in_bits {
7264 	u8         opcode[0x10];
7265 	u8         reserved_0[0x10];
7266 
7267 	u8         reserved_1[0x10];
7268 	u8         op_mod[0x10];
7269 
7270 	u8         mkey[0x20];
7271 
7272 	u8         reserved_2[0x20];
7273 };
7274 
7275 struct mlx5_ifc_create_xrc_srq_out_bits {
7276 	u8         status[0x8];
7277 	u8         reserved_0[0x18];
7278 
7279 	u8         syndrome[0x20];
7280 
7281 	u8         reserved_1[0x8];
7282 	u8         xrc_srqn[0x18];
7283 
7284 	u8         reserved_2[0x20];
7285 };
7286 
7287 struct mlx5_ifc_create_xrc_srq_in_bits {
7288 	u8         opcode[0x10];
7289 	u8         uid[0x10];
7290 
7291 	u8         reserved_1[0x10];
7292 	u8         op_mod[0x10];
7293 
7294 	u8         reserved_2[0x40];
7295 
7296 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7297 
7298 	u8         reserved_at_280[0x60];
7299 
7300 	u8         xrc_srq_umem_valid[0x1];
7301 	u8         reserved_at_2e1[0x1f];
7302 
7303 	u8         reserved_at_300[0x580];
7304 
7305 	u8         pas[0][0x40];
7306 };
7307 
7308 struct mlx5_ifc_create_tis_out_bits {
7309 	u8         status[0x8];
7310 	u8         reserved_0[0x18];
7311 
7312 	u8         syndrome[0x20];
7313 
7314 	u8         reserved_1[0x8];
7315 	u8         tisn[0x18];
7316 
7317 	u8         reserved_2[0x20];
7318 };
7319 
7320 struct mlx5_ifc_create_tis_in_bits {
7321 	u8         opcode[0x10];
7322 	u8         uid[0x10];
7323 
7324 	u8         reserved_1[0x10];
7325 	u8         op_mod[0x10];
7326 
7327 	u8         reserved_2[0xc0];
7328 
7329 	struct mlx5_ifc_tisc_bits ctx;
7330 };
7331 
7332 struct mlx5_ifc_create_tir_out_bits {
7333 	u8         status[0x8];
7334 	u8         reserved_0[0x18];
7335 
7336 	u8         syndrome[0x20];
7337 
7338 	u8         reserved_1[0x8];
7339 	u8         tirn[0x18];
7340 
7341 	u8         reserved_2[0x20];
7342 };
7343 
7344 struct mlx5_ifc_create_tir_in_bits {
7345 	u8         opcode[0x10];
7346 	u8         uid[0x10];
7347 
7348 	u8         reserved_1[0x10];
7349 	u8         op_mod[0x10];
7350 
7351 	u8         reserved_2[0xc0];
7352 
7353 	struct mlx5_ifc_tirc_bits tir_context;
7354 };
7355 
7356 struct mlx5_ifc_create_srq_out_bits {
7357 	u8         status[0x8];
7358 	u8         reserved_0[0x18];
7359 
7360 	u8         syndrome[0x20];
7361 
7362 	u8         reserved_1[0x8];
7363 	u8         srqn[0x18];
7364 
7365 	u8         reserved_2[0x20];
7366 };
7367 
7368 struct mlx5_ifc_create_srq_in_bits {
7369 	u8         opcode[0x10];
7370 	u8         uid[0x10];
7371 
7372 	u8         reserved_1[0x10];
7373 	u8         op_mod[0x10];
7374 
7375 	u8         reserved_2[0x40];
7376 
7377 	struct mlx5_ifc_srqc_bits srq_context_entry;
7378 
7379 	u8         reserved_3[0x600];
7380 
7381 	u8         pas[0][0x40];
7382 };
7383 
7384 struct mlx5_ifc_create_sq_out_bits {
7385 	u8         status[0x8];
7386 	u8         reserved_0[0x18];
7387 
7388 	u8         syndrome[0x20];
7389 
7390 	u8         reserved_1[0x8];
7391 	u8         sqn[0x18];
7392 
7393 	u8         reserved_2[0x20];
7394 };
7395 
7396 struct mlx5_ifc_create_sq_in_bits {
7397 	u8         opcode[0x10];
7398 	u8         uid[0x10];
7399 
7400 	u8         reserved_1[0x10];
7401 	u8         op_mod[0x10];
7402 
7403 	u8         reserved_2[0xc0];
7404 
7405 	struct mlx5_ifc_sqc_bits ctx;
7406 };
7407 
7408 struct mlx5_ifc_create_scheduling_element_out_bits {
7409 	u8         status[0x8];
7410 	u8         reserved_at_8[0x18];
7411 
7412 	u8         syndrome[0x20];
7413 
7414 	u8         reserved_at_40[0x40];
7415 
7416 	u8         scheduling_element_id[0x20];
7417 
7418 	u8         reserved_at_a0[0x160];
7419 };
7420 
7421 enum {
7422 	MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
7423 };
7424 
7425 struct mlx5_ifc_create_scheduling_element_in_bits {
7426 	u8         opcode[0x10];
7427 	u8         reserved_at_10[0x10];
7428 
7429 	u8         reserved_at_20[0x10];
7430 	u8         op_mod[0x10];
7431 
7432 	u8         scheduling_hierarchy[0x8];
7433 	u8         reserved_at_48[0x18];
7434 
7435 	u8         reserved_at_60[0xa0];
7436 
7437 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7438 
7439 	u8         reserved_at_300[0x100];
7440 };
7441 
7442 struct mlx5_ifc_create_rqt_out_bits {
7443 	u8         status[0x8];
7444 	u8         reserved_0[0x18];
7445 
7446 	u8         syndrome[0x20];
7447 
7448 	u8         reserved_1[0x8];
7449 	u8         rqtn[0x18];
7450 
7451 	u8         reserved_2[0x20];
7452 };
7453 
7454 struct mlx5_ifc_create_rqt_in_bits {
7455 	u8         opcode[0x10];
7456 	u8         uid[0x10];
7457 
7458 	u8         reserved_1[0x10];
7459 	u8         op_mod[0x10];
7460 
7461 	u8         reserved_2[0xc0];
7462 
7463 	struct mlx5_ifc_rqtc_bits rqt_context;
7464 };
7465 
7466 struct mlx5_ifc_create_rq_out_bits {
7467 	u8         status[0x8];
7468 	u8         reserved_0[0x18];
7469 
7470 	u8         syndrome[0x20];
7471 
7472 	u8         reserved_1[0x8];
7473 	u8         rqn[0x18];
7474 
7475 	u8         reserved_2[0x20];
7476 };
7477 
7478 struct mlx5_ifc_create_rq_in_bits {
7479 	u8         opcode[0x10];
7480 	u8         uid[0x10];
7481 
7482 	u8         reserved_1[0x10];
7483 	u8         op_mod[0x10];
7484 
7485 	u8         reserved_2[0xc0];
7486 
7487 	struct mlx5_ifc_rqc_bits ctx;
7488 };
7489 
7490 struct mlx5_ifc_create_rmp_out_bits {
7491 	u8         status[0x8];
7492 	u8         reserved_0[0x18];
7493 
7494 	u8         syndrome[0x20];
7495 
7496 	u8         reserved_1[0x8];
7497 	u8         rmpn[0x18];
7498 
7499 	u8         reserved_2[0x20];
7500 };
7501 
7502 struct mlx5_ifc_create_rmp_in_bits {
7503 	u8         opcode[0x10];
7504 	u8         uid[0x10];
7505 
7506 	u8         reserved_1[0x10];
7507 	u8         op_mod[0x10];
7508 
7509 	u8         reserved_2[0xc0];
7510 
7511 	struct mlx5_ifc_rmpc_bits ctx;
7512 };
7513 
7514 struct mlx5_ifc_create_qp_out_bits {
7515 	u8         status[0x8];
7516 	u8         reserved_0[0x18];
7517 
7518 	u8         syndrome[0x20];
7519 
7520 	u8         reserved_1[0x8];
7521 	u8         qpn[0x18];
7522 
7523 	u8         reserved_2[0x20];
7524 };
7525 
7526 struct mlx5_ifc_create_qp_in_bits {
7527 	u8         opcode[0x10];
7528 	u8         uid[0x10];
7529 
7530 	u8         reserved_1[0x10];
7531 	u8         op_mod[0x10];
7532 
7533 	u8         reserved_2[0x8];
7534 	u8         input_qpn[0x18];
7535 
7536 	u8         reserved_3[0x20];
7537 
7538 	u8         opt_param_mask[0x20];
7539 
7540 	u8         reserved_4[0x20];
7541 
7542 	struct mlx5_ifc_qpc_bits qpc;
7543 
7544 	u8         reserved_at_800[0x60];
7545 
7546 	u8         wq_umem_valid[0x1];
7547 	u8         reserved_at_861[0x1f];
7548 
7549 	u8         pas[0][0x40];
7550 };
7551 
7552 struct mlx5_ifc_create_qos_para_vport_out_bits {
7553 	u8         status[0x8];
7554 	u8         reserved_at_8[0x18];
7555 
7556 	u8         syndrome[0x20];
7557 
7558 	u8         reserved_at_40[0x20];
7559 
7560 	u8         reserved_at_60[0x10];
7561 	u8         qos_para_vport_number[0x10];
7562 
7563 	u8         reserved_at_80[0x180];
7564 };
7565 
7566 struct mlx5_ifc_create_qos_para_vport_in_bits {
7567 	u8         opcode[0x10];
7568 	u8         reserved_at_10[0x10];
7569 
7570 	u8         reserved_at_20[0x10];
7571 	u8         op_mod[0x10];
7572 
7573 	u8         reserved_at_40[0x1c0];
7574 };
7575 
7576 struct mlx5_ifc_create_psv_out_bits {
7577 	u8         status[0x8];
7578 	u8         reserved_0[0x18];
7579 
7580 	u8         syndrome[0x20];
7581 
7582 	u8         reserved_1[0x40];
7583 
7584 	u8         reserved_2[0x8];
7585 	u8         psv0_index[0x18];
7586 
7587 	u8         reserved_3[0x8];
7588 	u8         psv1_index[0x18];
7589 
7590 	u8         reserved_4[0x8];
7591 	u8         psv2_index[0x18];
7592 
7593 	u8         reserved_5[0x8];
7594 	u8         psv3_index[0x18];
7595 };
7596 
7597 struct mlx5_ifc_create_psv_in_bits {
7598 	u8         opcode[0x10];
7599 	u8         reserved_0[0x10];
7600 
7601 	u8         reserved_1[0x10];
7602 	u8         op_mod[0x10];
7603 
7604 	u8         num_psv[0x4];
7605 	u8         reserved_2[0x4];
7606 	u8         pd[0x18];
7607 
7608 	u8         reserved_3[0x20];
7609 };
7610 
7611 struct mlx5_ifc_create_mkey_out_bits {
7612 	u8         status[0x8];
7613 	u8         reserved_0[0x18];
7614 
7615 	u8         syndrome[0x20];
7616 
7617 	u8         reserved_1[0x8];
7618 	u8         mkey_index[0x18];
7619 
7620 	u8         reserved_2[0x20];
7621 };
7622 
7623 struct mlx5_ifc_create_mkey_in_bits {
7624 	u8         opcode[0x10];
7625 	u8         reserved_0[0x10];
7626 
7627 	u8         reserved_1[0x10];
7628 	u8         op_mod[0x10];
7629 
7630 	u8         reserved_2[0x20];
7631 
7632 	u8         pg_access[0x1];
7633 	u8         mkey_umem_valid[0x1];
7634 	u8         reserved_at_62[0x1e];
7635 
7636 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7637 
7638 	u8         reserved_4[0x80];
7639 
7640 	u8         translations_octword_actual_size[0x20];
7641 
7642 	u8         reserved_5[0x560];
7643 
7644 	u8         klm_pas_mtt[0][0x20];
7645 };
7646 
7647 struct mlx5_ifc_create_flow_table_out_bits {
7648 	u8         status[0x8];
7649 	u8         reserved_0[0x18];
7650 
7651 	u8         syndrome[0x20];
7652 
7653 	u8         reserved_1[0x8];
7654 	u8         table_id[0x18];
7655 
7656 	u8         reserved_2[0x20];
7657 };
7658 
7659 struct mlx5_ifc_create_flow_table_in_bits {
7660 	u8         opcode[0x10];
7661 	u8         reserved_at_10[0x10];
7662 
7663 	u8         reserved_at_20[0x10];
7664 	u8         op_mod[0x10];
7665 
7666 	u8         other_vport[0x1];
7667 	u8         reserved_at_41[0xf];
7668 	u8         vport_number[0x10];
7669 
7670 	u8         reserved_at_60[0x20];
7671 
7672 	u8         table_type[0x8];
7673 	u8         reserved_at_88[0x18];
7674 
7675 	u8         reserved_at_a0[0x20];
7676 
7677 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
7678 };
7679 
7680 struct mlx5_ifc_create_flow_group_out_bits {
7681 	u8         status[0x8];
7682 	u8         reserved_0[0x18];
7683 
7684 	u8         syndrome[0x20];
7685 
7686 	u8         reserved_1[0x8];
7687 	u8         group_id[0x18];
7688 
7689 	u8         reserved_2[0x20];
7690 };
7691 
7692 enum {
7693 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
7694 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
7695 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
7696 };
7697 
7698 struct mlx5_ifc_create_flow_group_in_bits {
7699 	u8         opcode[0x10];
7700 	u8         reserved_0[0x10];
7701 
7702 	u8         reserved_1[0x10];
7703 	u8         op_mod[0x10];
7704 
7705 	u8         other_vport[0x1];
7706 	u8         reserved_2[0xf];
7707 	u8         vport_number[0x10];
7708 
7709 	u8         reserved_3[0x20];
7710 
7711 	u8         table_type[0x8];
7712 	u8         reserved_4[0x18];
7713 
7714 	u8         reserved_5[0x8];
7715 	u8         table_id[0x18];
7716 
7717 	u8         reserved_6[0x20];
7718 
7719 	u8         start_flow_index[0x20];
7720 
7721 	u8         reserved_7[0x20];
7722 
7723 	u8         end_flow_index[0x20];
7724 
7725 	u8         reserved_8[0xa0];
7726 
7727 	u8         reserved_9[0x18];
7728 	u8         match_criteria_enable[0x8];
7729 
7730 	struct mlx5_ifc_fte_match_param_bits match_criteria;
7731 
7732 	u8         reserved_10[0xe00];
7733 };
7734 
7735 struct mlx5_ifc_create_encryption_key_out_bits {
7736 	u8         status[0x8];
7737 	u8         reserved_at_8[0x18];
7738 
7739 	u8         syndrome[0x20];
7740 
7741 	u8         obj_id[0x20];
7742 
7743 	u8         reserved_at_60[0x20];
7744 };
7745 
7746 struct mlx5_ifc_create_encryption_key_in_bits {
7747 	u8         opcode[0x10];
7748 	u8         reserved_at_10[0x10];
7749 
7750 	u8         reserved_at_20[0x10];
7751 	u8         obj_type[0x10];
7752 
7753 	u8         reserved_at_40[0x40];
7754 
7755 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
7756 };
7757 
7758 struct mlx5_ifc_create_eq_out_bits {
7759 	u8         status[0x8];
7760 	u8         reserved_0[0x18];
7761 
7762 	u8         syndrome[0x20];
7763 
7764 	u8         reserved_1[0x18];
7765 	u8         eq_number[0x8];
7766 
7767 	u8         reserved_2[0x20];
7768 };
7769 
7770 struct mlx5_ifc_create_eq_in_bits {
7771 	u8         opcode[0x10];
7772 	u8         reserved_0[0x10];
7773 
7774 	u8         reserved_1[0x10];
7775 	u8         op_mod[0x10];
7776 
7777 	u8         reserved_2[0x40];
7778 
7779 	struct mlx5_ifc_eqc_bits eq_context_entry;
7780 
7781 	u8         reserved_3[0x40];
7782 
7783 	u8         event_bitmask[0x40];
7784 
7785 	u8         reserved_4[0x580];
7786 
7787 	u8         pas[0][0x40];
7788 };
7789 
7790 struct mlx5_ifc_create_dct_out_bits {
7791 	u8         status[0x8];
7792 	u8         reserved_0[0x18];
7793 
7794 	u8         syndrome[0x20];
7795 
7796 	u8         reserved_1[0x8];
7797 	u8         dctn[0x18];
7798 
7799 	u8         reserved_2[0x20];
7800 };
7801 
7802 struct mlx5_ifc_create_dct_in_bits {
7803 	u8         opcode[0x10];
7804 	u8         uid[0x10];
7805 
7806 	u8         reserved_1[0x10];
7807 	u8         op_mod[0x10];
7808 
7809 	u8         reserved_2[0x40];
7810 
7811 	struct mlx5_ifc_dctc_bits dct_context_entry;
7812 
7813 	u8         reserved_3[0x180];
7814 };
7815 
7816 struct mlx5_ifc_create_cq_out_bits {
7817 	u8         status[0x8];
7818 	u8         reserved_0[0x18];
7819 
7820 	u8         syndrome[0x20];
7821 
7822 	u8         reserved_1[0x8];
7823 	u8         cqn[0x18];
7824 
7825 	u8         reserved_2[0x20];
7826 };
7827 
7828 struct mlx5_ifc_create_cq_in_bits {
7829 	u8         opcode[0x10];
7830 	u8         uid[0x10];
7831 
7832 	u8         reserved_1[0x10];
7833 	u8         op_mod[0x10];
7834 
7835 	u8         reserved_2[0x40];
7836 
7837 	struct mlx5_ifc_cqc_bits cq_context;
7838 
7839 	u8         reserved_at_280[0x60];
7840 
7841 	u8         cq_umem_valid[0x1];
7842 	u8         reserved_at_2e1[0x59f];
7843 
7844 	u8         pas[0][0x40];
7845 };
7846 
7847 struct mlx5_ifc_config_int_moderation_out_bits {
7848 	u8         status[0x8];
7849 	u8         reserved_0[0x18];
7850 
7851 	u8         syndrome[0x20];
7852 
7853 	u8         reserved_1[0x4];
7854 	u8         min_delay[0xc];
7855 	u8         int_vector[0x10];
7856 
7857 	u8         reserved_2[0x20];
7858 };
7859 
7860 enum {
7861 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7862 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7863 };
7864 
7865 struct mlx5_ifc_config_int_moderation_in_bits {
7866 	u8         opcode[0x10];
7867 	u8         reserved_0[0x10];
7868 
7869 	u8         reserved_1[0x10];
7870 	u8         op_mod[0x10];
7871 
7872 	u8         reserved_2[0x4];
7873 	u8         min_delay[0xc];
7874 	u8         int_vector[0x10];
7875 
7876 	u8         reserved_3[0x20];
7877 };
7878 
7879 struct mlx5_ifc_attach_to_mcg_out_bits {
7880 	u8         status[0x8];
7881 	u8         reserved_0[0x18];
7882 
7883 	u8         syndrome[0x20];
7884 
7885 	u8         reserved_1[0x40];
7886 };
7887 
7888 struct mlx5_ifc_attach_to_mcg_in_bits {
7889 	u8         opcode[0x10];
7890 	u8         uid[0x10];
7891 
7892 	u8         reserved_1[0x10];
7893 	u8         op_mod[0x10];
7894 
7895 	u8         reserved_2[0x8];
7896 	u8         qpn[0x18];
7897 
7898 	u8         reserved_3[0x20];
7899 
7900 	u8         multicast_gid[16][0x8];
7901 };
7902 
7903 struct mlx5_ifc_arm_xrq_out_bits {
7904 	u8         status[0x8];
7905 	u8         reserved_at_8[0x18];
7906 
7907 	u8         syndrome[0x20];
7908 
7909 	u8         reserved_at_40[0x40];
7910 };
7911 
7912 struct mlx5_ifc_arm_xrq_in_bits {
7913 	u8         opcode[0x10];
7914 	u8         reserved_at_10[0x10];
7915 
7916 	u8         reserved_at_20[0x10];
7917 	u8         op_mod[0x10];
7918 
7919 	u8         reserved_at_40[0x8];
7920 	u8         xrqn[0x18];
7921 
7922 	u8         reserved_at_60[0x10];
7923 	u8         lwm[0x10];
7924 };
7925 
7926 struct mlx5_ifc_arm_xrc_srq_out_bits {
7927 	u8         status[0x8];
7928 	u8         reserved_0[0x18];
7929 
7930 	u8         syndrome[0x20];
7931 
7932 	u8         reserved_1[0x40];
7933 };
7934 
7935 enum {
7936 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7937 };
7938 
7939 struct mlx5_ifc_arm_xrc_srq_in_bits {
7940 	u8         opcode[0x10];
7941 	u8         uid[0x10];
7942 
7943 	u8         reserved_1[0x10];
7944 	u8         op_mod[0x10];
7945 
7946 	u8         reserved_2[0x8];
7947 	u8         xrc_srqn[0x18];
7948 
7949 	u8         reserved_3[0x10];
7950 	u8         lwm[0x10];
7951 };
7952 
7953 struct mlx5_ifc_arm_rq_out_bits {
7954 	u8         status[0x8];
7955 	u8         reserved_0[0x18];
7956 
7957 	u8         syndrome[0x20];
7958 
7959 	u8         reserved_1[0x40];
7960 };
7961 
7962 enum {
7963 	MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
7964 };
7965 
7966 struct mlx5_ifc_arm_rq_in_bits {
7967 	u8         opcode[0x10];
7968 	u8         uid[0x10];
7969 
7970 	u8         reserved_1[0x10];
7971 	u8         op_mod[0x10];
7972 
7973 	u8         reserved_2[0x8];
7974 	u8         srq_number[0x18];
7975 
7976 	u8         reserved_3[0x10];
7977 	u8         lwm[0x10];
7978 };
7979 
7980 struct mlx5_ifc_arm_dct_out_bits {
7981 	u8         status[0x8];
7982 	u8         reserved_0[0x18];
7983 
7984 	u8         syndrome[0x20];
7985 
7986 	u8         reserved_1[0x40];
7987 };
7988 
7989 struct mlx5_ifc_arm_dct_in_bits {
7990 	u8         opcode[0x10];
7991 	u8         reserved_0[0x10];
7992 
7993 	u8         reserved_1[0x10];
7994 	u8         op_mod[0x10];
7995 
7996 	u8         reserved_2[0x8];
7997 	u8         dctn[0x18];
7998 
7999 	u8         reserved_3[0x20];
8000 };
8001 
8002 struct mlx5_ifc_alloc_xrcd_out_bits {
8003 	u8         status[0x8];
8004 	u8         reserved_0[0x18];
8005 
8006 	u8         syndrome[0x20];
8007 
8008 	u8         reserved_1[0x8];
8009 	u8         xrcd[0x18];
8010 
8011 	u8         reserved_2[0x20];
8012 };
8013 
8014 struct mlx5_ifc_alloc_xrcd_in_bits {
8015 	u8         opcode[0x10];
8016 	u8         uid[0x10];
8017 
8018 	u8         reserved_1[0x10];
8019 	u8         op_mod[0x10];
8020 
8021 	u8         reserved_2[0x40];
8022 };
8023 
8024 struct mlx5_ifc_alloc_uar_out_bits {
8025 	u8         status[0x8];
8026 	u8         reserved_0[0x18];
8027 
8028 	u8         syndrome[0x20];
8029 
8030 	u8         reserved_1[0x8];
8031 	u8         uar[0x18];
8032 
8033 	u8         reserved_2[0x20];
8034 };
8035 
8036 struct mlx5_ifc_alloc_uar_in_bits {
8037 	u8         opcode[0x10];
8038 	u8         reserved_0[0x10];
8039 
8040 	u8         reserved_1[0x10];
8041 	u8         op_mod[0x10];
8042 
8043 	u8         reserved_2[0x40];
8044 };
8045 
8046 struct mlx5_ifc_alloc_transport_domain_out_bits {
8047 	u8         status[0x8];
8048 	u8         reserved_0[0x18];
8049 
8050 	u8         syndrome[0x20];
8051 
8052 	u8         reserved_1[0x8];
8053 	u8         transport_domain[0x18];
8054 
8055 	u8         reserved_2[0x20];
8056 };
8057 
8058 struct mlx5_ifc_alloc_transport_domain_in_bits {
8059 	u8         opcode[0x10];
8060 	u8         uid[0x10];
8061 
8062 	u8         reserved_1[0x10];
8063 	u8         op_mod[0x10];
8064 
8065 	u8         reserved_2[0x40];
8066 };
8067 
8068 struct mlx5_ifc_alloc_q_counter_out_bits {
8069 	u8         status[0x8];
8070 	u8         reserved_0[0x18];
8071 
8072 	u8         syndrome[0x20];
8073 
8074 	u8         reserved_1[0x18];
8075 	u8         counter_set_id[0x8];
8076 
8077 	u8         reserved_2[0x20];
8078 };
8079 
8080 struct mlx5_ifc_alloc_q_counter_in_bits {
8081 	u8         opcode[0x10];
8082 	u8         uid[0x10];
8083 
8084 	u8         reserved_1[0x10];
8085 	u8         op_mod[0x10];
8086 
8087 	u8         reserved_2[0x40];
8088 };
8089 
8090 struct mlx5_ifc_alloc_pd_out_bits {
8091 	u8         status[0x8];
8092 	u8         reserved_0[0x18];
8093 
8094 	u8         syndrome[0x20];
8095 
8096 	u8         reserved_1[0x8];
8097 	u8         pd[0x18];
8098 
8099 	u8         reserved_2[0x20];
8100 };
8101 
8102 struct mlx5_ifc_alloc_pd_in_bits {
8103 	u8         opcode[0x10];
8104 	u8         uid[0x10];
8105 
8106 	u8         reserved_1[0x10];
8107 	u8         op_mod[0x10];
8108 
8109 	u8         reserved_2[0x40];
8110 };
8111 
8112 struct mlx5_ifc_alloc_flow_counter_out_bits {
8113 	u8         status[0x8];
8114 	u8         reserved_at_8[0x18];
8115 
8116 	u8         syndrome[0x20];
8117 
8118 	u8         flow_counter_id[0x20];
8119 
8120 	u8         reserved_at_60[0x20];
8121 };
8122 
8123 struct mlx5_ifc_alloc_flow_counter_in_bits {
8124 	u8         opcode[0x10];
8125 	u8         reserved_at_10[0x10];
8126 
8127 	u8         reserved_at_20[0x10];
8128 	u8         op_mod[0x10];
8129 
8130 	u8         reserved_at_40[0x38];
8131 	u8         flow_counter_bulk[0x8];
8132 };
8133 
8134 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8135 	u8         status[0x8];
8136 	u8         reserved_0[0x18];
8137 
8138 	u8         syndrome[0x20];
8139 
8140 	u8         reserved_1[0x40];
8141 };
8142 
8143 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8144 	u8         opcode[0x10];
8145 	u8         reserved_0[0x10];
8146 
8147 	u8         reserved_1[0x10];
8148 	u8         op_mod[0x10];
8149 
8150 	u8         reserved_2[0x20];
8151 
8152 	u8         reserved_3[0x10];
8153 	u8         vxlan_udp_port[0x10];
8154 };
8155 
8156 struct mlx5_ifc_activate_tracer_out_bits {
8157 	u8         status[0x8];
8158 	u8         reserved_0[0x18];
8159 
8160 	u8         syndrome[0x20];
8161 
8162 	u8         reserved_1[0x40];
8163 };
8164 
8165 struct mlx5_ifc_activate_tracer_in_bits {
8166 	u8         opcode[0x10];
8167 	u8         reserved_0[0x10];
8168 
8169 	u8         reserved_1[0x10];
8170 	u8         op_mod[0x10];
8171 
8172 	u8         mkey[0x20];
8173 
8174 	u8         reserved_2[0x20];
8175 };
8176 
8177 struct mlx5_ifc_set_rate_limit_out_bits {
8178 	u8         status[0x8];
8179 	u8         reserved_at_8[0x18];
8180 
8181 	u8         syndrome[0x20];
8182 
8183 	u8         reserved_at_40[0x40];
8184 };
8185 
8186 struct mlx5_ifc_set_rate_limit_in_bits {
8187 	u8         opcode[0x10];
8188 	u8         uid[0x10];
8189 
8190 	u8         reserved_at_20[0x10];
8191 	u8         op_mod[0x10];
8192 
8193 	u8         reserved_at_40[0x10];
8194 	u8         rate_limit_index[0x10];
8195 
8196 	u8         reserved_at_60[0x20];
8197 
8198 	u8         rate_limit[0x20];
8199 
8200 	u8         burst_upper_bound[0x20];
8201 
8202 	u8         reserved_at_c0[0x10];
8203 	u8         typical_packet_size[0x10];
8204 
8205 	u8         reserved_at_e0[0x120];
8206 };
8207 
8208 struct mlx5_ifc_access_register_out_bits {
8209 	u8         status[0x8];
8210 	u8         reserved_0[0x18];
8211 
8212 	u8         syndrome[0x20];
8213 
8214 	u8         reserved_1[0x40];
8215 
8216 	u8         register_data[0][0x20];
8217 };
8218 
8219 enum {
8220 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8221 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8222 };
8223 
8224 struct mlx5_ifc_access_register_in_bits {
8225 	u8         opcode[0x10];
8226 	u8         reserved_0[0x10];
8227 
8228 	u8         reserved_1[0x10];
8229 	u8         op_mod[0x10];
8230 
8231 	u8         reserved_2[0x10];
8232 	u8         register_id[0x10];
8233 
8234 	u8         argument[0x20];
8235 
8236 	u8         register_data[0][0x20];
8237 };
8238 
8239 struct mlx5_ifc_sltp_reg_bits {
8240 	u8         status[0x4];
8241 	u8         version[0x4];
8242 	u8         local_port[0x8];
8243 	u8         pnat[0x2];
8244 	u8         reserved_0[0x2];
8245 	u8         lane[0x4];
8246 	u8         reserved_1[0x8];
8247 
8248 	u8         reserved_2[0x20];
8249 
8250 	u8         reserved_3[0x7];
8251 	u8         polarity[0x1];
8252 	u8         ob_tap0[0x8];
8253 	u8         ob_tap1[0x8];
8254 	u8         ob_tap2[0x8];
8255 
8256 	u8         reserved_4[0xc];
8257 	u8         ob_preemp_mode[0x4];
8258 	u8         ob_reg[0x8];
8259 	u8         ob_bias[0x8];
8260 
8261 	u8         reserved_5[0x20];
8262 };
8263 
8264 struct mlx5_ifc_slrp_reg_bits {
8265 	u8         status[0x4];
8266 	u8         version[0x4];
8267 	u8         local_port[0x8];
8268 	u8         pnat[0x2];
8269 	u8         reserved_0[0x2];
8270 	u8         lane[0x4];
8271 	u8         reserved_1[0x8];
8272 
8273 	u8         ib_sel[0x2];
8274 	u8         reserved_2[0x11];
8275 	u8         dp_sel[0x1];
8276 	u8         dp90sel[0x4];
8277 	u8         mix90phase[0x8];
8278 
8279 	u8         ffe_tap0[0x8];
8280 	u8         ffe_tap1[0x8];
8281 	u8         ffe_tap2[0x8];
8282 	u8         ffe_tap3[0x8];
8283 
8284 	u8         ffe_tap4[0x8];
8285 	u8         ffe_tap5[0x8];
8286 	u8         ffe_tap6[0x8];
8287 	u8         ffe_tap7[0x8];
8288 
8289 	u8         ffe_tap8[0x8];
8290 	u8         mixerbias_tap_amp[0x8];
8291 	u8         reserved_3[0x7];
8292 	u8         ffe_tap_en[0x9];
8293 
8294 	u8         ffe_tap_offset0[0x8];
8295 	u8         ffe_tap_offset1[0x8];
8296 	u8         slicer_offset0[0x10];
8297 
8298 	u8         mixer_offset0[0x10];
8299 	u8         mixer_offset1[0x10];
8300 
8301 	u8         mixerbgn_inp[0x8];
8302 	u8         mixerbgn_inn[0x8];
8303 	u8         mixerbgn_refp[0x8];
8304 	u8         mixerbgn_refn[0x8];
8305 
8306 	u8         sel_slicer_lctrl_h[0x1];
8307 	u8         sel_slicer_lctrl_l[0x1];
8308 	u8         reserved_4[0x1];
8309 	u8         ref_mixer_vreg[0x5];
8310 	u8         slicer_gctrl[0x8];
8311 	u8         lctrl_input[0x8];
8312 	u8         mixer_offset_cm1[0x8];
8313 
8314 	u8         common_mode[0x6];
8315 	u8         reserved_5[0x1];
8316 	u8         mixer_offset_cm0[0x9];
8317 	u8         reserved_6[0x7];
8318 	u8         slicer_offset_cm[0x9];
8319 };
8320 
8321 struct mlx5_ifc_slrg_reg_bits {
8322 	u8         status[0x4];
8323 	u8         version[0x4];
8324 	u8         local_port[0x8];
8325 	u8         pnat[0x2];
8326 	u8         reserved_0[0x2];
8327 	u8         lane[0x4];
8328 	u8         reserved_1[0x8];
8329 
8330 	u8         time_to_link_up[0x10];
8331 	u8         reserved_2[0xc];
8332 	u8         grade_lane_speed[0x4];
8333 
8334 	u8         grade_version[0x8];
8335 	u8         grade[0x18];
8336 
8337 	u8         reserved_3[0x4];
8338 	u8         height_grade_type[0x4];
8339 	u8         height_grade[0x18];
8340 
8341 	u8         height_dz[0x10];
8342 	u8         height_dv[0x10];
8343 
8344 	u8         reserved_4[0x10];
8345 	u8         height_sigma[0x10];
8346 
8347 	u8         reserved_5[0x20];
8348 
8349 	u8         reserved_6[0x4];
8350 	u8         phase_grade_type[0x4];
8351 	u8         phase_grade[0x18];
8352 
8353 	u8         reserved_7[0x8];
8354 	u8         phase_eo_pos[0x8];
8355 	u8         reserved_8[0x8];
8356 	u8         phase_eo_neg[0x8];
8357 
8358 	u8         ffe_set_tested[0x10];
8359 	u8         test_errors_per_lane[0x10];
8360 };
8361 
8362 struct mlx5_ifc_pvlc_reg_bits {
8363 	u8         reserved_0[0x8];
8364 	u8         local_port[0x8];
8365 	u8         reserved_1[0x10];
8366 
8367 	u8         reserved_2[0x1c];
8368 	u8         vl_hw_cap[0x4];
8369 
8370 	u8         reserved_3[0x1c];
8371 	u8         vl_admin[0x4];
8372 
8373 	u8         reserved_4[0x1c];
8374 	u8         vl_operational[0x4];
8375 };
8376 
8377 struct mlx5_ifc_pude_reg_bits {
8378 	u8         swid[0x8];
8379 	u8         local_port[0x8];
8380 	u8         reserved_0[0x4];
8381 	u8         admin_status[0x4];
8382 	u8         reserved_1[0x4];
8383 	u8         oper_status[0x4];
8384 
8385 	u8         reserved_2[0x60];
8386 };
8387 
8388 enum {
8389 	MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
8390 	MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
8391 };
8392 
8393 struct mlx5_ifc_ptys_reg_bits {
8394 	u8         reserved_0[0x1];
8395 	u8         an_disable_admin[0x1];
8396 	u8         an_disable_cap[0x1];
8397 	u8         reserved_1[0x4];
8398 	u8         force_tx_aba_param[0x1];
8399 	u8         local_port[0x8];
8400 	u8         reserved_2[0xd];
8401 	u8         proto_mask[0x3];
8402 
8403 	u8         an_status[0x4];
8404 	u8         reserved_3[0xc];
8405 	u8         data_rate_oper[0x10];
8406 
8407 	u8         ext_eth_proto_capability[0x20];
8408 
8409 	u8         eth_proto_capability[0x20];
8410 
8411 	u8         ib_link_width_capability[0x10];
8412 	u8         ib_proto_capability[0x10];
8413 
8414 	u8         ext_eth_proto_admin[0x20];
8415 
8416 	u8         eth_proto_admin[0x20];
8417 
8418 	u8         ib_link_width_admin[0x10];
8419 	u8         ib_proto_admin[0x10];
8420 
8421 	u8         ext_eth_proto_oper[0x20];
8422 
8423 	u8         eth_proto_oper[0x20];
8424 
8425 	u8         ib_link_width_oper[0x10];
8426 	u8         ib_proto_oper[0x10];
8427 
8428 	u8         reserved_4[0x1c];
8429 	u8         connector_type[0x4];
8430 
8431 	u8         eth_proto_lp_advertise[0x20];
8432 
8433 	u8         reserved_5[0x60];
8434 };
8435 
8436 struct mlx5_ifc_ptas_reg_bits {
8437 	u8         reserved_0[0x20];
8438 
8439 	u8         algorithm_options[0x10];
8440 	u8         reserved_1[0x4];
8441 	u8         repetitions_mode[0x4];
8442 	u8         num_of_repetitions[0x8];
8443 
8444 	u8         grade_version[0x8];
8445 	u8         height_grade_type[0x4];
8446 	u8         phase_grade_type[0x4];
8447 	u8         height_grade_weight[0x8];
8448 	u8         phase_grade_weight[0x8];
8449 
8450 	u8         gisim_measure_bits[0x10];
8451 	u8         adaptive_tap_measure_bits[0x10];
8452 
8453 	u8         ber_bath_high_error_threshold[0x10];
8454 	u8         ber_bath_mid_error_threshold[0x10];
8455 
8456 	u8         ber_bath_low_error_threshold[0x10];
8457 	u8         one_ratio_high_threshold[0x10];
8458 
8459 	u8         one_ratio_high_mid_threshold[0x10];
8460 	u8         one_ratio_low_mid_threshold[0x10];
8461 
8462 	u8         one_ratio_low_threshold[0x10];
8463 	u8         ndeo_error_threshold[0x10];
8464 
8465 	u8         mixer_offset_step_size[0x10];
8466 	u8         reserved_2[0x8];
8467 	u8         mix90_phase_for_voltage_bath[0x8];
8468 
8469 	u8         mixer_offset_start[0x10];
8470 	u8         mixer_offset_end[0x10];
8471 
8472 	u8         reserved_3[0x15];
8473 	u8         ber_test_time[0xb];
8474 };
8475 
8476 struct mlx5_ifc_pspa_reg_bits {
8477 	u8         swid[0x8];
8478 	u8         local_port[0x8];
8479 	u8         sub_port[0x8];
8480 	u8         reserved_0[0x8];
8481 
8482 	u8         reserved_1[0x20];
8483 };
8484 
8485 struct mlx5_ifc_ppsc_reg_bits {
8486 	u8         reserved_0[0x8];
8487 	u8         local_port[0x8];
8488 	u8         reserved_1[0x10];
8489 
8490 	u8         reserved_2[0x60];
8491 
8492 	u8         reserved_3[0x1c];
8493 	u8         wrps_admin[0x4];
8494 
8495 	u8         reserved_4[0x1c];
8496 	u8         wrps_status[0x4];
8497 
8498 	u8         up_th_vld[0x1];
8499 	u8         down_th_vld[0x1];
8500 	u8         reserved_5[0x6];
8501 	u8         up_threshold[0x8];
8502 	u8         reserved_6[0x8];
8503 	u8         down_threshold[0x8];
8504 
8505 	u8         reserved_7[0x20];
8506 
8507 	u8         reserved_8[0x1c];
8508 	u8         srps_admin[0x4];
8509 
8510 	u8         reserved_9[0x60];
8511 };
8512 
8513 struct mlx5_ifc_pplr_reg_bits {
8514 	u8         reserved_0[0x8];
8515 	u8         local_port[0x8];
8516 	u8         reserved_1[0x10];
8517 
8518 	u8         reserved_2[0x8];
8519 	u8         lb_cap[0x8];
8520 	u8         reserved_3[0x8];
8521 	u8         lb_en[0x8];
8522 };
8523 
8524 struct mlx5_ifc_pplm_reg_bits {
8525 	u8         reserved_at_0[0x8];
8526 	u8	   local_port[0x8];
8527 	u8	   reserved_at_10[0x10];
8528 
8529 	u8	   reserved_at_20[0x20];
8530 
8531 	u8	   port_profile_mode[0x8];
8532 	u8	   static_port_profile[0x8];
8533 	u8	   active_port_profile[0x8];
8534 	u8	   reserved_at_58[0x8];
8535 
8536 	u8	   retransmission_active[0x8];
8537 	u8	   fec_mode_active[0x18];
8538 
8539 	u8	   rs_fec_correction_bypass_cap[0x4];
8540 	u8	   reserved_at_84[0x8];
8541 	u8	   fec_override_cap_56g[0x4];
8542 	u8	   fec_override_cap_100g[0x4];
8543 	u8	   fec_override_cap_50g[0x4];
8544 	u8	   fec_override_cap_25g[0x4];
8545 	u8	   fec_override_cap_10g_40g[0x4];
8546 
8547 	u8	   rs_fec_correction_bypass_admin[0x4];
8548 	u8	   reserved_at_a4[0x8];
8549 	u8	   fec_override_admin_56g[0x4];
8550 	u8	   fec_override_admin_100g[0x4];
8551 	u8	   fec_override_admin_50g[0x4];
8552 	u8	   fec_override_admin_25g[0x4];
8553 	u8	   fec_override_admin_10g_40g[0x4];
8554 
8555 	u8	   fec_override_cap_400g_8x[0x10];
8556 	u8	   fec_override_cap_200g_4x[0x10];
8557 	u8	   fec_override_cap_100g_2x[0x10];
8558 	u8	   fec_override_cap_50g_1x[0x10];
8559 
8560 	u8	   fec_override_admin_400g_8x[0x10];
8561 	u8	   fec_override_admin_200g_4x[0x10];
8562 	u8	   fec_override_admin_100g_2x[0x10];
8563 	u8	   fec_override_admin_50g_1x[0x10];
8564 
8565 	u8	   reserved_at_140[0x140];
8566 };
8567 
8568 struct mlx5_ifc_ppll_reg_bits {
8569 	u8         num_pll_groups[0x8];
8570 	u8         pll_group[0x8];
8571 	u8         reserved_0[0x4];
8572 	u8         num_plls[0x4];
8573 	u8         reserved_1[0x8];
8574 
8575 	u8         reserved_2[0x1f];
8576 	u8         ae[0x1];
8577 
8578 	u8         pll_status[4][0x40];
8579 };
8580 
8581 struct mlx5_ifc_ppad_reg_bits {
8582 	u8         reserved_0[0x3];
8583 	u8         single_mac[0x1];
8584 	u8         reserved_1[0x4];
8585 	u8         local_port[0x8];
8586 	u8         mac_47_32[0x10];
8587 
8588 	u8         mac_31_0[0x20];
8589 
8590 	u8         reserved_2[0x40];
8591 };
8592 
8593 struct mlx5_ifc_pmtu_reg_bits {
8594 	u8         reserved_0[0x8];
8595 	u8         local_port[0x8];
8596 	u8         reserved_1[0x10];
8597 
8598 	u8         max_mtu[0x10];
8599 	u8         reserved_2[0x10];
8600 
8601 	u8         admin_mtu[0x10];
8602 	u8         reserved_3[0x10];
8603 
8604 	u8         oper_mtu[0x10];
8605 	u8         reserved_4[0x10];
8606 };
8607 
8608 struct mlx5_ifc_pmpr_reg_bits {
8609 	u8         reserved_0[0x8];
8610 	u8         module[0x8];
8611 	u8         reserved_1[0x10];
8612 
8613 	u8         reserved_2[0x18];
8614 	u8         attenuation_5g[0x8];
8615 
8616 	u8         reserved_3[0x18];
8617 	u8         attenuation_7g[0x8];
8618 
8619 	u8         reserved_4[0x18];
8620 	u8         attenuation_12g[0x8];
8621 };
8622 
8623 struct mlx5_ifc_pmpe_reg_bits {
8624 	u8         reserved_0[0x8];
8625 	u8         module[0x8];
8626 	u8         reserved_1[0xc];
8627 	u8         module_status[0x4];
8628 
8629 	u8         reserved_2[0x14];
8630 	u8         error_type[0x4];
8631 	u8         reserved_3[0x8];
8632 
8633 	u8         reserved_4[0x40];
8634 };
8635 
8636 struct mlx5_ifc_pmpc_reg_bits {
8637 	u8         module_state_updated[32][0x8];
8638 };
8639 
8640 struct mlx5_ifc_pmlpn_reg_bits {
8641 	u8         reserved_0[0x4];
8642 	u8         mlpn_status[0x4];
8643 	u8         local_port[0x8];
8644 	u8         reserved_1[0x10];
8645 
8646 	u8         e[0x1];
8647 	u8         reserved_2[0x1f];
8648 };
8649 
8650 struct mlx5_ifc_pmlp_reg_bits {
8651 	u8         rxtx[0x1];
8652 	u8         reserved_0[0x7];
8653 	u8         local_port[0x8];
8654 	u8         reserved_1[0x8];
8655 	u8         width[0x8];
8656 
8657 	u8         lane0_module_mapping[0x20];
8658 
8659 	u8         lane1_module_mapping[0x20];
8660 
8661 	u8         lane2_module_mapping[0x20];
8662 
8663 	u8         lane3_module_mapping[0x20];
8664 
8665 	u8         reserved_2[0x160];
8666 };
8667 
8668 struct mlx5_ifc_pmaos_reg_bits {
8669 	u8         reserved_0[0x8];
8670 	u8         module[0x8];
8671 	u8         reserved_1[0x4];
8672 	u8         admin_status[0x4];
8673 	u8         reserved_2[0x4];
8674 	u8         oper_status[0x4];
8675 
8676 	u8         ase[0x1];
8677 	u8         ee[0x1];
8678 	u8         reserved_3[0x12];
8679 	u8         error_type[0x4];
8680 	u8         reserved_4[0x6];
8681 	u8         e[0x2];
8682 
8683 	u8         reserved_5[0x40];
8684 };
8685 
8686 struct mlx5_ifc_plpc_reg_bits {
8687 	u8         reserved_0[0x4];
8688 	u8         profile_id[0xc];
8689 	u8         reserved_1[0x4];
8690 	u8         proto_mask[0x4];
8691 	u8         reserved_2[0x8];
8692 
8693 	u8         reserved_3[0x10];
8694 	u8         lane_speed[0x10];
8695 
8696 	u8         reserved_4[0x17];
8697 	u8         lpbf[0x1];
8698 	u8         fec_mode_policy[0x8];
8699 
8700 	u8         retransmission_capability[0x8];
8701 	u8         fec_mode_capability[0x18];
8702 
8703 	u8         retransmission_support_admin[0x8];
8704 	u8         fec_mode_support_admin[0x18];
8705 
8706 	u8         retransmission_request_admin[0x8];
8707 	u8         fec_mode_request_admin[0x18];
8708 
8709 	u8         reserved_5[0x80];
8710 };
8711 
8712 struct mlx5_ifc_pll_status_data_bits {
8713 	u8         reserved_0[0x1];
8714 	u8         lock_cal[0x1];
8715 	u8         lock_status[0x2];
8716 	u8         reserved_1[0x2];
8717 	u8         algo_f_ctrl[0xa];
8718 	u8         analog_algo_num_var[0x6];
8719 	u8         f_ctrl_measure[0xa];
8720 
8721 	u8         reserved_2[0x2];
8722 	u8         analog_var[0x6];
8723 	u8         reserved_3[0x2];
8724 	u8         high_var[0x6];
8725 	u8         reserved_4[0x2];
8726 	u8         low_var[0x6];
8727 	u8         reserved_5[0x2];
8728 	u8         mid_val[0x6];
8729 };
8730 
8731 struct mlx5_ifc_plib_reg_bits {
8732 	u8         reserved_0[0x8];
8733 	u8         local_port[0x8];
8734 	u8         reserved_1[0x8];
8735 	u8         ib_port[0x8];
8736 
8737 	u8         reserved_2[0x60];
8738 };
8739 
8740 struct mlx5_ifc_plbf_reg_bits {
8741 	u8         reserved_0[0x8];
8742 	u8         local_port[0x8];
8743 	u8         reserved_1[0xd];
8744 	u8         lbf_mode[0x3];
8745 
8746 	u8         reserved_2[0x20];
8747 };
8748 
8749 struct mlx5_ifc_pipg_reg_bits {
8750 	u8         reserved_0[0x8];
8751 	u8         local_port[0x8];
8752 	u8         reserved_1[0x10];
8753 
8754 	u8         dic[0x1];
8755 	u8         reserved_2[0x19];
8756 	u8         ipg[0x4];
8757 	u8         reserved_3[0x2];
8758 };
8759 
8760 struct mlx5_ifc_pifr_reg_bits {
8761 	u8         reserved_0[0x8];
8762 	u8         local_port[0x8];
8763 	u8         reserved_1[0x10];
8764 
8765 	u8         reserved_2[0xe0];
8766 
8767 	u8         port_filter[8][0x20];
8768 
8769 	u8         port_filter_update_en[8][0x20];
8770 };
8771 
8772 struct mlx5_ifc_phys_layer_cntrs_bits {
8773 	u8         time_since_last_clear_high[0x20];
8774 
8775 	u8         time_since_last_clear_low[0x20];
8776 
8777 	u8         symbol_errors_high[0x20];
8778 
8779 	u8         symbol_errors_low[0x20];
8780 
8781 	u8         sync_headers_errors_high[0x20];
8782 
8783 	u8         sync_headers_errors_low[0x20];
8784 
8785 	u8         edpl_bip_errors_lane0_high[0x20];
8786 
8787 	u8         edpl_bip_errors_lane0_low[0x20];
8788 
8789 	u8         edpl_bip_errors_lane1_high[0x20];
8790 
8791 	u8         edpl_bip_errors_lane1_low[0x20];
8792 
8793 	u8         edpl_bip_errors_lane2_high[0x20];
8794 
8795 	u8         edpl_bip_errors_lane2_low[0x20];
8796 
8797 	u8         edpl_bip_errors_lane3_high[0x20];
8798 
8799 	u8         edpl_bip_errors_lane3_low[0x20];
8800 
8801 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
8802 
8803 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
8804 
8805 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
8806 
8807 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
8808 
8809 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
8810 
8811 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
8812 
8813 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
8814 
8815 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
8816 
8817 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
8818 
8819 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
8820 
8821 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
8822 
8823 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
8824 
8825 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
8826 
8827 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
8828 
8829 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
8830 
8831 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
8832 
8833 	u8         rs_fec_corrected_blocks_high[0x20];
8834 
8835 	u8         rs_fec_corrected_blocks_low[0x20];
8836 
8837 	u8         rs_fec_uncorrectable_blocks_high[0x20];
8838 
8839 	u8         rs_fec_uncorrectable_blocks_low[0x20];
8840 
8841 	u8         rs_fec_no_errors_blocks_high[0x20];
8842 
8843 	u8         rs_fec_no_errors_blocks_low[0x20];
8844 
8845 	u8         rs_fec_single_error_blocks_high[0x20];
8846 
8847 	u8         rs_fec_single_error_blocks_low[0x20];
8848 
8849 	u8         rs_fec_corrected_symbols_total_high[0x20];
8850 
8851 	u8         rs_fec_corrected_symbols_total_low[0x20];
8852 
8853 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
8854 
8855 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
8856 
8857 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
8858 
8859 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
8860 
8861 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
8862 
8863 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
8864 
8865 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
8866 
8867 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
8868 
8869 	u8         link_down_events[0x20];
8870 
8871 	u8         successful_recovery_events[0x20];
8872 
8873 	u8         reserved_0[0x180];
8874 };
8875 
8876 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
8877 	u8	   symbol_error_counter[0x10];
8878 
8879 	u8         link_error_recovery_counter[0x8];
8880 
8881 	u8         link_downed_counter[0x8];
8882 
8883 	u8         port_rcv_errors[0x10];
8884 
8885 	u8         port_rcv_remote_physical_errors[0x10];
8886 
8887 	u8         port_rcv_switch_relay_errors[0x10];
8888 
8889 	u8         port_xmit_discards[0x10];
8890 
8891 	u8         port_xmit_constraint_errors[0x8];
8892 
8893 	u8         port_rcv_constraint_errors[0x8];
8894 
8895 	u8         reserved_at_70[0x8];
8896 
8897 	u8         link_overrun_errors[0x8];
8898 
8899 	u8	   reserved_at_80[0x10];
8900 
8901 	u8         vl_15_dropped[0x10];
8902 
8903 	u8	   reserved_at_a0[0xa0];
8904 };
8905 
8906 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8907 	u8         time_since_last_clear_high[0x20];
8908 
8909 	u8         time_since_last_clear_low[0x20];
8910 
8911 	u8         phy_received_bits_high[0x20];
8912 
8913 	u8         phy_received_bits_low[0x20];
8914 
8915 	u8         phy_symbol_errors_high[0x20];
8916 
8917 	u8         phy_symbol_errors_low[0x20];
8918 
8919 	u8         phy_corrected_bits_high[0x20];
8920 
8921 	u8         phy_corrected_bits_low[0x20];
8922 
8923 	u8         phy_corrected_bits_lane0_high[0x20];
8924 
8925 	u8         phy_corrected_bits_lane0_low[0x20];
8926 
8927 	u8         phy_corrected_bits_lane1_high[0x20];
8928 
8929 	u8         phy_corrected_bits_lane1_low[0x20];
8930 
8931 	u8         phy_corrected_bits_lane2_high[0x20];
8932 
8933 	u8         phy_corrected_bits_lane2_low[0x20];
8934 
8935 	u8         phy_corrected_bits_lane3_high[0x20];
8936 
8937 	u8         phy_corrected_bits_lane3_low[0x20];
8938 
8939 	u8         reserved_at_200[0x5c0];
8940 };
8941 
8942 struct mlx5_ifc_infiniband_port_cntrs_bits {
8943 	u8         symbol_error_counter[0x10];
8944 	u8         link_error_recovery_counter[0x8];
8945 	u8         link_downed_counter[0x8];
8946 
8947 	u8         port_rcv_errors[0x10];
8948 	u8         port_rcv_remote_physical_errors[0x10];
8949 
8950 	u8         port_rcv_switch_relay_errors[0x10];
8951 	u8         port_xmit_discards[0x10];
8952 
8953 	u8         port_xmit_constraint_errors[0x8];
8954 	u8         port_rcv_constraint_errors[0x8];
8955 	u8         reserved_0[0x8];
8956 	u8         local_link_integrity_errors[0x4];
8957 	u8         excessive_buffer_overrun_errors[0x4];
8958 
8959 	u8         reserved_1[0x10];
8960 	u8         vl_15_dropped[0x10];
8961 
8962 	u8         port_xmit_data[0x20];
8963 
8964 	u8         port_rcv_data[0x20];
8965 
8966 	u8         port_xmit_pkts[0x20];
8967 
8968 	u8         port_rcv_pkts[0x20];
8969 
8970 	u8         port_xmit_wait[0x20];
8971 
8972 	u8         reserved_2[0x680];
8973 };
8974 
8975 struct mlx5_ifc_phrr_reg_bits {
8976 	u8         clr[0x1];
8977 	u8         reserved_0[0x7];
8978 	u8         local_port[0x8];
8979 	u8         reserved_1[0x10];
8980 
8981 	u8         hist_group[0x8];
8982 	u8         reserved_2[0x10];
8983 	u8         hist_id[0x8];
8984 
8985 	u8         reserved_3[0x40];
8986 
8987 	u8         time_since_last_clear_high[0x20];
8988 
8989 	u8         time_since_last_clear_low[0x20];
8990 
8991 	u8         bin[10][0x20];
8992 };
8993 
8994 struct mlx5_ifc_phbr_for_prio_reg_bits {
8995 	u8         reserved_0[0x18];
8996 	u8         prio[0x8];
8997 };
8998 
8999 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
9000 	u8         reserved_0[0x18];
9001 	u8         tclass[0x8];
9002 };
9003 
9004 struct mlx5_ifc_phbr_binding_reg_bits {
9005 	u8         opcode[0x4];
9006 	u8         reserved_0[0x4];
9007 	u8         local_port[0x8];
9008 	u8         pnat[0x2];
9009 	u8         reserved_1[0xe];
9010 
9011 	u8         hist_group[0x8];
9012 	u8         reserved_2[0x10];
9013 	u8         hist_id[0x8];
9014 
9015 	u8         reserved_3[0x10];
9016 	u8         hist_type[0x10];
9017 
9018 	u8         hist_parameters[0x20];
9019 
9020 	u8         hist_min_value[0x20];
9021 
9022 	u8         hist_max_value[0x20];
9023 
9024 	u8         sample_time[0x20];
9025 };
9026 
9027 enum {
9028 	MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
9029 	MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
9030 };
9031 
9032 struct mlx5_ifc_pfcc_reg_bits {
9033 	u8         dcbx_operation_type[0x2];
9034 	u8         cap_local_admin[0x1];
9035 	u8         cap_remote_admin[0x1];
9036 	u8         reserved_0[0x4];
9037 	u8         local_port[0x8];
9038 	u8         pnat[0x2];
9039 	u8         reserved_1[0xc];
9040 	u8         shl_cap[0x1];
9041 	u8         shl_opr[0x1];
9042 
9043 	u8         ppan[0x4];
9044 	u8         reserved_2[0x4];
9045 	u8         prio_mask_tx[0x8];
9046 	u8         reserved_3[0x8];
9047 	u8         prio_mask_rx[0x8];
9048 
9049 	u8         pptx[0x1];
9050 	u8         aptx[0x1];
9051 	u8         reserved_4[0x6];
9052 	u8         pfctx[0x8];
9053 	u8         reserved_5[0x8];
9054 	u8         cbftx[0x8];
9055 
9056 	u8         pprx[0x1];
9057 	u8         aprx[0x1];
9058 	u8         reserved_6[0x6];
9059 	u8         pfcrx[0x8];
9060 	u8         reserved_7[0x8];
9061 	u8         cbfrx[0x8];
9062 
9063 	u8         device_stall_minor_watermark[0x10];
9064 	u8         device_stall_critical_watermark[0x10];
9065 
9066 	u8         reserved_8[0x60];
9067 };
9068 
9069 struct mlx5_ifc_pelc_reg_bits {
9070 	u8         op[0x4];
9071 	u8         reserved_0[0x4];
9072 	u8         local_port[0x8];
9073 	u8         reserved_1[0x10];
9074 
9075 	u8         op_admin[0x8];
9076 	u8         op_capability[0x8];
9077 	u8         op_request[0x8];
9078 	u8         op_active[0x8];
9079 
9080 	u8         admin[0x40];
9081 
9082 	u8         capability[0x40];
9083 
9084 	u8         request[0x40];
9085 
9086 	u8         active[0x40];
9087 
9088 	u8         reserved_2[0x80];
9089 };
9090 
9091 struct mlx5_ifc_peir_reg_bits {
9092 	u8         reserved_0[0x8];
9093 	u8         local_port[0x8];
9094 	u8         reserved_1[0x10];
9095 
9096 	u8         reserved_2[0xc];
9097 	u8         error_count[0x4];
9098 	u8         reserved_3[0x10];
9099 
9100 	u8         reserved_4[0xc];
9101 	u8         lane[0x4];
9102 	u8         reserved_5[0x8];
9103 	u8         error_type[0x8];
9104 };
9105 
9106 struct mlx5_ifc_qcam_access_reg_cap_mask {
9107 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9108 	u8         qpdpm[0x1];
9109 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9110 	u8         qdpm[0x1];
9111 	u8         qpts[0x1];
9112 	u8         qcap[0x1];
9113 	u8         qcam_access_reg_cap_mask_0[0x1];
9114 };
9115 
9116 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9117 	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9118 	u8         qpts_trust_both[0x1];
9119 };
9120 
9121 struct mlx5_ifc_qcam_reg_bits {
9122 	u8         reserved_at_0[0x8];
9123 	u8         feature_group[0x8];
9124 	u8         reserved_at_10[0x8];
9125 	u8         access_reg_group[0x8];
9126 	u8         reserved_at_20[0x20];
9127 
9128 	union {
9129 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9130 		u8  reserved_at_0[0x80];
9131 	} qos_access_reg_cap_mask;
9132 
9133 	u8         reserved_at_c0[0x80];
9134 
9135 	union {
9136 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9137 		u8  reserved_at_0[0x80];
9138 	} qos_feature_cap_mask;
9139 
9140 	u8         reserved_at_1c0[0x80];
9141 };
9142 
9143 struct mlx5_ifc_pcam_enhanced_features_bits {
9144 	u8         reserved_at_0[0x6d];
9145 	u8         rx_icrc_encapsulated_counter[0x1];
9146 	u8	   reserved_at_6e[0x4];
9147 	u8         ptys_extended_ethernet[0x1];
9148 	u8	   reserved_at_73[0x3];
9149 	u8         pfcc_mask[0x1];
9150 	u8         reserved_at_77[0x3];
9151 	u8         per_lane_error_counters[0x1];
9152 	u8         rx_buffer_fullness_counters[0x1];
9153 	u8         ptys_connector_type[0x1];
9154 	u8         reserved_at_7d[0x1];
9155 	u8         ppcnt_discard_group[0x1];
9156 	u8         ppcnt_statistical_group[0x1];
9157 };
9158 
9159 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9160 	u8         port_access_reg_cap_mask_127_to_96[0x20];
9161 	u8         port_access_reg_cap_mask_95_to_64[0x20];
9162 
9163 	u8         reserved_at_40[0xe];
9164 	u8         pddr[0x1];
9165 	u8         reserved_at_4f[0xd];
9166 
9167 	u8         pplm[0x1];
9168 	u8         port_access_reg_cap_mask_34_to_32[0x3];
9169 
9170 	u8         port_access_reg_cap_mask_31_to_13[0x13];
9171 	u8         pbmc[0x1];
9172 	u8         pptb[0x1];
9173 	u8         port_access_reg_cap_mask_10_to_09[0x2];
9174 	u8         ppcnt[0x1];
9175 	u8         port_access_reg_cap_mask_07_to_00[0x8];
9176 };
9177 
9178 struct mlx5_ifc_pcam_reg_bits {
9179 	u8         reserved_at_0[0x8];
9180 	u8         feature_group[0x8];
9181 	u8         reserved_at_10[0x8];
9182 	u8         access_reg_group[0x8];
9183 
9184 	u8         reserved_at_20[0x20];
9185 
9186 	union {
9187 		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9188 		u8         reserved_at_0[0x80];
9189 	} port_access_reg_cap_mask;
9190 
9191 	u8         reserved_at_c0[0x80];
9192 
9193 	union {
9194 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9195 		u8         reserved_at_0[0x80];
9196 	} feature_cap_mask;
9197 
9198 	u8         reserved_at_1c0[0xc0];
9199 };
9200 
9201 struct mlx5_ifc_mcam_enhanced_features_bits {
9202 	u8         reserved_at_0[0x6e];
9203 	u8         pcie_status_and_power[0x1];
9204 	u8         reserved_at_111[0x10];
9205 	u8         pcie_performance_group[0x1];
9206 };
9207 
9208 struct mlx5_ifc_mcam_access_reg_bits {
9209 	u8         reserved_at_0[0x1c];
9210 	u8         mcda[0x1];
9211 	u8         mcc[0x1];
9212 	u8         mcqi[0x1];
9213 	u8         reserved_at_1f[0x1];
9214 
9215 	u8         regs_95_to_64[0x20];
9216 	u8         regs_63_to_32[0x20];
9217 	u8         regs_31_to_0[0x20];
9218 };
9219 
9220 struct mlx5_ifc_mcam_reg_bits {
9221 	u8         reserved_at_0[0x8];
9222 	u8         feature_group[0x8];
9223 	u8         reserved_at_10[0x8];
9224 	u8         access_reg_group[0x8];
9225 
9226 	u8         reserved_at_20[0x20];
9227 
9228 	union {
9229 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
9230 		u8         reserved_at_0[0x80];
9231 	} mng_access_reg_cap_mask;
9232 
9233 	u8         reserved_at_c0[0x80];
9234 
9235 	union {
9236 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9237 		u8         reserved_at_0[0x80];
9238 	} mng_feature_cap_mask;
9239 
9240 	u8         reserved_at_1c0[0x80];
9241 };
9242 
9243 struct mlx5_ifc_pcap_reg_bits {
9244 	u8         reserved_0[0x8];
9245 	u8         local_port[0x8];
9246 	u8         reserved_1[0x10];
9247 
9248 	u8         port_capability_mask[4][0x20];
9249 };
9250 
9251 struct mlx5_ifc_pbmc_reg_bits {
9252 	u8         reserved_at_0[0x8];
9253 	u8         local_port[0x8];
9254 	u8         reserved_at_10[0x10];
9255 
9256 	u8         xoff_timer_value[0x10];
9257 	u8         xoff_refresh[0x10];
9258 
9259 	u8         reserved_at_40[0x9];
9260 	u8         fullness_threshold[0x7];
9261 	u8         port_buffer_size[0x10];
9262 
9263 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
9264 
9265 	u8         reserved_at_2e0[0x80];
9266 };
9267 
9268 struct mlx5_ifc_paos_reg_bits {
9269 	u8         swid[0x8];
9270 	u8         local_port[0x8];
9271 	u8         reserved_0[0x4];
9272 	u8         admin_status[0x4];
9273 	u8         reserved_1[0x4];
9274 	u8         oper_status[0x4];
9275 
9276 	u8         ase[0x1];
9277 	u8         ee[0x1];
9278 	u8         reserved_2[0x1c];
9279 	u8         e[0x2];
9280 
9281 	u8         reserved_3[0x40];
9282 };
9283 
9284 struct mlx5_ifc_pamp_reg_bits {
9285 	u8         reserved_0[0x8];
9286 	u8         opamp_group[0x8];
9287 	u8         reserved_1[0xc];
9288 	u8         opamp_group_type[0x4];
9289 
9290 	u8         start_index[0x10];
9291 	u8         reserved_2[0x4];
9292 	u8         num_of_indices[0xc];
9293 
9294 	u8         index_data[18][0x10];
9295 };
9296 
9297 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
9298 	u8         llr_rx_cells_high[0x20];
9299 
9300 	u8         llr_rx_cells_low[0x20];
9301 
9302 	u8         llr_rx_error_high[0x20];
9303 
9304 	u8         llr_rx_error_low[0x20];
9305 
9306 	u8         llr_rx_crc_error_high[0x20];
9307 
9308 	u8         llr_rx_crc_error_low[0x20];
9309 
9310 	u8         llr_tx_cells_high[0x20];
9311 
9312 	u8         llr_tx_cells_low[0x20];
9313 
9314 	u8         llr_tx_ret_cells_high[0x20];
9315 
9316 	u8         llr_tx_ret_cells_low[0x20];
9317 
9318 	u8         llr_tx_ret_events_high[0x20];
9319 
9320 	u8         llr_tx_ret_events_low[0x20];
9321 
9322 	u8         reserved_0[0x640];
9323 };
9324 
9325 struct mlx5_ifc_mtmp_reg_bits {
9326 	u8         i[0x1];
9327 	u8         reserved_at_1[0x18];
9328 	u8         sensor_index[0x7];
9329 
9330 	u8         reserved_at_20[0x10];
9331 	u8         temperature[0x10];
9332 
9333 	u8         mte[0x1];
9334 	u8         mtr[0x1];
9335 	u8         reserved_at_42[0x0e];
9336 	u8         max_temperature[0x10];
9337 
9338 	u8         tee[0x2];
9339 	u8         reserved_at_62[0x0e];
9340 	u8         temperature_threshold_hi[0x10];
9341 
9342 	u8         reserved_at_80[0x10];
9343 	u8         temperature_threshold_lo[0x10];
9344 
9345 	u8         reserved_at_100[0x20];
9346 
9347 	u8         sensor_name[0x40];
9348 };
9349 
9350 struct mlx5_ifc_lane_2_module_mapping_bits {
9351 	u8         reserved_0[0x6];
9352 	u8         rx_lane[0x2];
9353 	u8         reserved_1[0x6];
9354 	u8         tx_lane[0x2];
9355 	u8         reserved_2[0x8];
9356 	u8         module[0x8];
9357 };
9358 
9359 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
9360 	u8         transmit_queue_high[0x20];
9361 
9362 	u8         transmit_queue_low[0x20];
9363 
9364 	u8         reserved_0[0x780];
9365 };
9366 
9367 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
9368 	u8         no_buffer_discard_uc_high[0x20];
9369 
9370 	u8         no_buffer_discard_uc_low[0x20];
9371 
9372 	u8         wred_discard_high[0x20];
9373 
9374 	u8         wred_discard_low[0x20];
9375 
9376 	u8         reserved_0[0x740];
9377 };
9378 
9379 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
9380 	u8         rx_octets_high[0x20];
9381 
9382 	u8         rx_octets_low[0x20];
9383 
9384 	u8         reserved_0[0xc0];
9385 
9386 	u8         rx_frames_high[0x20];
9387 
9388 	u8         rx_frames_low[0x20];
9389 
9390 	u8         tx_octets_high[0x20];
9391 
9392 	u8         tx_octets_low[0x20];
9393 
9394 	u8         reserved_1[0xc0];
9395 
9396 	u8         tx_frames_high[0x20];
9397 
9398 	u8         tx_frames_low[0x20];
9399 
9400 	u8         rx_pause_high[0x20];
9401 
9402 	u8         rx_pause_low[0x20];
9403 
9404 	u8         rx_pause_duration_high[0x20];
9405 
9406 	u8         rx_pause_duration_low[0x20];
9407 
9408 	u8         tx_pause_high[0x20];
9409 
9410 	u8         tx_pause_low[0x20];
9411 
9412 	u8         tx_pause_duration_high[0x20];
9413 
9414 	u8         tx_pause_duration_low[0x20];
9415 
9416 	u8         rx_pause_transition_high[0x20];
9417 
9418 	u8         rx_pause_transition_low[0x20];
9419 
9420 	u8         rx_discards_high[0x20];
9421 
9422 	u8         rx_discards_low[0x20];
9423 
9424 	u8         device_stall_minor_watermark_cnt_high[0x20];
9425 
9426 	u8         device_stall_minor_watermark_cnt_low[0x20];
9427 
9428 	u8         device_stall_critical_watermark_cnt_high[0x20];
9429 
9430 	u8         device_stall_critical_watermark_cnt_low[0x20];
9431 
9432 	u8         reserved_2[0x340];
9433 };
9434 
9435 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
9436 	u8         port_transmit_wait_high[0x20];
9437 
9438 	u8         port_transmit_wait_low[0x20];
9439 
9440 	u8         ecn_marked_high[0x20];
9441 
9442 	u8         ecn_marked_low[0x20];
9443 
9444 	u8         no_buffer_discard_mc_high[0x20];
9445 
9446 	u8         no_buffer_discard_mc_low[0x20];
9447 
9448 	u8         rx_ebp_high[0x20];
9449 
9450 	u8         rx_ebp_low[0x20];
9451 
9452 	u8         tx_ebp_high[0x20];
9453 
9454 	u8         tx_ebp_low[0x20];
9455 
9456         u8         rx_buffer_almost_full_high[0x20];
9457 
9458         u8         rx_buffer_almost_full_low[0x20];
9459 
9460         u8         rx_buffer_full_high[0x20];
9461 
9462         u8         rx_buffer_full_low[0x20];
9463 
9464         u8         rx_icrc_encapsulated_high[0x20];
9465 
9466         u8         rx_icrc_encapsulated_low[0x20];
9467 
9468 	u8         reserved_0[0x80];
9469 
9470         u8         tx_stats_pkts64octets_high[0x20];
9471 
9472         u8         tx_stats_pkts64octets_low[0x20];
9473 
9474         u8         tx_stats_pkts65to127octets_high[0x20];
9475 
9476         u8         tx_stats_pkts65to127octets_low[0x20];
9477 
9478         u8         tx_stats_pkts128to255octets_high[0x20];
9479 
9480         u8         tx_stats_pkts128to255octets_low[0x20];
9481 
9482         u8         tx_stats_pkts256to511octets_high[0x20];
9483 
9484         u8         tx_stats_pkts256to511octets_low[0x20];
9485 
9486         u8         tx_stats_pkts512to1023octets_high[0x20];
9487 
9488         u8         tx_stats_pkts512to1023octets_low[0x20];
9489 
9490         u8         tx_stats_pkts1024to1518octets_high[0x20];
9491 
9492         u8         tx_stats_pkts1024to1518octets_low[0x20];
9493 
9494         u8         tx_stats_pkts1519to2047octets_high[0x20];
9495 
9496         u8         tx_stats_pkts1519to2047octets_low[0x20];
9497 
9498         u8         tx_stats_pkts2048to4095octets_high[0x20];
9499 
9500         u8         tx_stats_pkts2048to4095octets_low[0x20];
9501 
9502         u8         tx_stats_pkts4096to8191octets_high[0x20];
9503 
9504         u8         tx_stats_pkts4096to8191octets_low[0x20];
9505 
9506         u8         tx_stats_pkts8192to10239octets_high[0x20];
9507 
9508         u8         tx_stats_pkts8192to10239octets_low[0x20];
9509 
9510 	u8         reserved_1[0x2C0];
9511 };
9512 
9513 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
9514 	u8         a_frames_transmitted_ok_high[0x20];
9515 
9516 	u8         a_frames_transmitted_ok_low[0x20];
9517 
9518 	u8         a_frames_received_ok_high[0x20];
9519 
9520 	u8         a_frames_received_ok_low[0x20];
9521 
9522 	u8         a_frame_check_sequence_errors_high[0x20];
9523 
9524 	u8         a_frame_check_sequence_errors_low[0x20];
9525 
9526 	u8         a_alignment_errors_high[0x20];
9527 
9528 	u8         a_alignment_errors_low[0x20];
9529 
9530 	u8         a_octets_transmitted_ok_high[0x20];
9531 
9532 	u8         a_octets_transmitted_ok_low[0x20];
9533 
9534 	u8         a_octets_received_ok_high[0x20];
9535 
9536 	u8         a_octets_received_ok_low[0x20];
9537 
9538 	u8         a_multicast_frames_xmitted_ok_high[0x20];
9539 
9540 	u8         a_multicast_frames_xmitted_ok_low[0x20];
9541 
9542 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
9543 
9544 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
9545 
9546 	u8         a_multicast_frames_received_ok_high[0x20];
9547 
9548 	u8         a_multicast_frames_received_ok_low[0x20];
9549 
9550 	u8         a_broadcast_frames_recieved_ok_high[0x20];
9551 
9552 	u8         a_broadcast_frames_recieved_ok_low[0x20];
9553 
9554 	u8         a_in_range_length_errors_high[0x20];
9555 
9556 	u8         a_in_range_length_errors_low[0x20];
9557 
9558 	u8         a_out_of_range_length_field_high[0x20];
9559 
9560 	u8         a_out_of_range_length_field_low[0x20];
9561 
9562 	u8         a_frame_too_long_errors_high[0x20];
9563 
9564 	u8         a_frame_too_long_errors_low[0x20];
9565 
9566 	u8         a_symbol_error_during_carrier_high[0x20];
9567 
9568 	u8         a_symbol_error_during_carrier_low[0x20];
9569 
9570 	u8         a_mac_control_frames_transmitted_high[0x20];
9571 
9572 	u8         a_mac_control_frames_transmitted_low[0x20];
9573 
9574 	u8         a_mac_control_frames_received_high[0x20];
9575 
9576 	u8         a_mac_control_frames_received_low[0x20];
9577 
9578 	u8         a_unsupported_opcodes_received_high[0x20];
9579 
9580 	u8         a_unsupported_opcodes_received_low[0x20];
9581 
9582 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
9583 
9584 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
9585 
9586 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
9587 
9588 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
9589 
9590 	u8         reserved_0[0x300];
9591 };
9592 
9593 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
9594 	u8         dot3stats_alignment_errors_high[0x20];
9595 
9596 	u8         dot3stats_alignment_errors_low[0x20];
9597 
9598 	u8         dot3stats_fcs_errors_high[0x20];
9599 
9600 	u8         dot3stats_fcs_errors_low[0x20];
9601 
9602 	u8         dot3stats_single_collision_frames_high[0x20];
9603 
9604 	u8         dot3stats_single_collision_frames_low[0x20];
9605 
9606 	u8         dot3stats_multiple_collision_frames_high[0x20];
9607 
9608 	u8         dot3stats_multiple_collision_frames_low[0x20];
9609 
9610 	u8         dot3stats_sqe_test_errors_high[0x20];
9611 
9612 	u8         dot3stats_sqe_test_errors_low[0x20];
9613 
9614 	u8         dot3stats_deferred_transmissions_high[0x20];
9615 
9616 	u8         dot3stats_deferred_transmissions_low[0x20];
9617 
9618 	u8         dot3stats_late_collisions_high[0x20];
9619 
9620 	u8         dot3stats_late_collisions_low[0x20];
9621 
9622 	u8         dot3stats_excessive_collisions_high[0x20];
9623 
9624 	u8         dot3stats_excessive_collisions_low[0x20];
9625 
9626 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
9627 
9628 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
9629 
9630 	u8         dot3stats_carrier_sense_errors_high[0x20];
9631 
9632 	u8         dot3stats_carrier_sense_errors_low[0x20];
9633 
9634 	u8         dot3stats_frame_too_longs_high[0x20];
9635 
9636 	u8         dot3stats_frame_too_longs_low[0x20];
9637 
9638 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
9639 
9640 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
9641 
9642 	u8         dot3stats_symbol_errors_high[0x20];
9643 
9644 	u8         dot3stats_symbol_errors_low[0x20];
9645 
9646 	u8         dot3control_in_unknown_opcodes_high[0x20];
9647 
9648 	u8         dot3control_in_unknown_opcodes_low[0x20];
9649 
9650 	u8         dot3in_pause_frames_high[0x20];
9651 
9652 	u8         dot3in_pause_frames_low[0x20];
9653 
9654 	u8         dot3out_pause_frames_high[0x20];
9655 
9656 	u8         dot3out_pause_frames_low[0x20];
9657 
9658 	u8         reserved_0[0x3c0];
9659 };
9660 
9661 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
9662 	u8         if_in_octets_high[0x20];
9663 
9664 	u8         if_in_octets_low[0x20];
9665 
9666 	u8         if_in_ucast_pkts_high[0x20];
9667 
9668 	u8         if_in_ucast_pkts_low[0x20];
9669 
9670 	u8         if_in_discards_high[0x20];
9671 
9672 	u8         if_in_discards_low[0x20];
9673 
9674 	u8         if_in_errors_high[0x20];
9675 
9676 	u8         if_in_errors_low[0x20];
9677 
9678 	u8         if_in_unknown_protos_high[0x20];
9679 
9680 	u8         if_in_unknown_protos_low[0x20];
9681 
9682 	u8         if_out_octets_high[0x20];
9683 
9684 	u8         if_out_octets_low[0x20];
9685 
9686 	u8         if_out_ucast_pkts_high[0x20];
9687 
9688 	u8         if_out_ucast_pkts_low[0x20];
9689 
9690 	u8         if_out_discards_high[0x20];
9691 
9692 	u8         if_out_discards_low[0x20];
9693 
9694 	u8         if_out_errors_high[0x20];
9695 
9696 	u8         if_out_errors_low[0x20];
9697 
9698 	u8         if_in_multicast_pkts_high[0x20];
9699 
9700 	u8         if_in_multicast_pkts_low[0x20];
9701 
9702 	u8         if_in_broadcast_pkts_high[0x20];
9703 
9704 	u8         if_in_broadcast_pkts_low[0x20];
9705 
9706 	u8         if_out_multicast_pkts_high[0x20];
9707 
9708 	u8         if_out_multicast_pkts_low[0x20];
9709 
9710 	u8         if_out_broadcast_pkts_high[0x20];
9711 
9712 	u8         if_out_broadcast_pkts_low[0x20];
9713 
9714 	u8         reserved_0[0x480];
9715 };
9716 
9717 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
9718 	u8         ether_stats_drop_events_high[0x20];
9719 
9720 	u8         ether_stats_drop_events_low[0x20];
9721 
9722 	u8         ether_stats_octets_high[0x20];
9723 
9724 	u8         ether_stats_octets_low[0x20];
9725 
9726 	u8         ether_stats_pkts_high[0x20];
9727 
9728 	u8         ether_stats_pkts_low[0x20];
9729 
9730 	u8         ether_stats_broadcast_pkts_high[0x20];
9731 
9732 	u8         ether_stats_broadcast_pkts_low[0x20];
9733 
9734 	u8         ether_stats_multicast_pkts_high[0x20];
9735 
9736 	u8         ether_stats_multicast_pkts_low[0x20];
9737 
9738 	u8         ether_stats_crc_align_errors_high[0x20];
9739 
9740 	u8         ether_stats_crc_align_errors_low[0x20];
9741 
9742 	u8         ether_stats_undersize_pkts_high[0x20];
9743 
9744 	u8         ether_stats_undersize_pkts_low[0x20];
9745 
9746 	u8         ether_stats_oversize_pkts_high[0x20];
9747 
9748 	u8         ether_stats_oversize_pkts_low[0x20];
9749 
9750 	u8         ether_stats_fragments_high[0x20];
9751 
9752 	u8         ether_stats_fragments_low[0x20];
9753 
9754 	u8         ether_stats_jabbers_high[0x20];
9755 
9756 	u8         ether_stats_jabbers_low[0x20];
9757 
9758 	u8         ether_stats_collisions_high[0x20];
9759 
9760 	u8         ether_stats_collisions_low[0x20];
9761 
9762 	u8         ether_stats_pkts64octets_high[0x20];
9763 
9764 	u8         ether_stats_pkts64octets_low[0x20];
9765 
9766 	u8         ether_stats_pkts65to127octets_high[0x20];
9767 
9768 	u8         ether_stats_pkts65to127octets_low[0x20];
9769 
9770 	u8         ether_stats_pkts128to255octets_high[0x20];
9771 
9772 	u8         ether_stats_pkts128to255octets_low[0x20];
9773 
9774 	u8         ether_stats_pkts256to511octets_high[0x20];
9775 
9776 	u8         ether_stats_pkts256to511octets_low[0x20];
9777 
9778 	u8         ether_stats_pkts512to1023octets_high[0x20];
9779 
9780 	u8         ether_stats_pkts512to1023octets_low[0x20];
9781 
9782 	u8         ether_stats_pkts1024to1518octets_high[0x20];
9783 
9784 	u8         ether_stats_pkts1024to1518octets_low[0x20];
9785 
9786 	u8         ether_stats_pkts1519to2047octets_high[0x20];
9787 
9788 	u8         ether_stats_pkts1519to2047octets_low[0x20];
9789 
9790 	u8         ether_stats_pkts2048to4095octets_high[0x20];
9791 
9792 	u8         ether_stats_pkts2048to4095octets_low[0x20];
9793 
9794 	u8         ether_stats_pkts4096to8191octets_high[0x20];
9795 
9796 	u8         ether_stats_pkts4096to8191octets_low[0x20];
9797 
9798 	u8         ether_stats_pkts8192to10239octets_high[0x20];
9799 
9800 	u8         ether_stats_pkts8192to10239octets_low[0x20];
9801 
9802 	u8         reserved_0[0x280];
9803 };
9804 
9805 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
9806 	u8         symbol_error_counter[0x10];
9807 	u8         link_error_recovery_counter[0x8];
9808 	u8         link_downed_counter[0x8];
9809 
9810 	u8         port_rcv_errors[0x10];
9811 	u8         port_rcv_remote_physical_errors[0x10];
9812 
9813 	u8         port_rcv_switch_relay_errors[0x10];
9814 	u8         port_xmit_discards[0x10];
9815 
9816 	u8         port_xmit_constraint_errors[0x8];
9817 	u8         port_rcv_constraint_errors[0x8];
9818 	u8         reserved_0[0x8];
9819 	u8         local_link_integrity_errors[0x4];
9820 	u8         excessive_buffer_overrun_errors[0x4];
9821 
9822 	u8         reserved_1[0x10];
9823 	u8         vl_15_dropped[0x10];
9824 
9825 	u8         port_xmit_data[0x20];
9826 
9827 	u8         port_rcv_data[0x20];
9828 
9829 	u8         port_xmit_pkts[0x20];
9830 
9831 	u8         port_rcv_pkts[0x20];
9832 
9833 	u8         port_xmit_wait[0x20];
9834 
9835 	u8         reserved_2[0x680];
9836 };
9837 
9838 struct mlx5_ifc_trc_tlb_reg_bits {
9839 	u8         reserved_0[0x80];
9840 
9841 	u8         tlb_addr[0][0x40];
9842 };
9843 
9844 struct mlx5_ifc_trc_read_fifo_reg_bits {
9845 	u8         reserved_0[0x10];
9846 	u8         requested_event_num[0x10];
9847 
9848 	u8         reserved_1[0x20];
9849 
9850 	u8         reserved_2[0x10];
9851 	u8         acual_event_num[0x10];
9852 
9853 	u8         reserved_3[0x20];
9854 
9855 	u8         event[0][0x40];
9856 };
9857 
9858 struct mlx5_ifc_trc_lock_reg_bits {
9859 	u8         reserved_0[0x1f];
9860 	u8         lock[0x1];
9861 
9862 	u8         reserved_1[0x60];
9863 };
9864 
9865 struct mlx5_ifc_trc_filter_reg_bits {
9866 	u8         status[0x1];
9867 	u8         reserved_0[0xf];
9868 	u8         filter_index[0x10];
9869 
9870 	u8         reserved_1[0x20];
9871 
9872 	u8         filter_val[0x20];
9873 
9874 	u8         reserved_2[0x1a0];
9875 };
9876 
9877 struct mlx5_ifc_trc_event_reg_bits {
9878 	u8         status[0x1];
9879 	u8         reserved_0[0xf];
9880 	u8         event_index[0x10];
9881 
9882 	u8         reserved_1[0x20];
9883 
9884 	u8         event_id[0x20];
9885 
9886 	u8         event_selector_val[0x10];
9887 	u8         event_selector_size[0x10];
9888 
9889 	u8         reserved_2[0x180];
9890 };
9891 
9892 struct mlx5_ifc_trc_conf_reg_bits {
9893 	u8         limit_en[0x1];
9894 	u8         reserved_0[0x3];
9895 	u8         dump_mode[0x4];
9896 	u8         reserved_1[0x15];
9897 	u8         state[0x3];
9898 
9899 	u8         reserved_2[0x20];
9900 
9901 	u8         limit_event_index[0x20];
9902 
9903 	u8         mkey[0x20];
9904 
9905 	u8         fifo_ready_ev_num[0x20];
9906 
9907 	u8         reserved_3[0x160];
9908 };
9909 
9910 struct mlx5_ifc_trc_cap_reg_bits {
9911 	u8         reserved_0[0x18];
9912 	u8         dump_mode[0x8];
9913 
9914 	u8         reserved_1[0x20];
9915 
9916 	u8         num_of_events[0x10];
9917 	u8         num_of_filters[0x10];
9918 
9919 	u8         fifo_size[0x20];
9920 
9921 	u8         tlb_size[0x10];
9922 	u8         event_size[0x10];
9923 
9924 	u8         reserved_2[0x160];
9925 };
9926 
9927 struct mlx5_ifc_set_node_in_bits {
9928 	u8         node_description[64][0x8];
9929 };
9930 
9931 struct mlx5_ifc_register_power_settings_bits {
9932 	u8         reserved_0[0x18];
9933 	u8         power_settings_level[0x8];
9934 
9935 	u8         reserved_1[0x60];
9936 };
9937 
9938 struct mlx5_ifc_register_host_endianess_bits {
9939 	u8         he[0x1];
9940 	u8         reserved_0[0x1f];
9941 
9942 	u8         reserved_1[0x60];
9943 };
9944 
9945 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
9946 	u8         physical_address[0x40];
9947 };
9948 
9949 struct mlx5_ifc_qtct_reg_bits {
9950 	u8         operation_type[0x2];
9951 	u8         cap_local_admin[0x1];
9952 	u8         cap_remote_admin[0x1];
9953 	u8         reserved_0[0x4];
9954 	u8         port_number[0x8];
9955 	u8         reserved_1[0xd];
9956 	u8         prio[0x3];
9957 
9958 	u8         reserved_2[0x1d];
9959 	u8         tclass[0x3];
9960 };
9961 
9962 struct mlx5_ifc_qpdp_reg_bits {
9963 	u8         reserved_0[0x8];
9964 	u8         port_number[0x8];
9965 	u8         reserved_1[0x10];
9966 
9967 	u8         reserved_2[0x1d];
9968 	u8         pprio[0x3];
9969 };
9970 
9971 struct mlx5_ifc_port_info_ro_fields_param_bits {
9972 	u8         reserved_0[0x8];
9973 	u8         port[0x8];
9974 	u8         max_gid[0x10];
9975 
9976 	u8         reserved_1[0x20];
9977 
9978 	u8         port_guid[0x40];
9979 };
9980 
9981 struct mlx5_ifc_nvqc_reg_bits {
9982 	u8         type[0x20];
9983 
9984 	u8         reserved_0[0x18];
9985 	u8         version[0x4];
9986 	u8         reserved_1[0x2];
9987 	u8         support_wr[0x1];
9988 	u8         support_rd[0x1];
9989 };
9990 
9991 struct mlx5_ifc_nvia_reg_bits {
9992 	u8         reserved_0[0x1d];
9993 	u8         target[0x3];
9994 
9995 	u8         reserved_1[0x20];
9996 };
9997 
9998 struct mlx5_ifc_nvdi_reg_bits {
9999 	struct mlx5_ifc_config_item_bits configuration_item_header;
10000 };
10001 
10002 struct mlx5_ifc_nvda_reg_bits {
10003 	struct mlx5_ifc_config_item_bits configuration_item_header;
10004 
10005 	u8         configuration_item_data[0x20];
10006 };
10007 
10008 struct mlx5_ifc_node_info_ro_fields_param_bits {
10009 	u8         system_image_guid[0x40];
10010 
10011 	u8         reserved_0[0x40];
10012 
10013 	u8         node_guid[0x40];
10014 
10015 	u8         reserved_1[0x10];
10016 	u8         max_pkey[0x10];
10017 
10018 	u8         reserved_2[0x20];
10019 };
10020 
10021 struct mlx5_ifc_ets_tcn_config_reg_bits {
10022 	u8         g[0x1];
10023 	u8         b[0x1];
10024 	u8         r[0x1];
10025 	u8         reserved_0[0x9];
10026 	u8         group[0x4];
10027 	u8         reserved_1[0x9];
10028 	u8         bw_allocation[0x7];
10029 
10030 	u8         reserved_2[0xc];
10031 	u8         max_bw_units[0x4];
10032 	u8         reserved_3[0x8];
10033 	u8         max_bw_value[0x8];
10034 };
10035 
10036 struct mlx5_ifc_ets_global_config_reg_bits {
10037 	u8         reserved_0[0x2];
10038 	u8         r[0x1];
10039 	u8         reserved_1[0x1d];
10040 
10041 	u8         reserved_2[0xc];
10042 	u8         max_bw_units[0x4];
10043 	u8         reserved_3[0x8];
10044 	u8         max_bw_value[0x8];
10045 };
10046 
10047 struct mlx5_ifc_qetc_reg_bits {
10048 	u8                                         reserved_at_0[0x8];
10049 	u8                                         port_number[0x8];
10050 	u8                                         reserved_at_10[0x30];
10051 
10052 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
10053 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10054 };
10055 
10056 struct mlx5_ifc_nodnic_mac_filters_bits {
10057 	struct mlx5_ifc_mac_address_layout_bits mac_filter0;
10058 
10059 	struct mlx5_ifc_mac_address_layout_bits mac_filter1;
10060 
10061 	struct mlx5_ifc_mac_address_layout_bits mac_filter2;
10062 
10063 	struct mlx5_ifc_mac_address_layout_bits mac_filter3;
10064 
10065 	struct mlx5_ifc_mac_address_layout_bits mac_filter4;
10066 
10067 	u8         reserved_0[0xc0];
10068 };
10069 
10070 struct mlx5_ifc_nodnic_gid_filters_bits {
10071 	u8         mgid_filter0[16][0x8];
10072 
10073 	u8         mgid_filter1[16][0x8];
10074 
10075 	u8         mgid_filter2[16][0x8];
10076 
10077 	u8         mgid_filter3[16][0x8];
10078 };
10079 
10080 enum {
10081 	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
10082 	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
10083 };
10084 
10085 enum {
10086 	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
10087 	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
10088 };
10089 
10090 struct mlx5_ifc_nodnic_config_reg_bits {
10091 	u8         no_dram_nic_revision[0x8];
10092 	u8         hardware_format[0x8];
10093 	u8         support_receive_filter[0x1];
10094 	u8         support_promisc_filter[0x1];
10095 	u8         support_promisc_multicast_filter[0x1];
10096 	u8         reserved_0[0x2];
10097 	u8         log_working_buffer_size[0x3];
10098 	u8         log_pkey_table_size[0x4];
10099 	u8         reserved_1[0x3];
10100 	u8         num_ports[0x1];
10101 
10102 	u8         reserved_2[0x2];
10103 	u8         log_max_ring_size[0x6];
10104 	u8         reserved_3[0x18];
10105 
10106 	u8         lkey[0x20];
10107 
10108 	u8         cqe_format[0x4];
10109 	u8         reserved_4[0x1c];
10110 
10111 	u8         node_guid[0x40];
10112 
10113 	u8         reserved_5[0x740];
10114 
10115 	struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
10116 
10117 	struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
10118 };
10119 
10120 struct mlx5_ifc_vlan_layout_bits {
10121 	u8         reserved_0[0x14];
10122 	u8         vlan[0xc];
10123 
10124 	u8         reserved_1[0x20];
10125 };
10126 
10127 struct mlx5_ifc_umr_pointer_desc_argument_bits {
10128 	u8         reserved_0[0x20];
10129 
10130 	u8         mkey[0x20];
10131 
10132 	u8         addressh_63_32[0x20];
10133 
10134 	u8         addressl_31_0[0x20];
10135 };
10136 
10137 struct mlx5_ifc_ud_adrs_vector_bits {
10138 	u8         dc_key[0x40];
10139 
10140 	u8         ext[0x1];
10141 	u8         reserved_0[0x7];
10142 	u8         destination_qp_dct[0x18];
10143 
10144 	u8         static_rate[0x4];
10145 	u8         sl_eth_prio[0x4];
10146 	u8         fl[0x1];
10147 	u8         mlid[0x7];
10148 	u8         rlid_udp_sport[0x10];
10149 
10150 	u8         reserved_1[0x20];
10151 
10152 	u8         rmac_47_16[0x20];
10153 
10154 	u8         rmac_15_0[0x10];
10155 	u8         tclass[0x8];
10156 	u8         hop_limit[0x8];
10157 
10158 	u8         reserved_2[0x1];
10159 	u8         grh[0x1];
10160 	u8         reserved_3[0x2];
10161 	u8         src_addr_index[0x8];
10162 	u8         flow_label[0x14];
10163 
10164 	u8         rgid_rip[16][0x8];
10165 };
10166 
10167 struct mlx5_ifc_port_module_event_bits {
10168 	u8         reserved_0[0x8];
10169 	u8         module[0x8];
10170 	u8         reserved_1[0xc];
10171 	u8         module_status[0x4];
10172 
10173 	u8         reserved_2[0x14];
10174 	u8         error_type[0x4];
10175 	u8         reserved_3[0x8];
10176 
10177 	u8         reserved_4[0xa0];
10178 };
10179 
10180 struct mlx5_ifc_icmd_control_bits {
10181 	u8         opcode[0x10];
10182 	u8         status[0x8];
10183 	u8         reserved_0[0x7];
10184 	u8         busy[0x1];
10185 };
10186 
10187 struct mlx5_ifc_eqe_bits {
10188 	u8         reserved_0[0x8];
10189 	u8         event_type[0x8];
10190 	u8         reserved_1[0x8];
10191 	u8         event_sub_type[0x8];
10192 
10193 	u8         reserved_2[0xe0];
10194 
10195 	union mlx5_ifc_event_auto_bits event_data;
10196 
10197 	u8         reserved_3[0x10];
10198 	u8         signature[0x8];
10199 	u8         reserved_4[0x7];
10200 	u8         owner[0x1];
10201 };
10202 
10203 enum {
10204 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10205 };
10206 
10207 struct mlx5_ifc_cmd_queue_entry_bits {
10208 	u8         type[0x8];
10209 	u8         reserved_0[0x18];
10210 
10211 	u8         input_length[0x20];
10212 
10213 	u8         input_mailbox_pointer_63_32[0x20];
10214 
10215 	u8         input_mailbox_pointer_31_9[0x17];
10216 	u8         reserved_1[0x9];
10217 
10218 	u8         command_input_inline_data[16][0x8];
10219 
10220 	u8         command_output_inline_data[16][0x8];
10221 
10222 	u8         output_mailbox_pointer_63_32[0x20];
10223 
10224 	u8         output_mailbox_pointer_31_9[0x17];
10225 	u8         reserved_2[0x9];
10226 
10227 	u8         output_length[0x20];
10228 
10229 	u8         token[0x8];
10230 	u8         signature[0x8];
10231 	u8         reserved_3[0x8];
10232 	u8         status[0x7];
10233 	u8         ownership[0x1];
10234 };
10235 
10236 struct mlx5_ifc_cmd_out_bits {
10237 	u8         status[0x8];
10238 	u8         reserved_0[0x18];
10239 
10240 	u8         syndrome[0x20];
10241 
10242 	u8         command_output[0x20];
10243 };
10244 
10245 struct mlx5_ifc_cmd_in_bits {
10246 	u8         opcode[0x10];
10247 	u8         reserved_0[0x10];
10248 
10249 	u8         reserved_1[0x10];
10250 	u8         op_mod[0x10];
10251 
10252 	u8         command[0][0x20];
10253 };
10254 
10255 struct mlx5_ifc_cmd_if_box_bits {
10256 	u8         mailbox_data[512][0x8];
10257 
10258 	u8         reserved_0[0x180];
10259 
10260 	u8         next_pointer_63_32[0x20];
10261 
10262 	u8         next_pointer_31_10[0x16];
10263 	u8         reserved_1[0xa];
10264 
10265 	u8         block_number[0x20];
10266 
10267 	u8         reserved_2[0x8];
10268 	u8         token[0x8];
10269 	u8         ctrl_signature[0x8];
10270 	u8         signature[0x8];
10271 };
10272 
10273 struct mlx5_ifc_mtt_bits {
10274 	u8         ptag_63_32[0x20];
10275 
10276 	u8         ptag_31_8[0x18];
10277 	u8         reserved_0[0x6];
10278 	u8         wr_en[0x1];
10279 	u8         rd_en[0x1];
10280 };
10281 
10282 struct mlx5_ifc_tls_progress_params_bits {
10283 	u8         valid[0x1];
10284 	u8         reserved_at_1[0x7];
10285 	u8         pd[0x18];
10286 
10287 	u8         next_record_tcp_sn[0x20];
10288 
10289 	u8         hw_resync_tcp_sn[0x20];
10290 
10291 	u8         record_tracker_state[0x2];
10292 	u8         auth_state[0x2];
10293 	u8         reserved_at_64[0x4];
10294 	u8         hw_offset_record_number[0x18];
10295 };
10296 
10297 struct mlx5_ifc_tls_static_params_bits {
10298 	u8         const_2[0x2];
10299 	u8         tls_version[0x4];
10300 	u8         const_1[0x2];
10301 	u8         reserved_at_8[0x14];
10302 	u8         encryption_standard[0x4];
10303 
10304 	u8         reserved_at_20[0x20];
10305 
10306 	u8         initial_record_number[0x40];
10307 
10308 	u8         resync_tcp_sn[0x20];
10309 
10310 	u8         gcm_iv[0x20];
10311 
10312 	u8         implicit_iv[0x40];
10313 
10314 	u8         reserved_at_100[0x8];
10315 	u8         dek_index[0x18];
10316 
10317 	u8         reserved_at_120[0xe0];
10318 };
10319 
10320 /* Vendor Specific Capabilities, VSC */
10321 enum {
10322 	MLX5_VSC_DOMAIN_ICMD			= 0x1,
10323 	MLX5_VSC_DOMAIN_PROTECTED_CRSPACE	= 0x6,
10324 	MLX5_VSC_DOMAIN_SCAN_CRSPACE		= 0x7,
10325 	MLX5_VSC_DOMAIN_SEMAPHORES		= 0xA,
10326 };
10327 
10328 struct mlx5_ifc_vendor_specific_cap_bits {
10329 	u8         type[0x8];
10330 	u8         length[0x8];
10331 	u8         next_pointer[0x8];
10332 	u8         capability_id[0x8];
10333 
10334 	u8         status[0x3];
10335 	u8         reserved_0[0xd];
10336 	u8         space[0x10];
10337 
10338 	u8         counter[0x20];
10339 
10340 	u8         semaphore[0x20];
10341 
10342 	u8         flag[0x1];
10343 	u8         reserved_1[0x1];
10344 	u8         address[0x1e];
10345 
10346 	u8         data[0x20];
10347 };
10348 
10349 struct mlx5_ifc_vsc_space_bits {
10350 	u8 status[0x3];
10351 	u8 reserved0[0xd];
10352 	u8 space[0x10];
10353 };
10354 
10355 struct mlx5_ifc_vsc_addr_bits {
10356 	u8 flag[0x1];
10357 	u8 reserved0[0x1];
10358 	u8 address[0x1e];
10359 };
10360 
10361 enum {
10362 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10363 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10364 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10365 };
10366 
10367 enum {
10368 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10369 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10370 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10371 };
10372 
10373 enum {
10374 	MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
10375 	MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
10376 	MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
10377 	MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
10378 	MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
10379 	MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
10380 	MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
10381 	MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
10382 	MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
10383 	MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
10384 	MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
10385 };
10386 
10387 struct mlx5_ifc_initial_seg_bits {
10388 	u8         fw_rev_minor[0x10];
10389 	u8         fw_rev_major[0x10];
10390 
10391 	u8         cmd_interface_rev[0x10];
10392 	u8         fw_rev_subminor[0x10];
10393 
10394 	u8         reserved_0[0x40];
10395 
10396 	u8         cmdq_phy_addr_63_32[0x20];
10397 
10398 	u8         cmdq_phy_addr_31_12[0x14];
10399 	u8         reserved_1[0x2];
10400 	u8         nic_interface[0x2];
10401 	u8         log_cmdq_size[0x4];
10402 	u8         log_cmdq_stride[0x4];
10403 
10404 	u8         command_doorbell_vector[0x20];
10405 
10406 	u8         reserved_2[0xf00];
10407 
10408 	u8         initializing[0x1];
10409 	u8         reserved_3[0x4];
10410 	u8         nic_interface_supported[0x3];
10411 	u8         reserved_4[0x18];
10412 
10413 	struct mlx5_ifc_health_buffer_bits health_buffer;
10414 
10415 	u8         no_dram_nic_offset[0x20];
10416 
10417 	u8         reserved_5[0x6de0];
10418 
10419 	u8         internal_timer_h[0x20];
10420 
10421 	u8         internal_timer_l[0x20];
10422 
10423 	u8         reserved_6[0x20];
10424 
10425 	u8         reserved_7[0x1f];
10426 	u8         clear_int[0x1];
10427 
10428 	u8         health_syndrome[0x8];
10429 	u8         health_counter[0x18];
10430 
10431 	u8         reserved_8[0x17fc0];
10432 };
10433 
10434 union mlx5_ifc_icmd_interface_document_bits {
10435 	struct mlx5_ifc_fw_version_bits fw_version;
10436 	struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
10437 	struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
10438 	struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
10439 	struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
10440 	struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
10441 	struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
10442 	struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
10443 	struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
10444 	struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
10445 	struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
10446 	struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
10447 	struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
10448 	struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
10449 	u8         reserved_0[0x42c0];
10450 };
10451 
10452 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
10453 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10454 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10455 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10456 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10457 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10458 	struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
10459 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10460 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10461 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
10462 	struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
10463 	u8         reserved_0[0x7c0];
10464 };
10465 
10466 struct mlx5_ifc_ppcnt_reg_bits {
10467 	u8         swid[0x8];
10468 	u8         local_port[0x8];
10469 	u8         pnat[0x2];
10470 	u8         reserved_0[0x8];
10471 	u8         grp[0x6];
10472 
10473 	u8         clr[0x1];
10474 	u8         reserved_1[0x1c];
10475 	u8         prio_tc[0x3];
10476 
10477 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
10478 };
10479 
10480 struct mlx5_ifc_pcie_lanes_counters_bits {
10481 	u8         life_time_counter_high[0x20];
10482 
10483 	u8         life_time_counter_low[0x20];
10484 
10485 	u8         error_counter_lane0[0x20];
10486 
10487 	u8         error_counter_lane1[0x20];
10488 
10489 	u8         error_counter_lane2[0x20];
10490 
10491 	u8         error_counter_lane3[0x20];
10492 
10493 	u8         error_counter_lane4[0x20];
10494 
10495 	u8         error_counter_lane5[0x20];
10496 
10497 	u8         error_counter_lane6[0x20];
10498 
10499 	u8         error_counter_lane7[0x20];
10500 
10501 	u8         error_counter_lane8[0x20];
10502 
10503 	u8         error_counter_lane9[0x20];
10504 
10505 	u8         error_counter_lane10[0x20];
10506 
10507 	u8         error_counter_lane11[0x20];
10508 
10509 	u8         error_counter_lane12[0x20];
10510 
10511 	u8         error_counter_lane13[0x20];
10512 
10513 	u8         error_counter_lane14[0x20];
10514 
10515 	u8         error_counter_lane15[0x20];
10516 
10517 	u8         reserved_at_240[0x580];
10518 };
10519 
10520 struct mlx5_ifc_pcie_lanes_counters_ext_bits {
10521 	u8         reserved_at_0[0x40];
10522 
10523 	u8         error_counter_lane0[0x20];
10524 
10525 	u8         error_counter_lane1[0x20];
10526 
10527 	u8         error_counter_lane2[0x20];
10528 
10529 	u8         error_counter_lane3[0x20];
10530 
10531 	u8         error_counter_lane4[0x20];
10532 
10533 	u8         error_counter_lane5[0x20];
10534 
10535 	u8         error_counter_lane6[0x20];
10536 
10537 	u8         error_counter_lane7[0x20];
10538 
10539 	u8         error_counter_lane8[0x20];
10540 
10541 	u8         error_counter_lane9[0x20];
10542 
10543 	u8         error_counter_lane10[0x20];
10544 
10545 	u8         error_counter_lane11[0x20];
10546 
10547 	u8         error_counter_lane12[0x20];
10548 
10549 	u8         error_counter_lane13[0x20];
10550 
10551 	u8         error_counter_lane14[0x20];
10552 
10553 	u8         error_counter_lane15[0x20];
10554 
10555 	u8         reserved_at_240[0x580];
10556 };
10557 
10558 struct mlx5_ifc_pcie_perf_counters_bits {
10559 	u8         life_time_counter_high[0x20];
10560 
10561 	u8         life_time_counter_low[0x20];
10562 
10563 	u8         rx_errors[0x20];
10564 
10565 	u8         tx_errors[0x20];
10566 
10567 	u8         l0_to_recovery_eieos[0x20];
10568 
10569 	u8         l0_to_recovery_ts[0x20];
10570 
10571 	u8         l0_to_recovery_framing[0x20];
10572 
10573 	u8         l0_to_recovery_retrain[0x20];
10574 
10575 	u8         crc_error_dllp[0x20];
10576 
10577 	u8         crc_error_tlp[0x20];
10578 
10579 	u8         tx_overflow_buffer_pkt[0x40];
10580 
10581 	u8         outbound_stalled_reads[0x20];
10582 
10583 	u8         outbound_stalled_writes[0x20];
10584 
10585 	u8         outbound_stalled_reads_events[0x20];
10586 
10587 	u8         outbound_stalled_writes_events[0x20];
10588 
10589 	u8         tx_overflow_buffer_marked_pkt[0x40];
10590 
10591 	u8         reserved_at_240[0x580];
10592 };
10593 
10594 struct mlx5_ifc_pcie_perf_counters_ext_bits {
10595 	u8         reserved_at_0[0x40];
10596 
10597 	u8         rx_errors[0x20];
10598 
10599 	u8         tx_errors[0x20];
10600 
10601 	u8         reserved_at_80[0xc0];
10602 
10603 	u8         tx_overflow_buffer_pkt[0x40];
10604 
10605 	u8         outbound_stalled_reads[0x20];
10606 
10607 	u8         outbound_stalled_writes[0x20];
10608 
10609 	u8         outbound_stalled_reads_events[0x20];
10610 
10611 	u8         outbound_stalled_writes_events[0x20];
10612 
10613 	u8         tx_overflow_buffer_marked_pkt[0x40];
10614 
10615 	u8         reserved_at_240[0x580];
10616 };
10617 
10618 struct mlx5_ifc_pcie_timers_states_bits {
10619 	u8         life_time_counter_high[0x20];
10620 
10621 	u8         life_time_counter_low[0x20];
10622 
10623 	u8         time_to_boot_image_start[0x20];
10624 
10625 	u8         time_to_link_image[0x20];
10626 
10627 	u8         calibration_time[0x20];
10628 
10629 	u8         time_to_first_perst[0x20];
10630 
10631 	u8         time_to_detect_state[0x20];
10632 
10633 	u8         time_to_l0[0x20];
10634 
10635 	u8         time_to_crs_en[0x20];
10636 
10637 	u8         time_to_plastic_image_start[0x20];
10638 
10639 	u8         time_to_iron_image_start[0x20];
10640 
10641 	u8         perst_handler[0x20];
10642 
10643 	u8         times_in_l1[0x20];
10644 
10645 	u8         times_in_l23[0x20];
10646 
10647 	u8         dl_down[0x20];
10648 
10649 	u8         config_cycle1usec[0x20];
10650 
10651 	u8         config_cycle2to7usec[0x20];
10652 
10653 	u8         config_cycle8to15usec[0x20];
10654 
10655 	u8         config_cycle16to63usec[0x20];
10656 
10657 	u8         config_cycle64usec[0x20];
10658 
10659 	u8         correctable_err_msg_sent[0x20];
10660 
10661 	u8         non_fatal_err_msg_sent[0x20];
10662 
10663 	u8         fatal_err_msg_sent[0x20];
10664 
10665 	u8         reserved_at_2e0[0x4e0];
10666 };
10667 
10668 struct mlx5_ifc_pcie_timers_states_ext_bits {
10669 	u8         reserved_at_0[0x40];
10670 
10671 	u8         time_to_boot_image_start[0x20];
10672 
10673 	u8         time_to_link_image[0x20];
10674 
10675 	u8         calibration_time[0x20];
10676 
10677 	u8         time_to_first_perst[0x20];
10678 
10679 	u8         time_to_detect_state[0x20];
10680 
10681 	u8         time_to_l0[0x20];
10682 
10683 	u8         time_to_crs_en[0x20];
10684 
10685 	u8         time_to_plastic_image_start[0x20];
10686 
10687 	u8         time_to_iron_image_start[0x20];
10688 
10689 	u8         perst_handler[0x20];
10690 
10691 	u8         times_in_l1[0x20];
10692 
10693 	u8         times_in_l23[0x20];
10694 
10695 	u8         dl_down[0x20];
10696 
10697 	u8         config_cycle1usec[0x20];
10698 
10699 	u8         config_cycle2to7usec[0x20];
10700 
10701 	u8         config_cycle8to15usec[0x20];
10702 
10703 	u8         config_cycle16to63usec[0x20];
10704 
10705 	u8         config_cycle64usec[0x20];
10706 
10707 	u8         correctable_err_msg_sent[0x20];
10708 
10709 	u8         non_fatal_err_msg_sent[0x20];
10710 
10711 	u8         fatal_err_msg_sent[0x20];
10712 
10713 	u8         reserved_at_2e0[0x4e0];
10714 };
10715 
10716 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits {
10717 	struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters;
10718 	struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters;
10719 	struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states;
10720 	u8         reserved_at_0[0x7c0];
10721 };
10722 
10723 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits {
10724 	struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext;
10725 	struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext;
10726 	struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext;
10727 	u8         reserved_at_0[0x7c0];
10728 };
10729 
10730 struct mlx5_ifc_mpcnt_reg_bits {
10731 	u8         reserved_at_0[0x2];
10732 	u8         depth[0x6];
10733 	u8         pcie_index[0x8];
10734 	u8         node[0x8];
10735 	u8         reserved_at_18[0x2];
10736 	u8         grp[0x6];
10737 
10738 	u8         clr[0x1];
10739 	u8         reserved_at_21[0x1f];
10740 
10741 	union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set;
10742 };
10743 
10744 struct mlx5_ifc_mpcnt_reg_ext_bits {
10745 	u8         reserved_at_0[0x2];
10746 	u8         depth[0x6];
10747 	u8         pcie_index[0x8];
10748 	u8         node[0x8];
10749 	u8         reserved_at_18[0x2];
10750 	u8         grp[0x6];
10751 
10752 	u8         clr[0x1];
10753 	u8         reserved_at_21[0x1f];
10754 
10755 	union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set;
10756 };
10757 
10758 struct mlx5_ifc_monitor_opcodes_layout_bits {
10759 	u8         reserved_at_0[0x10];
10760 	u8         monitor_opcode[0x10];
10761 };
10762 
10763 union mlx5_ifc_pddr_status_opcode_bits {
10764 	struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes;
10765 	u8         reserved_at_0[0x20];
10766 };
10767 
10768 struct mlx5_ifc_troubleshooting_info_page_layout_bits {
10769 	u8         reserved_at_0[0x10];
10770 	u8         group_opcode[0x10];
10771 
10772 	union mlx5_ifc_pddr_status_opcode_bits status_opcode;
10773 
10774 	u8         user_feedback_data[0x10];
10775 	u8         user_feedback_index[0x10];
10776 
10777 	u8         status_message[0x760];
10778 };
10779 
10780 union mlx5_ifc_pddr_page_data_bits {
10781 	struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page;
10782 	struct mlx5_ifc_pddr_module_info_bits pddr_module_info;
10783 	u8         reserved_at_0[0x7c0];
10784 };
10785 
10786 struct mlx5_ifc_pddr_reg_bits {
10787 	u8         reserved_at_0[0x8];
10788 	u8         local_port[0x8];
10789 	u8         pnat[0x2];
10790 	u8         reserved_at_12[0xe];
10791 
10792 	u8         reserved_at_20[0x18];
10793 	u8         page_select[0x8];
10794 
10795 	union mlx5_ifc_pddr_page_data_bits page_data;
10796 };
10797 
10798 enum {
10799 	MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050,
10800 	MLX5_MPEIN_PWR_STATUS_INVALID = 0,
10801 	MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1,
10802 	MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2,
10803 };
10804 
10805 struct mlx5_ifc_mpein_reg_bits {
10806 	u8         reserved_at_0[0x2];
10807 	u8         depth[0x6];
10808 	u8         pcie_index[0x8];
10809 	u8         node[0x8];
10810 	u8         reserved_at_18[0x8];
10811 
10812 	u8         capability_mask[0x20];
10813 
10814 	u8         reserved_at_40[0x8];
10815 	u8         link_width_enabled[0x8];
10816 	u8         link_speed_enabled[0x10];
10817 
10818 	u8         lane0_physical_position[0x8];
10819 	u8         link_width_active[0x8];
10820 	u8         link_speed_active[0x10];
10821 
10822 	u8         num_of_pfs[0x10];
10823 	u8         num_of_vfs[0x10];
10824 
10825 	u8         bdf0[0x10];
10826 	u8         reserved_at_b0[0x10];
10827 
10828 	u8         max_read_request_size[0x4];
10829 	u8         max_payload_size[0x4];
10830 	u8         reserved_at_c8[0x5];
10831 	u8         pwr_status[0x3];
10832 	u8         port_type[0x4];
10833 	u8         reserved_at_d4[0xb];
10834 	u8         lane_reversal[0x1];
10835 
10836 	u8         reserved_at_e0[0x14];
10837 	u8         pci_power[0xc];
10838 
10839 	u8         reserved_at_100[0x20];
10840 
10841 	u8         device_status[0x10];
10842 	u8         port_state[0x8];
10843 	u8         reserved_at_138[0x8];
10844 
10845 	u8         reserved_at_140[0x10];
10846 	u8         receiver_detect_result[0x10];
10847 
10848 	u8         reserved_at_160[0x20];
10849 };
10850 
10851 struct mlx5_ifc_mpein_reg_ext_bits {
10852 	u8         reserved_at_0[0x2];
10853 	u8         depth[0x6];
10854 	u8         pcie_index[0x8];
10855 	u8         node[0x8];
10856 	u8         reserved_at_18[0x8];
10857 
10858 	u8         reserved_at_20[0x20];
10859 
10860 	u8         reserved_at_40[0x8];
10861 	u8         link_width_enabled[0x8];
10862 	u8         link_speed_enabled[0x10];
10863 
10864 	u8         lane0_physical_position[0x8];
10865 	u8         link_width_active[0x8];
10866 	u8         link_speed_active[0x10];
10867 
10868 	u8         num_of_pfs[0x10];
10869 	u8         num_of_vfs[0x10];
10870 
10871 	u8         bdf0[0x10];
10872 	u8         reserved_at_b0[0x10];
10873 
10874 	u8         max_read_request_size[0x4];
10875 	u8         max_payload_size[0x4];
10876 	u8         reserved_at_c8[0x5];
10877 	u8         pwr_status[0x3];
10878 	u8         port_type[0x4];
10879 	u8         reserved_at_d4[0xb];
10880 	u8         lane_reversal[0x1];
10881 };
10882 
10883 struct mlx5_ifc_mcqi_cap_bits {
10884 	u8         supported_info_bitmask[0x20];
10885 
10886 	u8         component_size[0x20];
10887 
10888 	u8         max_component_size[0x20];
10889 
10890 	u8         log_mcda_word_size[0x4];
10891 	u8         reserved_at_64[0xc];
10892 	u8         mcda_max_write_size[0x10];
10893 
10894 	u8         rd_en[0x1];
10895 	u8         reserved_at_81[0x1];
10896 	u8         match_chip_id[0x1];
10897 	u8         match_psid[0x1];
10898 	u8         check_user_timestamp[0x1];
10899 	u8         match_base_guid_mac[0x1];
10900 	u8         reserved_at_86[0x1a];
10901 };
10902 
10903 struct mlx5_ifc_mcqi_reg_bits {
10904 	u8         read_pending_component[0x1];
10905 	u8         reserved_at_1[0xf];
10906 	u8         component_index[0x10];
10907 
10908 	u8         reserved_at_20[0x20];
10909 
10910 	u8         reserved_at_40[0x1b];
10911 	u8         info_type[0x5];
10912 
10913 	u8         info_size[0x20];
10914 
10915 	u8         offset[0x20];
10916 
10917 	u8         reserved_at_a0[0x10];
10918 	u8         data_size[0x10];
10919 
10920 	u8         data[0][0x20];
10921 };
10922 
10923 struct mlx5_ifc_mcc_reg_bits {
10924 	u8         reserved_at_0[0x4];
10925 	u8         time_elapsed_since_last_cmd[0xc];
10926 	u8         reserved_at_10[0x8];
10927 	u8         instruction[0x8];
10928 
10929 	u8         reserved_at_20[0x10];
10930 	u8         component_index[0x10];
10931 
10932 	u8         reserved_at_40[0x8];
10933 	u8         update_handle[0x18];
10934 
10935 	u8         handle_owner_type[0x4];
10936 	u8         handle_owner_host_id[0x4];
10937 	u8         reserved_at_68[0x1];
10938 	u8         control_progress[0x7];
10939 	u8         error_code[0x8];
10940 	u8         reserved_at_78[0x4];
10941 	u8         control_state[0x4];
10942 
10943 	u8         component_size[0x20];
10944 
10945 	u8         reserved_at_a0[0x60];
10946 };
10947 
10948 struct mlx5_ifc_mcda_reg_bits {
10949 	u8         reserved_at_0[0x8];
10950 	u8         update_handle[0x18];
10951 
10952 	u8         offset[0x20];
10953 
10954 	u8         reserved_at_40[0x10];
10955 	u8         size[0x10];
10956 
10957 	u8         reserved_at_60[0x20];
10958 
10959 	u8         data[0][0x20];
10960 };
10961 
10962 union mlx5_ifc_ports_control_registers_document_bits {
10963 	struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
10964 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10965 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10966 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10967 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10968 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10969 	struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
10970 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10971 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10972 	struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
10973 	struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
10974 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10975 	struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
10976 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
10977 	struct mlx5_ifc_paos_reg_bits paos_reg;
10978 	struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
10979 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
10980 	struct mlx5_ifc_peir_reg_bits peir_reg;
10981 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
10982 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10983 	struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
10984 	struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
10985 	struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
10986 	struct mlx5_ifc_phrr_reg_bits phrr_reg;
10987 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10988 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
10989 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
10990 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
10991 	struct mlx5_ifc_plib_reg_bits plib_reg;
10992 	struct mlx5_ifc_pll_status_data_bits pll_status_data;
10993 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
10994 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10995 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10996 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10997 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10998 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10999 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11000 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11001 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
11002 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11003 	struct mlx5_ifc_ppll_reg_bits ppll_reg;
11004 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
11005 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
11006 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11007 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
11008 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
11009 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
11010 	struct mlx5_ifc_pude_reg_bits pude_reg;
11011 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11012 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
11013 	struct mlx5_ifc_slrp_reg_bits slrp_reg;
11014 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
11015 	u8         reserved_0[0x7880];
11016 };
11017 
11018 union mlx5_ifc_debug_enhancements_document_bits {
11019 	struct mlx5_ifc_health_buffer_bits health_buffer;
11020 	u8         reserved_0[0x200];
11021 };
11022 
11023 union mlx5_ifc_no_dram_nic_document_bits {
11024 	struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
11025 	struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
11026 	struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
11027 	struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
11028 	struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
11029 	struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
11030 	struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
11031 	struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
11032 	u8         reserved_0[0x3160];
11033 };
11034 
11035 union mlx5_ifc_uplink_pci_interface_document_bits {
11036 	struct mlx5_ifc_initial_seg_bits initial_seg;
11037 	struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
11038 	u8         reserved_0[0x20120];
11039 };
11040 
11041 struct mlx5_ifc_qpdpm_dscp_reg_bits {
11042 	u8         e[0x1];
11043 	u8         reserved_at_01[0x0b];
11044 	u8         prio[0x04];
11045 };
11046 
11047 struct mlx5_ifc_qpdpm_reg_bits {
11048 	u8                                     reserved_at_0[0x8];
11049 	u8                                     local_port[0x8];
11050 	u8                                     reserved_at_10[0x10];
11051 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11052 };
11053 
11054 struct mlx5_ifc_qpts_reg_bits {
11055 	u8         reserved_at_0[0x8];
11056 	u8         local_port[0x8];
11057 	u8         reserved_at_10[0x2d];
11058 	u8         trust_state[0x3];
11059 };
11060 
11061 struct mlx5_ifc_mfrl_reg_bits {
11062 	u8         reserved_at_0[0x38];
11063 	u8         reset_level[0x8];
11064 };
11065 
11066 enum {
11067       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP	= 0x9009,
11068       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR	= 0x9109,
11069       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP	= 0x900a,
11070       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE	= 0x900b,
11071       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR	= 0x900f,
11072       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE	= 0x910b,
11073       MLX5_MAX_TEMPERATURE = 16,
11074 };
11075 
11076 struct mlx5_ifc_mtbr_temp_record_bits {
11077 	u8         max_temperature[0x10];
11078 	u8         temperature[0x10];
11079 };
11080 
11081 struct mlx5_ifc_mtbr_reg_bits {
11082 	u8         reserved_at_0[0x14];
11083 	u8         base_sensor_index[0xc];
11084 
11085 	u8         reserved_at_20[0x18];
11086 	u8         num_rec[0x8];
11087 
11088 	u8         reserved_at_40[0x40];
11089 
11090 	struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
11091 };
11092 
11093 struct mlx5_ifc_mtbr_reg_ext_bits {
11094 	u8         reserved_at_0[0x14];
11095 	u8         base_sensor_index[0xc];
11096 
11097 	u8         reserved_at_20[0x18];
11098 	u8         num_rec[0x8];
11099 
11100 	u8         reserved_at_40[0x40];
11101 
11102     struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
11103 };
11104 
11105 struct mlx5_ifc_mtcap_bits {
11106 	u8         reserved_at_0[0x19];
11107 	u8         sensor_count[0x7];
11108 
11109 	u8         reserved_at_20[0x19];
11110 	u8         internal_sensor_count[0x7];
11111 
11112 	u8         sensor_map[0x40];
11113 };
11114 
11115 struct mlx5_ifc_mtcap_ext_bits {
11116 	u8         reserved_at_0[0x19];
11117 	u8         sensor_count[0x7];
11118 
11119 	u8         reserved_at_20[0x20];
11120 
11121 	u8         sensor_map[0x40];
11122 };
11123 
11124 struct mlx5_ifc_mtecr_bits {
11125 	u8         reserved_at_0[0x4];
11126 	u8         last_sensor[0xc];
11127 	u8         reserved_at_10[0x4];
11128 	u8         sensor_count[0xc];
11129 
11130 	u8         reserved_at_20[0x19];
11131 	u8         internal_sensor_count[0x7];
11132 
11133 	u8         sensor_map_0[0x20];
11134 
11135 	u8         reserved_at_60[0x2a0];
11136 };
11137 
11138 struct mlx5_ifc_mtecr_ext_bits {
11139 	u8         reserved_at_0[0x4];
11140 	u8         last_sensor[0xc];
11141 	u8         reserved_at_10[0x4];
11142 	u8         sensor_count[0xc];
11143 
11144 	u8         reserved_at_20[0x20];
11145 
11146 	u8         sensor_map_0[0x20];
11147 
11148 	u8         reserved_at_60[0x2a0];
11149 };
11150 
11151 struct mlx5_ifc_mtewe_bits {
11152 	u8         reserved_at_0[0x4];
11153 	u8         last_sensor[0xc];
11154 	u8         reserved_at_10[0x4];
11155 	u8         sensor_count[0xc];
11156 
11157 	u8         sensor_warning_0[0x20];
11158 
11159 	u8         reserved_at_40[0x2a0];
11160 };
11161 
11162 struct mlx5_ifc_mtewe_ext_bits {
11163 	u8         reserved_at_0[0x4];
11164 	u8         last_sensor[0xc];
11165 	u8         reserved_at_10[0x4];
11166 	u8         sensor_count[0xc];
11167 
11168 	u8         sensor_warning_0[0x20];
11169 
11170 	u8         reserved_at_40[0x2a0];
11171 };
11172 
11173 struct mlx5_ifc_mtmp_bits {
11174 	u8         reserved_at_0[0x14];
11175 	u8         sensor_index[0xc];
11176 
11177 	u8         reserved_at_20[0x10];
11178 	u8         temperature[0x10];
11179 
11180 	u8         mte[0x1];
11181 	u8         mtr[0x1];
11182 	u8         reserved_at_42[0xe];
11183 	u8         max_temperature[0x10];
11184 
11185 	u8         tee[0x2];
11186 	u8         reserved_at_62[0xe];
11187 	u8         temperature_threshold_hi[0x10];
11188 
11189 	u8         reserved_at_80[0x10];
11190 	u8         temperature_threshold_lo[0x10];
11191 
11192 	u8         reserved_at_a0[0x20];
11193 
11194 	u8         sensor_name_hi[0x20];
11195 
11196 	u8         sensor_name_lo[0x20];
11197 };
11198 
11199 struct mlx5_ifc_mtmp_ext_bits {
11200 	u8         reserved_at_0[0x14];
11201 	u8         sensor_index[0xc];
11202 
11203 	u8         reserved_at_20[0x10];
11204 	u8         temperature[0x10];
11205 
11206 	u8         mte[0x1];
11207 	u8         mtr[0x1];
11208 	u8         reserved_at_42[0xe];
11209 	u8         max_temperature[0x10];
11210 
11211 	u8         tee[0x2];
11212 	u8         reserved_at_62[0xe];
11213 	u8         temperature_threshold_hi[0x10];
11214 
11215 	u8         reserved_at_80[0x10];
11216 	u8         temperature_threshold_lo[0x10];
11217 
11218 	u8         reserved_at_a0[0x20];
11219 
11220 	u8         sensor_name_hi[0x20];
11221 
11222 	u8         sensor_name_lo[0x20];
11223 };
11224 
11225 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
11226 	u8         opcode[0x10];
11227 	u8         uid[0x10];
11228 
11229 	u8         vhca_tunnel_id[0x10];
11230 	u8         obj_type[0x10];
11231 
11232 	u8         obj_id[0x20];
11233 
11234 	u8         reserved_at_60[0x20];
11235 };
11236 
11237 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
11238 	u8         status[0x8];
11239 	u8         reserved_at_8[0x18];
11240 
11241 	u8         syndrome[0x20];
11242 
11243 	u8         obj_id[0x20];
11244 
11245 	u8         reserved_at_60[0x20];
11246 };
11247 
11248 struct mlx5_ifc_umem_bits {
11249 	u8         reserved_at_0[0x80];
11250 
11251 	u8         reserved_at_80[0x1b];
11252 	u8         log_page_size[0x5];
11253 
11254 	u8         page_offset[0x20];
11255 
11256 	u8         num_of_mtt[0x40];
11257 
11258 	struct mlx5_ifc_mtt_bits  mtt[0];
11259 };
11260 
11261 struct mlx5_ifc_uctx_bits {
11262 	u8         cap[0x20];
11263 
11264 	u8         reserved_at_20[0x160];
11265 };
11266 
11267 struct mlx5_ifc_create_umem_in_bits {
11268 	u8         opcode[0x10];
11269 	u8         uid[0x10];
11270 
11271 	u8         reserved_at_20[0x10];
11272 	u8         op_mod[0x10];
11273 
11274 	u8         reserved_at_40[0x40];
11275 
11276 	struct mlx5_ifc_umem_bits  umem;
11277 };
11278 
11279 struct mlx5_ifc_create_uctx_in_bits {
11280 	u8         opcode[0x10];
11281 	u8         reserved_at_10[0x10];
11282 
11283 	u8         reserved_at_20[0x10];
11284 	u8         op_mod[0x10];
11285 
11286 	u8         reserved_at_40[0x40];
11287 
11288 	struct mlx5_ifc_uctx_bits  uctx;
11289 };
11290 
11291 struct mlx5_ifc_destroy_uctx_in_bits {
11292 	u8         opcode[0x10];
11293 	u8         reserved_at_10[0x10];
11294 
11295 	u8         reserved_at_20[0x10];
11296 	u8         op_mod[0x10];
11297 
11298 	u8         reserved_at_40[0x10];
11299 	u8         uid[0x10];
11300 
11301 	u8         reserved_at_60[0x20];
11302 };
11303 
11304 struct mlx5_ifc_mtrc_string_db_param_bits {
11305 	u8         string_db_base_address[0x20];
11306 
11307 	u8         reserved_at_20[0x8];
11308 	u8         string_db_size[0x18];
11309 };
11310 
11311 struct mlx5_ifc_mtrc_cap_bits {
11312 	u8         trace_owner[0x1];
11313 	u8         trace_to_memory[0x1];
11314 	u8         reserved_at_2[0x4];
11315 	u8         trc_ver[0x2];
11316 	u8         reserved_at_8[0x14];
11317 	u8         num_string_db[0x4];
11318 
11319 	u8         first_string_trace[0x8];
11320 	u8         num_string_trace[0x8];
11321 	u8         reserved_at_30[0x28];
11322 
11323 	u8         log_max_trace_buffer_size[0x8];
11324 
11325 	u8         reserved_at_60[0x20];
11326 
11327 	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11328 
11329 	u8         reserved_at_280[0x180];
11330 };
11331 
11332 struct mlx5_ifc_mtrc_conf_bits {
11333 	u8         reserved_at_0[0x1c];
11334 	u8         trace_mode[0x4];
11335 	u8         reserved_at_20[0x18];
11336 	u8         log_trace_buffer_size[0x8];
11337 	u8         trace_mkey[0x20];
11338 	u8         reserved_at_60[0x3a0];
11339 };
11340 
11341 struct mlx5_ifc_mtrc_stdb_bits {
11342 	u8         string_db_index[0x4];
11343 	u8         reserved_at_4[0x4];
11344 	u8         read_size[0x18];
11345 	u8         start_offset[0x20];
11346 	u8         string_db_data[0];
11347 };
11348 
11349 struct mlx5_ifc_mtrc_ctrl_bits {
11350 	u8         trace_status[0x2];
11351 	u8         reserved_at_2[0x2];
11352 	u8         arm_event[0x1];
11353 	u8         reserved_at_5[0xb];
11354 	u8         modify_field_select[0x10];
11355 	u8         reserved_at_20[0x2b];
11356 	u8         current_timestamp52_32[0x15];
11357 	u8         current_timestamp31_0[0x20];
11358 	u8         reserved_at_80[0x180];
11359 };
11360 
11361 struct mlx5_ifc_affiliated_event_header_bits {
11362 	u8         reserved_at_0[0x10];
11363 	u8         obj_type[0x10];
11364 
11365 	u8         obj_id[0x20];
11366 };
11367 
11368 #endif /* MLX5_IFC_H */
11369