1 /*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 27 Autogenerated file. 28 Date: 2015-04-13 14:59 29 Source Document Name: Mellanox <Doc Name> 30 Source Document Version: 0.28 31 Generated by adb_to_c.py (EAT.ME Version: 1.0.70) 32 */ 33 #ifndef MLX5_IFC_H 34 #define MLX5_IFC_H 35 36 enum { 37 MLX5_EVENT_TYPE_COMP = 0x0, 38 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 39 MLX5_EVENT_TYPE_COMM_EST = 0x2, 40 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 41 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 42 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 43 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 44 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 45 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 46 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 47 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 48 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 49 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 50 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 51 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 52 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 53 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 54 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 55 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 56 MLX5_EVENT_TYPE_CODING_TEMP_WARNING_EVENT = 0x17, 57 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 58 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 59 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 60 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 61 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 62 MLX5_EVENT_TYPE_CMD = 0xa, 63 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 64 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd 65 }; 66 67 enum { 68 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 69 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 70 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 71 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 72 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 73 }; 74 75 enum { 76 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 77 }; 78 79 enum { 80 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 81 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 82 MLX5_CMD_OP_INIT_HCA = 0x102, 83 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 84 MLX5_CMD_OP_ENABLE_HCA = 0x104, 85 MLX5_CMD_OP_DISABLE_HCA = 0x105, 86 MLX5_CMD_OP_QUERY_PAGES = 0x107, 87 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 88 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 89 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 90 MLX5_CMD_OP_SET_ISSI = 0x10b, 91 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 92 MLX5_CMD_OP_CREATE_MKEY = 0x200, 93 MLX5_CMD_OP_QUERY_MKEY = 0x201, 94 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 95 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 96 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 97 MLX5_CMD_OP_CREATE_EQ = 0x301, 98 MLX5_CMD_OP_DESTROY_EQ = 0x302, 99 MLX5_CMD_OP_QUERY_EQ = 0x303, 100 MLX5_CMD_OP_GEN_EQE = 0x304, 101 MLX5_CMD_OP_CREATE_CQ = 0x400, 102 MLX5_CMD_OP_DESTROY_CQ = 0x401, 103 MLX5_CMD_OP_QUERY_CQ = 0x402, 104 MLX5_CMD_OP_MODIFY_CQ = 0x403, 105 MLX5_CMD_OP_CREATE_QP = 0x500, 106 MLX5_CMD_OP_DESTROY_QP = 0x501, 107 MLX5_CMD_OP_RST2INIT_QP = 0x502, 108 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 109 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 110 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 111 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 112 MLX5_CMD_OP_2ERR_QP = 0x507, 113 MLX5_CMD_OP_2RST_QP = 0x50a, 114 MLX5_CMD_OP_QUERY_QP = 0x50b, 115 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 116 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 117 MLX5_CMD_OP_CREATE_PSV = 0x600, 118 MLX5_CMD_OP_DESTROY_PSV = 0x601, 119 MLX5_CMD_OP_CREATE_SRQ = 0x700, 120 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 121 MLX5_CMD_OP_QUERY_SRQ = 0x702, 122 MLX5_CMD_OP_ARM_RQ = 0x703, 123 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 124 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 125 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 126 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 127 MLX5_CMD_OP_CREATE_DCT = 0x710, 128 MLX5_CMD_OP_DESTROY_DCT = 0x711, 129 MLX5_CMD_OP_DRAIN_DCT = 0x712, 130 MLX5_CMD_OP_QUERY_DCT = 0x713, 131 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 132 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 133 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 134 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 135 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 141 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 146 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 147 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 148 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 149 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 150 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 151 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 152 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 153 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 154 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 155 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 156 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 157 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 158 MLX5_CMD_OP_ALLOC_PD = 0x800, 159 MLX5_CMD_OP_DEALLOC_PD = 0x801, 160 MLX5_CMD_OP_ALLOC_UAR = 0x802, 161 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 162 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 163 MLX5_CMD_OP_ACCESS_REG = 0x805, 164 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 165 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 166 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 167 MLX5_CMD_OP_MAD_IFC = 0x50d, 168 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 169 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 170 MLX5_CMD_OP_NOP = 0x80d, 171 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 172 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 173 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 174 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 175 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 176 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 177 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 178 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 179 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 180 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 181 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 182 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 183 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 184 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 185 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 186 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 187 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 188 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 189 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 190 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 191 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 192 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 193 MLX5_CMD_OP_CREATE_TIR = 0x900, 194 MLX5_CMD_OP_MODIFY_TIR = 0x901, 195 MLX5_CMD_OP_DESTROY_TIR = 0x902, 196 MLX5_CMD_OP_QUERY_TIR = 0x903, 197 MLX5_CMD_OP_CREATE_SQ = 0x904, 198 MLX5_CMD_OP_MODIFY_SQ = 0x905, 199 MLX5_CMD_OP_DESTROY_SQ = 0x906, 200 MLX5_CMD_OP_QUERY_SQ = 0x907, 201 MLX5_CMD_OP_CREATE_RQ = 0x908, 202 MLX5_CMD_OP_MODIFY_RQ = 0x909, 203 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 204 MLX5_CMD_OP_QUERY_RQ = 0x90b, 205 MLX5_CMD_OP_CREATE_RMP = 0x90c, 206 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 207 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 208 MLX5_CMD_OP_QUERY_RMP = 0x90f, 209 MLX5_CMD_OP_CREATE_TIS = 0x912, 210 MLX5_CMD_OP_MODIFY_TIS = 0x913, 211 MLX5_CMD_OP_DESTROY_TIS = 0x914, 212 MLX5_CMD_OP_QUERY_TIS = 0x915, 213 MLX5_CMD_OP_CREATE_RQT = 0x916, 214 MLX5_CMD_OP_MODIFY_RQT = 0x917, 215 MLX5_CMD_OP_DESTROY_RQT = 0x918, 216 MLX5_CMD_OP_QUERY_RQT = 0x919, 217 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 218 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 219 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 220 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 221 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 222 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 223 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 224 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 225 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 226 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 227 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 228 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 229 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b 230 }; 231 232 enum { 233 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 234 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 235 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 236 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 237 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 238 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 239 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 240 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 241 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 242 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 243 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 244 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 245 }; 246 247 struct mlx5_ifc_flow_table_fields_supported_bits { 248 u8 outer_dmac[0x1]; 249 u8 outer_smac[0x1]; 250 u8 outer_ether_type[0x1]; 251 u8 reserved_0[0x1]; 252 u8 outer_first_prio[0x1]; 253 u8 outer_first_cfi[0x1]; 254 u8 outer_first_vid[0x1]; 255 u8 reserved_1[0x1]; 256 u8 outer_second_prio[0x1]; 257 u8 outer_second_cfi[0x1]; 258 u8 outer_second_vid[0x1]; 259 u8 outer_ipv6_flow_label[0x1]; 260 u8 outer_sip[0x1]; 261 u8 outer_dip[0x1]; 262 u8 outer_frag[0x1]; 263 u8 outer_ip_protocol[0x1]; 264 u8 outer_ip_ecn[0x1]; 265 u8 outer_ip_dscp[0x1]; 266 u8 outer_udp_sport[0x1]; 267 u8 outer_udp_dport[0x1]; 268 u8 outer_tcp_sport[0x1]; 269 u8 outer_tcp_dport[0x1]; 270 u8 outer_tcp_flags[0x1]; 271 u8 outer_gre_protocol[0x1]; 272 u8 outer_gre_key[0x1]; 273 u8 outer_vxlan_vni[0x1]; 274 u8 reserved_2[0x5]; 275 u8 source_eswitch_port[0x1]; 276 277 u8 inner_dmac[0x1]; 278 u8 inner_smac[0x1]; 279 u8 inner_ether_type[0x1]; 280 u8 reserved_3[0x1]; 281 u8 inner_first_prio[0x1]; 282 u8 inner_first_cfi[0x1]; 283 u8 inner_first_vid[0x1]; 284 u8 reserved_4[0x1]; 285 u8 inner_second_prio[0x1]; 286 u8 inner_second_cfi[0x1]; 287 u8 inner_second_vid[0x1]; 288 u8 inner_ipv6_flow_label[0x1]; 289 u8 inner_sip[0x1]; 290 u8 inner_dip[0x1]; 291 u8 inner_frag[0x1]; 292 u8 inner_ip_protocol[0x1]; 293 u8 inner_ip_ecn[0x1]; 294 u8 inner_ip_dscp[0x1]; 295 u8 inner_udp_sport[0x1]; 296 u8 inner_udp_dport[0x1]; 297 u8 inner_tcp_sport[0x1]; 298 u8 inner_tcp_dport[0x1]; 299 u8 inner_tcp_flags[0x1]; 300 u8 reserved_5[0x9]; 301 302 u8 reserved_6[0x1f]; 303 u8 source_sqn[0x1]; 304 305 u8 reserved_7[0x20]; 306 }; 307 308 struct mlx5_ifc_eth_discard_cntrs_grp_bits { 309 u8 ingress_general_high[0x20]; 310 311 u8 ingress_general_low[0x20]; 312 313 u8 ingress_policy_engine_high[0x20]; 314 315 u8 ingress_policy_engine_low[0x20]; 316 317 u8 ingress_vlan_membership_high[0x20]; 318 319 u8 ingress_vlan_membership_low[0x20]; 320 321 u8 ingress_tag_frame_type_high[0x20]; 322 323 u8 ingress_tag_frame_type_low[0x20]; 324 325 u8 egress_vlan_membership_high[0x20]; 326 327 u8 egress_vlan_membership_low[0x20]; 328 329 u8 loopback_filter_high[0x20]; 330 331 u8 loopback_filter_low[0x20]; 332 333 u8 egress_general_high[0x20]; 334 335 u8 egress_general_low[0x20]; 336 337 u8 reserved_at_1c0[0x40]; 338 339 u8 egress_hoq_high[0x20]; 340 341 u8 egress_hoq_low[0x20]; 342 343 u8 port_isolation_high[0x20]; 344 345 u8 port_isolation_low[0x20]; 346 347 u8 egress_policy_engine_high[0x20]; 348 349 u8 egress_policy_engine_low[0x20]; 350 351 u8 ingress_tx_link_down_high[0x20]; 352 353 u8 ingress_tx_link_down_low[0x20]; 354 355 u8 egress_stp_filter_high[0x20]; 356 357 u8 egress_stp_filter_low[0x20]; 358 359 u8 reserved_at_340[0x480]; 360 }; 361 struct mlx5_ifc_flow_table_prop_layout_bits { 362 u8 ft_support[0x1]; 363 u8 flow_tag[0x1]; 364 u8 flow_counter[0x1]; 365 u8 flow_modify_en[0x1]; 366 u8 modify_root[0x1]; 367 u8 reserved_0[0x1b]; 368 369 u8 reserved_1[0x2]; 370 u8 log_max_ft_size[0x6]; 371 u8 reserved_2[0x10]; 372 u8 max_ft_level[0x8]; 373 374 u8 reserved_3[0x20]; 375 376 u8 reserved_4[0x18]; 377 u8 log_max_ft_num[0x8]; 378 379 u8 reserved_5[0x10]; 380 u8 log_max_flow_counter[0x8]; 381 u8 log_max_destination[0x8]; 382 383 u8 reserved_6[0x18]; 384 u8 log_max_flow[0x8]; 385 386 u8 reserved_7[0x40]; 387 388 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 389 390 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 391 }; 392 393 struct mlx5_ifc_odp_per_transport_service_cap_bits { 394 u8 send[0x1]; 395 u8 receive[0x1]; 396 u8 write[0x1]; 397 u8 read[0x1]; 398 u8 atomic[0x1]; 399 u8 srq_receive[0x1]; 400 u8 reserved_0[0x1a]; 401 }; 402 403 struct mlx5_ifc_flow_counter_list_bits { 404 u8 reserved_0[0x10]; 405 u8 flow_counter_id[0x10]; 406 407 u8 reserved_1[0x20]; 408 }; 409 410 enum { 411 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 412 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 413 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 414 }; 415 416 struct mlx5_ifc_dest_format_struct_bits { 417 u8 destination_type[0x8]; 418 u8 destination_id[0x18]; 419 420 u8 reserved_0[0x20]; 421 }; 422 423 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 424 u8 smac_47_16[0x20]; 425 426 u8 smac_15_0[0x10]; 427 u8 ethertype[0x10]; 428 429 u8 dmac_47_16[0x20]; 430 431 u8 dmac_15_0[0x10]; 432 u8 first_prio[0x3]; 433 u8 first_cfi[0x1]; 434 u8 first_vid[0xc]; 435 436 u8 ip_protocol[0x8]; 437 u8 ip_dscp[0x6]; 438 u8 ip_ecn[0x2]; 439 u8 cvlan_tag[0x1]; 440 u8 svlan_tag[0x1]; 441 u8 frag[0x1]; 442 u8 reserved_1[0x4]; 443 u8 tcp_flags[0x9]; 444 445 u8 tcp_sport[0x10]; 446 u8 tcp_dport[0x10]; 447 448 u8 reserved_2[0x20]; 449 450 u8 udp_sport[0x10]; 451 u8 udp_dport[0x10]; 452 453 u8 src_ip[4][0x20]; 454 455 u8 dst_ip[4][0x20]; 456 }; 457 458 struct mlx5_ifc_fte_match_set_misc_bits { 459 u8 reserved_0[0x8]; 460 u8 source_sqn[0x18]; 461 462 u8 reserved_1[0x10]; 463 u8 source_port[0x10]; 464 465 u8 outer_second_prio[0x3]; 466 u8 outer_second_cfi[0x1]; 467 u8 outer_second_vid[0xc]; 468 u8 inner_second_prio[0x3]; 469 u8 inner_second_cfi[0x1]; 470 u8 inner_second_vid[0xc]; 471 472 u8 outer_second_vlan_tag[0x1]; 473 u8 inner_second_vlan_tag[0x1]; 474 u8 reserved_2[0xe]; 475 u8 gre_protocol[0x10]; 476 477 u8 gre_key_h[0x18]; 478 u8 gre_key_l[0x8]; 479 480 u8 vxlan_vni[0x18]; 481 u8 reserved_3[0x8]; 482 483 u8 geneve_vni[0x18]; 484 u8 reserved4[0x7]; 485 u8 geneve_oam[0x1]; 486 487 u8 reserved_5[0xc]; 488 u8 outer_ipv6_flow_label[0x14]; 489 490 u8 reserved_6[0xc]; 491 u8 inner_ipv6_flow_label[0x14]; 492 493 u8 reserved7[0x10]; 494 u8 geneve_protocol_type[0x10]; 495 u8 reserved8[0xc0]; 496 }; 497 498 struct mlx5_ifc_cmd_pas_bits { 499 u8 pa_h[0x20]; 500 501 u8 pa_l[0x14]; 502 u8 reserved_0[0xc]; 503 }; 504 505 struct mlx5_ifc_uint64_bits { 506 u8 hi[0x20]; 507 508 u8 lo[0x20]; 509 }; 510 511 struct mlx5_ifc_application_prio_entry_bits { 512 u8 reserved_0[0x8]; 513 u8 priority[0x3]; 514 u8 reserved_1[0x2]; 515 u8 sel[0x3]; 516 u8 protocol_id[0x10]; 517 }; 518 519 struct mlx5_ifc_nodnic_ring_doorbell_bits { 520 u8 reserved_0[0x8]; 521 u8 ring_pi[0x10]; 522 u8 reserved_1[0x8]; 523 }; 524 525 enum { 526 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 527 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 528 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 529 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 530 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 531 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 532 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 533 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 534 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 535 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 536 }; 537 538 struct mlx5_ifc_ads_bits { 539 u8 fl[0x1]; 540 u8 free_ar[0x1]; 541 u8 reserved_0[0xe]; 542 u8 pkey_index[0x10]; 543 544 u8 reserved_1[0x8]; 545 u8 grh[0x1]; 546 u8 mlid[0x7]; 547 u8 rlid[0x10]; 548 549 u8 ack_timeout[0x5]; 550 u8 reserved_2[0x3]; 551 u8 src_addr_index[0x8]; 552 u8 log_rtm[0x4]; 553 u8 stat_rate[0x4]; 554 u8 hop_limit[0x8]; 555 556 u8 reserved_3[0x4]; 557 u8 tclass[0x8]; 558 u8 flow_label[0x14]; 559 560 u8 rgid_rip[16][0x8]; 561 562 u8 reserved_4[0x4]; 563 u8 f_dscp[0x1]; 564 u8 f_ecn[0x1]; 565 u8 reserved_5[0x1]; 566 u8 f_eth_prio[0x1]; 567 u8 ecn[0x2]; 568 u8 dscp[0x6]; 569 u8 udp_sport[0x10]; 570 571 u8 dei_cfi[0x1]; 572 u8 eth_prio[0x3]; 573 u8 sl[0x4]; 574 u8 port[0x8]; 575 u8 rmac_47_32[0x10]; 576 577 u8 rmac_31_0[0x20]; 578 }; 579 580 struct mlx5_ifc_diagnostic_counter_cap_bits { 581 u8 sync[0x1]; 582 u8 reserved_0[0xf]; 583 u8 counter_id[0x10]; 584 }; 585 586 struct mlx5_ifc_debug_cap_bits { 587 u8 reserved_0[0x18]; 588 u8 log_max_samples[0x8]; 589 590 u8 single[0x1]; 591 u8 repetitive[0x1]; 592 u8 health_mon_rx_activity[0x1]; 593 u8 reserved_1[0x15]; 594 u8 log_min_sample_period[0x8]; 595 596 u8 reserved_2[0x1c0]; 597 598 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 599 }; 600 601 struct mlx5_ifc_qos_cap_bits { 602 u8 packet_pacing[0x1]; 603 u8 esw_scheduling[0x1]; 604 u8 esw_bw_share[0x1]; 605 u8 esw_rate_limit[0x1]; 606 u8 hll[0x1]; 607 u8 packet_pacing_burst_bound[0x1]; 608 u8 reserved_at_6[0x1a]; 609 610 u8 reserved_at_20[0x20]; 611 612 u8 packet_pacing_max_rate[0x20]; 613 614 u8 packet_pacing_min_rate[0x20]; 615 616 u8 reserved_at_80[0x10]; 617 u8 packet_pacing_rate_table_size[0x10]; 618 619 u8 esw_element_type[0x10]; 620 u8 esw_tsar_type[0x10]; 621 622 u8 reserved_at_c0[0x10]; 623 u8 max_qos_para_vport[0x10]; 624 625 u8 max_tsar_bw_share[0x20]; 626 627 u8 reserved_at_100[0x700]; 628 }; 629 630 struct mlx5_ifc_snapshot_cap_bits { 631 u8 reserved_0[0x1d]; 632 u8 suspend_qp_uc[0x1]; 633 u8 suspend_qp_ud[0x1]; 634 u8 suspend_qp_rc[0x1]; 635 636 u8 reserved_1[0x1c]; 637 u8 restore_pd[0x1]; 638 u8 restore_uar[0x1]; 639 u8 restore_mkey[0x1]; 640 u8 restore_qp[0x1]; 641 642 u8 reserved_2[0x1e]; 643 u8 named_mkey[0x1]; 644 u8 named_qp[0x1]; 645 646 u8 reserved_3[0x7a0]; 647 }; 648 649 struct mlx5_ifc_e_switch_cap_bits { 650 u8 vport_svlan_strip[0x1]; 651 u8 vport_cvlan_strip[0x1]; 652 u8 vport_svlan_insert[0x1]; 653 u8 vport_cvlan_insert_if_not_exist[0x1]; 654 u8 vport_cvlan_insert_overwrite[0x1]; 655 656 u8 reserved_0[0x19]; 657 658 u8 nic_vport_node_guid_modify[0x1]; 659 u8 nic_vport_port_guid_modify[0x1]; 660 661 u8 reserved_1[0x7e0]; 662 }; 663 664 struct mlx5_ifc_flow_table_eswitch_cap_bits { 665 u8 reserved_0[0x200]; 666 667 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 668 669 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 670 671 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 672 673 u8 reserved_1[0x7800]; 674 }; 675 676 struct mlx5_ifc_flow_table_nic_cap_bits { 677 u8 reserved_0[0x200]; 678 679 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 680 681 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 682 683 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 684 685 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 686 687 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 688 689 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 690 691 u8 reserved_1[0x7200]; 692 }; 693 694 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 695 u8 csum_cap[0x1]; 696 u8 vlan_cap[0x1]; 697 u8 lro_cap[0x1]; 698 u8 lro_psh_flag[0x1]; 699 u8 lro_time_stamp[0x1]; 700 u8 lro_max_msg_sz_mode[0x2]; 701 u8 reserved_0[0x2]; 702 u8 self_lb_mc[0x1]; 703 u8 self_lb_uc[0x1]; 704 u8 max_lso_cap[0x5]; 705 u8 multi_pkt_send_wqe[0x2]; 706 u8 wqe_inline_mode[0x2]; 707 u8 rss_ind_tbl_cap[0x4]; 708 u8 reserved_1[0x3]; 709 u8 tunnel_lso_const_out_ip_id[0x1]; 710 u8 tunnel_lro_gre[0x1]; 711 u8 tunnel_lro_vxlan[0x1]; 712 u8 tunnel_statless_gre[0x1]; 713 u8 tunnel_stateless_vxlan[0x1]; 714 715 u8 swp[0x1]; 716 u8 swp_csum[0x1]; 717 u8 swp_lso[0x1]; 718 u8 reserved_2[0x1c]; 719 u8 tunnel_stateless_geneve_rx[0x1]; 720 721 u8 reserved_3[0x10]; 722 u8 lro_min_mss_size[0x10]; 723 724 u8 reserved_4[0x120]; 725 726 u8 lro_timer_supported_periods[4][0x20]; 727 728 u8 reserved_5[0x600]; 729 }; 730 731 enum { 732 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 733 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 734 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 735 }; 736 737 struct mlx5_ifc_roce_cap_bits { 738 u8 roce_apm[0x1]; 739 u8 rts2rts_primary_eth_prio[0x1]; 740 u8 roce_rx_allow_untagged[0x1]; 741 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 742 743 u8 reserved_0[0x1c]; 744 745 u8 reserved_1[0x60]; 746 747 u8 reserved_2[0xc]; 748 u8 l3_type[0x4]; 749 u8 reserved_3[0x8]; 750 u8 roce_version[0x8]; 751 752 u8 reserved_4[0x10]; 753 u8 r_roce_dest_udp_port[0x10]; 754 755 u8 r_roce_max_src_udp_port[0x10]; 756 u8 r_roce_min_src_udp_port[0x10]; 757 758 u8 reserved_5[0x10]; 759 u8 roce_address_table_size[0x10]; 760 761 u8 reserved_6[0x700]; 762 }; 763 764 enum { 765 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 766 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 767 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 768 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 769 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 770 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 771 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 772 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 773 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 774 }; 775 776 enum { 777 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 778 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 779 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 780 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 781 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 782 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 783 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 784 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 785 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 786 }; 787 788 struct mlx5_ifc_atomic_caps_bits { 789 u8 reserved_0[0x40]; 790 791 u8 atomic_req_8B_endianess_mode[0x2]; 792 u8 reserved_1[0x4]; 793 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 794 795 u8 reserved_2[0x19]; 796 797 u8 reserved_3[0x20]; 798 799 u8 reserved_4[0x10]; 800 u8 atomic_operations[0x10]; 801 802 u8 reserved_5[0x10]; 803 u8 atomic_size_qp[0x10]; 804 805 u8 reserved_6[0x10]; 806 u8 atomic_size_dc[0x10]; 807 808 u8 reserved_7[0x720]; 809 }; 810 811 struct mlx5_ifc_odp_cap_bits { 812 u8 reserved_0[0x40]; 813 814 u8 sig[0x1]; 815 u8 reserved_1[0x1f]; 816 817 u8 reserved_2[0x20]; 818 819 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 820 821 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 822 823 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 824 825 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 826 827 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 828 829 u8 reserved_3[0x6e0]; 830 }; 831 832 enum { 833 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 834 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 835 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 836 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 837 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 838 }; 839 840 enum { 841 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 842 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 843 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 844 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 845 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 846 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 847 }; 848 849 enum { 850 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 851 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 852 }; 853 854 enum { 855 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 856 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 857 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 858 }; 859 860 struct mlx5_ifc_cmd_hca_cap_bits { 861 u8 reserved_0[0x80]; 862 863 u8 log_max_srq_sz[0x8]; 864 u8 log_max_qp_sz[0x8]; 865 u8 reserved_1[0xb]; 866 u8 log_max_qp[0x5]; 867 868 u8 reserved_2[0xb]; 869 u8 log_max_srq[0x5]; 870 u8 reserved_3[0x10]; 871 872 u8 reserved_4[0x8]; 873 u8 log_max_cq_sz[0x8]; 874 u8 reserved_5[0xb]; 875 u8 log_max_cq[0x5]; 876 877 u8 log_max_eq_sz[0x8]; 878 u8 reserved_6[0x2]; 879 u8 log_max_mkey[0x6]; 880 u8 reserved_7[0xc]; 881 u8 log_max_eq[0x4]; 882 883 u8 max_indirection[0x8]; 884 u8 reserved_8[0x1]; 885 u8 log_max_mrw_sz[0x7]; 886 u8 reserved_9[0x2]; 887 u8 log_max_bsf_list_size[0x6]; 888 u8 reserved_10[0x2]; 889 u8 log_max_klm_list_size[0x6]; 890 891 u8 reserved_11[0xa]; 892 u8 log_max_ra_req_dc[0x6]; 893 u8 reserved_12[0xa]; 894 u8 log_max_ra_res_dc[0x6]; 895 896 u8 reserved_13[0xa]; 897 u8 log_max_ra_req_qp[0x6]; 898 u8 reserved_14[0xa]; 899 u8 log_max_ra_res_qp[0x6]; 900 901 u8 pad_cap[0x1]; 902 u8 cc_query_allowed[0x1]; 903 u8 cc_modify_allowed[0x1]; 904 u8 start_pad[0x1]; 905 u8 cache_line_128byte[0x1]; 906 u8 reserved_15[0xb]; 907 u8 gid_table_size[0x10]; 908 909 u8 out_of_seq_cnt[0x1]; 910 u8 vport_counters[0x1]; 911 u8 retransmission_q_counters[0x1]; 912 u8 debug[0x1]; 913 u8 reserved_16[0x2]; 914 u8 max_qp_cnt[0xa]; 915 u8 pkey_table_size[0x10]; 916 917 u8 vport_group_manager[0x1]; 918 u8 vhca_group_manager[0x1]; 919 u8 ib_virt[0x1]; 920 u8 eth_virt[0x1]; 921 u8 reserved_17[0x1]; 922 u8 ets[0x1]; 923 u8 nic_flow_table[0x1]; 924 u8 eswitch_flow_table[0x1]; 925 u8 reserved_18[0x3]; 926 u8 local_ca_ack_delay[0x5]; 927 u8 port_module_event[0x1]; 928 u8 reserved_19[0x5]; 929 u8 port_type[0x2]; 930 u8 num_ports[0x8]; 931 932 u8 snapshot[0x1]; 933 u8 reserved_20[0x2]; 934 u8 log_max_msg[0x5]; 935 u8 reserved_21[0x4]; 936 u8 max_tc[0x4]; 937 u8 temp_warn_event[0x1]; 938 u8 dcbx[0x1]; 939 u8 reserved_22[0x4]; 940 u8 rol_s[0x1]; 941 u8 rol_g[0x1]; 942 u8 reserved_23[0x1]; 943 u8 wol_s[0x1]; 944 u8 wol_g[0x1]; 945 u8 wol_a[0x1]; 946 u8 wol_b[0x1]; 947 u8 wol_m[0x1]; 948 u8 wol_u[0x1]; 949 u8 wol_p[0x1]; 950 951 u8 stat_rate_support[0x10]; 952 u8 reserved_24[0xc]; 953 u8 cqe_version[0x4]; 954 955 u8 compact_address_vector[0x1]; 956 u8 striding_rq[0x1]; 957 u8 reserved_25[0x1]; 958 u8 ipoib_enhanced_offloads[0x1]; 959 u8 ipoib_ipoib_offloads[0x1]; 960 u8 reserved_26[0x8]; 961 u8 dc_connect_qp[0x1]; 962 u8 dc_cnak_trace[0x1]; 963 u8 drain_sigerr[0x1]; 964 u8 cmdif_checksum[0x2]; 965 u8 sigerr_cqe[0x1]; 966 u8 reserved_27[0x1]; 967 u8 wq_signature[0x1]; 968 u8 sctr_data_cqe[0x1]; 969 u8 reserved_28[0x1]; 970 u8 sho[0x1]; 971 u8 tph[0x1]; 972 u8 rf[0x1]; 973 u8 dct[0x1]; 974 u8 qos[0x1]; 975 u8 eth_net_offloads[0x1]; 976 u8 roce[0x1]; 977 u8 atomic[0x1]; 978 u8 reserved_30[0x1]; 979 980 u8 cq_oi[0x1]; 981 u8 cq_resize[0x1]; 982 u8 cq_moderation[0x1]; 983 u8 reserved_31[0x3]; 984 u8 cq_eq_remap[0x1]; 985 u8 pg[0x1]; 986 u8 block_lb_mc[0x1]; 987 u8 exponential_backoff[0x1]; 988 u8 scqe_break_moderation[0x1]; 989 u8 cq_period_start_from_cqe[0x1]; 990 u8 cd[0x1]; 991 u8 atm[0x1]; 992 u8 apm[0x1]; 993 u8 reserved_32[0x7]; 994 u8 qkv[0x1]; 995 u8 pkv[0x1]; 996 u8 reserved_33[0x4]; 997 u8 xrc[0x1]; 998 u8 ud[0x1]; 999 u8 uc[0x1]; 1000 u8 rc[0x1]; 1001 1002 u8 reserved_34[0xa]; 1003 u8 uar_sz[0x6]; 1004 u8 reserved_35[0x8]; 1005 u8 log_pg_sz[0x8]; 1006 1007 u8 bf[0x1]; 1008 u8 driver_version[0x1]; 1009 u8 pad_tx_eth_packet[0x1]; 1010 u8 reserved_36[0x8]; 1011 u8 log_bf_reg_size[0x5]; 1012 u8 reserved_37[0x10]; 1013 1014 u8 num_of_diagnostic_counters[0x10]; 1015 u8 max_wqe_sz_sq[0x10]; 1016 1017 u8 reserved_38[0x10]; 1018 u8 max_wqe_sz_rq[0x10]; 1019 1020 u8 reserved_39[0x10]; 1021 u8 max_wqe_sz_sq_dc[0x10]; 1022 1023 u8 reserved_40[0x7]; 1024 u8 max_qp_mcg[0x19]; 1025 1026 u8 reserved_41[0x18]; 1027 u8 log_max_mcg[0x8]; 1028 1029 u8 reserved_42[0x3]; 1030 u8 log_max_transport_domain[0x5]; 1031 u8 reserved_43[0x3]; 1032 u8 log_max_pd[0x5]; 1033 u8 reserved_44[0xb]; 1034 u8 log_max_xrcd[0x5]; 1035 1036 u8 reserved_45[0x10]; 1037 u8 max_flow_counter[0x10]; 1038 1039 u8 reserved_46[0x3]; 1040 u8 log_max_rq[0x5]; 1041 u8 reserved_47[0x3]; 1042 u8 log_max_sq[0x5]; 1043 u8 reserved_48[0x3]; 1044 u8 log_max_tir[0x5]; 1045 u8 reserved_49[0x3]; 1046 u8 log_max_tis[0x5]; 1047 1048 u8 basic_cyclic_rcv_wqe[0x1]; 1049 u8 reserved_50[0x2]; 1050 u8 log_max_rmp[0x5]; 1051 u8 reserved_51[0x3]; 1052 u8 log_max_rqt[0x5]; 1053 u8 reserved_52[0x3]; 1054 u8 log_max_rqt_size[0x5]; 1055 u8 reserved_53[0x3]; 1056 u8 log_max_tis_per_sq[0x5]; 1057 1058 u8 reserved_54[0x3]; 1059 u8 log_max_stride_sz_rq[0x5]; 1060 u8 reserved_55[0x3]; 1061 u8 log_min_stride_sz_rq[0x5]; 1062 u8 reserved_56[0x3]; 1063 u8 log_max_stride_sz_sq[0x5]; 1064 u8 reserved_57[0x3]; 1065 u8 log_min_stride_sz_sq[0x5]; 1066 1067 u8 reserved_58[0x1b]; 1068 u8 log_max_wq_sz[0x5]; 1069 1070 u8 nic_vport_change_event[0x1]; 1071 u8 reserved_59[0xa]; 1072 u8 log_max_vlan_list[0x5]; 1073 u8 reserved_60[0x3]; 1074 u8 log_max_current_mc_list[0x5]; 1075 u8 reserved_61[0x3]; 1076 u8 log_max_current_uc_list[0x5]; 1077 1078 u8 reserved_62[0x80]; 1079 1080 u8 reserved_63[0x3]; 1081 u8 log_max_l2_table[0x5]; 1082 u8 reserved_64[0x8]; 1083 u8 log_uar_page_sz[0x10]; 1084 1085 u8 reserved_65[0x20]; 1086 1087 u8 device_frequency_mhz[0x20]; 1088 1089 u8 device_frequency_khz[0x20]; 1090 1091 u8 reserved_66[0x80]; 1092 1093 u8 log_max_atomic_size_qp[0x8]; 1094 u8 reserved_67[0x10]; 1095 u8 log_max_atomic_size_dc[0x8]; 1096 1097 u8 reserved_68[0x1f]; 1098 u8 cqe_compression[0x1]; 1099 1100 u8 cqe_compression_timeout[0x10]; 1101 u8 cqe_compression_max_num[0x10]; 1102 1103 u8 reserved_69[0x220]; 1104 }; 1105 1106 enum mlx5_flow_destination_type { 1107 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1108 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1109 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1110 }; 1111 1112 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1113 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1114 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1115 u8 reserved_0[0x40]; 1116 }; 1117 1118 struct mlx5_ifc_fte_match_param_bits { 1119 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1120 1121 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1122 1123 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1124 1125 u8 reserved_0[0xa00]; 1126 }; 1127 1128 enum { 1129 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1130 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1131 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1132 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1133 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1134 }; 1135 1136 struct mlx5_ifc_rx_hash_field_select_bits { 1137 u8 l3_prot_type[0x1]; 1138 u8 l4_prot_type[0x1]; 1139 u8 selected_fields[0x1e]; 1140 }; 1141 1142 enum { 1143 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1144 MLX5_WQ_TYPE_CYCLIC = 0x1, 1145 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1146 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1147 }; 1148 1149 enum rq_type { 1150 RQ_TYPE_NONE, 1151 RQ_TYPE_STRIDE, 1152 }; 1153 1154 enum { 1155 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1156 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1157 }; 1158 1159 struct mlx5_ifc_wq_bits { 1160 u8 wq_type[0x4]; 1161 u8 wq_signature[0x1]; 1162 u8 end_padding_mode[0x2]; 1163 u8 cd_slave[0x1]; 1164 u8 reserved_0[0x18]; 1165 1166 u8 hds_skip_first_sge[0x1]; 1167 u8 log2_hds_buf_size[0x3]; 1168 u8 reserved_1[0x7]; 1169 u8 page_offset[0x5]; 1170 u8 lwm[0x10]; 1171 1172 u8 reserved_2[0x8]; 1173 u8 pd[0x18]; 1174 1175 u8 reserved_3[0x8]; 1176 u8 uar_page[0x18]; 1177 1178 u8 dbr_addr[0x40]; 1179 1180 u8 hw_counter[0x20]; 1181 1182 u8 sw_counter[0x20]; 1183 1184 u8 reserved_4[0xc]; 1185 u8 log_wq_stride[0x4]; 1186 u8 reserved_5[0x3]; 1187 u8 log_wq_pg_sz[0x5]; 1188 u8 reserved_6[0x3]; 1189 u8 log_wq_sz[0x5]; 1190 1191 u8 reserved_7[0x15]; 1192 u8 single_wqe_log_num_of_strides[0x3]; 1193 u8 two_byte_shift_en[0x1]; 1194 u8 reserved_8[0x4]; 1195 u8 single_stride_log_num_of_bytes[0x3]; 1196 1197 u8 reserved_9[0x4c0]; 1198 1199 struct mlx5_ifc_cmd_pas_bits pas[0]; 1200 }; 1201 1202 struct mlx5_ifc_rq_num_bits { 1203 u8 reserved_0[0x8]; 1204 u8 rq_num[0x18]; 1205 }; 1206 1207 struct mlx5_ifc_mac_address_layout_bits { 1208 u8 reserved_0[0x10]; 1209 u8 mac_addr_47_32[0x10]; 1210 1211 u8 mac_addr_31_0[0x20]; 1212 }; 1213 1214 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1215 u8 reserved_0[0xa0]; 1216 1217 u8 min_time_between_cnps[0x20]; 1218 1219 u8 reserved_1[0x12]; 1220 u8 cnp_dscp[0x6]; 1221 u8 reserved_2[0x4]; 1222 u8 cnp_prio_mode[0x1]; 1223 u8 cnp_802p_prio[0x3]; 1224 1225 u8 reserved_3[0x720]; 1226 }; 1227 1228 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1229 u8 reserved_0[0x60]; 1230 1231 u8 reserved_1[0x4]; 1232 u8 clamp_tgt_rate[0x1]; 1233 u8 reserved_2[0x3]; 1234 u8 clamp_tgt_rate_after_time_inc[0x1]; 1235 u8 reserved_3[0x17]; 1236 1237 u8 reserved_4[0x20]; 1238 1239 u8 rpg_time_reset[0x20]; 1240 1241 u8 rpg_byte_reset[0x20]; 1242 1243 u8 rpg_threshold[0x20]; 1244 1245 u8 rpg_max_rate[0x20]; 1246 1247 u8 rpg_ai_rate[0x20]; 1248 1249 u8 rpg_hai_rate[0x20]; 1250 1251 u8 rpg_gd[0x20]; 1252 1253 u8 rpg_min_dec_fac[0x20]; 1254 1255 u8 rpg_min_rate[0x20]; 1256 1257 u8 reserved_5[0xe0]; 1258 1259 u8 rate_to_set_on_first_cnp[0x20]; 1260 1261 u8 dce_tcp_g[0x20]; 1262 1263 u8 dce_tcp_rtt[0x20]; 1264 1265 u8 rate_reduce_monitor_period[0x20]; 1266 1267 u8 reserved_6[0x20]; 1268 1269 u8 initial_alpha_value[0x20]; 1270 1271 u8 reserved_7[0x4a0]; 1272 }; 1273 1274 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1275 u8 reserved_0[0x80]; 1276 1277 u8 rppp_max_rps[0x20]; 1278 1279 u8 rpg_time_reset[0x20]; 1280 1281 u8 rpg_byte_reset[0x20]; 1282 1283 u8 rpg_threshold[0x20]; 1284 1285 u8 rpg_max_rate[0x20]; 1286 1287 u8 rpg_ai_rate[0x20]; 1288 1289 u8 rpg_hai_rate[0x20]; 1290 1291 u8 rpg_gd[0x20]; 1292 1293 u8 rpg_min_dec_fac[0x20]; 1294 1295 u8 rpg_min_rate[0x20]; 1296 1297 u8 reserved_1[0x640]; 1298 }; 1299 1300 enum { 1301 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1302 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1303 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1304 }; 1305 1306 struct mlx5_ifc_resize_field_select_bits { 1307 u8 resize_field_select[0x20]; 1308 }; 1309 1310 enum { 1311 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1312 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1313 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1314 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1315 }; 1316 1317 struct mlx5_ifc_modify_field_select_bits { 1318 u8 modify_field_select[0x20]; 1319 }; 1320 1321 struct mlx5_ifc_field_select_r_roce_np_bits { 1322 u8 field_select_r_roce_np[0x20]; 1323 }; 1324 1325 enum { 1326 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1327 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1328 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1329 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1330 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1331 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1332 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1333 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1334 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1335 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1336 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1337 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1338 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1339 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1340 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1341 }; 1342 1343 struct mlx5_ifc_field_select_r_roce_rp_bits { 1344 u8 field_select_r_roce_rp[0x20]; 1345 }; 1346 1347 enum { 1348 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1349 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1350 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1351 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1352 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1353 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1354 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1355 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1356 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1357 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1358 }; 1359 1360 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1361 u8 field_select_8021qaurp[0x20]; 1362 }; 1363 1364 struct mlx5_ifc_pptb_reg_bits { 1365 u8 reserved_0[0x2]; 1366 u8 mm[0x2]; 1367 u8 reserved_1[0x4]; 1368 u8 local_port[0x8]; 1369 u8 reserved_2[0x6]; 1370 u8 cm[0x1]; 1371 u8 um[0x1]; 1372 u8 pm[0x8]; 1373 1374 u8 prio7buff[0x4]; 1375 u8 prio6buff[0x4]; 1376 u8 prio5buff[0x4]; 1377 u8 prio4buff[0x4]; 1378 u8 prio3buff[0x4]; 1379 u8 prio2buff[0x4]; 1380 u8 prio1buff[0x4]; 1381 u8 prio0buff[0x4]; 1382 1383 u8 pm_msb[0x8]; 1384 u8 reserved_3[0x10]; 1385 u8 ctrl_buff[0x4]; 1386 u8 untagged_buff[0x4]; 1387 }; 1388 1389 struct mlx5_ifc_dcbx_app_reg_bits { 1390 u8 reserved_0[0x8]; 1391 u8 port_number[0x8]; 1392 u8 reserved_1[0x10]; 1393 1394 u8 reserved_2[0x1a]; 1395 u8 num_app_prio[0x6]; 1396 1397 u8 reserved_3[0x40]; 1398 1399 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1400 }; 1401 1402 struct mlx5_ifc_dcbx_param_reg_bits { 1403 u8 dcbx_cee_cap[0x1]; 1404 u8 dcbx_ieee_cap[0x1]; 1405 u8 dcbx_standby_cap[0x1]; 1406 u8 reserved_0[0x5]; 1407 u8 port_number[0x8]; 1408 u8 reserved_1[0xa]; 1409 u8 max_application_table_size[0x6]; 1410 1411 u8 reserved_2[0x15]; 1412 u8 version_oper[0x3]; 1413 u8 reserved_3[0x5]; 1414 u8 version_admin[0x3]; 1415 1416 u8 willing_admin[0x1]; 1417 u8 reserved_4[0x3]; 1418 u8 pfc_cap_oper[0x4]; 1419 u8 reserved_5[0x4]; 1420 u8 pfc_cap_admin[0x4]; 1421 u8 reserved_6[0x4]; 1422 u8 num_of_tc_oper[0x4]; 1423 u8 reserved_7[0x4]; 1424 u8 num_of_tc_admin[0x4]; 1425 1426 u8 remote_willing[0x1]; 1427 u8 reserved_8[0x3]; 1428 u8 remote_pfc_cap[0x4]; 1429 u8 reserved_9[0x14]; 1430 u8 remote_num_of_tc[0x4]; 1431 1432 u8 reserved_10[0x18]; 1433 u8 error[0x8]; 1434 1435 u8 reserved_11[0x160]; 1436 }; 1437 1438 struct mlx5_ifc_qhll_bits { 1439 u8 reserved_at_0[0x8]; 1440 u8 local_port[0x8]; 1441 u8 reserved_at_10[0x10]; 1442 1443 u8 reserved_at_20[0x1b]; 1444 u8 hll_time[0x5]; 1445 1446 u8 stall_en[0x1]; 1447 u8 reserved_at_41[0x1c]; 1448 u8 stall_cnt[0x3]; 1449 }; 1450 1451 struct mlx5_ifc_qetcr_reg_bits { 1452 u8 operation_type[0x2]; 1453 u8 cap_local_admin[0x1]; 1454 u8 cap_remote_admin[0x1]; 1455 u8 reserved_0[0x4]; 1456 u8 port_number[0x8]; 1457 u8 reserved_1[0x10]; 1458 1459 u8 reserved_2[0x20]; 1460 1461 u8 tc[8][0x40]; 1462 1463 u8 global_configuration[0x40]; 1464 }; 1465 1466 struct mlx5_ifc_nodnic_ring_config_reg_bits { 1467 u8 queue_address_63_32[0x20]; 1468 1469 u8 queue_address_31_12[0x14]; 1470 u8 reserved_0[0x6]; 1471 u8 log_size[0x6]; 1472 1473 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1474 1475 u8 reserved_1[0x8]; 1476 u8 queue_number[0x18]; 1477 1478 u8 q_key[0x20]; 1479 1480 u8 reserved_2[0x10]; 1481 u8 pkey_index[0x10]; 1482 1483 u8 reserved_3[0x40]; 1484 }; 1485 1486 struct mlx5_ifc_nodnic_cq_arming_word_bits { 1487 u8 reserved_0[0x8]; 1488 u8 cq_ci[0x10]; 1489 u8 reserved_1[0x8]; 1490 }; 1491 1492 enum { 1493 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1494 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1495 }; 1496 1497 enum { 1498 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1499 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1500 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1501 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1502 }; 1503 1504 struct mlx5_ifc_nodnic_event_word_bits { 1505 u8 driver_reset_needed[0x1]; 1506 u8 port_management_change_event[0x1]; 1507 u8 reserved_0[0x19]; 1508 u8 link_type[0x1]; 1509 u8 port_state[0x4]; 1510 }; 1511 1512 struct mlx5_ifc_nic_vport_change_event_bits { 1513 u8 reserved_0[0x10]; 1514 u8 vport_num[0x10]; 1515 1516 u8 reserved_1[0xc0]; 1517 }; 1518 1519 struct mlx5_ifc_pages_req_event_bits { 1520 u8 reserved_0[0x10]; 1521 u8 function_id[0x10]; 1522 1523 u8 num_pages[0x20]; 1524 1525 u8 reserved_1[0xa0]; 1526 }; 1527 1528 struct mlx5_ifc_cmd_inter_comp_event_bits { 1529 u8 command_completion_vector[0x20]; 1530 1531 u8 reserved_0[0xc0]; 1532 }; 1533 1534 struct mlx5_ifc_stall_vl_event_bits { 1535 u8 reserved_0[0x18]; 1536 u8 port_num[0x1]; 1537 u8 reserved_1[0x3]; 1538 u8 vl[0x4]; 1539 1540 u8 reserved_2[0xa0]; 1541 }; 1542 1543 struct mlx5_ifc_db_bf_congestion_event_bits { 1544 u8 event_subtype[0x8]; 1545 u8 reserved_0[0x8]; 1546 u8 congestion_level[0x8]; 1547 u8 reserved_1[0x8]; 1548 1549 u8 reserved_2[0xa0]; 1550 }; 1551 1552 struct mlx5_ifc_gpio_event_bits { 1553 u8 reserved_0[0x60]; 1554 1555 u8 gpio_event_hi[0x20]; 1556 1557 u8 gpio_event_lo[0x20]; 1558 1559 u8 reserved_1[0x40]; 1560 }; 1561 1562 struct mlx5_ifc_port_state_change_event_bits { 1563 u8 reserved_0[0x40]; 1564 1565 u8 port_num[0x4]; 1566 u8 reserved_1[0x1c]; 1567 1568 u8 reserved_2[0x80]; 1569 }; 1570 1571 struct mlx5_ifc_dropped_packet_logged_bits { 1572 u8 reserved_0[0xe0]; 1573 }; 1574 1575 enum { 1576 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1577 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1578 }; 1579 1580 struct mlx5_ifc_cq_error_bits { 1581 u8 reserved_0[0x8]; 1582 u8 cqn[0x18]; 1583 1584 u8 reserved_1[0x20]; 1585 1586 u8 reserved_2[0x18]; 1587 u8 syndrome[0x8]; 1588 1589 u8 reserved_3[0x80]; 1590 }; 1591 1592 struct mlx5_ifc_rdma_page_fault_event_bits { 1593 u8 bytes_commited[0x20]; 1594 1595 u8 r_key[0x20]; 1596 1597 u8 reserved_0[0x10]; 1598 u8 packet_len[0x10]; 1599 1600 u8 rdma_op_len[0x20]; 1601 1602 u8 rdma_va[0x40]; 1603 1604 u8 reserved_1[0x5]; 1605 u8 rdma[0x1]; 1606 u8 write[0x1]; 1607 u8 requestor[0x1]; 1608 u8 qp_number[0x18]; 1609 }; 1610 1611 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1612 u8 bytes_committed[0x20]; 1613 1614 u8 reserved_0[0x10]; 1615 u8 wqe_index[0x10]; 1616 1617 u8 reserved_1[0x10]; 1618 u8 len[0x10]; 1619 1620 u8 reserved_2[0x60]; 1621 1622 u8 reserved_3[0x5]; 1623 u8 rdma[0x1]; 1624 u8 write_read[0x1]; 1625 u8 requestor[0x1]; 1626 u8 qpn[0x18]; 1627 }; 1628 1629 enum { 1630 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1631 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1632 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1633 }; 1634 1635 struct mlx5_ifc_qp_events_bits { 1636 u8 reserved_0[0xa0]; 1637 1638 u8 type[0x8]; 1639 u8 reserved_1[0x18]; 1640 1641 u8 reserved_2[0x8]; 1642 u8 qpn_rqn_sqn[0x18]; 1643 }; 1644 1645 struct mlx5_ifc_dct_events_bits { 1646 u8 reserved_0[0xc0]; 1647 1648 u8 reserved_1[0x8]; 1649 u8 dct_number[0x18]; 1650 }; 1651 1652 struct mlx5_ifc_comp_event_bits { 1653 u8 reserved_0[0xc0]; 1654 1655 u8 reserved_1[0x8]; 1656 u8 cq_number[0x18]; 1657 }; 1658 1659 struct mlx5_ifc_fw_version_bits { 1660 u8 major[0x10]; 1661 u8 reserved_0[0x10]; 1662 1663 u8 minor[0x10]; 1664 u8 subminor[0x10]; 1665 1666 u8 second[0x8]; 1667 u8 minute[0x8]; 1668 u8 hour[0x8]; 1669 u8 reserved_1[0x8]; 1670 1671 u8 year[0x10]; 1672 u8 month[0x8]; 1673 u8 day[0x8]; 1674 }; 1675 1676 enum { 1677 MLX5_QPC_STATE_RST = 0x0, 1678 MLX5_QPC_STATE_INIT = 0x1, 1679 MLX5_QPC_STATE_RTR = 0x2, 1680 MLX5_QPC_STATE_RTS = 0x3, 1681 MLX5_QPC_STATE_SQER = 0x4, 1682 MLX5_QPC_STATE_SQD = 0x5, 1683 MLX5_QPC_STATE_ERR = 0x6, 1684 MLX5_QPC_STATE_SUSPENDED = 0x9, 1685 }; 1686 1687 enum { 1688 MLX5_QPC_ST_RC = 0x0, 1689 MLX5_QPC_ST_UC = 0x1, 1690 MLX5_QPC_ST_UD = 0x2, 1691 MLX5_QPC_ST_XRC = 0x3, 1692 MLX5_QPC_ST_DCI = 0x5, 1693 MLX5_QPC_ST_QP0 = 0x7, 1694 MLX5_QPC_ST_QP1 = 0x8, 1695 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1696 MLX5_QPC_ST_REG_UMR = 0xc, 1697 }; 1698 1699 enum { 1700 MLX5_QP_PM_ARMED = 0x0, 1701 MLX5_QP_PM_REARM = 0x1, 1702 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1703 MLX5_QP_PM_MIGRATED = 0x3, 1704 }; 1705 1706 enum { 1707 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1708 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1709 }; 1710 1711 enum { 1712 MLX5_QPC_MTU_256_BYTES = 0x1, 1713 MLX5_QPC_MTU_512_BYTES = 0x2, 1714 MLX5_QPC_MTU_1K_BYTES = 0x3, 1715 MLX5_QPC_MTU_2K_BYTES = 0x4, 1716 MLX5_QPC_MTU_4K_BYTES = 0x5, 1717 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1718 }; 1719 1720 enum { 1721 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1722 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1723 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1724 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1725 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1726 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1727 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1728 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1729 }; 1730 1731 enum { 1732 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1733 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1734 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1735 }; 1736 1737 enum { 1738 MLX5_QPC_CS_RES_DISABLE = 0x0, 1739 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1740 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1741 }; 1742 1743 struct mlx5_ifc_qpc_bits { 1744 u8 state[0x4]; 1745 u8 reserved_0[0x4]; 1746 u8 st[0x8]; 1747 u8 reserved_1[0x3]; 1748 u8 pm_state[0x2]; 1749 u8 reserved_2[0x7]; 1750 u8 end_padding_mode[0x2]; 1751 u8 reserved_3[0x2]; 1752 1753 u8 wq_signature[0x1]; 1754 u8 block_lb_mc[0x1]; 1755 u8 atomic_like_write_en[0x1]; 1756 u8 latency_sensitive[0x1]; 1757 u8 reserved_4[0x1]; 1758 u8 drain_sigerr[0x1]; 1759 u8 reserved_5[0x2]; 1760 u8 pd[0x18]; 1761 1762 u8 mtu[0x3]; 1763 u8 log_msg_max[0x5]; 1764 u8 reserved_6[0x1]; 1765 u8 log_rq_size[0x4]; 1766 u8 log_rq_stride[0x3]; 1767 u8 no_sq[0x1]; 1768 u8 log_sq_size[0x4]; 1769 u8 reserved_7[0x6]; 1770 u8 rlky[0x1]; 1771 u8 ulp_stateless_offload_mode[0x4]; 1772 1773 u8 counter_set_id[0x8]; 1774 u8 uar_page[0x18]; 1775 1776 u8 reserved_8[0x8]; 1777 u8 user_index[0x18]; 1778 1779 u8 reserved_9[0x3]; 1780 u8 log_page_size[0x5]; 1781 u8 remote_qpn[0x18]; 1782 1783 struct mlx5_ifc_ads_bits primary_address_path; 1784 1785 struct mlx5_ifc_ads_bits secondary_address_path; 1786 1787 u8 log_ack_req_freq[0x4]; 1788 u8 reserved_10[0x4]; 1789 u8 log_sra_max[0x3]; 1790 u8 reserved_11[0x2]; 1791 u8 retry_count[0x3]; 1792 u8 rnr_retry[0x3]; 1793 u8 reserved_12[0x1]; 1794 u8 fre[0x1]; 1795 u8 cur_rnr_retry[0x3]; 1796 u8 cur_retry_count[0x3]; 1797 u8 reserved_13[0x5]; 1798 1799 u8 reserved_14[0x20]; 1800 1801 u8 reserved_15[0x8]; 1802 u8 next_send_psn[0x18]; 1803 1804 u8 reserved_16[0x8]; 1805 u8 cqn_snd[0x18]; 1806 1807 u8 reserved_17[0x40]; 1808 1809 u8 reserved_18[0x8]; 1810 u8 last_acked_psn[0x18]; 1811 1812 u8 reserved_19[0x8]; 1813 u8 ssn[0x18]; 1814 1815 u8 reserved_20[0x8]; 1816 u8 log_rra_max[0x3]; 1817 u8 reserved_21[0x1]; 1818 u8 atomic_mode[0x4]; 1819 u8 rre[0x1]; 1820 u8 rwe[0x1]; 1821 u8 rae[0x1]; 1822 u8 reserved_22[0x1]; 1823 u8 page_offset[0x6]; 1824 u8 reserved_23[0x3]; 1825 u8 cd_slave_receive[0x1]; 1826 u8 cd_slave_send[0x1]; 1827 u8 cd_master[0x1]; 1828 1829 u8 reserved_24[0x3]; 1830 u8 min_rnr_nak[0x5]; 1831 u8 next_rcv_psn[0x18]; 1832 1833 u8 reserved_25[0x8]; 1834 u8 xrcd[0x18]; 1835 1836 u8 reserved_26[0x8]; 1837 u8 cqn_rcv[0x18]; 1838 1839 u8 dbr_addr[0x40]; 1840 1841 u8 q_key[0x20]; 1842 1843 u8 reserved_27[0x5]; 1844 u8 rq_type[0x3]; 1845 u8 srqn_rmpn[0x18]; 1846 1847 u8 reserved_28[0x8]; 1848 u8 rmsn[0x18]; 1849 1850 u8 hw_sq_wqebb_counter[0x10]; 1851 u8 sw_sq_wqebb_counter[0x10]; 1852 1853 u8 hw_rq_counter[0x20]; 1854 1855 u8 sw_rq_counter[0x20]; 1856 1857 u8 reserved_29[0x20]; 1858 1859 u8 reserved_30[0xf]; 1860 u8 cgs[0x1]; 1861 u8 cs_req[0x8]; 1862 u8 cs_res[0x8]; 1863 1864 u8 dc_access_key[0x40]; 1865 1866 u8 rdma_active[0x1]; 1867 u8 comm_est[0x1]; 1868 u8 suspended[0x1]; 1869 u8 reserved_31[0x5]; 1870 u8 send_msg_psn[0x18]; 1871 1872 u8 reserved_32[0x8]; 1873 u8 rcv_msg_psn[0x18]; 1874 1875 u8 rdma_va[0x40]; 1876 1877 u8 rdma_key[0x20]; 1878 1879 u8 reserved_33[0x20]; 1880 }; 1881 1882 struct mlx5_ifc_roce_addr_layout_bits { 1883 u8 source_l3_address[16][0x8]; 1884 1885 u8 reserved_0[0x3]; 1886 u8 vlan_valid[0x1]; 1887 u8 vlan_id[0xc]; 1888 u8 source_mac_47_32[0x10]; 1889 1890 u8 source_mac_31_0[0x20]; 1891 1892 u8 reserved_1[0x14]; 1893 u8 roce_l3_type[0x4]; 1894 u8 roce_version[0x8]; 1895 1896 u8 reserved_2[0x20]; 1897 }; 1898 1899 struct mlx5_ifc_rdbc_bits { 1900 u8 reserved_0[0x1c]; 1901 u8 type[0x4]; 1902 1903 u8 reserved_1[0x20]; 1904 1905 u8 reserved_2[0x8]; 1906 u8 psn[0x18]; 1907 1908 u8 rkey[0x20]; 1909 1910 u8 address[0x40]; 1911 1912 u8 byte_count[0x20]; 1913 1914 u8 reserved_3[0x20]; 1915 1916 u8 atomic_resp[32][0x8]; 1917 }; 1918 1919 enum { 1920 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 1921 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 1922 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 1923 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 1924 }; 1925 1926 struct mlx5_ifc_flow_context_bits { 1927 u8 reserved_0[0x20]; 1928 1929 u8 group_id[0x20]; 1930 1931 u8 reserved_1[0x8]; 1932 u8 flow_tag[0x18]; 1933 1934 u8 reserved_2[0x10]; 1935 u8 action[0x10]; 1936 1937 u8 reserved_3[0x8]; 1938 u8 destination_list_size[0x18]; 1939 1940 u8 reserved_4[0x8]; 1941 u8 flow_counter_list_size[0x18]; 1942 1943 u8 reserved_5[0x140]; 1944 1945 struct mlx5_ifc_fte_match_param_bits match_value; 1946 1947 u8 reserved_6[0x600]; 1948 1949 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 1950 }; 1951 1952 enum { 1953 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 1954 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 1955 }; 1956 1957 struct mlx5_ifc_xrc_srqc_bits { 1958 u8 state[0x4]; 1959 u8 log_xrc_srq_size[0x4]; 1960 u8 reserved_0[0x18]; 1961 1962 u8 wq_signature[0x1]; 1963 u8 cont_srq[0x1]; 1964 u8 reserved_1[0x1]; 1965 u8 rlky[0x1]; 1966 u8 basic_cyclic_rcv_wqe[0x1]; 1967 u8 log_rq_stride[0x3]; 1968 u8 xrcd[0x18]; 1969 1970 u8 page_offset[0x6]; 1971 u8 reserved_2[0x2]; 1972 u8 cqn[0x18]; 1973 1974 u8 reserved_3[0x20]; 1975 1976 u8 reserved_4[0x2]; 1977 u8 log_page_size[0x6]; 1978 u8 user_index[0x18]; 1979 1980 u8 reserved_5[0x20]; 1981 1982 u8 reserved_6[0x8]; 1983 u8 pd[0x18]; 1984 1985 u8 lwm[0x10]; 1986 u8 wqe_cnt[0x10]; 1987 1988 u8 reserved_7[0x40]; 1989 1990 u8 db_record_addr_h[0x20]; 1991 1992 u8 db_record_addr_l[0x1e]; 1993 u8 reserved_8[0x2]; 1994 1995 u8 reserved_9[0x80]; 1996 }; 1997 1998 struct mlx5_ifc_traffic_counter_bits { 1999 u8 packets[0x40]; 2000 2001 u8 octets[0x40]; 2002 }; 2003 2004 struct mlx5_ifc_tisc_bits { 2005 u8 reserved_0[0xc]; 2006 u8 prio[0x4]; 2007 u8 reserved_1[0x10]; 2008 2009 u8 reserved_2[0x100]; 2010 2011 u8 reserved_3[0x8]; 2012 u8 transport_domain[0x18]; 2013 2014 u8 reserved_4[0x8]; 2015 u8 underlay_qpn[0x18]; 2016 2017 u8 reserved_5[0x3a0]; 2018 }; 2019 2020 enum { 2021 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2022 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2023 }; 2024 2025 enum { 2026 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2027 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2028 }; 2029 2030 enum { 2031 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2032 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2033 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2034 }; 2035 2036 enum { 2037 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2038 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2039 }; 2040 2041 struct mlx5_ifc_tirc_bits { 2042 u8 reserved_0[0x20]; 2043 2044 u8 disp_type[0x4]; 2045 u8 reserved_1[0x1c]; 2046 2047 u8 reserved_2[0x40]; 2048 2049 u8 reserved_3[0x4]; 2050 u8 lro_timeout_period_usecs[0x10]; 2051 u8 lro_enable_mask[0x4]; 2052 u8 lro_max_msg_sz[0x8]; 2053 2054 u8 reserved_4[0x40]; 2055 2056 u8 reserved_5[0x8]; 2057 u8 inline_rqn[0x18]; 2058 2059 u8 rx_hash_symmetric[0x1]; 2060 u8 reserved_6[0x1]; 2061 u8 tunneled_offload_en[0x1]; 2062 u8 reserved_7[0x5]; 2063 u8 indirect_table[0x18]; 2064 2065 u8 rx_hash_fn[0x4]; 2066 u8 reserved_8[0x2]; 2067 u8 self_lb_en[0x2]; 2068 u8 transport_domain[0x18]; 2069 2070 u8 rx_hash_toeplitz_key[10][0x20]; 2071 2072 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2073 2074 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2075 2076 u8 reserved_9[0x4c0]; 2077 }; 2078 2079 enum { 2080 MLX5_SRQC_STATE_GOOD = 0x0, 2081 MLX5_SRQC_STATE_ERROR = 0x1, 2082 }; 2083 2084 struct mlx5_ifc_srqc_bits { 2085 u8 state[0x4]; 2086 u8 log_srq_size[0x4]; 2087 u8 reserved_0[0x18]; 2088 2089 u8 wq_signature[0x1]; 2090 u8 cont_srq[0x1]; 2091 u8 reserved_1[0x1]; 2092 u8 rlky[0x1]; 2093 u8 reserved_2[0x1]; 2094 u8 log_rq_stride[0x3]; 2095 u8 xrcd[0x18]; 2096 2097 u8 page_offset[0x6]; 2098 u8 reserved_3[0x2]; 2099 u8 cqn[0x18]; 2100 2101 u8 reserved_4[0x20]; 2102 2103 u8 reserved_5[0x2]; 2104 u8 log_page_size[0x6]; 2105 u8 reserved_6[0x18]; 2106 2107 u8 reserved_7[0x20]; 2108 2109 u8 reserved_8[0x8]; 2110 u8 pd[0x18]; 2111 2112 u8 lwm[0x10]; 2113 u8 wqe_cnt[0x10]; 2114 2115 u8 reserved_9[0x40]; 2116 2117 u8 db_record_addr_h[0x20]; 2118 2119 u8 db_record_addr_l[0x1e]; 2120 u8 reserved_10[0x2]; 2121 2122 u8 reserved_11[0x80]; 2123 }; 2124 2125 enum { 2126 MLX5_SQC_STATE_RST = 0x0, 2127 MLX5_SQC_STATE_RDY = 0x1, 2128 MLX5_SQC_STATE_ERR = 0x3, 2129 }; 2130 2131 struct mlx5_ifc_sqc_bits { 2132 u8 rlkey[0x1]; 2133 u8 cd_master[0x1]; 2134 u8 fre[0x1]; 2135 u8 flush_in_error_en[0x1]; 2136 u8 allow_multi_pkt_send_wqe[0x1]; 2137 u8 min_wqe_inline_mode[0x3]; 2138 u8 state[0x4]; 2139 u8 reg_umr[0x1]; 2140 u8 allow_swp[0x1]; 2141 u8 reserved_0[0x12]; 2142 2143 u8 reserved_1[0x8]; 2144 u8 user_index[0x18]; 2145 2146 u8 reserved_2[0x8]; 2147 u8 cqn[0x18]; 2148 2149 u8 reserved_3[0x80]; 2150 2151 u8 qos_para_vport_number[0x10]; 2152 u8 packet_pacing_rate_limit_index[0x10]; 2153 2154 u8 tis_lst_sz[0x10]; 2155 u8 reserved_4[0x10]; 2156 2157 u8 reserved_5[0x40]; 2158 2159 u8 reserved_6[0x8]; 2160 u8 tis_num_0[0x18]; 2161 2162 struct mlx5_ifc_wq_bits wq; 2163 }; 2164 2165 enum { 2166 MLX5_TSAR_TYPE_DWRR = 0, 2167 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2168 MLX5_TSAR_TYPE_ETS = 2 2169 }; 2170 2171 struct mlx5_ifc_tsar_element_attributes_bits { 2172 u8 reserved_0[0x8]; 2173 u8 tsar_type[0x8]; 2174 u8 reserved_1[0x10]; 2175 }; 2176 2177 struct mlx5_ifc_vport_element_attributes_bits { 2178 u8 reserved_0[0x10]; 2179 u8 vport_number[0x10]; 2180 }; 2181 2182 struct mlx5_ifc_vport_tc_element_attributes_bits { 2183 u8 traffic_class[0x10]; 2184 u8 vport_number[0x10]; 2185 }; 2186 2187 struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2188 u8 reserved_0[0x0C]; 2189 u8 traffic_class[0x04]; 2190 u8 qos_para_vport_number[0x10]; 2191 }; 2192 2193 enum { 2194 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2195 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2196 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2197 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2198 }; 2199 2200 struct mlx5_ifc_scheduling_context_bits { 2201 u8 element_type[0x8]; 2202 u8 reserved_at_8[0x18]; 2203 2204 u8 element_attributes[0x20]; 2205 2206 u8 parent_element_id[0x20]; 2207 2208 u8 reserved_at_60[0x40]; 2209 2210 u8 bw_share[0x20]; 2211 2212 u8 max_average_bw[0x20]; 2213 2214 u8 reserved_at_e0[0x120]; 2215 }; 2216 2217 struct mlx5_ifc_rqtc_bits { 2218 u8 reserved_0[0xa0]; 2219 2220 u8 reserved_1[0x10]; 2221 u8 rqt_max_size[0x10]; 2222 2223 u8 reserved_2[0x10]; 2224 u8 rqt_actual_size[0x10]; 2225 2226 u8 reserved_3[0x6a0]; 2227 2228 struct mlx5_ifc_rq_num_bits rq_num[0]; 2229 }; 2230 2231 enum { 2232 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2233 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2234 }; 2235 2236 enum { 2237 MLX5_RQC_STATE_RST = 0x0, 2238 MLX5_RQC_STATE_RDY = 0x1, 2239 MLX5_RQC_STATE_ERR = 0x3, 2240 }; 2241 2242 struct mlx5_ifc_rqc_bits { 2243 u8 rlky[0x1]; 2244 u8 reserved_0[0x2]; 2245 u8 vlan_strip_disable[0x1]; 2246 u8 mem_rq_type[0x4]; 2247 u8 state[0x4]; 2248 u8 reserved_1[0x1]; 2249 u8 flush_in_error_en[0x1]; 2250 u8 reserved_2[0x12]; 2251 2252 u8 reserved_3[0x8]; 2253 u8 user_index[0x18]; 2254 2255 u8 reserved_4[0x8]; 2256 u8 cqn[0x18]; 2257 2258 u8 counter_set_id[0x8]; 2259 u8 reserved_5[0x18]; 2260 2261 u8 reserved_6[0x8]; 2262 u8 rmpn[0x18]; 2263 2264 u8 reserved_7[0xe0]; 2265 2266 struct mlx5_ifc_wq_bits wq; 2267 }; 2268 2269 enum { 2270 MLX5_RMPC_STATE_RDY = 0x1, 2271 MLX5_RMPC_STATE_ERR = 0x3, 2272 }; 2273 2274 struct mlx5_ifc_rmpc_bits { 2275 u8 reserved_0[0x8]; 2276 u8 state[0x4]; 2277 u8 reserved_1[0x14]; 2278 2279 u8 basic_cyclic_rcv_wqe[0x1]; 2280 u8 reserved_2[0x1f]; 2281 2282 u8 reserved_3[0x140]; 2283 2284 struct mlx5_ifc_wq_bits wq; 2285 }; 2286 2287 enum { 2288 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2289 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2290 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2291 }; 2292 2293 struct mlx5_ifc_nic_vport_context_bits { 2294 u8 reserved_0[0x5]; 2295 u8 min_wqe_inline_mode[0x3]; 2296 u8 reserved_1[0x17]; 2297 u8 roce_en[0x1]; 2298 2299 u8 arm_change_event[0x1]; 2300 u8 reserved_2[0x1a]; 2301 u8 event_on_mtu[0x1]; 2302 u8 event_on_promisc_change[0x1]; 2303 u8 event_on_vlan_change[0x1]; 2304 u8 event_on_mc_address_change[0x1]; 2305 u8 event_on_uc_address_change[0x1]; 2306 2307 u8 reserved_3[0xe0]; 2308 2309 u8 reserved_4[0x10]; 2310 u8 mtu[0x10]; 2311 2312 u8 system_image_guid[0x40]; 2313 2314 u8 port_guid[0x40]; 2315 2316 u8 node_guid[0x40]; 2317 2318 u8 reserved_5[0x140]; 2319 2320 u8 qkey_violation_counter[0x10]; 2321 u8 reserved_6[0x10]; 2322 2323 u8 reserved_7[0x420]; 2324 2325 u8 promisc_uc[0x1]; 2326 u8 promisc_mc[0x1]; 2327 u8 promisc_all[0x1]; 2328 u8 reserved_8[0x2]; 2329 u8 allowed_list_type[0x3]; 2330 u8 reserved_9[0xc]; 2331 u8 allowed_list_size[0xc]; 2332 2333 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2334 2335 u8 reserved_10[0x20]; 2336 2337 u8 current_uc_mac_address[0][0x40]; 2338 }; 2339 2340 enum { 2341 MLX5_ACCESS_MODE_PA = 0x0, 2342 MLX5_ACCESS_MODE_MTT = 0x1, 2343 MLX5_ACCESS_MODE_KLM = 0x2, 2344 }; 2345 2346 struct mlx5_ifc_mkc_bits { 2347 u8 reserved_0[0x1]; 2348 u8 free[0x1]; 2349 u8 reserved_1[0xd]; 2350 u8 small_fence_on_rdma_read_response[0x1]; 2351 u8 umr_en[0x1]; 2352 u8 a[0x1]; 2353 u8 rw[0x1]; 2354 u8 rr[0x1]; 2355 u8 lw[0x1]; 2356 u8 lr[0x1]; 2357 u8 access_mode[0x2]; 2358 u8 reserved_2[0x8]; 2359 2360 u8 qpn[0x18]; 2361 u8 mkey_7_0[0x8]; 2362 2363 u8 reserved_3[0x20]; 2364 2365 u8 length64[0x1]; 2366 u8 bsf_en[0x1]; 2367 u8 sync_umr[0x1]; 2368 u8 reserved_4[0x2]; 2369 u8 expected_sigerr_count[0x1]; 2370 u8 reserved_5[0x1]; 2371 u8 en_rinval[0x1]; 2372 u8 pd[0x18]; 2373 2374 u8 start_addr[0x40]; 2375 2376 u8 len[0x40]; 2377 2378 u8 bsf_octword_size[0x20]; 2379 2380 u8 reserved_6[0x80]; 2381 2382 u8 translations_octword_size[0x20]; 2383 2384 u8 reserved_7[0x1b]; 2385 u8 log_page_size[0x5]; 2386 2387 u8 reserved_8[0x20]; 2388 }; 2389 2390 struct mlx5_ifc_pkey_bits { 2391 u8 reserved_0[0x10]; 2392 u8 pkey[0x10]; 2393 }; 2394 2395 struct mlx5_ifc_array128_auto_bits { 2396 u8 array128_auto[16][0x8]; 2397 }; 2398 2399 enum { 2400 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2401 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2402 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2403 }; 2404 2405 enum { 2406 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2407 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2408 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2409 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2410 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2411 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2412 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2413 }; 2414 2415 enum { 2416 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2417 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2418 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2419 }; 2420 2421 enum { 2422 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2423 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2424 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2425 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2426 }; 2427 2428 enum { 2429 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2430 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2431 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2432 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2433 }; 2434 2435 struct mlx5_ifc_hca_vport_context_bits { 2436 u8 field_select[0x20]; 2437 2438 u8 reserved_0[0xe0]; 2439 2440 u8 sm_virt_aware[0x1]; 2441 u8 has_smi[0x1]; 2442 u8 has_raw[0x1]; 2443 u8 grh_required[0x1]; 2444 u8 reserved_1[0x1]; 2445 u8 min_wqe_inline_mode[0x3]; 2446 u8 reserved_2[0x8]; 2447 u8 port_physical_state[0x4]; 2448 u8 vport_state_policy[0x4]; 2449 u8 port_state[0x4]; 2450 u8 vport_state[0x4]; 2451 2452 u8 reserved_3[0x20]; 2453 2454 u8 system_image_guid[0x40]; 2455 2456 u8 port_guid[0x40]; 2457 2458 u8 node_guid[0x40]; 2459 2460 u8 cap_mask1[0x20]; 2461 2462 u8 cap_mask1_field_select[0x20]; 2463 2464 u8 cap_mask2[0x20]; 2465 2466 u8 cap_mask2_field_select[0x20]; 2467 2468 u8 reserved_4[0x80]; 2469 2470 u8 lid[0x10]; 2471 u8 reserved_5[0x4]; 2472 u8 init_type_reply[0x4]; 2473 u8 lmc[0x3]; 2474 u8 subnet_timeout[0x5]; 2475 2476 u8 sm_lid[0x10]; 2477 u8 sm_sl[0x4]; 2478 u8 reserved_6[0xc]; 2479 2480 u8 qkey_violation_counter[0x10]; 2481 u8 pkey_violation_counter[0x10]; 2482 2483 u8 reserved_7[0xca0]; 2484 }; 2485 2486 union mlx5_ifc_hca_cap_union_bits { 2487 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2488 struct mlx5_ifc_odp_cap_bits odp_cap; 2489 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2490 struct mlx5_ifc_roce_cap_bits roce_cap; 2491 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2492 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2493 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2494 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2495 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2496 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2497 struct mlx5_ifc_qos_cap_bits qos_cap; 2498 u8 reserved_0[0x8000]; 2499 }; 2500 2501 struct mlx5_ifc_esw_vport_context_bits { 2502 u8 reserved_0[0x3]; 2503 u8 vport_svlan_strip[0x1]; 2504 u8 vport_cvlan_strip[0x1]; 2505 u8 vport_svlan_insert[0x1]; 2506 u8 vport_cvlan_insert[0x2]; 2507 u8 reserved_1[0x18]; 2508 2509 u8 reserved_2[0x20]; 2510 2511 u8 svlan_cfi[0x1]; 2512 u8 svlan_pcp[0x3]; 2513 u8 svlan_id[0xc]; 2514 u8 cvlan_cfi[0x1]; 2515 u8 cvlan_pcp[0x3]; 2516 u8 cvlan_id[0xc]; 2517 2518 u8 reserved_3[0x7a0]; 2519 }; 2520 2521 enum { 2522 MLX5_EQC_STATUS_OK = 0x0, 2523 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2524 }; 2525 2526 enum { 2527 MLX5_EQ_STATE_ARMED = 0x9, 2528 MLX5_EQ_STATE_FIRED = 0xa, 2529 }; 2530 2531 struct mlx5_ifc_eqc_bits { 2532 u8 status[0x4]; 2533 u8 reserved_0[0x9]; 2534 u8 ec[0x1]; 2535 u8 oi[0x1]; 2536 u8 reserved_1[0x5]; 2537 u8 st[0x4]; 2538 u8 reserved_2[0x8]; 2539 2540 u8 reserved_3[0x20]; 2541 2542 u8 reserved_4[0x14]; 2543 u8 page_offset[0x6]; 2544 u8 reserved_5[0x6]; 2545 2546 u8 reserved_6[0x3]; 2547 u8 log_eq_size[0x5]; 2548 u8 uar_page[0x18]; 2549 2550 u8 reserved_7[0x20]; 2551 2552 u8 reserved_8[0x18]; 2553 u8 intr[0x8]; 2554 2555 u8 reserved_9[0x3]; 2556 u8 log_page_size[0x5]; 2557 u8 reserved_10[0x18]; 2558 2559 u8 reserved_11[0x60]; 2560 2561 u8 reserved_12[0x8]; 2562 u8 consumer_counter[0x18]; 2563 2564 u8 reserved_13[0x8]; 2565 u8 producer_counter[0x18]; 2566 2567 u8 reserved_14[0x80]; 2568 }; 2569 2570 enum { 2571 MLX5_DCTC_STATE_ACTIVE = 0x0, 2572 MLX5_DCTC_STATE_DRAINING = 0x1, 2573 MLX5_DCTC_STATE_DRAINED = 0x2, 2574 }; 2575 2576 enum { 2577 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2578 MLX5_DCTC_CS_RES_NA = 0x1, 2579 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2580 }; 2581 2582 enum { 2583 MLX5_DCTC_MTU_256_BYTES = 0x1, 2584 MLX5_DCTC_MTU_512_BYTES = 0x2, 2585 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2586 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2587 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2588 }; 2589 2590 struct mlx5_ifc_dctc_bits { 2591 u8 reserved_0[0x4]; 2592 u8 state[0x4]; 2593 u8 reserved_1[0x18]; 2594 2595 u8 reserved_2[0x8]; 2596 u8 user_index[0x18]; 2597 2598 u8 reserved_3[0x8]; 2599 u8 cqn[0x18]; 2600 2601 u8 counter_set_id[0x8]; 2602 u8 atomic_mode[0x4]; 2603 u8 rre[0x1]; 2604 u8 rwe[0x1]; 2605 u8 rae[0x1]; 2606 u8 atomic_like_write_en[0x1]; 2607 u8 latency_sensitive[0x1]; 2608 u8 rlky[0x1]; 2609 u8 reserved_4[0xe]; 2610 2611 u8 reserved_5[0x8]; 2612 u8 cs_res[0x8]; 2613 u8 reserved_6[0x3]; 2614 u8 min_rnr_nak[0x5]; 2615 u8 reserved_7[0x8]; 2616 2617 u8 reserved_8[0x8]; 2618 u8 srqn[0x18]; 2619 2620 u8 reserved_9[0x8]; 2621 u8 pd[0x18]; 2622 2623 u8 tclass[0x8]; 2624 u8 reserved_10[0x4]; 2625 u8 flow_label[0x14]; 2626 2627 u8 dc_access_key[0x40]; 2628 2629 u8 reserved_11[0x5]; 2630 u8 mtu[0x3]; 2631 u8 port[0x8]; 2632 u8 pkey_index[0x10]; 2633 2634 u8 reserved_12[0x8]; 2635 u8 my_addr_index[0x8]; 2636 u8 reserved_13[0x8]; 2637 u8 hop_limit[0x8]; 2638 2639 u8 dc_access_key_violation_count[0x20]; 2640 2641 u8 reserved_14[0x14]; 2642 u8 dei_cfi[0x1]; 2643 u8 eth_prio[0x3]; 2644 u8 ecn[0x2]; 2645 u8 dscp[0x6]; 2646 2647 u8 reserved_15[0x40]; 2648 }; 2649 2650 enum { 2651 MLX5_CQC_STATUS_OK = 0x0, 2652 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2653 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2654 }; 2655 2656 enum { 2657 CQE_SIZE_64 = 0x0, 2658 CQE_SIZE_128 = 0x1, 2659 }; 2660 2661 enum { 2662 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2663 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2664 }; 2665 2666 enum { 2667 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 2668 MLX5_CQ_STATE_ARMED = 0x9, 2669 MLX5_CQ_STATE_FIRED = 0xa, 2670 }; 2671 2672 struct mlx5_ifc_cqc_bits { 2673 u8 status[0x4]; 2674 u8 reserved_0[0x4]; 2675 u8 cqe_sz[0x3]; 2676 u8 cc[0x1]; 2677 u8 reserved_1[0x1]; 2678 u8 scqe_break_moderation_en[0x1]; 2679 u8 oi[0x1]; 2680 u8 cq_period_mode[0x2]; 2681 u8 cqe_compression_en[0x1]; 2682 u8 mini_cqe_res_format[0x2]; 2683 u8 st[0x4]; 2684 u8 reserved_2[0x8]; 2685 2686 u8 reserved_3[0x20]; 2687 2688 u8 reserved_4[0x14]; 2689 u8 page_offset[0x6]; 2690 u8 reserved_5[0x6]; 2691 2692 u8 reserved_6[0x3]; 2693 u8 log_cq_size[0x5]; 2694 u8 uar_page[0x18]; 2695 2696 u8 reserved_7[0x4]; 2697 u8 cq_period[0xc]; 2698 u8 cq_max_count[0x10]; 2699 2700 u8 reserved_8[0x18]; 2701 u8 c_eqn[0x8]; 2702 2703 u8 reserved_9[0x3]; 2704 u8 log_page_size[0x5]; 2705 u8 reserved_10[0x18]; 2706 2707 u8 reserved_11[0x20]; 2708 2709 u8 reserved_12[0x8]; 2710 u8 last_notified_index[0x18]; 2711 2712 u8 reserved_13[0x8]; 2713 u8 last_solicit_index[0x18]; 2714 2715 u8 reserved_14[0x8]; 2716 u8 consumer_counter[0x18]; 2717 2718 u8 reserved_15[0x8]; 2719 u8 producer_counter[0x18]; 2720 2721 u8 reserved_16[0x40]; 2722 2723 u8 dbr_addr[0x40]; 2724 }; 2725 2726 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2727 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2728 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2729 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2730 u8 reserved_0[0x800]; 2731 }; 2732 2733 struct mlx5_ifc_query_adapter_param_block_bits { 2734 u8 reserved_0[0xc0]; 2735 2736 u8 reserved_1[0x8]; 2737 u8 ieee_vendor_id[0x18]; 2738 2739 u8 reserved_2[0x10]; 2740 u8 vsd_vendor_id[0x10]; 2741 2742 u8 vsd[208][0x8]; 2743 2744 u8 vsd_contd_psid[16][0x8]; 2745 }; 2746 2747 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2748 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2749 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2750 u8 reserved_0[0x20]; 2751 }; 2752 2753 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2754 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2755 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2756 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2757 u8 reserved_0[0x20]; 2758 }; 2759 2760 struct mlx5_ifc_bufferx_reg_bits { 2761 u8 reserved_0[0x6]; 2762 u8 lossy[0x1]; 2763 u8 epsb[0x1]; 2764 u8 reserved_1[0xc]; 2765 u8 size[0xc]; 2766 2767 u8 xoff_threshold[0x10]; 2768 u8 xon_threshold[0x10]; 2769 }; 2770 2771 struct mlx5_ifc_config_item_bits { 2772 u8 valid[0x2]; 2773 u8 reserved_0[0x2]; 2774 u8 header_type[0x2]; 2775 u8 reserved_1[0x2]; 2776 u8 default_location[0x1]; 2777 u8 reserved_2[0x7]; 2778 u8 version[0x4]; 2779 u8 reserved_3[0x3]; 2780 u8 length[0x9]; 2781 2782 u8 type[0x20]; 2783 2784 u8 reserved_4[0x10]; 2785 u8 crc16[0x10]; 2786 }; 2787 2788 struct mlx5_ifc_nodnic_port_config_reg_bits { 2789 struct mlx5_ifc_nodnic_event_word_bits event; 2790 2791 u8 network_en[0x1]; 2792 u8 dma_en[0x1]; 2793 u8 promisc_en[0x1]; 2794 u8 promisc_multicast_en[0x1]; 2795 u8 reserved_0[0x17]; 2796 u8 receive_filter_en[0x5]; 2797 2798 u8 reserved_1[0x10]; 2799 u8 mac_47_32[0x10]; 2800 2801 u8 mac_31_0[0x20]; 2802 2803 u8 receive_filters_mgid_mac[64][0x8]; 2804 2805 u8 gid[16][0x8]; 2806 2807 u8 reserved_2[0x10]; 2808 u8 lid[0x10]; 2809 2810 u8 reserved_3[0xc]; 2811 u8 sm_sl[0x4]; 2812 u8 sm_lid[0x10]; 2813 2814 u8 completion_address_63_32[0x20]; 2815 2816 u8 completion_address_31_12[0x14]; 2817 u8 reserved_4[0x6]; 2818 u8 log_cq_size[0x6]; 2819 2820 u8 working_buffer_address_63_32[0x20]; 2821 2822 u8 working_buffer_address_31_12[0x14]; 2823 u8 reserved_5[0xc]; 2824 2825 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 2826 2827 u8 pkey_index[0x10]; 2828 u8 pkey[0x10]; 2829 2830 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 2831 2832 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 2833 2834 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 2835 2836 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 2837 2838 u8 reserved_6[0x400]; 2839 }; 2840 2841 union mlx5_ifc_event_auto_bits { 2842 struct mlx5_ifc_comp_event_bits comp_event; 2843 struct mlx5_ifc_dct_events_bits dct_events; 2844 struct mlx5_ifc_qp_events_bits qp_events; 2845 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 2846 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 2847 struct mlx5_ifc_cq_error_bits cq_error; 2848 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 2849 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 2850 struct mlx5_ifc_gpio_event_bits gpio_event; 2851 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 2852 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 2853 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 2854 struct mlx5_ifc_pages_req_event_bits pages_req_event; 2855 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 2856 u8 reserved_0[0xe0]; 2857 }; 2858 2859 struct mlx5_ifc_health_buffer_bits { 2860 u8 reserved_0[0x100]; 2861 2862 u8 assert_existptr[0x20]; 2863 2864 u8 assert_callra[0x20]; 2865 2866 u8 reserved_1[0x40]; 2867 2868 u8 fw_version[0x20]; 2869 2870 u8 hw_id[0x20]; 2871 2872 u8 reserved_2[0x20]; 2873 2874 u8 irisc_index[0x8]; 2875 u8 synd[0x8]; 2876 u8 ext_synd[0x10]; 2877 }; 2878 2879 struct mlx5_ifc_register_loopback_control_bits { 2880 u8 no_lb[0x1]; 2881 u8 reserved_0[0x7]; 2882 u8 port[0x8]; 2883 u8 reserved_1[0x10]; 2884 2885 u8 reserved_2[0x60]; 2886 }; 2887 2888 struct mlx5_ifc_lrh_bits { 2889 u8 vl[4]; 2890 u8 lver[4]; 2891 u8 sl[4]; 2892 u8 reserved2[2]; 2893 u8 lnh[2]; 2894 u8 dlid[16]; 2895 u8 reserved5[5]; 2896 u8 pkt_len[11]; 2897 u8 slid[16]; 2898 }; 2899 2900 struct mlx5_ifc_icmd_set_wol_rol_out_bits { 2901 u8 reserved_0[0x40]; 2902 2903 u8 reserved_1[0x10]; 2904 u8 rol_mode[0x8]; 2905 u8 wol_mode[0x8]; 2906 }; 2907 2908 struct mlx5_ifc_icmd_set_wol_rol_in_bits { 2909 u8 reserved_0[0x40]; 2910 2911 u8 rol_mode_valid[0x1]; 2912 u8 wol_mode_valid[0x1]; 2913 u8 reserved_1[0xe]; 2914 u8 rol_mode[0x8]; 2915 u8 wol_mode[0x8]; 2916 2917 u8 reserved_2[0x7a0]; 2918 }; 2919 2920 struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 2921 u8 virtual_mac_en[0x1]; 2922 u8 mac_aux_v[0x1]; 2923 u8 reserved_0[0x1e]; 2924 2925 u8 reserved_1[0x40]; 2926 2927 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 2928 2929 u8 reserved_2[0x760]; 2930 }; 2931 2932 struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 2933 u8 virtual_mac_en[0x1]; 2934 u8 mac_aux_v[0x1]; 2935 u8 reserved_0[0x1e]; 2936 2937 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 2938 2939 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 2940 2941 u8 reserved_1[0x760]; 2942 }; 2943 2944 struct mlx5_ifc_icmd_query_fw_info_out_bits { 2945 struct mlx5_ifc_fw_version_bits fw_version; 2946 2947 u8 reserved_0[0x10]; 2948 u8 hash_signature[0x10]; 2949 2950 u8 psid[16][0x8]; 2951 2952 u8 reserved_1[0x6e0]; 2953 }; 2954 2955 struct mlx5_ifc_icmd_query_cap_in_bits { 2956 u8 reserved_0[0x10]; 2957 u8 capability_group[0x10]; 2958 }; 2959 2960 struct mlx5_ifc_icmd_query_cap_general_bits { 2961 u8 nv_access[0x1]; 2962 u8 fw_info_psid[0x1]; 2963 u8 reserved_0[0x1e]; 2964 2965 u8 reserved_1[0x16]; 2966 u8 rol_s[0x1]; 2967 u8 rol_g[0x1]; 2968 u8 reserved_2[0x1]; 2969 u8 wol_s[0x1]; 2970 u8 wol_g[0x1]; 2971 u8 wol_a[0x1]; 2972 u8 wol_b[0x1]; 2973 u8 wol_m[0x1]; 2974 u8 wol_u[0x1]; 2975 u8 wol_p[0x1]; 2976 }; 2977 2978 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 2979 u8 status[0x8]; 2980 u8 reserved_0[0x18]; 2981 2982 u8 reserved_1[0x7e0]; 2983 }; 2984 2985 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 2986 u8 status[0x8]; 2987 u8 reserved_0[0x18]; 2988 2989 u8 reserved_1[0x7e0]; 2990 }; 2991 2992 struct mlx5_ifc_icmd_ocbb_init_in_bits { 2993 u8 address_hi[0x20]; 2994 2995 u8 address_lo[0x20]; 2996 2997 u8 reserved_0[0x7c0]; 2998 }; 2999 3000 struct mlx5_ifc_icmd_init_ocsd_in_bits { 3001 u8 reserved_0[0x20]; 3002 3003 u8 address_hi[0x20]; 3004 3005 u8 address_lo[0x20]; 3006 3007 u8 reserved_1[0x7a0]; 3008 }; 3009 3010 struct mlx5_ifc_icmd_access_reg_out_bits { 3011 u8 reserved_0[0x11]; 3012 u8 status[0x7]; 3013 u8 reserved_1[0x8]; 3014 3015 u8 register_id[0x10]; 3016 u8 reserved_2[0x10]; 3017 3018 u8 reserved_3[0x40]; 3019 3020 u8 reserved_4[0x5]; 3021 u8 len[0xb]; 3022 u8 reserved_5[0x10]; 3023 3024 u8 register_data[0][0x20]; 3025 }; 3026 3027 enum { 3028 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3029 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3030 }; 3031 3032 struct mlx5_ifc_icmd_access_reg_in_bits { 3033 u8 constant_1[0x5]; 3034 u8 constant_2[0xb]; 3035 u8 reserved_0[0x10]; 3036 3037 u8 register_id[0x10]; 3038 u8 reserved_1[0x1]; 3039 u8 method[0x7]; 3040 u8 constant_3[0x8]; 3041 3042 u8 reserved_2[0x40]; 3043 3044 u8 constant_4[0x5]; 3045 u8 len[0xb]; 3046 u8 reserved_3[0x10]; 3047 3048 u8 register_data[0][0x20]; 3049 }; 3050 3051 struct mlx5_ifc_teardown_hca_out_bits { 3052 u8 status[0x8]; 3053 u8 reserved_0[0x18]; 3054 3055 u8 syndrome[0x20]; 3056 3057 u8 reserved_1[0x40]; 3058 }; 3059 3060 enum { 3061 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3062 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1, 3063 }; 3064 3065 struct mlx5_ifc_teardown_hca_in_bits { 3066 u8 opcode[0x10]; 3067 u8 reserved_0[0x10]; 3068 3069 u8 reserved_1[0x10]; 3070 u8 op_mod[0x10]; 3071 3072 u8 reserved_2[0x10]; 3073 u8 profile[0x10]; 3074 3075 u8 reserved_3[0x20]; 3076 }; 3077 3078 struct mlx5_ifc_suspend_qp_out_bits { 3079 u8 status[0x8]; 3080 u8 reserved_0[0x18]; 3081 3082 u8 syndrome[0x20]; 3083 3084 u8 reserved_1[0x40]; 3085 }; 3086 3087 struct mlx5_ifc_suspend_qp_in_bits { 3088 u8 opcode[0x10]; 3089 u8 reserved_0[0x10]; 3090 3091 u8 reserved_1[0x10]; 3092 u8 op_mod[0x10]; 3093 3094 u8 reserved_2[0x8]; 3095 u8 qpn[0x18]; 3096 3097 u8 reserved_3[0x20]; 3098 }; 3099 3100 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3101 u8 status[0x8]; 3102 u8 reserved_0[0x18]; 3103 3104 u8 syndrome[0x20]; 3105 3106 u8 reserved_1[0x40]; 3107 }; 3108 3109 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3110 u8 opcode[0x10]; 3111 u8 reserved_0[0x10]; 3112 3113 u8 reserved_1[0x10]; 3114 u8 op_mod[0x10]; 3115 3116 u8 reserved_2[0x8]; 3117 u8 qpn[0x18]; 3118 3119 u8 reserved_3[0x20]; 3120 3121 u8 opt_param_mask[0x20]; 3122 3123 u8 reserved_4[0x20]; 3124 3125 struct mlx5_ifc_qpc_bits qpc; 3126 3127 u8 reserved_5[0x80]; 3128 }; 3129 3130 struct mlx5_ifc_sqd2rts_qp_out_bits { 3131 u8 status[0x8]; 3132 u8 reserved_0[0x18]; 3133 3134 u8 syndrome[0x20]; 3135 3136 u8 reserved_1[0x40]; 3137 }; 3138 3139 struct mlx5_ifc_sqd2rts_qp_in_bits { 3140 u8 opcode[0x10]; 3141 u8 reserved_0[0x10]; 3142 3143 u8 reserved_1[0x10]; 3144 u8 op_mod[0x10]; 3145 3146 u8 reserved_2[0x8]; 3147 u8 qpn[0x18]; 3148 3149 u8 reserved_3[0x20]; 3150 3151 u8 opt_param_mask[0x20]; 3152 3153 u8 reserved_4[0x20]; 3154 3155 struct mlx5_ifc_qpc_bits qpc; 3156 3157 u8 reserved_5[0x80]; 3158 }; 3159 3160 struct mlx5_ifc_set_wol_rol_out_bits { 3161 u8 status[0x8]; 3162 u8 reserved_0[0x18]; 3163 3164 u8 syndrome[0x20]; 3165 3166 u8 reserved_1[0x40]; 3167 }; 3168 3169 struct mlx5_ifc_set_wol_rol_in_bits { 3170 u8 opcode[0x10]; 3171 u8 reserved_0[0x10]; 3172 3173 u8 reserved_1[0x10]; 3174 u8 op_mod[0x10]; 3175 3176 u8 rol_mode_valid[0x1]; 3177 u8 wol_mode_valid[0x1]; 3178 u8 reserved_2[0xe]; 3179 u8 rol_mode[0x8]; 3180 u8 wol_mode[0x8]; 3181 3182 u8 reserved_3[0x20]; 3183 }; 3184 3185 struct mlx5_ifc_set_roce_address_out_bits { 3186 u8 status[0x8]; 3187 u8 reserved_0[0x18]; 3188 3189 u8 syndrome[0x20]; 3190 3191 u8 reserved_1[0x40]; 3192 }; 3193 3194 struct mlx5_ifc_set_roce_address_in_bits { 3195 u8 opcode[0x10]; 3196 u8 reserved_0[0x10]; 3197 3198 u8 reserved_1[0x10]; 3199 u8 op_mod[0x10]; 3200 3201 u8 roce_address_index[0x10]; 3202 u8 reserved_2[0x10]; 3203 3204 u8 reserved_3[0x20]; 3205 3206 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3207 }; 3208 3209 struct mlx5_ifc_set_rdb_out_bits { 3210 u8 status[0x8]; 3211 u8 reserved_0[0x18]; 3212 3213 u8 syndrome[0x20]; 3214 3215 u8 reserved_1[0x40]; 3216 }; 3217 3218 struct mlx5_ifc_set_rdb_in_bits { 3219 u8 opcode[0x10]; 3220 u8 reserved_0[0x10]; 3221 3222 u8 reserved_1[0x10]; 3223 u8 op_mod[0x10]; 3224 3225 u8 reserved_2[0x8]; 3226 u8 qpn[0x18]; 3227 3228 u8 reserved_3[0x18]; 3229 u8 rdb_list_size[0x8]; 3230 3231 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3232 }; 3233 3234 struct mlx5_ifc_set_mad_demux_out_bits { 3235 u8 status[0x8]; 3236 u8 reserved_0[0x18]; 3237 3238 u8 syndrome[0x20]; 3239 3240 u8 reserved_1[0x40]; 3241 }; 3242 3243 enum { 3244 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3245 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3246 }; 3247 3248 struct mlx5_ifc_set_mad_demux_in_bits { 3249 u8 opcode[0x10]; 3250 u8 reserved_0[0x10]; 3251 3252 u8 reserved_1[0x10]; 3253 u8 op_mod[0x10]; 3254 3255 u8 reserved_2[0x20]; 3256 3257 u8 reserved_3[0x6]; 3258 u8 demux_mode[0x2]; 3259 u8 reserved_4[0x18]; 3260 }; 3261 3262 struct mlx5_ifc_set_l2_table_entry_out_bits { 3263 u8 status[0x8]; 3264 u8 reserved_0[0x18]; 3265 3266 u8 syndrome[0x20]; 3267 3268 u8 reserved_1[0x40]; 3269 }; 3270 3271 struct mlx5_ifc_set_l2_table_entry_in_bits { 3272 u8 opcode[0x10]; 3273 u8 reserved_0[0x10]; 3274 3275 u8 reserved_1[0x10]; 3276 u8 op_mod[0x10]; 3277 3278 u8 reserved_2[0x60]; 3279 3280 u8 reserved_3[0x8]; 3281 u8 table_index[0x18]; 3282 3283 u8 reserved_4[0x20]; 3284 3285 u8 reserved_5[0x13]; 3286 u8 vlan_valid[0x1]; 3287 u8 vlan[0xc]; 3288 3289 struct mlx5_ifc_mac_address_layout_bits mac_address; 3290 3291 u8 reserved_6[0xc0]; 3292 }; 3293 3294 struct mlx5_ifc_set_issi_out_bits { 3295 u8 status[0x8]; 3296 u8 reserved_0[0x18]; 3297 3298 u8 syndrome[0x20]; 3299 3300 u8 reserved_1[0x40]; 3301 }; 3302 3303 struct mlx5_ifc_set_issi_in_bits { 3304 u8 opcode[0x10]; 3305 u8 reserved_0[0x10]; 3306 3307 u8 reserved_1[0x10]; 3308 u8 op_mod[0x10]; 3309 3310 u8 reserved_2[0x10]; 3311 u8 current_issi[0x10]; 3312 3313 u8 reserved_3[0x20]; 3314 }; 3315 3316 struct mlx5_ifc_set_hca_cap_out_bits { 3317 u8 status[0x8]; 3318 u8 reserved_0[0x18]; 3319 3320 u8 syndrome[0x20]; 3321 3322 u8 reserved_1[0x40]; 3323 }; 3324 3325 struct mlx5_ifc_set_hca_cap_in_bits { 3326 u8 opcode[0x10]; 3327 u8 reserved_0[0x10]; 3328 3329 u8 reserved_1[0x10]; 3330 u8 op_mod[0x10]; 3331 3332 u8 reserved_2[0x40]; 3333 3334 union mlx5_ifc_hca_cap_union_bits capability; 3335 }; 3336 3337 enum { 3338 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3339 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3340 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3341 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3342 }; 3343 3344 struct mlx5_ifc_set_flow_table_root_out_bits { 3345 u8 status[0x8]; 3346 u8 reserved_0[0x18]; 3347 3348 u8 syndrome[0x20]; 3349 3350 u8 reserved_1[0x40]; 3351 }; 3352 3353 struct mlx5_ifc_set_flow_table_root_in_bits { 3354 u8 opcode[0x10]; 3355 u8 reserved_0[0x10]; 3356 3357 u8 reserved_1[0x10]; 3358 u8 op_mod[0x10]; 3359 3360 u8 other_vport[0x1]; 3361 u8 reserved_2[0xf]; 3362 u8 vport_number[0x10]; 3363 3364 u8 reserved_3[0x20]; 3365 3366 u8 table_type[0x8]; 3367 u8 reserved_4[0x18]; 3368 3369 u8 reserved_5[0x8]; 3370 u8 table_id[0x18]; 3371 3372 u8 reserved_6[0x8]; 3373 u8 underlay_qpn[0x18]; 3374 3375 u8 reserved_7[0x120]; 3376 }; 3377 3378 struct mlx5_ifc_set_fte_out_bits { 3379 u8 status[0x8]; 3380 u8 reserved_0[0x18]; 3381 3382 u8 syndrome[0x20]; 3383 3384 u8 reserved_1[0x40]; 3385 }; 3386 3387 struct mlx5_ifc_set_fte_in_bits { 3388 u8 opcode[0x10]; 3389 u8 reserved_0[0x10]; 3390 3391 u8 reserved_1[0x10]; 3392 u8 op_mod[0x10]; 3393 3394 u8 other_vport[0x1]; 3395 u8 reserved_2[0xf]; 3396 u8 vport_number[0x10]; 3397 3398 u8 reserved_3[0x20]; 3399 3400 u8 table_type[0x8]; 3401 u8 reserved_4[0x18]; 3402 3403 u8 reserved_5[0x8]; 3404 u8 table_id[0x18]; 3405 3406 u8 reserved_6[0x18]; 3407 u8 modify_enable_mask[0x8]; 3408 3409 u8 reserved_7[0x20]; 3410 3411 u8 flow_index[0x20]; 3412 3413 u8 reserved_8[0xe0]; 3414 3415 struct mlx5_ifc_flow_context_bits flow_context; 3416 }; 3417 3418 struct mlx5_ifc_set_driver_version_out_bits { 3419 u8 status[0x8]; 3420 u8 reserved_0[0x18]; 3421 3422 u8 syndrome[0x20]; 3423 3424 u8 reserved_1[0x40]; 3425 }; 3426 3427 struct mlx5_ifc_set_driver_version_in_bits { 3428 u8 opcode[0x10]; 3429 u8 reserved_0[0x10]; 3430 3431 u8 reserved_1[0x10]; 3432 u8 op_mod[0x10]; 3433 3434 u8 reserved_2[0x40]; 3435 3436 u8 driver_version[64][0x8]; 3437 }; 3438 3439 struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3440 u8 status[0x8]; 3441 u8 reserved_0[0x18]; 3442 3443 u8 syndrome[0x20]; 3444 3445 u8 reserved_1[0x40]; 3446 }; 3447 3448 struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3449 u8 opcode[0x10]; 3450 u8 reserved_0[0x10]; 3451 3452 u8 reserved_1[0x10]; 3453 u8 op_mod[0x10]; 3454 3455 u8 enable[0x1]; 3456 u8 reserved_2[0x1f]; 3457 3458 u8 reserved_3[0x160]; 3459 3460 struct mlx5_ifc_cmd_pas_bits pas; 3461 }; 3462 3463 struct mlx5_ifc_set_burst_size_out_bits { 3464 u8 status[0x8]; 3465 u8 reserved_0[0x18]; 3466 3467 u8 syndrome[0x20]; 3468 3469 u8 reserved_1[0x40]; 3470 }; 3471 3472 struct mlx5_ifc_set_burst_size_in_bits { 3473 u8 opcode[0x10]; 3474 u8 reserved_0[0x10]; 3475 3476 u8 reserved_1[0x10]; 3477 u8 op_mod[0x10]; 3478 3479 u8 reserved_2[0x20]; 3480 3481 u8 reserved_3[0x9]; 3482 u8 device_burst_size[0x17]; 3483 }; 3484 3485 struct mlx5_ifc_rts2rts_qp_out_bits { 3486 u8 status[0x8]; 3487 u8 reserved_0[0x18]; 3488 3489 u8 syndrome[0x20]; 3490 3491 u8 reserved_1[0x40]; 3492 }; 3493 3494 struct mlx5_ifc_rts2rts_qp_in_bits { 3495 u8 opcode[0x10]; 3496 u8 reserved_0[0x10]; 3497 3498 u8 reserved_1[0x10]; 3499 u8 op_mod[0x10]; 3500 3501 u8 reserved_2[0x8]; 3502 u8 qpn[0x18]; 3503 3504 u8 reserved_3[0x20]; 3505 3506 u8 opt_param_mask[0x20]; 3507 3508 u8 reserved_4[0x20]; 3509 3510 struct mlx5_ifc_qpc_bits qpc; 3511 3512 u8 reserved_5[0x80]; 3513 }; 3514 3515 struct mlx5_ifc_rtr2rts_qp_out_bits { 3516 u8 status[0x8]; 3517 u8 reserved_0[0x18]; 3518 3519 u8 syndrome[0x20]; 3520 3521 u8 reserved_1[0x40]; 3522 }; 3523 3524 struct mlx5_ifc_rtr2rts_qp_in_bits { 3525 u8 opcode[0x10]; 3526 u8 reserved_0[0x10]; 3527 3528 u8 reserved_1[0x10]; 3529 u8 op_mod[0x10]; 3530 3531 u8 reserved_2[0x8]; 3532 u8 qpn[0x18]; 3533 3534 u8 reserved_3[0x20]; 3535 3536 u8 opt_param_mask[0x20]; 3537 3538 u8 reserved_4[0x20]; 3539 3540 struct mlx5_ifc_qpc_bits qpc; 3541 3542 u8 reserved_5[0x80]; 3543 }; 3544 3545 struct mlx5_ifc_rst2init_qp_out_bits { 3546 u8 status[0x8]; 3547 u8 reserved_0[0x18]; 3548 3549 u8 syndrome[0x20]; 3550 3551 u8 reserved_1[0x40]; 3552 }; 3553 3554 struct mlx5_ifc_rst2init_qp_in_bits { 3555 u8 opcode[0x10]; 3556 u8 reserved_0[0x10]; 3557 3558 u8 reserved_1[0x10]; 3559 u8 op_mod[0x10]; 3560 3561 u8 reserved_2[0x8]; 3562 u8 qpn[0x18]; 3563 3564 u8 reserved_3[0x20]; 3565 3566 u8 opt_param_mask[0x20]; 3567 3568 u8 reserved_4[0x20]; 3569 3570 struct mlx5_ifc_qpc_bits qpc; 3571 3572 u8 reserved_5[0x80]; 3573 }; 3574 3575 struct mlx5_ifc_resume_qp_out_bits { 3576 u8 status[0x8]; 3577 u8 reserved_0[0x18]; 3578 3579 u8 syndrome[0x20]; 3580 3581 u8 reserved_1[0x40]; 3582 }; 3583 3584 struct mlx5_ifc_resume_qp_in_bits { 3585 u8 opcode[0x10]; 3586 u8 reserved_0[0x10]; 3587 3588 u8 reserved_1[0x10]; 3589 u8 op_mod[0x10]; 3590 3591 u8 reserved_2[0x8]; 3592 u8 qpn[0x18]; 3593 3594 u8 reserved_3[0x20]; 3595 }; 3596 3597 struct mlx5_ifc_query_xrc_srq_out_bits { 3598 u8 status[0x8]; 3599 u8 reserved_0[0x18]; 3600 3601 u8 syndrome[0x20]; 3602 3603 u8 reserved_1[0x40]; 3604 3605 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3606 3607 u8 reserved_2[0x600]; 3608 3609 u8 pas[0][0x40]; 3610 }; 3611 3612 struct mlx5_ifc_query_xrc_srq_in_bits { 3613 u8 opcode[0x10]; 3614 u8 reserved_0[0x10]; 3615 3616 u8 reserved_1[0x10]; 3617 u8 op_mod[0x10]; 3618 3619 u8 reserved_2[0x8]; 3620 u8 xrc_srqn[0x18]; 3621 3622 u8 reserved_3[0x20]; 3623 }; 3624 3625 struct mlx5_ifc_query_wol_rol_out_bits { 3626 u8 status[0x8]; 3627 u8 reserved_0[0x18]; 3628 3629 u8 syndrome[0x20]; 3630 3631 u8 reserved_1[0x10]; 3632 u8 rol_mode[0x8]; 3633 u8 wol_mode[0x8]; 3634 3635 u8 reserved_2[0x20]; 3636 }; 3637 3638 struct mlx5_ifc_query_wol_rol_in_bits { 3639 u8 opcode[0x10]; 3640 u8 reserved_0[0x10]; 3641 3642 u8 reserved_1[0x10]; 3643 u8 op_mod[0x10]; 3644 3645 u8 reserved_2[0x40]; 3646 }; 3647 3648 enum { 3649 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3650 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3651 }; 3652 3653 struct mlx5_ifc_query_vport_state_out_bits { 3654 u8 status[0x8]; 3655 u8 reserved_0[0x18]; 3656 3657 u8 syndrome[0x20]; 3658 3659 u8 reserved_1[0x20]; 3660 3661 u8 reserved_2[0x18]; 3662 u8 admin_state[0x4]; 3663 u8 state[0x4]; 3664 }; 3665 3666 enum { 3667 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3668 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3669 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 3670 }; 3671 3672 struct mlx5_ifc_query_vport_state_in_bits { 3673 u8 opcode[0x10]; 3674 u8 reserved_0[0x10]; 3675 3676 u8 reserved_1[0x10]; 3677 u8 op_mod[0x10]; 3678 3679 u8 other_vport[0x1]; 3680 u8 reserved_2[0xf]; 3681 u8 vport_number[0x10]; 3682 3683 u8 reserved_3[0x20]; 3684 }; 3685 3686 struct mlx5_ifc_query_vport_counter_out_bits { 3687 u8 status[0x8]; 3688 u8 reserved_0[0x18]; 3689 3690 u8 syndrome[0x20]; 3691 3692 u8 reserved_1[0x40]; 3693 3694 struct mlx5_ifc_traffic_counter_bits received_errors; 3695 3696 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3697 3698 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3699 3700 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3701 3702 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3703 3704 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3705 3706 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3707 3708 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3709 3710 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3711 3712 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3713 3714 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3715 3716 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3717 3718 u8 reserved_2[0xa00]; 3719 }; 3720 3721 enum { 3722 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3723 }; 3724 3725 struct mlx5_ifc_query_vport_counter_in_bits { 3726 u8 opcode[0x10]; 3727 u8 reserved_0[0x10]; 3728 3729 u8 reserved_1[0x10]; 3730 u8 op_mod[0x10]; 3731 3732 u8 other_vport[0x1]; 3733 u8 reserved_2[0xb]; 3734 u8 port_num[0x4]; 3735 u8 vport_number[0x10]; 3736 3737 u8 reserved_3[0x60]; 3738 3739 u8 clear[0x1]; 3740 u8 reserved_4[0x1f]; 3741 3742 u8 reserved_5[0x20]; 3743 }; 3744 3745 struct mlx5_ifc_query_tis_out_bits { 3746 u8 status[0x8]; 3747 u8 reserved_0[0x18]; 3748 3749 u8 syndrome[0x20]; 3750 3751 u8 reserved_1[0x40]; 3752 3753 struct mlx5_ifc_tisc_bits tis_context; 3754 }; 3755 3756 struct mlx5_ifc_query_tis_in_bits { 3757 u8 opcode[0x10]; 3758 u8 reserved_0[0x10]; 3759 3760 u8 reserved_1[0x10]; 3761 u8 op_mod[0x10]; 3762 3763 u8 reserved_2[0x8]; 3764 u8 tisn[0x18]; 3765 3766 u8 reserved_3[0x20]; 3767 }; 3768 3769 struct mlx5_ifc_query_tir_out_bits { 3770 u8 status[0x8]; 3771 u8 reserved_0[0x18]; 3772 3773 u8 syndrome[0x20]; 3774 3775 u8 reserved_1[0xc0]; 3776 3777 struct mlx5_ifc_tirc_bits tir_context; 3778 }; 3779 3780 struct mlx5_ifc_query_tir_in_bits { 3781 u8 opcode[0x10]; 3782 u8 reserved_0[0x10]; 3783 3784 u8 reserved_1[0x10]; 3785 u8 op_mod[0x10]; 3786 3787 u8 reserved_2[0x8]; 3788 u8 tirn[0x18]; 3789 3790 u8 reserved_3[0x20]; 3791 }; 3792 3793 struct mlx5_ifc_query_srq_out_bits { 3794 u8 status[0x8]; 3795 u8 reserved_0[0x18]; 3796 3797 u8 syndrome[0x20]; 3798 3799 u8 reserved_1[0x40]; 3800 3801 struct mlx5_ifc_srqc_bits srq_context_entry; 3802 3803 u8 reserved_2[0x600]; 3804 3805 u8 pas[0][0x40]; 3806 }; 3807 3808 struct mlx5_ifc_query_srq_in_bits { 3809 u8 opcode[0x10]; 3810 u8 reserved_0[0x10]; 3811 3812 u8 reserved_1[0x10]; 3813 u8 op_mod[0x10]; 3814 3815 u8 reserved_2[0x8]; 3816 u8 srqn[0x18]; 3817 3818 u8 reserved_3[0x20]; 3819 }; 3820 3821 struct mlx5_ifc_query_sq_out_bits { 3822 u8 status[0x8]; 3823 u8 reserved_0[0x18]; 3824 3825 u8 syndrome[0x20]; 3826 3827 u8 reserved_1[0xc0]; 3828 3829 struct mlx5_ifc_sqc_bits sq_context; 3830 }; 3831 3832 struct mlx5_ifc_query_sq_in_bits { 3833 u8 opcode[0x10]; 3834 u8 reserved_0[0x10]; 3835 3836 u8 reserved_1[0x10]; 3837 u8 op_mod[0x10]; 3838 3839 u8 reserved_2[0x8]; 3840 u8 sqn[0x18]; 3841 3842 u8 reserved_3[0x20]; 3843 }; 3844 3845 struct mlx5_ifc_query_special_contexts_out_bits { 3846 u8 status[0x8]; 3847 u8 reserved_0[0x18]; 3848 3849 u8 syndrome[0x20]; 3850 3851 u8 reserved_1[0x20]; 3852 3853 u8 resd_lkey[0x20]; 3854 }; 3855 3856 struct mlx5_ifc_query_special_contexts_in_bits { 3857 u8 opcode[0x10]; 3858 u8 reserved_0[0x10]; 3859 3860 u8 reserved_1[0x10]; 3861 u8 op_mod[0x10]; 3862 3863 u8 reserved_2[0x40]; 3864 }; 3865 3866 struct mlx5_ifc_query_scheduling_element_out_bits { 3867 u8 status[0x8]; 3868 u8 reserved_at_8[0x18]; 3869 3870 u8 syndrome[0x20]; 3871 3872 u8 reserved_at_40[0xc0]; 3873 3874 struct mlx5_ifc_scheduling_context_bits scheduling_context; 3875 3876 u8 reserved_at_300[0x100]; 3877 }; 3878 3879 enum { 3880 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 3881 }; 3882 3883 struct mlx5_ifc_query_scheduling_element_in_bits { 3884 u8 opcode[0x10]; 3885 u8 reserved_at_10[0x10]; 3886 3887 u8 reserved_at_20[0x10]; 3888 u8 op_mod[0x10]; 3889 3890 u8 scheduling_hierarchy[0x8]; 3891 u8 reserved_at_48[0x18]; 3892 3893 u8 scheduling_element_id[0x20]; 3894 3895 u8 reserved_at_80[0x180]; 3896 }; 3897 3898 struct mlx5_ifc_query_rqt_out_bits { 3899 u8 status[0x8]; 3900 u8 reserved_0[0x18]; 3901 3902 u8 syndrome[0x20]; 3903 3904 u8 reserved_1[0xc0]; 3905 3906 struct mlx5_ifc_rqtc_bits rqt_context; 3907 }; 3908 3909 struct mlx5_ifc_query_rqt_in_bits { 3910 u8 opcode[0x10]; 3911 u8 reserved_0[0x10]; 3912 3913 u8 reserved_1[0x10]; 3914 u8 op_mod[0x10]; 3915 3916 u8 reserved_2[0x8]; 3917 u8 rqtn[0x18]; 3918 3919 u8 reserved_3[0x20]; 3920 }; 3921 3922 struct mlx5_ifc_query_rq_out_bits { 3923 u8 status[0x8]; 3924 u8 reserved_0[0x18]; 3925 3926 u8 syndrome[0x20]; 3927 3928 u8 reserved_1[0xc0]; 3929 3930 struct mlx5_ifc_rqc_bits rq_context; 3931 }; 3932 3933 struct mlx5_ifc_query_rq_in_bits { 3934 u8 opcode[0x10]; 3935 u8 reserved_0[0x10]; 3936 3937 u8 reserved_1[0x10]; 3938 u8 op_mod[0x10]; 3939 3940 u8 reserved_2[0x8]; 3941 u8 rqn[0x18]; 3942 3943 u8 reserved_3[0x20]; 3944 }; 3945 3946 struct mlx5_ifc_query_roce_address_out_bits { 3947 u8 status[0x8]; 3948 u8 reserved_0[0x18]; 3949 3950 u8 syndrome[0x20]; 3951 3952 u8 reserved_1[0x40]; 3953 3954 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3955 }; 3956 3957 struct mlx5_ifc_query_roce_address_in_bits { 3958 u8 opcode[0x10]; 3959 u8 reserved_0[0x10]; 3960 3961 u8 reserved_1[0x10]; 3962 u8 op_mod[0x10]; 3963 3964 u8 roce_address_index[0x10]; 3965 u8 reserved_2[0x10]; 3966 3967 u8 reserved_3[0x20]; 3968 }; 3969 3970 struct mlx5_ifc_query_rmp_out_bits { 3971 u8 status[0x8]; 3972 u8 reserved_0[0x18]; 3973 3974 u8 syndrome[0x20]; 3975 3976 u8 reserved_1[0xc0]; 3977 3978 struct mlx5_ifc_rmpc_bits rmp_context; 3979 }; 3980 3981 struct mlx5_ifc_query_rmp_in_bits { 3982 u8 opcode[0x10]; 3983 u8 reserved_0[0x10]; 3984 3985 u8 reserved_1[0x10]; 3986 u8 op_mod[0x10]; 3987 3988 u8 reserved_2[0x8]; 3989 u8 rmpn[0x18]; 3990 3991 u8 reserved_3[0x20]; 3992 }; 3993 3994 struct mlx5_ifc_query_rdb_out_bits { 3995 u8 status[0x8]; 3996 u8 reserved_0[0x18]; 3997 3998 u8 syndrome[0x20]; 3999 4000 u8 reserved_1[0x20]; 4001 4002 u8 reserved_2[0x18]; 4003 u8 rdb_list_size[0x8]; 4004 4005 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4006 }; 4007 4008 struct mlx5_ifc_query_rdb_in_bits { 4009 u8 opcode[0x10]; 4010 u8 reserved_0[0x10]; 4011 4012 u8 reserved_1[0x10]; 4013 u8 op_mod[0x10]; 4014 4015 u8 reserved_2[0x8]; 4016 u8 qpn[0x18]; 4017 4018 u8 reserved_3[0x20]; 4019 }; 4020 4021 struct mlx5_ifc_query_qp_out_bits { 4022 u8 status[0x8]; 4023 u8 reserved_0[0x18]; 4024 4025 u8 syndrome[0x20]; 4026 4027 u8 reserved_1[0x40]; 4028 4029 u8 opt_param_mask[0x20]; 4030 4031 u8 reserved_2[0x20]; 4032 4033 struct mlx5_ifc_qpc_bits qpc; 4034 4035 u8 reserved_3[0x80]; 4036 4037 u8 pas[0][0x40]; 4038 }; 4039 4040 struct mlx5_ifc_query_qp_in_bits { 4041 u8 opcode[0x10]; 4042 u8 reserved_0[0x10]; 4043 4044 u8 reserved_1[0x10]; 4045 u8 op_mod[0x10]; 4046 4047 u8 reserved_2[0x8]; 4048 u8 qpn[0x18]; 4049 4050 u8 reserved_3[0x20]; 4051 }; 4052 4053 struct mlx5_ifc_query_q_counter_out_bits { 4054 u8 status[0x8]; 4055 u8 reserved_0[0x18]; 4056 4057 u8 syndrome[0x20]; 4058 4059 u8 reserved_1[0x40]; 4060 4061 u8 rx_write_requests[0x20]; 4062 4063 u8 reserved_2[0x20]; 4064 4065 u8 rx_read_requests[0x20]; 4066 4067 u8 reserved_3[0x20]; 4068 4069 u8 rx_atomic_requests[0x20]; 4070 4071 u8 reserved_4[0x20]; 4072 4073 u8 rx_dct_connect[0x20]; 4074 4075 u8 reserved_5[0x20]; 4076 4077 u8 out_of_buffer[0x20]; 4078 4079 u8 reserved_7[0x20]; 4080 4081 u8 out_of_sequence[0x20]; 4082 4083 u8 reserved_8[0x20]; 4084 4085 u8 duplicate_request[0x20]; 4086 4087 u8 reserved_9[0x20]; 4088 4089 u8 rnr_nak_retry_err[0x20]; 4090 4091 u8 reserved_10[0x20]; 4092 4093 u8 packet_seq_err[0x20]; 4094 4095 u8 reserved_11[0x20]; 4096 4097 u8 implied_nak_seq_err[0x20]; 4098 4099 u8 reserved_12[0x20]; 4100 4101 u8 local_ack_timeout_err[0x20]; 4102 4103 u8 reserved_13[0x4e0]; 4104 }; 4105 4106 struct mlx5_ifc_query_q_counter_in_bits { 4107 u8 opcode[0x10]; 4108 u8 reserved_0[0x10]; 4109 4110 u8 reserved_1[0x10]; 4111 u8 op_mod[0x10]; 4112 4113 u8 reserved_2[0x80]; 4114 4115 u8 clear[0x1]; 4116 u8 reserved_3[0x1f]; 4117 4118 u8 reserved_4[0x18]; 4119 u8 counter_set_id[0x8]; 4120 }; 4121 4122 struct mlx5_ifc_query_pages_out_bits { 4123 u8 status[0x8]; 4124 u8 reserved_0[0x18]; 4125 4126 u8 syndrome[0x20]; 4127 4128 u8 reserved_1[0x10]; 4129 u8 function_id[0x10]; 4130 4131 u8 num_pages[0x20]; 4132 }; 4133 4134 enum { 4135 MLX5_BOOT_PAGES = 0x1, 4136 MLX5_INIT_PAGES = 0x2, 4137 MLX5_POST_INIT_PAGES = 0x3, 4138 }; 4139 4140 struct mlx5_ifc_query_pages_in_bits { 4141 u8 opcode[0x10]; 4142 u8 reserved_0[0x10]; 4143 4144 u8 reserved_1[0x10]; 4145 u8 op_mod[0x10]; 4146 4147 u8 reserved_2[0x10]; 4148 u8 function_id[0x10]; 4149 4150 u8 reserved_3[0x20]; 4151 }; 4152 4153 struct mlx5_ifc_query_nic_vport_context_out_bits { 4154 u8 status[0x8]; 4155 u8 reserved_0[0x18]; 4156 4157 u8 syndrome[0x20]; 4158 4159 u8 reserved_1[0x40]; 4160 4161 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4162 }; 4163 4164 struct mlx5_ifc_query_nic_vport_context_in_bits { 4165 u8 opcode[0x10]; 4166 u8 reserved_0[0x10]; 4167 4168 u8 reserved_1[0x10]; 4169 u8 op_mod[0x10]; 4170 4171 u8 other_vport[0x1]; 4172 u8 reserved_2[0xf]; 4173 u8 vport_number[0x10]; 4174 4175 u8 reserved_3[0x5]; 4176 u8 allowed_list_type[0x3]; 4177 u8 reserved_4[0x18]; 4178 }; 4179 4180 struct mlx5_ifc_query_mkey_out_bits { 4181 u8 status[0x8]; 4182 u8 reserved_0[0x18]; 4183 4184 u8 syndrome[0x20]; 4185 4186 u8 reserved_1[0x40]; 4187 4188 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4189 4190 u8 reserved_2[0x600]; 4191 4192 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4193 4194 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4195 }; 4196 4197 struct mlx5_ifc_query_mkey_in_bits { 4198 u8 opcode[0x10]; 4199 u8 reserved_0[0x10]; 4200 4201 u8 reserved_1[0x10]; 4202 u8 op_mod[0x10]; 4203 4204 u8 reserved_2[0x8]; 4205 u8 mkey_index[0x18]; 4206 4207 u8 pg_access[0x1]; 4208 u8 reserved_3[0x1f]; 4209 }; 4210 4211 struct mlx5_ifc_query_mad_demux_out_bits { 4212 u8 status[0x8]; 4213 u8 reserved_0[0x18]; 4214 4215 u8 syndrome[0x20]; 4216 4217 u8 reserved_1[0x40]; 4218 4219 u8 mad_dumux_parameters_block[0x20]; 4220 }; 4221 4222 struct mlx5_ifc_query_mad_demux_in_bits { 4223 u8 opcode[0x10]; 4224 u8 reserved_0[0x10]; 4225 4226 u8 reserved_1[0x10]; 4227 u8 op_mod[0x10]; 4228 4229 u8 reserved_2[0x40]; 4230 }; 4231 4232 struct mlx5_ifc_query_l2_table_entry_out_bits { 4233 u8 status[0x8]; 4234 u8 reserved_0[0x18]; 4235 4236 u8 syndrome[0x20]; 4237 4238 u8 reserved_1[0xa0]; 4239 4240 u8 reserved_2[0x13]; 4241 u8 vlan_valid[0x1]; 4242 u8 vlan[0xc]; 4243 4244 struct mlx5_ifc_mac_address_layout_bits mac_address; 4245 4246 u8 reserved_3[0xc0]; 4247 }; 4248 4249 struct mlx5_ifc_query_l2_table_entry_in_bits { 4250 u8 opcode[0x10]; 4251 u8 reserved_0[0x10]; 4252 4253 u8 reserved_1[0x10]; 4254 u8 op_mod[0x10]; 4255 4256 u8 reserved_2[0x60]; 4257 4258 u8 reserved_3[0x8]; 4259 u8 table_index[0x18]; 4260 4261 u8 reserved_4[0x140]; 4262 }; 4263 4264 struct mlx5_ifc_query_issi_out_bits { 4265 u8 status[0x8]; 4266 u8 reserved_0[0x18]; 4267 4268 u8 syndrome[0x20]; 4269 4270 u8 reserved_1[0x10]; 4271 u8 current_issi[0x10]; 4272 4273 u8 reserved_2[0xa0]; 4274 4275 u8 supported_issi_reserved[76][0x8]; 4276 u8 supported_issi_dw0[0x20]; 4277 }; 4278 4279 struct mlx5_ifc_query_issi_in_bits { 4280 u8 opcode[0x10]; 4281 u8 reserved_0[0x10]; 4282 4283 u8 reserved_1[0x10]; 4284 u8 op_mod[0x10]; 4285 4286 u8 reserved_2[0x40]; 4287 }; 4288 4289 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4290 u8 status[0x8]; 4291 u8 reserved_0[0x18]; 4292 4293 u8 syndrome[0x20]; 4294 4295 u8 reserved_1[0x40]; 4296 4297 struct mlx5_ifc_pkey_bits pkey[0]; 4298 }; 4299 4300 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4301 u8 opcode[0x10]; 4302 u8 reserved_0[0x10]; 4303 4304 u8 reserved_1[0x10]; 4305 u8 op_mod[0x10]; 4306 4307 u8 other_vport[0x1]; 4308 u8 reserved_2[0xb]; 4309 u8 port_num[0x4]; 4310 u8 vport_number[0x10]; 4311 4312 u8 reserved_3[0x10]; 4313 u8 pkey_index[0x10]; 4314 }; 4315 4316 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4317 u8 status[0x8]; 4318 u8 reserved_0[0x18]; 4319 4320 u8 syndrome[0x20]; 4321 4322 u8 reserved_1[0x20]; 4323 4324 u8 gids_num[0x10]; 4325 u8 reserved_2[0x10]; 4326 4327 struct mlx5_ifc_array128_auto_bits gid[0]; 4328 }; 4329 4330 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4331 u8 opcode[0x10]; 4332 u8 reserved_0[0x10]; 4333 4334 u8 reserved_1[0x10]; 4335 u8 op_mod[0x10]; 4336 4337 u8 other_vport[0x1]; 4338 u8 reserved_2[0xb]; 4339 u8 port_num[0x4]; 4340 u8 vport_number[0x10]; 4341 4342 u8 reserved_3[0x10]; 4343 u8 gid_index[0x10]; 4344 }; 4345 4346 struct mlx5_ifc_query_hca_vport_context_out_bits { 4347 u8 status[0x8]; 4348 u8 reserved_0[0x18]; 4349 4350 u8 syndrome[0x20]; 4351 4352 u8 reserved_1[0x40]; 4353 4354 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4355 }; 4356 4357 struct mlx5_ifc_query_hca_vport_context_in_bits { 4358 u8 opcode[0x10]; 4359 u8 reserved_0[0x10]; 4360 4361 u8 reserved_1[0x10]; 4362 u8 op_mod[0x10]; 4363 4364 u8 other_vport[0x1]; 4365 u8 reserved_2[0xb]; 4366 u8 port_num[0x4]; 4367 u8 vport_number[0x10]; 4368 4369 u8 reserved_3[0x20]; 4370 }; 4371 4372 struct mlx5_ifc_query_hca_cap_out_bits { 4373 u8 status[0x8]; 4374 u8 reserved_0[0x18]; 4375 4376 u8 syndrome[0x20]; 4377 4378 u8 reserved_1[0x40]; 4379 4380 union mlx5_ifc_hca_cap_union_bits capability; 4381 }; 4382 4383 struct mlx5_ifc_query_hca_cap_in_bits { 4384 u8 opcode[0x10]; 4385 u8 reserved_0[0x10]; 4386 4387 u8 reserved_1[0x10]; 4388 u8 op_mod[0x10]; 4389 4390 u8 reserved_2[0x40]; 4391 }; 4392 4393 struct mlx5_ifc_query_flow_table_out_bits { 4394 u8 status[0x8]; 4395 u8 reserved_0[0x18]; 4396 4397 u8 syndrome[0x20]; 4398 4399 u8 reserved_1[0x80]; 4400 4401 u8 reserved_2[0x8]; 4402 u8 level[0x8]; 4403 u8 reserved_3[0x8]; 4404 u8 log_size[0x8]; 4405 4406 u8 reserved_4[0x120]; 4407 }; 4408 4409 struct mlx5_ifc_query_flow_table_in_bits { 4410 u8 opcode[0x10]; 4411 u8 reserved_0[0x10]; 4412 4413 u8 reserved_1[0x10]; 4414 u8 op_mod[0x10]; 4415 4416 u8 other_vport[0x1]; 4417 u8 reserved_2[0xf]; 4418 u8 vport_number[0x10]; 4419 4420 u8 reserved_3[0x20]; 4421 4422 u8 table_type[0x8]; 4423 u8 reserved_4[0x18]; 4424 4425 u8 reserved_5[0x8]; 4426 u8 table_id[0x18]; 4427 4428 u8 reserved_6[0x140]; 4429 }; 4430 4431 struct mlx5_ifc_query_fte_out_bits { 4432 u8 status[0x8]; 4433 u8 reserved_0[0x18]; 4434 4435 u8 syndrome[0x20]; 4436 4437 u8 reserved_1[0x1c0]; 4438 4439 struct mlx5_ifc_flow_context_bits flow_context; 4440 }; 4441 4442 struct mlx5_ifc_query_fte_in_bits { 4443 u8 opcode[0x10]; 4444 u8 reserved_0[0x10]; 4445 4446 u8 reserved_1[0x10]; 4447 u8 op_mod[0x10]; 4448 4449 u8 other_vport[0x1]; 4450 u8 reserved_2[0xf]; 4451 u8 vport_number[0x10]; 4452 4453 u8 reserved_3[0x20]; 4454 4455 u8 table_type[0x8]; 4456 u8 reserved_4[0x18]; 4457 4458 u8 reserved_5[0x8]; 4459 u8 table_id[0x18]; 4460 4461 u8 reserved_6[0x40]; 4462 4463 u8 flow_index[0x20]; 4464 4465 u8 reserved_7[0xe0]; 4466 }; 4467 4468 enum { 4469 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4470 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4471 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4472 }; 4473 4474 struct mlx5_ifc_query_flow_group_out_bits { 4475 u8 status[0x8]; 4476 u8 reserved_0[0x18]; 4477 4478 u8 syndrome[0x20]; 4479 4480 u8 reserved_1[0xa0]; 4481 4482 u8 start_flow_index[0x20]; 4483 4484 u8 reserved_2[0x20]; 4485 4486 u8 end_flow_index[0x20]; 4487 4488 u8 reserved_3[0xa0]; 4489 4490 u8 reserved_4[0x18]; 4491 u8 match_criteria_enable[0x8]; 4492 4493 struct mlx5_ifc_fte_match_param_bits match_criteria; 4494 4495 u8 reserved_5[0xe00]; 4496 }; 4497 4498 struct mlx5_ifc_query_flow_group_in_bits { 4499 u8 opcode[0x10]; 4500 u8 reserved_0[0x10]; 4501 4502 u8 reserved_1[0x10]; 4503 u8 op_mod[0x10]; 4504 4505 u8 other_vport[0x1]; 4506 u8 reserved_2[0xf]; 4507 u8 vport_number[0x10]; 4508 4509 u8 reserved_3[0x20]; 4510 4511 u8 table_type[0x8]; 4512 u8 reserved_4[0x18]; 4513 4514 u8 reserved_5[0x8]; 4515 u8 table_id[0x18]; 4516 4517 u8 group_id[0x20]; 4518 4519 u8 reserved_6[0x120]; 4520 }; 4521 4522 struct mlx5_ifc_query_flow_counter_out_bits { 4523 u8 status[0x8]; 4524 u8 reserved_0[0x18]; 4525 4526 u8 syndrome[0x20]; 4527 4528 u8 reserved_1[0x40]; 4529 4530 struct mlx5_ifc_traffic_counter_bits flow_statistics; 4531 4532 u8 reserved_2[0x700]; 4533 }; 4534 4535 struct mlx5_ifc_query_flow_counter_in_bits { 4536 u8 opcode[0x10]; 4537 u8 reserved_0[0x10]; 4538 4539 u8 reserved_1[0x10]; 4540 u8 op_mod[0x10]; 4541 4542 u8 reserved_2[0x80]; 4543 4544 u8 clear[0x1]; 4545 u8 reserved_3[0x1f]; 4546 4547 u8 reserved_4[0x10]; 4548 u8 flow_counter_id[0x10]; 4549 }; 4550 4551 struct mlx5_ifc_query_esw_vport_context_out_bits { 4552 u8 status[0x8]; 4553 u8 reserved_0[0x18]; 4554 4555 u8 syndrome[0x20]; 4556 4557 u8 reserved_1[0x40]; 4558 4559 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4560 }; 4561 4562 struct mlx5_ifc_query_esw_vport_context_in_bits { 4563 u8 opcode[0x10]; 4564 u8 reserved_0[0x10]; 4565 4566 u8 reserved_1[0x10]; 4567 u8 op_mod[0x10]; 4568 4569 u8 other_vport[0x1]; 4570 u8 reserved_2[0xf]; 4571 u8 vport_number[0x10]; 4572 4573 u8 reserved_3[0x20]; 4574 }; 4575 4576 struct mlx5_ifc_query_eq_out_bits { 4577 u8 status[0x8]; 4578 u8 reserved_0[0x18]; 4579 4580 u8 syndrome[0x20]; 4581 4582 u8 reserved_1[0x40]; 4583 4584 struct mlx5_ifc_eqc_bits eq_context_entry; 4585 4586 u8 reserved_2[0x40]; 4587 4588 u8 event_bitmask[0x40]; 4589 4590 u8 reserved_3[0x580]; 4591 4592 u8 pas[0][0x40]; 4593 }; 4594 4595 struct mlx5_ifc_query_eq_in_bits { 4596 u8 opcode[0x10]; 4597 u8 reserved_0[0x10]; 4598 4599 u8 reserved_1[0x10]; 4600 u8 op_mod[0x10]; 4601 4602 u8 reserved_2[0x18]; 4603 u8 eq_number[0x8]; 4604 4605 u8 reserved_3[0x20]; 4606 }; 4607 4608 struct mlx5_ifc_query_dct_out_bits { 4609 u8 status[0x8]; 4610 u8 reserved_0[0x18]; 4611 4612 u8 syndrome[0x20]; 4613 4614 u8 reserved_1[0x40]; 4615 4616 struct mlx5_ifc_dctc_bits dct_context_entry; 4617 4618 u8 reserved_2[0x180]; 4619 }; 4620 4621 struct mlx5_ifc_query_dct_in_bits { 4622 u8 opcode[0x10]; 4623 u8 reserved_0[0x10]; 4624 4625 u8 reserved_1[0x10]; 4626 u8 op_mod[0x10]; 4627 4628 u8 reserved_2[0x8]; 4629 u8 dctn[0x18]; 4630 4631 u8 reserved_3[0x20]; 4632 }; 4633 4634 struct mlx5_ifc_query_dc_cnak_trace_out_bits { 4635 u8 status[0x8]; 4636 u8 reserved_0[0x18]; 4637 4638 u8 syndrome[0x20]; 4639 4640 u8 enable[0x1]; 4641 u8 reserved_1[0x1f]; 4642 4643 u8 reserved_2[0x160]; 4644 4645 struct mlx5_ifc_cmd_pas_bits pas; 4646 }; 4647 4648 struct mlx5_ifc_query_dc_cnak_trace_in_bits { 4649 u8 opcode[0x10]; 4650 u8 reserved_0[0x10]; 4651 4652 u8 reserved_1[0x10]; 4653 u8 op_mod[0x10]; 4654 4655 u8 reserved_2[0x40]; 4656 }; 4657 4658 struct mlx5_ifc_query_cq_out_bits { 4659 u8 status[0x8]; 4660 u8 reserved_0[0x18]; 4661 4662 u8 syndrome[0x20]; 4663 4664 u8 reserved_1[0x40]; 4665 4666 struct mlx5_ifc_cqc_bits cq_context; 4667 4668 u8 reserved_2[0x600]; 4669 4670 u8 pas[0][0x40]; 4671 }; 4672 4673 struct mlx5_ifc_query_cq_in_bits { 4674 u8 opcode[0x10]; 4675 u8 reserved_0[0x10]; 4676 4677 u8 reserved_1[0x10]; 4678 u8 op_mod[0x10]; 4679 4680 u8 reserved_2[0x8]; 4681 u8 cqn[0x18]; 4682 4683 u8 reserved_3[0x20]; 4684 }; 4685 4686 struct mlx5_ifc_query_cong_status_out_bits { 4687 u8 status[0x8]; 4688 u8 reserved_0[0x18]; 4689 4690 u8 syndrome[0x20]; 4691 4692 u8 reserved_1[0x20]; 4693 4694 u8 enable[0x1]; 4695 u8 tag_enable[0x1]; 4696 u8 reserved_2[0x1e]; 4697 }; 4698 4699 struct mlx5_ifc_query_cong_status_in_bits { 4700 u8 opcode[0x10]; 4701 u8 reserved_0[0x10]; 4702 4703 u8 reserved_1[0x10]; 4704 u8 op_mod[0x10]; 4705 4706 u8 reserved_2[0x18]; 4707 u8 priority[0x4]; 4708 u8 cong_protocol[0x4]; 4709 4710 u8 reserved_3[0x20]; 4711 }; 4712 4713 struct mlx5_ifc_query_cong_statistics_out_bits { 4714 u8 status[0x8]; 4715 u8 reserved_0[0x18]; 4716 4717 u8 syndrome[0x20]; 4718 4719 u8 reserved_1[0x40]; 4720 4721 u8 cur_flows[0x20]; 4722 4723 u8 sum_flows[0x20]; 4724 4725 u8 cnp_ignored_high[0x20]; 4726 4727 u8 cnp_ignored_low[0x20]; 4728 4729 u8 cnp_handled_high[0x20]; 4730 4731 u8 cnp_handled_low[0x20]; 4732 4733 u8 reserved_2[0x100]; 4734 4735 u8 time_stamp_high[0x20]; 4736 4737 u8 time_stamp_low[0x20]; 4738 4739 u8 accumulators_period[0x20]; 4740 4741 u8 ecn_marked_roce_packets_high[0x20]; 4742 4743 u8 ecn_marked_roce_packets_low[0x20]; 4744 4745 u8 cnps_sent_high[0x20]; 4746 4747 u8 cnps_sent_low[0x20]; 4748 4749 u8 reserved_3[0x560]; 4750 }; 4751 4752 struct mlx5_ifc_query_cong_statistics_in_bits { 4753 u8 opcode[0x10]; 4754 u8 reserved_0[0x10]; 4755 4756 u8 reserved_1[0x10]; 4757 u8 op_mod[0x10]; 4758 4759 u8 clear[0x1]; 4760 u8 reserved_2[0x1f]; 4761 4762 u8 reserved_3[0x20]; 4763 }; 4764 4765 struct mlx5_ifc_query_cong_params_out_bits { 4766 u8 status[0x8]; 4767 u8 reserved_0[0x18]; 4768 4769 u8 syndrome[0x20]; 4770 4771 u8 reserved_1[0x40]; 4772 4773 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4774 }; 4775 4776 struct mlx5_ifc_query_cong_params_in_bits { 4777 u8 opcode[0x10]; 4778 u8 reserved_0[0x10]; 4779 4780 u8 reserved_1[0x10]; 4781 u8 op_mod[0x10]; 4782 4783 u8 reserved_2[0x1c]; 4784 u8 cong_protocol[0x4]; 4785 4786 u8 reserved_3[0x20]; 4787 }; 4788 4789 struct mlx5_ifc_query_burst_size_out_bits { 4790 u8 status[0x8]; 4791 u8 reserved_0[0x18]; 4792 4793 u8 syndrome[0x20]; 4794 4795 u8 reserved_1[0x20]; 4796 4797 u8 reserved_2[0x9]; 4798 u8 device_burst_size[0x17]; 4799 }; 4800 4801 struct mlx5_ifc_query_burst_size_in_bits { 4802 u8 opcode[0x10]; 4803 u8 reserved_0[0x10]; 4804 4805 u8 reserved_1[0x10]; 4806 u8 op_mod[0x10]; 4807 4808 u8 reserved_2[0x40]; 4809 }; 4810 4811 struct mlx5_ifc_query_adapter_out_bits { 4812 u8 status[0x8]; 4813 u8 reserved_0[0x18]; 4814 4815 u8 syndrome[0x20]; 4816 4817 u8 reserved_1[0x40]; 4818 4819 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 4820 }; 4821 4822 struct mlx5_ifc_query_adapter_in_bits { 4823 u8 opcode[0x10]; 4824 u8 reserved_0[0x10]; 4825 4826 u8 reserved_1[0x10]; 4827 u8 op_mod[0x10]; 4828 4829 u8 reserved_2[0x40]; 4830 }; 4831 4832 struct mlx5_ifc_qp_2rst_out_bits { 4833 u8 status[0x8]; 4834 u8 reserved_0[0x18]; 4835 4836 u8 syndrome[0x20]; 4837 4838 u8 reserved_1[0x40]; 4839 }; 4840 4841 struct mlx5_ifc_qp_2rst_in_bits { 4842 u8 opcode[0x10]; 4843 u8 reserved_0[0x10]; 4844 4845 u8 reserved_1[0x10]; 4846 u8 op_mod[0x10]; 4847 4848 u8 reserved_2[0x8]; 4849 u8 qpn[0x18]; 4850 4851 u8 reserved_3[0x20]; 4852 }; 4853 4854 struct mlx5_ifc_qp_2err_out_bits { 4855 u8 status[0x8]; 4856 u8 reserved_0[0x18]; 4857 4858 u8 syndrome[0x20]; 4859 4860 u8 reserved_1[0x40]; 4861 }; 4862 4863 struct mlx5_ifc_qp_2err_in_bits { 4864 u8 opcode[0x10]; 4865 u8 reserved_0[0x10]; 4866 4867 u8 reserved_1[0x10]; 4868 u8 op_mod[0x10]; 4869 4870 u8 reserved_2[0x8]; 4871 u8 qpn[0x18]; 4872 4873 u8 reserved_3[0x20]; 4874 }; 4875 4876 struct mlx5_ifc_para_vport_element_bits { 4877 u8 reserved_at_0[0xc]; 4878 u8 traffic_class[0x4]; 4879 u8 qos_para_vport_number[0x10]; 4880 }; 4881 4882 struct mlx5_ifc_page_fault_resume_out_bits { 4883 u8 status[0x8]; 4884 u8 reserved_0[0x18]; 4885 4886 u8 syndrome[0x20]; 4887 4888 u8 reserved_1[0x40]; 4889 }; 4890 4891 struct mlx5_ifc_page_fault_resume_in_bits { 4892 u8 opcode[0x10]; 4893 u8 reserved_0[0x10]; 4894 4895 u8 reserved_1[0x10]; 4896 u8 op_mod[0x10]; 4897 4898 u8 error[0x1]; 4899 u8 reserved_2[0x4]; 4900 u8 rdma[0x1]; 4901 u8 read_write[0x1]; 4902 u8 req_res[0x1]; 4903 u8 qpn[0x18]; 4904 4905 u8 reserved_3[0x20]; 4906 }; 4907 4908 struct mlx5_ifc_nop_out_bits { 4909 u8 status[0x8]; 4910 u8 reserved_0[0x18]; 4911 4912 u8 syndrome[0x20]; 4913 4914 u8 reserved_1[0x40]; 4915 }; 4916 4917 struct mlx5_ifc_nop_in_bits { 4918 u8 opcode[0x10]; 4919 u8 reserved_0[0x10]; 4920 4921 u8 reserved_1[0x10]; 4922 u8 op_mod[0x10]; 4923 4924 u8 reserved_2[0x40]; 4925 }; 4926 4927 struct mlx5_ifc_modify_vport_state_out_bits { 4928 u8 status[0x8]; 4929 u8 reserved_0[0x18]; 4930 4931 u8 syndrome[0x20]; 4932 4933 u8 reserved_1[0x40]; 4934 }; 4935 4936 enum { 4937 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 4938 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 4939 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 4940 }; 4941 4942 enum { 4943 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 4944 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 4945 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 4946 }; 4947 4948 struct mlx5_ifc_modify_vport_state_in_bits { 4949 u8 opcode[0x10]; 4950 u8 reserved_0[0x10]; 4951 4952 u8 reserved_1[0x10]; 4953 u8 op_mod[0x10]; 4954 4955 u8 other_vport[0x1]; 4956 u8 reserved_2[0xf]; 4957 u8 vport_number[0x10]; 4958 4959 u8 reserved_3[0x18]; 4960 u8 admin_state[0x4]; 4961 u8 reserved_4[0x4]; 4962 }; 4963 4964 struct mlx5_ifc_modify_tis_out_bits { 4965 u8 status[0x8]; 4966 u8 reserved_0[0x18]; 4967 4968 u8 syndrome[0x20]; 4969 4970 u8 reserved_1[0x40]; 4971 }; 4972 4973 struct mlx5_ifc_modify_tis_in_bits { 4974 u8 opcode[0x10]; 4975 u8 reserved_0[0x10]; 4976 4977 u8 reserved_1[0x10]; 4978 u8 op_mod[0x10]; 4979 4980 u8 reserved_2[0x8]; 4981 u8 tisn[0x18]; 4982 4983 u8 reserved_3[0x20]; 4984 4985 u8 modify_bitmask[0x40]; 4986 4987 u8 reserved_4[0x40]; 4988 4989 struct mlx5_ifc_tisc_bits ctx; 4990 }; 4991 4992 struct mlx5_ifc_modify_tir_out_bits { 4993 u8 status[0x8]; 4994 u8 reserved_0[0x18]; 4995 4996 u8 syndrome[0x20]; 4997 4998 u8 reserved_1[0x40]; 4999 }; 5000 5001 enum 5002 { 5003 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5004 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5005 }; 5006 5007 struct mlx5_ifc_modify_tir_in_bits { 5008 u8 opcode[0x10]; 5009 u8 reserved_0[0x10]; 5010 5011 u8 reserved_1[0x10]; 5012 u8 op_mod[0x10]; 5013 5014 u8 reserved_2[0x8]; 5015 u8 tirn[0x18]; 5016 5017 u8 reserved_3[0x20]; 5018 5019 u8 modify_bitmask[0x40]; 5020 5021 u8 reserved_4[0x40]; 5022 5023 struct mlx5_ifc_tirc_bits tir_context; 5024 }; 5025 5026 struct mlx5_ifc_modify_sq_out_bits { 5027 u8 status[0x8]; 5028 u8 reserved_0[0x18]; 5029 5030 u8 syndrome[0x20]; 5031 5032 u8 reserved_1[0x40]; 5033 }; 5034 5035 struct mlx5_ifc_modify_sq_in_bits { 5036 u8 opcode[0x10]; 5037 u8 reserved_0[0x10]; 5038 5039 u8 reserved_1[0x10]; 5040 u8 op_mod[0x10]; 5041 5042 u8 sq_state[0x4]; 5043 u8 reserved_2[0x4]; 5044 u8 sqn[0x18]; 5045 5046 u8 reserved_3[0x20]; 5047 5048 u8 modify_bitmask[0x40]; 5049 5050 u8 reserved_4[0x40]; 5051 5052 struct mlx5_ifc_sqc_bits ctx; 5053 }; 5054 5055 struct mlx5_ifc_modify_scheduling_element_out_bits { 5056 u8 status[0x8]; 5057 u8 reserved_at_8[0x18]; 5058 5059 u8 syndrome[0x20]; 5060 5061 u8 reserved_at_40[0x1c0]; 5062 }; 5063 5064 enum { 5065 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5066 }; 5067 5068 enum { 5069 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5070 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5071 }; 5072 5073 struct mlx5_ifc_modify_scheduling_element_in_bits { 5074 u8 opcode[0x10]; 5075 u8 reserved_at_10[0x10]; 5076 5077 u8 reserved_at_20[0x10]; 5078 u8 op_mod[0x10]; 5079 5080 u8 scheduling_hierarchy[0x8]; 5081 u8 reserved_at_48[0x18]; 5082 5083 u8 scheduling_element_id[0x20]; 5084 5085 u8 reserved_at_80[0x20]; 5086 5087 u8 modify_bitmask[0x20]; 5088 5089 u8 reserved_at_c0[0x40]; 5090 5091 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5092 5093 u8 reserved_at_300[0x100]; 5094 }; 5095 5096 struct mlx5_ifc_modify_rqt_out_bits { 5097 u8 status[0x8]; 5098 u8 reserved_0[0x18]; 5099 5100 u8 syndrome[0x20]; 5101 5102 u8 reserved_1[0x40]; 5103 }; 5104 5105 struct mlx5_ifc_modify_rqt_in_bits { 5106 u8 opcode[0x10]; 5107 u8 reserved_0[0x10]; 5108 5109 u8 reserved_1[0x10]; 5110 u8 op_mod[0x10]; 5111 5112 u8 reserved_2[0x8]; 5113 u8 rqtn[0x18]; 5114 5115 u8 reserved_3[0x20]; 5116 5117 u8 modify_bitmask[0x40]; 5118 5119 u8 reserved_4[0x40]; 5120 5121 struct mlx5_ifc_rqtc_bits ctx; 5122 }; 5123 5124 struct mlx5_ifc_modify_rq_out_bits { 5125 u8 status[0x8]; 5126 u8 reserved_0[0x18]; 5127 5128 u8 syndrome[0x20]; 5129 5130 u8 reserved_1[0x40]; 5131 }; 5132 5133 struct mlx5_ifc_rq_bitmask_bits { 5134 u8 reserved[0x20]; 5135 5136 u8 reserved1[0x1e]; 5137 u8 vlan_strip_disable[0x1]; 5138 u8 reserved2[0x1]; 5139 }; 5140 5141 struct mlx5_ifc_modify_rq_in_bits { 5142 u8 opcode[0x10]; 5143 u8 reserved_0[0x10]; 5144 5145 u8 reserved_1[0x10]; 5146 u8 op_mod[0x10]; 5147 5148 u8 rq_state[0x4]; 5149 u8 reserved_2[0x4]; 5150 u8 rqn[0x18]; 5151 5152 u8 reserved_3[0x20]; 5153 5154 struct mlx5_ifc_rq_bitmask_bits bitmask; 5155 5156 u8 reserved_4[0x40]; 5157 5158 struct mlx5_ifc_rqc_bits ctx; 5159 }; 5160 5161 struct mlx5_ifc_modify_rmp_out_bits { 5162 u8 status[0x8]; 5163 u8 reserved_0[0x18]; 5164 5165 u8 syndrome[0x20]; 5166 5167 u8 reserved_1[0x40]; 5168 }; 5169 5170 struct mlx5_ifc_rmp_bitmask_bits { 5171 u8 reserved[0x20]; 5172 5173 u8 reserved1[0x1f]; 5174 u8 lwm[0x1]; 5175 }; 5176 5177 struct mlx5_ifc_modify_rmp_in_bits { 5178 u8 opcode[0x10]; 5179 u8 reserved_0[0x10]; 5180 5181 u8 reserved_1[0x10]; 5182 u8 op_mod[0x10]; 5183 5184 u8 rmp_state[0x4]; 5185 u8 reserved_2[0x4]; 5186 u8 rmpn[0x18]; 5187 5188 u8 reserved_3[0x20]; 5189 5190 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5191 5192 u8 reserved_4[0x40]; 5193 5194 struct mlx5_ifc_rmpc_bits ctx; 5195 }; 5196 5197 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5198 u8 status[0x8]; 5199 u8 reserved_0[0x18]; 5200 5201 u8 syndrome[0x20]; 5202 5203 u8 reserved_1[0x40]; 5204 }; 5205 5206 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5207 u8 reserved_0[0x16]; 5208 u8 node_guid[0x1]; 5209 u8 port_guid[0x1]; 5210 u8 min_wqe_inline_mode[0x1]; 5211 u8 mtu[0x1]; 5212 u8 change_event[0x1]; 5213 u8 promisc[0x1]; 5214 u8 permanent_address[0x1]; 5215 u8 addresses_list[0x1]; 5216 u8 roce_en[0x1]; 5217 u8 reserved_1[0x1]; 5218 }; 5219 5220 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5221 u8 opcode[0x10]; 5222 u8 reserved_0[0x10]; 5223 5224 u8 reserved_1[0x10]; 5225 u8 op_mod[0x10]; 5226 5227 u8 other_vport[0x1]; 5228 u8 reserved_2[0xf]; 5229 u8 vport_number[0x10]; 5230 5231 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5232 5233 u8 reserved_3[0x780]; 5234 5235 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5236 }; 5237 5238 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5239 u8 status[0x8]; 5240 u8 reserved_0[0x18]; 5241 5242 u8 syndrome[0x20]; 5243 5244 u8 reserved_1[0x40]; 5245 }; 5246 5247 struct mlx5_ifc_grh_bits { 5248 u8 ip_version[4]; 5249 u8 traffic_class[8]; 5250 u8 flow_label[20]; 5251 u8 payload_length[16]; 5252 u8 next_header[8]; 5253 u8 hop_limit[8]; 5254 u8 sgid[128]; 5255 u8 dgid[128]; 5256 }; 5257 5258 struct mlx5_ifc_bth_bits { 5259 u8 opcode[8]; 5260 u8 se[1]; 5261 u8 migreq[1]; 5262 u8 pad_count[2]; 5263 u8 tver[4]; 5264 u8 p_key[16]; 5265 u8 reserved8[8]; 5266 u8 dest_qp[24]; 5267 u8 ack_req[1]; 5268 u8 reserved7[7]; 5269 u8 psn[24]; 5270 }; 5271 5272 struct mlx5_ifc_aeth_bits { 5273 u8 syndrome[8]; 5274 u8 msn[24]; 5275 }; 5276 5277 struct mlx5_ifc_dceth_bits { 5278 u8 reserved0[8]; 5279 u8 session_id[24]; 5280 u8 reserved1[8]; 5281 u8 dci_dct[24]; 5282 }; 5283 5284 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5285 u8 opcode[0x10]; 5286 u8 reserved_0[0x10]; 5287 5288 u8 reserved_1[0x10]; 5289 u8 op_mod[0x10]; 5290 5291 u8 other_vport[0x1]; 5292 u8 reserved_2[0xb]; 5293 u8 port_num[0x4]; 5294 u8 vport_number[0x10]; 5295 5296 u8 reserved_3[0x20]; 5297 5298 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5299 }; 5300 5301 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5302 u8 status[0x8]; 5303 u8 reserved_0[0x18]; 5304 5305 u8 syndrome[0x20]; 5306 5307 u8 reserved_1[0x40]; 5308 }; 5309 5310 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5311 u8 reserved[0x1c]; 5312 u8 vport_cvlan_insert[0x1]; 5313 u8 vport_svlan_insert[0x1]; 5314 u8 vport_cvlan_strip[0x1]; 5315 u8 vport_svlan_strip[0x1]; 5316 }; 5317 5318 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5319 u8 opcode[0x10]; 5320 u8 reserved_0[0x10]; 5321 5322 u8 reserved_1[0x10]; 5323 u8 op_mod[0x10]; 5324 5325 u8 other_vport[0x1]; 5326 u8 reserved_2[0xf]; 5327 u8 vport_number[0x10]; 5328 5329 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5330 5331 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5332 }; 5333 5334 struct mlx5_ifc_modify_cq_out_bits { 5335 u8 status[0x8]; 5336 u8 reserved_0[0x18]; 5337 5338 u8 syndrome[0x20]; 5339 5340 u8 reserved_1[0x40]; 5341 }; 5342 5343 enum { 5344 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5345 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5346 }; 5347 5348 struct mlx5_ifc_modify_cq_in_bits { 5349 u8 opcode[0x10]; 5350 u8 reserved_0[0x10]; 5351 5352 u8 reserved_1[0x10]; 5353 u8 op_mod[0x10]; 5354 5355 u8 reserved_2[0x8]; 5356 u8 cqn[0x18]; 5357 5358 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5359 5360 struct mlx5_ifc_cqc_bits cq_context; 5361 5362 u8 reserved_3[0x600]; 5363 5364 u8 pas[0][0x40]; 5365 }; 5366 5367 struct mlx5_ifc_modify_cong_status_out_bits { 5368 u8 status[0x8]; 5369 u8 reserved_0[0x18]; 5370 5371 u8 syndrome[0x20]; 5372 5373 u8 reserved_1[0x40]; 5374 }; 5375 5376 struct mlx5_ifc_modify_cong_status_in_bits { 5377 u8 opcode[0x10]; 5378 u8 reserved_0[0x10]; 5379 5380 u8 reserved_1[0x10]; 5381 u8 op_mod[0x10]; 5382 5383 u8 reserved_2[0x18]; 5384 u8 priority[0x4]; 5385 u8 cong_protocol[0x4]; 5386 5387 u8 enable[0x1]; 5388 u8 tag_enable[0x1]; 5389 u8 reserved_3[0x1e]; 5390 }; 5391 5392 struct mlx5_ifc_modify_cong_params_out_bits { 5393 u8 status[0x8]; 5394 u8 reserved_0[0x18]; 5395 5396 u8 syndrome[0x20]; 5397 5398 u8 reserved_1[0x40]; 5399 }; 5400 5401 struct mlx5_ifc_modify_cong_params_in_bits { 5402 u8 opcode[0x10]; 5403 u8 reserved_0[0x10]; 5404 5405 u8 reserved_1[0x10]; 5406 u8 op_mod[0x10]; 5407 5408 u8 reserved_2[0x1c]; 5409 u8 cong_protocol[0x4]; 5410 5411 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5412 5413 u8 reserved_3[0x80]; 5414 5415 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5416 }; 5417 5418 struct mlx5_ifc_manage_pages_out_bits { 5419 u8 status[0x8]; 5420 u8 reserved_0[0x18]; 5421 5422 u8 syndrome[0x20]; 5423 5424 u8 output_num_entries[0x20]; 5425 5426 u8 reserved_1[0x20]; 5427 5428 u8 pas[0][0x40]; 5429 }; 5430 5431 enum { 5432 MLX5_PAGES_CANT_GIVE = 0x0, 5433 MLX5_PAGES_GIVE = 0x1, 5434 MLX5_PAGES_TAKE = 0x2, 5435 }; 5436 5437 struct mlx5_ifc_manage_pages_in_bits { 5438 u8 opcode[0x10]; 5439 u8 reserved_0[0x10]; 5440 5441 u8 reserved_1[0x10]; 5442 u8 op_mod[0x10]; 5443 5444 u8 reserved_2[0x10]; 5445 u8 function_id[0x10]; 5446 5447 u8 input_num_entries[0x20]; 5448 5449 u8 pas[0][0x40]; 5450 }; 5451 5452 struct mlx5_ifc_mad_ifc_out_bits { 5453 u8 status[0x8]; 5454 u8 reserved_0[0x18]; 5455 5456 u8 syndrome[0x20]; 5457 5458 u8 reserved_1[0x40]; 5459 5460 u8 response_mad_packet[256][0x8]; 5461 }; 5462 5463 struct mlx5_ifc_mad_ifc_in_bits { 5464 u8 opcode[0x10]; 5465 u8 reserved_0[0x10]; 5466 5467 u8 reserved_1[0x10]; 5468 u8 op_mod[0x10]; 5469 5470 u8 remote_lid[0x10]; 5471 u8 reserved_2[0x8]; 5472 u8 port[0x8]; 5473 5474 u8 reserved_3[0x20]; 5475 5476 u8 mad[256][0x8]; 5477 }; 5478 5479 struct mlx5_ifc_init_hca_out_bits { 5480 u8 status[0x8]; 5481 u8 reserved_0[0x18]; 5482 5483 u8 syndrome[0x20]; 5484 5485 u8 reserved_1[0x40]; 5486 }; 5487 5488 enum { 5489 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 5490 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 5491 }; 5492 5493 struct mlx5_ifc_init_hca_in_bits { 5494 u8 opcode[0x10]; 5495 u8 reserved_0[0x10]; 5496 5497 u8 reserved_1[0x10]; 5498 u8 op_mod[0x10]; 5499 5500 u8 reserved_2[0x40]; 5501 }; 5502 5503 struct mlx5_ifc_init2rtr_qp_out_bits { 5504 u8 status[0x8]; 5505 u8 reserved_0[0x18]; 5506 5507 u8 syndrome[0x20]; 5508 5509 u8 reserved_1[0x40]; 5510 }; 5511 5512 struct mlx5_ifc_init2rtr_qp_in_bits { 5513 u8 opcode[0x10]; 5514 u8 reserved_0[0x10]; 5515 5516 u8 reserved_1[0x10]; 5517 u8 op_mod[0x10]; 5518 5519 u8 reserved_2[0x8]; 5520 u8 qpn[0x18]; 5521 5522 u8 reserved_3[0x20]; 5523 5524 u8 opt_param_mask[0x20]; 5525 5526 u8 reserved_4[0x20]; 5527 5528 struct mlx5_ifc_qpc_bits qpc; 5529 5530 u8 reserved_5[0x80]; 5531 }; 5532 5533 struct mlx5_ifc_init2init_qp_out_bits { 5534 u8 status[0x8]; 5535 u8 reserved_0[0x18]; 5536 5537 u8 syndrome[0x20]; 5538 5539 u8 reserved_1[0x40]; 5540 }; 5541 5542 struct mlx5_ifc_init2init_qp_in_bits { 5543 u8 opcode[0x10]; 5544 u8 reserved_0[0x10]; 5545 5546 u8 reserved_1[0x10]; 5547 u8 op_mod[0x10]; 5548 5549 u8 reserved_2[0x8]; 5550 u8 qpn[0x18]; 5551 5552 u8 reserved_3[0x20]; 5553 5554 u8 opt_param_mask[0x20]; 5555 5556 u8 reserved_4[0x20]; 5557 5558 struct mlx5_ifc_qpc_bits qpc; 5559 5560 u8 reserved_5[0x80]; 5561 }; 5562 5563 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5564 u8 status[0x8]; 5565 u8 reserved_0[0x18]; 5566 5567 u8 syndrome[0x20]; 5568 5569 u8 reserved_1[0x40]; 5570 5571 u8 packet_headers_log[128][0x8]; 5572 5573 u8 packet_syndrome[64][0x8]; 5574 }; 5575 5576 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5577 u8 opcode[0x10]; 5578 u8 reserved_0[0x10]; 5579 5580 u8 reserved_1[0x10]; 5581 u8 op_mod[0x10]; 5582 5583 u8 reserved_2[0x40]; 5584 }; 5585 5586 struct mlx5_ifc_gen_eqe_in_bits { 5587 u8 opcode[0x10]; 5588 u8 reserved_0[0x10]; 5589 5590 u8 reserved_1[0x10]; 5591 u8 op_mod[0x10]; 5592 5593 u8 reserved_2[0x18]; 5594 u8 eq_number[0x8]; 5595 5596 u8 reserved_3[0x20]; 5597 5598 u8 eqe[64][0x8]; 5599 }; 5600 5601 struct mlx5_ifc_gen_eq_out_bits { 5602 u8 status[0x8]; 5603 u8 reserved_0[0x18]; 5604 5605 u8 syndrome[0x20]; 5606 5607 u8 reserved_1[0x40]; 5608 }; 5609 5610 struct mlx5_ifc_enable_hca_out_bits { 5611 u8 status[0x8]; 5612 u8 reserved_0[0x18]; 5613 5614 u8 syndrome[0x20]; 5615 5616 u8 reserved_1[0x20]; 5617 }; 5618 5619 struct mlx5_ifc_enable_hca_in_bits { 5620 u8 opcode[0x10]; 5621 u8 reserved_0[0x10]; 5622 5623 u8 reserved_1[0x10]; 5624 u8 op_mod[0x10]; 5625 5626 u8 reserved_2[0x10]; 5627 u8 function_id[0x10]; 5628 5629 u8 reserved_3[0x20]; 5630 }; 5631 5632 struct mlx5_ifc_drain_dct_out_bits { 5633 u8 status[0x8]; 5634 u8 reserved_0[0x18]; 5635 5636 u8 syndrome[0x20]; 5637 5638 u8 reserved_1[0x40]; 5639 }; 5640 5641 struct mlx5_ifc_drain_dct_in_bits { 5642 u8 opcode[0x10]; 5643 u8 reserved_0[0x10]; 5644 5645 u8 reserved_1[0x10]; 5646 u8 op_mod[0x10]; 5647 5648 u8 reserved_2[0x8]; 5649 u8 dctn[0x18]; 5650 5651 u8 reserved_3[0x20]; 5652 }; 5653 5654 struct mlx5_ifc_disable_hca_out_bits { 5655 u8 status[0x8]; 5656 u8 reserved_0[0x18]; 5657 5658 u8 syndrome[0x20]; 5659 5660 u8 reserved_1[0x20]; 5661 }; 5662 5663 struct mlx5_ifc_disable_hca_in_bits { 5664 u8 opcode[0x10]; 5665 u8 reserved_0[0x10]; 5666 5667 u8 reserved_1[0x10]; 5668 u8 op_mod[0x10]; 5669 5670 u8 reserved_2[0x10]; 5671 u8 function_id[0x10]; 5672 5673 u8 reserved_3[0x20]; 5674 }; 5675 5676 struct mlx5_ifc_detach_from_mcg_out_bits { 5677 u8 status[0x8]; 5678 u8 reserved_0[0x18]; 5679 5680 u8 syndrome[0x20]; 5681 5682 u8 reserved_1[0x40]; 5683 }; 5684 5685 struct mlx5_ifc_detach_from_mcg_in_bits { 5686 u8 opcode[0x10]; 5687 u8 reserved_0[0x10]; 5688 5689 u8 reserved_1[0x10]; 5690 u8 op_mod[0x10]; 5691 5692 u8 reserved_2[0x8]; 5693 u8 qpn[0x18]; 5694 5695 u8 reserved_3[0x20]; 5696 5697 u8 multicast_gid[16][0x8]; 5698 }; 5699 5700 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5701 u8 status[0x8]; 5702 u8 reserved_0[0x18]; 5703 5704 u8 syndrome[0x20]; 5705 5706 u8 reserved_1[0x40]; 5707 }; 5708 5709 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5710 u8 opcode[0x10]; 5711 u8 reserved_0[0x10]; 5712 5713 u8 reserved_1[0x10]; 5714 u8 op_mod[0x10]; 5715 5716 u8 reserved_2[0x8]; 5717 u8 xrc_srqn[0x18]; 5718 5719 u8 reserved_3[0x20]; 5720 }; 5721 5722 struct mlx5_ifc_destroy_tis_out_bits { 5723 u8 status[0x8]; 5724 u8 reserved_0[0x18]; 5725 5726 u8 syndrome[0x20]; 5727 5728 u8 reserved_1[0x40]; 5729 }; 5730 5731 struct mlx5_ifc_destroy_tis_in_bits { 5732 u8 opcode[0x10]; 5733 u8 reserved_0[0x10]; 5734 5735 u8 reserved_1[0x10]; 5736 u8 op_mod[0x10]; 5737 5738 u8 reserved_2[0x8]; 5739 u8 tisn[0x18]; 5740 5741 u8 reserved_3[0x20]; 5742 }; 5743 5744 struct mlx5_ifc_destroy_tir_out_bits { 5745 u8 status[0x8]; 5746 u8 reserved_0[0x18]; 5747 5748 u8 syndrome[0x20]; 5749 5750 u8 reserved_1[0x40]; 5751 }; 5752 5753 struct mlx5_ifc_destroy_tir_in_bits { 5754 u8 opcode[0x10]; 5755 u8 reserved_0[0x10]; 5756 5757 u8 reserved_1[0x10]; 5758 u8 op_mod[0x10]; 5759 5760 u8 reserved_2[0x8]; 5761 u8 tirn[0x18]; 5762 5763 u8 reserved_3[0x20]; 5764 }; 5765 5766 struct mlx5_ifc_destroy_srq_out_bits { 5767 u8 status[0x8]; 5768 u8 reserved_0[0x18]; 5769 5770 u8 syndrome[0x20]; 5771 5772 u8 reserved_1[0x40]; 5773 }; 5774 5775 struct mlx5_ifc_destroy_srq_in_bits { 5776 u8 opcode[0x10]; 5777 u8 reserved_0[0x10]; 5778 5779 u8 reserved_1[0x10]; 5780 u8 op_mod[0x10]; 5781 5782 u8 reserved_2[0x8]; 5783 u8 srqn[0x18]; 5784 5785 u8 reserved_3[0x20]; 5786 }; 5787 5788 struct mlx5_ifc_destroy_sq_out_bits { 5789 u8 status[0x8]; 5790 u8 reserved_0[0x18]; 5791 5792 u8 syndrome[0x20]; 5793 5794 u8 reserved_1[0x40]; 5795 }; 5796 5797 struct mlx5_ifc_destroy_sq_in_bits { 5798 u8 opcode[0x10]; 5799 u8 reserved_0[0x10]; 5800 5801 u8 reserved_1[0x10]; 5802 u8 op_mod[0x10]; 5803 5804 u8 reserved_2[0x8]; 5805 u8 sqn[0x18]; 5806 5807 u8 reserved_3[0x20]; 5808 }; 5809 5810 struct mlx5_ifc_destroy_scheduling_element_out_bits { 5811 u8 status[0x8]; 5812 u8 reserved_at_8[0x18]; 5813 5814 u8 syndrome[0x20]; 5815 5816 u8 reserved_at_40[0x1c0]; 5817 }; 5818 5819 enum { 5820 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5821 }; 5822 5823 struct mlx5_ifc_destroy_scheduling_element_in_bits { 5824 u8 opcode[0x10]; 5825 u8 reserved_at_10[0x10]; 5826 5827 u8 reserved_at_20[0x10]; 5828 u8 op_mod[0x10]; 5829 5830 u8 scheduling_hierarchy[0x8]; 5831 u8 reserved_at_48[0x18]; 5832 5833 u8 scheduling_element_id[0x20]; 5834 5835 u8 reserved_at_80[0x180]; 5836 }; 5837 5838 struct mlx5_ifc_destroy_rqt_out_bits { 5839 u8 status[0x8]; 5840 u8 reserved_0[0x18]; 5841 5842 u8 syndrome[0x20]; 5843 5844 u8 reserved_1[0x40]; 5845 }; 5846 5847 struct mlx5_ifc_destroy_rqt_in_bits { 5848 u8 opcode[0x10]; 5849 u8 reserved_0[0x10]; 5850 5851 u8 reserved_1[0x10]; 5852 u8 op_mod[0x10]; 5853 5854 u8 reserved_2[0x8]; 5855 u8 rqtn[0x18]; 5856 5857 u8 reserved_3[0x20]; 5858 }; 5859 5860 struct mlx5_ifc_destroy_rq_out_bits { 5861 u8 status[0x8]; 5862 u8 reserved_0[0x18]; 5863 5864 u8 syndrome[0x20]; 5865 5866 u8 reserved_1[0x40]; 5867 }; 5868 5869 struct mlx5_ifc_destroy_rq_in_bits { 5870 u8 opcode[0x10]; 5871 u8 reserved_0[0x10]; 5872 5873 u8 reserved_1[0x10]; 5874 u8 op_mod[0x10]; 5875 5876 u8 reserved_2[0x8]; 5877 u8 rqn[0x18]; 5878 5879 u8 reserved_3[0x20]; 5880 }; 5881 5882 struct mlx5_ifc_destroy_rmp_out_bits { 5883 u8 status[0x8]; 5884 u8 reserved_0[0x18]; 5885 5886 u8 syndrome[0x20]; 5887 5888 u8 reserved_1[0x40]; 5889 }; 5890 5891 struct mlx5_ifc_destroy_rmp_in_bits { 5892 u8 opcode[0x10]; 5893 u8 reserved_0[0x10]; 5894 5895 u8 reserved_1[0x10]; 5896 u8 op_mod[0x10]; 5897 5898 u8 reserved_2[0x8]; 5899 u8 rmpn[0x18]; 5900 5901 u8 reserved_3[0x20]; 5902 }; 5903 5904 struct mlx5_ifc_destroy_qp_out_bits { 5905 u8 status[0x8]; 5906 u8 reserved_0[0x18]; 5907 5908 u8 syndrome[0x20]; 5909 5910 u8 reserved_1[0x40]; 5911 }; 5912 5913 struct mlx5_ifc_destroy_qp_in_bits { 5914 u8 opcode[0x10]; 5915 u8 reserved_0[0x10]; 5916 5917 u8 reserved_1[0x10]; 5918 u8 op_mod[0x10]; 5919 5920 u8 reserved_2[0x8]; 5921 u8 qpn[0x18]; 5922 5923 u8 reserved_3[0x20]; 5924 }; 5925 5926 struct mlx5_ifc_destroy_qos_para_vport_out_bits { 5927 u8 status[0x8]; 5928 u8 reserved_at_8[0x18]; 5929 5930 u8 syndrome[0x20]; 5931 5932 u8 reserved_at_40[0x1c0]; 5933 }; 5934 5935 struct mlx5_ifc_destroy_qos_para_vport_in_bits { 5936 u8 opcode[0x10]; 5937 u8 reserved_at_10[0x10]; 5938 5939 u8 reserved_at_20[0x10]; 5940 u8 op_mod[0x10]; 5941 5942 u8 reserved_at_40[0x20]; 5943 5944 u8 reserved_at_60[0x10]; 5945 u8 qos_para_vport_number[0x10]; 5946 5947 u8 reserved_at_80[0x180]; 5948 }; 5949 5950 struct mlx5_ifc_destroy_psv_out_bits { 5951 u8 status[0x8]; 5952 u8 reserved_0[0x18]; 5953 5954 u8 syndrome[0x20]; 5955 5956 u8 reserved_1[0x40]; 5957 }; 5958 5959 struct mlx5_ifc_destroy_psv_in_bits { 5960 u8 opcode[0x10]; 5961 u8 reserved_0[0x10]; 5962 5963 u8 reserved_1[0x10]; 5964 u8 op_mod[0x10]; 5965 5966 u8 reserved_2[0x8]; 5967 u8 psvn[0x18]; 5968 5969 u8 reserved_3[0x20]; 5970 }; 5971 5972 struct mlx5_ifc_destroy_mkey_out_bits { 5973 u8 status[0x8]; 5974 u8 reserved_0[0x18]; 5975 5976 u8 syndrome[0x20]; 5977 5978 u8 reserved_1[0x40]; 5979 }; 5980 5981 struct mlx5_ifc_destroy_mkey_in_bits { 5982 u8 opcode[0x10]; 5983 u8 reserved_0[0x10]; 5984 5985 u8 reserved_1[0x10]; 5986 u8 op_mod[0x10]; 5987 5988 u8 reserved_2[0x8]; 5989 u8 mkey_index[0x18]; 5990 5991 u8 reserved_3[0x20]; 5992 }; 5993 5994 struct mlx5_ifc_destroy_flow_table_out_bits { 5995 u8 status[0x8]; 5996 u8 reserved_0[0x18]; 5997 5998 u8 syndrome[0x20]; 5999 6000 u8 reserved_1[0x40]; 6001 }; 6002 6003 struct mlx5_ifc_destroy_flow_table_in_bits { 6004 u8 opcode[0x10]; 6005 u8 reserved_0[0x10]; 6006 6007 u8 reserved_1[0x10]; 6008 u8 op_mod[0x10]; 6009 6010 u8 other_vport[0x1]; 6011 u8 reserved_2[0xf]; 6012 u8 vport_number[0x10]; 6013 6014 u8 reserved_3[0x20]; 6015 6016 u8 table_type[0x8]; 6017 u8 reserved_4[0x18]; 6018 6019 u8 reserved_5[0x8]; 6020 u8 table_id[0x18]; 6021 6022 u8 reserved_6[0x140]; 6023 }; 6024 6025 struct mlx5_ifc_destroy_flow_group_out_bits { 6026 u8 status[0x8]; 6027 u8 reserved_0[0x18]; 6028 6029 u8 syndrome[0x20]; 6030 6031 u8 reserved_1[0x40]; 6032 }; 6033 6034 struct mlx5_ifc_destroy_flow_group_in_bits { 6035 u8 opcode[0x10]; 6036 u8 reserved_0[0x10]; 6037 6038 u8 reserved_1[0x10]; 6039 u8 op_mod[0x10]; 6040 6041 u8 other_vport[0x1]; 6042 u8 reserved_2[0xf]; 6043 u8 vport_number[0x10]; 6044 6045 u8 reserved_3[0x20]; 6046 6047 u8 table_type[0x8]; 6048 u8 reserved_4[0x18]; 6049 6050 u8 reserved_5[0x8]; 6051 u8 table_id[0x18]; 6052 6053 u8 group_id[0x20]; 6054 6055 u8 reserved_6[0x120]; 6056 }; 6057 6058 struct mlx5_ifc_destroy_eq_out_bits { 6059 u8 status[0x8]; 6060 u8 reserved_0[0x18]; 6061 6062 u8 syndrome[0x20]; 6063 6064 u8 reserved_1[0x40]; 6065 }; 6066 6067 struct mlx5_ifc_destroy_eq_in_bits { 6068 u8 opcode[0x10]; 6069 u8 reserved_0[0x10]; 6070 6071 u8 reserved_1[0x10]; 6072 u8 op_mod[0x10]; 6073 6074 u8 reserved_2[0x18]; 6075 u8 eq_number[0x8]; 6076 6077 u8 reserved_3[0x20]; 6078 }; 6079 6080 struct mlx5_ifc_destroy_dct_out_bits { 6081 u8 status[0x8]; 6082 u8 reserved_0[0x18]; 6083 6084 u8 syndrome[0x20]; 6085 6086 u8 reserved_1[0x40]; 6087 }; 6088 6089 struct mlx5_ifc_destroy_dct_in_bits { 6090 u8 opcode[0x10]; 6091 u8 reserved_0[0x10]; 6092 6093 u8 reserved_1[0x10]; 6094 u8 op_mod[0x10]; 6095 6096 u8 reserved_2[0x8]; 6097 u8 dctn[0x18]; 6098 6099 u8 reserved_3[0x20]; 6100 }; 6101 6102 struct mlx5_ifc_destroy_cq_out_bits { 6103 u8 status[0x8]; 6104 u8 reserved_0[0x18]; 6105 6106 u8 syndrome[0x20]; 6107 6108 u8 reserved_1[0x40]; 6109 }; 6110 6111 struct mlx5_ifc_destroy_cq_in_bits { 6112 u8 opcode[0x10]; 6113 u8 reserved_0[0x10]; 6114 6115 u8 reserved_1[0x10]; 6116 u8 op_mod[0x10]; 6117 6118 u8 reserved_2[0x8]; 6119 u8 cqn[0x18]; 6120 6121 u8 reserved_3[0x20]; 6122 }; 6123 6124 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6125 u8 status[0x8]; 6126 u8 reserved_0[0x18]; 6127 6128 u8 syndrome[0x20]; 6129 6130 u8 reserved_1[0x40]; 6131 }; 6132 6133 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6134 u8 opcode[0x10]; 6135 u8 reserved_0[0x10]; 6136 6137 u8 reserved_1[0x10]; 6138 u8 op_mod[0x10]; 6139 6140 u8 reserved_2[0x20]; 6141 6142 u8 reserved_3[0x10]; 6143 u8 vxlan_udp_port[0x10]; 6144 }; 6145 6146 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6147 u8 status[0x8]; 6148 u8 reserved_0[0x18]; 6149 6150 u8 syndrome[0x20]; 6151 6152 u8 reserved_1[0x40]; 6153 }; 6154 6155 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6156 u8 opcode[0x10]; 6157 u8 reserved_0[0x10]; 6158 6159 u8 reserved_1[0x10]; 6160 u8 op_mod[0x10]; 6161 6162 u8 reserved_2[0x60]; 6163 6164 u8 reserved_3[0x8]; 6165 u8 table_index[0x18]; 6166 6167 u8 reserved_4[0x140]; 6168 }; 6169 6170 struct mlx5_ifc_delete_fte_out_bits { 6171 u8 status[0x8]; 6172 u8 reserved_0[0x18]; 6173 6174 u8 syndrome[0x20]; 6175 6176 u8 reserved_1[0x40]; 6177 }; 6178 6179 struct mlx5_ifc_delete_fte_in_bits { 6180 u8 opcode[0x10]; 6181 u8 reserved_0[0x10]; 6182 6183 u8 reserved_1[0x10]; 6184 u8 op_mod[0x10]; 6185 6186 u8 other_vport[0x1]; 6187 u8 reserved_2[0xf]; 6188 u8 vport_number[0x10]; 6189 6190 u8 reserved_3[0x20]; 6191 6192 u8 table_type[0x8]; 6193 u8 reserved_4[0x18]; 6194 6195 u8 reserved_5[0x8]; 6196 u8 table_id[0x18]; 6197 6198 u8 reserved_6[0x40]; 6199 6200 u8 flow_index[0x20]; 6201 6202 u8 reserved_7[0xe0]; 6203 }; 6204 6205 struct mlx5_ifc_dealloc_xrcd_out_bits { 6206 u8 status[0x8]; 6207 u8 reserved_0[0x18]; 6208 6209 u8 syndrome[0x20]; 6210 6211 u8 reserved_1[0x40]; 6212 }; 6213 6214 struct mlx5_ifc_dealloc_xrcd_in_bits { 6215 u8 opcode[0x10]; 6216 u8 reserved_0[0x10]; 6217 6218 u8 reserved_1[0x10]; 6219 u8 op_mod[0x10]; 6220 6221 u8 reserved_2[0x8]; 6222 u8 xrcd[0x18]; 6223 6224 u8 reserved_3[0x20]; 6225 }; 6226 6227 struct mlx5_ifc_dealloc_uar_out_bits { 6228 u8 status[0x8]; 6229 u8 reserved_0[0x18]; 6230 6231 u8 syndrome[0x20]; 6232 6233 u8 reserved_1[0x40]; 6234 }; 6235 6236 struct mlx5_ifc_dealloc_uar_in_bits { 6237 u8 opcode[0x10]; 6238 u8 reserved_0[0x10]; 6239 6240 u8 reserved_1[0x10]; 6241 u8 op_mod[0x10]; 6242 6243 u8 reserved_2[0x8]; 6244 u8 uar[0x18]; 6245 6246 u8 reserved_3[0x20]; 6247 }; 6248 6249 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6250 u8 status[0x8]; 6251 u8 reserved_0[0x18]; 6252 6253 u8 syndrome[0x20]; 6254 6255 u8 reserved_1[0x40]; 6256 }; 6257 6258 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6259 u8 opcode[0x10]; 6260 u8 reserved_0[0x10]; 6261 6262 u8 reserved_1[0x10]; 6263 u8 op_mod[0x10]; 6264 6265 u8 reserved_2[0x8]; 6266 u8 transport_domain[0x18]; 6267 6268 u8 reserved_3[0x20]; 6269 }; 6270 6271 struct mlx5_ifc_dealloc_q_counter_out_bits { 6272 u8 status[0x8]; 6273 u8 reserved_0[0x18]; 6274 6275 u8 syndrome[0x20]; 6276 6277 u8 reserved_1[0x40]; 6278 }; 6279 6280 struct mlx5_ifc_counter_id_bits { 6281 u8 reserved[0x10]; 6282 u8 counter_id[0x10]; 6283 }; 6284 6285 struct mlx5_ifc_diagnostic_params_context_bits { 6286 u8 num_of_counters[0x10]; 6287 u8 reserved_2[0x8]; 6288 u8 log_num_of_samples[0x8]; 6289 6290 u8 single[0x1]; 6291 u8 repetitive[0x1]; 6292 u8 sync[0x1]; 6293 u8 clear[0x1]; 6294 u8 on_demand[0x1]; 6295 u8 enable[0x1]; 6296 u8 reserved_3[0x12]; 6297 u8 log_sample_period[0x8]; 6298 6299 u8 reserved_4[0x80]; 6300 6301 struct mlx5_ifc_counter_id_bits counter_id[0]; 6302 }; 6303 6304 struct mlx5_ifc_set_diagnostic_params_in_bits { 6305 u8 opcode[0x10]; 6306 u8 reserved_0[0x10]; 6307 6308 u8 reserved_1[0x10]; 6309 u8 op_mod[0x10]; 6310 6311 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 6312 }; 6313 6314 struct mlx5_ifc_set_diagnostic_params_out_bits { 6315 u8 status[0x8]; 6316 u8 reserved_0[0x18]; 6317 6318 u8 syndrome[0x20]; 6319 6320 u8 reserved_1[0x40]; 6321 }; 6322 6323 struct mlx5_ifc_query_diagnostic_counters_in_bits { 6324 u8 opcode[0x10]; 6325 u8 reserved_0[0x10]; 6326 6327 u8 reserved_1[0x10]; 6328 u8 op_mod[0x10]; 6329 6330 u8 num_of_samples[0x10]; 6331 u8 sample_index[0x10]; 6332 6333 u8 reserved_2[0x20]; 6334 }; 6335 6336 struct mlx5_ifc_diagnostic_counter_bits { 6337 u8 counter_id[0x10]; 6338 u8 sample_id[0x10]; 6339 6340 u8 time_stamp_31_0[0x20]; 6341 6342 u8 counter_value_h[0x20]; 6343 6344 u8 counter_value_l[0x20]; 6345 }; 6346 6347 struct mlx5_ifc_query_diagnostic_counters_out_bits { 6348 u8 status[0x8]; 6349 u8 reserved_0[0x18]; 6350 6351 u8 syndrome[0x20]; 6352 6353 u8 reserved_1[0x40]; 6354 6355 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 6356 }; 6357 6358 struct mlx5_ifc_dealloc_q_counter_in_bits { 6359 u8 opcode[0x10]; 6360 u8 reserved_0[0x10]; 6361 6362 u8 reserved_1[0x10]; 6363 u8 op_mod[0x10]; 6364 6365 u8 reserved_2[0x18]; 6366 u8 counter_set_id[0x8]; 6367 6368 u8 reserved_3[0x20]; 6369 }; 6370 6371 struct mlx5_ifc_dealloc_pd_out_bits { 6372 u8 status[0x8]; 6373 u8 reserved_0[0x18]; 6374 6375 u8 syndrome[0x20]; 6376 6377 u8 reserved_1[0x40]; 6378 }; 6379 6380 struct mlx5_ifc_dealloc_pd_in_bits { 6381 u8 opcode[0x10]; 6382 u8 reserved_0[0x10]; 6383 6384 u8 reserved_1[0x10]; 6385 u8 op_mod[0x10]; 6386 6387 u8 reserved_2[0x8]; 6388 u8 pd[0x18]; 6389 6390 u8 reserved_3[0x20]; 6391 }; 6392 6393 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6394 u8 status[0x8]; 6395 u8 reserved_0[0x18]; 6396 6397 u8 syndrome[0x20]; 6398 6399 u8 reserved_1[0x40]; 6400 }; 6401 6402 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6403 u8 opcode[0x10]; 6404 u8 reserved_0[0x10]; 6405 6406 u8 reserved_1[0x10]; 6407 u8 op_mod[0x10]; 6408 6409 u8 reserved_2[0x10]; 6410 u8 flow_counter_id[0x10]; 6411 6412 u8 reserved_3[0x20]; 6413 }; 6414 6415 struct mlx5_ifc_deactivate_tracer_out_bits { 6416 u8 status[0x8]; 6417 u8 reserved_0[0x18]; 6418 6419 u8 syndrome[0x20]; 6420 6421 u8 reserved_1[0x40]; 6422 }; 6423 6424 struct mlx5_ifc_deactivate_tracer_in_bits { 6425 u8 opcode[0x10]; 6426 u8 reserved_0[0x10]; 6427 6428 u8 reserved_1[0x10]; 6429 u8 op_mod[0x10]; 6430 6431 u8 mkey[0x20]; 6432 6433 u8 reserved_2[0x20]; 6434 }; 6435 6436 struct mlx5_ifc_create_xrc_srq_out_bits { 6437 u8 status[0x8]; 6438 u8 reserved_0[0x18]; 6439 6440 u8 syndrome[0x20]; 6441 6442 u8 reserved_1[0x8]; 6443 u8 xrc_srqn[0x18]; 6444 6445 u8 reserved_2[0x20]; 6446 }; 6447 6448 struct mlx5_ifc_create_xrc_srq_in_bits { 6449 u8 opcode[0x10]; 6450 u8 reserved_0[0x10]; 6451 6452 u8 reserved_1[0x10]; 6453 u8 op_mod[0x10]; 6454 6455 u8 reserved_2[0x40]; 6456 6457 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6458 6459 u8 reserved_3[0x600]; 6460 6461 u8 pas[0][0x40]; 6462 }; 6463 6464 struct mlx5_ifc_create_tis_out_bits { 6465 u8 status[0x8]; 6466 u8 reserved_0[0x18]; 6467 6468 u8 syndrome[0x20]; 6469 6470 u8 reserved_1[0x8]; 6471 u8 tisn[0x18]; 6472 6473 u8 reserved_2[0x20]; 6474 }; 6475 6476 struct mlx5_ifc_create_tis_in_bits { 6477 u8 opcode[0x10]; 6478 u8 reserved_0[0x10]; 6479 6480 u8 reserved_1[0x10]; 6481 u8 op_mod[0x10]; 6482 6483 u8 reserved_2[0xc0]; 6484 6485 struct mlx5_ifc_tisc_bits ctx; 6486 }; 6487 6488 struct mlx5_ifc_create_tir_out_bits { 6489 u8 status[0x8]; 6490 u8 reserved_0[0x18]; 6491 6492 u8 syndrome[0x20]; 6493 6494 u8 reserved_1[0x8]; 6495 u8 tirn[0x18]; 6496 6497 u8 reserved_2[0x20]; 6498 }; 6499 6500 struct mlx5_ifc_create_tir_in_bits { 6501 u8 opcode[0x10]; 6502 u8 reserved_0[0x10]; 6503 6504 u8 reserved_1[0x10]; 6505 u8 op_mod[0x10]; 6506 6507 u8 reserved_2[0xc0]; 6508 6509 struct mlx5_ifc_tirc_bits tir_context; 6510 }; 6511 6512 struct mlx5_ifc_create_srq_out_bits { 6513 u8 status[0x8]; 6514 u8 reserved_0[0x18]; 6515 6516 u8 syndrome[0x20]; 6517 6518 u8 reserved_1[0x8]; 6519 u8 srqn[0x18]; 6520 6521 u8 reserved_2[0x20]; 6522 }; 6523 6524 struct mlx5_ifc_create_srq_in_bits { 6525 u8 opcode[0x10]; 6526 u8 reserved_0[0x10]; 6527 6528 u8 reserved_1[0x10]; 6529 u8 op_mod[0x10]; 6530 6531 u8 reserved_2[0x40]; 6532 6533 struct mlx5_ifc_srqc_bits srq_context_entry; 6534 6535 u8 reserved_3[0x600]; 6536 6537 u8 pas[0][0x40]; 6538 }; 6539 6540 struct mlx5_ifc_create_sq_out_bits { 6541 u8 status[0x8]; 6542 u8 reserved_0[0x18]; 6543 6544 u8 syndrome[0x20]; 6545 6546 u8 reserved_1[0x8]; 6547 u8 sqn[0x18]; 6548 6549 u8 reserved_2[0x20]; 6550 }; 6551 6552 struct mlx5_ifc_create_sq_in_bits { 6553 u8 opcode[0x10]; 6554 u8 reserved_0[0x10]; 6555 6556 u8 reserved_1[0x10]; 6557 u8 op_mod[0x10]; 6558 6559 u8 reserved_2[0xc0]; 6560 6561 struct mlx5_ifc_sqc_bits ctx; 6562 }; 6563 6564 struct mlx5_ifc_create_scheduling_element_out_bits { 6565 u8 status[0x8]; 6566 u8 reserved_at_8[0x18]; 6567 6568 u8 syndrome[0x20]; 6569 6570 u8 reserved_at_40[0x40]; 6571 6572 u8 scheduling_element_id[0x20]; 6573 6574 u8 reserved_at_a0[0x160]; 6575 }; 6576 6577 enum { 6578 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6579 }; 6580 6581 struct mlx5_ifc_create_scheduling_element_in_bits { 6582 u8 opcode[0x10]; 6583 u8 reserved_at_10[0x10]; 6584 6585 u8 reserved_at_20[0x10]; 6586 u8 op_mod[0x10]; 6587 6588 u8 scheduling_hierarchy[0x8]; 6589 u8 reserved_at_48[0x18]; 6590 6591 u8 reserved_at_60[0xa0]; 6592 6593 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6594 6595 u8 reserved_at_300[0x100]; 6596 }; 6597 6598 struct mlx5_ifc_create_rqt_out_bits { 6599 u8 status[0x8]; 6600 u8 reserved_0[0x18]; 6601 6602 u8 syndrome[0x20]; 6603 6604 u8 reserved_1[0x8]; 6605 u8 rqtn[0x18]; 6606 6607 u8 reserved_2[0x20]; 6608 }; 6609 6610 struct mlx5_ifc_create_rqt_in_bits { 6611 u8 opcode[0x10]; 6612 u8 reserved_0[0x10]; 6613 6614 u8 reserved_1[0x10]; 6615 u8 op_mod[0x10]; 6616 6617 u8 reserved_2[0xc0]; 6618 6619 struct mlx5_ifc_rqtc_bits rqt_context; 6620 }; 6621 6622 struct mlx5_ifc_create_rq_out_bits { 6623 u8 status[0x8]; 6624 u8 reserved_0[0x18]; 6625 6626 u8 syndrome[0x20]; 6627 6628 u8 reserved_1[0x8]; 6629 u8 rqn[0x18]; 6630 6631 u8 reserved_2[0x20]; 6632 }; 6633 6634 struct mlx5_ifc_create_rq_in_bits { 6635 u8 opcode[0x10]; 6636 u8 reserved_0[0x10]; 6637 6638 u8 reserved_1[0x10]; 6639 u8 op_mod[0x10]; 6640 6641 u8 reserved_2[0xc0]; 6642 6643 struct mlx5_ifc_rqc_bits ctx; 6644 }; 6645 6646 struct mlx5_ifc_create_rmp_out_bits { 6647 u8 status[0x8]; 6648 u8 reserved_0[0x18]; 6649 6650 u8 syndrome[0x20]; 6651 6652 u8 reserved_1[0x8]; 6653 u8 rmpn[0x18]; 6654 6655 u8 reserved_2[0x20]; 6656 }; 6657 6658 struct mlx5_ifc_create_rmp_in_bits { 6659 u8 opcode[0x10]; 6660 u8 reserved_0[0x10]; 6661 6662 u8 reserved_1[0x10]; 6663 u8 op_mod[0x10]; 6664 6665 u8 reserved_2[0xc0]; 6666 6667 struct mlx5_ifc_rmpc_bits ctx; 6668 }; 6669 6670 struct mlx5_ifc_create_qp_out_bits { 6671 u8 status[0x8]; 6672 u8 reserved_0[0x18]; 6673 6674 u8 syndrome[0x20]; 6675 6676 u8 reserved_1[0x8]; 6677 u8 qpn[0x18]; 6678 6679 u8 reserved_2[0x20]; 6680 }; 6681 6682 struct mlx5_ifc_create_qp_in_bits { 6683 u8 opcode[0x10]; 6684 u8 reserved_0[0x10]; 6685 6686 u8 reserved_1[0x10]; 6687 u8 op_mod[0x10]; 6688 6689 u8 reserved_2[0x8]; 6690 u8 input_qpn[0x18]; 6691 6692 u8 reserved_3[0x20]; 6693 6694 u8 opt_param_mask[0x20]; 6695 6696 u8 reserved_4[0x20]; 6697 6698 struct mlx5_ifc_qpc_bits qpc; 6699 6700 u8 reserved_5[0x80]; 6701 6702 u8 pas[0][0x40]; 6703 }; 6704 6705 struct mlx5_ifc_create_qos_para_vport_out_bits { 6706 u8 status[0x8]; 6707 u8 reserved_at_8[0x18]; 6708 6709 u8 syndrome[0x20]; 6710 6711 u8 reserved_at_40[0x20]; 6712 6713 u8 reserved_at_60[0x10]; 6714 u8 qos_para_vport_number[0x10]; 6715 6716 u8 reserved_at_80[0x180]; 6717 }; 6718 6719 struct mlx5_ifc_create_qos_para_vport_in_bits { 6720 u8 opcode[0x10]; 6721 u8 reserved_at_10[0x10]; 6722 6723 u8 reserved_at_20[0x10]; 6724 u8 op_mod[0x10]; 6725 6726 u8 reserved_at_40[0x1c0]; 6727 }; 6728 6729 struct mlx5_ifc_create_psv_out_bits { 6730 u8 status[0x8]; 6731 u8 reserved_0[0x18]; 6732 6733 u8 syndrome[0x20]; 6734 6735 u8 reserved_1[0x40]; 6736 6737 u8 reserved_2[0x8]; 6738 u8 psv0_index[0x18]; 6739 6740 u8 reserved_3[0x8]; 6741 u8 psv1_index[0x18]; 6742 6743 u8 reserved_4[0x8]; 6744 u8 psv2_index[0x18]; 6745 6746 u8 reserved_5[0x8]; 6747 u8 psv3_index[0x18]; 6748 }; 6749 6750 struct mlx5_ifc_create_psv_in_bits { 6751 u8 opcode[0x10]; 6752 u8 reserved_0[0x10]; 6753 6754 u8 reserved_1[0x10]; 6755 u8 op_mod[0x10]; 6756 6757 u8 num_psv[0x4]; 6758 u8 reserved_2[0x4]; 6759 u8 pd[0x18]; 6760 6761 u8 reserved_3[0x20]; 6762 }; 6763 6764 struct mlx5_ifc_create_mkey_out_bits { 6765 u8 status[0x8]; 6766 u8 reserved_0[0x18]; 6767 6768 u8 syndrome[0x20]; 6769 6770 u8 reserved_1[0x8]; 6771 u8 mkey_index[0x18]; 6772 6773 u8 reserved_2[0x20]; 6774 }; 6775 6776 struct mlx5_ifc_create_mkey_in_bits { 6777 u8 opcode[0x10]; 6778 u8 reserved_0[0x10]; 6779 6780 u8 reserved_1[0x10]; 6781 u8 op_mod[0x10]; 6782 6783 u8 reserved_2[0x20]; 6784 6785 u8 pg_access[0x1]; 6786 u8 reserved_3[0x1f]; 6787 6788 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6789 6790 u8 reserved_4[0x80]; 6791 6792 u8 translations_octword_actual_size[0x20]; 6793 6794 u8 reserved_5[0x560]; 6795 6796 u8 klm_pas_mtt[0][0x20]; 6797 }; 6798 6799 struct mlx5_ifc_create_flow_table_out_bits { 6800 u8 status[0x8]; 6801 u8 reserved_0[0x18]; 6802 6803 u8 syndrome[0x20]; 6804 6805 u8 reserved_1[0x8]; 6806 u8 table_id[0x18]; 6807 6808 u8 reserved_2[0x20]; 6809 }; 6810 6811 struct mlx5_ifc_create_flow_table_in_bits { 6812 u8 opcode[0x10]; 6813 u8 reserved_0[0x10]; 6814 6815 u8 reserved_1[0x10]; 6816 u8 op_mod[0x10]; 6817 6818 u8 other_vport[0x1]; 6819 u8 reserved_2[0xf]; 6820 u8 vport_number[0x10]; 6821 6822 u8 reserved_3[0x20]; 6823 6824 u8 table_type[0x8]; 6825 u8 reserved_4[0x18]; 6826 6827 u8 reserved_5[0x20]; 6828 6829 u8 reserved_6[0x8]; 6830 u8 level[0x8]; 6831 u8 reserved_7[0x8]; 6832 u8 log_size[0x8]; 6833 6834 u8 reserved_8[0x120]; 6835 }; 6836 6837 struct mlx5_ifc_create_flow_group_out_bits { 6838 u8 status[0x8]; 6839 u8 reserved_0[0x18]; 6840 6841 u8 syndrome[0x20]; 6842 6843 u8 reserved_1[0x8]; 6844 u8 group_id[0x18]; 6845 6846 u8 reserved_2[0x20]; 6847 }; 6848 6849 enum { 6850 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6851 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6852 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6853 }; 6854 6855 struct mlx5_ifc_create_flow_group_in_bits { 6856 u8 opcode[0x10]; 6857 u8 reserved_0[0x10]; 6858 6859 u8 reserved_1[0x10]; 6860 u8 op_mod[0x10]; 6861 6862 u8 other_vport[0x1]; 6863 u8 reserved_2[0xf]; 6864 u8 vport_number[0x10]; 6865 6866 u8 reserved_3[0x20]; 6867 6868 u8 table_type[0x8]; 6869 u8 reserved_4[0x18]; 6870 6871 u8 reserved_5[0x8]; 6872 u8 table_id[0x18]; 6873 6874 u8 reserved_6[0x20]; 6875 6876 u8 start_flow_index[0x20]; 6877 6878 u8 reserved_7[0x20]; 6879 6880 u8 end_flow_index[0x20]; 6881 6882 u8 reserved_8[0xa0]; 6883 6884 u8 reserved_9[0x18]; 6885 u8 match_criteria_enable[0x8]; 6886 6887 struct mlx5_ifc_fte_match_param_bits match_criteria; 6888 6889 u8 reserved_10[0xe00]; 6890 }; 6891 6892 struct mlx5_ifc_create_eq_out_bits { 6893 u8 status[0x8]; 6894 u8 reserved_0[0x18]; 6895 6896 u8 syndrome[0x20]; 6897 6898 u8 reserved_1[0x18]; 6899 u8 eq_number[0x8]; 6900 6901 u8 reserved_2[0x20]; 6902 }; 6903 6904 struct mlx5_ifc_create_eq_in_bits { 6905 u8 opcode[0x10]; 6906 u8 reserved_0[0x10]; 6907 6908 u8 reserved_1[0x10]; 6909 u8 op_mod[0x10]; 6910 6911 u8 reserved_2[0x40]; 6912 6913 struct mlx5_ifc_eqc_bits eq_context_entry; 6914 6915 u8 reserved_3[0x40]; 6916 6917 u8 event_bitmask[0x40]; 6918 6919 u8 reserved_4[0x580]; 6920 6921 u8 pas[0][0x40]; 6922 }; 6923 6924 struct mlx5_ifc_create_dct_out_bits { 6925 u8 status[0x8]; 6926 u8 reserved_0[0x18]; 6927 6928 u8 syndrome[0x20]; 6929 6930 u8 reserved_1[0x8]; 6931 u8 dctn[0x18]; 6932 6933 u8 reserved_2[0x20]; 6934 }; 6935 6936 struct mlx5_ifc_create_dct_in_bits { 6937 u8 opcode[0x10]; 6938 u8 reserved_0[0x10]; 6939 6940 u8 reserved_1[0x10]; 6941 u8 op_mod[0x10]; 6942 6943 u8 reserved_2[0x40]; 6944 6945 struct mlx5_ifc_dctc_bits dct_context_entry; 6946 6947 u8 reserved_3[0x180]; 6948 }; 6949 6950 struct mlx5_ifc_create_cq_out_bits { 6951 u8 status[0x8]; 6952 u8 reserved_0[0x18]; 6953 6954 u8 syndrome[0x20]; 6955 6956 u8 reserved_1[0x8]; 6957 u8 cqn[0x18]; 6958 6959 u8 reserved_2[0x20]; 6960 }; 6961 6962 struct mlx5_ifc_create_cq_in_bits { 6963 u8 opcode[0x10]; 6964 u8 reserved_0[0x10]; 6965 6966 u8 reserved_1[0x10]; 6967 u8 op_mod[0x10]; 6968 6969 u8 reserved_2[0x40]; 6970 6971 struct mlx5_ifc_cqc_bits cq_context; 6972 6973 u8 reserved_3[0x600]; 6974 6975 u8 pas[0][0x40]; 6976 }; 6977 6978 struct mlx5_ifc_config_int_moderation_out_bits { 6979 u8 status[0x8]; 6980 u8 reserved_0[0x18]; 6981 6982 u8 syndrome[0x20]; 6983 6984 u8 reserved_1[0x4]; 6985 u8 min_delay[0xc]; 6986 u8 int_vector[0x10]; 6987 6988 u8 reserved_2[0x20]; 6989 }; 6990 6991 enum { 6992 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 6993 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 6994 }; 6995 6996 struct mlx5_ifc_config_int_moderation_in_bits { 6997 u8 opcode[0x10]; 6998 u8 reserved_0[0x10]; 6999 7000 u8 reserved_1[0x10]; 7001 u8 op_mod[0x10]; 7002 7003 u8 reserved_2[0x4]; 7004 u8 min_delay[0xc]; 7005 u8 int_vector[0x10]; 7006 7007 u8 reserved_3[0x20]; 7008 }; 7009 7010 struct mlx5_ifc_attach_to_mcg_out_bits { 7011 u8 status[0x8]; 7012 u8 reserved_0[0x18]; 7013 7014 u8 syndrome[0x20]; 7015 7016 u8 reserved_1[0x40]; 7017 }; 7018 7019 struct mlx5_ifc_attach_to_mcg_in_bits { 7020 u8 opcode[0x10]; 7021 u8 reserved_0[0x10]; 7022 7023 u8 reserved_1[0x10]; 7024 u8 op_mod[0x10]; 7025 7026 u8 reserved_2[0x8]; 7027 u8 qpn[0x18]; 7028 7029 u8 reserved_3[0x20]; 7030 7031 u8 multicast_gid[16][0x8]; 7032 }; 7033 7034 struct mlx5_ifc_arm_xrc_srq_out_bits { 7035 u8 status[0x8]; 7036 u8 reserved_0[0x18]; 7037 7038 u8 syndrome[0x20]; 7039 7040 u8 reserved_1[0x40]; 7041 }; 7042 7043 enum { 7044 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7045 }; 7046 7047 struct mlx5_ifc_arm_xrc_srq_in_bits { 7048 u8 opcode[0x10]; 7049 u8 reserved_0[0x10]; 7050 7051 u8 reserved_1[0x10]; 7052 u8 op_mod[0x10]; 7053 7054 u8 reserved_2[0x8]; 7055 u8 xrc_srqn[0x18]; 7056 7057 u8 reserved_3[0x10]; 7058 u8 lwm[0x10]; 7059 }; 7060 7061 struct mlx5_ifc_arm_rq_out_bits { 7062 u8 status[0x8]; 7063 u8 reserved_0[0x18]; 7064 7065 u8 syndrome[0x20]; 7066 7067 u8 reserved_1[0x40]; 7068 }; 7069 7070 enum { 7071 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7072 }; 7073 7074 struct mlx5_ifc_arm_rq_in_bits { 7075 u8 opcode[0x10]; 7076 u8 reserved_0[0x10]; 7077 7078 u8 reserved_1[0x10]; 7079 u8 op_mod[0x10]; 7080 7081 u8 reserved_2[0x8]; 7082 u8 srq_number[0x18]; 7083 7084 u8 reserved_3[0x10]; 7085 u8 lwm[0x10]; 7086 }; 7087 7088 struct mlx5_ifc_arm_dct_out_bits { 7089 u8 status[0x8]; 7090 u8 reserved_0[0x18]; 7091 7092 u8 syndrome[0x20]; 7093 7094 u8 reserved_1[0x40]; 7095 }; 7096 7097 struct mlx5_ifc_arm_dct_in_bits { 7098 u8 opcode[0x10]; 7099 u8 reserved_0[0x10]; 7100 7101 u8 reserved_1[0x10]; 7102 u8 op_mod[0x10]; 7103 7104 u8 reserved_2[0x8]; 7105 u8 dctn[0x18]; 7106 7107 u8 reserved_3[0x20]; 7108 }; 7109 7110 struct mlx5_ifc_alloc_xrcd_out_bits { 7111 u8 status[0x8]; 7112 u8 reserved_0[0x18]; 7113 7114 u8 syndrome[0x20]; 7115 7116 u8 reserved_1[0x8]; 7117 u8 xrcd[0x18]; 7118 7119 u8 reserved_2[0x20]; 7120 }; 7121 7122 struct mlx5_ifc_alloc_xrcd_in_bits { 7123 u8 opcode[0x10]; 7124 u8 reserved_0[0x10]; 7125 7126 u8 reserved_1[0x10]; 7127 u8 op_mod[0x10]; 7128 7129 u8 reserved_2[0x40]; 7130 }; 7131 7132 struct mlx5_ifc_alloc_uar_out_bits { 7133 u8 status[0x8]; 7134 u8 reserved_0[0x18]; 7135 7136 u8 syndrome[0x20]; 7137 7138 u8 reserved_1[0x8]; 7139 u8 uar[0x18]; 7140 7141 u8 reserved_2[0x20]; 7142 }; 7143 7144 struct mlx5_ifc_alloc_uar_in_bits { 7145 u8 opcode[0x10]; 7146 u8 reserved_0[0x10]; 7147 7148 u8 reserved_1[0x10]; 7149 u8 op_mod[0x10]; 7150 7151 u8 reserved_2[0x40]; 7152 }; 7153 7154 struct mlx5_ifc_alloc_transport_domain_out_bits { 7155 u8 status[0x8]; 7156 u8 reserved_0[0x18]; 7157 7158 u8 syndrome[0x20]; 7159 7160 u8 reserved_1[0x8]; 7161 u8 transport_domain[0x18]; 7162 7163 u8 reserved_2[0x20]; 7164 }; 7165 7166 struct mlx5_ifc_alloc_transport_domain_in_bits { 7167 u8 opcode[0x10]; 7168 u8 reserved_0[0x10]; 7169 7170 u8 reserved_1[0x10]; 7171 u8 op_mod[0x10]; 7172 7173 u8 reserved_2[0x40]; 7174 }; 7175 7176 struct mlx5_ifc_alloc_q_counter_out_bits { 7177 u8 status[0x8]; 7178 u8 reserved_0[0x18]; 7179 7180 u8 syndrome[0x20]; 7181 7182 u8 reserved_1[0x18]; 7183 u8 counter_set_id[0x8]; 7184 7185 u8 reserved_2[0x20]; 7186 }; 7187 7188 struct mlx5_ifc_alloc_q_counter_in_bits { 7189 u8 opcode[0x10]; 7190 u8 reserved_0[0x10]; 7191 7192 u8 reserved_1[0x10]; 7193 u8 op_mod[0x10]; 7194 7195 u8 reserved_2[0x40]; 7196 }; 7197 7198 struct mlx5_ifc_alloc_pd_out_bits { 7199 u8 status[0x8]; 7200 u8 reserved_0[0x18]; 7201 7202 u8 syndrome[0x20]; 7203 7204 u8 reserved_1[0x8]; 7205 u8 pd[0x18]; 7206 7207 u8 reserved_2[0x20]; 7208 }; 7209 7210 struct mlx5_ifc_alloc_pd_in_bits { 7211 u8 opcode[0x10]; 7212 u8 reserved_0[0x10]; 7213 7214 u8 reserved_1[0x10]; 7215 u8 op_mod[0x10]; 7216 7217 u8 reserved_2[0x40]; 7218 }; 7219 7220 struct mlx5_ifc_alloc_flow_counter_out_bits { 7221 u8 status[0x8]; 7222 u8 reserved_0[0x18]; 7223 7224 u8 syndrome[0x20]; 7225 7226 u8 reserved_1[0x10]; 7227 u8 flow_counter_id[0x10]; 7228 7229 u8 reserved_2[0x20]; 7230 }; 7231 7232 struct mlx5_ifc_alloc_flow_counter_in_bits { 7233 u8 opcode[0x10]; 7234 u8 reserved_0[0x10]; 7235 7236 u8 reserved_1[0x10]; 7237 u8 op_mod[0x10]; 7238 7239 u8 reserved_2[0x40]; 7240 }; 7241 7242 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7243 u8 status[0x8]; 7244 u8 reserved_0[0x18]; 7245 7246 u8 syndrome[0x20]; 7247 7248 u8 reserved_1[0x40]; 7249 }; 7250 7251 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7252 u8 opcode[0x10]; 7253 u8 reserved_0[0x10]; 7254 7255 u8 reserved_1[0x10]; 7256 u8 op_mod[0x10]; 7257 7258 u8 reserved_2[0x20]; 7259 7260 u8 reserved_3[0x10]; 7261 u8 vxlan_udp_port[0x10]; 7262 }; 7263 7264 struct mlx5_ifc_activate_tracer_out_bits { 7265 u8 status[0x8]; 7266 u8 reserved_0[0x18]; 7267 7268 u8 syndrome[0x20]; 7269 7270 u8 reserved_1[0x40]; 7271 }; 7272 7273 struct mlx5_ifc_activate_tracer_in_bits { 7274 u8 opcode[0x10]; 7275 u8 reserved_0[0x10]; 7276 7277 u8 reserved_1[0x10]; 7278 u8 op_mod[0x10]; 7279 7280 u8 mkey[0x20]; 7281 7282 u8 reserved_2[0x20]; 7283 }; 7284 7285 struct mlx5_ifc_set_rate_limit_out_bits { 7286 u8 status[0x8]; 7287 u8 reserved_at_8[0x18]; 7288 7289 u8 syndrome[0x20]; 7290 7291 u8 reserved_at_40[0x40]; 7292 }; 7293 7294 struct mlx5_ifc_set_rate_limit_in_bits { 7295 u8 opcode[0x10]; 7296 u8 reserved_at_10[0x10]; 7297 7298 u8 reserved_at_20[0x10]; 7299 u8 op_mod[0x10]; 7300 7301 u8 reserved_at_40[0x10]; 7302 u8 rate_limit_index[0x10]; 7303 7304 u8 reserved_at_60[0x20]; 7305 7306 u8 rate_limit[0x20]; 7307 u8 burst_upper_bound[0x20]; 7308 }; 7309 7310 struct mlx5_ifc_access_register_out_bits { 7311 u8 status[0x8]; 7312 u8 reserved_0[0x18]; 7313 7314 u8 syndrome[0x20]; 7315 7316 u8 reserved_1[0x40]; 7317 7318 u8 register_data[0][0x20]; 7319 }; 7320 7321 enum { 7322 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7323 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7324 }; 7325 7326 struct mlx5_ifc_access_register_in_bits { 7327 u8 opcode[0x10]; 7328 u8 reserved_0[0x10]; 7329 7330 u8 reserved_1[0x10]; 7331 u8 op_mod[0x10]; 7332 7333 u8 reserved_2[0x10]; 7334 u8 register_id[0x10]; 7335 7336 u8 argument[0x20]; 7337 7338 u8 register_data[0][0x20]; 7339 }; 7340 7341 struct mlx5_ifc_sltp_reg_bits { 7342 u8 status[0x4]; 7343 u8 version[0x4]; 7344 u8 local_port[0x8]; 7345 u8 pnat[0x2]; 7346 u8 reserved_0[0x2]; 7347 u8 lane[0x4]; 7348 u8 reserved_1[0x8]; 7349 7350 u8 reserved_2[0x20]; 7351 7352 u8 reserved_3[0x7]; 7353 u8 polarity[0x1]; 7354 u8 ob_tap0[0x8]; 7355 u8 ob_tap1[0x8]; 7356 u8 ob_tap2[0x8]; 7357 7358 u8 reserved_4[0xc]; 7359 u8 ob_preemp_mode[0x4]; 7360 u8 ob_reg[0x8]; 7361 u8 ob_bias[0x8]; 7362 7363 u8 reserved_5[0x20]; 7364 }; 7365 7366 struct mlx5_ifc_slrp_reg_bits { 7367 u8 status[0x4]; 7368 u8 version[0x4]; 7369 u8 local_port[0x8]; 7370 u8 pnat[0x2]; 7371 u8 reserved_0[0x2]; 7372 u8 lane[0x4]; 7373 u8 reserved_1[0x8]; 7374 7375 u8 ib_sel[0x2]; 7376 u8 reserved_2[0x11]; 7377 u8 dp_sel[0x1]; 7378 u8 dp90sel[0x4]; 7379 u8 mix90phase[0x8]; 7380 7381 u8 ffe_tap0[0x8]; 7382 u8 ffe_tap1[0x8]; 7383 u8 ffe_tap2[0x8]; 7384 u8 ffe_tap3[0x8]; 7385 7386 u8 ffe_tap4[0x8]; 7387 u8 ffe_tap5[0x8]; 7388 u8 ffe_tap6[0x8]; 7389 u8 ffe_tap7[0x8]; 7390 7391 u8 ffe_tap8[0x8]; 7392 u8 mixerbias_tap_amp[0x8]; 7393 u8 reserved_3[0x7]; 7394 u8 ffe_tap_en[0x9]; 7395 7396 u8 ffe_tap_offset0[0x8]; 7397 u8 ffe_tap_offset1[0x8]; 7398 u8 slicer_offset0[0x10]; 7399 7400 u8 mixer_offset0[0x10]; 7401 u8 mixer_offset1[0x10]; 7402 7403 u8 mixerbgn_inp[0x8]; 7404 u8 mixerbgn_inn[0x8]; 7405 u8 mixerbgn_refp[0x8]; 7406 u8 mixerbgn_refn[0x8]; 7407 7408 u8 sel_slicer_lctrl_h[0x1]; 7409 u8 sel_slicer_lctrl_l[0x1]; 7410 u8 reserved_4[0x1]; 7411 u8 ref_mixer_vreg[0x5]; 7412 u8 slicer_gctrl[0x8]; 7413 u8 lctrl_input[0x8]; 7414 u8 mixer_offset_cm1[0x8]; 7415 7416 u8 common_mode[0x6]; 7417 u8 reserved_5[0x1]; 7418 u8 mixer_offset_cm0[0x9]; 7419 u8 reserved_6[0x7]; 7420 u8 slicer_offset_cm[0x9]; 7421 }; 7422 7423 struct mlx5_ifc_slrg_reg_bits { 7424 u8 status[0x4]; 7425 u8 version[0x4]; 7426 u8 local_port[0x8]; 7427 u8 pnat[0x2]; 7428 u8 reserved_0[0x2]; 7429 u8 lane[0x4]; 7430 u8 reserved_1[0x8]; 7431 7432 u8 time_to_link_up[0x10]; 7433 u8 reserved_2[0xc]; 7434 u8 grade_lane_speed[0x4]; 7435 7436 u8 grade_version[0x8]; 7437 u8 grade[0x18]; 7438 7439 u8 reserved_3[0x4]; 7440 u8 height_grade_type[0x4]; 7441 u8 height_grade[0x18]; 7442 7443 u8 height_dz[0x10]; 7444 u8 height_dv[0x10]; 7445 7446 u8 reserved_4[0x10]; 7447 u8 height_sigma[0x10]; 7448 7449 u8 reserved_5[0x20]; 7450 7451 u8 reserved_6[0x4]; 7452 u8 phase_grade_type[0x4]; 7453 u8 phase_grade[0x18]; 7454 7455 u8 reserved_7[0x8]; 7456 u8 phase_eo_pos[0x8]; 7457 u8 reserved_8[0x8]; 7458 u8 phase_eo_neg[0x8]; 7459 7460 u8 ffe_set_tested[0x10]; 7461 u8 test_errors_per_lane[0x10]; 7462 }; 7463 7464 struct mlx5_ifc_pvlc_reg_bits { 7465 u8 reserved_0[0x8]; 7466 u8 local_port[0x8]; 7467 u8 reserved_1[0x10]; 7468 7469 u8 reserved_2[0x1c]; 7470 u8 vl_hw_cap[0x4]; 7471 7472 u8 reserved_3[0x1c]; 7473 u8 vl_admin[0x4]; 7474 7475 u8 reserved_4[0x1c]; 7476 u8 vl_operational[0x4]; 7477 }; 7478 7479 struct mlx5_ifc_pude_reg_bits { 7480 u8 swid[0x8]; 7481 u8 local_port[0x8]; 7482 u8 reserved_0[0x4]; 7483 u8 admin_status[0x4]; 7484 u8 reserved_1[0x4]; 7485 u8 oper_status[0x4]; 7486 7487 u8 reserved_2[0x60]; 7488 }; 7489 7490 enum { 7491 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 7492 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 7493 }; 7494 7495 struct mlx5_ifc_ptys_reg_bits { 7496 u8 reserved_0[0x1]; 7497 u8 an_disable_admin[0x1]; 7498 u8 an_disable_cap[0x1]; 7499 u8 reserved_1[0x4]; 7500 u8 force_tx_aba_param[0x1]; 7501 u8 local_port[0x8]; 7502 u8 reserved_2[0xd]; 7503 u8 proto_mask[0x3]; 7504 7505 u8 an_status[0x4]; 7506 u8 reserved_3[0xc]; 7507 u8 data_rate_oper[0x10]; 7508 7509 u8 fc_proto_capability[0x20]; 7510 7511 u8 eth_proto_capability[0x20]; 7512 7513 u8 ib_link_width_capability[0x10]; 7514 u8 ib_proto_capability[0x10]; 7515 7516 u8 fc_proto_admin[0x20]; 7517 7518 u8 eth_proto_admin[0x20]; 7519 7520 u8 ib_link_width_admin[0x10]; 7521 u8 ib_proto_admin[0x10]; 7522 7523 u8 fc_proto_oper[0x20]; 7524 7525 u8 eth_proto_oper[0x20]; 7526 7527 u8 ib_link_width_oper[0x10]; 7528 u8 ib_proto_oper[0x10]; 7529 7530 u8 reserved_4[0x20]; 7531 7532 u8 eth_proto_lp_advertise[0x20]; 7533 7534 u8 reserved_5[0x60]; 7535 }; 7536 7537 struct mlx5_ifc_ptas_reg_bits { 7538 u8 reserved_0[0x20]; 7539 7540 u8 algorithm_options[0x10]; 7541 u8 reserved_1[0x4]; 7542 u8 repetitions_mode[0x4]; 7543 u8 num_of_repetitions[0x8]; 7544 7545 u8 grade_version[0x8]; 7546 u8 height_grade_type[0x4]; 7547 u8 phase_grade_type[0x4]; 7548 u8 height_grade_weight[0x8]; 7549 u8 phase_grade_weight[0x8]; 7550 7551 u8 gisim_measure_bits[0x10]; 7552 u8 adaptive_tap_measure_bits[0x10]; 7553 7554 u8 ber_bath_high_error_threshold[0x10]; 7555 u8 ber_bath_mid_error_threshold[0x10]; 7556 7557 u8 ber_bath_low_error_threshold[0x10]; 7558 u8 one_ratio_high_threshold[0x10]; 7559 7560 u8 one_ratio_high_mid_threshold[0x10]; 7561 u8 one_ratio_low_mid_threshold[0x10]; 7562 7563 u8 one_ratio_low_threshold[0x10]; 7564 u8 ndeo_error_threshold[0x10]; 7565 7566 u8 mixer_offset_step_size[0x10]; 7567 u8 reserved_2[0x8]; 7568 u8 mix90_phase_for_voltage_bath[0x8]; 7569 7570 u8 mixer_offset_start[0x10]; 7571 u8 mixer_offset_end[0x10]; 7572 7573 u8 reserved_3[0x15]; 7574 u8 ber_test_time[0xb]; 7575 }; 7576 7577 struct mlx5_ifc_pspa_reg_bits { 7578 u8 swid[0x8]; 7579 u8 local_port[0x8]; 7580 u8 sub_port[0x8]; 7581 u8 reserved_0[0x8]; 7582 7583 u8 reserved_1[0x20]; 7584 }; 7585 7586 struct mlx5_ifc_ppsc_reg_bits { 7587 u8 reserved_0[0x8]; 7588 u8 local_port[0x8]; 7589 u8 reserved_1[0x10]; 7590 7591 u8 reserved_2[0x60]; 7592 7593 u8 reserved_3[0x1c]; 7594 u8 wrps_admin[0x4]; 7595 7596 u8 reserved_4[0x1c]; 7597 u8 wrps_status[0x4]; 7598 7599 u8 up_th_vld[0x1]; 7600 u8 down_th_vld[0x1]; 7601 u8 reserved_5[0x6]; 7602 u8 up_threshold[0x8]; 7603 u8 reserved_6[0x8]; 7604 u8 down_threshold[0x8]; 7605 7606 u8 reserved_7[0x20]; 7607 7608 u8 reserved_8[0x1c]; 7609 u8 srps_admin[0x4]; 7610 7611 u8 reserved_9[0x60]; 7612 }; 7613 7614 struct mlx5_ifc_pplr_reg_bits { 7615 u8 reserved_0[0x8]; 7616 u8 local_port[0x8]; 7617 u8 reserved_1[0x10]; 7618 7619 u8 reserved_2[0x8]; 7620 u8 lb_cap[0x8]; 7621 u8 reserved_3[0x8]; 7622 u8 lb_en[0x8]; 7623 }; 7624 7625 struct mlx5_ifc_pplm_reg_bits { 7626 u8 reserved_0[0x8]; 7627 u8 local_port[0x8]; 7628 u8 reserved_1[0x10]; 7629 7630 u8 reserved_2[0x20]; 7631 7632 u8 port_profile_mode[0x8]; 7633 u8 static_port_profile[0x8]; 7634 u8 active_port_profile[0x8]; 7635 u8 reserved_3[0x8]; 7636 7637 u8 retransmission_active[0x8]; 7638 u8 fec_mode_active[0x18]; 7639 7640 u8 reserved_4[0x10]; 7641 u8 v_100g_fec_override_cap[0x4]; 7642 u8 v_50g_fec_override_cap[0x4]; 7643 u8 v_25g_fec_override_cap[0x4]; 7644 u8 v_10g_40g_fec_override_cap[0x4]; 7645 7646 u8 reserved_5[0x10]; 7647 u8 v_100g_fec_override_admin[0x4]; 7648 u8 v_50g_fec_override_admin[0x4]; 7649 u8 v_25g_fec_override_admin[0x4]; 7650 u8 v_10g_40g_fec_override_admin[0x4]; 7651 }; 7652 7653 struct mlx5_ifc_ppll_reg_bits { 7654 u8 num_pll_groups[0x8]; 7655 u8 pll_group[0x8]; 7656 u8 reserved_0[0x4]; 7657 u8 num_plls[0x4]; 7658 u8 reserved_1[0x8]; 7659 7660 u8 reserved_2[0x1f]; 7661 u8 ae[0x1]; 7662 7663 u8 pll_status[4][0x40]; 7664 }; 7665 7666 struct mlx5_ifc_ppad_reg_bits { 7667 u8 reserved_0[0x3]; 7668 u8 single_mac[0x1]; 7669 u8 reserved_1[0x4]; 7670 u8 local_port[0x8]; 7671 u8 mac_47_32[0x10]; 7672 7673 u8 mac_31_0[0x20]; 7674 7675 u8 reserved_2[0x40]; 7676 }; 7677 7678 struct mlx5_ifc_pmtu_reg_bits { 7679 u8 reserved_0[0x8]; 7680 u8 local_port[0x8]; 7681 u8 reserved_1[0x10]; 7682 7683 u8 max_mtu[0x10]; 7684 u8 reserved_2[0x10]; 7685 7686 u8 admin_mtu[0x10]; 7687 u8 reserved_3[0x10]; 7688 7689 u8 oper_mtu[0x10]; 7690 u8 reserved_4[0x10]; 7691 }; 7692 7693 struct mlx5_ifc_pmpr_reg_bits { 7694 u8 reserved_0[0x8]; 7695 u8 module[0x8]; 7696 u8 reserved_1[0x10]; 7697 7698 u8 reserved_2[0x18]; 7699 u8 attenuation_5g[0x8]; 7700 7701 u8 reserved_3[0x18]; 7702 u8 attenuation_7g[0x8]; 7703 7704 u8 reserved_4[0x18]; 7705 u8 attenuation_12g[0x8]; 7706 }; 7707 7708 struct mlx5_ifc_pmpe_reg_bits { 7709 u8 reserved_0[0x8]; 7710 u8 module[0x8]; 7711 u8 reserved_1[0xc]; 7712 u8 module_status[0x4]; 7713 7714 u8 reserved_2[0x14]; 7715 u8 error_type[0x4]; 7716 u8 reserved_3[0x8]; 7717 7718 u8 reserved_4[0x40]; 7719 }; 7720 7721 struct mlx5_ifc_pmpc_reg_bits { 7722 u8 module_state_updated[32][0x8]; 7723 }; 7724 7725 struct mlx5_ifc_pmlpn_reg_bits { 7726 u8 reserved_0[0x4]; 7727 u8 mlpn_status[0x4]; 7728 u8 local_port[0x8]; 7729 u8 reserved_1[0x10]; 7730 7731 u8 e[0x1]; 7732 u8 reserved_2[0x1f]; 7733 }; 7734 7735 struct mlx5_ifc_pmlp_reg_bits { 7736 u8 rxtx[0x1]; 7737 u8 reserved_0[0x7]; 7738 u8 local_port[0x8]; 7739 u8 reserved_1[0x8]; 7740 u8 width[0x8]; 7741 7742 u8 lane0_module_mapping[0x20]; 7743 7744 u8 lane1_module_mapping[0x20]; 7745 7746 u8 lane2_module_mapping[0x20]; 7747 7748 u8 lane3_module_mapping[0x20]; 7749 7750 u8 reserved_2[0x160]; 7751 }; 7752 7753 struct mlx5_ifc_pmaos_reg_bits { 7754 u8 reserved_0[0x8]; 7755 u8 module[0x8]; 7756 u8 reserved_1[0x4]; 7757 u8 admin_status[0x4]; 7758 u8 reserved_2[0x4]; 7759 u8 oper_status[0x4]; 7760 7761 u8 ase[0x1]; 7762 u8 ee[0x1]; 7763 u8 reserved_3[0x12]; 7764 u8 error_type[0x4]; 7765 u8 reserved_4[0x6]; 7766 u8 e[0x2]; 7767 7768 u8 reserved_5[0x40]; 7769 }; 7770 7771 struct mlx5_ifc_plpc_reg_bits { 7772 u8 reserved_0[0x4]; 7773 u8 profile_id[0xc]; 7774 u8 reserved_1[0x4]; 7775 u8 proto_mask[0x4]; 7776 u8 reserved_2[0x8]; 7777 7778 u8 reserved_3[0x10]; 7779 u8 lane_speed[0x10]; 7780 7781 u8 reserved_4[0x17]; 7782 u8 lpbf[0x1]; 7783 u8 fec_mode_policy[0x8]; 7784 7785 u8 retransmission_capability[0x8]; 7786 u8 fec_mode_capability[0x18]; 7787 7788 u8 retransmission_support_admin[0x8]; 7789 u8 fec_mode_support_admin[0x18]; 7790 7791 u8 retransmission_request_admin[0x8]; 7792 u8 fec_mode_request_admin[0x18]; 7793 7794 u8 reserved_5[0x80]; 7795 }; 7796 7797 struct mlx5_ifc_pll_status_data_bits { 7798 u8 reserved_0[0x1]; 7799 u8 lock_cal[0x1]; 7800 u8 lock_status[0x2]; 7801 u8 reserved_1[0x2]; 7802 u8 algo_f_ctrl[0xa]; 7803 u8 analog_algo_num_var[0x6]; 7804 u8 f_ctrl_measure[0xa]; 7805 7806 u8 reserved_2[0x2]; 7807 u8 analog_var[0x6]; 7808 u8 reserved_3[0x2]; 7809 u8 high_var[0x6]; 7810 u8 reserved_4[0x2]; 7811 u8 low_var[0x6]; 7812 u8 reserved_5[0x2]; 7813 u8 mid_val[0x6]; 7814 }; 7815 7816 struct mlx5_ifc_plib_reg_bits { 7817 u8 reserved_0[0x8]; 7818 u8 local_port[0x8]; 7819 u8 reserved_1[0x8]; 7820 u8 ib_port[0x8]; 7821 7822 u8 reserved_2[0x60]; 7823 }; 7824 7825 struct mlx5_ifc_plbf_reg_bits { 7826 u8 reserved_0[0x8]; 7827 u8 local_port[0x8]; 7828 u8 reserved_1[0xd]; 7829 u8 lbf_mode[0x3]; 7830 7831 u8 reserved_2[0x20]; 7832 }; 7833 7834 struct mlx5_ifc_pipg_reg_bits { 7835 u8 reserved_0[0x8]; 7836 u8 local_port[0x8]; 7837 u8 reserved_1[0x10]; 7838 7839 u8 dic[0x1]; 7840 u8 reserved_2[0x19]; 7841 u8 ipg[0x4]; 7842 u8 reserved_3[0x2]; 7843 }; 7844 7845 struct mlx5_ifc_pifr_reg_bits { 7846 u8 reserved_0[0x8]; 7847 u8 local_port[0x8]; 7848 u8 reserved_1[0x10]; 7849 7850 u8 reserved_2[0xe0]; 7851 7852 u8 port_filter[8][0x20]; 7853 7854 u8 port_filter_update_en[8][0x20]; 7855 }; 7856 7857 struct mlx5_ifc_phys_layer_cntrs_bits { 7858 u8 time_since_last_clear_high[0x20]; 7859 7860 u8 time_since_last_clear_low[0x20]; 7861 7862 u8 symbol_errors_high[0x20]; 7863 7864 u8 symbol_errors_low[0x20]; 7865 7866 u8 sync_headers_errors_high[0x20]; 7867 7868 u8 sync_headers_errors_low[0x20]; 7869 7870 u8 edpl_bip_errors_lane0_high[0x20]; 7871 7872 u8 edpl_bip_errors_lane0_low[0x20]; 7873 7874 u8 edpl_bip_errors_lane1_high[0x20]; 7875 7876 u8 edpl_bip_errors_lane1_low[0x20]; 7877 7878 u8 edpl_bip_errors_lane2_high[0x20]; 7879 7880 u8 edpl_bip_errors_lane2_low[0x20]; 7881 7882 u8 edpl_bip_errors_lane3_high[0x20]; 7883 7884 u8 edpl_bip_errors_lane3_low[0x20]; 7885 7886 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 7887 7888 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 7889 7890 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 7891 7892 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 7893 7894 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 7895 7896 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 7897 7898 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 7899 7900 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 7901 7902 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 7903 7904 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 7905 7906 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 7907 7908 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 7909 7910 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 7911 7912 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 7913 7914 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 7915 7916 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 7917 7918 u8 rs_fec_corrected_blocks_high[0x20]; 7919 7920 u8 rs_fec_corrected_blocks_low[0x20]; 7921 7922 u8 rs_fec_uncorrectable_blocks_high[0x20]; 7923 7924 u8 rs_fec_uncorrectable_blocks_low[0x20]; 7925 7926 u8 rs_fec_no_errors_blocks_high[0x20]; 7927 7928 u8 rs_fec_no_errors_blocks_low[0x20]; 7929 7930 u8 rs_fec_single_error_blocks_high[0x20]; 7931 7932 u8 rs_fec_single_error_blocks_low[0x20]; 7933 7934 u8 rs_fec_corrected_symbols_total_high[0x20]; 7935 7936 u8 rs_fec_corrected_symbols_total_low[0x20]; 7937 7938 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 7939 7940 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 7941 7942 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 7943 7944 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 7945 7946 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 7947 7948 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 7949 7950 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 7951 7952 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 7953 7954 u8 link_down_events[0x20]; 7955 7956 u8 successful_recovery_events[0x20]; 7957 7958 u8 reserved_0[0x180]; 7959 }; 7960 7961 struct mlx5_ifc_infiniband_port_cntrs_bits { 7962 u8 symbol_error_counter[0x10]; 7963 u8 link_error_recovery_counter[0x8]; 7964 u8 link_downed_counter[0x8]; 7965 7966 u8 port_rcv_errors[0x10]; 7967 u8 port_rcv_remote_physical_errors[0x10]; 7968 7969 u8 port_rcv_switch_relay_errors[0x10]; 7970 u8 port_xmit_discards[0x10]; 7971 7972 u8 port_xmit_constraint_errors[0x8]; 7973 u8 port_rcv_constraint_errors[0x8]; 7974 u8 reserved_0[0x8]; 7975 u8 local_link_integrity_errors[0x4]; 7976 u8 excessive_buffer_overrun_errors[0x4]; 7977 7978 u8 reserved_1[0x10]; 7979 u8 vl_15_dropped[0x10]; 7980 7981 u8 port_xmit_data[0x20]; 7982 7983 u8 port_rcv_data[0x20]; 7984 7985 u8 port_xmit_pkts[0x20]; 7986 7987 u8 port_rcv_pkts[0x20]; 7988 7989 u8 port_xmit_wait[0x20]; 7990 7991 u8 reserved_2[0x680]; 7992 }; 7993 7994 struct mlx5_ifc_phrr_reg_bits { 7995 u8 clr[0x1]; 7996 u8 reserved_0[0x7]; 7997 u8 local_port[0x8]; 7998 u8 reserved_1[0x10]; 7999 8000 u8 hist_group[0x8]; 8001 u8 reserved_2[0x10]; 8002 u8 hist_id[0x8]; 8003 8004 u8 reserved_3[0x40]; 8005 8006 u8 time_since_last_clear_high[0x20]; 8007 8008 u8 time_since_last_clear_low[0x20]; 8009 8010 u8 bin[10][0x20]; 8011 }; 8012 8013 struct mlx5_ifc_phbr_for_prio_reg_bits { 8014 u8 reserved_0[0x18]; 8015 u8 prio[0x8]; 8016 }; 8017 8018 struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8019 u8 reserved_0[0x18]; 8020 u8 tclass[0x8]; 8021 }; 8022 8023 struct mlx5_ifc_phbr_binding_reg_bits { 8024 u8 opcode[0x4]; 8025 u8 reserved_0[0x4]; 8026 u8 local_port[0x8]; 8027 u8 pnat[0x2]; 8028 u8 reserved_1[0xe]; 8029 8030 u8 hist_group[0x8]; 8031 u8 reserved_2[0x10]; 8032 u8 hist_id[0x8]; 8033 8034 u8 reserved_3[0x10]; 8035 u8 hist_type[0x10]; 8036 8037 u8 hist_parameters[0x20]; 8038 8039 u8 hist_min_value[0x20]; 8040 8041 u8 hist_max_value[0x20]; 8042 8043 u8 sample_time[0x20]; 8044 }; 8045 8046 enum { 8047 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 8048 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 8049 }; 8050 8051 struct mlx5_ifc_pfcc_reg_bits { 8052 u8 dcbx_operation_type[0x2]; 8053 u8 cap_local_admin[0x1]; 8054 u8 cap_remote_admin[0x1]; 8055 u8 reserved_0[0x4]; 8056 u8 local_port[0x8]; 8057 u8 pnat[0x2]; 8058 u8 reserved_1[0xc]; 8059 u8 shl_cap[0x1]; 8060 u8 shl_opr[0x1]; 8061 8062 u8 ppan[0x4]; 8063 u8 reserved_2[0x4]; 8064 u8 prio_mask_tx[0x8]; 8065 u8 reserved_3[0x8]; 8066 u8 prio_mask_rx[0x8]; 8067 8068 u8 pptx[0x1]; 8069 u8 aptx[0x1]; 8070 u8 reserved_4[0x6]; 8071 u8 pfctx[0x8]; 8072 u8 reserved_5[0x8]; 8073 u8 cbftx[0x8]; 8074 8075 u8 pprx[0x1]; 8076 u8 aprx[0x1]; 8077 u8 reserved_6[0x6]; 8078 u8 pfcrx[0x8]; 8079 u8 reserved_7[0x8]; 8080 u8 cbfrx[0x8]; 8081 8082 u8 device_stall_minor_watermark[0x10]; 8083 u8 device_stall_critical_watermark[0x10]; 8084 8085 u8 reserved_8[0x60]; 8086 }; 8087 8088 struct mlx5_ifc_pelc_reg_bits { 8089 u8 op[0x4]; 8090 u8 reserved_0[0x4]; 8091 u8 local_port[0x8]; 8092 u8 reserved_1[0x10]; 8093 8094 u8 op_admin[0x8]; 8095 u8 op_capability[0x8]; 8096 u8 op_request[0x8]; 8097 u8 op_active[0x8]; 8098 8099 u8 admin[0x40]; 8100 8101 u8 capability[0x40]; 8102 8103 u8 request[0x40]; 8104 8105 u8 active[0x40]; 8106 8107 u8 reserved_2[0x80]; 8108 }; 8109 8110 struct mlx5_ifc_peir_reg_bits { 8111 u8 reserved_0[0x8]; 8112 u8 local_port[0x8]; 8113 u8 reserved_1[0x10]; 8114 8115 u8 reserved_2[0xc]; 8116 u8 error_count[0x4]; 8117 u8 reserved_3[0x10]; 8118 8119 u8 reserved_4[0xc]; 8120 u8 lane[0x4]; 8121 u8 reserved_5[0x8]; 8122 u8 error_type[0x8]; 8123 }; 8124 8125 struct mlx5_ifc_pcap_reg_bits { 8126 u8 reserved_0[0x8]; 8127 u8 local_port[0x8]; 8128 u8 reserved_1[0x10]; 8129 8130 u8 port_capability_mask[4][0x20]; 8131 }; 8132 8133 struct mlx5_ifc_pbmc_reg_bits { 8134 u8 reserved_0[0x8]; 8135 u8 local_port[0x8]; 8136 u8 reserved_1[0x10]; 8137 8138 u8 xoff_timer_value[0x10]; 8139 u8 xoff_refresh[0x10]; 8140 8141 u8 reserved_2[0x10]; 8142 u8 port_buffer_size[0x10]; 8143 8144 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8145 8146 u8 reserved_3[0x40]; 8147 8148 u8 port_shared_buffer[0x40]; 8149 }; 8150 8151 struct mlx5_ifc_paos_reg_bits { 8152 u8 swid[0x8]; 8153 u8 local_port[0x8]; 8154 u8 reserved_0[0x4]; 8155 u8 admin_status[0x4]; 8156 u8 reserved_1[0x4]; 8157 u8 oper_status[0x4]; 8158 8159 u8 ase[0x1]; 8160 u8 ee[0x1]; 8161 u8 reserved_2[0x1c]; 8162 u8 e[0x2]; 8163 8164 u8 reserved_3[0x40]; 8165 }; 8166 8167 struct mlx5_ifc_pamp_reg_bits { 8168 u8 reserved_0[0x8]; 8169 u8 opamp_group[0x8]; 8170 u8 reserved_1[0xc]; 8171 u8 opamp_group_type[0x4]; 8172 8173 u8 start_index[0x10]; 8174 u8 reserved_2[0x4]; 8175 u8 num_of_indices[0xc]; 8176 8177 u8 index_data[18][0x10]; 8178 }; 8179 8180 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 8181 u8 llr_rx_cells_high[0x20]; 8182 8183 u8 llr_rx_cells_low[0x20]; 8184 8185 u8 llr_rx_error_high[0x20]; 8186 8187 u8 llr_rx_error_low[0x20]; 8188 8189 u8 llr_rx_crc_error_high[0x20]; 8190 8191 u8 llr_rx_crc_error_low[0x20]; 8192 8193 u8 llr_tx_cells_high[0x20]; 8194 8195 u8 llr_tx_cells_low[0x20]; 8196 8197 u8 llr_tx_ret_cells_high[0x20]; 8198 8199 u8 llr_tx_ret_cells_low[0x20]; 8200 8201 u8 llr_tx_ret_events_high[0x20]; 8202 8203 u8 llr_tx_ret_events_low[0x20]; 8204 8205 u8 reserved_0[0x640]; 8206 }; 8207 8208 struct mlx5_ifc_lane_2_module_mapping_bits { 8209 u8 reserved_0[0x6]; 8210 u8 rx_lane[0x2]; 8211 u8 reserved_1[0x6]; 8212 u8 tx_lane[0x2]; 8213 u8 reserved_2[0x8]; 8214 u8 module[0x8]; 8215 }; 8216 8217 struct mlx5_ifc_eth_per_traffic_class_layout_bits { 8218 u8 transmit_queue_high[0x20]; 8219 8220 u8 transmit_queue_low[0x20]; 8221 8222 u8 reserved_0[0x780]; 8223 }; 8224 8225 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 8226 u8 no_buffer_discard_uc_high[0x20]; 8227 8228 u8 no_buffer_discard_uc_low[0x20]; 8229 8230 u8 wred_discard_high[0x20]; 8231 8232 u8 wred_discard_low[0x20]; 8233 8234 u8 reserved_0[0x740]; 8235 }; 8236 8237 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 8238 u8 rx_octets_high[0x20]; 8239 8240 u8 rx_octets_low[0x20]; 8241 8242 u8 reserved_0[0xc0]; 8243 8244 u8 rx_frames_high[0x20]; 8245 8246 u8 rx_frames_low[0x20]; 8247 8248 u8 tx_octets_high[0x20]; 8249 8250 u8 tx_octets_low[0x20]; 8251 8252 u8 reserved_1[0xc0]; 8253 8254 u8 tx_frames_high[0x20]; 8255 8256 u8 tx_frames_low[0x20]; 8257 8258 u8 rx_pause_high[0x20]; 8259 8260 u8 rx_pause_low[0x20]; 8261 8262 u8 rx_pause_duration_high[0x20]; 8263 8264 u8 rx_pause_duration_low[0x20]; 8265 8266 u8 tx_pause_high[0x20]; 8267 8268 u8 tx_pause_low[0x20]; 8269 8270 u8 tx_pause_duration_high[0x20]; 8271 8272 u8 tx_pause_duration_low[0x20]; 8273 8274 u8 rx_pause_transition_high[0x20]; 8275 8276 u8 rx_pause_transition_low[0x20]; 8277 8278 u8 rx_discards_high[0x20]; 8279 8280 u8 rx_discards_low[0x20]; 8281 8282 u8 device_stall_minor_watermark_cnt_high[0x20]; 8283 8284 u8 device_stall_minor_watermark_cnt_low[0x20]; 8285 8286 u8 device_stall_critical_watermark_cnt_high[0x20]; 8287 8288 u8 device_stall_critical_watermark_cnt_low[0x20]; 8289 8290 u8 reserved_2[0x340]; 8291 }; 8292 8293 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 8294 u8 port_transmit_wait_high[0x20]; 8295 8296 u8 port_transmit_wait_low[0x20]; 8297 8298 u8 ecn_marked_high[0x20]; 8299 8300 u8 ecn_marked_low[0x20]; 8301 8302 u8 no_buffer_discard_mc_high[0x20]; 8303 8304 u8 no_buffer_discard_mc_low[0x20]; 8305 8306 u8 reserved_0[0x700]; 8307 }; 8308 8309 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 8310 u8 a_frames_transmitted_ok_high[0x20]; 8311 8312 u8 a_frames_transmitted_ok_low[0x20]; 8313 8314 u8 a_frames_received_ok_high[0x20]; 8315 8316 u8 a_frames_received_ok_low[0x20]; 8317 8318 u8 a_frame_check_sequence_errors_high[0x20]; 8319 8320 u8 a_frame_check_sequence_errors_low[0x20]; 8321 8322 u8 a_alignment_errors_high[0x20]; 8323 8324 u8 a_alignment_errors_low[0x20]; 8325 8326 u8 a_octets_transmitted_ok_high[0x20]; 8327 8328 u8 a_octets_transmitted_ok_low[0x20]; 8329 8330 u8 a_octets_received_ok_high[0x20]; 8331 8332 u8 a_octets_received_ok_low[0x20]; 8333 8334 u8 a_multicast_frames_xmitted_ok_high[0x20]; 8335 8336 u8 a_multicast_frames_xmitted_ok_low[0x20]; 8337 8338 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 8339 8340 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 8341 8342 u8 a_multicast_frames_received_ok_high[0x20]; 8343 8344 u8 a_multicast_frames_received_ok_low[0x20]; 8345 8346 u8 a_broadcast_frames_recieved_ok_high[0x20]; 8347 8348 u8 a_broadcast_frames_recieved_ok_low[0x20]; 8349 8350 u8 a_in_range_length_errors_high[0x20]; 8351 8352 u8 a_in_range_length_errors_low[0x20]; 8353 8354 u8 a_out_of_range_length_field_high[0x20]; 8355 8356 u8 a_out_of_range_length_field_low[0x20]; 8357 8358 u8 a_frame_too_long_errors_high[0x20]; 8359 8360 u8 a_frame_too_long_errors_low[0x20]; 8361 8362 u8 a_symbol_error_during_carrier_high[0x20]; 8363 8364 u8 a_symbol_error_during_carrier_low[0x20]; 8365 8366 u8 a_mac_control_frames_transmitted_high[0x20]; 8367 8368 u8 a_mac_control_frames_transmitted_low[0x20]; 8369 8370 u8 a_mac_control_frames_received_high[0x20]; 8371 8372 u8 a_mac_control_frames_received_low[0x20]; 8373 8374 u8 a_unsupported_opcodes_received_high[0x20]; 8375 8376 u8 a_unsupported_opcodes_received_low[0x20]; 8377 8378 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 8379 8380 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 8381 8382 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 8383 8384 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 8385 8386 u8 reserved_0[0x300]; 8387 }; 8388 8389 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 8390 u8 dot3stats_alignment_errors_high[0x20]; 8391 8392 u8 dot3stats_alignment_errors_low[0x20]; 8393 8394 u8 dot3stats_fcs_errors_high[0x20]; 8395 8396 u8 dot3stats_fcs_errors_low[0x20]; 8397 8398 u8 dot3stats_single_collision_frames_high[0x20]; 8399 8400 u8 dot3stats_single_collision_frames_low[0x20]; 8401 8402 u8 dot3stats_multiple_collision_frames_high[0x20]; 8403 8404 u8 dot3stats_multiple_collision_frames_low[0x20]; 8405 8406 u8 dot3stats_sqe_test_errors_high[0x20]; 8407 8408 u8 dot3stats_sqe_test_errors_low[0x20]; 8409 8410 u8 dot3stats_deferred_transmissions_high[0x20]; 8411 8412 u8 dot3stats_deferred_transmissions_low[0x20]; 8413 8414 u8 dot3stats_late_collisions_high[0x20]; 8415 8416 u8 dot3stats_late_collisions_low[0x20]; 8417 8418 u8 dot3stats_excessive_collisions_high[0x20]; 8419 8420 u8 dot3stats_excessive_collisions_low[0x20]; 8421 8422 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 8423 8424 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 8425 8426 u8 dot3stats_carrier_sense_errors_high[0x20]; 8427 8428 u8 dot3stats_carrier_sense_errors_low[0x20]; 8429 8430 u8 dot3stats_frame_too_longs_high[0x20]; 8431 8432 u8 dot3stats_frame_too_longs_low[0x20]; 8433 8434 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 8435 8436 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 8437 8438 u8 dot3stats_symbol_errors_high[0x20]; 8439 8440 u8 dot3stats_symbol_errors_low[0x20]; 8441 8442 u8 dot3control_in_unknown_opcodes_high[0x20]; 8443 8444 u8 dot3control_in_unknown_opcodes_low[0x20]; 8445 8446 u8 dot3in_pause_frames_high[0x20]; 8447 8448 u8 dot3in_pause_frames_low[0x20]; 8449 8450 u8 dot3out_pause_frames_high[0x20]; 8451 8452 u8 dot3out_pause_frames_low[0x20]; 8453 8454 u8 reserved_0[0x3c0]; 8455 }; 8456 8457 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 8458 u8 if_in_octets_high[0x20]; 8459 8460 u8 if_in_octets_low[0x20]; 8461 8462 u8 if_in_ucast_pkts_high[0x20]; 8463 8464 u8 if_in_ucast_pkts_low[0x20]; 8465 8466 u8 if_in_discards_high[0x20]; 8467 8468 u8 if_in_discards_low[0x20]; 8469 8470 u8 if_in_errors_high[0x20]; 8471 8472 u8 if_in_errors_low[0x20]; 8473 8474 u8 if_in_unknown_protos_high[0x20]; 8475 8476 u8 if_in_unknown_protos_low[0x20]; 8477 8478 u8 if_out_octets_high[0x20]; 8479 8480 u8 if_out_octets_low[0x20]; 8481 8482 u8 if_out_ucast_pkts_high[0x20]; 8483 8484 u8 if_out_ucast_pkts_low[0x20]; 8485 8486 u8 if_out_discards_high[0x20]; 8487 8488 u8 if_out_discards_low[0x20]; 8489 8490 u8 if_out_errors_high[0x20]; 8491 8492 u8 if_out_errors_low[0x20]; 8493 8494 u8 if_in_multicast_pkts_high[0x20]; 8495 8496 u8 if_in_multicast_pkts_low[0x20]; 8497 8498 u8 if_in_broadcast_pkts_high[0x20]; 8499 8500 u8 if_in_broadcast_pkts_low[0x20]; 8501 8502 u8 if_out_multicast_pkts_high[0x20]; 8503 8504 u8 if_out_multicast_pkts_low[0x20]; 8505 8506 u8 if_out_broadcast_pkts_high[0x20]; 8507 8508 u8 if_out_broadcast_pkts_low[0x20]; 8509 8510 u8 reserved_0[0x480]; 8511 }; 8512 8513 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 8514 u8 ether_stats_drop_events_high[0x20]; 8515 8516 u8 ether_stats_drop_events_low[0x20]; 8517 8518 u8 ether_stats_octets_high[0x20]; 8519 8520 u8 ether_stats_octets_low[0x20]; 8521 8522 u8 ether_stats_pkts_high[0x20]; 8523 8524 u8 ether_stats_pkts_low[0x20]; 8525 8526 u8 ether_stats_broadcast_pkts_high[0x20]; 8527 8528 u8 ether_stats_broadcast_pkts_low[0x20]; 8529 8530 u8 ether_stats_multicast_pkts_high[0x20]; 8531 8532 u8 ether_stats_multicast_pkts_low[0x20]; 8533 8534 u8 ether_stats_crc_align_errors_high[0x20]; 8535 8536 u8 ether_stats_crc_align_errors_low[0x20]; 8537 8538 u8 ether_stats_undersize_pkts_high[0x20]; 8539 8540 u8 ether_stats_undersize_pkts_low[0x20]; 8541 8542 u8 ether_stats_oversize_pkts_high[0x20]; 8543 8544 u8 ether_stats_oversize_pkts_low[0x20]; 8545 8546 u8 ether_stats_fragments_high[0x20]; 8547 8548 u8 ether_stats_fragments_low[0x20]; 8549 8550 u8 ether_stats_jabbers_high[0x20]; 8551 8552 u8 ether_stats_jabbers_low[0x20]; 8553 8554 u8 ether_stats_collisions_high[0x20]; 8555 8556 u8 ether_stats_collisions_low[0x20]; 8557 8558 u8 ether_stats_pkts64octets_high[0x20]; 8559 8560 u8 ether_stats_pkts64octets_low[0x20]; 8561 8562 u8 ether_stats_pkts65to127octets_high[0x20]; 8563 8564 u8 ether_stats_pkts65to127octets_low[0x20]; 8565 8566 u8 ether_stats_pkts128to255octets_high[0x20]; 8567 8568 u8 ether_stats_pkts128to255octets_low[0x20]; 8569 8570 u8 ether_stats_pkts256to511octets_high[0x20]; 8571 8572 u8 ether_stats_pkts256to511octets_low[0x20]; 8573 8574 u8 ether_stats_pkts512to1023octets_high[0x20]; 8575 8576 u8 ether_stats_pkts512to1023octets_low[0x20]; 8577 8578 u8 ether_stats_pkts1024to1518octets_high[0x20]; 8579 8580 u8 ether_stats_pkts1024to1518octets_low[0x20]; 8581 8582 u8 ether_stats_pkts1519to2047octets_high[0x20]; 8583 8584 u8 ether_stats_pkts1519to2047octets_low[0x20]; 8585 8586 u8 ether_stats_pkts2048to4095octets_high[0x20]; 8587 8588 u8 ether_stats_pkts2048to4095octets_low[0x20]; 8589 8590 u8 ether_stats_pkts4096to8191octets_high[0x20]; 8591 8592 u8 ether_stats_pkts4096to8191octets_low[0x20]; 8593 8594 u8 ether_stats_pkts8192to10239octets_high[0x20]; 8595 8596 u8 ether_stats_pkts8192to10239octets_low[0x20]; 8597 8598 u8 reserved_0[0x280]; 8599 }; 8600 8601 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 8602 u8 symbol_error_counter[0x10]; 8603 u8 link_error_recovery_counter[0x8]; 8604 u8 link_downed_counter[0x8]; 8605 8606 u8 port_rcv_errors[0x10]; 8607 u8 port_rcv_remote_physical_errors[0x10]; 8608 8609 u8 port_rcv_switch_relay_errors[0x10]; 8610 u8 port_xmit_discards[0x10]; 8611 8612 u8 port_xmit_constraint_errors[0x8]; 8613 u8 port_rcv_constraint_errors[0x8]; 8614 u8 reserved_0[0x8]; 8615 u8 local_link_integrity_errors[0x4]; 8616 u8 excessive_buffer_overrun_errors[0x4]; 8617 8618 u8 reserved_1[0x10]; 8619 u8 vl_15_dropped[0x10]; 8620 8621 u8 port_xmit_data[0x20]; 8622 8623 u8 port_rcv_data[0x20]; 8624 8625 u8 port_xmit_pkts[0x20]; 8626 8627 u8 port_rcv_pkts[0x20]; 8628 8629 u8 port_xmit_wait[0x20]; 8630 8631 u8 reserved_2[0x680]; 8632 }; 8633 8634 struct mlx5_ifc_trc_tlb_reg_bits { 8635 u8 reserved_0[0x80]; 8636 8637 u8 tlb_addr[0][0x40]; 8638 }; 8639 8640 struct mlx5_ifc_trc_read_fifo_reg_bits { 8641 u8 reserved_0[0x10]; 8642 u8 requested_event_num[0x10]; 8643 8644 u8 reserved_1[0x20]; 8645 8646 u8 reserved_2[0x10]; 8647 u8 acual_event_num[0x10]; 8648 8649 u8 reserved_3[0x20]; 8650 8651 u8 event[0][0x40]; 8652 }; 8653 8654 struct mlx5_ifc_trc_lock_reg_bits { 8655 u8 reserved_0[0x1f]; 8656 u8 lock[0x1]; 8657 8658 u8 reserved_1[0x60]; 8659 }; 8660 8661 struct mlx5_ifc_trc_filter_reg_bits { 8662 u8 status[0x1]; 8663 u8 reserved_0[0xf]; 8664 u8 filter_index[0x10]; 8665 8666 u8 reserved_1[0x20]; 8667 8668 u8 filter_val[0x20]; 8669 8670 u8 reserved_2[0x1a0]; 8671 }; 8672 8673 struct mlx5_ifc_trc_event_reg_bits { 8674 u8 status[0x1]; 8675 u8 reserved_0[0xf]; 8676 u8 event_index[0x10]; 8677 8678 u8 reserved_1[0x20]; 8679 8680 u8 event_id[0x20]; 8681 8682 u8 event_selector_val[0x10]; 8683 u8 event_selector_size[0x10]; 8684 8685 u8 reserved_2[0x180]; 8686 }; 8687 8688 struct mlx5_ifc_trc_conf_reg_bits { 8689 u8 limit_en[0x1]; 8690 u8 reserved_0[0x3]; 8691 u8 dump_mode[0x4]; 8692 u8 reserved_1[0x15]; 8693 u8 state[0x3]; 8694 8695 u8 reserved_2[0x20]; 8696 8697 u8 limit_event_index[0x20]; 8698 8699 u8 mkey[0x20]; 8700 8701 u8 fifo_ready_ev_num[0x20]; 8702 8703 u8 reserved_3[0x160]; 8704 }; 8705 8706 struct mlx5_ifc_trc_cap_reg_bits { 8707 u8 reserved_0[0x18]; 8708 u8 dump_mode[0x8]; 8709 8710 u8 reserved_1[0x20]; 8711 8712 u8 num_of_events[0x10]; 8713 u8 num_of_filters[0x10]; 8714 8715 u8 fifo_size[0x20]; 8716 8717 u8 tlb_size[0x10]; 8718 u8 event_size[0x10]; 8719 8720 u8 reserved_2[0x160]; 8721 }; 8722 8723 struct mlx5_ifc_set_node_in_bits { 8724 u8 node_description[64][0x8]; 8725 }; 8726 8727 struct mlx5_ifc_register_power_settings_bits { 8728 u8 reserved_0[0x18]; 8729 u8 power_settings_level[0x8]; 8730 8731 u8 reserved_1[0x60]; 8732 }; 8733 8734 struct mlx5_ifc_register_host_endianess_bits { 8735 u8 he[0x1]; 8736 u8 reserved_0[0x1f]; 8737 8738 u8 reserved_1[0x60]; 8739 }; 8740 8741 struct mlx5_ifc_register_diag_buffer_ctrl_bits { 8742 u8 physical_address[0x40]; 8743 }; 8744 8745 struct mlx5_ifc_qtct_reg_bits { 8746 u8 operation_type[0x2]; 8747 u8 cap_local_admin[0x1]; 8748 u8 cap_remote_admin[0x1]; 8749 u8 reserved_0[0x4]; 8750 u8 port_number[0x8]; 8751 u8 reserved_1[0xd]; 8752 u8 prio[0x3]; 8753 8754 u8 reserved_2[0x1d]; 8755 u8 tclass[0x3]; 8756 }; 8757 8758 struct mlx5_ifc_qpdp_reg_bits { 8759 u8 reserved_0[0x8]; 8760 u8 port_number[0x8]; 8761 u8 reserved_1[0x10]; 8762 8763 u8 reserved_2[0x1d]; 8764 u8 pprio[0x3]; 8765 }; 8766 8767 struct mlx5_ifc_port_info_ro_fields_param_bits { 8768 u8 reserved_0[0x8]; 8769 u8 port[0x8]; 8770 u8 max_gid[0x10]; 8771 8772 u8 reserved_1[0x20]; 8773 8774 u8 port_guid[0x40]; 8775 }; 8776 8777 struct mlx5_ifc_nvqc_reg_bits { 8778 u8 type[0x20]; 8779 8780 u8 reserved_0[0x18]; 8781 u8 version[0x4]; 8782 u8 reserved_1[0x2]; 8783 u8 support_wr[0x1]; 8784 u8 support_rd[0x1]; 8785 }; 8786 8787 struct mlx5_ifc_nvia_reg_bits { 8788 u8 reserved_0[0x1d]; 8789 u8 target[0x3]; 8790 8791 u8 reserved_1[0x20]; 8792 }; 8793 8794 struct mlx5_ifc_nvdi_reg_bits { 8795 struct mlx5_ifc_config_item_bits configuration_item_header; 8796 }; 8797 8798 struct mlx5_ifc_nvda_reg_bits { 8799 struct mlx5_ifc_config_item_bits configuration_item_header; 8800 8801 u8 configuration_item_data[0x20]; 8802 }; 8803 8804 struct mlx5_ifc_node_info_ro_fields_param_bits { 8805 u8 system_image_guid[0x40]; 8806 8807 u8 reserved_0[0x40]; 8808 8809 u8 node_guid[0x40]; 8810 8811 u8 reserved_1[0x10]; 8812 u8 max_pkey[0x10]; 8813 8814 u8 reserved_2[0x20]; 8815 }; 8816 8817 struct mlx5_ifc_ets_tcn_config_reg_bits { 8818 u8 g[0x1]; 8819 u8 b[0x1]; 8820 u8 r[0x1]; 8821 u8 reserved_0[0x9]; 8822 u8 group[0x4]; 8823 u8 reserved_1[0x9]; 8824 u8 bw_allocation[0x7]; 8825 8826 u8 reserved_2[0xc]; 8827 u8 max_bw_units[0x4]; 8828 u8 reserved_3[0x8]; 8829 u8 max_bw_value[0x8]; 8830 }; 8831 8832 struct mlx5_ifc_ets_global_config_reg_bits { 8833 u8 reserved_0[0x2]; 8834 u8 r[0x1]; 8835 u8 reserved_1[0x1d]; 8836 8837 u8 reserved_2[0xc]; 8838 u8 max_bw_units[0x4]; 8839 u8 reserved_3[0x8]; 8840 u8 max_bw_value[0x8]; 8841 }; 8842 8843 struct mlx5_ifc_nodnic_mac_filters_bits { 8844 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 8845 8846 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 8847 8848 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 8849 8850 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 8851 8852 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 8853 8854 u8 reserved_0[0xc0]; 8855 }; 8856 8857 struct mlx5_ifc_nodnic_gid_filters_bits { 8858 u8 mgid_filter0[16][0x8]; 8859 8860 u8 mgid_filter1[16][0x8]; 8861 8862 u8 mgid_filter2[16][0x8]; 8863 8864 u8 mgid_filter3[16][0x8]; 8865 }; 8866 8867 enum { 8868 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 8869 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 8870 }; 8871 8872 enum { 8873 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 8874 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 8875 }; 8876 8877 struct mlx5_ifc_nodnic_config_reg_bits { 8878 u8 no_dram_nic_revision[0x8]; 8879 u8 hardware_format[0x8]; 8880 u8 support_receive_filter[0x1]; 8881 u8 support_promisc_filter[0x1]; 8882 u8 support_promisc_multicast_filter[0x1]; 8883 u8 reserved_0[0x2]; 8884 u8 log_working_buffer_size[0x3]; 8885 u8 log_pkey_table_size[0x4]; 8886 u8 reserved_1[0x3]; 8887 u8 num_ports[0x1]; 8888 8889 u8 reserved_2[0x2]; 8890 u8 log_max_ring_size[0x6]; 8891 u8 reserved_3[0x18]; 8892 8893 u8 lkey[0x20]; 8894 8895 u8 cqe_format[0x4]; 8896 u8 reserved_4[0x1c]; 8897 8898 u8 node_guid[0x40]; 8899 8900 u8 reserved_5[0x740]; 8901 8902 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 8903 8904 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 8905 }; 8906 8907 struct mlx5_ifc_vlan_layout_bits { 8908 u8 reserved_0[0x14]; 8909 u8 vlan[0xc]; 8910 8911 u8 reserved_1[0x20]; 8912 }; 8913 8914 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8915 u8 reserved_0[0x20]; 8916 8917 u8 mkey[0x20]; 8918 8919 u8 addressh_63_32[0x20]; 8920 8921 u8 addressl_31_0[0x20]; 8922 }; 8923 8924 struct mlx5_ifc_ud_adrs_vector_bits { 8925 u8 dc_key[0x40]; 8926 8927 u8 ext[0x1]; 8928 u8 reserved_0[0x7]; 8929 u8 destination_qp_dct[0x18]; 8930 8931 u8 static_rate[0x4]; 8932 u8 sl_eth_prio[0x4]; 8933 u8 fl[0x1]; 8934 u8 mlid[0x7]; 8935 u8 rlid_udp_sport[0x10]; 8936 8937 u8 reserved_1[0x20]; 8938 8939 u8 rmac_47_16[0x20]; 8940 8941 u8 rmac_15_0[0x10]; 8942 u8 tclass[0x8]; 8943 u8 hop_limit[0x8]; 8944 8945 u8 reserved_2[0x1]; 8946 u8 grh[0x1]; 8947 u8 reserved_3[0x2]; 8948 u8 src_addr_index[0x8]; 8949 u8 flow_label[0x14]; 8950 8951 u8 rgid_rip[16][0x8]; 8952 }; 8953 8954 struct mlx5_ifc_port_module_event_bits { 8955 u8 reserved_0[0x8]; 8956 u8 module[0x8]; 8957 u8 reserved_1[0xc]; 8958 u8 module_status[0x4]; 8959 8960 u8 reserved_2[0x14]; 8961 u8 error_type[0x4]; 8962 u8 reserved_3[0x8]; 8963 8964 u8 reserved_4[0xa0]; 8965 }; 8966 8967 struct mlx5_ifc_icmd_control_bits { 8968 u8 opcode[0x10]; 8969 u8 status[0x8]; 8970 u8 reserved_0[0x7]; 8971 u8 busy[0x1]; 8972 }; 8973 8974 struct mlx5_ifc_eqe_bits { 8975 u8 reserved_0[0x8]; 8976 u8 event_type[0x8]; 8977 u8 reserved_1[0x8]; 8978 u8 event_sub_type[0x8]; 8979 8980 u8 reserved_2[0xe0]; 8981 8982 union mlx5_ifc_event_auto_bits event_data; 8983 8984 u8 reserved_3[0x10]; 8985 u8 signature[0x8]; 8986 u8 reserved_4[0x7]; 8987 u8 owner[0x1]; 8988 }; 8989 8990 enum { 8991 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8992 }; 8993 8994 struct mlx5_ifc_cmd_queue_entry_bits { 8995 u8 type[0x8]; 8996 u8 reserved_0[0x18]; 8997 8998 u8 input_length[0x20]; 8999 9000 u8 input_mailbox_pointer_63_32[0x20]; 9001 9002 u8 input_mailbox_pointer_31_9[0x17]; 9003 u8 reserved_1[0x9]; 9004 9005 u8 command_input_inline_data[16][0x8]; 9006 9007 u8 command_output_inline_data[16][0x8]; 9008 9009 u8 output_mailbox_pointer_63_32[0x20]; 9010 9011 u8 output_mailbox_pointer_31_9[0x17]; 9012 u8 reserved_2[0x9]; 9013 9014 u8 output_length[0x20]; 9015 9016 u8 token[0x8]; 9017 u8 signature[0x8]; 9018 u8 reserved_3[0x8]; 9019 u8 status[0x7]; 9020 u8 ownership[0x1]; 9021 }; 9022 9023 struct mlx5_ifc_cmd_out_bits { 9024 u8 status[0x8]; 9025 u8 reserved_0[0x18]; 9026 9027 u8 syndrome[0x20]; 9028 9029 u8 command_output[0x20]; 9030 }; 9031 9032 struct mlx5_ifc_cmd_in_bits { 9033 u8 opcode[0x10]; 9034 u8 reserved_0[0x10]; 9035 9036 u8 reserved_1[0x10]; 9037 u8 op_mod[0x10]; 9038 9039 u8 command[0][0x20]; 9040 }; 9041 9042 struct mlx5_ifc_cmd_if_box_bits { 9043 u8 mailbox_data[512][0x8]; 9044 9045 u8 reserved_0[0x180]; 9046 9047 u8 next_pointer_63_32[0x20]; 9048 9049 u8 next_pointer_31_10[0x16]; 9050 u8 reserved_1[0xa]; 9051 9052 u8 block_number[0x20]; 9053 9054 u8 reserved_2[0x8]; 9055 u8 token[0x8]; 9056 u8 ctrl_signature[0x8]; 9057 u8 signature[0x8]; 9058 }; 9059 9060 struct mlx5_ifc_mtt_bits { 9061 u8 ptag_63_32[0x20]; 9062 9063 u8 ptag_31_8[0x18]; 9064 u8 reserved_0[0x6]; 9065 u8 wr_en[0x1]; 9066 u8 rd_en[0x1]; 9067 }; 9068 9069 struct mlx5_ifc_vendor_specific_cap_bits { 9070 u8 type[0x8]; 9071 u8 length[0x8]; 9072 u8 next_pointer[0x8]; 9073 u8 capability_id[0x8]; 9074 9075 u8 status[0x3]; 9076 u8 reserved_0[0xd]; 9077 u8 space[0x10]; 9078 9079 u8 counter[0x20]; 9080 9081 u8 semaphore[0x20]; 9082 9083 u8 flag[0x1]; 9084 u8 reserved_1[0x1]; 9085 u8 address[0x1e]; 9086 9087 u8 data[0x20]; 9088 }; 9089 9090 enum { 9091 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9092 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9093 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9094 }; 9095 9096 enum { 9097 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9098 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9099 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9100 }; 9101 9102 enum { 9103 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 9104 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 9105 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 9106 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 9107 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 9108 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 9109 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 9110 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 9111 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 9112 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 9113 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 9114 }; 9115 9116 struct mlx5_ifc_initial_seg_bits { 9117 u8 fw_rev_minor[0x10]; 9118 u8 fw_rev_major[0x10]; 9119 9120 u8 cmd_interface_rev[0x10]; 9121 u8 fw_rev_subminor[0x10]; 9122 9123 u8 reserved_0[0x40]; 9124 9125 u8 cmdq_phy_addr_63_32[0x20]; 9126 9127 u8 cmdq_phy_addr_31_12[0x14]; 9128 u8 reserved_1[0x2]; 9129 u8 nic_interface[0x2]; 9130 u8 log_cmdq_size[0x4]; 9131 u8 log_cmdq_stride[0x4]; 9132 9133 u8 command_doorbell_vector[0x20]; 9134 9135 u8 reserved_2[0xf00]; 9136 9137 u8 initializing[0x1]; 9138 u8 reserved_3[0x4]; 9139 u8 nic_interface_supported[0x3]; 9140 u8 reserved_4[0x18]; 9141 9142 struct mlx5_ifc_health_buffer_bits health_buffer; 9143 9144 u8 no_dram_nic_offset[0x20]; 9145 9146 u8 reserved_5[0x6de0]; 9147 9148 u8 internal_timer_h[0x20]; 9149 9150 u8 internal_timer_l[0x20]; 9151 9152 u8 reserved_6[0x20]; 9153 9154 u8 reserved_7[0x1f]; 9155 u8 clear_int[0x1]; 9156 9157 u8 health_syndrome[0x8]; 9158 u8 health_counter[0x18]; 9159 9160 u8 reserved_8[0x17fc0]; 9161 }; 9162 9163 union mlx5_ifc_icmd_interface_document_bits { 9164 struct mlx5_ifc_fw_version_bits fw_version; 9165 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 9166 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 9167 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 9168 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 9169 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 9170 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 9171 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 9172 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 9173 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 9174 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 9175 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 9176 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 9177 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 9178 u8 reserved_0[0x42c0]; 9179 }; 9180 9181 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 9182 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9183 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9184 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9185 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9186 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9187 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 9188 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9189 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9190 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 9191 u8 reserved_0[0x7c0]; 9192 }; 9193 9194 struct mlx5_ifc_ppcnt_reg_bits { 9195 u8 swid[0x8]; 9196 u8 local_port[0x8]; 9197 u8 pnat[0x2]; 9198 u8 reserved_0[0x8]; 9199 u8 grp[0x6]; 9200 9201 u8 clr[0x1]; 9202 u8 reserved_1[0x1c]; 9203 u8 prio_tc[0x3]; 9204 9205 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9206 }; 9207 9208 struct mlx5_ifc_pcie_performance_counters_data_layout_bits { 9209 u8 life_time_counter_high[0x20]; 9210 9211 u8 life_time_counter_low[0x20]; 9212 9213 u8 rx_errors[0x20]; 9214 9215 u8 tx_errors[0x20]; 9216 9217 u8 l0_to_recovery_eieos[0x20]; 9218 9219 u8 l0_to_recovery_ts[0x20]; 9220 9221 u8 l0_to_recovery_framing[0x20]; 9222 9223 u8 l0_to_recovery_retrain[0x20]; 9224 9225 u8 crc_error_dllp[0x20]; 9226 9227 u8 crc_error_tlp[0x20]; 9228 9229 u8 reserved_0[0x680]; 9230 }; 9231 9232 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits { 9233 u8 life_time_counter_high[0x20]; 9234 9235 u8 life_time_counter_low[0x20]; 9236 9237 u8 time_to_boot_image_start[0x20]; 9238 9239 u8 time_to_link_image[0x20]; 9240 9241 u8 calibration_time[0x20]; 9242 9243 u8 time_to_first_perst[0x20]; 9244 9245 u8 time_to_detect_state[0x20]; 9246 9247 u8 time_to_l0[0x20]; 9248 9249 u8 time_to_crs_en[0x20]; 9250 9251 u8 time_to_plastic_image_start[0x20]; 9252 9253 u8 time_to_iron_image_start[0x20]; 9254 9255 u8 perst_handler[0x20]; 9256 9257 u8 times_in_l1[0x20]; 9258 9259 u8 times_in_l23[0x20]; 9260 9261 u8 dl_down[0x20]; 9262 9263 u8 config_cycle1usec[0x20]; 9264 9265 u8 config_cycle2to7usec[0x20]; 9266 9267 u8 config_cycle8to15usec[0x20]; 9268 9269 u8 config_cycle16to63usec[0x20]; 9270 9271 u8 config_cycle64usec[0x20]; 9272 9273 u8 correctable_err_msg_sent[0x20]; 9274 9275 u8 non_fatal_err_msg_sent[0x20]; 9276 9277 u8 fatal_err_msg_sent[0x20]; 9278 9279 u8 reserved_0[0x4e0]; 9280 }; 9281 9282 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits { 9283 u8 life_time_counter_high[0x20]; 9284 9285 u8 life_time_counter_low[0x20]; 9286 9287 u8 error_counter_lane0[0x20]; 9288 9289 u8 error_counter_lane1[0x20]; 9290 9291 u8 error_counter_lane2[0x20]; 9292 9293 u8 error_counter_lane3[0x20]; 9294 9295 u8 error_counter_lane4[0x20]; 9296 9297 u8 error_counter_lane5[0x20]; 9298 9299 u8 error_counter_lane6[0x20]; 9300 9301 u8 error_counter_lane7[0x20]; 9302 9303 u8 error_counter_lane8[0x20]; 9304 9305 u8 error_counter_lane9[0x20]; 9306 9307 u8 error_counter_lane10[0x20]; 9308 9309 u8 error_counter_lane11[0x20]; 9310 9311 u8 error_counter_lane12[0x20]; 9312 9313 u8 error_counter_lane13[0x20]; 9314 9315 u8 error_counter_lane14[0x20]; 9316 9317 u8 error_counter_lane15[0x20]; 9318 9319 u8 reserved_0[0x580]; 9320 }; 9321 9322 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits { 9323 struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout; 9324 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout; 9325 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout; 9326 u8 reserved_0[0xf8]; 9327 }; 9328 9329 struct mlx5_ifc_mpcnt_reg_bits { 9330 u8 reserved_0[0x8]; 9331 u8 pcie_index[0x8]; 9332 u8 reserved_1[0xa]; 9333 u8 grp[0x6]; 9334 9335 u8 clr[0x1]; 9336 u8 reserved_2[0x1f]; 9337 9338 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set; 9339 }; 9340 9341 union mlx5_ifc_ports_control_registers_document_bits { 9342 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 9343 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9344 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9345 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9346 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9347 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9348 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 9349 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9350 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9351 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 9352 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 9353 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9354 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 9355 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9356 struct mlx5_ifc_paos_reg_bits paos_reg; 9357 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 9358 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9359 struct mlx5_ifc_peir_reg_bits peir_reg; 9360 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9361 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9362 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 9363 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 9364 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 9365 struct mlx5_ifc_phrr_reg_bits phrr_reg; 9366 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9367 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9368 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9369 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9370 struct mlx5_ifc_plib_reg_bits plib_reg; 9371 struct mlx5_ifc_pll_status_data_bits pll_status_data; 9372 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9373 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9374 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9375 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9376 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9377 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9378 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9379 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9380 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9381 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9382 struct mlx5_ifc_ppll_reg_bits ppll_reg; 9383 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9384 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9385 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9386 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9387 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9388 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9389 struct mlx5_ifc_pude_reg_bits pude_reg; 9390 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9391 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9392 struct mlx5_ifc_slrp_reg_bits slrp_reg; 9393 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9394 u8 reserved_0[0x7880]; 9395 }; 9396 9397 union mlx5_ifc_debug_enhancements_document_bits { 9398 struct mlx5_ifc_health_buffer_bits health_buffer; 9399 u8 reserved_0[0x200]; 9400 }; 9401 9402 union mlx5_ifc_no_dram_nic_document_bits { 9403 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 9404 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 9405 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 9406 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 9407 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 9408 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 9409 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 9410 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 9411 u8 reserved_0[0x3160]; 9412 }; 9413 9414 union mlx5_ifc_uplink_pci_interface_document_bits { 9415 struct mlx5_ifc_initial_seg_bits initial_seg; 9416 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 9417 u8 reserved_0[0x20120]; 9418 }; 9419 9420 9421 #endif /* MLX5_IFC_H */ 9422