xref: /freebsd/sys/dev/mlx5/mlx5_ifc.h (revision 60d717baf2144cf344ec9b47d715ce837b5d46d4)
1  /*-
2   * Copyright (c) 2013-2020, Mellanox Technologies.  All rights reserved.
3   *
4   * Redistribution and use in source and binary forms, with or without
5   * modification, are permitted provided that the following conditions
6   * are met:
7   * 1. Redistributions of source code must retain the above copyright
8   *    notice, this list of conditions and the following disclaimer.
9   * 2. Redistributions in binary form must reproduce the above copyright
10   *    notice, this list of conditions and the following disclaimer in the
11   *    documentation and/or other materials provided with the distribution.
12   *
13   * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14   * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16   * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19   * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20   * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21   * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22   * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23   * SUCH DAMAGE.
24   */
25  
26  #ifndef MLX5_IFC_H
27  #define MLX5_IFC_H
28  
29  #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h>
30  
31  enum {
32  	MLX5_EVENT_TYPE_NOTIFY_ANY				   = 0x0,
33  	MLX5_EVENT_TYPE_COMP                                       = 0x0,
34  	MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
35  	MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
36  	MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
37  	MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
38  	MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
39  	MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
40  	MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
41  	MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
42  	MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
43  	MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
44  	MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
45  	MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
46  	MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
47  	MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
48  	MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
49  	MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
50  	MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
51  	MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
52  	MLX5_EVENT_TYPE_TEMP_WARN_EVENT                            = 0x17,
53  	MLX5_EVENT_TYPE_XRQ_ERROR				   = 0x18,
54  	MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
55  	MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
56  	MLX5_EVENT_TYPE_CODING_PPS_EVENT                           = 0x25,
57  	MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT          = 0x22,
58  	MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
59  	MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
60  	MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
61  	MLX5_EVENT_TYPE_CMD                                        = 0xa,
62  	MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
63  	MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd,
64  	MLX5_EVENT_TYPE_FPGA_ERROR                                 = 0x20,
65  	MLX5_EVENT_TYPE_FPGA_QP_ERROR                              = 0x21,
66  	MLX5_EVENT_TYPE_OBJECT_CHANGE                              = 0x27,
67  };
68  
69  enum {
70  	MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
71  	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
72  	MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
73  	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
74  	MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
75  };
76  
77  enum {
78  	MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
79  };
80  
81  enum {
82  	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
83  	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
84  };
85  
86  enum {
87  	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
88  	MLX5_OBJ_TYPE_MKEY = 0xff01,
89  	MLX5_OBJ_TYPE_QP = 0xff02,
90  	MLX5_OBJ_TYPE_PSV = 0xff03,
91  	MLX5_OBJ_TYPE_RMP = 0xff04,
92  	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
93  	MLX5_OBJ_TYPE_RQ = 0xff06,
94  	MLX5_OBJ_TYPE_SQ = 0xff07,
95  	MLX5_OBJ_TYPE_TIR = 0xff08,
96  	MLX5_OBJ_TYPE_TIS = 0xff09,
97  	MLX5_OBJ_TYPE_DCT = 0xff0a,
98  	MLX5_OBJ_TYPE_XRQ = 0xff0b,
99  	MLX5_OBJ_TYPE_RQT = 0xff0e,
100  	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
101  	MLX5_OBJ_TYPE_CQ = 0xff10,
102  };
103  
104  enum {
105  	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
106  	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
107  	MLX5_CMD_OP_INIT_HCA                      = 0x102,
108  	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
109  	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
110  	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
111  	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
112  	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
113  	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
114  	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
115  	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
116  	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
117  	MLX5_CMD_OP_QUERY_OTHER_HCA_CAP           = 0x10e,
118  	MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP          = 0x10f,
119  	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
120  	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
121  	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
122  	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
123  	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
124  	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
125  	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
126  	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
127  	MLX5_CMD_OP_GEN_EQE                       = 0x304,
128  	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
129  	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
130  	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
131  	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
132  	MLX5_CMD_OP_CREATE_QP                     = 0x500,
133  	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
134  	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
135  	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
136  	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
137  	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
138  	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
139  	MLX5_CMD_OP_2ERR_QP                       = 0x507,
140  	MLX5_CMD_OP_2RST_QP                       = 0x50a,
141  	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
142  	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
143  	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
144  	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
145  	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
146  	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
147  	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
148  	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
149  	MLX5_CMD_OP_ARM_RQ                        = 0x703,
150  	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
151  	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
152  	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
153  	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
154  	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
155  	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
156  	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
157  	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
158  	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
159  	MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
160  	MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
161  	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
162  	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
163  	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
164  	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
165  	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
166  	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
167  	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
168  	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
169  	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
170  
171  	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
172  	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
173  	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
174  	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
175  	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
176  	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
177  	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
178  	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
179  	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
180  	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
181  	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
182  	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
183  	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
184  	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
185  	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
186  	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
187  	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
188  	MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
189  	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
190  	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT     = 0x782,
191  	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT    = 0x783,
192  	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT      = 0x784,
193  	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT     = 0x785,
194  	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
195  	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
196  	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
197  	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
198  	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
199  	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
200  	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
201  	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
202  	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
203  	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
204  	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
205  	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
206  	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
207  	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
208  	MLX5_CMD_OP_NOP                           = 0x80d,
209  	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
210  	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
211  	MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
212  	MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
213  	MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
214  	MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
215  	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
216  	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
217  	MLX5_CMD_OP_QUERY_DIAGNOSTIC_PARAMS       = 0x819,
218  	MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
219  	MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
220  	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
221  	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
222  	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
223  	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
224  	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
225  	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
226  	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
227  	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
228  	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
229  	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
230  	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
231  	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
232  	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
233  	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
234  	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
235  	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
236  	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
237  	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
238  	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
239  	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
240  	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
241  	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
242  	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
243  	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
244  	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
245  	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
246  	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
247  	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
248  	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
249  	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
250  	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
251  	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
252  	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
253  	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
254  	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
255  	MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS       = 0x911,
256  	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
257  	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
258  	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
259  	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
260  	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
261  	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
262  	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
263  	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
264  	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
265  	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
266  	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
267  	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
268  	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
269  	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
270  	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
271  	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
272  	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
273  	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
274  	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
275  	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
276  	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
277  	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
278  	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
279  	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
280  	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
281  	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
282  	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
283  	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
284  	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
285  	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
286  	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
287  	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
288  	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
289  	MLX5_CMD_OP_CREATE_GENERAL_OBJ            = 0xa00,
290  	MLX5_CMD_OP_MODIFY_GENERAL_OBJ            = 0xa01,
291  	MLX5_CMD_OP_QUERY_GENERAL_OBJ             = 0xa02,
292  	MLX5_CMD_OP_DESTROY_GENERAL_OBJ           = 0xa03,
293  	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
294  	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
295  	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
296  	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
297  };
298  
299  /* Valid range for general commands that don't work over an object */
300  enum {
301  	MLX5_CMD_OP_GENERAL_START = 0xb00,
302  	MLX5_CMD_OP_GENERAL_END = 0xd00,
303  };
304  
305  enum {
306  	MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
307  	MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
308  };
309  
310  enum {
311  	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
312  	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
313  	MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
314  	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
315  	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
316  	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
317  	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
318  	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
319  	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
320  	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
321  	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
322  	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
323  };
324  
325  enum {
326  	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 1ULL << 0x13,
327  };
328  
329  enum {
330  	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
331  	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
332  };
333  
334  enum {
335  	MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc,
336  };
337  
338  enum {
339  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
340  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
341  };
342  
343  enum {
344  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
345  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
346  };
347  
348  struct mlx5_ifc_flow_table_fields_supported_bits {
349  	u8         outer_dmac[0x1];
350  	u8         outer_smac[0x1];
351  	u8         outer_ether_type[0x1];
352  	u8         outer_ip_version[0x1];
353  	u8         outer_first_prio[0x1];
354  	u8         outer_first_cfi[0x1];
355  	u8         outer_first_vid[0x1];
356  	u8         reserved_1[0x1];
357  	u8         outer_second_prio[0x1];
358  	u8         outer_second_cfi[0x1];
359  	u8         outer_second_vid[0x1];
360  	u8         outer_ipv6_flow_label[0x1];
361  	u8         outer_sip[0x1];
362  	u8         outer_dip[0x1];
363  	u8         outer_frag[0x1];
364  	u8         outer_ip_protocol[0x1];
365  	u8         outer_ip_ecn[0x1];
366  	u8         outer_ip_dscp[0x1];
367  	u8         outer_udp_sport[0x1];
368  	u8         outer_udp_dport[0x1];
369  	u8         outer_tcp_sport[0x1];
370  	u8         outer_tcp_dport[0x1];
371  	u8         outer_tcp_flags[0x1];
372  	u8         outer_gre_protocol[0x1];
373  	u8         outer_gre_key[0x1];
374  	u8         outer_vxlan_vni[0x1];
375  	u8         outer_geneve_vni[0x1];
376  	u8         outer_geneve_oam[0x1];
377  	u8         outer_geneve_protocol_type[0x1];
378  	u8         outer_geneve_opt_len[0x1];
379  	u8         reserved_2[0x1];
380  	u8         source_eswitch_port[0x1];
381  
382  	u8         inner_dmac[0x1];
383  	u8         inner_smac[0x1];
384  	u8         inner_ether_type[0x1];
385  	u8         inner_ip_version[0x1];
386  	u8         inner_first_prio[0x1];
387  	u8         inner_first_cfi[0x1];
388  	u8         inner_first_vid[0x1];
389  	u8         reserved_4[0x1];
390  	u8         inner_second_prio[0x1];
391  	u8         inner_second_cfi[0x1];
392  	u8         inner_second_vid[0x1];
393  	u8         inner_ipv6_flow_label[0x1];
394  	u8         inner_sip[0x1];
395  	u8         inner_dip[0x1];
396  	u8         inner_frag[0x1];
397  	u8         inner_ip_protocol[0x1];
398  	u8         inner_ip_ecn[0x1];
399  	u8         inner_ip_dscp[0x1];
400  	u8         inner_udp_sport[0x1];
401  	u8         inner_udp_dport[0x1];
402  	u8         inner_tcp_sport[0x1];
403  	u8         inner_tcp_dport[0x1];
404  	u8         inner_tcp_flags[0x1];
405  	u8         reserved_5[0x9];
406  
407  	u8         reserved_6[0x1a];
408  	u8         bth_dst_qp[0x1];
409  	u8         reserved_7[0x4];
410  	u8         source_sqn[0x1];
411  
412  	u8         reserved_8[0x20];
413  };
414  
415  struct mlx5_ifc_eth_discard_cntrs_grp_bits {
416  	u8         ingress_general_high[0x20];
417  
418  	u8         ingress_general_low[0x20];
419  
420  	u8         ingress_policy_engine_high[0x20];
421  
422  	u8         ingress_policy_engine_low[0x20];
423  
424  	u8         ingress_vlan_membership_high[0x20];
425  
426  	u8         ingress_vlan_membership_low[0x20];
427  
428  	u8         ingress_tag_frame_type_high[0x20];
429  
430  	u8         ingress_tag_frame_type_low[0x20];
431  
432  	u8         egress_vlan_membership_high[0x20];
433  
434  	u8         egress_vlan_membership_low[0x20];
435  
436  	u8         loopback_filter_high[0x20];
437  
438  	u8         loopback_filter_low[0x20];
439  
440  	u8         egress_general_high[0x20];
441  
442  	u8         egress_general_low[0x20];
443  
444  	u8         reserved_at_1c0[0x40];
445  
446  	u8         egress_hoq_high[0x20];
447  
448  	u8         egress_hoq_low[0x20];
449  
450  	u8         port_isolation_high[0x20];
451  
452  	u8         port_isolation_low[0x20];
453  
454  	u8         egress_policy_engine_high[0x20];
455  
456  	u8         egress_policy_engine_low[0x20];
457  
458  	u8         ingress_tx_link_down_high[0x20];
459  
460  	u8         ingress_tx_link_down_low[0x20];
461  
462  	u8         egress_stp_filter_high[0x20];
463  
464  	u8         egress_stp_filter_low[0x20];
465  
466  	u8         egress_hoq_stall_high[0x20];
467  
468  	u8         egress_hoq_stall_low[0x20];
469  
470  	u8         reserved_at_340[0x440];
471  };
472  
473  struct mlx5_ifc_flow_table_prop_layout_bits {
474  	u8         ft_support[0x1];
475  	u8         reserved_at_1[0x1];
476  	u8         flow_counter[0x1];
477  	u8         flow_modify_en[0x1];
478  	u8         modify_root[0x1];
479  	u8         identified_miss_table_mode[0x1];
480  	u8         flow_table_modify[0x1];
481  	u8         reformat[0x1];
482  	u8         decap[0x1];
483  	u8         reserved_at_9[0x1];
484  	u8         pop_vlan[0x1];
485  	u8         push_vlan[0x1];
486  	u8         reserved_at_c[0x1];
487  	u8         pop_vlan_2[0x1];
488  	u8         push_vlan_2[0x1];
489  	u8         reformat_and_vlan_action[0x1];
490  	u8         reserved_at_10[0x1];
491  	u8         sw_owner[0x1];
492  	u8         reformat_l3_tunnel_to_l2[0x1];
493  	u8         reformat_l2_to_l3_tunnel[0x1];
494  	u8         reformat_and_modify_action[0x1];
495  	u8         ignore_flow_level[0x1];
496  	u8         reserved_at_16[0x1];
497  	u8         table_miss_action_domain[0x1];
498  	u8         termination_table[0x1];
499  	u8         reformat_and_fwd_to_table[0x1];
500  	u8         reserved_at_1a[0x2];
501  	u8         ipsec_encrypt[0x1];
502  	u8         ipsec_decrypt[0x1];
503  	u8         sw_owner_v2[0x1];
504  	u8         reserved_at_1f[0x1];
505  	u8         termination_table_raw_traffic[0x1];
506  	u8         reserved_at_21[0x1];
507  	u8         log_max_ft_size[0x6];
508  	u8         log_max_modify_header_context[0x8];
509          u8         max_modify_header_actions[0x8];
510  	u8         max_ft_level[0x8];
511  
512  	u8         reformat_add_esp_trasport[0x1];
513  	u8         reformat_l2_to_l3_esp_tunnel[0x1];
514  	u8         reformat_add_esp_transport_over_udp[0x1];
515  	u8         reformat_del_esp_trasport[0x1];
516  	u8         reformat_l3_esp_tunnel_to_l2[0x1];
517  	u8         reformat_del_esp_transport_over_udp[0x1];
518  	u8         execute_aso[0x1];
519  	u8         reserved_at_47[0x19];
520  	u8         reserved_at_60[0x2];
521  	u8         reformat_insert[0x1];
522  	u8         reformat_remove[0x1];
523  	u8         macsec_encrypt[0x1];
524  	u8         macsec_decrypt[0x1];
525  	u8         reserved_at_66[0x2];
526  	u8         reformat_add_macsec[0x1];
527  	u8         reformat_remove_macsec[0x1];
528  	u8         reserved_at_6a[0xe];
529  	u8         log_max_ft_num[0x8];
530  	u8         reserved_at_80[0x10];
531  	u8         log_max_flow_counter[0x8];
532  	u8         log_max_destination[0x8];
533  	u8         reserved_at_a0[0x18];
534  	u8         log_max_flow[0x8];
535  	u8         reserved_at_c0[0x40];
536  	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
537  
538  	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
539  };
540  
541  struct mlx5_ifc_odp_per_transport_service_cap_bits {
542  	u8         send[0x1];
543  	u8         receive[0x1];
544  	u8         write[0x1];
545  	u8         read[0x1];
546  	u8         atomic[0x1];
547  	u8         srq_receive[0x1];
548  	u8         reserved_0[0x1a];
549  };
550  
551  struct mlx5_ifc_flow_counter_list_bits {
552  	u8         reserved_0[0x10];
553  	u8         flow_counter_id[0x10];
554  
555  	u8         reserved_1[0x20];
556  };
557  
558  enum {
559  	MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
560  	MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
561  	MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
562  	MLX5_FLOW_CONTEXT_DEST_TYPE_QP                       = 0x3,
563  	MLX5_FLOW_CONTEXT_DEST_TYPE_TABLE_TYPE               = 0xA,
564  };
565  
566  struct mlx5_ifc_dest_format_struct_bits {
567          u8         destination_type[0x8];
568          u8         destination_id[0x18];
569  
570          u8         destination_eswitch_owner_vhca_id_valid[0x1];
571          u8         packet_reformat[0x1];
572          u8         reserved_at_22[0x6];
573          u8         destination_table_type[0x8];
574          u8         destination_eswitch_owner_vhca_id[0x10];
575  };
576  
577  struct mlx5_ifc_ipv4_layout_bits {
578  	u8         reserved_at_0[0x60];
579  
580  	u8         ipv4[0x20];
581  };
582  
583  struct mlx5_ifc_ipv6_layout_bits {
584  	u8         ipv6[16][0x8];
585  };
586  
587  union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
588  	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
589  	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
590  	u8         reserved_at_0[0x80];
591  };
592  
593  struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
594  	u8         smac_47_16[0x20];
595  
596  	u8         smac_15_0[0x10];
597  	u8         ethertype[0x10];
598  
599  	u8         dmac_47_16[0x20];
600  
601  	u8         dmac_15_0[0x10];
602  	u8         first_prio[0x3];
603  	u8         first_cfi[0x1];
604  	u8         first_vid[0xc];
605  
606  	u8         ip_protocol[0x8];
607  	u8         ip_dscp[0x6];
608  	u8         ip_ecn[0x2];
609  	u8         cvlan_tag[0x1];
610  	u8         svlan_tag[0x1];
611  	u8         frag[0x1];
612  	u8         ip_version[0x4];
613  	u8         tcp_flags[0x9];
614  
615  	u8         tcp_sport[0x10];
616  	u8         tcp_dport[0x10];
617  
618  	u8         reserved_2[0x20];
619  
620  	u8         udp_sport[0x10];
621  	u8         udp_dport[0x10];
622  
623  	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
624  
625  	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
626  };
627  
628  struct mlx5_ifc_nvgre_key_bits {
629  	u8 hi[0x18];
630  	u8 lo[0x8];
631  };
632  
633  union mlx5_ifc_gre_key_bits {
634  	struct mlx5_ifc_nvgre_key_bits nvgre;
635  	u8 key[0x20];
636  };
637  
638  struct mlx5_ifc_fte_match_set_misc_bits {
639  	u8         gre_c_present[0x1];
640  	u8         reserved_at_1[0x1];
641  	u8         gre_k_present[0x1];
642  	u8         gre_s_present[0x1];
643  	u8         source_vhca_port[0x4];
644  	u8         source_sqn[0x18];
645  
646  	u8         source_eswitch_owner_vhca_id[0x10];
647  	u8         source_port[0x10];
648  
649  	u8         outer_second_prio[0x3];
650  	u8         outer_second_cfi[0x1];
651  	u8         outer_second_vid[0xc];
652  	u8         inner_second_prio[0x3];
653  	u8         inner_second_cfi[0x1];
654  	u8         inner_second_vid[0xc];
655  
656  	u8         outer_second_cvlan_tag[0x1];
657  	u8         inner_second_cvlan_tag[0x1];
658  	u8         outer_second_svlan_tag[0x1];
659  	u8         inner_second_svlan_tag[0x1];
660  	u8         reserved_at_64[0xc];
661  	u8         gre_protocol[0x10];
662  
663  	union mlx5_ifc_gre_key_bits gre_key;
664  
665  	u8         vxlan_vni[0x18];
666  	u8         bth_opcode[0x8];
667  
668  	u8         geneve_vni[0x18];
669  	u8         reserved_at_d8[0x6];
670  	u8         geneve_tlv_option_0_exist[0x1];
671  	u8         geneve_oam[0x1];
672  
673  	u8         reserved_at_e0[0xc];
674  	u8         outer_ipv6_flow_label[0x14];
675  
676  	u8         reserved_at_100[0xc];
677  	u8         inner_ipv6_flow_label[0x14];
678  
679  	u8         reserved_at_120[0xa];
680  	u8         geneve_opt_len[0x6];
681  	u8         geneve_protocol_type[0x10];
682  
683  	u8         reserved_at_140[0x8];
684  	u8         bth_dst_qp[0x18];
685  	u8         inner_esp_spi[0x20];
686  	u8         outer_esp_spi[0x20];
687  	u8         reserved_at_1a0[0x60];
688  };
689  
690  struct mlx5_ifc_fte_match_mpls_bits {
691  	u8         mpls_label[0x14];
692  	u8         mpls_exp[0x3];
693  	u8         mpls_s_bos[0x1];
694  	u8         mpls_ttl[0x8];
695  };
696  
697  struct mlx5_ifc_fte_match_set_misc2_bits {
698  	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
699  
700  	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
701  
702  	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
703  
704  	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
705  
706  	u8         metadata_reg_c_7[0x20];
707  
708  	u8         metadata_reg_c_6[0x20];
709  
710  	u8         metadata_reg_c_5[0x20];
711  
712  	u8         metadata_reg_c_4[0x20];
713  
714  	u8         metadata_reg_c_3[0x20];
715  
716  	u8         metadata_reg_c_2[0x20];
717  
718  	u8         metadata_reg_c_1[0x20];
719  
720  	u8         metadata_reg_c_0[0x20];
721  
722  	u8         metadata_reg_a[0x20];
723  
724  	u8         reserved_at_1a0[0x8];
725  
726  	u8         macsec_syndrome[0x8];
727  	u8         ipsec_syndrome[0x8];
728  	u8         reserved_at_1b8[0x8];
729  
730  	u8         reserved_at_1c0[0x40];
731  };
732  
733  struct mlx5_ifc_fte_match_set_misc3_bits {
734  	u8         inner_tcp_seq_num[0x20];
735  
736  	u8         outer_tcp_seq_num[0x20];
737  
738  	u8         inner_tcp_ack_num[0x20];
739  
740  	u8         outer_tcp_ack_num[0x20];
741  
742  	u8         reserved_at_80[0x8];
743  	u8         outer_vxlan_gpe_vni[0x18];
744  
745  	u8         outer_vxlan_gpe_next_protocol[0x8];
746  	u8         outer_vxlan_gpe_flags[0x8];
747  	u8         reserved_at_b0[0x10];
748  
749  	u8         icmp_header_data[0x20];
750  
751  	u8         icmpv6_header_data[0x20];
752  
753  	u8         icmp_type[0x8];
754  	u8         icmp_code[0x8];
755  	u8         icmpv6_type[0x8];
756  	u8         icmpv6_code[0x8];
757  
758  	u8         geneve_tlv_option_0_data[0x20];
759  
760  	u8         gtpu_teid[0x20];
761  
762  	u8         gtpu_msg_type[0x8];
763  	u8         gtpu_msg_flags[0x8];
764  	u8         reserved_at_170[0x10];
765  
766  	u8         gtpu_dw_2[0x20];
767  
768  	u8         gtpu_first_ext_dw_0[0x20];
769  
770  	u8         gtpu_dw_0[0x20];
771  
772  	u8         reserved_at_1e0[0x20];
773  };
774  
775  struct mlx5_ifc_fte_match_set_misc4_bits {
776          u8         prog_sample_field_value_0[0x20];
777  
778          u8         prog_sample_field_id_0[0x20];
779  
780          u8         prog_sample_field_value_1[0x20];
781  
782          u8         prog_sample_field_id_1[0x20];
783  
784          u8         prog_sample_field_value_2[0x20];
785  
786          u8         prog_sample_field_id_2[0x20];
787  
788          u8         prog_sample_field_value_3[0x20];
789  
790          u8         prog_sample_field_id_3[0x20];
791  
792          u8         reserved_at_100[0x100];
793  };
794  
795  struct mlx5_ifc_fte_match_set_misc5_bits {
796          u8         macsec_tag_0[0x20];
797  
798          u8         macsec_tag_1[0x20];
799  
800          u8         macsec_tag_2[0x20];
801  
802          u8         macsec_tag_3[0x20];
803  
804          u8         tunnel_header_0[0x20];
805  
806          u8         tunnel_header_1[0x20];
807  
808          u8         tunnel_header_2[0x20];
809  
810          u8         tunnel_header_3[0x20];
811  
812          u8         reserved_at_100[0x100];
813  };
814  
815  struct mlx5_ifc_cmd_pas_bits {
816  	u8         pa_h[0x20];
817  
818  	u8         pa_l[0x14];
819  	u8         reserved_0[0xc];
820  };
821  
822  struct mlx5_ifc_uint64_bits {
823  	u8         hi[0x20];
824  
825  	u8         lo[0x20];
826  };
827  
828  struct mlx5_ifc_application_prio_entry_bits {
829  	u8         reserved_0[0x8];
830  	u8         priority[0x3];
831  	u8         reserved_1[0x2];
832  	u8         sel[0x3];
833  	u8         protocol_id[0x10];
834  };
835  
836  struct mlx5_ifc_nodnic_ring_doorbell_bits {
837  	u8         reserved_0[0x8];
838  	u8         ring_pi[0x10];
839  	u8         reserved_1[0x8];
840  };
841  
842  enum {
843  	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
844  	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
845  	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
846  	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
847  	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
848  	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
849  	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
850  	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
851  	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
852  	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
853  };
854  
855  struct mlx5_ifc_ads_bits {
856  	u8         fl[0x1];
857  	u8         free_ar[0x1];
858  	u8         reserved_0[0xe];
859  	u8         pkey_index[0x10];
860  
861  	u8         reserved_1[0x8];
862  	u8         grh[0x1];
863  	u8         mlid[0x7];
864  	u8         rlid[0x10];
865  
866  	u8         ack_timeout[0x5];
867  	u8         reserved_2[0x3];
868  	u8         src_addr_index[0x8];
869  	u8         log_rtm[0x4];
870  	u8         stat_rate[0x4];
871  	u8         hop_limit[0x8];
872  
873  	u8         reserved_3[0x4];
874  	u8         tclass[0x8];
875  	u8         flow_label[0x14];
876  
877  	u8         rgid_rip[16][0x8];
878  
879  	u8         reserved_4[0x4];
880  	u8         f_dscp[0x1];
881  	u8         f_ecn[0x1];
882  	u8         reserved_5[0x1];
883  	u8         f_eth_prio[0x1];
884  	u8         ecn[0x2];
885  	u8         dscp[0x6];
886  	u8         udp_sport[0x10];
887  
888  	u8         dei_cfi[0x1];
889  	u8         eth_prio[0x3];
890  	u8         sl[0x4];
891  	u8         port[0x8];
892  	u8         rmac_47_32[0x10];
893  
894  	u8         rmac_31_0[0x20];
895  };
896  
897  struct mlx5_ifc_diagnostic_counter_cap_bits {
898  	u8         sync[0x1];
899  	u8         reserved_0[0xf];
900  	u8         counter_id[0x10];
901  };
902  
903  struct mlx5_ifc_debug_cap_bits {
904  	u8         reserved_0[0x18];
905  	u8         log_max_samples[0x8];
906  
907  	u8         single[0x1];
908  	u8         repetitive[0x1];
909  	u8         health_mon_rx_activity[0x1];
910  	u8         reserved_1[0x15];
911  	u8         log_min_sample_period[0x8];
912  
913  	u8         reserved_2[0x1c0];
914  
915  	struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
916  };
917  
918  struct mlx5_ifc_qos_cap_bits {
919  	u8         packet_pacing[0x1];
920  	u8         esw_scheduling[0x1];
921  	u8         esw_bw_share[0x1];
922  	u8         esw_rate_limit[0x1];
923  	u8         hll[0x1];
924  	u8         packet_pacing_burst_bound[0x1];
925  	u8         packet_pacing_typical_size[0x1];
926  	u8         reserved_at_7[0x19];
927  
928  	u8 	   reserved_at_20[0xA];
929  	u8	   qos_remap_pp[0x1];
930  	u8         reserved_at_2b[0x15];
931  
932  	u8         packet_pacing_max_rate[0x20];
933  
934  	u8         packet_pacing_min_rate[0x20];
935  
936  	u8         reserved_at_80[0x10];
937  	u8         packet_pacing_rate_table_size[0x10];
938  
939  	u8         esw_element_type[0x10];
940  	u8         esw_tsar_type[0x10];
941  
942  	u8         reserved_at_c0[0x10];
943  	u8         max_qos_para_vport[0x10];
944  
945  	u8         max_tsar_bw_share[0x20];
946  
947  	u8         reserved_at_100[0x700];
948  };
949  
950  struct mlx5_ifc_snapshot_cap_bits {
951  	u8         reserved_0[0x1d];
952  	u8         suspend_qp_uc[0x1];
953  	u8         suspend_qp_ud[0x1];
954  	u8         suspend_qp_rc[0x1];
955  
956  	u8         reserved_1[0x1c];
957  	u8         restore_pd[0x1];
958  	u8         restore_uar[0x1];
959  	u8         restore_mkey[0x1];
960  	u8         restore_qp[0x1];
961  
962  	u8         reserved_2[0x1e];
963  	u8         named_mkey[0x1];
964  	u8         named_qp[0x1];
965  
966  	u8         reserved_3[0x7a0];
967  };
968  
969  struct mlx5_ifc_e_switch_cap_bits {
970          u8         vport_svlan_strip[0x1];
971          u8         vport_cvlan_strip[0x1];
972          u8         vport_svlan_insert[0x1];
973          u8         vport_cvlan_insert_if_not_exist[0x1];
974          u8         vport_cvlan_insert_overwrite[0x1];
975          u8         reserved_at_5[0x1];
976          u8         vport_cvlan_insert_always[0x1];
977          u8         esw_shared_ingress_acl[0x1];
978          u8         esw_uplink_ingress_acl[0x1];
979          u8         root_ft_on_other_esw[0x1];
980          u8         reserved_at_a[0xf];
981          u8         esw_functions_changed[0x1];
982          u8         reserved_at_1a[0x1];
983          u8         ecpf_vport_exists[0x1];
984          u8         counter_eswitch_affinity[0x1];
985          u8         merged_eswitch[0x1];
986          u8         nic_vport_node_guid_modify[0x1];
987          u8         nic_vport_port_guid_modify[0x1];
988  
989          u8         vxlan_encap_decap[0x1];
990          u8         nvgre_encap_decap[0x1];
991          u8         reserved_at_22[0x1];
992          u8         log_max_fdb_encap_uplink[0x5];
993          u8         reserved_at_21[0x3];
994          u8         log_max_packet_reformat_context[0x5];
995          u8         reserved_2b[0x6];
996          u8         max_encap_header_size[0xa];
997  
998          u8         reserved_at_40[0xb];
999          u8         log_max_esw_sf[0x5];
1000          u8         esw_sf_base_id[0x10];
1001  
1002          u8         reserved_at_60[0x7a0];
1003  
1004  };
1005  
1006  struct mlx5_ifc_flow_table_eswitch_cap_bits {
1007  	u8         reserved_0[0x200];
1008  
1009  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
1010  
1011  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
1012  
1013  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
1014  
1015  	u8         reserved_1[0x7800];
1016  };
1017  
1018  struct mlx5_ifc_flow_table_nic_cap_bits {
1019  	u8         nic_rx_multi_path_tirs[0x1];
1020          u8         nic_rx_multi_path_tirs_fts[0x1];
1021          u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
1022          u8         reserved_at_3[0x4];
1023          u8         sw_owner_reformat_supported[0x1];
1024          u8         reserved_at_8[0x18];
1025  
1026          u8         encap_general_header[0x1];
1027          u8         reserved_at_21[0xa];
1028          u8         log_max_packet_reformat_context[0x5];
1029          u8         reserved_at_30[0x6];
1030          u8         max_encap_header_size[0xa];
1031          u8         reserved_at_40[0x1c0];
1032  
1033  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
1034  
1035  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
1036  
1037  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
1038  
1039  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
1040  
1041  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
1042  
1043  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
1044  
1045  	u8         reserved_1[0x7200];
1046  };
1047  
1048  struct mlx5_ifc_port_selection_cap_bits {
1049          u8         reserved_at_0[0x10];
1050          u8         port_select_flow_table[0x1];
1051          u8         reserved_at_11[0x1];
1052          u8         port_select_flow_table_bypass[0x1];
1053          u8         reserved_at_13[0xd];
1054  
1055          u8         reserved_at_20[0x1e0];
1056  
1057          struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
1058  
1059          u8         reserved_at_400[0x7c00];
1060  };
1061  
1062  struct mlx5_ifc_pddr_module_info_bits {
1063  	u8         cable_technology[0x8];
1064  	u8         cable_breakout[0x8];
1065  	u8         ext_ethernet_compliance_code[0x8];
1066  	u8         ethernet_compliance_code[0x8];
1067  
1068  	u8         cable_type[0x4];
1069  	u8         cable_vendor[0x4];
1070  	u8         cable_length[0x8];
1071  	u8         cable_identifier[0x8];
1072  	u8         cable_power_class[0x8];
1073  
1074  	u8         reserved_at_40[0x8];
1075  	u8         cable_rx_amp[0x8];
1076  	u8         cable_rx_emphasis[0x8];
1077  	u8         cable_tx_equalization[0x8];
1078  
1079  	u8         reserved_at_60[0x8];
1080  	u8         cable_attenuation_12g[0x8];
1081  	u8         cable_attenuation_7g[0x8];
1082  	u8         cable_attenuation_5g[0x8];
1083  
1084  	u8         reserved_at_80[0x8];
1085  	u8         rx_cdr_cap[0x4];
1086  	u8         tx_cdr_cap[0x4];
1087  	u8         reserved_at_90[0x4];
1088  	u8         rx_cdr_state[0x4];
1089  	u8         reserved_at_98[0x4];
1090  	u8         tx_cdr_state[0x4];
1091  
1092  	u8         vendor_name[16][0x8];
1093  
1094  	u8         vendor_pn[16][0x8];
1095  
1096  	u8         vendor_rev[0x20];
1097  
1098  	u8         fw_version[0x20];
1099  
1100  	u8         vendor_sn[16][0x8];
1101  
1102  	u8         temperature[0x10];
1103  	u8         voltage[0x10];
1104  
1105  	u8         rx_power_lane0[0x10];
1106  	u8         rx_power_lane1[0x10];
1107  
1108  	u8         rx_power_lane2[0x10];
1109  	u8         rx_power_lane3[0x10];
1110  
1111  	u8         reserved_at_2c0[0x40];
1112  
1113  	u8         tx_power_lane0[0x10];
1114  	u8         tx_power_lane1[0x10];
1115  
1116  	u8         tx_power_lane2[0x10];
1117  	u8         tx_power_lane3[0x10];
1118  
1119  	u8         reserved_at_340[0x40];
1120  
1121  	u8         tx_bias_lane0[0x10];
1122  	u8         tx_bias_lane1[0x10];
1123  
1124  	u8         tx_bias_lane2[0x10];
1125  	u8         tx_bias_lane3[0x10];
1126  
1127  	u8         reserved_at_3c0[0x40];
1128  
1129  	u8         temperature_high_th[0x10];
1130  	u8         temperature_low_th[0x10];
1131  
1132  	u8         voltage_high_th[0x10];
1133  	u8         voltage_low_th[0x10];
1134  
1135  	u8         rx_power_high_th[0x10];
1136  	u8         rx_power_low_th[0x10];
1137  
1138  	u8         tx_power_high_th[0x10];
1139  	u8         tx_power_low_th[0x10];
1140  
1141  	u8         tx_bias_high_th[0x10];
1142  	u8         tx_bias_low_th[0x10];
1143  
1144  	u8         reserved_at_4a0[0x10];
1145  	u8         wavelength[0x10];
1146  
1147  	u8         reserved_at_4c0[0x300];
1148  };
1149  
1150  struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1151  	u8         csum_cap[0x1];
1152  	u8         vlan_cap[0x1];
1153  	u8         lro_cap[0x1];
1154  	u8         lro_psh_flag[0x1];
1155  	u8         lro_time_stamp[0x1];
1156  	u8         lro_max_msg_sz_mode[0x2];
1157  	u8         wqe_vlan_insert[0x1];
1158  	u8         self_lb_en_modifiable[0x1];
1159  	u8         self_lb_mc[0x1];
1160  	u8         self_lb_uc[0x1];
1161  	u8         max_lso_cap[0x5];
1162  	u8         multi_pkt_send_wqe[0x2];
1163  	u8         wqe_inline_mode[0x2];
1164  	u8         rss_ind_tbl_cap[0x4];
1165  	u8	   reg_umr_sq[0x1];
1166  	u8         scatter_fcs[0x1];
1167  	u8	   enhanced_multi_pkt_send_wqe[0x1];
1168  	u8         tunnel_lso_const_out_ip_id[0x1];
1169  	u8         tunnel_lro_gre[0x1];
1170  	u8         tunnel_lro_vxlan[0x1];
1171  	u8         tunnel_statless_gre[0x1];
1172  	u8         tunnel_stateless_vxlan[0x1];
1173  
1174  	u8         swp[0x1];
1175  	u8         swp_csum[0x1];
1176  	u8         swp_lso[0x1];
1177  	u8         reserved_2[0x1b];
1178  	u8         max_geneve_opt_len[0x1];
1179  	u8         tunnel_stateless_geneve_rx[0x1];
1180  
1181  	u8         reserved_3[0x10];
1182  	u8         lro_min_mss_size[0x10];
1183  
1184  	u8         reserved_4[0x120];
1185  
1186  	u8         lro_timer_supported_periods[4][0x20];
1187  
1188  	u8         reserved_5[0x600];
1189  };
1190  
1191  enum {
1192  	MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
1193  	MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
1194  	MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
1195  };
1196  
1197  enum {
1198  	MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1199  	MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1200  	MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1201  };
1202  
1203  struct mlx5_ifc_roce_cap_bits {
1204  	u8         roce_apm[0x1];
1205  	u8         rts2rts_primary_eth_prio[0x1];
1206  	u8         roce_rx_allow_untagged[0x1];
1207  	u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
1208  	u8         reserved_at_4[0x1a];
1209  	u8         qp_ts_format[0x2];
1210  
1211  	u8         reserved_1[0x60];
1212  
1213  	u8         reserved_2[0xc];
1214  	u8         l3_type[0x4];
1215  	u8         reserved_3[0x8];
1216  	u8         roce_version[0x8];
1217  
1218  	u8         reserved_4[0x10];
1219  	u8         r_roce_dest_udp_port[0x10];
1220  
1221  	u8         r_roce_max_src_udp_port[0x10];
1222  	u8         r_roce_min_src_udp_port[0x10];
1223  
1224  	u8         reserved_5[0x10];
1225  	u8         roce_address_table_size[0x10];
1226  
1227  	u8         reserved_6[0x700];
1228  };
1229  
1230  struct mlx5_ifc_device_event_cap_bits {
1231  	u8         user_affiliated_events[4][0x40];
1232  
1233  	u8         user_unaffiliated_events[4][0x40];
1234  };
1235  
1236  enum {
1237  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
1238  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1239  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1240  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1241  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1242  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1243  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1244  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1245  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1246  };
1247  
1248  enum {
1249  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1250  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1251  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1252  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1253  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1254  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1255  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1256  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1257  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1258  };
1259  
1260  struct mlx5_ifc_atomic_caps_bits {
1261  	u8         reserved_0[0x40];
1262  
1263  	u8         atomic_req_8B_endianess_mode[0x2];
1264  	u8         reserved_1[0x4];
1265  	u8         supported_atomic_req_8B_endianess_mode_1[0x1];
1266  
1267  	u8         reserved_2[0x19];
1268  
1269  	u8         reserved_3[0x20];
1270  
1271  	u8         reserved_4[0x10];
1272  	u8         atomic_operations[0x10];
1273  
1274  	u8         reserved_5[0x10];
1275  	u8         atomic_size_qp[0x10];
1276  
1277  	u8         reserved_6[0x10];
1278  	u8         atomic_size_dc[0x10];
1279  
1280  	u8         reserved_7[0x720];
1281  };
1282  
1283  struct mlx5_ifc_odp_cap_bits {
1284  	u8         reserved_0[0x40];
1285  
1286  	u8         sig[0x1];
1287  	u8         reserved_1[0x1f];
1288  
1289  	u8         reserved_2[0x20];
1290  
1291  	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1292  
1293  	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1294  
1295  	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1296  
1297  	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1298  
1299  	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1300  
1301  	u8         reserved_3[0x6e0];
1302  };
1303  
1304  enum {
1305  	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1306  	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1307  	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1308  	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1309  	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1310  };
1311  
1312  enum {
1313  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1314  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1315  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1316  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1317  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1318  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1319  };
1320  
1321  enum {
1322  	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1323  	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1324  };
1325  
1326  enum {
1327  	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1328  	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1329  	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1330  };
1331  
1332  enum {
1333  	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1334  	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1335  };
1336  
1337  enum {
1338  	MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1339  	MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1340  	MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1341  };
1342  
1343  enum {
1344  	MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1345  	MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1346  	MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1347  };
1348  
1349  struct mlx5_ifc_cmd_hca_cap_bits {
1350  	u8         reserved_0[0x20];
1351  
1352  	u8         hca_cap_2[0x1];
1353  	u8         create_lag_when_not_master_up[0x1];
1354          u8         dtor[0x1];
1355          u8         event_on_vhca_state_teardown_request[0x1];
1356          u8         event_on_vhca_state_in_use[0x1];
1357          u8         event_on_vhca_state_active[0x1];
1358          u8         event_on_vhca_state_allocated[0x1];
1359          u8         event_on_vhca_state_invalid[0x1];
1360          u8         reserved_at_28[0x8];
1361          u8         vhca_id[0x10];
1362  
1363  	u8         reserved_at_40[0x40];
1364  
1365  	u8         log_max_srq_sz[0x8];
1366  	u8         log_max_qp_sz[0x8];
1367  	u8         event_cap[0x1];
1368  	u8         reserved_1[0xa];
1369  	u8         log_max_qp[0x5];
1370  
1371  	u8         reserved_2[0xb];
1372  	u8         log_max_srq[0x5];
1373  	u8         reserved_3[0x10];
1374  
1375  	u8         reserved_4[0x8];
1376  	u8         log_max_cq_sz[0x8];
1377  	u8         relaxed_ordering_write_umr[0x1];
1378  	u8         relaxed_ordering_read_umr[0x1];
1379  	u8         reserved_5[0x9];
1380  	u8         log_max_cq[0x5];
1381  
1382  	u8         log_max_eq_sz[0x8];
1383  	u8         relaxed_ordering_write[0x1];
1384  	u8         relaxed_ordering_read[0x1];
1385  	u8         log_max_mkey[0x6];
1386  	u8         reserved_7[0xb];
1387  	u8         fast_teardown[0x1];
1388  	u8         log_max_eq[0x4];
1389  
1390  	u8         max_indirection[0x8];
1391  	u8         reserved_8[0x1];
1392  	u8         log_max_mrw_sz[0x7];
1393  	u8	   force_teardown[0x1];
1394  	u8         reserved_9[0x1];
1395  	u8         log_max_bsf_list_size[0x6];
1396  	u8         reserved_10[0x2];
1397  	u8         log_max_klm_list_size[0x6];
1398  
1399  	u8         reserved_11[0xa];
1400  	u8         log_max_ra_req_dc[0x6];
1401  	u8         reserved_12[0xa];
1402  	u8         log_max_ra_res_dc[0x6];
1403  
1404  	u8         reserved_13[0xa];
1405  	u8         log_max_ra_req_qp[0x6];
1406  	u8         reserved_14[0xa];
1407  	u8         log_max_ra_res_qp[0x6];
1408  
1409  	u8         pad_cap[0x1];
1410  	u8         cc_query_allowed[0x1];
1411  	u8         cc_modify_allowed[0x1];
1412  	u8         start_pad[0x1];
1413  	u8         cache_line_128byte[0x1];
1414  	u8         reserved_at_165[0xa];
1415  	u8         qcam_reg[0x1];
1416  	u8         gid_table_size[0x10];
1417  
1418  	u8         out_of_seq_cnt[0x1];
1419  	u8         vport_counters[0x1];
1420  	u8         retransmission_q_counters[0x1];
1421  	u8         debug[0x1];
1422  	u8         modify_rq_counters_set_id[0x1];
1423  	u8         rq_delay_drop[0x1];
1424  	u8         max_qp_cnt[0xa];
1425  	u8         pkey_table_size[0x10];
1426  
1427  	u8         vport_group_manager[0x1];
1428  	u8         vhca_group_manager[0x1];
1429  	u8         ib_virt[0x1];
1430  	u8         eth_virt[0x1];
1431  	u8         reserved_17[0x1];
1432  	u8         ets[0x1];
1433  	u8         nic_flow_table[0x1];
1434  	u8         eswitch_flow_table[0x1];
1435  	u8         reserved_18[0x1];
1436  	u8         mcam_reg[0x1];
1437  	u8         pcam_reg[0x1];
1438  	u8         local_ca_ack_delay[0x5];
1439  	u8         port_module_event[0x1];
1440  	u8         reserved_19[0x5];
1441  	u8         port_type[0x2];
1442  	u8         num_ports[0x8];
1443  
1444  	u8         snapshot[0x1];
1445  	u8         reserved_20[0x2];
1446  	u8         log_max_msg[0x5];
1447  	u8         reserved_21[0x4];
1448  	u8         max_tc[0x4];
1449  	u8         temp_warn_event[0x1];
1450  	u8         dcbx[0x1];
1451  	u8         general_notification_event[0x1];
1452  	u8         reserved_at_1d3[0x2];
1453  	u8         fpga[0x1];
1454  	u8         rol_s[0x1];
1455  	u8         rol_g[0x1];
1456  	u8         reserved_23[0x1];
1457  	u8         wol_s[0x1];
1458  	u8         wol_g[0x1];
1459  	u8         wol_a[0x1];
1460  	u8         wol_b[0x1];
1461  	u8         wol_m[0x1];
1462  	u8         wol_u[0x1];
1463  	u8         wol_p[0x1];
1464  
1465  	u8         stat_rate_support[0x10];
1466  	u8         reserved_24[0xc];
1467  	u8         cqe_version[0x4];
1468  
1469  	u8         compact_address_vector[0x1];
1470  	u8         striding_rq[0x1];
1471  	u8         reserved_25[0x1];
1472  	u8         ipoib_enhanced_offloads[0x1];
1473  	u8         ipoib_ipoib_offloads[0x1];
1474  	u8         reserved_26[0x8];
1475  	u8         dc_connect_qp[0x1];
1476  	u8         dc_cnak_trace[0x1];
1477  	u8         drain_sigerr[0x1];
1478  	u8         cmdif_checksum[0x2];
1479  	u8         sigerr_cqe[0x1];
1480  	u8         reserved_27[0x1];
1481  	u8         wq_signature[0x1];
1482  	u8         sctr_data_cqe[0x1];
1483  	u8         reserved_28[0x1];
1484  	u8         sho[0x1];
1485  	u8         tph[0x1];
1486  	u8         rf[0x1];
1487  	u8         dct[0x1];
1488  	u8         qos[0x1];
1489  	u8         eth_net_offloads[0x1];
1490  	u8         roce[0x1];
1491  	u8         atomic[0x1];
1492  	u8         reserved_30[0x1];
1493  
1494  	u8         cq_oi[0x1];
1495  	u8         cq_resize[0x1];
1496  	u8         cq_moderation[0x1];
1497  	u8         cq_period_mode_modify[0x1];
1498  	u8         cq_invalidate[0x1];
1499  	u8         reserved_at_225[0x1];
1500  	u8         cq_eq_remap[0x1];
1501  	u8         pg[0x1];
1502  	u8         block_lb_mc[0x1];
1503  	u8         exponential_backoff[0x1];
1504  	u8         scqe_break_moderation[0x1];
1505  	u8         cq_period_start_from_cqe[0x1];
1506  	u8         cd[0x1];
1507  	u8         atm[0x1];
1508  	u8         apm[0x1];
1509  	u8	   imaicl[0x1];
1510  	u8         reserved_32[0x6];
1511  	u8         qkv[0x1];
1512  	u8         pkv[0x1];
1513  	u8	   set_deth_sqpn[0x1];
1514  	u8         reserved_33[0x3];
1515  	u8         xrc[0x1];
1516  	u8         ud[0x1];
1517  	u8         uc[0x1];
1518  	u8         rc[0x1];
1519  
1520  	u8         uar_4k[0x1];
1521  	u8         reserved_at_241[0x9];
1522  	u8         uar_sz[0x6];
1523  	u8         reserved_35[0x8];
1524  	u8         log_pg_sz[0x8];
1525  
1526  	u8         bf[0x1];
1527  	u8         driver_version[0x1];
1528  	u8         pad_tx_eth_packet[0x1];
1529  	u8         reserved_36[0x8];
1530  	u8         log_bf_reg_size[0x5];
1531  	u8         reserved_37[0x10];
1532  
1533  	u8         num_of_diagnostic_counters[0x10];
1534  	u8         max_wqe_sz_sq[0x10];
1535  
1536  	u8         reserved_38[0x10];
1537  	u8         max_wqe_sz_rq[0x10];
1538  
1539  	u8         reserved_39[0x10];
1540  	u8         max_wqe_sz_sq_dc[0x10];
1541  
1542  	u8         reserved_40[0x7];
1543  	u8         max_qp_mcg[0x19];
1544  
1545  	u8         reserved_41[0x10];
1546  	u8         flow_counter_bulk_alloc[0x8];
1547  	u8         log_max_mcg[0x8];
1548  
1549  	u8         reserved_42[0x3];
1550  	u8         log_max_transport_domain[0x5];
1551  	u8         reserved_43[0x3];
1552  	u8         log_max_pd[0x5];
1553  	u8         reserved_44[0xb];
1554  	u8         log_max_xrcd[0x5];
1555  
1556  	u8         nic_receive_steering_discard[0x1];
1557  	u8	   reserved_45[0x7];
1558  	u8         log_max_flow_counter_bulk[0x8];
1559  	u8         max_flow_counter[0x10];
1560  
1561  	u8         reserved_46[0x3];
1562  	u8         log_max_rq[0x5];
1563  	u8         reserved_47[0x3];
1564  	u8         log_max_sq[0x5];
1565  	u8         reserved_48[0x3];
1566  	u8         log_max_tir[0x5];
1567  	u8         reserved_49[0x3];
1568  	u8         log_max_tis[0x5];
1569  
1570  	u8         basic_cyclic_rcv_wqe[0x1];
1571  	u8         reserved_50[0x2];
1572  	u8         log_max_rmp[0x5];
1573  	u8         reserved_51[0x3];
1574  	u8         log_max_rqt[0x5];
1575  	u8         reserved_52[0x3];
1576  	u8         log_max_rqt_size[0x5];
1577  	u8         reserved_53[0x3];
1578  	u8         log_max_tis_per_sq[0x5];
1579  
1580  	u8         reserved_54[0x3];
1581  	u8         log_max_stride_sz_rq[0x5];
1582  	u8         reserved_55[0x3];
1583  	u8         log_min_stride_sz_rq[0x5];
1584  	u8         reserved_56[0x3];
1585  	u8         log_max_stride_sz_sq[0x5];
1586  	u8         reserved_57[0x3];
1587  	u8         log_min_stride_sz_sq[0x5];
1588  
1589  	u8         reserved_58[0x1b];
1590  	u8         log_max_wq_sz[0x5];
1591  
1592  	u8         nic_vport_change_event[0x1];
1593  	u8         disable_local_lb_uc[0x1];
1594  	u8         disable_local_lb_mc[0x1];
1595  	u8         reserved_59[0x8];
1596  	u8         log_max_vlan_list[0x5];
1597  	u8         reserved_60[0x3];
1598  	u8         log_max_current_mc_list[0x5];
1599  	u8         reserved_61[0x3];
1600  	u8         log_max_current_uc_list[0x5];
1601  
1602  	u8         general_obj_types[0x40];
1603  
1604  	u8         sq_ts_format[0x2];
1605  	u8         rq_ts_format[0x2];
1606  	u8         reserved_at_444[0x4];
1607  	u8         create_qp_start_hint[0x18];
1608  
1609  	u8         reserved_at_460[0x3];
1610  	u8         log_max_uctx[0x5];
1611  	u8         reserved_at_468[0x2];
1612  	u8         ipsec_offload[0x1];
1613  	u8         log_max_umem[0x5];
1614  	u8         max_num_eqs[0x10];
1615  
1616  	u8         reserved_at_480[0x1];
1617  	u8         tls_tx[0x1];
1618  	u8         tls_rx[0x1];
1619  	u8         log_max_l2_table[0x5];
1620  	u8         reserved_64[0x8];
1621  	u8         log_uar_page_sz[0x10];
1622  
1623  	u8         reserved_65[0x20];
1624  
1625  	u8         device_frequency_mhz[0x20];
1626  
1627  	u8         device_frequency_khz[0x20];
1628  
1629  	u8         reserved_at_500[0x20];
1630  	u8	   num_of_uars_per_page[0x20];
1631  	u8         reserved_at_540[0x40];
1632  
1633  	u8         log_max_atomic_size_qp[0x8];
1634  	u8         reserved_67[0x10];
1635  	u8         log_max_atomic_size_dc[0x8];
1636  
1637  	u8         reserved_at_5a0[0x13];
1638  	u8         log_max_dek[0x5];
1639  	u8         reserved_at_5b8[0x4];
1640  	u8         mini_cqe_resp_stride_index[0x1];
1641  	u8         cqe_128_always[0x1];
1642  	u8         cqe_compression_128b[0x1];
1643  
1644  	u8         cqe_compression[0x1];
1645  
1646  	u8         cqe_compression_timeout[0x10];
1647  	u8         cqe_compression_max_num[0x10];
1648  
1649  	u8         reserved_5e0[0xc0];
1650  
1651  	u8         uctx_cap[0x20];
1652  
1653  	u8         reserved_6c0[0xc0];
1654  
1655  	u8	   vhca_tunnel_commands[0x40];
1656  	u8	   reserved_at_7c0[0x40];
1657  };
1658  
1659  struct mlx5_ifc_cmd_hca_cap_2_bits {
1660  	u8	   reserved_at_0[0x80];
1661  
1662  	u8         migratable[0x1];
1663  	u8         reserved_at_81[0x1f];
1664  
1665  	u8	   max_reformat_insert_size[0x8];
1666  	u8	   max_reformat_insert_offset[0x8];
1667  	u8	   max_reformat_remove_size[0x8];
1668  	u8	   max_reformat_remove_offset[0x8];
1669  
1670  	u8	   reserved_at_c0[0x8];
1671  	u8	   migration_multi_load[0x1];
1672  	u8	   migration_tracking_state[0x1];
1673  	u8	   reserved_at_ca[0x16];
1674  
1675  	u8	   reserved_at_e0[0xc0];
1676  
1677  	u8	   flow_table_type_2_type[0x8];
1678  	u8	   reserved_at_1a8[0x3];
1679  	u8	   log_min_mkey_entity_size[0x5];
1680  	u8	   reserved_at_1b0[0x10];
1681  
1682  	u8	   reserved_at_1c0[0x60];
1683  
1684  	u8	   reserved_at_220[0x1];
1685  	u8	   sw_vhca_id_valid[0x1];
1686  	u8	   sw_vhca_id[0xe];
1687  	u8	   reserved_at_230[0x10];
1688  
1689  	u8	   reserved_at_240[0xb];
1690  	u8	   ts_cqe_metadata_size2wqe_counter[0x5];
1691  	u8	   reserved_at_250[0x10];
1692  
1693  	u8	   reserved_at_260[0x5a0];
1694  };
1695  
1696  enum mlx5_ifc_flow_destination_type {
1697          MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1698          MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1699          MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1700          MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1701          MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
1702          MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
1703  };
1704  
1705  enum mlx5_flow_table_miss_action {
1706          MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1707          MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1708          MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1709  };
1710  
1711  struct mlx5_ifc_extended_dest_format_bits {
1712          struct mlx5_ifc_dest_format_struct_bits destination_entry;
1713  
1714          u8         packet_reformat_id[0x20];
1715  
1716          u8         reserved_at_60[0x20];
1717  };
1718  
1719  union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1720  	struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1721  	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1722  	u8         reserved_0[0x40];
1723  };
1724  
1725  struct mlx5_ifc_fte_match_param_bits {
1726          struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1727  
1728          struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1729  
1730          struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1731  
1732          struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1733  
1734          struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1735  
1736          struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1737  
1738          struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1739  
1740          u8         reserved_at_e00[0x200];
1741  };
1742  
1743  enum {
1744  	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1745  	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1746  	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1747  	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1748  	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1749  };
1750  
1751  struct mlx5_ifc_rx_hash_field_select_bits {
1752  	u8         l3_prot_type[0x1];
1753  	u8         l4_prot_type[0x1];
1754  	u8         selected_fields[0x1e];
1755  };
1756  
1757  struct mlx5_ifc_tls_capabilities_bits {
1758  	u8         tls_1_2_aes_gcm_128[0x1];
1759  	u8         tls_1_3_aes_gcm_128[0x1];
1760  	u8         tls_1_2_aes_gcm_256[0x1];
1761  	u8         tls_1_3_aes_gcm_256[0x1];
1762  	u8         reserved_at_4[0x1c];
1763  
1764  	u8         reserved_at_20[0x7e0];
1765  };
1766  
1767  enum {
1768  	MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
1769  	MLX5_WQ_TYPE_CYCLIC                      = 0x1,
1770  	MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
1771  	MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
1772  };
1773  
1774  enum rq_type {
1775  	RQ_TYPE_NONE,
1776  	RQ_TYPE_STRIDE,
1777  };
1778  
1779  enum {
1780  	MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
1781  	MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
1782  };
1783  
1784  struct mlx5_ifc_wq_bits {
1785  	u8         wq_type[0x4];
1786  	u8         wq_signature[0x1];
1787  	u8         end_padding_mode[0x2];
1788  	u8         cd_slave[0x1];
1789  	u8         reserved_0[0x18];
1790  
1791  	u8         hds_skip_first_sge[0x1];
1792  	u8         log2_hds_buf_size[0x3];
1793  	u8         reserved_1[0x7];
1794  	u8         page_offset[0x5];
1795  	u8         lwm[0x10];
1796  
1797  	u8         reserved_2[0x8];
1798  	u8         pd[0x18];
1799  
1800  	u8         reserved_3[0x8];
1801  	u8         uar_page[0x18];
1802  
1803  	u8         dbr_addr[0x40];
1804  
1805  	u8         hw_counter[0x20];
1806  
1807  	u8         sw_counter[0x20];
1808  
1809  	u8         reserved_4[0xc];
1810  	u8         log_wq_stride[0x4];
1811  	u8         reserved_5[0x3];
1812  	u8         log_wq_pg_sz[0x5];
1813  	u8         reserved_6[0x3];
1814  	u8         log_wq_sz[0x5];
1815  
1816  	u8         dbr_umem_valid[0x1];
1817  	u8         wq_umem_valid[0x1];
1818  	u8         reserved_7[0x13];
1819  	u8         single_wqe_log_num_of_strides[0x3];
1820  	u8         two_byte_shift_en[0x1];
1821  	u8         reserved_8[0x4];
1822  	u8         single_stride_log_num_of_bytes[0x3];
1823  
1824  	u8         reserved_9[0x4c0];
1825  
1826  	struct mlx5_ifc_cmd_pas_bits pas[0];
1827  };
1828  
1829  struct mlx5_ifc_rq_num_bits {
1830  	u8         reserved_0[0x8];
1831  	u8         rq_num[0x18];
1832  };
1833  
1834  struct mlx5_ifc_mac_address_layout_bits {
1835  	u8         reserved_0[0x10];
1836  	u8         mac_addr_47_32[0x10];
1837  
1838  	u8         mac_addr_31_0[0x20];
1839  };
1840  
1841  struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1842  	u8         reserved_0[0xa0];
1843  
1844  	u8         min_time_between_cnps[0x20];
1845  
1846  	u8         reserved_1[0x12];
1847  	u8         cnp_dscp[0x6];
1848  	u8         reserved_2[0x4];
1849  	u8         cnp_prio_mode[0x1];
1850  	u8         cnp_802p_prio[0x3];
1851  
1852  	u8         reserved_3[0x720];
1853  };
1854  
1855  struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1856  	u8         reserved_0[0x60];
1857  
1858  	u8         reserved_1[0x4];
1859  	u8         clamp_tgt_rate[0x1];
1860  	u8         reserved_2[0x3];
1861  	u8         clamp_tgt_rate_after_time_inc[0x1];
1862  	u8         reserved_3[0x17];
1863  
1864  	u8         reserved_4[0x20];
1865  
1866  	u8         rpg_time_reset[0x20];
1867  
1868  	u8         rpg_byte_reset[0x20];
1869  
1870  	u8         rpg_threshold[0x20];
1871  
1872  	u8         rpg_max_rate[0x20];
1873  
1874  	u8         rpg_ai_rate[0x20];
1875  
1876  	u8         rpg_hai_rate[0x20];
1877  
1878  	u8         rpg_gd[0x20];
1879  
1880  	u8         rpg_min_dec_fac[0x20];
1881  
1882  	u8         rpg_min_rate[0x20];
1883  
1884  	u8         reserved_5[0xe0];
1885  
1886  	u8         rate_to_set_on_first_cnp[0x20];
1887  
1888  	u8         dce_tcp_g[0x20];
1889  
1890  	u8         dce_tcp_rtt[0x20];
1891  
1892  	u8         rate_reduce_monitor_period[0x20];
1893  
1894  	u8         reserved_6[0x20];
1895  
1896  	u8         initial_alpha_value[0x20];
1897  
1898  	u8         reserved_7[0x4a0];
1899  };
1900  
1901  struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1902  	u8         reserved_0[0x80];
1903  
1904  	u8         rppp_max_rps[0x20];
1905  
1906  	u8         rpg_time_reset[0x20];
1907  
1908  	u8         rpg_byte_reset[0x20];
1909  
1910  	u8         rpg_threshold[0x20];
1911  
1912  	u8         rpg_max_rate[0x20];
1913  
1914  	u8         rpg_ai_rate[0x20];
1915  
1916  	u8         rpg_hai_rate[0x20];
1917  
1918  	u8         rpg_gd[0x20];
1919  
1920  	u8         rpg_min_dec_fac[0x20];
1921  
1922  	u8         rpg_min_rate[0x20];
1923  
1924  	u8         reserved_1[0x640];
1925  };
1926  
1927  enum {
1928  	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1929  	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1930  	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1931  };
1932  
1933  struct mlx5_ifc_resize_field_select_bits {
1934  	u8         resize_field_select[0x20];
1935  };
1936  
1937  enum {
1938  	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1939  	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1940  	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1941  	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1942  	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE  = 0x10,
1943  	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS          = 0x20,
1944  };
1945  
1946  struct mlx5_ifc_modify_field_select_bits {
1947  	u8         modify_field_select[0x20];
1948  };
1949  
1950  struct mlx5_ifc_field_select_r_roce_np_bits {
1951  	u8         field_select_r_roce_np[0x20];
1952  };
1953  
1954  enum {
1955  	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1956  	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1957  	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1958  	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1959  	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1960  	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1961  	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1962  	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1963  	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1964  	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1965  	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1966  	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1967  	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1968  	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1969  	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1970  };
1971  
1972  struct mlx5_ifc_field_select_r_roce_rp_bits {
1973  	u8         field_select_r_roce_rp[0x20];
1974  };
1975  
1976  enum {
1977  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1978  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1979  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1980  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1981  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1982  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1983  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1984  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1985  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1986  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1987  };
1988  
1989  struct mlx5_ifc_field_select_802_1qau_rp_bits {
1990  	u8         field_select_8021qaurp[0x20];
1991  };
1992  
1993  struct mlx5_ifc_pptb_reg_bits {
1994  	u8         reserved_at_0[0x2];
1995  	u8         mm[0x2];
1996  	u8         reserved_at_4[0x4];
1997  	u8         local_port[0x8];
1998  	u8         reserved_at_10[0x6];
1999  	u8         cm[0x1];
2000  	u8         um[0x1];
2001  	u8         pm[0x8];
2002  
2003  	u8         prio_x_buff[0x20];
2004  
2005  	u8         pm_msb[0x8];
2006  	u8         reserved_at_48[0x10];
2007  	u8         ctrl_buff[0x4];
2008  	u8         untagged_buff[0x4];
2009  };
2010  
2011  struct mlx5_ifc_dcbx_app_reg_bits {
2012  	u8         reserved_0[0x8];
2013  	u8         port_number[0x8];
2014  	u8         reserved_1[0x10];
2015  
2016  	u8         reserved_2[0x1a];
2017  	u8         num_app_prio[0x6];
2018  
2019  	u8         reserved_3[0x40];
2020  
2021  	struct mlx5_ifc_application_prio_entry_bits app_prio[0];
2022  };
2023  
2024  struct mlx5_ifc_dcbx_param_reg_bits {
2025  	u8         dcbx_cee_cap[0x1];
2026  	u8         dcbx_ieee_cap[0x1];
2027  	u8         dcbx_standby_cap[0x1];
2028  	u8         reserved_0[0x5];
2029  	u8         port_number[0x8];
2030  	u8         reserved_1[0xa];
2031  	u8         max_application_table_size[0x6];
2032  
2033  	u8         reserved_2[0x15];
2034  	u8         version_oper[0x3];
2035  	u8         reserved_3[0x5];
2036  	u8         version_admin[0x3];
2037  
2038  	u8         willing_admin[0x1];
2039  	u8         reserved_4[0x3];
2040  	u8         pfc_cap_oper[0x4];
2041  	u8         reserved_5[0x4];
2042  	u8         pfc_cap_admin[0x4];
2043  	u8         reserved_6[0x4];
2044  	u8         num_of_tc_oper[0x4];
2045  	u8         reserved_7[0x4];
2046  	u8         num_of_tc_admin[0x4];
2047  
2048  	u8         remote_willing[0x1];
2049  	u8         reserved_8[0x3];
2050  	u8         remote_pfc_cap[0x4];
2051  	u8         reserved_9[0x14];
2052  	u8         remote_num_of_tc[0x4];
2053  
2054  	u8         reserved_10[0x18];
2055  	u8         error[0x8];
2056  
2057  	u8         reserved_11[0x160];
2058  };
2059  
2060  struct mlx5_ifc_qhll_bits {
2061  	u8         reserved_at_0[0x8];
2062  	u8         local_port[0x8];
2063  	u8         reserved_at_10[0x10];
2064  
2065  	u8         reserved_at_20[0x1b];
2066  	u8         hll_time[0x5];
2067  
2068  	u8         stall_en[0x1];
2069  	u8         reserved_at_41[0x1c];
2070  	u8         stall_cnt[0x3];
2071  };
2072  
2073  struct mlx5_ifc_qetcr_reg_bits {
2074  	u8         operation_type[0x2];
2075  	u8         cap_local_admin[0x1];
2076  	u8         cap_remote_admin[0x1];
2077  	u8         reserved_0[0x4];
2078  	u8         port_number[0x8];
2079  	u8         reserved_1[0x10];
2080  
2081  	u8         reserved_2[0x20];
2082  
2083  	u8         tc[8][0x40];
2084  
2085  	u8         global_configuration[0x40];
2086  };
2087  
2088  struct mlx5_ifc_nodnic_ring_config_reg_bits {
2089  	u8         queue_address_63_32[0x20];
2090  
2091  	u8         queue_address_31_12[0x14];
2092  	u8         reserved_0[0x6];
2093  	u8         log_size[0x6];
2094  
2095  	struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
2096  
2097  	u8         reserved_1[0x8];
2098  	u8         queue_number[0x18];
2099  
2100  	u8         q_key[0x20];
2101  
2102  	u8         reserved_2[0x10];
2103  	u8         pkey_index[0x10];
2104  
2105  	u8         reserved_3[0x40];
2106  };
2107  
2108  struct mlx5_ifc_nodnic_cq_arming_word_bits {
2109  	u8         reserved_0[0x8];
2110  	u8         cq_ci[0x10];
2111  	u8         reserved_1[0x8];
2112  };
2113  
2114  enum {
2115  	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
2116  	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
2117  };
2118  
2119  enum {
2120  	MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
2121  	MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
2122  	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
2123  	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
2124  };
2125  
2126  struct mlx5_ifc_nodnic_event_word_bits {
2127  	u8         driver_reset_needed[0x1];
2128  	u8         port_management_change_event[0x1];
2129  	u8         reserved_0[0x19];
2130  	u8         link_type[0x1];
2131  	u8         port_state[0x4];
2132  };
2133  
2134  struct mlx5_ifc_nic_vport_change_event_bits {
2135  	u8         reserved_0[0x10];
2136  	u8         vport_num[0x10];
2137  
2138  	u8         reserved_1[0xc0];
2139  };
2140  
2141  struct mlx5_ifc_pages_req_event_bits {
2142  	u8         reserved_0[0x10];
2143  	u8         function_id[0x10];
2144  
2145  	u8         num_pages[0x20];
2146  
2147  	u8         reserved_1[0xa0];
2148  };
2149  
2150  struct mlx5_ifc_cmd_inter_comp_event_bits {
2151  	u8         command_completion_vector[0x20];
2152  
2153  	u8         reserved_0[0xc0];
2154  };
2155  
2156  struct mlx5_ifc_stall_vl_event_bits {
2157  	u8         reserved_0[0x18];
2158  	u8         port_num[0x1];
2159  	u8         reserved_1[0x3];
2160  	u8         vl[0x4];
2161  
2162  	u8         reserved_2[0xa0];
2163  };
2164  
2165  struct mlx5_ifc_db_bf_congestion_event_bits {
2166  	u8         event_subtype[0x8];
2167  	u8         reserved_0[0x8];
2168  	u8         congestion_level[0x8];
2169  	u8         reserved_1[0x8];
2170  
2171  	u8         reserved_2[0xa0];
2172  };
2173  
2174  struct mlx5_ifc_gpio_event_bits {
2175  	u8         reserved_0[0x60];
2176  
2177  	u8         gpio_event_hi[0x20];
2178  
2179  	u8         gpio_event_lo[0x20];
2180  
2181  	u8         reserved_1[0x40];
2182  };
2183  
2184  struct mlx5_ifc_port_state_change_event_bits {
2185  	u8         reserved_0[0x40];
2186  
2187  	u8         port_num[0x4];
2188  	u8         reserved_1[0x1c];
2189  
2190  	u8         reserved_2[0x80];
2191  };
2192  
2193  struct mlx5_ifc_dropped_packet_logged_bits {
2194  	u8         reserved_0[0xe0];
2195  };
2196  
2197  enum {
2198  	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2199  	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2200  };
2201  
2202  struct mlx5_ifc_cq_error_bits {
2203  	u8         reserved_0[0x8];
2204  	u8         cqn[0x18];
2205  
2206  	u8         reserved_1[0x20];
2207  
2208  	u8         reserved_2[0x18];
2209  	u8         syndrome[0x8];
2210  
2211  	u8         reserved_3[0x80];
2212  };
2213  
2214  struct mlx5_ifc_rdma_page_fault_event_bits {
2215  	u8         bytes_commited[0x20];
2216  
2217  	u8         r_key[0x20];
2218  
2219  	u8         reserved_0[0x10];
2220  	u8         packet_len[0x10];
2221  
2222  	u8         rdma_op_len[0x20];
2223  
2224  	u8         rdma_va[0x40];
2225  
2226  	u8         reserved_1[0x5];
2227  	u8         rdma[0x1];
2228  	u8         write[0x1];
2229  	u8         requestor[0x1];
2230  	u8         qp_number[0x18];
2231  };
2232  
2233  struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2234  	u8         bytes_committed[0x20];
2235  
2236  	u8         reserved_0[0x10];
2237  	u8         wqe_index[0x10];
2238  
2239  	u8         reserved_1[0x10];
2240  	u8         len[0x10];
2241  
2242  	u8         reserved_2[0x60];
2243  
2244  	u8         reserved_3[0x5];
2245  	u8         rdma[0x1];
2246  	u8         write_read[0x1];
2247  	u8         requestor[0x1];
2248  	u8         qpn[0x18];
2249  };
2250  
2251  enum {
2252  	MLX5_QP_EVENTS_TYPE_QP  = 0x0,
2253  	MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
2254  	MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
2255  };
2256  
2257  struct mlx5_ifc_qp_events_bits {
2258  	u8         reserved_0[0xa0];
2259  
2260  	u8         type[0x8];
2261  	u8         reserved_1[0x18];
2262  
2263  	u8         reserved_2[0x8];
2264  	u8         qpn_rqn_sqn[0x18];
2265  };
2266  
2267  struct mlx5_ifc_dct_events_bits {
2268  	u8         reserved_0[0xc0];
2269  
2270  	u8         reserved_1[0x8];
2271  	u8         dct_number[0x18];
2272  };
2273  
2274  struct mlx5_ifc_comp_event_bits {
2275  	u8         reserved_0[0xc0];
2276  
2277  	u8         reserved_1[0x8];
2278  	u8         cq_number[0x18];
2279  };
2280  
2281  struct mlx5_ifc_fw_version_bits {
2282  	u8         major[0x10];
2283  	u8         reserved_0[0x10];
2284  
2285  	u8         minor[0x10];
2286  	u8         subminor[0x10];
2287  
2288  	u8         second[0x8];
2289  	u8         minute[0x8];
2290  	u8         hour[0x8];
2291  	u8         reserved_1[0x8];
2292  
2293  	u8         year[0x10];
2294  	u8         month[0x8];
2295  	u8         day[0x8];
2296  };
2297  
2298  enum {
2299  	MLX5_QPC_STATE_RST        = 0x0,
2300  	MLX5_QPC_STATE_INIT       = 0x1,
2301  	MLX5_QPC_STATE_RTR        = 0x2,
2302  	MLX5_QPC_STATE_RTS        = 0x3,
2303  	MLX5_QPC_STATE_SQER       = 0x4,
2304  	MLX5_QPC_STATE_SQD        = 0x5,
2305  	MLX5_QPC_STATE_ERR        = 0x6,
2306  	MLX5_QPC_STATE_SUSPENDED  = 0x9,
2307  };
2308  
2309  enum {
2310  	MLX5_QPC_ST_RC            = 0x0,
2311  	MLX5_QPC_ST_UC            = 0x1,
2312  	MLX5_QPC_ST_UD            = 0x2,
2313  	MLX5_QPC_ST_XRC           = 0x3,
2314  	MLX5_QPC_ST_DCI           = 0x5,
2315  	MLX5_QPC_ST_QP0           = 0x7,
2316  	MLX5_QPC_ST_QP1           = 0x8,
2317  	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2318  	MLX5_QPC_ST_REG_UMR       = 0xc,
2319  };
2320  
2321  enum {
2322  	MLX5_QP_PM_ARMED            = 0x0,
2323  	MLX5_QP_PM_REARM            = 0x1,
2324  	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2325  	MLX5_QP_PM_MIGRATED         = 0x3,
2326  };
2327  
2328  enum {
2329  	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2330  	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2331  };
2332  
2333  enum {
2334  	MLX5_QPC_MTU_256_BYTES        = 0x1,
2335  	MLX5_QPC_MTU_512_BYTES        = 0x2,
2336  	MLX5_QPC_MTU_1K_BYTES         = 0x3,
2337  	MLX5_QPC_MTU_2K_BYTES         = 0x4,
2338  	MLX5_QPC_MTU_4K_BYTES         = 0x5,
2339  	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2340  };
2341  
2342  enum {
2343  	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2344  	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2345  	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2346  	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2347  	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2348  	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2349  	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2350  	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2351  };
2352  
2353  enum {
2354  	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2355  	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2356  	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2357  };
2358  
2359  enum {
2360  	MLX5_QPC_CS_RES_DISABLE    = 0x0,
2361  	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2362  	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2363  };
2364  
2365  enum {
2366  	MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2367  	MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
2368  	MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
2369  };
2370  
2371  struct mlx5_ifc_qpc_bits {
2372  	u8         state[0x4];
2373  	u8         lag_tx_port_affinity[0x4];
2374  	u8         st[0x8];
2375  	u8         reserved_1[0x3];
2376  	u8         pm_state[0x2];
2377  	u8         reserved_2[0x7];
2378  	u8         end_padding_mode[0x2];
2379  	u8         reserved_3[0x2];
2380  
2381  	u8         wq_signature[0x1];
2382  	u8         block_lb_mc[0x1];
2383  	u8         atomic_like_write_en[0x1];
2384  	u8         latency_sensitive[0x1];
2385  	u8         reserved_4[0x1];
2386  	u8         drain_sigerr[0x1];
2387  	u8         reserved_5[0x2];
2388  	u8         pd[0x18];
2389  
2390  	u8         mtu[0x3];
2391  	u8         log_msg_max[0x5];
2392  	u8         reserved_6[0x1];
2393  	u8         log_rq_size[0x4];
2394  	u8         log_rq_stride[0x3];
2395  	u8         no_sq[0x1];
2396  	u8         log_sq_size[0x4];
2397  	u8         reserved_at_55[0x3];
2398  	u8         ts_format[0x2];
2399  	u8         reserved_at_5a[0x1];
2400  	u8         rlky[0x1];
2401  	u8         ulp_stateless_offload_mode[0x4];
2402  
2403  	u8         counter_set_id[0x8];
2404  	u8         uar_page[0x18];
2405  
2406  	u8         reserved_8[0x8];
2407  	u8         user_index[0x18];
2408  
2409  	u8         reserved_9[0x3];
2410  	u8         log_page_size[0x5];
2411  	u8         remote_qpn[0x18];
2412  
2413  	struct mlx5_ifc_ads_bits primary_address_path;
2414  
2415  	struct mlx5_ifc_ads_bits secondary_address_path;
2416  
2417  	u8         log_ack_req_freq[0x4];
2418  	u8         reserved_10[0x4];
2419  	u8         log_sra_max[0x3];
2420  	u8         reserved_11[0x2];
2421  	u8         retry_count[0x3];
2422  	u8         rnr_retry[0x3];
2423  	u8         reserved_12[0x1];
2424  	u8         fre[0x1];
2425  	u8         cur_rnr_retry[0x3];
2426  	u8         cur_retry_count[0x3];
2427  	u8         reserved_13[0x5];
2428  
2429  	u8         reserved_14[0x20];
2430  
2431  	u8         reserved_15[0x8];
2432  	u8         next_send_psn[0x18];
2433  
2434  	u8         reserved_16[0x8];
2435  	u8         cqn_snd[0x18];
2436  
2437  	u8         reserved_at_400[0x8];
2438  
2439  	u8         deth_sqpn[0x18];
2440  	u8         reserved_17[0x20];
2441  
2442  	u8         reserved_18[0x8];
2443  	u8         last_acked_psn[0x18];
2444  
2445  	u8         reserved_19[0x8];
2446  	u8         ssn[0x18];
2447  
2448  	u8         reserved_20[0x8];
2449  	u8         log_rra_max[0x3];
2450  	u8         reserved_21[0x1];
2451  	u8         atomic_mode[0x4];
2452  	u8         rre[0x1];
2453  	u8         rwe[0x1];
2454  	u8         rae[0x1];
2455  	u8         reserved_22[0x1];
2456  	u8         page_offset[0x6];
2457  	u8         reserved_23[0x3];
2458  	u8         cd_slave_receive[0x1];
2459  	u8         cd_slave_send[0x1];
2460  	u8         cd_master[0x1];
2461  
2462  	u8         reserved_24[0x3];
2463  	u8         min_rnr_nak[0x5];
2464  	u8         next_rcv_psn[0x18];
2465  
2466  	u8         reserved_25[0x8];
2467  	u8         xrcd[0x18];
2468  
2469  	u8         reserved_26[0x8];
2470  	u8         cqn_rcv[0x18];
2471  
2472  	u8         dbr_addr[0x40];
2473  
2474  	u8         q_key[0x20];
2475  
2476  	u8         reserved_27[0x5];
2477  	u8         rq_type[0x3];
2478  	u8         srqn_rmpn[0x18];
2479  
2480  	u8         reserved_28[0x8];
2481  	u8         rmsn[0x18];
2482  
2483  	u8         hw_sq_wqebb_counter[0x10];
2484  	u8         sw_sq_wqebb_counter[0x10];
2485  
2486  	u8         hw_rq_counter[0x20];
2487  
2488  	u8         sw_rq_counter[0x20];
2489  
2490  	u8         reserved_29[0x20];
2491  
2492  	u8         reserved_30[0xf];
2493  	u8         cgs[0x1];
2494  	u8         cs_req[0x8];
2495  	u8         cs_res[0x8];
2496  
2497  	u8         dc_access_key[0x40];
2498  
2499  	u8         reserved_at_680[0x3];
2500  	u8         dbr_umem_valid[0x1];
2501  
2502  	u8         reserved_at_684[0xbc];
2503  };
2504  
2505  struct mlx5_ifc_roce_addr_layout_bits {
2506  	u8         source_l3_address[16][0x8];
2507  
2508  	u8         reserved_0[0x3];
2509  	u8         vlan_valid[0x1];
2510  	u8         vlan_id[0xc];
2511  	u8         source_mac_47_32[0x10];
2512  
2513  	u8         source_mac_31_0[0x20];
2514  
2515  	u8         reserved_1[0x14];
2516  	u8         roce_l3_type[0x4];
2517  	u8         roce_version[0x8];
2518  
2519  	u8         reserved_2[0x20];
2520  };
2521  
2522  struct mlx5_ifc_rdbc_bits {
2523  	u8         reserved_0[0x1c];
2524  	u8         type[0x4];
2525  
2526  	u8         reserved_1[0x20];
2527  
2528  	u8         reserved_2[0x8];
2529  	u8         psn[0x18];
2530  
2531  	u8         rkey[0x20];
2532  
2533  	u8         address[0x40];
2534  
2535  	u8         byte_count[0x20];
2536  
2537  	u8         reserved_3[0x20];
2538  
2539  	u8         atomic_resp[32][0x8];
2540  };
2541  
2542  struct mlx5_ifc_vlan_bits {
2543  	u8         ethtype[0x10];
2544  	u8         prio[0x3];
2545  	u8         cfi[0x1];
2546  	u8         vid[0xc];
2547  };
2548  
2549  enum {
2550  	MLX5_FLOW_METER_COLOR_RED       = 0x0,
2551  	MLX5_FLOW_METER_COLOR_YELLOW    = 0x1,
2552  	MLX5_FLOW_METER_COLOR_GREEN     = 0x2,
2553  	MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
2554  };
2555  
2556  enum {
2557  	MLX5_EXE_ASO_FLOW_METER         = 0x2,
2558  };
2559  
2560  struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
2561  	u8        return_reg_id[0x4];
2562  	u8        aso_type[0x4];
2563  	u8        reserved_at_8[0x14];
2564  	u8        action[0x1];
2565  	u8        init_color[0x2];
2566  	u8        meter_id[0x1];
2567  };
2568  
2569  union mlx5_ifc_exe_aso_ctrl {
2570  	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
2571  };
2572  
2573  struct mlx5_ifc_execute_aso_bits {
2574  	u8        valid[0x1];
2575  	u8        reserved_at_1[0x7];
2576  	u8        aso_object_id[0x18];
2577  
2578  	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
2579  };
2580  
2581  enum {
2582  	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
2583  };
2584  
2585  struct mlx5_ifc_flow_context_bits {
2586  	struct mlx5_ifc_vlan_bits push_vlan;
2587  
2588  	u8         group_id[0x20];
2589  
2590  	u8         reserved_at_40[0x8];
2591  	u8         flow_tag[0x18];
2592  
2593  	u8         reserved_at_60[0x10];
2594  	u8         action[0x10];
2595  
2596  	u8         extended_destination[0x1];
2597  	u8         reserved_at_81[0x1];
2598  	u8         flow_source[0x2];
2599  	u8         encrypt_decrypt_type[0x4];
2600  	u8         destination_list_size[0x18];
2601  
2602  	u8         reserved_at_a0[0x8];
2603  	u8         flow_counter_list_size[0x18];
2604  
2605  	u8         packet_reformat_id[0x20];
2606  
2607  	u8         modify_header_id[0x20];
2608  
2609  	struct mlx5_ifc_vlan_bits push_vlan_2;
2610  
2611  	u8         encrypt_decrypt_obj_id[0x20];
2612  	u8         reserved_at_140[0xc0];
2613  
2614  	struct mlx5_ifc_fte_match_param_bits match_value;
2615  
2616  	struct mlx5_ifc_execute_aso_bits execute_aso[4];
2617  
2618  	u8         reserved_at_1300[0x500];
2619  
2620  	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
2621  };
2622  
2623  enum {
2624  	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2625  	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2626  };
2627  
2628  struct mlx5_ifc_xrc_srqc_bits {
2629  	u8         state[0x4];
2630  	u8         log_xrc_srq_size[0x4];
2631  	u8         reserved_0[0x18];
2632  
2633  	u8         wq_signature[0x1];
2634  	u8         cont_srq[0x1];
2635  	u8         reserved_1[0x1];
2636  	u8         rlky[0x1];
2637  	u8         basic_cyclic_rcv_wqe[0x1];
2638  	u8         log_rq_stride[0x3];
2639  	u8         xrcd[0x18];
2640  
2641  	u8         page_offset[0x6];
2642  	u8         reserved_at_46[0x1];
2643  	u8         dbr_umem_valid[0x1];
2644  	u8         cqn[0x18];
2645  
2646  	u8         reserved_3[0x20];
2647  
2648  	u8         reserved_4[0x2];
2649  	u8         log_page_size[0x6];
2650  	u8         user_index[0x18];
2651  
2652  	u8         reserved_5[0x20];
2653  
2654  	u8         reserved_6[0x8];
2655  	u8         pd[0x18];
2656  
2657  	u8         lwm[0x10];
2658  	u8         wqe_cnt[0x10];
2659  
2660  	u8         reserved_7[0x40];
2661  
2662  	u8         db_record_addr_h[0x20];
2663  
2664  	u8         db_record_addr_l[0x1e];
2665  	u8         reserved_8[0x2];
2666  
2667  	u8         reserved_9[0x80];
2668  };
2669  
2670  struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2671  	u8         counter_error_queues[0x20];
2672  
2673  	u8         total_error_queues[0x20];
2674  
2675  	u8         send_queue_priority_update_flow[0x20];
2676  
2677  	u8         reserved_at_60[0x20];
2678  
2679  	u8         nic_receive_steering_discard[0x40];
2680  
2681  	u8         receive_discard_vport_down[0x40];
2682  
2683  	u8         transmit_discard_vport_down[0x40];
2684  
2685  	u8         reserved_at_140[0xec0];
2686  };
2687  
2688  struct mlx5_ifc_traffic_counter_bits {
2689  	u8         packets[0x40];
2690  
2691  	u8         octets[0x40];
2692  };
2693  
2694  struct mlx5_ifc_tisc_bits {
2695  	u8         strict_lag_tx_port_affinity[0x1];
2696  	u8         tls_en[0x1];
2697  	u8         reserved_at_2[0x2];
2698  	u8         lag_tx_port_affinity[0x04];
2699  
2700  	u8         reserved_at_8[0x4];
2701  	u8         prio[0x4];
2702  	u8         reserved_1[0x10];
2703  
2704  	u8         reserved_2[0x100];
2705  
2706  	u8         reserved_3[0x8];
2707  	u8         transport_domain[0x18];
2708  
2709  	u8         reserved_4[0x8];
2710  	u8         underlay_qpn[0x18];
2711  
2712  	u8         reserved_5[0x8];
2713  	u8         pd[0x18];
2714  
2715  	u8         reserved_6[0x380];
2716  };
2717  
2718  enum {
2719  	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2720  	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2721  };
2722  
2723  enum {
2724  	MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2725  	MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2726  };
2727  
2728  enum {
2729  	MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
2730  	MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
2731  	MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
2732  };
2733  
2734  enum {
2735  	MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
2736  	MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
2737  };
2738  
2739  struct mlx5_ifc_tirc_bits {
2740  	u8         reserved_0[0x20];
2741  
2742  	u8         disp_type[0x4];
2743  	u8         tls_en[0x1];
2744  	u8         reserved_at_25[0x1b];
2745  
2746  	u8         reserved_2[0x40];
2747  
2748  	u8         reserved_3[0x4];
2749  	u8         lro_timeout_period_usecs[0x10];
2750  	u8         lro_enable_mask[0x4];
2751  	u8         lro_max_msg_sz[0x8];
2752  
2753  	u8         reserved_4[0x40];
2754  
2755  	u8         reserved_5[0x8];
2756  	u8         inline_rqn[0x18];
2757  
2758  	u8         rx_hash_symmetric[0x1];
2759  	u8         reserved_6[0x1];
2760  	u8         tunneled_offload_en[0x1];
2761  	u8         reserved_7[0x5];
2762  	u8         indirect_table[0x18];
2763  
2764  	u8         rx_hash_fn[0x4];
2765  	u8         reserved_8[0x2];
2766  	u8         self_lb_en[0x2];
2767  	u8         transport_domain[0x18];
2768  
2769  	u8         rx_hash_toeplitz_key[10][0x20];
2770  
2771  	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2772  
2773  	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2774  
2775  	u8         reserved_9[0x4c0];
2776  };
2777  
2778  enum {
2779  	MLX5_SRQC_STATE_GOOD   = 0x0,
2780  	MLX5_SRQC_STATE_ERROR  = 0x1,
2781  };
2782  
2783  struct mlx5_ifc_srqc_bits {
2784  	u8         state[0x4];
2785  	u8         log_srq_size[0x4];
2786  	u8         reserved_0[0x18];
2787  
2788  	u8         wq_signature[0x1];
2789  	u8         cont_srq[0x1];
2790  	u8         reserved_1[0x1];
2791  	u8         rlky[0x1];
2792  	u8         reserved_2[0x1];
2793  	u8         log_rq_stride[0x3];
2794  	u8         xrcd[0x18];
2795  
2796  	u8         page_offset[0x6];
2797  	u8         reserved_3[0x2];
2798  	u8         cqn[0x18];
2799  
2800  	u8         reserved_4[0x20];
2801  
2802  	u8         reserved_5[0x2];
2803  	u8         log_page_size[0x6];
2804  	u8         reserved_6[0x18];
2805  
2806  	u8         reserved_7[0x20];
2807  
2808  	u8         reserved_8[0x8];
2809  	u8         pd[0x18];
2810  
2811  	u8         lwm[0x10];
2812  	u8         wqe_cnt[0x10];
2813  
2814  	u8         reserved_9[0x40];
2815  
2816  	u8	   dbr_addr[0x40];
2817  
2818  	u8	   reserved_10[0x80];
2819  };
2820  
2821  enum {
2822  	MLX5_SQC_STATE_RST  = 0x0,
2823  	MLX5_SQC_STATE_RDY  = 0x1,
2824  	MLX5_SQC_STATE_ERR  = 0x3,
2825  };
2826  
2827  enum {
2828  	MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2829  	MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
2830  	MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
2831  };
2832  
2833  struct mlx5_ifc_sqc_bits {
2834  	u8         rlkey[0x1];
2835  	u8         cd_master[0x1];
2836  	u8         fre[0x1];
2837  	u8         flush_in_error_en[0x1];
2838  	u8         allow_multi_pkt_send_wqe[0x1];
2839  	u8         min_wqe_inline_mode[0x3];
2840  	u8         state[0x4];
2841  	u8         reg_umr[0x1];
2842  	u8         allow_swp[0x1];
2843  	u8         reserved_at_e[0x4];
2844  	u8	   qos_remap_en[0x1];
2845  	u8	   reserved_at_d[0x7];
2846  	u8         ts_format[0x2];
2847  	u8         reserved_at_1c[0x4];
2848  
2849  	u8         reserved_1[0x8];
2850  	u8         user_index[0x18];
2851  
2852  	u8         reserved_2[0x8];
2853  	u8         cqn[0x18];
2854  
2855  	u8         reserved_3[0x80];
2856  
2857  	u8         qos_para_vport_number[0x10];
2858  	u8         packet_pacing_rate_limit_index[0x10];
2859  
2860  	u8         tis_lst_sz[0x10];
2861  	u8         qos_queue_group_id[0x10];
2862  
2863  	u8	   reserved_4[0x8];
2864  	u8	   queue_handle[0x18];
2865  
2866  	u8         reserved_5[0x20];
2867  
2868  	u8         reserved_6[0x8];
2869  	u8         tis_num_0[0x18];
2870  
2871  	struct mlx5_ifc_wq_bits wq;
2872  };
2873  
2874  struct mlx5_ifc_query_pp_rate_limit_in_bits {
2875  	u8	   opcode[0x10];
2876  	u8	   uid[0x10];
2877  
2878  	u8	   reserved1[0x10];
2879  	u8         op_mod[0x10];
2880  
2881  	u8         reserved2[0x10];
2882          u8         rate_limit_index[0x10];
2883  
2884  	u8         reserved_3[0x20];
2885  };
2886  
2887  struct mlx5_ifc_pp_context_bits {
2888  	u8	   rate_limit[0x20];
2889  
2890  	u8	   burst_upper_bound[0x20];
2891  
2892  	u8	   reserved_1[0xc];
2893  	u8	   rate_mode[0x4];
2894  	u8	   typical_packet_size[0x10];
2895  
2896  	u8	   reserved_2[0x8];
2897  	u8	   qos_handle[0x18];
2898  
2899  	u8	   reserved_3[0x40];
2900  };
2901  
2902  struct mlx5_ifc_query_pp_rate_limit_out_bits {
2903          u8	   status[0x8];
2904  	u8         reserved_1[0x18];
2905  
2906          u8         syndrome[0x20];
2907  
2908          u8         reserved_2[0x40];
2909  
2910  	struct mlx5_ifc_pp_context_bits pp_context;
2911  };
2912  
2913  enum {
2914  	MLX5_TSAR_TYPE_DWRR = 0,
2915  	MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2916  	MLX5_TSAR_TYPE_ETS = 2
2917  };
2918  
2919  struct mlx5_ifc_tsar_element_attributes_bits {
2920  	u8         reserved_0[0x8];
2921  	u8         tsar_type[0x8];
2922  	u8	   reserved_1[0x10];
2923  };
2924  
2925  struct mlx5_ifc_vport_element_attributes_bits {
2926  	u8         reserved_0[0x10];
2927  	u8         vport_number[0x10];
2928  };
2929  
2930  struct mlx5_ifc_vport_tc_element_attributes_bits {
2931  	u8         traffic_class[0x10];
2932  	u8         vport_number[0x10];
2933  };
2934  
2935  struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2936  	u8         reserved_0[0x0C];
2937  	u8         traffic_class[0x04];
2938  	u8         qos_para_vport_number[0x10];
2939  };
2940  
2941  enum {
2942  	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR           = 0x0,
2943  	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT          = 0x1,
2944  	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC       = 0x2,
2945  	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC  = 0x3,
2946  };
2947  
2948  struct mlx5_ifc_scheduling_context_bits {
2949  	u8         element_type[0x8];
2950  	u8         reserved_at_8[0x18];
2951  
2952  	u8         element_attributes[0x20];
2953  
2954  	u8         parent_element_id[0x20];
2955  
2956  	u8         reserved_at_60[0x40];
2957  
2958  	u8         bw_share[0x20];
2959  
2960  	u8         max_average_bw[0x20];
2961  
2962  	u8         reserved_at_e0[0x120];
2963  };
2964  
2965  struct mlx5_ifc_rqtc_bits {
2966  	u8         reserved_0[0xa0];
2967  
2968  	u8         reserved_1[0x10];
2969  	u8         rqt_max_size[0x10];
2970  
2971  	u8         reserved_2[0x10];
2972  	u8         rqt_actual_size[0x10];
2973  
2974  	u8         reserved_3[0x6a0];
2975  
2976  	struct mlx5_ifc_rq_num_bits rq_num[0];
2977  };
2978  
2979  enum {
2980  	MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
2981  	MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
2982  };
2983  
2984  enum {
2985  	MLX5_RQC_STATE_RST  = 0x0,
2986  	MLX5_RQC_STATE_RDY  = 0x1,
2987  	MLX5_RQC_STATE_ERR  = 0x3,
2988  };
2989  
2990  enum {
2991  	MLX5_RQC_DROPLESS_MODE_DISABLE        = 0x0,
2992  	MLX5_RQC_DROPLESS_MODE_ENABLE         = 0x1,
2993  };
2994  
2995  enum {
2996  	MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2997  	MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
2998  	MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
2999  };
3000  
3001  struct mlx5_ifc_rqc_bits {
3002  	u8         rlkey[0x1];
3003  	u8         delay_drop_en[0x1];
3004  	u8         scatter_fcs[0x1];
3005  	u8         vlan_strip_disable[0x1];
3006  	u8         mem_rq_type[0x4];
3007  	u8         state[0x4];
3008  	u8         reserved_1[0x1];
3009  	u8         flush_in_error_en[0x1];
3010  	u8         reserved_at_e[0xc];
3011  	u8         ts_format[0x2];
3012  	u8         reserved_at_1c[0x4];
3013  
3014  	u8         reserved_3[0x8];
3015  	u8         user_index[0x18];
3016  
3017  	u8         reserved_4[0x8];
3018  	u8         cqn[0x18];
3019  
3020  	u8         counter_set_id[0x8];
3021  	u8         reserved_5[0x18];
3022  
3023  	u8         reserved_6[0x8];
3024  	u8         rmpn[0x18];
3025  
3026  	u8         reserved_7[0xe0];
3027  
3028  	struct mlx5_ifc_wq_bits wq;
3029  };
3030  
3031  enum {
3032  	MLX5_RMPC_STATE_RDY  = 0x1,
3033  	MLX5_RMPC_STATE_ERR  = 0x3,
3034  };
3035  
3036  struct mlx5_ifc_rmpc_bits {
3037  	u8         reserved_0[0x8];
3038  	u8         state[0x4];
3039  	u8         reserved_1[0x14];
3040  
3041  	u8         basic_cyclic_rcv_wqe[0x1];
3042  	u8         reserved_2[0x1f];
3043  
3044  	u8         reserved_3[0x140];
3045  
3046  	struct mlx5_ifc_wq_bits wq;
3047  };
3048  
3049  enum {
3050  	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
3051  	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
3052  	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
3053  };
3054  
3055  struct mlx5_ifc_nic_vport_context_bits {
3056  	u8         reserved_0[0x5];
3057  	u8         min_wqe_inline_mode[0x3];
3058  	u8         reserved_1[0x15];
3059  	u8         disable_mc_local_lb[0x1];
3060  	u8         disable_uc_local_lb[0x1];
3061  	u8         roce_en[0x1];
3062  
3063  	u8         arm_change_event[0x1];
3064  	u8         reserved_2[0x1a];
3065  	u8         event_on_mtu[0x1];
3066  	u8         event_on_promisc_change[0x1];
3067  	u8         event_on_vlan_change[0x1];
3068  	u8         event_on_mc_address_change[0x1];
3069  	u8         event_on_uc_address_change[0x1];
3070  
3071  	u8         reserved_3[0xe0];
3072  
3073  	u8         reserved_4[0x10];
3074  	u8         mtu[0x10];
3075  
3076  	u8         system_image_guid[0x40];
3077  
3078  	u8         port_guid[0x40];
3079  
3080  	u8         node_guid[0x40];
3081  
3082  	u8         reserved_5[0x140];
3083  
3084  	u8         qkey_violation_counter[0x10];
3085  	u8         reserved_6[0x10];
3086  
3087  	u8         reserved_7[0x420];
3088  
3089  	u8         promisc_uc[0x1];
3090  	u8         promisc_mc[0x1];
3091  	u8         promisc_all[0x1];
3092  	u8         reserved_8[0x2];
3093  	u8         allowed_list_type[0x3];
3094  	u8         reserved_9[0xc];
3095  	u8         allowed_list_size[0xc];
3096  
3097  	struct mlx5_ifc_mac_address_layout_bits permanent_address;
3098  
3099  	u8         reserved_10[0x20];
3100  
3101  	u8         current_uc_mac_address[0][0x40];
3102  };
3103  
3104  enum {
3105  	MLX5_ACCESS_MODE_PA        = 0x0,
3106  	MLX5_ACCESS_MODE_MTT       = 0x1,
3107  	MLX5_ACCESS_MODE_KLM       = 0x2,
3108  	MLX5_ACCESS_MODE_KSM       = 0x3,
3109  	MLX5_ACCESS_MODE_SW_ICM    = 0x4,
3110  	MLX5_ACCESS_MODE_MEMIC     = 0x5,
3111  };
3112  
3113  struct mlx5_ifc_mkc_bits {
3114  	u8         reserved_at_0[0x1];
3115  	u8         free[0x1];
3116  	u8         reserved_at_2[0x1];
3117  	u8         access_mode_4_2[0x3];
3118  	u8         reserved_at_6[0x7];
3119  	u8         relaxed_ordering_write[0x1];
3120  	u8         reserved_at_e[0x1];
3121  	u8         small_fence_on_rdma_read_response[0x1];
3122  	u8         umr_en[0x1];
3123  	u8         a[0x1];
3124  	u8         rw[0x1];
3125  	u8         rr[0x1];
3126  	u8         lw[0x1];
3127  	u8         lr[0x1];
3128  	u8         access_mode[0x2];
3129  	u8         reserved_2[0x8];
3130  
3131  	u8         qpn[0x18];
3132  	u8         mkey_7_0[0x8];
3133  
3134  	u8         reserved_3[0x20];
3135  
3136  	u8         length64[0x1];
3137  	u8         bsf_en[0x1];
3138  	u8         sync_umr[0x1];
3139  	u8         reserved_4[0x2];
3140  	u8         expected_sigerr_count[0x1];
3141  	u8         reserved_5[0x1];
3142  	u8         en_rinval[0x1];
3143  	u8         pd[0x18];
3144  
3145  	u8         start_addr[0x40];
3146  
3147  	u8         len[0x40];
3148  
3149  	u8         bsf_octword_size[0x20];
3150  
3151  	u8         reserved_6[0x80];
3152  
3153  	u8         translations_octword_size[0x20];
3154  
3155  	u8         reserved_at_1c0[0x19];
3156  	u8         relaxed_ordering_read[0x1];
3157  	u8         reserved_at_1d9[0x1];
3158  	u8         log_page_size[0x5];
3159  
3160  	u8         reserved_8[0x20];
3161  };
3162  
3163  struct mlx5_ifc_pkey_bits {
3164  	u8         reserved_0[0x10];
3165  	u8         pkey[0x10];
3166  };
3167  
3168  struct mlx5_ifc_array128_auto_bits {
3169  	u8         array128_auto[16][0x8];
3170  };
3171  
3172  enum {
3173  	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
3174  	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
3175  	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
3176  };
3177  
3178  enum {
3179  	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
3180  	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
3181  	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
3182  	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
3183  	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
3184  	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
3185  	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
3186  };
3187  
3188  enum {
3189  	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
3190  	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
3191  	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
3192  };
3193  
3194  enum {
3195  	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
3196  	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
3197  	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
3198  	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
3199  };
3200  
3201  enum {
3202  	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
3203  	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
3204  	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
3205  	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
3206  };
3207  
3208  struct mlx5_ifc_hca_vport_context_bits {
3209  	u8         field_select[0x20];
3210  
3211  	u8         reserved_0[0xe0];
3212  
3213  	u8         sm_virt_aware[0x1];
3214  	u8         has_smi[0x1];
3215  	u8         has_raw[0x1];
3216  	u8         grh_required[0x1];
3217  	u8         reserved_1[0x1];
3218  	u8         min_wqe_inline_mode[0x3];
3219  	u8         reserved_2[0x8];
3220  	u8         port_physical_state[0x4];
3221  	u8         vport_state_policy[0x4];
3222  	u8         port_state[0x4];
3223  	u8         vport_state[0x4];
3224  
3225  	u8         reserved_3[0x20];
3226  
3227  	u8         system_image_guid[0x40];
3228  
3229  	u8         port_guid[0x40];
3230  
3231  	u8         node_guid[0x40];
3232  
3233  	u8         cap_mask1[0x20];
3234  
3235  	u8         cap_mask1_field_select[0x20];
3236  
3237  	u8         cap_mask2[0x20];
3238  
3239  	u8         cap_mask2_field_select[0x20];
3240  
3241  	u8         reserved_4[0x80];
3242  
3243  	u8         lid[0x10];
3244  	u8         reserved_5[0x4];
3245  	u8         init_type_reply[0x4];
3246  	u8         lmc[0x3];
3247  	u8         subnet_timeout[0x5];
3248  
3249  	u8         sm_lid[0x10];
3250  	u8         sm_sl[0x4];
3251  	u8         reserved_6[0xc];
3252  
3253  	u8         qkey_violation_counter[0x10];
3254  	u8         pkey_violation_counter[0x10];
3255  
3256  	u8         reserved_7[0xca0];
3257  };
3258  
3259  union mlx5_ifc_hca_cap_union_bits {
3260  	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3261  	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3262  	struct mlx5_ifc_odp_cap_bits odp_cap;
3263  	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3264  	struct mlx5_ifc_roce_cap_bits roce_cap;
3265  	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3266  	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3267  	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3268  	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3269  	struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
3270  	struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
3271  	struct mlx5_ifc_qos_cap_bits qos_cap;
3272  	struct mlx5_ifc_tls_capabilities_bits tls_capabilities;
3273  	u8         reserved_0[0x8000];
3274  };
3275  
3276  enum {
3277  	MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
3278  	MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
3279  };
3280  
3281  struct mlx5_ifc_flow_table_context_bits {
3282          u8         reformat_en[0x1];
3283          u8         decap_en[0x1];
3284          u8         sw_owner[0x1];
3285          u8         termination_table[0x1];
3286          u8         table_miss_action[0x4];
3287          u8         level[0x8];
3288          u8         reserved_at_10[0x8];
3289          u8         log_size[0x8];
3290  
3291          u8         reserved_at_20[0x8];
3292          u8         table_miss_id[0x18];
3293  
3294          u8         reserved_at_40[0x8];
3295          u8         lag_master_next_table_id[0x18];
3296  
3297          u8         reserved_at_60[0x60];
3298  
3299          u8         sw_owner_icm_root_1[0x40];
3300  
3301          u8         sw_owner_icm_root_0[0x40];
3302  
3303  };
3304  
3305  struct mlx5_ifc_esw_vport_context_bits {
3306  	u8         reserved_0[0x3];
3307  	u8         vport_svlan_strip[0x1];
3308  	u8         vport_cvlan_strip[0x1];
3309  	u8         vport_svlan_insert[0x1];
3310  	u8         vport_cvlan_insert[0x2];
3311  	u8         reserved_1[0x18];
3312  
3313  	u8         reserved_2[0x20];
3314  
3315  	u8         svlan_cfi[0x1];
3316  	u8         svlan_pcp[0x3];
3317  	u8         svlan_id[0xc];
3318  	u8         cvlan_cfi[0x1];
3319  	u8         cvlan_pcp[0x3];
3320  	u8         cvlan_id[0xc];
3321  
3322  	u8         reserved_3[0x7a0];
3323  };
3324  
3325  enum {
3326  	MLX5_EQC_STATUS_OK                = 0x0,
3327  	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3328  };
3329  
3330  enum {
3331  	MLX5_EQ_STATE_ARMED = 0x9,
3332  	MLX5_EQ_STATE_FIRED = 0xa,
3333  };
3334  
3335  struct mlx5_ifc_eqc_bits {
3336  	u8         status[0x4];
3337  	u8         reserved_0[0x9];
3338  	u8         ec[0x1];
3339  	u8         oi[0x1];
3340  	u8         reserved_1[0x5];
3341  	u8         st[0x4];
3342  	u8         reserved_2[0x8];
3343  
3344  	u8         reserved_3[0x20];
3345  
3346  	u8         reserved_4[0x14];
3347  	u8         page_offset[0x6];
3348  	u8         reserved_5[0x6];
3349  
3350  	u8         reserved_6[0x3];
3351  	u8         log_eq_size[0x5];
3352  	u8         uar_page[0x18];
3353  
3354  	u8         reserved_7[0x20];
3355  
3356  	u8         reserved_8[0x18];
3357  	u8         intr[0x8];
3358  
3359  	u8         reserved_9[0x3];
3360  	u8         log_page_size[0x5];
3361  	u8         reserved_10[0x18];
3362  
3363  	u8         reserved_11[0x60];
3364  
3365  	u8         reserved_12[0x8];
3366  	u8         consumer_counter[0x18];
3367  
3368  	u8         reserved_13[0x8];
3369  	u8         producer_counter[0x18];
3370  
3371  	u8         reserved_14[0x80];
3372  };
3373  
3374  enum {
3375  	MLX5_DCTC_STATE_ACTIVE    = 0x0,
3376  	MLX5_DCTC_STATE_DRAINING  = 0x1,
3377  	MLX5_DCTC_STATE_DRAINED   = 0x2,
3378  };
3379  
3380  enum {
3381  	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3382  	MLX5_DCTC_CS_RES_NA         = 0x1,
3383  	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3384  };
3385  
3386  enum {
3387  	MLX5_DCTC_MTU_256_BYTES  = 0x1,
3388  	MLX5_DCTC_MTU_512_BYTES  = 0x2,
3389  	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3390  	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3391  	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3392  };
3393  
3394  struct mlx5_ifc_dctc_bits {
3395  	u8         reserved_0[0x4];
3396  	u8         state[0x4];
3397  	u8         reserved_1[0x18];
3398  
3399  	u8         reserved_2[0x8];
3400  	u8         user_index[0x18];
3401  
3402  	u8         reserved_3[0x8];
3403  	u8         cqn[0x18];
3404  
3405  	u8         counter_set_id[0x8];
3406  	u8         atomic_mode[0x4];
3407  	u8         rre[0x1];
3408  	u8         rwe[0x1];
3409  	u8         rae[0x1];
3410  	u8         atomic_like_write_en[0x1];
3411  	u8         latency_sensitive[0x1];
3412  	u8         rlky[0x1];
3413  	u8         reserved_4[0xe];
3414  
3415  	u8         reserved_5[0x8];
3416  	u8         cs_res[0x8];
3417  	u8         reserved_6[0x3];
3418  	u8         min_rnr_nak[0x5];
3419  	u8         reserved_7[0x8];
3420  
3421  	u8         reserved_8[0x8];
3422  	u8         srqn[0x18];
3423  
3424  	u8         reserved_9[0x8];
3425  	u8         pd[0x18];
3426  
3427  	u8         tclass[0x8];
3428  	u8         reserved_10[0x4];
3429  	u8         flow_label[0x14];
3430  
3431  	u8         dc_access_key[0x40];
3432  
3433  	u8         reserved_11[0x5];
3434  	u8         mtu[0x3];
3435  	u8         port[0x8];
3436  	u8         pkey_index[0x10];
3437  
3438  	u8         reserved_12[0x8];
3439  	u8         my_addr_index[0x8];
3440  	u8         reserved_13[0x8];
3441  	u8         hop_limit[0x8];
3442  
3443  	u8         dc_access_key_violation_count[0x20];
3444  
3445  	u8         reserved_14[0x14];
3446  	u8         dei_cfi[0x1];
3447  	u8         eth_prio[0x3];
3448  	u8         ecn[0x2];
3449  	u8         dscp[0x6];
3450  
3451  	u8         reserved_15[0x40];
3452  };
3453  
3454  enum {
3455  	MLX5_CQC_STATUS_OK             = 0x0,
3456  	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3457  	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3458  };
3459  
3460  enum {
3461  	CQE_SIZE_64                = 0x0,
3462  	CQE_SIZE_128               = 0x1,
3463  };
3464  
3465  enum {
3466  	MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
3467  	MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
3468  };
3469  
3470  enum {
3471  	MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
3472  	MLX5_CQ_STATE_ARMED                               = 0x9,
3473  	MLX5_CQ_STATE_FIRED                               = 0xa,
3474  };
3475  
3476  struct mlx5_ifc_cqc_bits {
3477  	u8         status[0x4];
3478  	u8         reserved_at_4[0x2];
3479  	u8         dbr_umem_valid[0x1];
3480  	u8         reserved_at_7[0x1];
3481  	u8         cqe_sz[0x3];
3482  	u8         cc[0x1];
3483  	u8         reserved_1[0x1];
3484  	u8         scqe_break_moderation_en[0x1];
3485  	u8         oi[0x1];
3486  	u8         cq_period_mode[0x2];
3487  	u8         cqe_compression_en[0x1];
3488  	u8         mini_cqe_res_format[0x2];
3489  	u8         st[0x4];
3490  	u8         reserved_2[0x8];
3491  
3492  	u8         reserved_3[0x20];
3493  
3494  	u8         reserved_4[0x14];
3495  	u8         page_offset[0x6];
3496  	u8         reserved_5[0x6];
3497  
3498  	u8         reserved_6[0x3];
3499  	u8         log_cq_size[0x5];
3500  	u8         uar_page[0x18];
3501  
3502  	u8         reserved_7[0x4];
3503  	u8         cq_period[0xc];
3504  	u8         cq_max_count[0x10];
3505  
3506  	u8         reserved_8[0x18];
3507  	u8         c_eqn[0x8];
3508  
3509  	u8         reserved_9[0x3];
3510  	u8         log_page_size[0x5];
3511  	u8         reserved_10[0x18];
3512  
3513  	u8         reserved_11[0x20];
3514  
3515  	u8         reserved_12[0x8];
3516  	u8         last_notified_index[0x18];
3517  
3518  	u8         reserved_13[0x8];
3519  	u8         last_solicit_index[0x18];
3520  
3521  	u8         reserved_14[0x8];
3522  	u8         consumer_counter[0x18];
3523  
3524  	u8         reserved_15[0x8];
3525  	u8         producer_counter[0x18];
3526  
3527  	u8         reserved_16[0x40];
3528  
3529  	u8         dbr_addr[0x40];
3530  };
3531  
3532  union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3533  	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3534  	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3535  	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3536  	u8         reserved_0[0x800];
3537  };
3538  
3539  struct mlx5_ifc_query_adapter_param_block_bits {
3540  	u8         reserved_0[0xc0];
3541  
3542  	u8         reserved_1[0x8];
3543  	u8         ieee_vendor_id[0x18];
3544  
3545  	u8         reserved_2[0x10];
3546  	u8         vsd_vendor_id[0x10];
3547  
3548  	u8         vsd[208][0x8];
3549  
3550  	u8         vsd_contd_psid[16][0x8];
3551  };
3552  
3553  union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3554  	struct mlx5_ifc_modify_field_select_bits modify_field_select;
3555  	struct mlx5_ifc_resize_field_select_bits resize_field_select;
3556  	u8         reserved_0[0x20];
3557  };
3558  
3559  union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3560  	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3561  	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3562  	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3563  	u8         reserved_0[0x20];
3564  };
3565  
3566  struct mlx5_ifc_bufferx_reg_bits {
3567  	u8         reserved_0[0x6];
3568  	u8         lossy[0x1];
3569  	u8         epsb[0x1];
3570  	u8         reserved_1[0xc];
3571  	u8         size[0xc];
3572  
3573  	u8         xoff_threshold[0x10];
3574  	u8         xon_threshold[0x10];
3575  };
3576  
3577  struct mlx5_ifc_config_item_bits {
3578  	u8         valid[0x2];
3579  	u8         reserved_0[0x2];
3580  	u8         header_type[0x2];
3581  	u8         reserved_1[0x2];
3582  	u8         default_location[0x1];
3583  	u8         reserved_2[0x7];
3584  	u8         version[0x4];
3585  	u8         reserved_3[0x3];
3586  	u8         length[0x9];
3587  
3588  	u8         type[0x20];
3589  
3590  	u8         reserved_4[0x10];
3591  	u8         crc16[0x10];
3592  };
3593  
3594  enum {
3595  	MLX5_XRQC_STATE_GOOD   = 0x0,
3596  	MLX5_XRQC_STATE_ERROR  = 0x1,
3597  };
3598  
3599  enum {
3600  	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3601  	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3602  };
3603  
3604  enum {
3605  	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3606  };
3607  
3608  struct mlx5_ifc_tag_matching_topology_context_bits {
3609  	u8         log_matching_list_sz[0x4];
3610  	u8         reserved_at_4[0xc];
3611  	u8         append_next_index[0x10];
3612  
3613  	u8         sw_phase_cnt[0x10];
3614  	u8         hw_phase_cnt[0x10];
3615  
3616  	u8         reserved_at_40[0x40];
3617  };
3618  
3619  struct mlx5_ifc_xrqc_bits {
3620  	u8         state[0x4];
3621  	u8         rlkey[0x1];
3622  	u8         reserved_at_5[0xf];
3623  	u8         topology[0x4];
3624  	u8         reserved_at_18[0x4];
3625  	u8         offload[0x4];
3626  
3627  	u8         reserved_at_20[0x8];
3628  	u8         user_index[0x18];
3629  
3630  	u8         reserved_at_40[0x8];
3631  	u8         cqn[0x18];
3632  
3633  	u8         reserved_at_60[0xa0];
3634  
3635  	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3636  
3637  	u8         reserved_at_180[0x280];
3638  
3639  	struct mlx5_ifc_wq_bits wq;
3640  };
3641  
3642  struct mlx5_ifc_nodnic_port_config_reg_bits {
3643  	struct mlx5_ifc_nodnic_event_word_bits event;
3644  
3645  	u8         network_en[0x1];
3646  	u8         dma_en[0x1];
3647  	u8         promisc_en[0x1];
3648  	u8         promisc_multicast_en[0x1];
3649  	u8         reserved_0[0x17];
3650  	u8         receive_filter_en[0x5];
3651  
3652  	u8         reserved_1[0x10];
3653  	u8         mac_47_32[0x10];
3654  
3655  	u8         mac_31_0[0x20];
3656  
3657  	u8         receive_filters_mgid_mac[64][0x8];
3658  
3659  	u8         gid[16][0x8];
3660  
3661  	u8         reserved_2[0x10];
3662  	u8         lid[0x10];
3663  
3664  	u8         reserved_3[0xc];
3665  	u8         sm_sl[0x4];
3666  	u8         sm_lid[0x10];
3667  
3668  	u8         completion_address_63_32[0x20];
3669  
3670  	u8         completion_address_31_12[0x14];
3671  	u8         reserved_4[0x6];
3672  	u8         log_cq_size[0x6];
3673  
3674  	u8         working_buffer_address_63_32[0x20];
3675  
3676  	u8         working_buffer_address_31_12[0x14];
3677  	u8         reserved_5[0xc];
3678  
3679  	struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
3680  
3681  	u8         pkey_index[0x10];
3682  	u8         pkey[0x10];
3683  
3684  	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
3685  
3686  	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
3687  
3688  	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
3689  
3690  	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
3691  
3692  	u8         reserved_6[0x400];
3693  };
3694  
3695  union mlx5_ifc_event_auto_bits {
3696  	struct mlx5_ifc_comp_event_bits comp_event;
3697  	struct mlx5_ifc_dct_events_bits dct_events;
3698  	struct mlx5_ifc_qp_events_bits qp_events;
3699  	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3700  	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3701  	struct mlx5_ifc_cq_error_bits cq_error;
3702  	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3703  	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3704  	struct mlx5_ifc_gpio_event_bits gpio_event;
3705  	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3706  	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3707  	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3708  	struct mlx5_ifc_pages_req_event_bits pages_req_event;
3709  	struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
3710  	u8         reserved_0[0xe0];
3711  };
3712  
3713  struct mlx5_ifc_health_buffer_bits {
3714  	u8         reserved_0[0x100];
3715  
3716  	u8         assert_existptr[0x20];
3717  
3718  	u8         assert_callra[0x20];
3719  
3720  	u8         reserved_1[0x40];
3721  
3722  	u8         fw_version[0x20];
3723  
3724  	u8         hw_id[0x20];
3725  
3726  	u8         reserved_2[0x20];
3727  
3728  	u8         irisc_index[0x8];
3729  	u8         synd[0x8];
3730  	u8         ext_synd[0x10];
3731  };
3732  
3733  struct mlx5_ifc_register_loopback_control_bits {
3734  	u8         no_lb[0x1];
3735  	u8         reserved_0[0x7];
3736  	u8         port[0x8];
3737  	u8         reserved_1[0x10];
3738  
3739  	u8         reserved_2[0x60];
3740  };
3741  
3742  struct mlx5_ifc_lrh_bits {
3743  	u8	vl[4];
3744  	u8	lver[4];
3745  	u8	sl[4];
3746  	u8	reserved2[2];
3747  	u8	lnh[2];
3748  	u8	dlid[16];
3749  	u8	reserved5[5];
3750  	u8	pkt_len[11];
3751  	u8	slid[16];
3752  };
3753  
3754  struct mlx5_ifc_icmd_set_wol_rol_out_bits {
3755  	u8         reserved_0[0x40];
3756  
3757  	u8         reserved_1[0x10];
3758  	u8         rol_mode[0x8];
3759  	u8         wol_mode[0x8];
3760  };
3761  
3762  struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3763  	u8         reserved_0[0x40];
3764  
3765  	u8         rol_mode_valid[0x1];
3766  	u8         wol_mode_valid[0x1];
3767  	u8         reserved_1[0xe];
3768  	u8         rol_mode[0x8];
3769  	u8         wol_mode[0x8];
3770  
3771  	u8         reserved_2[0x7a0];
3772  };
3773  
3774  struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3775  	u8         virtual_mac_en[0x1];
3776  	u8         mac_aux_v[0x1];
3777  	u8         reserved_0[0x1e];
3778  
3779  	u8         reserved_1[0x40];
3780  
3781  	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3782  
3783  	u8         reserved_2[0x760];
3784  };
3785  
3786  struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3787  	u8         virtual_mac_en[0x1];
3788  	u8         mac_aux_v[0x1];
3789  	u8         reserved_0[0x1e];
3790  
3791  	struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3792  
3793  	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3794  
3795  	u8         reserved_1[0x760];
3796  };
3797  
3798  struct mlx5_ifc_icmd_query_fw_info_out_bits {
3799  	struct mlx5_ifc_fw_version_bits fw_version;
3800  
3801  	u8         reserved_0[0x10];
3802  	u8         hash_signature[0x10];
3803  
3804  	u8         psid[16][0x8];
3805  
3806  	u8         reserved_1[0x6e0];
3807  };
3808  
3809  struct mlx5_ifc_icmd_query_cap_in_bits {
3810  	u8         reserved_0[0x10];
3811  	u8         capability_group[0x10];
3812  };
3813  
3814  struct mlx5_ifc_icmd_query_cap_general_bits {
3815  	u8         nv_access[0x1];
3816  	u8         fw_info_psid[0x1];
3817  	u8         reserved_0[0x1e];
3818  
3819  	u8         reserved_1[0x16];
3820  	u8         rol_s[0x1];
3821  	u8         rol_g[0x1];
3822  	u8         reserved_2[0x1];
3823  	u8         wol_s[0x1];
3824  	u8         wol_g[0x1];
3825  	u8         wol_a[0x1];
3826  	u8         wol_b[0x1];
3827  	u8         wol_m[0x1];
3828  	u8         wol_u[0x1];
3829  	u8         wol_p[0x1];
3830  };
3831  
3832  struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3833  	u8         status[0x8];
3834  	u8         reserved_0[0x18];
3835  
3836  	u8         reserved_1[0x7e0];
3837  };
3838  
3839  struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3840  	u8         status[0x8];
3841  	u8         reserved_0[0x18];
3842  
3843  	u8         reserved_1[0x7e0];
3844  };
3845  
3846  struct mlx5_ifc_icmd_ocbb_init_in_bits {
3847  	u8         address_hi[0x20];
3848  
3849  	u8         address_lo[0x20];
3850  
3851  	u8         reserved_0[0x7c0];
3852  };
3853  
3854  struct mlx5_ifc_icmd_init_ocsd_in_bits {
3855  	u8         reserved_0[0x20];
3856  
3857  	u8         address_hi[0x20];
3858  
3859  	u8         address_lo[0x20];
3860  
3861  	u8         reserved_1[0x7a0];
3862  };
3863  
3864  struct mlx5_ifc_icmd_access_reg_out_bits {
3865  	u8         reserved_0[0x11];
3866  	u8         status[0x7];
3867  	u8         reserved_1[0x8];
3868  
3869  	u8         register_id[0x10];
3870  	u8         reserved_2[0x10];
3871  
3872  	u8         reserved_3[0x40];
3873  
3874  	u8         reserved_4[0x5];
3875  	u8         len[0xb];
3876  	u8         reserved_5[0x10];
3877  
3878  	u8         register_data[0][0x20];
3879  };
3880  
3881  enum {
3882  	MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
3883  	MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
3884  };
3885  
3886  struct mlx5_ifc_icmd_access_reg_in_bits {
3887  	u8         constant_1[0x5];
3888  	u8         constant_2[0xb];
3889  	u8         reserved_0[0x10];
3890  
3891  	u8         register_id[0x10];
3892  	u8         reserved_1[0x1];
3893  	u8         method[0x7];
3894  	u8         constant_3[0x8];
3895  
3896  	u8         reserved_2[0x40];
3897  
3898  	u8         constant_4[0x5];
3899  	u8         len[0xb];
3900  	u8         reserved_3[0x10];
3901  
3902  	u8         register_data[0][0x20];
3903  };
3904  
3905  enum {
3906  	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3907  	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3908  };
3909  
3910  struct mlx5_ifc_teardown_hca_out_bits {
3911  	u8         status[0x8];
3912  	u8         reserved_0[0x18];
3913  
3914  	u8         syndrome[0x20];
3915  
3916  	u8         reserved_1[0x3f];
3917  
3918  	u8	   state[0x1];
3919  };
3920  
3921  enum {
3922  	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3923  	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3924  	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3925  };
3926  
3927  struct mlx5_ifc_teardown_hca_in_bits {
3928  	u8         opcode[0x10];
3929  	u8         reserved_0[0x10];
3930  
3931  	u8         reserved_1[0x10];
3932  	u8         op_mod[0x10];
3933  
3934  	u8         reserved_2[0x10];
3935  	u8         profile[0x10];
3936  
3937  	u8         reserved_3[0x20];
3938  };
3939  
3940  struct mlx5_ifc_set_delay_drop_params_out_bits {
3941  	u8         status[0x8];
3942  	u8         reserved_at_8[0x18];
3943  
3944  	u8         syndrome[0x20];
3945  
3946  	u8         reserved_at_40[0x40];
3947  };
3948  
3949  struct mlx5_ifc_set_delay_drop_params_in_bits {
3950  	u8         opcode[0x10];
3951  	u8         reserved_at_10[0x10];
3952  
3953  	u8         reserved_at_20[0x10];
3954  	u8         op_mod[0x10];
3955  
3956  	u8         reserved_at_40[0x20];
3957  
3958  	u8         reserved_at_60[0x10];
3959  	u8         delay_drop_timeout[0x10];
3960  };
3961  
3962  struct mlx5_ifc_query_delay_drop_params_out_bits {
3963  	u8         status[0x8];
3964  	u8         reserved_at_8[0x18];
3965  
3966  	u8         syndrome[0x20];
3967  
3968  	u8         reserved_at_40[0x20];
3969  
3970  	u8         reserved_at_60[0x10];
3971  	u8         delay_drop_timeout[0x10];
3972  };
3973  
3974  struct mlx5_ifc_query_delay_drop_params_in_bits {
3975  	u8         opcode[0x10];
3976  	u8         reserved_at_10[0x10];
3977  
3978  	u8         reserved_at_20[0x10];
3979  	u8         op_mod[0x10];
3980  
3981  	u8         reserved_at_40[0x40];
3982  };
3983  
3984  struct mlx5_ifc_suspend_qp_out_bits {
3985  	u8         status[0x8];
3986  	u8         reserved_0[0x18];
3987  
3988  	u8         syndrome[0x20];
3989  
3990  	u8         reserved_1[0x40];
3991  };
3992  
3993  struct mlx5_ifc_suspend_qp_in_bits {
3994  	u8         opcode[0x10];
3995  	u8         reserved_0[0x10];
3996  
3997  	u8         reserved_1[0x10];
3998  	u8         op_mod[0x10];
3999  
4000  	u8         reserved_2[0x8];
4001  	u8         qpn[0x18];
4002  
4003  	u8         reserved_3[0x20];
4004  };
4005  
4006  struct mlx5_ifc_sqerr2rts_qp_out_bits {
4007  	u8         status[0x8];
4008  	u8         reserved_0[0x18];
4009  
4010  	u8         syndrome[0x20];
4011  
4012  	u8         reserved_1[0x40];
4013  };
4014  
4015  struct mlx5_ifc_sqerr2rts_qp_in_bits {
4016  	u8         opcode[0x10];
4017  	u8         uid[0x10];
4018  
4019  	u8         reserved_1[0x10];
4020  	u8         op_mod[0x10];
4021  
4022  	u8         reserved_2[0x8];
4023  	u8         qpn[0x18];
4024  
4025  	u8         reserved_3[0x20];
4026  
4027  	u8         opt_param_mask[0x20];
4028  
4029  	u8         reserved_4[0x20];
4030  
4031  	struct mlx5_ifc_qpc_bits qpc;
4032  
4033  	u8         reserved_5[0x80];
4034  };
4035  
4036  struct mlx5_ifc_sqd2rts_qp_out_bits {
4037  	u8         status[0x8];
4038  	u8         reserved_0[0x18];
4039  
4040  	u8         syndrome[0x20];
4041  
4042  	u8         reserved_1[0x40];
4043  };
4044  
4045  struct mlx5_ifc_sqd2rts_qp_in_bits {
4046  	u8         opcode[0x10];
4047  	u8         uid[0x10];
4048  
4049  	u8         reserved_1[0x10];
4050  	u8         op_mod[0x10];
4051  
4052  	u8         reserved_2[0x8];
4053  	u8         qpn[0x18];
4054  
4055  	u8         reserved_3[0x20];
4056  
4057  	u8         opt_param_mask[0x20];
4058  
4059  	u8         reserved_4[0x20];
4060  
4061  	struct mlx5_ifc_qpc_bits qpc;
4062  
4063  	u8         reserved_5[0x80];
4064  };
4065  
4066  struct mlx5_ifc_set_wol_rol_out_bits {
4067  	u8         status[0x8];
4068  	u8         reserved_0[0x18];
4069  
4070  	u8         syndrome[0x20];
4071  
4072  	u8         reserved_1[0x40];
4073  };
4074  
4075  struct mlx5_ifc_set_wol_rol_in_bits {
4076  	u8         opcode[0x10];
4077  	u8         reserved_0[0x10];
4078  
4079  	u8         reserved_1[0x10];
4080  	u8         op_mod[0x10];
4081  
4082  	u8         rol_mode_valid[0x1];
4083  	u8         wol_mode_valid[0x1];
4084  	u8         reserved_2[0xe];
4085  	u8         rol_mode[0x8];
4086  	u8         wol_mode[0x8];
4087  
4088  	u8         reserved_3[0x20];
4089  };
4090  
4091  struct mlx5_ifc_set_roce_address_out_bits {
4092  	u8         status[0x8];
4093  	u8         reserved_0[0x18];
4094  
4095  	u8         syndrome[0x20];
4096  
4097  	u8         reserved_1[0x40];
4098  };
4099  
4100  struct mlx5_ifc_set_roce_address_in_bits {
4101  	u8         opcode[0x10];
4102  	u8         reserved_0[0x10];
4103  
4104  	u8         reserved_1[0x10];
4105  	u8         op_mod[0x10];
4106  
4107  	u8         roce_address_index[0x10];
4108  	u8         reserved_2[0x10];
4109  
4110  	u8         reserved_3[0x20];
4111  
4112  	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4113  };
4114  
4115  struct mlx5_ifc_set_rdb_out_bits {
4116  	u8         status[0x8];
4117  	u8         reserved_0[0x18];
4118  
4119  	u8         syndrome[0x20];
4120  
4121  	u8         reserved_1[0x40];
4122  };
4123  
4124  struct mlx5_ifc_set_rdb_in_bits {
4125  	u8         opcode[0x10];
4126  	u8         reserved_0[0x10];
4127  
4128  	u8         reserved_1[0x10];
4129  	u8         op_mod[0x10];
4130  
4131  	u8         reserved_2[0x8];
4132  	u8         qpn[0x18];
4133  
4134  	u8         reserved_3[0x18];
4135  	u8         rdb_list_size[0x8];
4136  
4137  	struct mlx5_ifc_rdbc_bits rdb_context[0];
4138  };
4139  
4140  struct mlx5_ifc_set_mad_demux_out_bits {
4141  	u8         status[0x8];
4142  	u8         reserved_0[0x18];
4143  
4144  	u8         syndrome[0x20];
4145  
4146  	u8         reserved_1[0x40];
4147  };
4148  
4149  enum {
4150  	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4151  	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4152  };
4153  
4154  struct mlx5_ifc_set_mad_demux_in_bits {
4155  	u8         opcode[0x10];
4156  	u8         reserved_0[0x10];
4157  
4158  	u8         reserved_1[0x10];
4159  	u8         op_mod[0x10];
4160  
4161  	u8         reserved_2[0x20];
4162  
4163  	u8         reserved_3[0x6];
4164  	u8         demux_mode[0x2];
4165  	u8         reserved_4[0x18];
4166  };
4167  
4168  struct mlx5_ifc_set_l2_table_entry_out_bits {
4169  	u8         status[0x8];
4170  	u8         reserved_0[0x18];
4171  
4172  	u8         syndrome[0x20];
4173  
4174  	u8         reserved_1[0x40];
4175  };
4176  
4177  struct mlx5_ifc_set_l2_table_entry_in_bits {
4178  	u8         opcode[0x10];
4179  	u8         reserved_0[0x10];
4180  
4181  	u8         reserved_1[0x10];
4182  	u8         op_mod[0x10];
4183  
4184  	u8         reserved_2[0x60];
4185  
4186  	u8         reserved_3[0x8];
4187  	u8         table_index[0x18];
4188  
4189  	u8         reserved_4[0x20];
4190  
4191  	u8         reserved_5[0x13];
4192  	u8         vlan_valid[0x1];
4193  	u8         vlan[0xc];
4194  
4195  	struct mlx5_ifc_mac_address_layout_bits mac_address;
4196  
4197  	u8         reserved_6[0xc0];
4198  };
4199  
4200  struct mlx5_ifc_set_issi_out_bits {
4201  	u8         status[0x8];
4202  	u8         reserved_0[0x18];
4203  
4204  	u8         syndrome[0x20];
4205  
4206  	u8         reserved_1[0x40];
4207  };
4208  
4209  struct mlx5_ifc_set_issi_in_bits {
4210  	u8         opcode[0x10];
4211  	u8         reserved_0[0x10];
4212  
4213  	u8         reserved_1[0x10];
4214  	u8         op_mod[0x10];
4215  
4216  	u8         reserved_2[0x10];
4217  	u8         current_issi[0x10];
4218  
4219  	u8         reserved_3[0x20];
4220  };
4221  
4222  struct mlx5_ifc_set_hca_cap_out_bits {
4223  	u8         status[0x8];
4224  	u8         reserved_0[0x18];
4225  
4226  	u8         syndrome[0x20];
4227  
4228  	u8         reserved_1[0x40];
4229  };
4230  
4231  struct mlx5_ifc_set_hca_cap_in_bits {
4232  	u8         opcode[0x10];
4233  	u8         reserved_0[0x10];
4234  
4235  	u8         reserved_1[0x10];
4236  	u8         op_mod[0x10];
4237  
4238  	u8         reserved_2[0x40];
4239  
4240  	union mlx5_ifc_hca_cap_union_bits capability;
4241  };
4242  
4243  enum {
4244  	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION			= 0x0,
4245  	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG		= 0x1,
4246  	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST	= 0x2,
4247  	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS		= 0x3
4248  };
4249  
4250  struct mlx5_ifc_set_flow_table_root_out_bits {
4251  	u8         status[0x8];
4252  	u8         reserved_0[0x18];
4253  
4254  	u8         syndrome[0x20];
4255  
4256  	u8         reserved_1[0x40];
4257  };
4258  
4259  struct mlx5_ifc_set_flow_table_root_in_bits {
4260          u8         opcode[0x10];
4261          u8         reserved_at_10[0x10];
4262  
4263          u8         reserved_at_20[0x10];
4264          u8         op_mod[0x10];
4265  
4266          u8         other_vport[0x1];
4267          u8         reserved_at_41[0xf];
4268          u8         vport_number[0x10];
4269  
4270          u8         reserved_at_60[0x20];
4271  
4272          u8         table_type[0x8];
4273          u8         reserved_at_88[0x7];
4274          u8         table_of_other_vport[0x1];
4275          u8         table_vport_number[0x10];
4276  
4277          u8         reserved_at_a0[0x8];
4278          u8         table_id[0x18];
4279  
4280          u8         reserved_at_c0[0x8];
4281          u8         underlay_qpn[0x18];
4282          u8         table_eswitch_owner_vhca_id_valid[0x1];
4283          u8         reserved_at_e1[0xf];
4284          u8         table_eswitch_owner_vhca_id[0x10];
4285          u8         reserved_at_100[0x100];
4286  };
4287  
4288  struct mlx5_ifc_set_fte_out_bits {
4289  	u8         status[0x8];
4290  	u8         reserved_0[0x18];
4291  
4292  	u8         syndrome[0x20];
4293  
4294  	u8         reserved_1[0x40];
4295  };
4296  
4297  struct mlx5_ifc_set_fte_in_bits {
4298          u8         opcode[0x10];
4299          u8         reserved_at_10[0x10];
4300  
4301          u8         reserved_at_20[0x10];
4302          u8         op_mod[0x10];
4303  
4304          u8         other_vport[0x1];
4305          u8         reserved_at_41[0xf];
4306          u8         vport_number[0x10];
4307  
4308          u8         reserved_at_60[0x20];
4309  
4310          u8         table_type[0x8];
4311          u8         reserved_at_88[0x18];
4312  
4313          u8         reserved_at_a0[0x8];
4314          u8         table_id[0x18];
4315  
4316          u8         ignore_flow_level[0x1];
4317          u8         reserved_at_c1[0x17];
4318          u8         modify_enable_mask[0x8];
4319  
4320          u8         reserved_at_e0[0x20];
4321  
4322          u8         flow_index[0x20];
4323  
4324          u8         reserved_at_120[0xe0];
4325  
4326          struct mlx5_ifc_flow_context_bits flow_context;
4327  };
4328  
4329  struct mlx5_ifc_set_driver_version_out_bits {
4330  	u8         status[0x8];
4331  	u8         reserved_0[0x18];
4332  
4333  	u8         syndrome[0x20];
4334  
4335  	u8         reserved_1[0x40];
4336  };
4337  
4338  struct mlx5_ifc_set_driver_version_in_bits {
4339  	u8         opcode[0x10];
4340  	u8         reserved_0[0x10];
4341  
4342  	u8         reserved_1[0x10];
4343  	u8         op_mod[0x10];
4344  
4345  	u8         reserved_2[0x40];
4346  
4347  	u8         driver_version[64][0x8];
4348  };
4349  
4350  struct mlx5_ifc_set_dc_cnak_trace_out_bits {
4351  	u8         status[0x8];
4352  	u8         reserved_0[0x18];
4353  
4354  	u8         syndrome[0x20];
4355  
4356  	u8         reserved_1[0x40];
4357  };
4358  
4359  struct mlx5_ifc_set_dc_cnak_trace_in_bits {
4360  	u8         opcode[0x10];
4361  	u8         reserved_0[0x10];
4362  
4363  	u8         reserved_1[0x10];
4364  	u8         op_mod[0x10];
4365  
4366  	u8         enable[0x1];
4367  	u8         reserved_2[0x1f];
4368  
4369  	u8         reserved_3[0x160];
4370  
4371  	struct mlx5_ifc_cmd_pas_bits pas;
4372  };
4373  
4374  struct mlx5_ifc_set_burst_size_out_bits {
4375  	u8         status[0x8];
4376  	u8         reserved_0[0x18];
4377  
4378  	u8         syndrome[0x20];
4379  
4380  	u8         reserved_1[0x40];
4381  };
4382  
4383  struct mlx5_ifc_set_burst_size_in_bits {
4384  	u8         opcode[0x10];
4385  	u8         reserved_0[0x10];
4386  
4387  	u8         reserved_1[0x10];
4388  	u8         op_mod[0x10];
4389  
4390  	u8         reserved_2[0x20];
4391  
4392  	u8         reserved_3[0x9];
4393  	u8         device_burst_size[0x17];
4394  };
4395  
4396  struct mlx5_ifc_rts2rts_qp_out_bits {
4397  	u8         status[0x8];
4398  	u8         reserved_0[0x18];
4399  
4400  	u8         syndrome[0x20];
4401  
4402  	u8         reserved_1[0x40];
4403  };
4404  
4405  struct mlx5_ifc_rts2rts_qp_in_bits {
4406  	u8         opcode[0x10];
4407  	u8         uid[0x10];
4408  
4409  	u8         reserved_1[0x10];
4410  	u8         op_mod[0x10];
4411  
4412  	u8         reserved_2[0x8];
4413  	u8         qpn[0x18];
4414  
4415  	u8         reserved_3[0x20];
4416  
4417  	u8         opt_param_mask[0x20];
4418  
4419  	u8         reserved_4[0x20];
4420  
4421  	struct mlx5_ifc_qpc_bits qpc;
4422  
4423  	u8         reserved_5[0x80];
4424  };
4425  
4426  struct mlx5_ifc_rtr2rts_qp_out_bits {
4427  	u8         status[0x8];
4428  	u8         reserved_0[0x18];
4429  
4430  	u8         syndrome[0x20];
4431  
4432  	u8         reserved_1[0x40];
4433  };
4434  
4435  struct mlx5_ifc_rtr2rts_qp_in_bits {
4436  	u8         opcode[0x10];
4437  	u8         uid[0x10];
4438  
4439  	u8         reserved_1[0x10];
4440  	u8         op_mod[0x10];
4441  
4442  	u8         reserved_2[0x8];
4443  	u8         qpn[0x18];
4444  
4445  	u8         reserved_3[0x20];
4446  
4447  	u8         opt_param_mask[0x20];
4448  
4449  	u8         reserved_4[0x20];
4450  
4451  	struct mlx5_ifc_qpc_bits qpc;
4452  
4453  	u8         reserved_5[0x80];
4454  };
4455  
4456  struct mlx5_ifc_rst2init_qp_out_bits {
4457  	u8         status[0x8];
4458  	u8         reserved_0[0x18];
4459  
4460  	u8         syndrome[0x20];
4461  
4462  	u8         reserved_1[0x40];
4463  };
4464  
4465  struct mlx5_ifc_rst2init_qp_in_bits {
4466  	u8         opcode[0x10];
4467  	u8         uid[0x10];
4468  
4469  	u8         reserved_1[0x10];
4470  	u8         op_mod[0x10];
4471  
4472  	u8         reserved_2[0x8];
4473  	u8         qpn[0x18];
4474  
4475  	u8         reserved_3[0x20];
4476  
4477  	u8         opt_param_mask[0x20];
4478  
4479  	u8         reserved_4[0x20];
4480  
4481  	struct mlx5_ifc_qpc_bits qpc;
4482  
4483  	u8         reserved_5[0x80];
4484  };
4485  
4486  struct mlx5_ifc_query_xrq_out_bits {
4487  	u8         status[0x8];
4488  	u8         reserved_at_8[0x18];
4489  
4490  	u8         syndrome[0x20];
4491  
4492  	u8         reserved_at_40[0x40];
4493  
4494  	struct mlx5_ifc_xrqc_bits xrq_context;
4495  };
4496  
4497  struct mlx5_ifc_query_xrq_in_bits {
4498  	u8         opcode[0x10];
4499  	u8         reserved_at_10[0x10];
4500  
4501  	u8         reserved_at_20[0x10];
4502  	u8         op_mod[0x10];
4503  
4504  	u8         reserved_at_40[0x8];
4505  	u8         xrqn[0x18];
4506  
4507  	u8         reserved_at_60[0x20];
4508  };
4509  
4510  struct mlx5_ifc_resume_qp_out_bits {
4511  	u8         status[0x8];
4512  	u8         reserved_0[0x18];
4513  
4514  	u8         syndrome[0x20];
4515  
4516  	u8         reserved_1[0x40];
4517  };
4518  
4519  struct mlx5_ifc_resume_qp_in_bits {
4520  	u8         opcode[0x10];
4521  	u8         reserved_0[0x10];
4522  
4523  	u8         reserved_1[0x10];
4524  	u8         op_mod[0x10];
4525  
4526  	u8         reserved_2[0x8];
4527  	u8         qpn[0x18];
4528  
4529  	u8         reserved_3[0x20];
4530  };
4531  
4532  struct mlx5_ifc_query_xrc_srq_out_bits {
4533  	u8         status[0x8];
4534  	u8         reserved_0[0x18];
4535  
4536  	u8         syndrome[0x20];
4537  
4538  	u8         reserved_1[0x40];
4539  
4540  	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4541  
4542  	u8         reserved_2[0x600];
4543  
4544  	u8         pas[0][0x40];
4545  };
4546  
4547  struct mlx5_ifc_query_xrc_srq_in_bits {
4548  	u8         opcode[0x10];
4549  	u8         uid[0x10];
4550  
4551  	u8         reserved_1[0x10];
4552  	u8         op_mod[0x10];
4553  
4554  	u8         reserved_2[0x8];
4555  	u8         xrc_srqn[0x18];
4556  
4557  	u8         reserved_3[0x20];
4558  };
4559  
4560  struct mlx5_ifc_query_wol_rol_out_bits {
4561  	u8         status[0x8];
4562  	u8         reserved_0[0x18];
4563  
4564  	u8         syndrome[0x20];
4565  
4566  	u8         reserved_1[0x10];
4567  	u8         rol_mode[0x8];
4568  	u8         wol_mode[0x8];
4569  
4570  	u8         reserved_2[0x20];
4571  };
4572  
4573  struct mlx5_ifc_query_wol_rol_in_bits {
4574  	u8         opcode[0x10];
4575  	u8         reserved_0[0x10];
4576  
4577  	u8         reserved_1[0x10];
4578  	u8         op_mod[0x10];
4579  
4580  	u8         reserved_2[0x40];
4581  };
4582  
4583  enum {
4584  	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4585  	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4586  };
4587  
4588  struct mlx5_ifc_query_vport_state_out_bits {
4589  	u8         status[0x8];
4590  	u8         reserved_0[0x18];
4591  
4592  	u8         syndrome[0x20];
4593  
4594  	u8         reserved_1[0x20];
4595  
4596  	u8         reserved_2[0x18];
4597  	u8         admin_state[0x4];
4598  	u8         state[0x4];
4599  };
4600  
4601  enum {
4602  	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
4603  	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
4604  	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
4605  };
4606  
4607  enum {
4608          MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
4609          MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
4610          MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
4611          MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
4612          MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
4613          MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
4614          MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
4615          MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
4616          MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
4617          MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
4618          MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
4619          MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
4620          MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
4621          MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
4622  };
4623  
4624  struct mlx5_ifc_query_vport_state_in_bits {
4625  	u8         opcode[0x10];
4626  	u8         reserved_0[0x10];
4627  
4628  	u8         reserved_1[0x10];
4629  	u8         op_mod[0x10];
4630  
4631  	u8         other_vport[0x1];
4632  	u8         reserved_2[0xf];
4633  	u8         vport_number[0x10];
4634  
4635  	u8         reserved_3[0x20];
4636  };
4637  
4638  struct mlx5_ifc_query_vnic_env_out_bits {
4639  	u8         status[0x8];
4640  	u8         reserved_at_8[0x18];
4641  
4642  	u8         syndrome[0x20];
4643  
4644  	u8         reserved_at_40[0x40];
4645  
4646  	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4647  };
4648  
4649  enum {
4650  	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4651  };
4652  
4653  struct mlx5_ifc_query_vnic_env_in_bits {
4654  	u8         opcode[0x10];
4655  	u8         reserved_at_10[0x10];
4656  
4657  	u8         reserved_at_20[0x10];
4658  	u8         op_mod[0x10];
4659  
4660  	u8         other_vport[0x1];
4661  	u8         reserved_at_41[0xf];
4662  	u8         vport_number[0x10];
4663  
4664  	u8         reserved_at_60[0x20];
4665  };
4666  
4667  struct mlx5_ifc_query_vport_counter_out_bits {
4668  	u8         status[0x8];
4669  	u8         reserved_0[0x18];
4670  
4671  	u8         syndrome[0x20];
4672  
4673  	u8         reserved_1[0x40];
4674  
4675  	struct mlx5_ifc_traffic_counter_bits received_errors;
4676  
4677  	struct mlx5_ifc_traffic_counter_bits transmit_errors;
4678  
4679  	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4680  
4681  	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4682  
4683  	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4684  
4685  	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4686  
4687  	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4688  
4689  	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4690  
4691  	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4692  
4693  	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4694  
4695  	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4696  
4697  	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4698  
4699  	u8         reserved_2[0xa00];
4700  };
4701  
4702  enum {
4703  	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4704  };
4705  
4706  struct mlx5_ifc_query_vport_counter_in_bits {
4707  	u8         opcode[0x10];
4708  	u8         reserved_0[0x10];
4709  
4710  	u8         reserved_1[0x10];
4711  	u8         op_mod[0x10];
4712  
4713  	u8         other_vport[0x1];
4714  	u8         reserved_2[0xb];
4715  	u8         port_num[0x4];
4716  	u8         vport_number[0x10];
4717  
4718  	u8         reserved_3[0x60];
4719  
4720  	u8         clear[0x1];
4721  	u8         reserved_4[0x1f];
4722  
4723  	u8         reserved_5[0x20];
4724  };
4725  
4726  struct mlx5_ifc_query_tis_out_bits {
4727  	u8         status[0x8];
4728  	u8         reserved_0[0x18];
4729  
4730  	u8         syndrome[0x20];
4731  
4732  	u8         reserved_1[0x40];
4733  
4734  	struct mlx5_ifc_tisc_bits tis_context;
4735  };
4736  
4737  struct mlx5_ifc_query_tis_in_bits {
4738  	u8         opcode[0x10];
4739  	u8         reserved_0[0x10];
4740  
4741  	u8         reserved_1[0x10];
4742  	u8         op_mod[0x10];
4743  
4744  	u8         reserved_2[0x8];
4745  	u8         tisn[0x18];
4746  
4747  	u8         reserved_3[0x20];
4748  };
4749  
4750  struct mlx5_ifc_query_tir_out_bits {
4751  	u8         status[0x8];
4752  	u8         reserved_0[0x18];
4753  
4754  	u8         syndrome[0x20];
4755  
4756  	u8         reserved_1[0xc0];
4757  
4758  	struct mlx5_ifc_tirc_bits tir_context;
4759  };
4760  
4761  struct mlx5_ifc_query_tir_in_bits {
4762  	u8         opcode[0x10];
4763  	u8         reserved_0[0x10];
4764  
4765  	u8         reserved_1[0x10];
4766  	u8         op_mod[0x10];
4767  
4768  	u8         reserved_2[0x8];
4769  	u8         tirn[0x18];
4770  
4771  	u8         reserved_3[0x20];
4772  };
4773  
4774  struct mlx5_ifc_query_srq_out_bits {
4775  	u8         status[0x8];
4776  	u8         reserved_0[0x18];
4777  
4778  	u8         syndrome[0x20];
4779  
4780  	u8         reserved_1[0x40];
4781  
4782  	struct mlx5_ifc_srqc_bits srq_context_entry;
4783  
4784  	u8         reserved_2[0x600];
4785  
4786  	u8         pas[0][0x40];
4787  };
4788  
4789  struct mlx5_ifc_query_srq_in_bits {
4790  	u8         opcode[0x10];
4791  	u8         reserved_0[0x10];
4792  
4793  	u8         reserved_1[0x10];
4794  	u8         op_mod[0x10];
4795  
4796  	u8         reserved_2[0x8];
4797  	u8         srqn[0x18];
4798  
4799  	u8         reserved_3[0x20];
4800  };
4801  
4802  struct mlx5_ifc_query_sq_out_bits {
4803  	u8         status[0x8];
4804  	u8         reserved_0[0x18];
4805  
4806  	u8         syndrome[0x20];
4807  
4808  	u8         reserved_1[0xc0];
4809  
4810  	struct mlx5_ifc_sqc_bits sq_context;
4811  };
4812  
4813  struct mlx5_ifc_query_sq_in_bits {
4814  	u8         opcode[0x10];
4815  	u8         reserved_0[0x10];
4816  
4817  	u8         reserved_1[0x10];
4818  	u8         op_mod[0x10];
4819  
4820  	u8         reserved_2[0x8];
4821  	u8         sqn[0x18];
4822  
4823  	u8         reserved_3[0x20];
4824  };
4825  
4826  struct mlx5_ifc_query_special_contexts_out_bits {
4827  	u8         status[0x8];
4828  	u8         reserved_0[0x18];
4829  
4830  	u8         syndrome[0x20];
4831  
4832  	u8	   dump_fill_mkey[0x20];
4833  
4834  	u8         resd_lkey[0x20];
4835  };
4836  
4837  struct mlx5_ifc_query_special_contexts_in_bits {
4838  	u8         opcode[0x10];
4839  	u8         reserved_0[0x10];
4840  
4841  	u8         reserved_1[0x10];
4842  	u8         op_mod[0x10];
4843  
4844  	u8         reserved_2[0x40];
4845  };
4846  
4847  struct mlx5_ifc_query_scheduling_element_out_bits {
4848  	u8         status[0x8];
4849  	u8         reserved_at_8[0x18];
4850  
4851  	u8         syndrome[0x20];
4852  
4853  	u8         reserved_at_40[0xc0];
4854  
4855  	struct mlx5_ifc_scheduling_context_bits scheduling_context;
4856  
4857  	u8         reserved_at_300[0x100];
4858  };
4859  
4860  enum {
4861  	MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4862  };
4863  
4864  struct mlx5_ifc_query_scheduling_element_in_bits {
4865  	u8         opcode[0x10];
4866  	u8         reserved_at_10[0x10];
4867  
4868  	u8         reserved_at_20[0x10];
4869  	u8         op_mod[0x10];
4870  
4871  	u8         scheduling_hierarchy[0x8];
4872  	u8         reserved_at_48[0x18];
4873  
4874  	u8         scheduling_element_id[0x20];
4875  
4876  	u8         reserved_at_80[0x180];
4877  };
4878  
4879  struct mlx5_ifc_query_rqt_out_bits {
4880  	u8         status[0x8];
4881  	u8         reserved_0[0x18];
4882  
4883  	u8         syndrome[0x20];
4884  
4885  	u8         reserved_1[0xc0];
4886  
4887  	struct mlx5_ifc_rqtc_bits rqt_context;
4888  };
4889  
4890  struct mlx5_ifc_query_rqt_in_bits {
4891  	u8         opcode[0x10];
4892  	u8         reserved_0[0x10];
4893  
4894  	u8         reserved_1[0x10];
4895  	u8         op_mod[0x10];
4896  
4897  	u8         reserved_2[0x8];
4898  	u8         rqtn[0x18];
4899  
4900  	u8         reserved_3[0x20];
4901  };
4902  
4903  struct mlx5_ifc_query_rq_out_bits {
4904  	u8         status[0x8];
4905  	u8         reserved_0[0x18];
4906  
4907  	u8         syndrome[0x20];
4908  
4909  	u8         reserved_1[0xc0];
4910  
4911  	struct mlx5_ifc_rqc_bits rq_context;
4912  };
4913  
4914  struct mlx5_ifc_query_rq_in_bits {
4915  	u8         opcode[0x10];
4916  	u8         reserved_0[0x10];
4917  
4918  	u8         reserved_1[0x10];
4919  	u8         op_mod[0x10];
4920  
4921  	u8         reserved_2[0x8];
4922  	u8         rqn[0x18];
4923  
4924  	u8         reserved_3[0x20];
4925  };
4926  
4927  struct mlx5_ifc_query_roce_address_out_bits {
4928  	u8         status[0x8];
4929  	u8         reserved_0[0x18];
4930  
4931  	u8         syndrome[0x20];
4932  
4933  	u8         reserved_1[0x40];
4934  
4935  	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4936  };
4937  
4938  struct mlx5_ifc_query_roce_address_in_bits {
4939  	u8         opcode[0x10];
4940  	u8         reserved_0[0x10];
4941  
4942  	u8         reserved_1[0x10];
4943  	u8         op_mod[0x10];
4944  
4945  	u8         roce_address_index[0x10];
4946  	u8         reserved_2[0x10];
4947  
4948  	u8         reserved_3[0x20];
4949  };
4950  
4951  struct mlx5_ifc_query_rmp_out_bits {
4952  	u8         status[0x8];
4953  	u8         reserved_0[0x18];
4954  
4955  	u8         syndrome[0x20];
4956  
4957  	u8         reserved_1[0xc0];
4958  
4959  	struct mlx5_ifc_rmpc_bits rmp_context;
4960  };
4961  
4962  struct mlx5_ifc_query_rmp_in_bits {
4963  	u8         opcode[0x10];
4964  	u8         reserved_0[0x10];
4965  
4966  	u8         reserved_1[0x10];
4967  	u8         op_mod[0x10];
4968  
4969  	u8         reserved_2[0x8];
4970  	u8         rmpn[0x18];
4971  
4972  	u8         reserved_3[0x20];
4973  };
4974  
4975  struct mlx5_ifc_query_rdb_out_bits {
4976  	u8         status[0x8];
4977  	u8         reserved_0[0x18];
4978  
4979  	u8         syndrome[0x20];
4980  
4981  	u8         reserved_1[0x20];
4982  
4983  	u8         reserved_2[0x18];
4984  	u8         rdb_list_size[0x8];
4985  
4986  	struct mlx5_ifc_rdbc_bits rdb_context[0];
4987  };
4988  
4989  struct mlx5_ifc_query_rdb_in_bits {
4990  	u8         opcode[0x10];
4991  	u8         reserved_0[0x10];
4992  
4993  	u8         reserved_1[0x10];
4994  	u8         op_mod[0x10];
4995  
4996  	u8         reserved_2[0x8];
4997  	u8         qpn[0x18];
4998  
4999  	u8         reserved_3[0x20];
5000  };
5001  
5002  struct mlx5_ifc_query_qp_out_bits {
5003  	u8         status[0x8];
5004  	u8         reserved_0[0x18];
5005  
5006  	u8         syndrome[0x20];
5007  
5008  	u8         reserved_1[0x40];
5009  
5010  	u8         opt_param_mask[0x20];
5011  
5012  	u8         reserved_2[0x20];
5013  
5014  	struct mlx5_ifc_qpc_bits qpc;
5015  
5016  	u8         reserved_3[0x80];
5017  
5018  	u8         pas[0][0x40];
5019  };
5020  
5021  struct mlx5_ifc_query_qp_in_bits {
5022  	u8         opcode[0x10];
5023  	u8         reserved_0[0x10];
5024  
5025  	u8         reserved_1[0x10];
5026  	u8         op_mod[0x10];
5027  
5028  	u8         reserved_2[0x8];
5029  	u8         qpn[0x18];
5030  
5031  	u8         reserved_3[0x20];
5032  };
5033  
5034  struct mlx5_ifc_query_q_counter_out_bits {
5035  	u8         status[0x8];
5036  	u8         reserved_0[0x18];
5037  
5038  	u8         syndrome[0x20];
5039  
5040  	u8         reserved_1[0x40];
5041  
5042  	u8         rx_write_requests[0x20];
5043  
5044  	u8         reserved_2[0x20];
5045  
5046  	u8         rx_read_requests[0x20];
5047  
5048  	u8         reserved_3[0x20];
5049  
5050  	u8         rx_atomic_requests[0x20];
5051  
5052  	u8         reserved_4[0x20];
5053  
5054  	u8         rx_dct_connect[0x20];
5055  
5056  	u8         reserved_5[0x20];
5057  
5058  	u8         out_of_buffer[0x20];
5059  
5060  	u8         reserved_7[0x20];
5061  
5062  	u8         out_of_sequence[0x20];
5063  
5064  	u8         reserved_8[0x20];
5065  
5066  	u8         duplicate_request[0x20];
5067  
5068  	u8         reserved_9[0x20];
5069  
5070  	u8         rnr_nak_retry_err[0x20];
5071  
5072  	u8         reserved_10[0x20];
5073  
5074  	u8         packet_seq_err[0x20];
5075  
5076  	u8         reserved_11[0x20];
5077  
5078  	u8         implied_nak_seq_err[0x20];
5079  
5080  	u8         reserved_12[0x20];
5081  
5082  	u8         local_ack_timeout_err[0x20];
5083  
5084  	u8         reserved_13[0x20];
5085  
5086  	u8         resp_rnr_nak[0x20];
5087  
5088  	u8         reserved_14[0x20];
5089  
5090  	u8         req_rnr_retries_exceeded[0x20];
5091  
5092  	u8         reserved_15[0x460];
5093  };
5094  
5095  struct mlx5_ifc_query_q_counter_in_bits {
5096  	u8         opcode[0x10];
5097  	u8         reserved_0[0x10];
5098  
5099  	u8         reserved_1[0x10];
5100  	u8         op_mod[0x10];
5101  
5102  	u8         reserved_2[0x80];
5103  
5104  	u8         clear[0x1];
5105  	u8         reserved_3[0x1f];
5106  
5107  	u8         reserved_4[0x18];
5108  	u8         counter_set_id[0x8];
5109  };
5110  
5111  struct mlx5_ifc_query_pages_out_bits {
5112  	u8         status[0x8];
5113  	u8         reserved_0[0x18];
5114  
5115  	u8         syndrome[0x20];
5116  
5117  	u8         reserved_1[0x10];
5118  	u8         function_id[0x10];
5119  
5120  	u8         num_pages[0x20];
5121  };
5122  
5123  enum {
5124  	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES	  = 0x1,
5125  	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES	  = 0x2,
5126  	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5127  };
5128  
5129  struct mlx5_ifc_query_pages_in_bits {
5130  	u8         opcode[0x10];
5131  	u8         reserved_0[0x10];
5132  
5133  	u8         reserved_1[0x10];
5134  	u8         op_mod[0x10];
5135  
5136  	u8         reserved_2[0x10];
5137  	u8         function_id[0x10];
5138  
5139  	u8         reserved_3[0x20];
5140  };
5141  
5142  struct mlx5_ifc_query_nic_vport_context_out_bits {
5143  	u8         status[0x8];
5144  	u8         reserved_0[0x18];
5145  
5146  	u8         syndrome[0x20];
5147  
5148  	u8         reserved_1[0x40];
5149  
5150  	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5151  };
5152  
5153  struct mlx5_ifc_query_nic_vport_context_in_bits {
5154  	u8         opcode[0x10];
5155  	u8         reserved_0[0x10];
5156  
5157  	u8         reserved_1[0x10];
5158  	u8         op_mod[0x10];
5159  
5160  	u8         other_vport[0x1];
5161  	u8         reserved_2[0xf];
5162  	u8         vport_number[0x10];
5163  
5164  	u8         reserved_3[0x5];
5165  	u8         allowed_list_type[0x3];
5166  	u8         reserved_4[0x18];
5167  };
5168  
5169  struct mlx5_ifc_query_mkey_out_bits {
5170  	u8         status[0x8];
5171  	u8         reserved_0[0x18];
5172  
5173  	u8         syndrome[0x20];
5174  
5175  	u8         reserved_1[0x40];
5176  
5177  	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5178  
5179  	u8         reserved_2[0x600];
5180  
5181  	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5182  
5183  	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5184  };
5185  
5186  struct mlx5_ifc_query_mkey_in_bits {
5187  	u8         opcode[0x10];
5188  	u8         reserved_0[0x10];
5189  
5190  	u8         reserved_1[0x10];
5191  	u8         op_mod[0x10];
5192  
5193  	u8         reserved_2[0x8];
5194  	u8         mkey_index[0x18];
5195  
5196  	u8         pg_access[0x1];
5197  	u8         reserved_3[0x1f];
5198  };
5199  
5200  struct mlx5_ifc_query_mad_demux_out_bits {
5201  	u8         status[0x8];
5202  	u8         reserved_0[0x18];
5203  
5204  	u8         syndrome[0x20];
5205  
5206  	u8         reserved_1[0x40];
5207  
5208  	u8         mad_dumux_parameters_block[0x20];
5209  };
5210  
5211  struct mlx5_ifc_query_mad_demux_in_bits {
5212  	u8         opcode[0x10];
5213  	u8         reserved_0[0x10];
5214  
5215  	u8         reserved_1[0x10];
5216  	u8         op_mod[0x10];
5217  
5218  	u8         reserved_2[0x40];
5219  };
5220  
5221  struct mlx5_ifc_query_l2_table_entry_out_bits {
5222  	u8         status[0x8];
5223  	u8         reserved_0[0x18];
5224  
5225  	u8         syndrome[0x20];
5226  
5227  	u8         reserved_1[0xa0];
5228  
5229  	u8         reserved_2[0x13];
5230  	u8         vlan_valid[0x1];
5231  	u8         vlan[0xc];
5232  
5233  	struct mlx5_ifc_mac_address_layout_bits mac_address;
5234  
5235  	u8         reserved_3[0xc0];
5236  };
5237  
5238  struct mlx5_ifc_query_l2_table_entry_in_bits {
5239  	u8         opcode[0x10];
5240  	u8         reserved_0[0x10];
5241  
5242  	u8         reserved_1[0x10];
5243  	u8         op_mod[0x10];
5244  
5245  	u8         reserved_2[0x60];
5246  
5247  	u8         reserved_3[0x8];
5248  	u8         table_index[0x18];
5249  
5250  	u8         reserved_4[0x140];
5251  };
5252  
5253  struct mlx5_ifc_query_issi_out_bits {
5254  	u8         status[0x8];
5255  	u8         reserved_0[0x18];
5256  
5257  	u8         syndrome[0x20];
5258  
5259  	u8         reserved_1[0x10];
5260  	u8         current_issi[0x10];
5261  
5262  	u8         reserved_2[0xa0];
5263  
5264  	u8         supported_issi_reserved[76][0x8];
5265  	u8         supported_issi_dw0[0x20];
5266  };
5267  
5268  struct mlx5_ifc_query_issi_in_bits {
5269  	u8         opcode[0x10];
5270  	u8         reserved_0[0x10];
5271  
5272  	u8         reserved_1[0x10];
5273  	u8         op_mod[0x10];
5274  
5275  	u8         reserved_2[0x40];
5276  };
5277  
5278  struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5279  	u8         status[0x8];
5280  	u8         reserved_0[0x18];
5281  
5282  	u8         syndrome[0x20];
5283  
5284  	u8         reserved_1[0x40];
5285  
5286  	struct mlx5_ifc_pkey_bits pkey[0];
5287  };
5288  
5289  struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5290  	u8         opcode[0x10];
5291  	u8         reserved_0[0x10];
5292  
5293  	u8         reserved_1[0x10];
5294  	u8         op_mod[0x10];
5295  
5296  	u8         other_vport[0x1];
5297  	u8         reserved_2[0xb];
5298  	u8         port_num[0x4];
5299  	u8         vport_number[0x10];
5300  
5301  	u8         reserved_3[0x10];
5302  	u8         pkey_index[0x10];
5303  };
5304  
5305  struct mlx5_ifc_query_hca_vport_gid_out_bits {
5306  	u8         status[0x8];
5307  	u8         reserved_0[0x18];
5308  
5309  	u8         syndrome[0x20];
5310  
5311  	u8         reserved_1[0x20];
5312  
5313  	u8         gids_num[0x10];
5314  	u8         reserved_2[0x10];
5315  
5316  	struct mlx5_ifc_array128_auto_bits gid[0];
5317  };
5318  
5319  struct mlx5_ifc_query_hca_vport_gid_in_bits {
5320  	u8         opcode[0x10];
5321  	u8         reserved_0[0x10];
5322  
5323  	u8         reserved_1[0x10];
5324  	u8         op_mod[0x10];
5325  
5326  	u8         other_vport[0x1];
5327  	u8         reserved_2[0xb];
5328  	u8         port_num[0x4];
5329  	u8         vport_number[0x10];
5330  
5331  	u8         reserved_3[0x10];
5332  	u8         gid_index[0x10];
5333  };
5334  
5335  struct mlx5_ifc_query_hca_vport_context_out_bits {
5336  	u8         status[0x8];
5337  	u8         reserved_0[0x18];
5338  
5339  	u8         syndrome[0x20];
5340  
5341  	u8         reserved_1[0x40];
5342  
5343  	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5344  };
5345  
5346  struct mlx5_ifc_query_hca_vport_context_in_bits {
5347  	u8         opcode[0x10];
5348  	u8         reserved_0[0x10];
5349  
5350  	u8         reserved_1[0x10];
5351  	u8         op_mod[0x10];
5352  
5353  	u8         other_vport[0x1];
5354  	u8         reserved_2[0xb];
5355  	u8         port_num[0x4];
5356  	u8         vport_number[0x10];
5357  
5358  	u8         reserved_3[0x20];
5359  };
5360  
5361  struct mlx5_ifc_query_hca_cap_out_bits {
5362  	u8         status[0x8];
5363  	u8         reserved_0[0x18];
5364  
5365  	u8         syndrome[0x20];
5366  
5367  	u8         reserved_1[0x40];
5368  
5369  	union mlx5_ifc_hca_cap_union_bits capability;
5370  };
5371  
5372  struct mlx5_ifc_query_hca_cap_in_bits {
5373  	u8         opcode[0x10];
5374  	u8         reserved_0[0x10];
5375  
5376  	u8         reserved_1[0x10];
5377  	u8         op_mod[0x10];
5378  
5379  	u8         reserved_2[0x40];
5380  };
5381  
5382  struct mlx5_ifc_query_flow_table_out_bits {
5383  	u8         status[0x8];
5384  	u8         reserved_at_8[0x18];
5385  
5386  	u8         syndrome[0x20];
5387  
5388  	u8         reserved_at_40[0x80];
5389  
5390  	struct mlx5_ifc_flow_table_context_bits flow_table_context;
5391  };
5392  
5393  struct mlx5_ifc_query_flow_table_in_bits {
5394  	u8         opcode[0x10];
5395  	u8         reserved_0[0x10];
5396  
5397  	u8         reserved_1[0x10];
5398  	u8         op_mod[0x10];
5399  
5400  	u8         other_vport[0x1];
5401  	u8         reserved_2[0xf];
5402  	u8         vport_number[0x10];
5403  
5404  	u8         reserved_3[0x20];
5405  
5406  	u8         table_type[0x8];
5407  	u8         reserved_4[0x18];
5408  
5409  	u8         reserved_5[0x8];
5410  	u8         table_id[0x18];
5411  
5412  	u8         reserved_6[0x140];
5413  };
5414  
5415  struct mlx5_ifc_query_fte_out_bits {
5416  	u8         status[0x8];
5417  	u8         reserved_0[0x18];
5418  
5419  	u8         syndrome[0x20];
5420  
5421  	u8         reserved_1[0x1c0];
5422  
5423  	struct mlx5_ifc_flow_context_bits flow_context;
5424  };
5425  
5426  struct mlx5_ifc_query_fte_in_bits {
5427  	u8         opcode[0x10];
5428  	u8         reserved_0[0x10];
5429  
5430  	u8         reserved_1[0x10];
5431  	u8         op_mod[0x10];
5432  
5433  	u8         other_vport[0x1];
5434  	u8         reserved_2[0xf];
5435  	u8         vport_number[0x10];
5436  
5437  	u8         reserved_3[0x20];
5438  
5439  	u8         table_type[0x8];
5440  	u8         reserved_4[0x18];
5441  
5442  	u8         reserved_5[0x8];
5443  	u8         table_id[0x18];
5444  
5445  	u8         reserved_6[0x40];
5446  
5447  	u8         flow_index[0x20];
5448  
5449  	u8         reserved_7[0xe0];
5450  };
5451  
5452  enum {
5453  	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5454  	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5455  	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5456  };
5457  
5458  struct mlx5_ifc_query_flow_group_out_bits {
5459  	u8         status[0x8];
5460  	u8         reserved_0[0x18];
5461  
5462  	u8         syndrome[0x20];
5463  
5464  	u8         reserved_1[0xa0];
5465  
5466  	u8         start_flow_index[0x20];
5467  
5468  	u8         reserved_2[0x20];
5469  
5470  	u8         end_flow_index[0x20];
5471  
5472  	u8         reserved_3[0xa0];
5473  
5474  	u8         reserved_4[0x18];
5475  	u8         match_criteria_enable[0x8];
5476  
5477  	struct mlx5_ifc_fte_match_param_bits match_criteria;
5478  
5479  	u8         reserved_5[0xe00];
5480  };
5481  
5482  struct mlx5_ifc_query_flow_group_in_bits {
5483  	u8         opcode[0x10];
5484  	u8         reserved_0[0x10];
5485  
5486  	u8         reserved_1[0x10];
5487  	u8         op_mod[0x10];
5488  
5489  	u8         other_vport[0x1];
5490  	u8         reserved_2[0xf];
5491  	u8         vport_number[0x10];
5492  
5493  	u8         reserved_3[0x20];
5494  
5495  	u8         table_type[0x8];
5496  	u8         reserved_4[0x18];
5497  
5498  	u8         reserved_5[0x8];
5499  	u8         table_id[0x18];
5500  
5501  	u8         group_id[0x20];
5502  
5503  	u8         reserved_6[0x120];
5504  };
5505  
5506  struct mlx5_ifc_query_flow_counter_out_bits {
5507  	u8         status[0x8];
5508  	u8         reserved_at_8[0x18];
5509  
5510  	u8         syndrome[0x20];
5511  
5512  	u8         reserved_at_40[0x40];
5513  
5514  	struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5515  };
5516  
5517  struct mlx5_ifc_query_flow_counter_in_bits {
5518  	u8         opcode[0x10];
5519  	u8         reserved_at_10[0x10];
5520  
5521  	u8         reserved_at_20[0x10];
5522  	u8         op_mod[0x10];
5523  
5524  	u8         reserved_at_40[0x80];
5525  
5526  	u8         clear[0x1];
5527  	u8         reserved_at_c1[0xf];
5528  	u8         num_of_counters[0x10];
5529  
5530  	u8         reserved_at_e0[0x10];
5531  	u8         flow_counter_id[0x10];
5532  };
5533  
5534  struct mlx5_ifc_query_esw_vport_context_out_bits {
5535  	u8         status[0x8];
5536  	u8         reserved_0[0x18];
5537  
5538  	u8         syndrome[0x20];
5539  
5540  	u8         reserved_1[0x40];
5541  
5542  	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5543  };
5544  
5545  struct mlx5_ifc_query_esw_vport_context_in_bits {
5546  	u8         opcode[0x10];
5547  	u8         reserved_0[0x10];
5548  
5549  	u8         reserved_1[0x10];
5550  	u8         op_mod[0x10];
5551  
5552  	u8         other_vport[0x1];
5553  	u8         reserved_2[0xf];
5554  	u8         vport_number[0x10];
5555  
5556  	u8         reserved_3[0x20];
5557  };
5558  
5559  struct mlx5_ifc_query_eq_out_bits {
5560  	u8         status[0x8];
5561  	u8         reserved_0[0x18];
5562  
5563  	u8         syndrome[0x20];
5564  
5565  	u8         reserved_1[0x40];
5566  
5567  	struct mlx5_ifc_eqc_bits eq_context_entry;
5568  
5569  	u8         reserved_2[0x40];
5570  
5571  	u8         event_bitmask[0x40];
5572  
5573  	u8         reserved_3[0x580];
5574  
5575  	u8         pas[0][0x40];
5576  };
5577  
5578  struct mlx5_ifc_query_eq_in_bits {
5579  	u8         opcode[0x10];
5580  	u8         reserved_0[0x10];
5581  
5582  	u8         reserved_1[0x10];
5583  	u8         op_mod[0x10];
5584  
5585  	u8         reserved_2[0x18];
5586  	u8         eq_number[0x8];
5587  
5588  	u8         reserved_3[0x20];
5589  };
5590  
5591  struct mlx5_ifc_set_action_in_bits {
5592          u8         action_type[0x4];
5593          u8         field[0xc];
5594          u8         reserved_at_10[0x3];
5595          u8         offset[0x5];
5596          u8         reserved_at_18[0x3];
5597          u8         length[0x5];
5598  
5599          u8         data[0x20];
5600  };
5601  
5602  struct mlx5_ifc_add_action_in_bits {
5603          u8         action_type[0x4];
5604          u8         field[0xc];
5605          u8         reserved_at_10[0x10];
5606  
5607          u8         data[0x20];
5608  };
5609  
5610  struct mlx5_ifc_copy_action_in_bits {
5611          u8         action_type[0x4];
5612          u8         src_field[0xc];
5613          u8         reserved_at_10[0x3];
5614          u8         src_offset[0x5];
5615          u8         reserved_at_18[0x3];
5616          u8         length[0x5];
5617  
5618          u8         reserved_at_20[0x4];
5619          u8         dst_field[0xc];
5620          u8         reserved_at_30[0x3];
5621          u8         dst_offset[0x5];
5622          u8         reserved_at_38[0x8];
5623  };
5624  
5625  union mlx5_ifc_set_add_copy_action_in_auto_bits {
5626          struct mlx5_ifc_set_action_in_bits  set_action_in;
5627          struct mlx5_ifc_add_action_in_bits  add_action_in;
5628          struct mlx5_ifc_copy_action_in_bits copy_action_in;
5629          u8         reserved_at_0[0x40];
5630  };
5631  
5632  enum {
5633          MLX5_ACTION_TYPE_SET   = 0x1,
5634          MLX5_ACTION_TYPE_ADD   = 0x2,
5635          MLX5_ACTION_TYPE_COPY  = 0x3,
5636  };
5637  
5638  enum {
5639          MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5640          MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5641          MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5642          MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5643          MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5644          MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5645          MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5646          MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5647          MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5648          MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5649          MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5650          MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5651          MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5652          MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5653          MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5654          MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5655          MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5656          MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5657          MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5658          MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5659          MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5660          MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5661          MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5662          MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5663          MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
5664          MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
5665          MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5666          MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
5667          MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
5668          MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
5669          MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
5670          MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
5671          MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
5672          MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
5673          MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
5674          MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
5675          MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
5676          MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
5677          MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
5678  };
5679  
5680  struct mlx5_ifc_alloc_modify_header_context_out_bits {
5681          u8         status[0x8];
5682          u8         reserved_at_8[0x18];
5683  
5684          u8         syndrome[0x20];
5685  
5686          u8         modify_header_id[0x20];
5687  
5688          u8         reserved_at_60[0x20];
5689  };
5690  
5691  struct mlx5_ifc_alloc_modify_header_context_in_bits {
5692          u8         opcode[0x10];
5693          u8         reserved_at_10[0x10];
5694  
5695          u8         reserved_at_20[0x10];
5696          u8         op_mod[0x10];
5697  
5698          u8         reserved_at_40[0x20];
5699  
5700          u8         table_type[0x8];
5701          u8         reserved_at_68[0x10];
5702          u8         num_of_actions[0x8];
5703  
5704          union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
5705  };
5706  
5707  struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5708          u8         status[0x8];
5709          u8         reserved_at_8[0x18];
5710  
5711          u8         syndrome[0x20];
5712  
5713          u8         reserved_at_40[0x40];
5714  };
5715  
5716  struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5717          u8         opcode[0x10];
5718          u8         reserved_at_10[0x10];
5719  
5720          u8         reserved_at_20[0x10];
5721          u8         op_mod[0x10];
5722  
5723          u8         modify_header_id[0x20];
5724  
5725          u8         reserved_at_60[0x20];
5726  };
5727  
5728  struct mlx5_ifc_query_modify_header_context_in_bits {
5729          u8         opcode[0x10];
5730          u8         uid[0x10];
5731  
5732          u8         reserved_at_20[0x10];
5733          u8         op_mod[0x10];
5734  
5735          u8         modify_header_id[0x20];
5736  
5737          u8         reserved_at_60[0xa0];
5738  };
5739  
5740  struct mlx5_ifc_query_dct_out_bits {
5741  	u8         status[0x8];
5742  	u8         reserved_0[0x18];
5743  
5744  	u8         syndrome[0x20];
5745  
5746  	u8         reserved_1[0x40];
5747  
5748  	struct mlx5_ifc_dctc_bits dct_context_entry;
5749  
5750  	u8         reserved_2[0x180];
5751  };
5752  
5753  struct mlx5_ifc_query_dct_in_bits {
5754  	u8         opcode[0x10];
5755  	u8         reserved_0[0x10];
5756  
5757  	u8         reserved_1[0x10];
5758  	u8         op_mod[0x10];
5759  
5760  	u8         reserved_2[0x8];
5761  	u8         dctn[0x18];
5762  
5763  	u8         reserved_3[0x20];
5764  };
5765  
5766  struct mlx5_ifc_query_dc_cnak_trace_out_bits {
5767  	u8         status[0x8];
5768  	u8         reserved_0[0x18];
5769  
5770  	u8         syndrome[0x20];
5771  
5772  	u8         enable[0x1];
5773  	u8         reserved_1[0x1f];
5774  
5775  	u8         reserved_2[0x160];
5776  
5777  	struct mlx5_ifc_cmd_pas_bits pas;
5778  };
5779  
5780  struct mlx5_ifc_query_dc_cnak_trace_in_bits {
5781  	u8         opcode[0x10];
5782  	u8         reserved_0[0x10];
5783  
5784  	u8         reserved_1[0x10];
5785  	u8         op_mod[0x10];
5786  
5787  	u8         reserved_2[0x40];
5788  };
5789  
5790  struct mlx5_ifc_packet_reformat_context_in_bits {
5791          u8         reformat_type[0x8];
5792          u8         reserved_at_8[0x4];
5793          u8         reformat_param_0[0x4];
5794          u8         reserved_at_10[0x6];
5795          u8         reformat_data_size[0xa];
5796  
5797          u8         reformat_param_1[0x8];
5798          u8         reserved_at_28[0x8];
5799          u8         reformat_data[2][0x8];
5800  
5801          u8         more_reformat_data[][0x8];
5802  };
5803  
5804  struct mlx5_ifc_query_packet_reformat_context_out_bits {
5805  	u8         status[0x8];
5806  	u8         reserved_at_8[0x18];
5807  
5808  	u8         syndrome[0x20];
5809  
5810  	u8         reserved_at_40[0xa0];
5811  
5812  	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5813  };
5814  
5815  struct mlx5_ifc_query_packet_reformat_context_in_bits {
5816  	u8         opcode[0x10];
5817  	u8         reserved_at_10[0x10];
5818  
5819  	u8         reserved_at_20[0x10];
5820  	u8         op_mod[0x10];
5821  
5822  	u8         packet_reformat_id[0x20];
5823  
5824  	u8         reserved_at_60[0xa0];
5825  };
5826  
5827  struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5828  	u8         status[0x8];
5829  	u8         reserved_at_8[0x18];
5830  
5831  	u8         syndrome[0x20];
5832  
5833  	u8         packet_reformat_id[0x20];
5834  
5835  	u8         reserved_at_60[0x20];
5836  };
5837  
5838  enum mlx5_reformat_ctx_type {
5839  	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5840  	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5841  	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5842  	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5843  	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5844  	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
5845  	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
5846  	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
5847  	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
5848  	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
5849  	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
5850  };
5851  
5852  struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5853  	u8         opcode[0x10];
5854  	u8         reserved_at_10[0x10];
5855  
5856  	u8         reserved_at_20[0x10];
5857  	u8         op_mod[0x10];
5858  
5859  	u8         reserved_at_40[0xa0];
5860  
5861  	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5862  };
5863  
5864  struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5865  	u8         status[0x8];
5866  	u8         reserved_at_8[0x18];
5867  
5868  	u8         syndrome[0x20];
5869  
5870  	u8         reserved_at_40[0x40];
5871  };
5872  
5873  struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5874  	u8         opcode[0x10];
5875  	u8         reserved_at_10[0x10];
5876  
5877  	u8         reserved_20[0x10];
5878  	u8         op_mod[0x10];
5879  
5880  	u8         packet_reformat_id[0x20];
5881  
5882  	u8         reserved_60[0x20];
5883  };
5884  
5885  struct mlx5_ifc_diagnostic_cntr_struct_bits {
5886  	u8         counter_id[0x10];
5887  	u8         sample_id[0x10];
5888  
5889  	u8         time_stamp_31_0[0x20];
5890  
5891  	u8         counter_value_h[0x20];
5892  
5893  	u8         counter_value_l[0x20];
5894  };
5895  
5896  enum {
5897  	MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_ENABLE   = 0x1,
5898  	MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_DISABLE  = 0x0,
5899  };
5900  
5901  struct mlx5_ifc_query_cq_out_bits {
5902  	u8         status[0x8];
5903  	u8         reserved_0[0x18];
5904  
5905  	u8         syndrome[0x20];
5906  
5907  	u8         reserved_1[0x40];
5908  
5909  	struct mlx5_ifc_cqc_bits cq_context;
5910  
5911  	u8         reserved_2[0x600];
5912  
5913  	u8         pas[0][0x40];
5914  };
5915  
5916  struct mlx5_ifc_query_cq_in_bits {
5917  	u8         opcode[0x10];
5918  	u8         reserved_0[0x10];
5919  
5920  	u8         reserved_1[0x10];
5921  	u8         op_mod[0x10];
5922  
5923  	u8         reserved_2[0x8];
5924  	u8         cqn[0x18];
5925  
5926  	u8         reserved_3[0x20];
5927  };
5928  
5929  struct mlx5_ifc_query_cong_status_out_bits {
5930  	u8         status[0x8];
5931  	u8         reserved_0[0x18];
5932  
5933  	u8         syndrome[0x20];
5934  
5935  	u8         reserved_1[0x20];
5936  
5937  	u8         enable[0x1];
5938  	u8         tag_enable[0x1];
5939  	u8         reserved_2[0x1e];
5940  };
5941  
5942  struct mlx5_ifc_query_cong_status_in_bits {
5943  	u8         opcode[0x10];
5944  	u8         reserved_0[0x10];
5945  
5946  	u8         reserved_1[0x10];
5947  	u8         op_mod[0x10];
5948  
5949  	u8         reserved_2[0x18];
5950  	u8         priority[0x4];
5951  	u8         cong_protocol[0x4];
5952  
5953  	u8         reserved_3[0x20];
5954  };
5955  
5956  struct mlx5_ifc_query_cong_statistics_out_bits {
5957  	u8         status[0x8];
5958  	u8         reserved_0[0x18];
5959  
5960  	u8         syndrome[0x20];
5961  
5962  	u8         reserved_1[0x40];
5963  
5964  	u8         rp_cur_flows[0x20];
5965  
5966  	u8         sum_flows[0x20];
5967  
5968  	u8         rp_cnp_ignored_high[0x20];
5969  
5970  	u8         rp_cnp_ignored_low[0x20];
5971  
5972  	u8         rp_cnp_handled_high[0x20];
5973  
5974  	u8         rp_cnp_handled_low[0x20];
5975  
5976  	u8         reserved_2[0x100];
5977  
5978  	u8         time_stamp_high[0x20];
5979  
5980  	u8         time_stamp_low[0x20];
5981  
5982  	u8         accumulators_period[0x20];
5983  
5984  	u8         np_ecn_marked_roce_packets_high[0x20];
5985  
5986  	u8         np_ecn_marked_roce_packets_low[0x20];
5987  
5988  	u8         np_cnp_sent_high[0x20];
5989  
5990  	u8         np_cnp_sent_low[0x20];
5991  
5992  	u8         reserved_3[0x560];
5993  };
5994  
5995  struct mlx5_ifc_query_cong_statistics_in_bits {
5996  	u8         opcode[0x10];
5997  	u8         reserved_0[0x10];
5998  
5999  	u8         reserved_1[0x10];
6000  	u8         op_mod[0x10];
6001  
6002  	u8         clear[0x1];
6003  	u8         reserved_2[0x1f];
6004  
6005  	u8         reserved_3[0x20];
6006  };
6007  
6008  struct mlx5_ifc_query_cong_params_out_bits {
6009  	u8         status[0x8];
6010  	u8         reserved_0[0x18];
6011  
6012  	u8         syndrome[0x20];
6013  
6014  	u8         reserved_1[0x40];
6015  
6016  	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6017  };
6018  
6019  struct mlx5_ifc_query_cong_params_in_bits {
6020  	u8         opcode[0x10];
6021  	u8         reserved_0[0x10];
6022  
6023  	u8         reserved_1[0x10];
6024  	u8         op_mod[0x10];
6025  
6026  	u8         reserved_2[0x1c];
6027  	u8         cong_protocol[0x4];
6028  
6029  	u8         reserved_3[0x20];
6030  };
6031  
6032  struct mlx5_ifc_query_burst_size_out_bits {
6033  	u8         status[0x8];
6034  	u8         reserved_0[0x18];
6035  
6036  	u8         syndrome[0x20];
6037  
6038  	u8         reserved_1[0x20];
6039  
6040  	u8         reserved_2[0x9];
6041  	u8         device_burst_size[0x17];
6042  };
6043  
6044  struct mlx5_ifc_query_burst_size_in_bits {
6045  	u8         opcode[0x10];
6046  	u8         reserved_0[0x10];
6047  
6048  	u8         reserved_1[0x10];
6049  	u8         op_mod[0x10];
6050  
6051  	u8         reserved_2[0x40];
6052  };
6053  
6054  struct mlx5_ifc_query_adapter_out_bits {
6055  	u8         status[0x8];
6056  	u8         reserved_0[0x18];
6057  
6058  	u8         syndrome[0x20];
6059  
6060  	u8         reserved_1[0x40];
6061  
6062  	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6063  };
6064  
6065  struct mlx5_ifc_query_adapter_in_bits {
6066  	u8         opcode[0x10];
6067  	u8         reserved_0[0x10];
6068  
6069  	u8         reserved_1[0x10];
6070  	u8         op_mod[0x10];
6071  
6072  	u8         reserved_2[0x40];
6073  };
6074  
6075  struct mlx5_ifc_qp_2rst_out_bits {
6076  	u8         status[0x8];
6077  	u8         reserved_0[0x18];
6078  
6079  	u8         syndrome[0x20];
6080  
6081  	u8         reserved_1[0x40];
6082  };
6083  
6084  struct mlx5_ifc_qp_2rst_in_bits {
6085  	u8         opcode[0x10];
6086  	u8         uid[0x10];
6087  
6088  	u8         reserved_1[0x10];
6089  	u8         op_mod[0x10];
6090  
6091  	u8         reserved_2[0x8];
6092  	u8         qpn[0x18];
6093  
6094  	u8         reserved_3[0x20];
6095  };
6096  
6097  struct mlx5_ifc_qp_2err_out_bits {
6098  	u8         status[0x8];
6099  	u8         reserved_0[0x18];
6100  
6101  	u8         syndrome[0x20];
6102  
6103  	u8         reserved_1[0x40];
6104  };
6105  
6106  struct mlx5_ifc_qp_2err_in_bits {
6107  	u8         opcode[0x10];
6108  	u8         uid[0x10];
6109  
6110  	u8         reserved_1[0x10];
6111  	u8         op_mod[0x10];
6112  
6113  	u8         reserved_2[0x8];
6114  	u8         qpn[0x18];
6115  
6116  	u8         reserved_3[0x20];
6117  };
6118  
6119  struct mlx5_ifc_para_vport_element_bits {
6120  	u8         reserved_at_0[0xc];
6121  	u8         traffic_class[0x4];
6122  	u8         qos_para_vport_number[0x10];
6123  };
6124  
6125  struct mlx5_ifc_page_fault_resume_out_bits {
6126  	u8         status[0x8];
6127  	u8         reserved_0[0x18];
6128  
6129  	u8         syndrome[0x20];
6130  
6131  	u8         reserved_1[0x40];
6132  };
6133  
6134  struct mlx5_ifc_page_fault_resume_in_bits {
6135  	u8         opcode[0x10];
6136  	u8         reserved_0[0x10];
6137  
6138  	u8         reserved_1[0x10];
6139  	u8         op_mod[0x10];
6140  
6141  	u8         error[0x1];
6142  	u8         reserved_2[0x4];
6143  	u8         rdma[0x1];
6144  	u8         read_write[0x1];
6145  	u8         req_res[0x1];
6146  	u8         qpn[0x18];
6147  
6148  	u8         reserved_3[0x20];
6149  };
6150  
6151  struct mlx5_ifc_nop_out_bits {
6152  	u8         status[0x8];
6153  	u8         reserved_0[0x18];
6154  
6155  	u8         syndrome[0x20];
6156  
6157  	u8         reserved_1[0x40];
6158  };
6159  
6160  struct mlx5_ifc_nop_in_bits {
6161  	u8         opcode[0x10];
6162  	u8         reserved_0[0x10];
6163  
6164  	u8         reserved_1[0x10];
6165  	u8         op_mod[0x10];
6166  
6167  	u8         reserved_2[0x40];
6168  };
6169  
6170  struct mlx5_ifc_modify_vport_state_out_bits {
6171  	u8         status[0x8];
6172  	u8         reserved_0[0x18];
6173  
6174  	u8         syndrome[0x20];
6175  
6176  	u8         reserved_1[0x40];
6177  };
6178  
6179  enum {
6180  	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
6181  	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
6182  	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
6183  };
6184  
6185  enum {
6186  	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
6187  	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
6188  	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
6189  };
6190  
6191  struct mlx5_ifc_modify_vport_state_in_bits {
6192  	u8         opcode[0x10];
6193  	u8         reserved_0[0x10];
6194  
6195  	u8         reserved_1[0x10];
6196  	u8         op_mod[0x10];
6197  
6198  	u8         other_vport[0x1];
6199  	u8         reserved_2[0xf];
6200  	u8         vport_number[0x10];
6201  
6202  	u8         reserved_3[0x18];
6203  	u8         admin_state[0x4];
6204  	u8         reserved_4[0x4];
6205  };
6206  
6207  struct mlx5_ifc_modify_tis_out_bits {
6208  	u8         status[0x8];
6209  	u8         reserved_0[0x18];
6210  
6211  	u8         syndrome[0x20];
6212  
6213  	u8         reserved_1[0x40];
6214  };
6215  
6216  struct mlx5_ifc_modify_tis_bitmask_bits {
6217  	u8         reserved_at_0[0x20];
6218  
6219  	u8         reserved_at_20[0x1d];
6220  	u8         lag_tx_port_affinity[0x1];
6221  	u8         strict_lag_tx_port_affinity[0x1];
6222  	u8         prio[0x1];
6223  };
6224  
6225  struct mlx5_ifc_modify_tis_in_bits {
6226  	u8         opcode[0x10];
6227  	u8         uid[0x10];
6228  
6229  	u8         reserved_1[0x10];
6230  	u8         op_mod[0x10];
6231  
6232  	u8         reserved_2[0x8];
6233  	u8         tisn[0x18];
6234  
6235  	u8         reserved_3[0x20];
6236  
6237  	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6238  
6239  	u8         reserved_4[0x40];
6240  
6241  	struct mlx5_ifc_tisc_bits ctx;
6242  };
6243  
6244  struct mlx5_ifc_modify_tir_out_bits {
6245  	u8         status[0x8];
6246  	u8         reserved_0[0x18];
6247  
6248  	u8         syndrome[0x20];
6249  
6250  	u8         reserved_1[0x40];
6251  };
6252  
6253  enum
6254  {
6255  	MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
6256  	MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER =		0x1 << 1
6257  };
6258  
6259  struct mlx5_ifc_modify_tir_in_bits {
6260  	u8         opcode[0x10];
6261  	u8         uid[0x10];
6262  
6263  	u8         reserved_1[0x10];
6264  	u8         op_mod[0x10];
6265  
6266  	u8         reserved_2[0x8];
6267  	u8         tirn[0x18];
6268  
6269  	u8         reserved_3[0x20];
6270  
6271  	u8         modify_bitmask[0x40];
6272  
6273  	u8         reserved_4[0x40];
6274  
6275  	struct mlx5_ifc_tirc_bits tir_context;
6276  };
6277  
6278  struct mlx5_ifc_modify_sq_out_bits {
6279  	u8         status[0x8];
6280  	u8         reserved_0[0x18];
6281  
6282  	u8         syndrome[0x20];
6283  
6284  	u8         reserved_1[0x40];
6285  };
6286  
6287  struct mlx5_ifc_modify_sq_in_bits {
6288  	u8         opcode[0x10];
6289  	u8         uid[0x10];
6290  
6291  	u8         reserved_1[0x10];
6292  	u8         op_mod[0x10];
6293  
6294  	u8         sq_state[0x4];
6295  	u8         reserved_2[0x4];
6296  	u8         sqn[0x18];
6297  
6298  	u8         reserved_3[0x20];
6299  
6300  	u8         modify_bitmask[0x40];
6301  
6302  	u8         reserved_4[0x40];
6303  
6304  	struct mlx5_ifc_sqc_bits ctx;
6305  };
6306  
6307  struct mlx5_ifc_modify_scheduling_element_out_bits {
6308  	u8         status[0x8];
6309  	u8         reserved_at_8[0x18];
6310  
6311  	u8         syndrome[0x20];
6312  
6313  	u8         reserved_at_40[0x1c0];
6314  };
6315  
6316  enum {
6317  	MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6318  };
6319  
6320  enum {
6321  	MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE        = 0x1,
6322  	MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW  = 0x2,
6323  };
6324  
6325  struct mlx5_ifc_modify_scheduling_element_in_bits {
6326  	u8         opcode[0x10];
6327  	u8         reserved_at_10[0x10];
6328  
6329  	u8         reserved_at_20[0x10];
6330  	u8         op_mod[0x10];
6331  
6332  	u8         scheduling_hierarchy[0x8];
6333  	u8         reserved_at_48[0x18];
6334  
6335  	u8         scheduling_element_id[0x20];
6336  
6337  	u8         reserved_at_80[0x20];
6338  
6339  	u8         modify_bitmask[0x20];
6340  
6341  	u8         reserved_at_c0[0x40];
6342  
6343  	struct mlx5_ifc_scheduling_context_bits scheduling_context;
6344  
6345  	u8         reserved_at_300[0x100];
6346  };
6347  
6348  struct mlx5_ifc_modify_rqt_out_bits {
6349  	u8         status[0x8];
6350  	u8         reserved_0[0x18];
6351  
6352  	u8         syndrome[0x20];
6353  
6354  	u8         reserved_1[0x40];
6355  };
6356  
6357  struct mlx5_ifc_rqt_bitmask_bits {
6358  	u8         reserved_at_0[0x20];
6359  
6360  	u8         reserved_at_20[0x1f];
6361  	u8         rqn_list[0x1];
6362  };
6363  
6364  
6365  struct mlx5_ifc_modify_rqt_in_bits {
6366  	u8         opcode[0x10];
6367  	u8         uid[0x10];
6368  
6369  	u8         reserved_1[0x10];
6370  	u8         op_mod[0x10];
6371  
6372  	u8         reserved_2[0x8];
6373  	u8         rqtn[0x18];
6374  
6375  	u8         reserved_3[0x20];
6376  
6377  	struct mlx5_ifc_rqt_bitmask_bits bitmask;
6378  
6379  	u8         reserved_4[0x40];
6380  
6381  	struct mlx5_ifc_rqtc_bits ctx;
6382  };
6383  
6384  struct mlx5_ifc_modify_rq_out_bits {
6385  	u8         status[0x8];
6386  	u8         reserved_0[0x18];
6387  
6388  	u8         syndrome[0x20];
6389  
6390  	u8         reserved_1[0x40];
6391  };
6392  
6393  enum {
6394  	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6395  	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
6396  };
6397  
6398  struct mlx5_ifc_modify_rq_in_bits {
6399  	u8         opcode[0x10];
6400  	u8         uid[0x10];
6401  
6402  	u8         reserved_1[0x10];
6403  	u8         op_mod[0x10];
6404  
6405  	u8         rq_state[0x4];
6406  	u8         reserved_2[0x4];
6407  	u8         rqn[0x18];
6408  
6409  	u8         reserved_3[0x20];
6410  
6411  	u8         modify_bitmask[0x40];
6412  
6413  	u8         reserved_4[0x40];
6414  
6415  	struct mlx5_ifc_rqc_bits ctx;
6416  };
6417  
6418  struct mlx5_ifc_modify_rmp_out_bits {
6419  	u8         status[0x8];
6420  	u8         reserved_0[0x18];
6421  
6422  	u8         syndrome[0x20];
6423  
6424  	u8         reserved_1[0x40];
6425  };
6426  
6427  struct mlx5_ifc_rmp_bitmask_bits {
6428  	u8	   reserved[0x20];
6429  
6430  	u8         reserved1[0x1f];
6431  	u8         lwm[0x1];
6432  };
6433  
6434  struct mlx5_ifc_modify_rmp_in_bits {
6435  	u8         opcode[0x10];
6436  	u8         uid[0x10];
6437  
6438  	u8         reserved_1[0x10];
6439  	u8         op_mod[0x10];
6440  
6441  	u8         rmp_state[0x4];
6442  	u8         reserved_2[0x4];
6443  	u8         rmpn[0x18];
6444  
6445  	u8         reserved_3[0x20];
6446  
6447  	struct mlx5_ifc_rmp_bitmask_bits bitmask;
6448  
6449  	u8         reserved_4[0x40];
6450  
6451  	struct mlx5_ifc_rmpc_bits ctx;
6452  };
6453  
6454  struct mlx5_ifc_modify_nic_vport_context_out_bits {
6455  	u8         status[0x8];
6456  	u8         reserved_0[0x18];
6457  
6458  	u8         syndrome[0x20];
6459  
6460  	u8         reserved_1[0x40];
6461  };
6462  
6463  struct mlx5_ifc_modify_nic_vport_field_select_bits {
6464  	u8         reserved_0[0x14];
6465  	u8         disable_uc_local_lb[0x1];
6466  	u8         disable_mc_local_lb[0x1];
6467  	u8         node_guid[0x1];
6468  	u8         port_guid[0x1];
6469  	u8         min_wqe_inline_mode[0x1];
6470  	u8         mtu[0x1];
6471  	u8         change_event[0x1];
6472  	u8         promisc[0x1];
6473  	u8         permanent_address[0x1];
6474  	u8         addresses_list[0x1];
6475  	u8         roce_en[0x1];
6476  	u8         reserved_1[0x1];
6477  };
6478  
6479  struct mlx5_ifc_modify_nic_vport_context_in_bits {
6480  	u8         opcode[0x10];
6481  	u8         reserved_0[0x10];
6482  
6483  	u8         reserved_1[0x10];
6484  	u8         op_mod[0x10];
6485  
6486  	u8         other_vport[0x1];
6487  	u8         reserved_2[0xf];
6488  	u8         vport_number[0x10];
6489  
6490  	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6491  
6492  	u8         reserved_3[0x780];
6493  
6494  	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6495  };
6496  
6497  struct mlx5_ifc_modify_hca_vport_context_out_bits {
6498  	u8         status[0x8];
6499  	u8         reserved_0[0x18];
6500  
6501  	u8         syndrome[0x20];
6502  
6503  	u8         reserved_1[0x40];
6504  };
6505  
6506  struct mlx5_ifc_grh_bits {
6507  	u8	ip_version[4];
6508  	u8	traffic_class[8];
6509  	u8	flow_label[20];
6510  	u8	payload_length[16];
6511  	u8	next_header[8];
6512  	u8	hop_limit[8];
6513  	u8	sgid[128];
6514  	u8	dgid[128];
6515  };
6516  
6517  struct mlx5_ifc_bth_bits {
6518  	u8	opcode[8];
6519  	u8	se[1];
6520  	u8	migreq[1];
6521  	u8	pad_count[2];
6522  	u8	tver[4];
6523  	u8	p_key[16];
6524  	u8	reserved8[8];
6525  	u8	dest_qp[24];
6526  	u8	ack_req[1];
6527  	u8	reserved7[7];
6528  	u8	psn[24];
6529  };
6530  
6531  struct mlx5_ifc_aeth_bits {
6532  	u8	syndrome[8];
6533  	u8	msn[24];
6534  };
6535  
6536  struct mlx5_ifc_dceth_bits {
6537  	u8	reserved0[8];
6538  	u8	session_id[24];
6539  	u8	reserved1[8];
6540  	u8	dci_dct[24];
6541  };
6542  
6543  struct mlx5_ifc_modify_hca_vport_context_in_bits {
6544  	u8         opcode[0x10];
6545  	u8         reserved_0[0x10];
6546  
6547  	u8         reserved_1[0x10];
6548  	u8         op_mod[0x10];
6549  
6550  	u8         other_vport[0x1];
6551  	u8         reserved_2[0xb];
6552  	u8         port_num[0x4];
6553  	u8         vport_number[0x10];
6554  
6555  	u8         reserved_3[0x20];
6556  
6557  	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6558  };
6559  
6560  enum {
6561          MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
6562          MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
6563  };
6564  
6565  struct mlx5_ifc_modify_flow_table_out_bits {
6566  	u8         status[0x8];
6567  	u8         reserved_at_8[0x18];
6568  
6569  	u8         syndrome[0x20];
6570  
6571  	u8         reserved_at_40[0x40];
6572  };
6573  
6574  enum {
6575  	MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
6576  	MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
6577  };
6578  
6579  struct mlx5_ifc_modify_flow_table_in_bits {
6580  	u8         opcode[0x10];
6581  	u8         reserved_at_10[0x10];
6582  
6583  	u8         reserved_at_20[0x10];
6584  	u8         op_mod[0x10];
6585  
6586  	u8         other_vport[0x1];
6587  	u8         reserved_at_41[0xf];
6588  	u8         vport_number[0x10];
6589  
6590  	u8         reserved_at_60[0x10];
6591  	u8         modify_field_select[0x10];
6592  
6593  	u8         table_type[0x8];
6594  	u8         reserved_at_88[0x18];
6595  
6596  	u8         reserved_at_a0[0x8];
6597  	u8         table_id[0x18];
6598  
6599  	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6600  };
6601  
6602  struct mlx5_ifc_modify_esw_vport_context_out_bits {
6603  	u8         status[0x8];
6604  	u8         reserved_0[0x18];
6605  
6606  	u8         syndrome[0x20];
6607  
6608  	u8         reserved_1[0x40];
6609  };
6610  
6611  struct mlx5_ifc_esw_vport_context_fields_select_bits {
6612  	u8         reserved[0x1c];
6613  	u8         vport_cvlan_insert[0x1];
6614  	u8         vport_svlan_insert[0x1];
6615  	u8         vport_cvlan_strip[0x1];
6616  	u8         vport_svlan_strip[0x1];
6617  };
6618  
6619  struct mlx5_ifc_modify_esw_vport_context_in_bits {
6620  	u8         opcode[0x10];
6621  	u8         reserved_0[0x10];
6622  
6623  	u8         reserved_1[0x10];
6624  	u8         op_mod[0x10];
6625  
6626  	u8         other_vport[0x1];
6627  	u8         reserved_2[0xf];
6628  	u8         vport_number[0x10];
6629  
6630  	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6631  
6632  	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6633  };
6634  
6635  struct mlx5_ifc_modify_cq_out_bits {
6636  	u8         status[0x8];
6637  	u8         reserved_0[0x18];
6638  
6639  	u8         syndrome[0x20];
6640  
6641  	u8         reserved_1[0x40];
6642  };
6643  
6644  enum {
6645  	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6646  	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6647  };
6648  
6649  struct mlx5_ifc_modify_cq_in_bits {
6650  	u8         opcode[0x10];
6651  	u8         uid[0x10];
6652  
6653  	u8         reserved_1[0x10];
6654  	u8         op_mod[0x10];
6655  
6656  	u8         reserved_2[0x8];
6657  	u8         cqn[0x18];
6658  
6659  	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6660  
6661  	struct mlx5_ifc_cqc_bits cq_context;
6662  
6663  	u8         reserved_at_280[0x60];
6664  
6665  	u8         cq_umem_valid[0x1];
6666  	u8         reserved_at_2e1[0x1f];
6667  
6668  	u8         reserved_at_300[0x580];
6669  
6670  	u8         pas[0][0x40];
6671  };
6672  
6673  struct mlx5_ifc_modify_cong_status_out_bits {
6674  	u8         status[0x8];
6675  	u8         reserved_0[0x18];
6676  
6677  	u8         syndrome[0x20];
6678  
6679  	u8         reserved_1[0x40];
6680  };
6681  
6682  struct mlx5_ifc_modify_cong_status_in_bits {
6683  	u8         opcode[0x10];
6684  	u8         reserved_0[0x10];
6685  
6686  	u8         reserved_1[0x10];
6687  	u8         op_mod[0x10];
6688  
6689  	u8         reserved_2[0x18];
6690  	u8         priority[0x4];
6691  	u8         cong_protocol[0x4];
6692  
6693  	u8         enable[0x1];
6694  	u8         tag_enable[0x1];
6695  	u8         reserved_3[0x1e];
6696  };
6697  
6698  struct mlx5_ifc_modify_cong_params_out_bits {
6699  	u8         status[0x8];
6700  	u8         reserved_0[0x18];
6701  
6702  	u8         syndrome[0x20];
6703  
6704  	u8         reserved_1[0x40];
6705  };
6706  
6707  struct mlx5_ifc_modify_cong_params_in_bits {
6708  	u8         opcode[0x10];
6709  	u8         reserved_0[0x10];
6710  
6711  	u8         reserved_1[0x10];
6712  	u8         op_mod[0x10];
6713  
6714  	u8         reserved_2[0x1c];
6715  	u8         cong_protocol[0x4];
6716  
6717  	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6718  
6719  	u8         reserved_3[0x80];
6720  
6721  	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6722  };
6723  
6724  struct mlx5_ifc_manage_pages_out_bits {
6725  	u8         status[0x8];
6726  	u8         reserved_0[0x18];
6727  
6728  	u8         syndrome[0x20];
6729  
6730  	u8         output_num_entries[0x20];
6731  
6732  	u8         reserved_1[0x20];
6733  
6734  	u8         pas[0][0x40];
6735  };
6736  
6737  enum {
6738  	MLX5_PAGES_CANT_GIVE                            = 0x0,
6739  	MLX5_PAGES_GIVE                                 = 0x1,
6740  	MLX5_PAGES_TAKE                                 = 0x2,
6741  };
6742  
6743  struct mlx5_ifc_manage_pages_in_bits {
6744  	u8         opcode[0x10];
6745  	u8         reserved_0[0x10];
6746  
6747  	u8         reserved_1[0x10];
6748  	u8         op_mod[0x10];
6749  
6750  	u8         reserved_2[0x10];
6751  	u8         function_id[0x10];
6752  
6753  	u8         input_num_entries[0x20];
6754  
6755  	u8         pas[0][0x40];
6756  };
6757  
6758  struct mlx5_ifc_mad_ifc_out_bits {
6759  	u8         status[0x8];
6760  	u8         reserved_0[0x18];
6761  
6762  	u8         syndrome[0x20];
6763  
6764  	u8         reserved_1[0x40];
6765  
6766  	u8         response_mad_packet[256][0x8];
6767  };
6768  
6769  struct mlx5_ifc_mad_ifc_in_bits {
6770  	u8         opcode[0x10];
6771  	u8         reserved_0[0x10];
6772  
6773  	u8         reserved_1[0x10];
6774  	u8         op_mod[0x10];
6775  
6776  	u8         remote_lid[0x10];
6777  	u8         reserved_2[0x8];
6778  	u8         port[0x8];
6779  
6780  	u8         reserved_3[0x20];
6781  
6782  	u8         mad[256][0x8];
6783  };
6784  
6785  struct mlx5_ifc_init_hca_out_bits {
6786  	u8         status[0x8];
6787  	u8         reserved_0[0x18];
6788  
6789  	u8         syndrome[0x20];
6790  
6791  	u8         reserved_1[0x40];
6792  };
6793  
6794  enum {
6795  	MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
6796  	MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
6797  };
6798  
6799  struct mlx5_ifc_init_hca_in_bits {
6800  	u8         opcode[0x10];
6801  	u8         reserved_0[0x10];
6802  
6803  	u8         reserved_1[0x10];
6804  	u8         op_mod[0x10];
6805  
6806  	u8         reserved_2[0x40];
6807  };
6808  
6809  struct mlx5_ifc_init2rtr_qp_out_bits {
6810  	u8         status[0x8];
6811  	u8         reserved_0[0x18];
6812  
6813  	u8         syndrome[0x20];
6814  
6815  	u8         reserved_1[0x40];
6816  };
6817  
6818  struct mlx5_ifc_init2rtr_qp_in_bits {
6819  	u8         opcode[0x10];
6820  	u8         uid[0x10];
6821  
6822  	u8         reserved_1[0x10];
6823  	u8         op_mod[0x10];
6824  
6825  	u8         reserved_2[0x8];
6826  	u8         qpn[0x18];
6827  
6828  	u8         reserved_3[0x20];
6829  
6830  	u8         opt_param_mask[0x20];
6831  
6832  	u8         reserved_4[0x20];
6833  
6834  	struct mlx5_ifc_qpc_bits qpc;
6835  
6836  	u8         reserved_5[0x80];
6837  };
6838  
6839  struct mlx5_ifc_init2init_qp_out_bits {
6840  	u8         status[0x8];
6841  	u8         reserved_0[0x18];
6842  
6843  	u8         syndrome[0x20];
6844  
6845  	u8         reserved_1[0x40];
6846  };
6847  
6848  struct mlx5_ifc_init2init_qp_in_bits {
6849  	u8         opcode[0x10];
6850  	u8         uid[0x10];
6851  
6852  	u8         reserved_1[0x10];
6853  	u8         op_mod[0x10];
6854  
6855  	u8         reserved_2[0x8];
6856  	u8         qpn[0x18];
6857  
6858  	u8         reserved_3[0x20];
6859  
6860  	u8         opt_param_mask[0x20];
6861  
6862  	u8         reserved_4[0x20];
6863  
6864  	struct mlx5_ifc_qpc_bits qpc;
6865  
6866  	u8         reserved_5[0x80];
6867  };
6868  
6869  struct mlx5_ifc_get_dropped_packet_log_out_bits {
6870  	u8         status[0x8];
6871  	u8         reserved_0[0x18];
6872  
6873  	u8         syndrome[0x20];
6874  
6875  	u8         reserved_1[0x40];
6876  
6877  	u8         packet_headers_log[128][0x8];
6878  
6879  	u8         packet_syndrome[64][0x8];
6880  };
6881  
6882  struct mlx5_ifc_get_dropped_packet_log_in_bits {
6883  	u8         opcode[0x10];
6884  	u8         reserved_0[0x10];
6885  
6886  	u8         reserved_1[0x10];
6887  	u8         op_mod[0x10];
6888  
6889  	u8         reserved_2[0x40];
6890  };
6891  
6892  struct mlx5_ifc_encryption_key_obj_bits {
6893  	u8         modify_field_select[0x40];
6894  
6895  	u8         reserved_at_40[0x14];
6896  	u8         key_size[0x4];
6897  	u8         reserved_at_58[0x4];
6898  	u8         key_type[0x4];
6899  
6900  	u8         reserved_at_60[0x8];
6901  	u8         pd[0x18];
6902  
6903  	u8         reserved_at_80[0x180];
6904  
6905  	u8         key[8][0x20];
6906  
6907  	u8         reserved_at_300[0x500];
6908  };
6909  
6910  struct mlx5_ifc_gen_eqe_in_bits {
6911  	u8         opcode[0x10];
6912  	u8         reserved_0[0x10];
6913  
6914  	u8         reserved_1[0x10];
6915  	u8         op_mod[0x10];
6916  
6917  	u8         reserved_2[0x18];
6918  	u8         eq_number[0x8];
6919  
6920  	u8         reserved_3[0x20];
6921  
6922  	u8         eqe[64][0x8];
6923  };
6924  
6925  struct mlx5_ifc_gen_eq_out_bits {
6926  	u8         status[0x8];
6927  	u8         reserved_0[0x18];
6928  
6929  	u8         syndrome[0x20];
6930  
6931  	u8         reserved_1[0x40];
6932  };
6933  
6934  struct mlx5_ifc_enable_hca_out_bits {
6935  	u8         status[0x8];
6936  	u8         reserved_0[0x18];
6937  
6938  	u8         syndrome[0x20];
6939  
6940  	u8         reserved_1[0x20];
6941  };
6942  
6943  struct mlx5_ifc_enable_hca_in_bits {
6944  	u8         opcode[0x10];
6945  	u8         reserved_0[0x10];
6946  
6947  	u8         reserved_1[0x10];
6948  	u8         op_mod[0x10];
6949  
6950  	u8         reserved_2[0x10];
6951  	u8         function_id[0x10];
6952  
6953  	u8         reserved_3[0x20];
6954  };
6955  
6956  struct mlx5_ifc_drain_dct_out_bits {
6957  	u8         status[0x8];
6958  	u8         reserved_0[0x18];
6959  
6960  	u8         syndrome[0x20];
6961  
6962  	u8         reserved_1[0x40];
6963  };
6964  
6965  struct mlx5_ifc_drain_dct_in_bits {
6966  	u8         opcode[0x10];
6967  	u8         uid[0x10];
6968  
6969  	u8         reserved_1[0x10];
6970  	u8         op_mod[0x10];
6971  
6972  	u8         reserved_2[0x8];
6973  	u8         dctn[0x18];
6974  
6975  	u8         reserved_3[0x20];
6976  };
6977  
6978  struct mlx5_ifc_disable_hca_out_bits {
6979  	u8         status[0x8];
6980  	u8         reserved_0[0x18];
6981  
6982  	u8         syndrome[0x20];
6983  
6984  	u8         reserved_1[0x20];
6985  };
6986  
6987  struct mlx5_ifc_disable_hca_in_bits {
6988  	u8         opcode[0x10];
6989  	u8         reserved_0[0x10];
6990  
6991  	u8         reserved_1[0x10];
6992  	u8         op_mod[0x10];
6993  
6994  	u8         reserved_2[0x10];
6995  	u8         function_id[0x10];
6996  
6997  	u8         reserved_3[0x20];
6998  };
6999  
7000  struct mlx5_ifc_detach_from_mcg_out_bits {
7001  	u8         status[0x8];
7002  	u8         reserved_0[0x18];
7003  
7004  	u8         syndrome[0x20];
7005  
7006  	u8         reserved_1[0x40];
7007  };
7008  
7009  struct mlx5_ifc_detach_from_mcg_in_bits {
7010  	u8         opcode[0x10];
7011  	u8         uid[0x10];
7012  
7013  	u8         reserved_1[0x10];
7014  	u8         op_mod[0x10];
7015  
7016  	u8         reserved_2[0x8];
7017  	u8         qpn[0x18];
7018  
7019  	u8         reserved_3[0x20];
7020  
7021  	u8         multicast_gid[16][0x8];
7022  };
7023  
7024  struct mlx5_ifc_destroy_xrc_srq_out_bits {
7025  	u8         status[0x8];
7026  	u8         reserved_0[0x18];
7027  
7028  	u8         syndrome[0x20];
7029  
7030  	u8         reserved_1[0x40];
7031  };
7032  
7033  struct mlx5_ifc_destroy_xrc_srq_in_bits {
7034  	u8         opcode[0x10];
7035  	u8         uid[0x10];
7036  
7037  	u8         reserved_1[0x10];
7038  	u8         op_mod[0x10];
7039  
7040  	u8         reserved_2[0x8];
7041  	u8         xrc_srqn[0x18];
7042  
7043  	u8         reserved_3[0x20];
7044  };
7045  
7046  struct mlx5_ifc_destroy_tis_out_bits {
7047  	u8         status[0x8];
7048  	u8         reserved_0[0x18];
7049  
7050  	u8         syndrome[0x20];
7051  
7052  	u8         reserved_1[0x40];
7053  };
7054  
7055  struct mlx5_ifc_destroy_tis_in_bits {
7056  	u8         opcode[0x10];
7057  	u8         uid[0x10];
7058  
7059  	u8         reserved_1[0x10];
7060  	u8         op_mod[0x10];
7061  
7062  	u8         reserved_2[0x8];
7063  	u8         tisn[0x18];
7064  
7065  	u8         reserved_3[0x20];
7066  };
7067  
7068  struct mlx5_ifc_destroy_tir_out_bits {
7069  	u8         status[0x8];
7070  	u8         reserved_0[0x18];
7071  
7072  	u8         syndrome[0x20];
7073  
7074  	u8         reserved_1[0x40];
7075  };
7076  
7077  struct mlx5_ifc_destroy_tir_in_bits {
7078  	u8         opcode[0x10];
7079  	u8         uid[0x10];
7080  
7081  	u8         reserved_1[0x10];
7082  	u8         op_mod[0x10];
7083  
7084  	u8         reserved_2[0x8];
7085  	u8         tirn[0x18];
7086  
7087  	u8         reserved_3[0x20];
7088  };
7089  
7090  struct mlx5_ifc_destroy_srq_out_bits {
7091  	u8         status[0x8];
7092  	u8         reserved_0[0x18];
7093  
7094  	u8         syndrome[0x20];
7095  
7096  	u8         reserved_1[0x40];
7097  };
7098  
7099  struct mlx5_ifc_destroy_srq_in_bits {
7100  	u8         opcode[0x10];
7101  	u8         uid[0x10];
7102  
7103  	u8         reserved_1[0x10];
7104  	u8         op_mod[0x10];
7105  
7106  	u8         reserved_2[0x8];
7107  	u8         srqn[0x18];
7108  
7109  	u8         reserved_3[0x20];
7110  };
7111  
7112  struct mlx5_ifc_destroy_sq_out_bits {
7113  	u8         status[0x8];
7114  	u8         reserved_0[0x18];
7115  
7116  	u8         syndrome[0x20];
7117  
7118  	u8         reserved_1[0x40];
7119  };
7120  
7121  struct mlx5_ifc_destroy_sq_in_bits {
7122  	u8         opcode[0x10];
7123  	u8         uid[0x10];
7124  
7125  	u8         reserved_1[0x10];
7126  	u8         op_mod[0x10];
7127  
7128  	u8         reserved_2[0x8];
7129  	u8         sqn[0x18];
7130  
7131  	u8         reserved_3[0x20];
7132  };
7133  
7134  struct mlx5_ifc_destroy_scheduling_element_out_bits {
7135  	u8         status[0x8];
7136  	u8         reserved_at_8[0x18];
7137  
7138  	u8         syndrome[0x20];
7139  
7140  	u8         reserved_at_40[0x1c0];
7141  };
7142  
7143  enum {
7144  	MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
7145  };
7146  
7147  struct mlx5_ifc_destroy_scheduling_element_in_bits {
7148  	u8         opcode[0x10];
7149  	u8         reserved_at_10[0x10];
7150  
7151  	u8         reserved_at_20[0x10];
7152  	u8         op_mod[0x10];
7153  
7154  	u8         scheduling_hierarchy[0x8];
7155  	u8         reserved_at_48[0x18];
7156  
7157  	u8         scheduling_element_id[0x20];
7158  
7159  	u8         reserved_at_80[0x180];
7160  };
7161  
7162  struct mlx5_ifc_destroy_rqt_out_bits {
7163  	u8         status[0x8];
7164  	u8         reserved_0[0x18];
7165  
7166  	u8         syndrome[0x20];
7167  
7168  	u8         reserved_1[0x40];
7169  };
7170  
7171  struct mlx5_ifc_destroy_rqt_in_bits {
7172  	u8         opcode[0x10];
7173  	u8         uid[0x10];
7174  
7175  	u8         reserved_1[0x10];
7176  	u8         op_mod[0x10];
7177  
7178  	u8         reserved_2[0x8];
7179  	u8         rqtn[0x18];
7180  
7181  	u8         reserved_3[0x20];
7182  };
7183  
7184  struct mlx5_ifc_destroy_rq_out_bits {
7185  	u8         status[0x8];
7186  	u8         reserved_0[0x18];
7187  
7188  	u8         syndrome[0x20];
7189  
7190  	u8         reserved_1[0x40];
7191  };
7192  
7193  struct mlx5_ifc_destroy_rq_in_bits {
7194  	u8         opcode[0x10];
7195  	u8         uid[0x10];
7196  
7197  	u8         reserved_1[0x10];
7198  	u8         op_mod[0x10];
7199  
7200  	u8         reserved_2[0x8];
7201  	u8         rqn[0x18];
7202  
7203  	u8         reserved_3[0x20];
7204  };
7205  
7206  struct mlx5_ifc_destroy_rmp_out_bits {
7207  	u8         status[0x8];
7208  	u8         reserved_0[0x18];
7209  
7210  	u8         syndrome[0x20];
7211  
7212  	u8         reserved_1[0x40];
7213  };
7214  
7215  struct mlx5_ifc_destroy_rmp_in_bits {
7216  	u8         opcode[0x10];
7217  	u8         reserved_0[0x10];
7218  
7219  	u8         reserved_1[0x10];
7220  	u8         op_mod[0x10];
7221  
7222  	u8         reserved_2[0x8];
7223  	u8         rmpn[0x18];
7224  
7225  	u8         reserved_3[0x20];
7226  };
7227  
7228  struct mlx5_ifc_destroy_qp_out_bits {
7229  	u8         status[0x8];
7230  	u8         reserved_0[0x18];
7231  
7232  	u8         syndrome[0x20];
7233  
7234  	u8         reserved_1[0x40];
7235  };
7236  
7237  struct mlx5_ifc_destroy_qp_in_bits {
7238  	u8         opcode[0x10];
7239  	u8         uid[0x10];
7240  
7241  	u8         reserved_1[0x10];
7242  	u8         op_mod[0x10];
7243  
7244  	u8         reserved_2[0x8];
7245  	u8         qpn[0x18];
7246  
7247  	u8         reserved_3[0x20];
7248  };
7249  
7250  struct mlx5_ifc_destroy_qos_para_vport_out_bits {
7251  	u8         status[0x8];
7252  	u8         reserved_at_8[0x18];
7253  
7254  	u8         syndrome[0x20];
7255  
7256  	u8         reserved_at_40[0x1c0];
7257  };
7258  
7259  struct mlx5_ifc_destroy_qos_para_vport_in_bits {
7260  	u8         opcode[0x10];
7261  	u8         reserved_at_10[0x10];
7262  
7263  	u8         reserved_at_20[0x10];
7264  	u8         op_mod[0x10];
7265  
7266  	u8         reserved_at_40[0x20];
7267  
7268  	u8         reserved_at_60[0x10];
7269  	u8         qos_para_vport_number[0x10];
7270  
7271  	u8         reserved_at_80[0x180];
7272  };
7273  
7274  struct mlx5_ifc_destroy_psv_out_bits {
7275  	u8         status[0x8];
7276  	u8         reserved_0[0x18];
7277  
7278  	u8         syndrome[0x20];
7279  
7280  	u8         reserved_1[0x40];
7281  };
7282  
7283  struct mlx5_ifc_destroy_psv_in_bits {
7284  	u8         opcode[0x10];
7285  	u8         reserved_0[0x10];
7286  
7287  	u8         reserved_1[0x10];
7288  	u8         op_mod[0x10];
7289  
7290  	u8         reserved_2[0x8];
7291  	u8         psvn[0x18];
7292  
7293  	u8         reserved_3[0x20];
7294  };
7295  
7296  struct mlx5_ifc_destroy_mkey_out_bits {
7297  	u8         status[0x8];
7298  	u8         reserved_0[0x18];
7299  
7300  	u8         syndrome[0x20];
7301  
7302  	u8         reserved_1[0x40];
7303  };
7304  
7305  struct mlx5_ifc_destroy_mkey_in_bits {
7306  	u8         opcode[0x10];
7307  	u8         reserved_0[0x10];
7308  
7309  	u8         reserved_1[0x10];
7310  	u8         op_mod[0x10];
7311  
7312  	u8         reserved_2[0x8];
7313  	u8         mkey_index[0x18];
7314  
7315  	u8         reserved_3[0x20];
7316  };
7317  
7318  struct mlx5_ifc_destroy_flow_table_out_bits {
7319  	u8         status[0x8];
7320  	u8         reserved_0[0x18];
7321  
7322  	u8         syndrome[0x20];
7323  
7324  	u8         reserved_1[0x40];
7325  };
7326  
7327  struct mlx5_ifc_destroy_flow_table_in_bits {
7328  	u8         opcode[0x10];
7329  	u8         reserved_0[0x10];
7330  
7331  	u8         reserved_1[0x10];
7332  	u8         op_mod[0x10];
7333  
7334  	u8         other_vport[0x1];
7335  	u8         reserved_2[0xf];
7336  	u8         vport_number[0x10];
7337  
7338  	u8         reserved_3[0x20];
7339  
7340  	u8         table_type[0x8];
7341  	u8         reserved_4[0x18];
7342  
7343  	u8         reserved_5[0x8];
7344  	u8         table_id[0x18];
7345  
7346  	u8         reserved_6[0x140];
7347  };
7348  
7349  struct mlx5_ifc_destroy_flow_group_out_bits {
7350  	u8         status[0x8];
7351  	u8         reserved_0[0x18];
7352  
7353  	u8         syndrome[0x20];
7354  
7355  	u8         reserved_1[0x40];
7356  };
7357  
7358  struct mlx5_ifc_destroy_flow_group_in_bits {
7359  	u8         opcode[0x10];
7360  	u8         reserved_0[0x10];
7361  
7362  	u8         reserved_1[0x10];
7363  	u8         op_mod[0x10];
7364  
7365  	u8         other_vport[0x1];
7366  	u8         reserved_2[0xf];
7367  	u8         vport_number[0x10];
7368  
7369  	u8         reserved_3[0x20];
7370  
7371  	u8         table_type[0x8];
7372  	u8         reserved_4[0x18];
7373  
7374  	u8         reserved_5[0x8];
7375  	u8         table_id[0x18];
7376  
7377  	u8         group_id[0x20];
7378  
7379  	u8         reserved_6[0x120];
7380  };
7381  
7382  struct mlx5_ifc_destroy_encryption_key_out_bits {
7383  	u8         status[0x8];
7384  	u8         reserved_at_8[0x18];
7385  
7386  	u8         syndrome[0x20];
7387  
7388  	u8         reserved_at_40[0x40];
7389  };
7390  
7391  struct mlx5_ifc_destroy_encryption_key_in_bits {
7392  	u8         opcode[0x10];
7393  	u8         reserved_at_10[0x10];
7394  
7395  	u8         reserved_at_20[0x10];
7396  	u8         obj_type[0x10];
7397  
7398  	u8         obj_id[0x20];
7399  
7400  	u8         reserved_at_60[0x20];
7401  };
7402  
7403  struct mlx5_ifc_destroy_eq_out_bits {
7404  	u8         status[0x8];
7405  	u8         reserved_0[0x18];
7406  
7407  	u8         syndrome[0x20];
7408  
7409  	u8         reserved_1[0x40];
7410  };
7411  
7412  struct mlx5_ifc_destroy_eq_in_bits {
7413  	u8         opcode[0x10];
7414  	u8         reserved_0[0x10];
7415  
7416  	u8         reserved_1[0x10];
7417  	u8         op_mod[0x10];
7418  
7419  	u8         reserved_2[0x18];
7420  	u8         eq_number[0x8];
7421  
7422  	u8         reserved_3[0x20];
7423  };
7424  
7425  struct mlx5_ifc_destroy_dct_out_bits {
7426  	u8         status[0x8];
7427  	u8         reserved_0[0x18];
7428  
7429  	u8         syndrome[0x20];
7430  
7431  	u8         reserved_1[0x40];
7432  };
7433  
7434  struct mlx5_ifc_destroy_dct_in_bits {
7435  	u8         opcode[0x10];
7436  	u8         uid[0x10];
7437  
7438  	u8         reserved_1[0x10];
7439  	u8         op_mod[0x10];
7440  
7441  	u8         reserved_2[0x8];
7442  	u8         dctn[0x18];
7443  
7444  	u8         reserved_3[0x20];
7445  };
7446  
7447  struct mlx5_ifc_destroy_cq_out_bits {
7448  	u8         status[0x8];
7449  	u8         reserved_0[0x18];
7450  
7451  	u8         syndrome[0x20];
7452  
7453  	u8         reserved_1[0x40];
7454  };
7455  
7456  struct mlx5_ifc_destroy_cq_in_bits {
7457  	u8         opcode[0x10];
7458  	u8         uid[0x10];
7459  
7460  	u8         reserved_1[0x10];
7461  	u8         op_mod[0x10];
7462  
7463  	u8         reserved_2[0x8];
7464  	u8         cqn[0x18];
7465  
7466  	u8         reserved_3[0x20];
7467  };
7468  
7469  struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7470  	u8         status[0x8];
7471  	u8         reserved_0[0x18];
7472  
7473  	u8         syndrome[0x20];
7474  
7475  	u8         reserved_1[0x40];
7476  };
7477  
7478  struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7479  	u8         opcode[0x10];
7480  	u8         reserved_0[0x10];
7481  
7482  	u8         reserved_1[0x10];
7483  	u8         op_mod[0x10];
7484  
7485  	u8         reserved_2[0x20];
7486  
7487  	u8         reserved_3[0x10];
7488  	u8         vxlan_udp_port[0x10];
7489  };
7490  
7491  struct mlx5_ifc_delete_l2_table_entry_out_bits {
7492  	u8         status[0x8];
7493  	u8         reserved_0[0x18];
7494  
7495  	u8         syndrome[0x20];
7496  
7497  	u8         reserved_1[0x40];
7498  };
7499  
7500  struct mlx5_ifc_delete_l2_table_entry_in_bits {
7501  	u8         opcode[0x10];
7502  	u8         reserved_0[0x10];
7503  
7504  	u8         reserved_1[0x10];
7505  	u8         op_mod[0x10];
7506  
7507  	u8         reserved_2[0x60];
7508  
7509  	u8         reserved_3[0x8];
7510  	u8         table_index[0x18];
7511  
7512  	u8         reserved_4[0x140];
7513  };
7514  
7515  struct mlx5_ifc_delete_fte_out_bits {
7516  	u8         status[0x8];
7517  	u8         reserved_0[0x18];
7518  
7519  	u8         syndrome[0x20];
7520  
7521  	u8         reserved_1[0x40];
7522  };
7523  
7524  struct mlx5_ifc_delete_fte_in_bits {
7525  	u8         opcode[0x10];
7526  	u8         reserved_0[0x10];
7527  
7528  	u8         reserved_1[0x10];
7529  	u8         op_mod[0x10];
7530  
7531  	u8         other_vport[0x1];
7532  	u8         reserved_2[0xf];
7533  	u8         vport_number[0x10];
7534  
7535  	u8         reserved_3[0x20];
7536  
7537  	u8         table_type[0x8];
7538  	u8         reserved_4[0x18];
7539  
7540  	u8         reserved_5[0x8];
7541  	u8         table_id[0x18];
7542  
7543  	u8         reserved_6[0x40];
7544  
7545  	u8         flow_index[0x20];
7546  
7547  	u8         reserved_7[0xe0];
7548  };
7549  
7550  struct mlx5_ifc_dealloc_xrcd_out_bits {
7551  	u8         status[0x8];
7552  	u8         reserved_0[0x18];
7553  
7554  	u8         syndrome[0x20];
7555  
7556  	u8         reserved_1[0x40];
7557  };
7558  
7559  struct mlx5_ifc_dealloc_xrcd_in_bits {
7560  	u8         opcode[0x10];
7561  	u8         uid[0x10];
7562  
7563  	u8         reserved_1[0x10];
7564  	u8         op_mod[0x10];
7565  
7566  	u8         reserved_2[0x8];
7567  	u8         xrcd[0x18];
7568  
7569  	u8         reserved_3[0x20];
7570  };
7571  
7572  struct mlx5_ifc_dealloc_uar_out_bits {
7573  	u8         status[0x8];
7574  	u8         reserved_0[0x18];
7575  
7576  	u8         syndrome[0x20];
7577  
7578  	u8         reserved_1[0x40];
7579  };
7580  
7581  struct mlx5_ifc_dealloc_uar_in_bits {
7582  	u8         opcode[0x10];
7583  	u8         reserved_0[0x10];
7584  
7585  	u8         reserved_1[0x10];
7586  	u8         op_mod[0x10];
7587  
7588  	u8         reserved_2[0x8];
7589  	u8         uar[0x18];
7590  
7591  	u8         reserved_3[0x20];
7592  };
7593  
7594  struct mlx5_ifc_dealloc_transport_domain_out_bits {
7595  	u8         status[0x8];
7596  	u8         reserved_0[0x18];
7597  
7598  	u8         syndrome[0x20];
7599  
7600  	u8         reserved_1[0x40];
7601  };
7602  
7603  struct mlx5_ifc_dealloc_transport_domain_in_bits {
7604  	u8         opcode[0x10];
7605  	u8         uid[0x10];
7606  
7607  	u8         reserved_1[0x10];
7608  	u8         op_mod[0x10];
7609  
7610  	u8         reserved_2[0x8];
7611  	u8         transport_domain[0x18];
7612  
7613  	u8         reserved_3[0x20];
7614  };
7615  
7616  struct mlx5_ifc_dealloc_q_counter_out_bits {
7617  	u8         status[0x8];
7618  	u8         reserved_0[0x18];
7619  
7620  	u8         syndrome[0x20];
7621  
7622  	u8         reserved_1[0x40];
7623  };
7624  
7625  struct mlx5_ifc_counter_id_bits {
7626  	u8         reserved[0x10];
7627  	u8         counter_id[0x10];
7628  };
7629  
7630  struct mlx5_ifc_diagnostic_params_context_bits {
7631  	u8         num_of_counters[0x10];
7632  	u8         reserved_2[0x8];
7633  	u8         log_num_of_samples[0x8];
7634  
7635  	u8         single[0x1];
7636  	u8         repetitive[0x1];
7637  	u8         sync[0x1];
7638  	u8         clear[0x1];
7639  	u8         on_demand[0x1];
7640  	u8         enable[0x1];
7641  	u8         reserved_3[0x12];
7642  	u8         log_sample_period[0x8];
7643  
7644  	u8         reserved_4[0x80];
7645  
7646  	struct mlx5_ifc_counter_id_bits counter_id[0];
7647  };
7648  
7649  struct mlx5_ifc_query_diagnostic_params_in_bits {
7650  	u8         opcode[0x10];
7651  	u8         reserved_at_10[0x10];
7652  
7653  	u8         reserved_at_20[0x10];
7654  	u8         op_mod[0x10];
7655  
7656  	u8         reserved_at_40[0x40];
7657  };
7658  
7659  struct mlx5_ifc_query_diagnostic_params_out_bits {
7660  	u8         status[0x8];
7661  	u8         reserved_at_8[0x18];
7662  
7663  	u8         syndrome[0x20];
7664  
7665  	struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
7666  };
7667  
7668  struct mlx5_ifc_set_diagnostic_params_in_bits {
7669  	u8         opcode[0x10];
7670  	u8         reserved_0[0x10];
7671  
7672  	u8         reserved_1[0x10];
7673  	u8         op_mod[0x10];
7674  
7675  	struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
7676  };
7677  
7678  struct mlx5_ifc_set_diagnostic_params_out_bits {
7679  	u8         status[0x8];
7680  	u8         reserved_0[0x18];
7681  
7682  	u8         syndrome[0x20];
7683  
7684  	u8         reserved_1[0x40];
7685  };
7686  
7687  struct mlx5_ifc_query_diagnostic_counters_in_bits {
7688  	u8         opcode[0x10];
7689  	u8         reserved_0[0x10];
7690  
7691  	u8         reserved_1[0x10];
7692  	u8         op_mod[0x10];
7693  
7694  	u8         num_of_samples[0x10];
7695  	u8         sample_index[0x10];
7696  
7697  	u8         reserved_2[0x20];
7698  };
7699  
7700  struct mlx5_ifc_diagnostic_counter_bits {
7701  	u8         counter_id[0x10];
7702  	u8         sample_id[0x10];
7703  
7704  	u8         time_stamp_31_0[0x20];
7705  
7706  	u8         counter_value_h[0x20];
7707  
7708  	u8         counter_value_l[0x20];
7709  };
7710  
7711  struct mlx5_ifc_query_diagnostic_counters_out_bits {
7712  	u8         status[0x8];
7713  	u8         reserved_0[0x18];
7714  
7715  	u8         syndrome[0x20];
7716  
7717  	u8         reserved_1[0x40];
7718  
7719  	struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
7720  };
7721  
7722  struct mlx5_ifc_dealloc_q_counter_in_bits {
7723  	u8         opcode[0x10];
7724  	u8         reserved_0[0x10];
7725  
7726  	u8         reserved_1[0x10];
7727  	u8         op_mod[0x10];
7728  
7729  	u8         reserved_2[0x18];
7730  	u8         counter_set_id[0x8];
7731  
7732  	u8         reserved_3[0x20];
7733  };
7734  
7735  struct mlx5_ifc_dealloc_pd_out_bits {
7736  	u8         status[0x8];
7737  	u8         reserved_0[0x18];
7738  
7739  	u8         syndrome[0x20];
7740  
7741  	u8         reserved_1[0x40];
7742  };
7743  
7744  struct mlx5_ifc_dealloc_pd_in_bits {
7745  	u8         opcode[0x10];
7746  	u8         uid[0x10];
7747  
7748  	u8         reserved_1[0x10];
7749  	u8         op_mod[0x10];
7750  
7751  	u8         reserved_2[0x8];
7752  	u8         pd[0x18];
7753  
7754  	u8         reserved_3[0x20];
7755  };
7756  
7757  struct mlx5_ifc_dealloc_flow_counter_out_bits {
7758  	u8         status[0x8];
7759  	u8         reserved_0[0x18];
7760  
7761  	u8         syndrome[0x20];
7762  
7763  	u8         reserved_1[0x40];
7764  };
7765  
7766  struct mlx5_ifc_dealloc_flow_counter_in_bits {
7767  	u8         opcode[0x10];
7768  	u8         reserved_0[0x10];
7769  
7770  	u8         reserved_1[0x10];
7771  	u8         op_mod[0x10];
7772  
7773  	u8         flow_counter_id[0x20];
7774  
7775  	u8         reserved_3[0x20];
7776  };
7777  
7778  struct mlx5_ifc_create_xrq_out_bits {
7779  	u8         status[0x8];
7780  	u8         reserved_at_8[0x18];
7781  
7782  	u8         syndrome[0x20];
7783  
7784  	u8         reserved_at_40[0x8];
7785  	u8         xrqn[0x18];
7786  
7787  	u8         reserved_at_60[0x20];
7788  };
7789  
7790  struct mlx5_ifc_create_xrq_in_bits {
7791  	u8         opcode[0x10];
7792  	u8         uid[0x10];
7793  
7794  	u8         reserved_at_20[0x10];
7795  	u8         op_mod[0x10];
7796  
7797  	u8         reserved_at_40[0x40];
7798  
7799  	struct mlx5_ifc_xrqc_bits xrq_context;
7800  };
7801  
7802  struct mlx5_ifc_deactivate_tracer_out_bits {
7803  	u8         status[0x8];
7804  	u8         reserved_0[0x18];
7805  
7806  	u8         syndrome[0x20];
7807  
7808  	u8         reserved_1[0x40];
7809  };
7810  
7811  struct mlx5_ifc_deactivate_tracer_in_bits {
7812  	u8         opcode[0x10];
7813  	u8         reserved_0[0x10];
7814  
7815  	u8         reserved_1[0x10];
7816  	u8         op_mod[0x10];
7817  
7818  	u8         mkey[0x20];
7819  
7820  	u8         reserved_2[0x20];
7821  };
7822  
7823  struct mlx5_ifc_create_xrc_srq_out_bits {
7824  	u8         status[0x8];
7825  	u8         reserved_0[0x18];
7826  
7827  	u8         syndrome[0x20];
7828  
7829  	u8         reserved_1[0x8];
7830  	u8         xrc_srqn[0x18];
7831  
7832  	u8         reserved_2[0x20];
7833  };
7834  
7835  struct mlx5_ifc_create_xrc_srq_in_bits {
7836  	u8         opcode[0x10];
7837  	u8         uid[0x10];
7838  
7839  	u8         reserved_1[0x10];
7840  	u8         op_mod[0x10];
7841  
7842  	u8         reserved_2[0x40];
7843  
7844  	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7845  
7846  	u8         reserved_at_280[0x60];
7847  
7848  	u8         xrc_srq_umem_valid[0x1];
7849  	u8         reserved_at_2e1[0x1f];
7850  
7851  	u8         reserved_at_300[0x580];
7852  
7853  	u8         pas[0][0x40];
7854  };
7855  
7856  struct mlx5_ifc_create_tis_out_bits {
7857  	u8         status[0x8];
7858  	u8         reserved_0[0x18];
7859  
7860  	u8         syndrome[0x20];
7861  
7862  	u8         reserved_1[0x8];
7863  	u8         tisn[0x18];
7864  
7865  	u8         reserved_2[0x20];
7866  };
7867  
7868  struct mlx5_ifc_create_tis_in_bits {
7869  	u8         opcode[0x10];
7870  	u8         uid[0x10];
7871  
7872  	u8         reserved_1[0x10];
7873  	u8         op_mod[0x10];
7874  
7875  	u8         reserved_2[0xc0];
7876  
7877  	struct mlx5_ifc_tisc_bits ctx;
7878  };
7879  
7880  struct mlx5_ifc_create_tir_out_bits {
7881  	u8         status[0x8];
7882  	u8         reserved_0[0x18];
7883  
7884  	u8         syndrome[0x20];
7885  
7886  	u8         reserved_1[0x8];
7887  	u8         tirn[0x18];
7888  
7889  	u8         reserved_2[0x20];
7890  };
7891  
7892  struct mlx5_ifc_create_tir_in_bits {
7893  	u8         opcode[0x10];
7894  	u8         uid[0x10];
7895  
7896  	u8         reserved_1[0x10];
7897  	u8         op_mod[0x10];
7898  
7899  	u8         reserved_2[0xc0];
7900  
7901  	struct mlx5_ifc_tirc_bits tir_context;
7902  };
7903  
7904  struct mlx5_ifc_create_srq_out_bits {
7905  	u8         status[0x8];
7906  	u8         reserved_0[0x18];
7907  
7908  	u8         syndrome[0x20];
7909  
7910  	u8         reserved_1[0x8];
7911  	u8         srqn[0x18];
7912  
7913  	u8         reserved_2[0x20];
7914  };
7915  
7916  struct mlx5_ifc_create_srq_in_bits {
7917  	u8         opcode[0x10];
7918  	u8         uid[0x10];
7919  
7920  	u8         reserved_1[0x10];
7921  	u8         op_mod[0x10];
7922  
7923  	u8         reserved_2[0x40];
7924  
7925  	struct mlx5_ifc_srqc_bits srq_context_entry;
7926  
7927  	u8         reserved_3[0x600];
7928  
7929  	u8         pas[0][0x40];
7930  };
7931  
7932  struct mlx5_ifc_create_sq_out_bits {
7933  	u8         status[0x8];
7934  	u8         reserved_0[0x18];
7935  
7936  	u8         syndrome[0x20];
7937  
7938  	u8         reserved_1[0x8];
7939  	u8         sqn[0x18];
7940  
7941  	u8         reserved_2[0x20];
7942  };
7943  
7944  struct mlx5_ifc_create_sq_in_bits {
7945  	u8         opcode[0x10];
7946  	u8         uid[0x10];
7947  
7948  	u8         reserved_1[0x10];
7949  	u8         op_mod[0x10];
7950  
7951  	u8         reserved_2[0xc0];
7952  
7953  	struct mlx5_ifc_sqc_bits ctx;
7954  };
7955  
7956  struct mlx5_ifc_create_scheduling_element_out_bits {
7957  	u8         status[0x8];
7958  	u8         reserved_at_8[0x18];
7959  
7960  	u8         syndrome[0x20];
7961  
7962  	u8         reserved_at_40[0x40];
7963  
7964  	u8         scheduling_element_id[0x20];
7965  
7966  	u8         reserved_at_a0[0x160];
7967  };
7968  
7969  enum {
7970  	MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
7971  };
7972  
7973  struct mlx5_ifc_create_scheduling_element_in_bits {
7974  	u8         opcode[0x10];
7975  	u8         reserved_at_10[0x10];
7976  
7977  	u8         reserved_at_20[0x10];
7978  	u8         op_mod[0x10];
7979  
7980  	u8         scheduling_hierarchy[0x8];
7981  	u8         reserved_at_48[0x18];
7982  
7983  	u8         reserved_at_60[0xa0];
7984  
7985  	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7986  
7987  	u8         reserved_at_300[0x100];
7988  };
7989  
7990  struct mlx5_ifc_create_rqt_out_bits {
7991  	u8         status[0x8];
7992  	u8         reserved_0[0x18];
7993  
7994  	u8         syndrome[0x20];
7995  
7996  	u8         reserved_1[0x8];
7997  	u8         rqtn[0x18];
7998  
7999  	u8         reserved_2[0x20];
8000  };
8001  
8002  struct mlx5_ifc_create_rqt_in_bits {
8003  	u8         opcode[0x10];
8004  	u8         uid[0x10];
8005  
8006  	u8         reserved_1[0x10];
8007  	u8         op_mod[0x10];
8008  
8009  	u8         reserved_2[0xc0];
8010  
8011  	struct mlx5_ifc_rqtc_bits rqt_context;
8012  };
8013  
8014  struct mlx5_ifc_create_rq_out_bits {
8015  	u8         status[0x8];
8016  	u8         reserved_0[0x18];
8017  
8018  	u8         syndrome[0x20];
8019  
8020  	u8         reserved_1[0x8];
8021  	u8         rqn[0x18];
8022  
8023  	u8         reserved_2[0x20];
8024  };
8025  
8026  struct mlx5_ifc_create_rq_in_bits {
8027  	u8         opcode[0x10];
8028  	u8         uid[0x10];
8029  
8030  	u8         reserved_1[0x10];
8031  	u8         op_mod[0x10];
8032  
8033  	u8         reserved_2[0xc0];
8034  
8035  	struct mlx5_ifc_rqc_bits ctx;
8036  };
8037  
8038  struct mlx5_ifc_create_rmp_out_bits {
8039  	u8         status[0x8];
8040  	u8         reserved_0[0x18];
8041  
8042  	u8         syndrome[0x20];
8043  
8044  	u8         reserved_1[0x8];
8045  	u8         rmpn[0x18];
8046  
8047  	u8         reserved_2[0x20];
8048  };
8049  
8050  struct mlx5_ifc_create_rmp_in_bits {
8051  	u8         opcode[0x10];
8052  	u8         uid[0x10];
8053  
8054  	u8         reserved_1[0x10];
8055  	u8         op_mod[0x10];
8056  
8057  	u8         reserved_2[0xc0];
8058  
8059  	struct mlx5_ifc_rmpc_bits ctx;
8060  };
8061  
8062  struct mlx5_ifc_create_qp_out_bits {
8063  	u8         status[0x8];
8064  	u8         reserved_0[0x18];
8065  
8066  	u8         syndrome[0x20];
8067  
8068  	u8         reserved_1[0x8];
8069  	u8         qpn[0x18];
8070  
8071  	u8         reserved_2[0x20];
8072  };
8073  
8074  struct mlx5_ifc_create_qp_in_bits {
8075  	u8         opcode[0x10];
8076  	u8         uid[0x10];
8077  
8078  	u8         reserved_1[0x10];
8079  	u8         op_mod[0x10];
8080  
8081  	u8         reserved_2[0x8];
8082  	u8         input_qpn[0x18];
8083  
8084  	u8         reserved_3[0x20];
8085  
8086  	u8         opt_param_mask[0x20];
8087  
8088  	u8         reserved_4[0x20];
8089  
8090  	struct mlx5_ifc_qpc_bits qpc;
8091  
8092  	u8         reserved_at_800[0x60];
8093  
8094  	u8         wq_umem_valid[0x1];
8095  	u8         reserved_at_861[0x1f];
8096  
8097  	u8         pas[0][0x40];
8098  };
8099  
8100  struct mlx5_ifc_create_qos_para_vport_out_bits {
8101  	u8         status[0x8];
8102  	u8         reserved_at_8[0x18];
8103  
8104  	u8         syndrome[0x20];
8105  
8106  	u8         reserved_at_40[0x20];
8107  
8108  	u8         reserved_at_60[0x10];
8109  	u8         qos_para_vport_number[0x10];
8110  
8111  	u8         reserved_at_80[0x180];
8112  };
8113  
8114  struct mlx5_ifc_create_qos_para_vport_in_bits {
8115  	u8         opcode[0x10];
8116  	u8         reserved_at_10[0x10];
8117  
8118  	u8         reserved_at_20[0x10];
8119  	u8         op_mod[0x10];
8120  
8121  	u8         reserved_at_40[0x1c0];
8122  };
8123  
8124  struct mlx5_ifc_create_psv_out_bits {
8125  	u8         status[0x8];
8126  	u8         reserved_0[0x18];
8127  
8128  	u8         syndrome[0x20];
8129  
8130  	u8         reserved_1[0x40];
8131  
8132  	u8         reserved_2[0x8];
8133  	u8         psv0_index[0x18];
8134  
8135  	u8         reserved_3[0x8];
8136  	u8         psv1_index[0x18];
8137  
8138  	u8         reserved_4[0x8];
8139  	u8         psv2_index[0x18];
8140  
8141  	u8         reserved_5[0x8];
8142  	u8         psv3_index[0x18];
8143  };
8144  
8145  struct mlx5_ifc_create_psv_in_bits {
8146  	u8         opcode[0x10];
8147  	u8         reserved_0[0x10];
8148  
8149  	u8         reserved_1[0x10];
8150  	u8         op_mod[0x10];
8151  
8152  	u8         num_psv[0x4];
8153  	u8         reserved_2[0x4];
8154  	u8         pd[0x18];
8155  
8156  	u8         reserved_3[0x20];
8157  };
8158  
8159  struct mlx5_ifc_create_mkey_out_bits {
8160  	u8         status[0x8];
8161  	u8         reserved_0[0x18];
8162  
8163  	u8         syndrome[0x20];
8164  
8165  	u8         reserved_1[0x8];
8166  	u8         mkey_index[0x18];
8167  
8168  	u8         reserved_2[0x20];
8169  };
8170  
8171  struct mlx5_ifc_create_mkey_in_bits {
8172  	u8         opcode[0x10];
8173  	u8         reserved_0[0x10];
8174  
8175  	u8         reserved_1[0x10];
8176  	u8         op_mod[0x10];
8177  
8178  	u8         reserved_2[0x20];
8179  
8180  	u8         pg_access[0x1];
8181  	u8         mkey_umem_valid[0x1];
8182  	u8         reserved_at_62[0x1e];
8183  
8184  	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8185  
8186  	u8         reserved_4[0x80];
8187  
8188  	u8         translations_octword_actual_size[0x20];
8189  
8190  	u8         reserved_5[0x560];
8191  
8192  	u8         klm_pas_mtt[0][0x20];
8193  };
8194  
8195  struct mlx5_ifc_create_flow_table_out_bits {
8196  	u8         status[0x8];
8197  	u8         reserved_0[0x18];
8198  
8199  	u8         syndrome[0x20];
8200  
8201  	u8         reserved_1[0x8];
8202  	u8         table_id[0x18];
8203  
8204  	u8         reserved_2[0x20];
8205  };
8206  
8207  struct mlx5_ifc_create_flow_table_in_bits {
8208          u8         opcode[0x10];
8209          u8         uid[0x10];
8210  
8211          u8         reserved_at_20[0x10];
8212          u8         op_mod[0x10];
8213  
8214          u8         other_vport[0x1];
8215          u8         reserved_at_41[0xf];
8216          u8         vport_number[0x10];
8217  
8218          u8         reserved_at_60[0x20];
8219  
8220          u8         table_type[0x8];
8221          u8         reserved_at_88[0x18];
8222  
8223          u8         reserved_at_a0[0x20];
8224  
8225          struct mlx5_ifc_flow_table_context_bits flow_table_context;
8226  };
8227  
8228  struct mlx5_ifc_create_flow_group_out_bits {
8229  	u8         status[0x8];
8230  	u8         reserved_0[0x18];
8231  
8232  	u8         syndrome[0x20];
8233  
8234  	u8         reserved_1[0x8];
8235  	u8         group_id[0x18];
8236  
8237  	u8         reserved_2[0x20];
8238  };
8239  
8240  enum {
8241  	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8242  	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8243  	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8244  	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8245  };
8246  
8247  struct mlx5_ifc_create_flow_group_in_bits {
8248          u8         opcode[0x10];
8249          u8         reserved_at_10[0x10];
8250  
8251          u8         reserved_at_20[0x10];
8252          u8         op_mod[0x10];
8253  
8254          u8         other_vport[0x1];
8255          u8         reserved_at_41[0xf];
8256          u8         vport_number[0x10];
8257  
8258          u8         reserved_at_60[0x20];
8259  
8260          u8         table_type[0x8];
8261          u8         reserved_at_88[0x4];
8262          u8         group_type[0x4];
8263          u8         reserved_at_90[0x10];
8264  
8265          u8         reserved_at_a0[0x8];
8266          u8         table_id[0x18];
8267  
8268          u8         source_eswitch_owner_vhca_id_valid[0x1];
8269  
8270          u8         reserved_at_c1[0x1f];
8271  
8272          u8         start_flow_index[0x20];
8273  
8274          u8         reserved_at_100[0x20];
8275  
8276          u8         end_flow_index[0x20];
8277  
8278          u8         reserved_at_140[0x10];
8279          u8         match_definer_id[0x10];
8280  
8281          u8         reserved_at_160[0x80];
8282  
8283          u8         reserved_at_1e0[0x18];
8284          u8         match_criteria_enable[0x8];
8285  
8286          struct mlx5_ifc_fte_match_param_bits match_criteria;
8287  
8288          u8         reserved_at_1200[0xe00];
8289  };
8290  
8291  struct mlx5_ifc_create_encryption_key_out_bits {
8292  	u8         status[0x8];
8293  	u8         reserved_at_8[0x18];
8294  
8295  	u8         syndrome[0x20];
8296  
8297  	u8         obj_id[0x20];
8298  
8299  	u8         reserved_at_60[0x20];
8300  };
8301  
8302  struct mlx5_ifc_create_encryption_key_in_bits {
8303  	u8         opcode[0x10];
8304  	u8         reserved_at_10[0x10];
8305  
8306  	u8         reserved_at_20[0x10];
8307  	u8         obj_type[0x10];
8308  
8309  	u8         reserved_at_40[0x40];
8310  
8311  	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
8312  };
8313  
8314  struct mlx5_ifc_create_eq_out_bits {
8315  	u8         status[0x8];
8316  	u8         reserved_0[0x18];
8317  
8318  	u8         syndrome[0x20];
8319  
8320  	u8         reserved_1[0x18];
8321  	u8         eq_number[0x8];
8322  
8323  	u8         reserved_2[0x20];
8324  };
8325  
8326  struct mlx5_ifc_create_eq_in_bits {
8327  	u8         opcode[0x10];
8328  	u8         reserved_0[0x10];
8329  
8330  	u8         reserved_1[0x10];
8331  	u8         op_mod[0x10];
8332  
8333  	u8         reserved_2[0x40];
8334  
8335  	struct mlx5_ifc_eqc_bits eq_context_entry;
8336  
8337  	u8         reserved_3[0x40];
8338  
8339  	u8         event_bitmask[0x40];
8340  
8341  	u8         reserved_4[0x580];
8342  
8343  	u8         pas[0][0x40];
8344  };
8345  
8346  struct mlx5_ifc_create_dct_out_bits {
8347  	u8         status[0x8];
8348  	u8         reserved_0[0x18];
8349  
8350  	u8         syndrome[0x20];
8351  
8352  	u8         reserved_1[0x8];
8353  	u8         dctn[0x18];
8354  
8355  	u8         reserved_2[0x20];
8356  };
8357  
8358  struct mlx5_ifc_create_dct_in_bits {
8359  	u8         opcode[0x10];
8360  	u8         uid[0x10];
8361  
8362  	u8         reserved_1[0x10];
8363  	u8         op_mod[0x10];
8364  
8365  	u8         reserved_2[0x40];
8366  
8367  	struct mlx5_ifc_dctc_bits dct_context_entry;
8368  
8369  	u8         reserved_3[0x180];
8370  };
8371  
8372  struct mlx5_ifc_create_cq_out_bits {
8373  	u8         status[0x8];
8374  	u8         reserved_0[0x18];
8375  
8376  	u8         syndrome[0x20];
8377  
8378  	u8         reserved_1[0x8];
8379  	u8         cqn[0x18];
8380  
8381  	u8         reserved_2[0x20];
8382  };
8383  
8384  struct mlx5_ifc_create_cq_in_bits {
8385  	u8         opcode[0x10];
8386  	u8         uid[0x10];
8387  
8388  	u8         reserved_1[0x10];
8389  	u8         op_mod[0x10];
8390  
8391  	u8         reserved_2[0x40];
8392  
8393  	struct mlx5_ifc_cqc_bits cq_context;
8394  
8395  	u8         reserved_at_280[0x60];
8396  
8397  	u8         cq_umem_valid[0x1];
8398  	u8         reserved_at_2e1[0x59f];
8399  
8400  	u8         pas[0][0x40];
8401  };
8402  
8403  struct mlx5_ifc_config_int_moderation_out_bits {
8404  	u8         status[0x8];
8405  	u8         reserved_0[0x18];
8406  
8407  	u8         syndrome[0x20];
8408  
8409  	u8         reserved_1[0x4];
8410  	u8         min_delay[0xc];
8411  	u8         int_vector[0x10];
8412  
8413  	u8         reserved_2[0x20];
8414  };
8415  
8416  enum {
8417  	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
8418  	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
8419  };
8420  
8421  struct mlx5_ifc_config_int_moderation_in_bits {
8422  	u8         opcode[0x10];
8423  	u8         reserved_0[0x10];
8424  
8425  	u8         reserved_1[0x10];
8426  	u8         op_mod[0x10];
8427  
8428  	u8         reserved_2[0x4];
8429  	u8         min_delay[0xc];
8430  	u8         int_vector[0x10];
8431  
8432  	u8         reserved_3[0x20];
8433  };
8434  
8435  struct mlx5_ifc_attach_to_mcg_out_bits {
8436  	u8         status[0x8];
8437  	u8         reserved_0[0x18];
8438  
8439  	u8         syndrome[0x20];
8440  
8441  	u8         reserved_1[0x40];
8442  };
8443  
8444  struct mlx5_ifc_attach_to_mcg_in_bits {
8445  	u8         opcode[0x10];
8446  	u8         uid[0x10];
8447  
8448  	u8         reserved_1[0x10];
8449  	u8         op_mod[0x10];
8450  
8451  	u8         reserved_2[0x8];
8452  	u8         qpn[0x18];
8453  
8454  	u8         reserved_3[0x20];
8455  
8456  	u8         multicast_gid[16][0x8];
8457  };
8458  
8459  struct mlx5_ifc_arm_xrq_out_bits {
8460  	u8         status[0x8];
8461  	u8         reserved_at_8[0x18];
8462  
8463  	u8         syndrome[0x20];
8464  
8465  	u8         reserved_at_40[0x40];
8466  };
8467  
8468  struct mlx5_ifc_arm_xrq_in_bits {
8469  	u8         opcode[0x10];
8470  	u8         reserved_at_10[0x10];
8471  
8472  	u8         reserved_at_20[0x10];
8473  	u8         op_mod[0x10];
8474  
8475  	u8         reserved_at_40[0x8];
8476  	u8         xrqn[0x18];
8477  
8478  	u8         reserved_at_60[0x10];
8479  	u8         lwm[0x10];
8480  };
8481  
8482  struct mlx5_ifc_arm_xrc_srq_out_bits {
8483  	u8         status[0x8];
8484  	u8         reserved_0[0x18];
8485  
8486  	u8         syndrome[0x20];
8487  
8488  	u8         reserved_1[0x40];
8489  };
8490  
8491  enum {
8492  	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8493  };
8494  
8495  struct mlx5_ifc_arm_xrc_srq_in_bits {
8496  	u8         opcode[0x10];
8497  	u8         uid[0x10];
8498  
8499  	u8         reserved_1[0x10];
8500  	u8         op_mod[0x10];
8501  
8502  	u8         reserved_2[0x8];
8503  	u8         xrc_srqn[0x18];
8504  
8505  	u8         reserved_3[0x10];
8506  	u8         lwm[0x10];
8507  };
8508  
8509  struct mlx5_ifc_arm_rq_out_bits {
8510  	u8         status[0x8];
8511  	u8         reserved_0[0x18];
8512  
8513  	u8         syndrome[0x20];
8514  
8515  	u8         reserved_1[0x40];
8516  };
8517  
8518  enum {
8519  	MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
8520  };
8521  
8522  struct mlx5_ifc_arm_rq_in_bits {
8523  	u8         opcode[0x10];
8524  	u8         uid[0x10];
8525  
8526  	u8         reserved_1[0x10];
8527  	u8         op_mod[0x10];
8528  
8529  	u8         reserved_2[0x8];
8530  	u8         srq_number[0x18];
8531  
8532  	u8         reserved_3[0x10];
8533  	u8         lwm[0x10];
8534  };
8535  
8536  struct mlx5_ifc_arm_dct_out_bits {
8537  	u8         status[0x8];
8538  	u8         reserved_0[0x18];
8539  
8540  	u8         syndrome[0x20];
8541  
8542  	u8         reserved_1[0x40];
8543  };
8544  
8545  struct mlx5_ifc_arm_dct_in_bits {
8546  	u8         opcode[0x10];
8547  	u8         reserved_0[0x10];
8548  
8549  	u8         reserved_1[0x10];
8550  	u8         op_mod[0x10];
8551  
8552  	u8         reserved_2[0x8];
8553  	u8         dctn[0x18];
8554  
8555  	u8         reserved_3[0x20];
8556  };
8557  
8558  struct mlx5_ifc_alloc_xrcd_out_bits {
8559  	u8         status[0x8];
8560  	u8         reserved_0[0x18];
8561  
8562  	u8         syndrome[0x20];
8563  
8564  	u8         reserved_1[0x8];
8565  	u8         xrcd[0x18];
8566  
8567  	u8         reserved_2[0x20];
8568  };
8569  
8570  struct mlx5_ifc_alloc_xrcd_in_bits {
8571  	u8         opcode[0x10];
8572  	u8         uid[0x10];
8573  
8574  	u8         reserved_1[0x10];
8575  	u8         op_mod[0x10];
8576  
8577  	u8         reserved_2[0x40];
8578  };
8579  
8580  struct mlx5_ifc_alloc_uar_out_bits {
8581  	u8         status[0x8];
8582  	u8         reserved_0[0x18];
8583  
8584  	u8         syndrome[0x20];
8585  
8586  	u8         reserved_1[0x8];
8587  	u8         uar[0x18];
8588  
8589  	u8         reserved_2[0x20];
8590  };
8591  
8592  struct mlx5_ifc_alloc_uar_in_bits {
8593  	u8         opcode[0x10];
8594  	u8         reserved_0[0x10];
8595  
8596  	u8         reserved_1[0x10];
8597  	u8         op_mod[0x10];
8598  
8599  	u8         reserved_2[0x40];
8600  };
8601  
8602  struct mlx5_ifc_alloc_transport_domain_out_bits {
8603  	u8         status[0x8];
8604  	u8         reserved_0[0x18];
8605  
8606  	u8         syndrome[0x20];
8607  
8608  	u8         reserved_1[0x8];
8609  	u8         transport_domain[0x18];
8610  
8611  	u8         reserved_2[0x20];
8612  };
8613  
8614  struct mlx5_ifc_alloc_transport_domain_in_bits {
8615  	u8         opcode[0x10];
8616  	u8         uid[0x10];
8617  
8618  	u8         reserved_1[0x10];
8619  	u8         op_mod[0x10];
8620  
8621  	u8         reserved_2[0x40];
8622  };
8623  
8624  struct mlx5_ifc_alloc_q_counter_out_bits {
8625  	u8         status[0x8];
8626  	u8         reserved_0[0x18];
8627  
8628  	u8         syndrome[0x20];
8629  
8630  	u8         reserved_1[0x18];
8631  	u8         counter_set_id[0x8];
8632  
8633  	u8         reserved_2[0x20];
8634  };
8635  
8636  struct mlx5_ifc_alloc_q_counter_in_bits {
8637  	u8         opcode[0x10];
8638  	u8         uid[0x10];
8639  
8640  	u8         reserved_1[0x10];
8641  	u8         op_mod[0x10];
8642  
8643  	u8         reserved_2[0x40];
8644  };
8645  
8646  struct mlx5_ifc_alloc_pd_out_bits {
8647  	u8         status[0x8];
8648  	u8         reserved_0[0x18];
8649  
8650  	u8         syndrome[0x20];
8651  
8652  	u8         reserved_1[0x8];
8653  	u8         pd[0x18];
8654  
8655  	u8         reserved_2[0x20];
8656  };
8657  
8658  struct mlx5_ifc_alloc_pd_in_bits {
8659  	u8         opcode[0x10];
8660  	u8         uid[0x10];
8661  
8662  	u8         reserved_1[0x10];
8663  	u8         op_mod[0x10];
8664  
8665  	u8         reserved_2[0x40];
8666  };
8667  
8668  struct mlx5_ifc_alloc_flow_counter_out_bits {
8669  	u8         status[0x8];
8670  	u8         reserved_at_8[0x18];
8671  
8672  	u8         syndrome[0x20];
8673  
8674  	u8         flow_counter_id[0x20];
8675  
8676  	u8         reserved_at_60[0x20];
8677  };
8678  
8679  struct mlx5_ifc_alloc_flow_counter_in_bits {
8680  	u8         opcode[0x10];
8681  	u8         reserved_at_10[0x10];
8682  
8683  	u8         reserved_at_20[0x10];
8684  	u8         op_mod[0x10];
8685  
8686  	u8         reserved_at_40[0x38];
8687  	u8         flow_counter_bulk[0x8];
8688  };
8689  
8690  struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8691  	u8         status[0x8];
8692  	u8         reserved_0[0x18];
8693  
8694  	u8         syndrome[0x20];
8695  
8696  	u8         reserved_1[0x40];
8697  };
8698  
8699  struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8700  	u8         opcode[0x10];
8701  	u8         reserved_0[0x10];
8702  
8703  	u8         reserved_1[0x10];
8704  	u8         op_mod[0x10];
8705  
8706  	u8         reserved_2[0x20];
8707  
8708  	u8         reserved_3[0x10];
8709  	u8         vxlan_udp_port[0x10];
8710  };
8711  
8712  struct mlx5_ifc_activate_tracer_out_bits {
8713  	u8         status[0x8];
8714  	u8         reserved_0[0x18];
8715  
8716  	u8         syndrome[0x20];
8717  
8718  	u8         reserved_1[0x40];
8719  };
8720  
8721  struct mlx5_ifc_activate_tracer_in_bits {
8722  	u8         opcode[0x10];
8723  	u8         reserved_0[0x10];
8724  
8725  	u8         reserved_1[0x10];
8726  	u8         op_mod[0x10];
8727  
8728  	u8         mkey[0x20];
8729  
8730  	u8         reserved_2[0x20];
8731  };
8732  
8733  struct mlx5_ifc_set_rate_limit_out_bits {
8734  	u8         status[0x8];
8735  	u8         reserved_at_8[0x18];
8736  
8737  	u8         syndrome[0x20];
8738  
8739  	u8         reserved_at_40[0x40];
8740  };
8741  
8742  struct mlx5_ifc_set_rate_limit_in_bits {
8743  	u8         opcode[0x10];
8744  	u8         uid[0x10];
8745  
8746  	u8         reserved_at_20[0x10];
8747  	u8         op_mod[0x10];
8748  
8749  	u8         reserved_at_40[0x10];
8750  	u8         rate_limit_index[0x10];
8751  
8752  	u8         reserved_at_60[0x20];
8753  
8754  	u8         rate_limit[0x20];
8755  
8756  	u8         burst_upper_bound[0x20];
8757  
8758  	u8         reserved_at_c0[0x10];
8759  	u8         typical_packet_size[0x10];
8760  
8761  	u8         reserved_at_e0[0x120];
8762  };
8763  
8764  struct mlx5_ifc_access_register_out_bits {
8765  	u8         status[0x8];
8766  	u8         reserved_0[0x18];
8767  
8768  	u8         syndrome[0x20];
8769  
8770  	u8         reserved_1[0x40];
8771  
8772  	u8         register_data[0][0x20];
8773  };
8774  
8775  enum {
8776  	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8777  	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8778  };
8779  
8780  struct mlx5_ifc_access_register_in_bits {
8781  	u8         opcode[0x10];
8782  	u8         reserved_0[0x10];
8783  
8784  	u8         reserved_1[0x10];
8785  	u8         op_mod[0x10];
8786  
8787  	u8         reserved_2[0x10];
8788  	u8         register_id[0x10];
8789  
8790  	u8         argument[0x20];
8791  
8792  	u8         register_data[0][0x20];
8793  };
8794  
8795  struct mlx5_ifc_sltp_reg_bits {
8796  	u8         status[0x4];
8797  	u8         version[0x4];
8798  	u8         local_port[0x8];
8799  	u8         pnat[0x2];
8800  	u8         reserved_0[0x2];
8801  	u8         lane[0x4];
8802  	u8         reserved_1[0x8];
8803  
8804  	u8         reserved_2[0x20];
8805  
8806  	u8         reserved_3[0x7];
8807  	u8         polarity[0x1];
8808  	u8         ob_tap0[0x8];
8809  	u8         ob_tap1[0x8];
8810  	u8         ob_tap2[0x8];
8811  
8812  	u8         reserved_4[0xc];
8813  	u8         ob_preemp_mode[0x4];
8814  	u8         ob_reg[0x8];
8815  	u8         ob_bias[0x8];
8816  
8817  	u8         reserved_5[0x20];
8818  };
8819  
8820  struct mlx5_ifc_slrp_reg_bits {
8821  	u8         status[0x4];
8822  	u8         version[0x4];
8823  	u8         local_port[0x8];
8824  	u8         pnat[0x2];
8825  	u8         reserved_0[0x2];
8826  	u8         lane[0x4];
8827  	u8         reserved_1[0x8];
8828  
8829  	u8         ib_sel[0x2];
8830  	u8         reserved_2[0x11];
8831  	u8         dp_sel[0x1];
8832  	u8         dp90sel[0x4];
8833  	u8         mix90phase[0x8];
8834  
8835  	u8         ffe_tap0[0x8];
8836  	u8         ffe_tap1[0x8];
8837  	u8         ffe_tap2[0x8];
8838  	u8         ffe_tap3[0x8];
8839  
8840  	u8         ffe_tap4[0x8];
8841  	u8         ffe_tap5[0x8];
8842  	u8         ffe_tap6[0x8];
8843  	u8         ffe_tap7[0x8];
8844  
8845  	u8         ffe_tap8[0x8];
8846  	u8         mixerbias_tap_amp[0x8];
8847  	u8         reserved_3[0x7];
8848  	u8         ffe_tap_en[0x9];
8849  
8850  	u8         ffe_tap_offset0[0x8];
8851  	u8         ffe_tap_offset1[0x8];
8852  	u8         slicer_offset0[0x10];
8853  
8854  	u8         mixer_offset0[0x10];
8855  	u8         mixer_offset1[0x10];
8856  
8857  	u8         mixerbgn_inp[0x8];
8858  	u8         mixerbgn_inn[0x8];
8859  	u8         mixerbgn_refp[0x8];
8860  	u8         mixerbgn_refn[0x8];
8861  
8862  	u8         sel_slicer_lctrl_h[0x1];
8863  	u8         sel_slicer_lctrl_l[0x1];
8864  	u8         reserved_4[0x1];
8865  	u8         ref_mixer_vreg[0x5];
8866  	u8         slicer_gctrl[0x8];
8867  	u8         lctrl_input[0x8];
8868  	u8         mixer_offset_cm1[0x8];
8869  
8870  	u8         common_mode[0x6];
8871  	u8         reserved_5[0x1];
8872  	u8         mixer_offset_cm0[0x9];
8873  	u8         reserved_6[0x7];
8874  	u8         slicer_offset_cm[0x9];
8875  };
8876  
8877  struct mlx5_ifc_slrg_reg_bits {
8878  	u8         status[0x4];
8879  	u8         version[0x4];
8880  	u8         local_port[0x8];
8881  	u8         pnat[0x2];
8882  	u8         reserved_0[0x2];
8883  	u8         lane[0x4];
8884  	u8         reserved_1[0x8];
8885  
8886  	u8         time_to_link_up[0x10];
8887  	u8         reserved_2[0xc];
8888  	u8         grade_lane_speed[0x4];
8889  
8890  	u8         grade_version[0x8];
8891  	u8         grade[0x18];
8892  
8893  	u8         reserved_3[0x4];
8894  	u8         height_grade_type[0x4];
8895  	u8         height_grade[0x18];
8896  
8897  	u8         height_dz[0x10];
8898  	u8         height_dv[0x10];
8899  
8900  	u8         reserved_4[0x10];
8901  	u8         height_sigma[0x10];
8902  
8903  	u8         reserved_5[0x20];
8904  
8905  	u8         reserved_6[0x4];
8906  	u8         phase_grade_type[0x4];
8907  	u8         phase_grade[0x18];
8908  
8909  	u8         reserved_7[0x8];
8910  	u8         phase_eo_pos[0x8];
8911  	u8         reserved_8[0x8];
8912  	u8         phase_eo_neg[0x8];
8913  
8914  	u8         ffe_set_tested[0x10];
8915  	u8         test_errors_per_lane[0x10];
8916  };
8917  
8918  struct mlx5_ifc_pvlc_reg_bits {
8919  	u8         reserved_0[0x8];
8920  	u8         local_port[0x8];
8921  	u8         reserved_1[0x10];
8922  
8923  	u8         reserved_2[0x1c];
8924  	u8         vl_hw_cap[0x4];
8925  
8926  	u8         reserved_3[0x1c];
8927  	u8         vl_admin[0x4];
8928  
8929  	u8         reserved_4[0x1c];
8930  	u8         vl_operational[0x4];
8931  };
8932  
8933  struct mlx5_ifc_pude_reg_bits {
8934  	u8         swid[0x8];
8935  	u8         local_port[0x8];
8936  	u8         reserved_0[0x4];
8937  	u8         admin_status[0x4];
8938  	u8         reserved_1[0x4];
8939  	u8         oper_status[0x4];
8940  
8941  	u8         reserved_2[0x60];
8942  };
8943  
8944  enum {
8945  	MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
8946  	MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
8947  };
8948  
8949  struct mlx5_ifc_ptys_reg_bits {
8950  	u8         reserved_0[0x1];
8951  	u8         an_disable_admin[0x1];
8952  	u8         an_disable_cap[0x1];
8953  	u8         reserved_1[0x4];
8954  	u8         force_tx_aba_param[0x1];
8955  	u8         local_port[0x8];
8956  	u8         reserved_2[0xd];
8957  	u8         proto_mask[0x3];
8958  
8959  	u8         an_status[0x4];
8960  	u8         reserved_3[0xc];
8961  	u8         data_rate_oper[0x10];
8962  
8963  	u8         ext_eth_proto_capability[0x20];
8964  
8965  	u8         eth_proto_capability[0x20];
8966  
8967  	u8         ib_link_width_capability[0x10];
8968  	u8         ib_proto_capability[0x10];
8969  
8970  	u8         ext_eth_proto_admin[0x20];
8971  
8972  	u8         eth_proto_admin[0x20];
8973  
8974  	u8         ib_link_width_admin[0x10];
8975  	u8         ib_proto_admin[0x10];
8976  
8977  	u8         ext_eth_proto_oper[0x20];
8978  
8979  	u8         eth_proto_oper[0x20];
8980  
8981  	u8         ib_link_width_oper[0x10];
8982  	u8         ib_proto_oper[0x10];
8983  
8984  	u8         reserved_4[0x1c];
8985  	u8         connector_type[0x4];
8986  
8987  	u8         eth_proto_lp_advertise[0x20];
8988  
8989  	u8         reserved_5[0x60];
8990  };
8991  
8992  struct mlx5_ifc_ptas_reg_bits {
8993  	u8         reserved_0[0x20];
8994  
8995  	u8         algorithm_options[0x10];
8996  	u8         reserved_1[0x4];
8997  	u8         repetitions_mode[0x4];
8998  	u8         num_of_repetitions[0x8];
8999  
9000  	u8         grade_version[0x8];
9001  	u8         height_grade_type[0x4];
9002  	u8         phase_grade_type[0x4];
9003  	u8         height_grade_weight[0x8];
9004  	u8         phase_grade_weight[0x8];
9005  
9006  	u8         gisim_measure_bits[0x10];
9007  	u8         adaptive_tap_measure_bits[0x10];
9008  
9009  	u8         ber_bath_high_error_threshold[0x10];
9010  	u8         ber_bath_mid_error_threshold[0x10];
9011  
9012  	u8         ber_bath_low_error_threshold[0x10];
9013  	u8         one_ratio_high_threshold[0x10];
9014  
9015  	u8         one_ratio_high_mid_threshold[0x10];
9016  	u8         one_ratio_low_mid_threshold[0x10];
9017  
9018  	u8         one_ratio_low_threshold[0x10];
9019  	u8         ndeo_error_threshold[0x10];
9020  
9021  	u8         mixer_offset_step_size[0x10];
9022  	u8         reserved_2[0x8];
9023  	u8         mix90_phase_for_voltage_bath[0x8];
9024  
9025  	u8         mixer_offset_start[0x10];
9026  	u8         mixer_offset_end[0x10];
9027  
9028  	u8         reserved_3[0x15];
9029  	u8         ber_test_time[0xb];
9030  };
9031  
9032  struct mlx5_ifc_pspa_reg_bits {
9033  	u8         swid[0x8];
9034  	u8         local_port[0x8];
9035  	u8         sub_port[0x8];
9036  	u8         reserved_0[0x8];
9037  
9038  	u8         reserved_1[0x20];
9039  };
9040  
9041  struct mlx5_ifc_ppsc_reg_bits {
9042  	u8         reserved_0[0x8];
9043  	u8         local_port[0x8];
9044  	u8         reserved_1[0x10];
9045  
9046  	u8         reserved_2[0x60];
9047  
9048  	u8         reserved_3[0x1c];
9049  	u8         wrps_admin[0x4];
9050  
9051  	u8         reserved_4[0x1c];
9052  	u8         wrps_status[0x4];
9053  
9054  	u8         up_th_vld[0x1];
9055  	u8         down_th_vld[0x1];
9056  	u8         reserved_5[0x6];
9057  	u8         up_threshold[0x8];
9058  	u8         reserved_6[0x8];
9059  	u8         down_threshold[0x8];
9060  
9061  	u8         reserved_7[0x20];
9062  
9063  	u8         reserved_8[0x1c];
9064  	u8         srps_admin[0x4];
9065  
9066  	u8         reserved_9[0x60];
9067  };
9068  
9069  struct mlx5_ifc_pplr_reg_bits {
9070  	u8         reserved_0[0x8];
9071  	u8         local_port[0x8];
9072  	u8         reserved_1[0x10];
9073  
9074  	u8         reserved_2[0x8];
9075  	u8         lb_cap[0x8];
9076  	u8         reserved_3[0x8];
9077  	u8         lb_en[0x8];
9078  };
9079  
9080  struct mlx5_ifc_pplm_reg_bits {
9081  	u8         reserved_at_0[0x8];
9082  	u8	   local_port[0x8];
9083  	u8	   reserved_at_10[0x10];
9084  
9085  	u8	   reserved_at_20[0x20];
9086  
9087  	u8	   port_profile_mode[0x8];
9088  	u8	   static_port_profile[0x8];
9089  	u8	   active_port_profile[0x8];
9090  	u8	   reserved_at_58[0x8];
9091  
9092  	u8	   retransmission_active[0x8];
9093  	u8	   fec_mode_active[0x18];
9094  
9095  	u8	   rs_fec_correction_bypass_cap[0x4];
9096  	u8	   reserved_at_84[0x8];
9097  	u8	   fec_override_cap_56g[0x4];
9098  	u8	   fec_override_cap_100g[0x4];
9099  	u8	   fec_override_cap_50g[0x4];
9100  	u8	   fec_override_cap_25g[0x4];
9101  	u8	   fec_override_cap_10g_40g[0x4];
9102  
9103  	u8	   rs_fec_correction_bypass_admin[0x4];
9104  	u8	   reserved_at_a4[0x8];
9105  	u8	   fec_override_admin_56g[0x4];
9106  	u8	   fec_override_admin_100g[0x4];
9107  	u8	   fec_override_admin_50g[0x4];
9108  	u8	   fec_override_admin_25g[0x4];
9109  	u8	   fec_override_admin_10g_40g[0x4];
9110  
9111  	u8	   fec_override_cap_400g_8x[0x10];
9112  	u8	   fec_override_cap_200g_4x[0x10];
9113  	u8	   fec_override_cap_100g_2x[0x10];
9114  	u8	   fec_override_cap_50g_1x[0x10];
9115  
9116  	u8	   fec_override_admin_400g_8x[0x10];
9117  	u8	   fec_override_admin_200g_4x[0x10];
9118  	u8	   fec_override_admin_100g_2x[0x10];
9119  	u8	   fec_override_admin_50g_1x[0x10];
9120  
9121  	u8	   reserved_at_140[0x140];
9122  };
9123  
9124  struct mlx5_ifc_ppll_reg_bits {
9125  	u8         num_pll_groups[0x8];
9126  	u8         pll_group[0x8];
9127  	u8         reserved_0[0x4];
9128  	u8         num_plls[0x4];
9129  	u8         reserved_1[0x8];
9130  
9131  	u8         reserved_2[0x1f];
9132  	u8         ae[0x1];
9133  
9134  	u8         pll_status[4][0x40];
9135  };
9136  
9137  struct mlx5_ifc_ppad_reg_bits {
9138  	u8         reserved_0[0x3];
9139  	u8         single_mac[0x1];
9140  	u8         reserved_1[0x4];
9141  	u8         local_port[0x8];
9142  	u8         mac_47_32[0x10];
9143  
9144  	u8         mac_31_0[0x20];
9145  
9146  	u8         reserved_2[0x40];
9147  };
9148  
9149  struct mlx5_ifc_pmtu_reg_bits {
9150  	u8         reserved_0[0x8];
9151  	u8         local_port[0x8];
9152  	u8         reserved_1[0x10];
9153  
9154  	u8         max_mtu[0x10];
9155  	u8         reserved_2[0x10];
9156  
9157  	u8         admin_mtu[0x10];
9158  	u8         reserved_3[0x10];
9159  
9160  	u8         oper_mtu[0x10];
9161  	u8         reserved_4[0x10];
9162  };
9163  
9164  struct mlx5_ifc_pmpr_reg_bits {
9165  	u8         reserved_0[0x8];
9166  	u8         module[0x8];
9167  	u8         reserved_1[0x10];
9168  
9169  	u8         reserved_2[0x18];
9170  	u8         attenuation_5g[0x8];
9171  
9172  	u8         reserved_3[0x18];
9173  	u8         attenuation_7g[0x8];
9174  
9175  	u8         reserved_4[0x18];
9176  	u8         attenuation_12g[0x8];
9177  };
9178  
9179  struct mlx5_ifc_pmpe_reg_bits {
9180  	u8         reserved_0[0x8];
9181  	u8         module[0x8];
9182  	u8         reserved_1[0xc];
9183  	u8         module_status[0x4];
9184  
9185  	u8         reserved_2[0x14];
9186  	u8         error_type[0x4];
9187  	u8         reserved_3[0x8];
9188  
9189  	u8         reserved_4[0x40];
9190  };
9191  
9192  struct mlx5_ifc_pmpc_reg_bits {
9193  	u8         module_state_updated[32][0x8];
9194  };
9195  
9196  struct mlx5_ifc_pmlpn_reg_bits {
9197  	u8         reserved_0[0x4];
9198  	u8         mlpn_status[0x4];
9199  	u8         local_port[0x8];
9200  	u8         reserved_1[0x10];
9201  
9202  	u8         e[0x1];
9203  	u8         reserved_2[0x1f];
9204  };
9205  
9206  struct mlx5_ifc_pmlp_reg_bits {
9207  	u8         rxtx[0x1];
9208  	u8         reserved_0[0x7];
9209  	u8         local_port[0x8];
9210  	u8         reserved_1[0x8];
9211  	u8         width[0x8];
9212  
9213  	u8         lane0_module_mapping[0x20];
9214  
9215  	u8         lane1_module_mapping[0x20];
9216  
9217  	u8         lane2_module_mapping[0x20];
9218  
9219  	u8         lane3_module_mapping[0x20];
9220  
9221  	u8         reserved_2[0x160];
9222  };
9223  
9224  struct mlx5_ifc_pmaos_reg_bits {
9225  	u8         reserved_0[0x8];
9226  	u8         module[0x8];
9227  	u8         reserved_1[0x4];
9228  	u8         admin_status[0x4];
9229  	u8         reserved_2[0x4];
9230  	u8         oper_status[0x4];
9231  
9232  	u8         ase[0x1];
9233  	u8         ee[0x1];
9234  	u8         reserved_3[0x12];
9235  	u8         error_type[0x4];
9236  	u8         reserved_4[0x6];
9237  	u8         e[0x2];
9238  
9239  	u8         reserved_5[0x40];
9240  };
9241  
9242  struct mlx5_ifc_plpc_reg_bits {
9243  	u8         reserved_0[0x4];
9244  	u8         profile_id[0xc];
9245  	u8         reserved_1[0x4];
9246  	u8         proto_mask[0x4];
9247  	u8         reserved_2[0x8];
9248  
9249  	u8         reserved_3[0x10];
9250  	u8         lane_speed[0x10];
9251  
9252  	u8         reserved_4[0x17];
9253  	u8         lpbf[0x1];
9254  	u8         fec_mode_policy[0x8];
9255  
9256  	u8         retransmission_capability[0x8];
9257  	u8         fec_mode_capability[0x18];
9258  
9259  	u8         retransmission_support_admin[0x8];
9260  	u8         fec_mode_support_admin[0x18];
9261  
9262  	u8         retransmission_request_admin[0x8];
9263  	u8         fec_mode_request_admin[0x18];
9264  
9265  	u8         reserved_5[0x80];
9266  };
9267  
9268  struct mlx5_ifc_pll_status_data_bits {
9269  	u8         reserved_0[0x1];
9270  	u8         lock_cal[0x1];
9271  	u8         lock_status[0x2];
9272  	u8         reserved_1[0x2];
9273  	u8         algo_f_ctrl[0xa];
9274  	u8         analog_algo_num_var[0x6];
9275  	u8         f_ctrl_measure[0xa];
9276  
9277  	u8         reserved_2[0x2];
9278  	u8         analog_var[0x6];
9279  	u8         reserved_3[0x2];
9280  	u8         high_var[0x6];
9281  	u8         reserved_4[0x2];
9282  	u8         low_var[0x6];
9283  	u8         reserved_5[0x2];
9284  	u8         mid_val[0x6];
9285  };
9286  
9287  struct mlx5_ifc_plib_reg_bits {
9288  	u8         reserved_0[0x8];
9289  	u8         local_port[0x8];
9290  	u8         reserved_1[0x8];
9291  	u8         ib_port[0x8];
9292  
9293  	u8         reserved_2[0x60];
9294  };
9295  
9296  struct mlx5_ifc_plbf_reg_bits {
9297  	u8         reserved_0[0x8];
9298  	u8         local_port[0x8];
9299  	u8         reserved_1[0xd];
9300  	u8         lbf_mode[0x3];
9301  
9302  	u8         reserved_2[0x20];
9303  };
9304  
9305  struct mlx5_ifc_pipg_reg_bits {
9306  	u8         reserved_0[0x8];
9307  	u8         local_port[0x8];
9308  	u8         reserved_1[0x10];
9309  
9310  	u8         dic[0x1];
9311  	u8         reserved_2[0x19];
9312  	u8         ipg[0x4];
9313  	u8         reserved_3[0x2];
9314  };
9315  
9316  struct mlx5_ifc_pifr_reg_bits {
9317  	u8         reserved_0[0x8];
9318  	u8         local_port[0x8];
9319  	u8         reserved_1[0x10];
9320  
9321  	u8         reserved_2[0xe0];
9322  
9323  	u8         port_filter[8][0x20];
9324  
9325  	u8         port_filter_update_en[8][0x20];
9326  };
9327  
9328  struct mlx5_ifc_phys_layer_cntrs_bits {
9329  	u8         time_since_last_clear_high[0x20];
9330  
9331  	u8         time_since_last_clear_low[0x20];
9332  
9333  	u8         symbol_errors_high[0x20];
9334  
9335  	u8         symbol_errors_low[0x20];
9336  
9337  	u8         sync_headers_errors_high[0x20];
9338  
9339  	u8         sync_headers_errors_low[0x20];
9340  
9341  	u8         edpl_bip_errors_lane0_high[0x20];
9342  
9343  	u8         edpl_bip_errors_lane0_low[0x20];
9344  
9345  	u8         edpl_bip_errors_lane1_high[0x20];
9346  
9347  	u8         edpl_bip_errors_lane1_low[0x20];
9348  
9349  	u8         edpl_bip_errors_lane2_high[0x20];
9350  
9351  	u8         edpl_bip_errors_lane2_low[0x20];
9352  
9353  	u8         edpl_bip_errors_lane3_high[0x20];
9354  
9355  	u8         edpl_bip_errors_lane3_low[0x20];
9356  
9357  	u8         fc_fec_corrected_blocks_lane0_high[0x20];
9358  
9359  	u8         fc_fec_corrected_blocks_lane0_low[0x20];
9360  
9361  	u8         fc_fec_corrected_blocks_lane1_high[0x20];
9362  
9363  	u8         fc_fec_corrected_blocks_lane1_low[0x20];
9364  
9365  	u8         fc_fec_corrected_blocks_lane2_high[0x20];
9366  
9367  	u8         fc_fec_corrected_blocks_lane2_low[0x20];
9368  
9369  	u8         fc_fec_corrected_blocks_lane3_high[0x20];
9370  
9371  	u8         fc_fec_corrected_blocks_lane3_low[0x20];
9372  
9373  	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
9374  
9375  	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
9376  
9377  	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
9378  
9379  	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
9380  
9381  	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
9382  
9383  	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
9384  
9385  	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
9386  
9387  	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
9388  
9389  	u8         rs_fec_corrected_blocks_high[0x20];
9390  
9391  	u8         rs_fec_corrected_blocks_low[0x20];
9392  
9393  	u8         rs_fec_uncorrectable_blocks_high[0x20];
9394  
9395  	u8         rs_fec_uncorrectable_blocks_low[0x20];
9396  
9397  	u8         rs_fec_no_errors_blocks_high[0x20];
9398  
9399  	u8         rs_fec_no_errors_blocks_low[0x20];
9400  
9401  	u8         rs_fec_single_error_blocks_high[0x20];
9402  
9403  	u8         rs_fec_single_error_blocks_low[0x20];
9404  
9405  	u8         rs_fec_corrected_symbols_total_high[0x20];
9406  
9407  	u8         rs_fec_corrected_symbols_total_low[0x20];
9408  
9409  	u8         rs_fec_corrected_symbols_lane0_high[0x20];
9410  
9411  	u8         rs_fec_corrected_symbols_lane0_low[0x20];
9412  
9413  	u8         rs_fec_corrected_symbols_lane1_high[0x20];
9414  
9415  	u8         rs_fec_corrected_symbols_lane1_low[0x20];
9416  
9417  	u8         rs_fec_corrected_symbols_lane2_high[0x20];
9418  
9419  	u8         rs_fec_corrected_symbols_lane2_low[0x20];
9420  
9421  	u8         rs_fec_corrected_symbols_lane3_high[0x20];
9422  
9423  	u8         rs_fec_corrected_symbols_lane3_low[0x20];
9424  
9425  	u8         link_down_events[0x20];
9426  
9427  	u8         successful_recovery_events[0x20];
9428  
9429  	u8         reserved_0[0x180];
9430  };
9431  
9432  struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
9433  	u8	   symbol_error_counter[0x10];
9434  
9435  	u8         link_error_recovery_counter[0x8];
9436  
9437  	u8         link_downed_counter[0x8];
9438  
9439  	u8         port_rcv_errors[0x10];
9440  
9441  	u8         port_rcv_remote_physical_errors[0x10];
9442  
9443  	u8         port_rcv_switch_relay_errors[0x10];
9444  
9445  	u8         port_xmit_discards[0x10];
9446  
9447  	u8         port_xmit_constraint_errors[0x8];
9448  
9449  	u8         port_rcv_constraint_errors[0x8];
9450  
9451  	u8         reserved_at_70[0x8];
9452  
9453  	u8         link_overrun_errors[0x8];
9454  
9455  	u8	   reserved_at_80[0x10];
9456  
9457  	u8         vl_15_dropped[0x10];
9458  
9459  	u8	   reserved_at_a0[0xa0];
9460  };
9461  
9462  struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
9463  	u8         time_since_last_clear_high[0x20];
9464  
9465  	u8         time_since_last_clear_low[0x20];
9466  
9467  	u8         phy_received_bits_high[0x20];
9468  
9469  	u8         phy_received_bits_low[0x20];
9470  
9471  	u8         phy_symbol_errors_high[0x20];
9472  
9473  	u8         phy_symbol_errors_low[0x20];
9474  
9475  	u8         phy_corrected_bits_high[0x20];
9476  
9477  	u8         phy_corrected_bits_low[0x20];
9478  
9479  	u8         phy_corrected_bits_lane0_high[0x20];
9480  
9481  	u8         phy_corrected_bits_lane0_low[0x20];
9482  
9483  	u8         phy_corrected_bits_lane1_high[0x20];
9484  
9485  	u8         phy_corrected_bits_lane1_low[0x20];
9486  
9487  	u8         phy_corrected_bits_lane2_high[0x20];
9488  
9489  	u8         phy_corrected_bits_lane2_low[0x20];
9490  
9491  	u8         phy_corrected_bits_lane3_high[0x20];
9492  
9493  	u8         phy_corrected_bits_lane3_low[0x20];
9494  
9495  	u8         reserved_at_200[0x5c0];
9496  };
9497  
9498  struct mlx5_ifc_infiniband_port_cntrs_bits {
9499  	u8         symbol_error_counter[0x10];
9500  	u8         link_error_recovery_counter[0x8];
9501  	u8         link_downed_counter[0x8];
9502  
9503  	u8         port_rcv_errors[0x10];
9504  	u8         port_rcv_remote_physical_errors[0x10];
9505  
9506  	u8         port_rcv_switch_relay_errors[0x10];
9507  	u8         port_xmit_discards[0x10];
9508  
9509  	u8         port_xmit_constraint_errors[0x8];
9510  	u8         port_rcv_constraint_errors[0x8];
9511  	u8         reserved_0[0x8];
9512  	u8         local_link_integrity_errors[0x4];
9513  	u8         excessive_buffer_overrun_errors[0x4];
9514  
9515  	u8         reserved_1[0x10];
9516  	u8         vl_15_dropped[0x10];
9517  
9518  	u8         port_xmit_data[0x20];
9519  
9520  	u8         port_rcv_data[0x20];
9521  
9522  	u8         port_xmit_pkts[0x20];
9523  
9524  	u8         port_rcv_pkts[0x20];
9525  
9526  	u8         port_xmit_wait[0x20];
9527  
9528  	u8         reserved_2[0x680];
9529  };
9530  
9531  struct mlx5_ifc_phrr_reg_bits {
9532  	u8         clr[0x1];
9533  	u8         reserved_0[0x7];
9534  	u8         local_port[0x8];
9535  	u8         reserved_1[0x10];
9536  
9537  	u8         hist_group[0x8];
9538  	u8         reserved_2[0x10];
9539  	u8         hist_id[0x8];
9540  
9541  	u8         reserved_3[0x40];
9542  
9543  	u8         time_since_last_clear_high[0x20];
9544  
9545  	u8         time_since_last_clear_low[0x20];
9546  
9547  	u8         bin[10][0x20];
9548  };
9549  
9550  struct mlx5_ifc_phbr_for_prio_reg_bits {
9551  	u8         reserved_0[0x18];
9552  	u8         prio[0x8];
9553  };
9554  
9555  struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
9556  	u8         reserved_0[0x18];
9557  	u8         tclass[0x8];
9558  };
9559  
9560  struct mlx5_ifc_phbr_binding_reg_bits {
9561  	u8         opcode[0x4];
9562  	u8         reserved_0[0x4];
9563  	u8         local_port[0x8];
9564  	u8         pnat[0x2];
9565  	u8         reserved_1[0xe];
9566  
9567  	u8         hist_group[0x8];
9568  	u8         reserved_2[0x10];
9569  	u8         hist_id[0x8];
9570  
9571  	u8         reserved_3[0x10];
9572  	u8         hist_type[0x10];
9573  
9574  	u8         hist_parameters[0x20];
9575  
9576  	u8         hist_min_value[0x20];
9577  
9578  	u8         hist_max_value[0x20];
9579  
9580  	u8         sample_time[0x20];
9581  };
9582  
9583  enum {
9584  	MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
9585  	MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
9586  };
9587  
9588  struct mlx5_ifc_pfcc_reg_bits {
9589  	u8         dcbx_operation_type[0x2];
9590  	u8         cap_local_admin[0x1];
9591  	u8         cap_remote_admin[0x1];
9592  	u8         reserved_0[0x4];
9593  	u8         local_port[0x8];
9594  	u8         pnat[0x2];
9595  	u8         reserved_1[0xc];
9596  	u8         shl_cap[0x1];
9597  	u8         shl_opr[0x1];
9598  
9599  	u8         ppan[0x4];
9600  	u8         reserved_2[0x4];
9601  	u8         prio_mask_tx[0x8];
9602  	u8         reserved_3[0x8];
9603  	u8         prio_mask_rx[0x8];
9604  
9605  	u8         pptx[0x1];
9606  	u8         aptx[0x1];
9607  	u8         reserved_4[0x6];
9608  	u8         pfctx[0x8];
9609  	u8         reserved_5[0x8];
9610  	u8         cbftx[0x8];
9611  
9612  	u8         pprx[0x1];
9613  	u8         aprx[0x1];
9614  	u8         reserved_6[0x6];
9615  	u8         pfcrx[0x8];
9616  	u8         reserved_7[0x8];
9617  	u8         cbfrx[0x8];
9618  
9619  	u8         device_stall_minor_watermark[0x10];
9620  	u8         device_stall_critical_watermark[0x10];
9621  
9622  	u8         reserved_8[0x60];
9623  };
9624  
9625  struct mlx5_ifc_pelc_reg_bits {
9626  	u8         op[0x4];
9627  	u8         reserved_0[0x4];
9628  	u8         local_port[0x8];
9629  	u8         reserved_1[0x10];
9630  
9631  	u8         op_admin[0x8];
9632  	u8         op_capability[0x8];
9633  	u8         op_request[0x8];
9634  	u8         op_active[0x8];
9635  
9636  	u8         admin[0x40];
9637  
9638  	u8         capability[0x40];
9639  
9640  	u8         request[0x40];
9641  
9642  	u8         active[0x40];
9643  
9644  	u8         reserved_2[0x80];
9645  };
9646  
9647  struct mlx5_ifc_peir_reg_bits {
9648  	u8         reserved_0[0x8];
9649  	u8         local_port[0x8];
9650  	u8         reserved_1[0x10];
9651  
9652  	u8         reserved_2[0xc];
9653  	u8         error_count[0x4];
9654  	u8         reserved_3[0x10];
9655  
9656  	u8         reserved_4[0xc];
9657  	u8         lane[0x4];
9658  	u8         reserved_5[0x8];
9659  	u8         error_type[0x8];
9660  };
9661  
9662  struct mlx5_ifc_qcam_access_reg_cap_mask {
9663  	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9664  	u8         qpdpm[0x1];
9665  	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9666  	u8         qdpm[0x1];
9667  	u8         qpts[0x1];
9668  	u8         qcap[0x1];
9669  	u8         qcam_access_reg_cap_mask_0[0x1];
9670  };
9671  
9672  struct mlx5_ifc_qcam_qos_feature_cap_mask {
9673  	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9674  	u8         qpts_trust_both[0x1];
9675  };
9676  
9677  struct mlx5_ifc_qcam_reg_bits {
9678  	u8         reserved_at_0[0x8];
9679  	u8         feature_group[0x8];
9680  	u8         reserved_at_10[0x8];
9681  	u8         access_reg_group[0x8];
9682  	u8         reserved_at_20[0x20];
9683  
9684  	union {
9685  		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9686  		u8  reserved_at_0[0x80];
9687  	} qos_access_reg_cap_mask;
9688  
9689  	u8         reserved_at_c0[0x80];
9690  
9691  	union {
9692  		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9693  		u8  reserved_at_0[0x80];
9694  	} qos_feature_cap_mask;
9695  
9696  	u8         reserved_at_1c0[0x80];
9697  };
9698  
9699  struct mlx5_ifc_pcam_enhanced_features_bits {
9700  	u8         reserved_at_0[0x6d];
9701  	u8         rx_icrc_encapsulated_counter[0x1];
9702  	u8	   reserved_at_6e[0x4];
9703  	u8         ptys_extended_ethernet[0x1];
9704  	u8	   reserved_at_73[0x3];
9705  	u8         pfcc_mask[0x1];
9706  	u8         reserved_at_77[0x3];
9707  	u8         per_lane_error_counters[0x1];
9708  	u8         rx_buffer_fullness_counters[0x1];
9709  	u8         ptys_connector_type[0x1];
9710  	u8         reserved_at_7d[0x1];
9711  	u8         ppcnt_discard_group[0x1];
9712  	u8         ppcnt_statistical_group[0x1];
9713  };
9714  
9715  struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9716  	u8         port_access_reg_cap_mask_127_to_96[0x20];
9717  	u8         port_access_reg_cap_mask_95_to_64[0x20];
9718  
9719  	u8         reserved_at_40[0xe];
9720  	u8         pddr[0x1];
9721  	u8         reserved_at_4f[0xd];
9722  
9723  	u8         pplm[0x1];
9724  	u8         port_access_reg_cap_mask_34_to_32[0x3];
9725  
9726  	u8         port_access_reg_cap_mask_31_to_13[0x13];
9727  	u8         pbmc[0x1];
9728  	u8         pptb[0x1];
9729  	u8         port_access_reg_cap_mask_10_to_09[0x2];
9730  	u8         ppcnt[0x1];
9731  	u8         port_access_reg_cap_mask_07_to_00[0x8];
9732  };
9733  
9734  struct mlx5_ifc_pcam_reg_bits {
9735  	u8         reserved_at_0[0x8];
9736  	u8         feature_group[0x8];
9737  	u8         reserved_at_10[0x8];
9738  	u8         access_reg_group[0x8];
9739  
9740  	u8         reserved_at_20[0x20];
9741  
9742  	union {
9743  		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9744  		u8         reserved_at_0[0x80];
9745  	} port_access_reg_cap_mask;
9746  
9747  	u8         reserved_at_c0[0x80];
9748  
9749  	union {
9750  		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9751  		u8         reserved_at_0[0x80];
9752  	} feature_cap_mask;
9753  
9754  	u8         reserved_at_1c0[0xc0];
9755  };
9756  
9757  struct mlx5_ifc_mcam_enhanced_features_bits {
9758  	u8         reserved_at_0[0x6e];
9759  	u8         pcie_status_and_power[0x1];
9760  	u8         reserved_at_111[0x10];
9761  	u8         pcie_performance_group[0x1];
9762  };
9763  
9764  struct mlx5_ifc_mcam_access_reg_bits {
9765  	u8         reserved_at_0[0x1c];
9766  	u8         mcda[0x1];
9767  	u8         mcc[0x1];
9768  	u8         mcqi[0x1];
9769  	u8         reserved_at_1f[0x1];
9770  
9771  	u8         regs_95_to_64[0x20];
9772  	u8         regs_63_to_32[0x20];
9773  	u8         regs_31_to_0[0x20];
9774  };
9775  
9776  struct mlx5_ifc_mcam_reg_bits {
9777  	u8         reserved_at_0[0x8];
9778  	u8         feature_group[0x8];
9779  	u8         reserved_at_10[0x8];
9780  	u8         access_reg_group[0x8];
9781  
9782  	u8         reserved_at_20[0x20];
9783  
9784  	union {
9785  		struct mlx5_ifc_mcam_access_reg_bits access_regs;
9786  		u8         reserved_at_0[0x80];
9787  	} mng_access_reg_cap_mask;
9788  
9789  	u8         reserved_at_c0[0x80];
9790  
9791  	union {
9792  		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9793  		u8         reserved_at_0[0x80];
9794  	} mng_feature_cap_mask;
9795  
9796  	u8         reserved_at_1c0[0x80];
9797  };
9798  
9799  struct mlx5_ifc_pcap_reg_bits {
9800  	u8         reserved_0[0x8];
9801  	u8         local_port[0x8];
9802  	u8         reserved_1[0x10];
9803  
9804  	u8         port_capability_mask[4][0x20];
9805  };
9806  
9807  struct mlx5_ifc_pbmc_reg_bits {
9808  	u8         reserved_at_0[0x8];
9809  	u8         local_port[0x8];
9810  	u8         reserved_at_10[0x10];
9811  
9812  	u8         xoff_timer_value[0x10];
9813  	u8         xoff_refresh[0x10];
9814  
9815  	u8         reserved_at_40[0x9];
9816  	u8         fullness_threshold[0x7];
9817  	u8         port_buffer_size[0x10];
9818  
9819  	struct mlx5_ifc_bufferx_reg_bits buffer[10];
9820  
9821  	u8         reserved_at_2e0[0x80];
9822  };
9823  
9824  struct mlx5_ifc_paos_reg_bits {
9825  	u8         swid[0x8];
9826  	u8         local_port[0x8];
9827  	u8         reserved_0[0x4];
9828  	u8         admin_status[0x4];
9829  	u8         reserved_1[0x4];
9830  	u8         oper_status[0x4];
9831  
9832  	u8         ase[0x1];
9833  	u8         ee[0x1];
9834  	u8         reserved_2[0x1c];
9835  	u8         e[0x2];
9836  
9837  	u8         reserved_3[0x40];
9838  };
9839  
9840  struct mlx5_ifc_pamp_reg_bits {
9841  	u8         reserved_0[0x8];
9842  	u8         opamp_group[0x8];
9843  	u8         reserved_1[0xc];
9844  	u8         opamp_group_type[0x4];
9845  
9846  	u8         start_index[0x10];
9847  	u8         reserved_2[0x4];
9848  	u8         num_of_indices[0xc];
9849  
9850  	u8         index_data[18][0x10];
9851  };
9852  
9853  struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
9854  	u8         llr_rx_cells_high[0x20];
9855  
9856  	u8         llr_rx_cells_low[0x20];
9857  
9858  	u8         llr_rx_error_high[0x20];
9859  
9860  	u8         llr_rx_error_low[0x20];
9861  
9862  	u8         llr_rx_crc_error_high[0x20];
9863  
9864  	u8         llr_rx_crc_error_low[0x20];
9865  
9866  	u8         llr_tx_cells_high[0x20];
9867  
9868  	u8         llr_tx_cells_low[0x20];
9869  
9870  	u8         llr_tx_ret_cells_high[0x20];
9871  
9872  	u8         llr_tx_ret_cells_low[0x20];
9873  
9874  	u8         llr_tx_ret_events_high[0x20];
9875  
9876  	u8         llr_tx_ret_events_low[0x20];
9877  
9878  	u8         reserved_0[0x640];
9879  };
9880  
9881  struct mlx5_ifc_mtmp_reg_bits {
9882  	u8         i[0x1];
9883  	u8         reserved_at_1[0x18];
9884  	u8         sensor_index[0x7];
9885  
9886  	u8         reserved_at_20[0x10];
9887  	u8         temperature[0x10];
9888  
9889  	u8         mte[0x1];
9890  	u8         mtr[0x1];
9891  	u8         reserved_at_42[0x0e];
9892  	u8         max_temperature[0x10];
9893  
9894  	u8         tee[0x2];
9895  	u8         reserved_at_62[0x0e];
9896  	u8         temperature_threshold_hi[0x10];
9897  
9898  	u8         reserved_at_80[0x10];
9899  	u8         temperature_threshold_lo[0x10];
9900  
9901  	u8         reserved_at_100[0x20];
9902  
9903  	u8         sensor_name[0x40];
9904  };
9905  
9906  struct mlx5_ifc_lane_2_module_mapping_bits {
9907  	u8         reserved_0[0x6];
9908  	u8         rx_lane[0x2];
9909  	u8         reserved_1[0x6];
9910  	u8         tx_lane[0x2];
9911  	u8         reserved_2[0x8];
9912  	u8         module[0x8];
9913  };
9914  
9915  struct mlx5_ifc_eth_per_traffic_class_layout_bits {
9916  	u8         transmit_queue_high[0x20];
9917  
9918  	u8         transmit_queue_low[0x20];
9919  
9920  	u8         reserved_0[0x780];
9921  };
9922  
9923  struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
9924  	u8         no_buffer_discard_uc_high[0x20];
9925  
9926  	u8         no_buffer_discard_uc_low[0x20];
9927  
9928  	u8         wred_discard_high[0x20];
9929  
9930  	u8         wred_discard_low[0x20];
9931  
9932  	u8         reserved_0[0x740];
9933  };
9934  
9935  struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
9936  	u8         rx_octets_high[0x20];
9937  
9938  	u8         rx_octets_low[0x20];
9939  
9940  	u8         reserved_0[0xc0];
9941  
9942  	u8         rx_frames_high[0x20];
9943  
9944  	u8         rx_frames_low[0x20];
9945  
9946  	u8         tx_octets_high[0x20];
9947  
9948  	u8         tx_octets_low[0x20];
9949  
9950  	u8         reserved_1[0xc0];
9951  
9952  	u8         tx_frames_high[0x20];
9953  
9954  	u8         tx_frames_low[0x20];
9955  
9956  	u8         rx_pause_high[0x20];
9957  
9958  	u8         rx_pause_low[0x20];
9959  
9960  	u8         rx_pause_duration_high[0x20];
9961  
9962  	u8         rx_pause_duration_low[0x20];
9963  
9964  	u8         tx_pause_high[0x20];
9965  
9966  	u8         tx_pause_low[0x20];
9967  
9968  	u8         tx_pause_duration_high[0x20];
9969  
9970  	u8         tx_pause_duration_low[0x20];
9971  
9972  	u8         rx_pause_transition_high[0x20];
9973  
9974  	u8         rx_pause_transition_low[0x20];
9975  
9976  	u8         rx_discards_high[0x20];
9977  
9978  	u8         rx_discards_low[0x20];
9979  
9980  	u8         device_stall_minor_watermark_cnt_high[0x20];
9981  
9982  	u8         device_stall_minor_watermark_cnt_low[0x20];
9983  
9984  	u8         device_stall_critical_watermark_cnt_high[0x20];
9985  
9986  	u8         device_stall_critical_watermark_cnt_low[0x20];
9987  
9988  	u8         reserved_2[0x340];
9989  };
9990  
9991  struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
9992  	u8         port_transmit_wait_high[0x20];
9993  
9994  	u8         port_transmit_wait_low[0x20];
9995  
9996  	u8         ecn_marked_high[0x20];
9997  
9998  	u8         ecn_marked_low[0x20];
9999  
10000  	u8         no_buffer_discard_mc_high[0x20];
10001  
10002  	u8         no_buffer_discard_mc_low[0x20];
10003  
10004  	u8         rx_ebp_high[0x20];
10005  
10006  	u8         rx_ebp_low[0x20];
10007  
10008  	u8         tx_ebp_high[0x20];
10009  
10010  	u8         tx_ebp_low[0x20];
10011  
10012          u8         rx_buffer_almost_full_high[0x20];
10013  
10014          u8         rx_buffer_almost_full_low[0x20];
10015  
10016          u8         rx_buffer_full_high[0x20];
10017  
10018          u8         rx_buffer_full_low[0x20];
10019  
10020          u8         rx_icrc_encapsulated_high[0x20];
10021  
10022          u8         rx_icrc_encapsulated_low[0x20];
10023  
10024  	u8         reserved_0[0x80];
10025  
10026          u8         tx_stats_pkts64octets_high[0x20];
10027  
10028          u8         tx_stats_pkts64octets_low[0x20];
10029  
10030          u8         tx_stats_pkts65to127octets_high[0x20];
10031  
10032          u8         tx_stats_pkts65to127octets_low[0x20];
10033  
10034          u8         tx_stats_pkts128to255octets_high[0x20];
10035  
10036          u8         tx_stats_pkts128to255octets_low[0x20];
10037  
10038          u8         tx_stats_pkts256to511octets_high[0x20];
10039  
10040          u8         tx_stats_pkts256to511octets_low[0x20];
10041  
10042          u8         tx_stats_pkts512to1023octets_high[0x20];
10043  
10044          u8         tx_stats_pkts512to1023octets_low[0x20];
10045  
10046          u8         tx_stats_pkts1024to1518octets_high[0x20];
10047  
10048          u8         tx_stats_pkts1024to1518octets_low[0x20];
10049  
10050          u8         tx_stats_pkts1519to2047octets_high[0x20];
10051  
10052          u8         tx_stats_pkts1519to2047octets_low[0x20];
10053  
10054          u8         tx_stats_pkts2048to4095octets_high[0x20];
10055  
10056          u8         tx_stats_pkts2048to4095octets_low[0x20];
10057  
10058          u8         tx_stats_pkts4096to8191octets_high[0x20];
10059  
10060          u8         tx_stats_pkts4096to8191octets_low[0x20];
10061  
10062          u8         tx_stats_pkts8192to10239octets_high[0x20];
10063  
10064          u8         tx_stats_pkts8192to10239octets_low[0x20];
10065  
10066  	u8         reserved_1[0x2C0];
10067  };
10068  
10069  struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
10070  	u8         a_frames_transmitted_ok_high[0x20];
10071  
10072  	u8         a_frames_transmitted_ok_low[0x20];
10073  
10074  	u8         a_frames_received_ok_high[0x20];
10075  
10076  	u8         a_frames_received_ok_low[0x20];
10077  
10078  	u8         a_frame_check_sequence_errors_high[0x20];
10079  
10080  	u8         a_frame_check_sequence_errors_low[0x20];
10081  
10082  	u8         a_alignment_errors_high[0x20];
10083  
10084  	u8         a_alignment_errors_low[0x20];
10085  
10086  	u8         a_octets_transmitted_ok_high[0x20];
10087  
10088  	u8         a_octets_transmitted_ok_low[0x20];
10089  
10090  	u8         a_octets_received_ok_high[0x20];
10091  
10092  	u8         a_octets_received_ok_low[0x20];
10093  
10094  	u8         a_multicast_frames_xmitted_ok_high[0x20];
10095  
10096  	u8         a_multicast_frames_xmitted_ok_low[0x20];
10097  
10098  	u8         a_broadcast_frames_xmitted_ok_high[0x20];
10099  
10100  	u8         a_broadcast_frames_xmitted_ok_low[0x20];
10101  
10102  	u8         a_multicast_frames_received_ok_high[0x20];
10103  
10104  	u8         a_multicast_frames_received_ok_low[0x20];
10105  
10106  	u8         a_broadcast_frames_recieved_ok_high[0x20];
10107  
10108  	u8         a_broadcast_frames_recieved_ok_low[0x20];
10109  
10110  	u8         a_in_range_length_errors_high[0x20];
10111  
10112  	u8         a_in_range_length_errors_low[0x20];
10113  
10114  	u8         a_out_of_range_length_field_high[0x20];
10115  
10116  	u8         a_out_of_range_length_field_low[0x20];
10117  
10118  	u8         a_frame_too_long_errors_high[0x20];
10119  
10120  	u8         a_frame_too_long_errors_low[0x20];
10121  
10122  	u8         a_symbol_error_during_carrier_high[0x20];
10123  
10124  	u8         a_symbol_error_during_carrier_low[0x20];
10125  
10126  	u8         a_mac_control_frames_transmitted_high[0x20];
10127  
10128  	u8         a_mac_control_frames_transmitted_low[0x20];
10129  
10130  	u8         a_mac_control_frames_received_high[0x20];
10131  
10132  	u8         a_mac_control_frames_received_low[0x20];
10133  
10134  	u8         a_unsupported_opcodes_received_high[0x20];
10135  
10136  	u8         a_unsupported_opcodes_received_low[0x20];
10137  
10138  	u8         a_pause_mac_ctrl_frames_received_high[0x20];
10139  
10140  	u8         a_pause_mac_ctrl_frames_received_low[0x20];
10141  
10142  	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
10143  
10144  	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
10145  
10146  	u8         reserved_0[0x300];
10147  };
10148  
10149  struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
10150  	u8         dot3stats_alignment_errors_high[0x20];
10151  
10152  	u8         dot3stats_alignment_errors_low[0x20];
10153  
10154  	u8         dot3stats_fcs_errors_high[0x20];
10155  
10156  	u8         dot3stats_fcs_errors_low[0x20];
10157  
10158  	u8         dot3stats_single_collision_frames_high[0x20];
10159  
10160  	u8         dot3stats_single_collision_frames_low[0x20];
10161  
10162  	u8         dot3stats_multiple_collision_frames_high[0x20];
10163  
10164  	u8         dot3stats_multiple_collision_frames_low[0x20];
10165  
10166  	u8         dot3stats_sqe_test_errors_high[0x20];
10167  
10168  	u8         dot3stats_sqe_test_errors_low[0x20];
10169  
10170  	u8         dot3stats_deferred_transmissions_high[0x20];
10171  
10172  	u8         dot3stats_deferred_transmissions_low[0x20];
10173  
10174  	u8         dot3stats_late_collisions_high[0x20];
10175  
10176  	u8         dot3stats_late_collisions_low[0x20];
10177  
10178  	u8         dot3stats_excessive_collisions_high[0x20];
10179  
10180  	u8         dot3stats_excessive_collisions_low[0x20];
10181  
10182  	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
10183  
10184  	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
10185  
10186  	u8         dot3stats_carrier_sense_errors_high[0x20];
10187  
10188  	u8         dot3stats_carrier_sense_errors_low[0x20];
10189  
10190  	u8         dot3stats_frame_too_longs_high[0x20];
10191  
10192  	u8         dot3stats_frame_too_longs_low[0x20];
10193  
10194  	u8         dot3stats_internal_mac_receive_errors_high[0x20];
10195  
10196  	u8         dot3stats_internal_mac_receive_errors_low[0x20];
10197  
10198  	u8         dot3stats_symbol_errors_high[0x20];
10199  
10200  	u8         dot3stats_symbol_errors_low[0x20];
10201  
10202  	u8         dot3control_in_unknown_opcodes_high[0x20];
10203  
10204  	u8         dot3control_in_unknown_opcodes_low[0x20];
10205  
10206  	u8         dot3in_pause_frames_high[0x20];
10207  
10208  	u8         dot3in_pause_frames_low[0x20];
10209  
10210  	u8         dot3out_pause_frames_high[0x20];
10211  
10212  	u8         dot3out_pause_frames_low[0x20];
10213  
10214  	u8         reserved_0[0x3c0];
10215  };
10216  
10217  struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
10218  	u8         if_in_octets_high[0x20];
10219  
10220  	u8         if_in_octets_low[0x20];
10221  
10222  	u8         if_in_ucast_pkts_high[0x20];
10223  
10224  	u8         if_in_ucast_pkts_low[0x20];
10225  
10226  	u8         if_in_discards_high[0x20];
10227  
10228  	u8         if_in_discards_low[0x20];
10229  
10230  	u8         if_in_errors_high[0x20];
10231  
10232  	u8         if_in_errors_low[0x20];
10233  
10234  	u8         if_in_unknown_protos_high[0x20];
10235  
10236  	u8         if_in_unknown_protos_low[0x20];
10237  
10238  	u8         if_out_octets_high[0x20];
10239  
10240  	u8         if_out_octets_low[0x20];
10241  
10242  	u8         if_out_ucast_pkts_high[0x20];
10243  
10244  	u8         if_out_ucast_pkts_low[0x20];
10245  
10246  	u8         if_out_discards_high[0x20];
10247  
10248  	u8         if_out_discards_low[0x20];
10249  
10250  	u8         if_out_errors_high[0x20];
10251  
10252  	u8         if_out_errors_low[0x20];
10253  
10254  	u8         if_in_multicast_pkts_high[0x20];
10255  
10256  	u8         if_in_multicast_pkts_low[0x20];
10257  
10258  	u8         if_in_broadcast_pkts_high[0x20];
10259  
10260  	u8         if_in_broadcast_pkts_low[0x20];
10261  
10262  	u8         if_out_multicast_pkts_high[0x20];
10263  
10264  	u8         if_out_multicast_pkts_low[0x20];
10265  
10266  	u8         if_out_broadcast_pkts_high[0x20];
10267  
10268  	u8         if_out_broadcast_pkts_low[0x20];
10269  
10270  	u8         reserved_0[0x480];
10271  };
10272  
10273  struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
10274  	u8         ether_stats_drop_events_high[0x20];
10275  
10276  	u8         ether_stats_drop_events_low[0x20];
10277  
10278  	u8         ether_stats_octets_high[0x20];
10279  
10280  	u8         ether_stats_octets_low[0x20];
10281  
10282  	u8         ether_stats_pkts_high[0x20];
10283  
10284  	u8         ether_stats_pkts_low[0x20];
10285  
10286  	u8         ether_stats_broadcast_pkts_high[0x20];
10287  
10288  	u8         ether_stats_broadcast_pkts_low[0x20];
10289  
10290  	u8         ether_stats_multicast_pkts_high[0x20];
10291  
10292  	u8         ether_stats_multicast_pkts_low[0x20];
10293  
10294  	u8         ether_stats_crc_align_errors_high[0x20];
10295  
10296  	u8         ether_stats_crc_align_errors_low[0x20];
10297  
10298  	u8         ether_stats_undersize_pkts_high[0x20];
10299  
10300  	u8         ether_stats_undersize_pkts_low[0x20];
10301  
10302  	u8         ether_stats_oversize_pkts_high[0x20];
10303  
10304  	u8         ether_stats_oversize_pkts_low[0x20];
10305  
10306  	u8         ether_stats_fragments_high[0x20];
10307  
10308  	u8         ether_stats_fragments_low[0x20];
10309  
10310  	u8         ether_stats_jabbers_high[0x20];
10311  
10312  	u8         ether_stats_jabbers_low[0x20];
10313  
10314  	u8         ether_stats_collisions_high[0x20];
10315  
10316  	u8         ether_stats_collisions_low[0x20];
10317  
10318  	u8         ether_stats_pkts64octets_high[0x20];
10319  
10320  	u8         ether_stats_pkts64octets_low[0x20];
10321  
10322  	u8         ether_stats_pkts65to127octets_high[0x20];
10323  
10324  	u8         ether_stats_pkts65to127octets_low[0x20];
10325  
10326  	u8         ether_stats_pkts128to255octets_high[0x20];
10327  
10328  	u8         ether_stats_pkts128to255octets_low[0x20];
10329  
10330  	u8         ether_stats_pkts256to511octets_high[0x20];
10331  
10332  	u8         ether_stats_pkts256to511octets_low[0x20];
10333  
10334  	u8         ether_stats_pkts512to1023octets_high[0x20];
10335  
10336  	u8         ether_stats_pkts512to1023octets_low[0x20];
10337  
10338  	u8         ether_stats_pkts1024to1518octets_high[0x20];
10339  
10340  	u8         ether_stats_pkts1024to1518octets_low[0x20];
10341  
10342  	u8         ether_stats_pkts1519to2047octets_high[0x20];
10343  
10344  	u8         ether_stats_pkts1519to2047octets_low[0x20];
10345  
10346  	u8         ether_stats_pkts2048to4095octets_high[0x20];
10347  
10348  	u8         ether_stats_pkts2048to4095octets_low[0x20];
10349  
10350  	u8         ether_stats_pkts4096to8191octets_high[0x20];
10351  
10352  	u8         ether_stats_pkts4096to8191octets_low[0x20];
10353  
10354  	u8         ether_stats_pkts8192to10239octets_high[0x20];
10355  
10356  	u8         ether_stats_pkts8192to10239octets_low[0x20];
10357  
10358  	u8         reserved_0[0x280];
10359  };
10360  
10361  struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
10362  	u8         symbol_error_counter[0x10];
10363  	u8         link_error_recovery_counter[0x8];
10364  	u8         link_downed_counter[0x8];
10365  
10366  	u8         port_rcv_errors[0x10];
10367  	u8         port_rcv_remote_physical_errors[0x10];
10368  
10369  	u8         port_rcv_switch_relay_errors[0x10];
10370  	u8         port_xmit_discards[0x10];
10371  
10372  	u8         port_xmit_constraint_errors[0x8];
10373  	u8         port_rcv_constraint_errors[0x8];
10374  	u8         reserved_0[0x8];
10375  	u8         local_link_integrity_errors[0x4];
10376  	u8         excessive_buffer_overrun_errors[0x4];
10377  
10378  	u8         reserved_1[0x10];
10379  	u8         vl_15_dropped[0x10];
10380  
10381  	u8         port_xmit_data[0x20];
10382  
10383  	u8         port_rcv_data[0x20];
10384  
10385  	u8         port_xmit_pkts[0x20];
10386  
10387  	u8         port_rcv_pkts[0x20];
10388  
10389  	u8         port_xmit_wait[0x20];
10390  
10391  	u8         reserved_2[0x680];
10392  };
10393  
10394  struct mlx5_ifc_trc_tlb_reg_bits {
10395  	u8         reserved_0[0x80];
10396  
10397  	u8         tlb_addr[0][0x40];
10398  };
10399  
10400  struct mlx5_ifc_trc_read_fifo_reg_bits {
10401  	u8         reserved_0[0x10];
10402  	u8         requested_event_num[0x10];
10403  
10404  	u8         reserved_1[0x20];
10405  
10406  	u8         reserved_2[0x10];
10407  	u8         acual_event_num[0x10];
10408  
10409  	u8         reserved_3[0x20];
10410  
10411  	u8         event[0][0x40];
10412  };
10413  
10414  struct mlx5_ifc_trc_lock_reg_bits {
10415  	u8         reserved_0[0x1f];
10416  	u8         lock[0x1];
10417  
10418  	u8         reserved_1[0x60];
10419  };
10420  
10421  struct mlx5_ifc_trc_filter_reg_bits {
10422  	u8         status[0x1];
10423  	u8         reserved_0[0xf];
10424  	u8         filter_index[0x10];
10425  
10426  	u8         reserved_1[0x20];
10427  
10428  	u8         filter_val[0x20];
10429  
10430  	u8         reserved_2[0x1a0];
10431  };
10432  
10433  struct mlx5_ifc_trc_event_reg_bits {
10434  	u8         status[0x1];
10435  	u8         reserved_0[0xf];
10436  	u8         event_index[0x10];
10437  
10438  	u8         reserved_1[0x20];
10439  
10440  	u8         event_id[0x20];
10441  
10442  	u8         event_selector_val[0x10];
10443  	u8         event_selector_size[0x10];
10444  
10445  	u8         reserved_2[0x180];
10446  };
10447  
10448  struct mlx5_ifc_trc_conf_reg_bits {
10449  	u8         limit_en[0x1];
10450  	u8         reserved_0[0x3];
10451  	u8         dump_mode[0x4];
10452  	u8         reserved_1[0x15];
10453  	u8         state[0x3];
10454  
10455  	u8         reserved_2[0x20];
10456  
10457  	u8         limit_event_index[0x20];
10458  
10459  	u8         mkey[0x20];
10460  
10461  	u8         fifo_ready_ev_num[0x20];
10462  
10463  	u8         reserved_3[0x160];
10464  };
10465  
10466  struct mlx5_ifc_trc_cap_reg_bits {
10467  	u8         reserved_0[0x18];
10468  	u8         dump_mode[0x8];
10469  
10470  	u8         reserved_1[0x20];
10471  
10472  	u8         num_of_events[0x10];
10473  	u8         num_of_filters[0x10];
10474  
10475  	u8         fifo_size[0x20];
10476  
10477  	u8         tlb_size[0x10];
10478  	u8         event_size[0x10];
10479  
10480  	u8         reserved_2[0x160];
10481  };
10482  
10483  struct mlx5_ifc_set_node_in_bits {
10484  	u8         node_description[64][0x8];
10485  };
10486  
10487  struct mlx5_ifc_register_power_settings_bits {
10488  	u8         reserved_0[0x18];
10489  	u8         power_settings_level[0x8];
10490  
10491  	u8         reserved_1[0x60];
10492  };
10493  
10494  struct mlx5_ifc_register_host_endianess_bits {
10495  	u8         he[0x1];
10496  	u8         reserved_0[0x1f];
10497  
10498  	u8         reserved_1[0x60];
10499  };
10500  
10501  struct mlx5_ifc_register_diag_buffer_ctrl_bits {
10502  	u8         physical_address[0x40];
10503  };
10504  
10505  struct mlx5_ifc_qtct_reg_bits {
10506  	u8         operation_type[0x2];
10507  	u8         cap_local_admin[0x1];
10508  	u8         cap_remote_admin[0x1];
10509  	u8         reserved_0[0x4];
10510  	u8         port_number[0x8];
10511  	u8         reserved_1[0xd];
10512  	u8         prio[0x3];
10513  
10514  	u8         reserved_2[0x1d];
10515  	u8         tclass[0x3];
10516  };
10517  
10518  struct mlx5_ifc_qpdp_reg_bits {
10519  	u8         reserved_0[0x8];
10520  	u8         port_number[0x8];
10521  	u8         reserved_1[0x10];
10522  
10523  	u8         reserved_2[0x1d];
10524  	u8         pprio[0x3];
10525  };
10526  
10527  struct mlx5_ifc_port_info_ro_fields_param_bits {
10528  	u8         reserved_0[0x8];
10529  	u8         port[0x8];
10530  	u8         max_gid[0x10];
10531  
10532  	u8         reserved_1[0x20];
10533  
10534  	u8         port_guid[0x40];
10535  };
10536  
10537  struct mlx5_ifc_nvqc_reg_bits {
10538  	u8         type[0x20];
10539  
10540  	u8         reserved_0[0x18];
10541  	u8         version[0x4];
10542  	u8         reserved_1[0x2];
10543  	u8         support_wr[0x1];
10544  	u8         support_rd[0x1];
10545  };
10546  
10547  struct mlx5_ifc_nvia_reg_bits {
10548  	u8         reserved_0[0x1d];
10549  	u8         target[0x3];
10550  
10551  	u8         reserved_1[0x20];
10552  };
10553  
10554  struct mlx5_ifc_nvdi_reg_bits {
10555  	struct mlx5_ifc_config_item_bits configuration_item_header;
10556  };
10557  
10558  struct mlx5_ifc_nvda_reg_bits {
10559  	struct mlx5_ifc_config_item_bits configuration_item_header;
10560  
10561  	u8         configuration_item_data[0x20];
10562  };
10563  
10564  struct mlx5_ifc_node_info_ro_fields_param_bits {
10565  	u8         system_image_guid[0x40];
10566  
10567  	u8         reserved_0[0x40];
10568  
10569  	u8         node_guid[0x40];
10570  
10571  	u8         reserved_1[0x10];
10572  	u8         max_pkey[0x10];
10573  
10574  	u8         reserved_2[0x20];
10575  };
10576  
10577  struct mlx5_ifc_ets_tcn_config_reg_bits {
10578  	u8         g[0x1];
10579  	u8         b[0x1];
10580  	u8         r[0x1];
10581  	u8         reserved_0[0x9];
10582  	u8         group[0x4];
10583  	u8         reserved_1[0x9];
10584  	u8         bw_allocation[0x7];
10585  
10586  	u8         reserved_2[0xc];
10587  	u8         max_bw_units[0x4];
10588  	u8         reserved_3[0x8];
10589  	u8         max_bw_value[0x8];
10590  };
10591  
10592  struct mlx5_ifc_ets_global_config_reg_bits {
10593  	u8         reserved_0[0x2];
10594  	u8         r[0x1];
10595  	u8         reserved_1[0x1d];
10596  
10597  	u8         reserved_2[0xc];
10598  	u8         max_bw_units[0x4];
10599  	u8         reserved_3[0x8];
10600  	u8         max_bw_value[0x8];
10601  };
10602  
10603  struct mlx5_ifc_qetc_reg_bits {
10604  	u8                                         reserved_at_0[0x8];
10605  	u8                                         port_number[0x8];
10606  	u8                                         reserved_at_10[0x30];
10607  
10608  	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
10609  	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10610  };
10611  
10612  struct mlx5_ifc_nodnic_mac_filters_bits {
10613  	struct mlx5_ifc_mac_address_layout_bits mac_filter0;
10614  
10615  	struct mlx5_ifc_mac_address_layout_bits mac_filter1;
10616  
10617  	struct mlx5_ifc_mac_address_layout_bits mac_filter2;
10618  
10619  	struct mlx5_ifc_mac_address_layout_bits mac_filter3;
10620  
10621  	struct mlx5_ifc_mac_address_layout_bits mac_filter4;
10622  
10623  	u8         reserved_0[0xc0];
10624  };
10625  
10626  struct mlx5_ifc_nodnic_gid_filters_bits {
10627  	u8         mgid_filter0[16][0x8];
10628  
10629  	u8         mgid_filter1[16][0x8];
10630  
10631  	u8         mgid_filter2[16][0x8];
10632  
10633  	u8         mgid_filter3[16][0x8];
10634  };
10635  
10636  enum {
10637  	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
10638  	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
10639  };
10640  
10641  enum {
10642  	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
10643  	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
10644  };
10645  
10646  struct mlx5_ifc_nodnic_config_reg_bits {
10647  	u8         no_dram_nic_revision[0x8];
10648  	u8         hardware_format[0x8];
10649  	u8         support_receive_filter[0x1];
10650  	u8         support_promisc_filter[0x1];
10651  	u8         support_promisc_multicast_filter[0x1];
10652  	u8         reserved_0[0x2];
10653  	u8         log_working_buffer_size[0x3];
10654  	u8         log_pkey_table_size[0x4];
10655  	u8         reserved_1[0x3];
10656  	u8         num_ports[0x1];
10657  
10658  	u8         reserved_2[0x2];
10659  	u8         log_max_ring_size[0x6];
10660  	u8         reserved_3[0x18];
10661  
10662  	u8         lkey[0x20];
10663  
10664  	u8         cqe_format[0x4];
10665  	u8         reserved_4[0x1c];
10666  
10667  	u8         node_guid[0x40];
10668  
10669  	u8         reserved_5[0x740];
10670  
10671  	struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
10672  
10673  	struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
10674  };
10675  
10676  struct mlx5_ifc_vlan_layout_bits {
10677  	u8         reserved_0[0x14];
10678  	u8         vlan[0xc];
10679  
10680  	u8         reserved_1[0x20];
10681  };
10682  
10683  struct mlx5_ifc_umr_pointer_desc_argument_bits {
10684  	u8         reserved_0[0x20];
10685  
10686  	u8         mkey[0x20];
10687  
10688  	u8         addressh_63_32[0x20];
10689  
10690  	u8         addressl_31_0[0x20];
10691  };
10692  
10693  struct mlx5_ifc_ud_adrs_vector_bits {
10694  	u8         dc_key[0x40];
10695  
10696  	u8         ext[0x1];
10697  	u8         reserved_0[0x7];
10698  	u8         destination_qp_dct[0x18];
10699  
10700  	u8         static_rate[0x4];
10701  	u8         sl_eth_prio[0x4];
10702  	u8         fl[0x1];
10703  	u8         mlid[0x7];
10704  	u8         rlid_udp_sport[0x10];
10705  
10706  	u8         reserved_1[0x20];
10707  
10708  	u8         rmac_47_16[0x20];
10709  
10710  	u8         rmac_15_0[0x10];
10711  	u8         tclass[0x8];
10712  	u8         hop_limit[0x8];
10713  
10714  	u8         reserved_2[0x1];
10715  	u8         grh[0x1];
10716  	u8         reserved_3[0x2];
10717  	u8         src_addr_index[0x8];
10718  	u8         flow_label[0x14];
10719  
10720  	u8         rgid_rip[16][0x8];
10721  };
10722  
10723  struct mlx5_ifc_port_module_event_bits {
10724  	u8         reserved_0[0x8];
10725  	u8         module[0x8];
10726  	u8         reserved_1[0xc];
10727  	u8         module_status[0x4];
10728  
10729  	u8         reserved_2[0x14];
10730  	u8         error_type[0x4];
10731  	u8         reserved_3[0x8];
10732  
10733  	u8         reserved_4[0xa0];
10734  };
10735  
10736  struct mlx5_ifc_icmd_control_bits {
10737  	u8         opcode[0x10];
10738  	u8         status[0x8];
10739  	u8         reserved_0[0x7];
10740  	u8         busy[0x1];
10741  };
10742  
10743  struct mlx5_ifc_eqe_bits {
10744  	u8         reserved_0[0x8];
10745  	u8         event_type[0x8];
10746  	u8         reserved_1[0x8];
10747  	u8         event_sub_type[0x8];
10748  
10749  	u8         reserved_2[0xe0];
10750  
10751  	union mlx5_ifc_event_auto_bits event_data;
10752  
10753  	u8         reserved_3[0x10];
10754  	u8         signature[0x8];
10755  	u8         reserved_4[0x7];
10756  	u8         owner[0x1];
10757  };
10758  
10759  enum {
10760  	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10761  };
10762  
10763  struct mlx5_ifc_cmd_queue_entry_bits {
10764  	u8         type[0x8];
10765  	u8         reserved_0[0x18];
10766  
10767  	u8         input_length[0x20];
10768  
10769  	u8         input_mailbox_pointer_63_32[0x20];
10770  
10771  	u8         input_mailbox_pointer_31_9[0x17];
10772  	u8         reserved_1[0x9];
10773  
10774  	u8         command_input_inline_data[16][0x8];
10775  
10776  	u8         command_output_inline_data[16][0x8];
10777  
10778  	u8         output_mailbox_pointer_63_32[0x20];
10779  
10780  	u8         output_mailbox_pointer_31_9[0x17];
10781  	u8         reserved_2[0x9];
10782  
10783  	u8         output_length[0x20];
10784  
10785  	u8         token[0x8];
10786  	u8         signature[0x8];
10787  	u8         reserved_3[0x8];
10788  	u8         status[0x7];
10789  	u8         ownership[0x1];
10790  };
10791  
10792  struct mlx5_ifc_cmd_out_bits {
10793  	u8         status[0x8];
10794  	u8         reserved_0[0x18];
10795  
10796  	u8         syndrome[0x20];
10797  
10798  	u8         command_output[0x20];
10799  };
10800  
10801  struct mlx5_ifc_cmd_in_bits {
10802  	u8         opcode[0x10];
10803  	u8         reserved_0[0x10];
10804  
10805  	u8         reserved_1[0x10];
10806  	u8         op_mod[0x10];
10807  
10808  	u8         command[0][0x20];
10809  };
10810  
10811  struct mlx5_ifc_cmd_if_box_bits {
10812  	u8         mailbox_data[512][0x8];
10813  
10814  	u8         reserved_0[0x180];
10815  
10816  	u8         next_pointer_63_32[0x20];
10817  
10818  	u8         next_pointer_31_10[0x16];
10819  	u8         reserved_1[0xa];
10820  
10821  	u8         block_number[0x20];
10822  
10823  	u8         reserved_2[0x8];
10824  	u8         token[0x8];
10825  	u8         ctrl_signature[0x8];
10826  	u8         signature[0x8];
10827  };
10828  
10829  struct mlx5_ifc_mtt_bits {
10830  	u8         ptag_63_32[0x20];
10831  
10832  	u8         ptag_31_8[0x18];
10833  	u8         reserved_0[0x6];
10834  	u8         wr_en[0x1];
10835  	u8         rd_en[0x1];
10836  };
10837  
10838  struct mlx5_ifc_tls_progress_params_bits {
10839  	u8         valid[0x1];
10840  	u8         reserved_at_1[0x7];
10841  	u8         pd[0x18];
10842  
10843  	u8         next_record_tcp_sn[0x20];
10844  
10845  	u8         hw_resync_tcp_sn[0x20];
10846  
10847  	u8         record_tracker_state[0x2];
10848  	u8         auth_state[0x2];
10849  	u8         reserved_at_64[0x4];
10850  	u8         hw_offset_record_number[0x18];
10851  };
10852  
10853  struct mlx5_ifc_tls_static_params_bits {
10854  	u8         const_2[0x2];
10855  	u8         tls_version[0x4];
10856  	u8         const_1[0x2];
10857  	u8         reserved_at_8[0x14];
10858  	u8         encryption_standard[0x4];
10859  
10860  	u8         reserved_at_20[0x20];
10861  
10862  	u8         initial_record_number[0x40];
10863  
10864  	u8         resync_tcp_sn[0x20];
10865  
10866  	u8         gcm_iv[0x20];
10867  
10868  	u8         implicit_iv[0x40];
10869  
10870  	u8         reserved_at_100[0x8];
10871  	u8         dek_index[0x18];
10872  
10873  	u8         reserved_at_120[0xe0];
10874  };
10875  
10876  /* Vendor Specific Capabilities, VSC */
10877  enum {
10878  	MLX5_VSC_DOMAIN_ICMD			= 0x1,
10879  	MLX5_VSC_DOMAIN_PROTECTED_CRSPACE	= 0x6,
10880  	MLX5_VSC_DOMAIN_SCAN_CRSPACE		= 0x7,
10881  	MLX5_VSC_DOMAIN_SEMAPHORES		= 0xA,
10882  };
10883  
10884  struct mlx5_ifc_vendor_specific_cap_bits {
10885  	u8         type[0x8];
10886  	u8         length[0x8];
10887  	u8         next_pointer[0x8];
10888  	u8         capability_id[0x8];
10889  
10890  	u8         status[0x3];
10891  	u8         reserved_0[0xd];
10892  	u8         space[0x10];
10893  
10894  	u8         counter[0x20];
10895  
10896  	u8         semaphore[0x20];
10897  
10898  	u8         flag[0x1];
10899  	u8         reserved_1[0x1];
10900  	u8         address[0x1e];
10901  
10902  	u8         data[0x20];
10903  };
10904  
10905  struct mlx5_ifc_vsc_space_bits {
10906  	u8 status[0x3];
10907  	u8 reserved0[0xd];
10908  	u8 space[0x10];
10909  };
10910  
10911  struct mlx5_ifc_vsc_addr_bits {
10912  	u8 flag[0x1];
10913  	u8 reserved0[0x1];
10914  	u8 address[0x1e];
10915  };
10916  
10917  enum {
10918  	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10919  	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10920  	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10921  };
10922  
10923  enum {
10924  	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10925  	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10926  	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10927  };
10928  
10929  enum {
10930  	MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
10931  	MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
10932  	MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
10933  	MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
10934  	MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
10935  	MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
10936  	MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
10937  	MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
10938  	MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
10939  	MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
10940  	MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
10941  };
10942  
10943  struct mlx5_ifc_initial_seg_bits {
10944  	u8         fw_rev_minor[0x10];
10945  	u8         fw_rev_major[0x10];
10946  
10947  	u8         cmd_interface_rev[0x10];
10948  	u8         fw_rev_subminor[0x10];
10949  
10950  	u8         reserved_0[0x40];
10951  
10952  	u8         cmdq_phy_addr_63_32[0x20];
10953  
10954  	u8         cmdq_phy_addr_31_12[0x14];
10955  	u8         reserved_1[0x2];
10956  	u8         nic_interface[0x2];
10957  	u8         log_cmdq_size[0x4];
10958  	u8         log_cmdq_stride[0x4];
10959  
10960  	u8         command_doorbell_vector[0x20];
10961  
10962  	u8         reserved_2[0xf00];
10963  
10964  	u8         initializing[0x1];
10965  	u8         reserved_3[0x4];
10966  	u8         nic_interface_supported[0x3];
10967  	u8         reserved_4[0x18];
10968  
10969  	struct mlx5_ifc_health_buffer_bits health_buffer;
10970  
10971  	u8         no_dram_nic_offset[0x20];
10972  
10973  	u8         reserved_5[0x6de0];
10974  
10975  	u8         internal_timer_h[0x20];
10976  
10977  	u8         internal_timer_l[0x20];
10978  
10979  	u8         reserved_6[0x20];
10980  
10981  	u8         reserved_7[0x1f];
10982  	u8         clear_int[0x1];
10983  
10984  	u8         health_syndrome[0x8];
10985  	u8         health_counter[0x18];
10986  
10987  	u8         reserved_8[0x17fc0];
10988  };
10989  
10990  union mlx5_ifc_icmd_interface_document_bits {
10991  	struct mlx5_ifc_fw_version_bits fw_version;
10992  	struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
10993  	struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
10994  	struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
10995  	struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
10996  	struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
10997  	struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
10998  	struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
10999  	struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
11000  	struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
11001  	struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
11002  	struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
11003  	struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
11004  	struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
11005  	u8         reserved_0[0x42c0];
11006  };
11007  
11008  union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
11009  	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11010  	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11011  	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11012  	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11013  	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11014  	struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
11015  	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11016  	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11017  	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
11018  	struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
11019  	u8         reserved_0[0x7c0];
11020  };
11021  
11022  struct mlx5_ifc_ppcnt_reg_bits {
11023  	u8         swid[0x8];
11024  	u8         local_port[0x8];
11025  	u8         pnat[0x2];
11026  	u8         reserved_0[0x8];
11027  	u8         grp[0x6];
11028  
11029  	u8         clr[0x1];
11030  	u8         reserved_1[0x1c];
11031  	u8         prio_tc[0x3];
11032  
11033  	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
11034  };
11035  
11036  struct mlx5_ifc_pcie_lanes_counters_bits {
11037  	u8         life_time_counter_high[0x20];
11038  
11039  	u8         life_time_counter_low[0x20];
11040  
11041  	u8         error_counter_lane0[0x20];
11042  
11043  	u8         error_counter_lane1[0x20];
11044  
11045  	u8         error_counter_lane2[0x20];
11046  
11047  	u8         error_counter_lane3[0x20];
11048  
11049  	u8         error_counter_lane4[0x20];
11050  
11051  	u8         error_counter_lane5[0x20];
11052  
11053  	u8         error_counter_lane6[0x20];
11054  
11055  	u8         error_counter_lane7[0x20];
11056  
11057  	u8         error_counter_lane8[0x20];
11058  
11059  	u8         error_counter_lane9[0x20];
11060  
11061  	u8         error_counter_lane10[0x20];
11062  
11063  	u8         error_counter_lane11[0x20];
11064  
11065  	u8         error_counter_lane12[0x20];
11066  
11067  	u8         error_counter_lane13[0x20];
11068  
11069  	u8         error_counter_lane14[0x20];
11070  
11071  	u8         error_counter_lane15[0x20];
11072  
11073  	u8         reserved_at_240[0x580];
11074  };
11075  
11076  struct mlx5_ifc_pcie_lanes_counters_ext_bits {
11077  	u8         reserved_at_0[0x40];
11078  
11079  	u8         error_counter_lane0[0x20];
11080  
11081  	u8         error_counter_lane1[0x20];
11082  
11083  	u8         error_counter_lane2[0x20];
11084  
11085  	u8         error_counter_lane3[0x20];
11086  
11087  	u8         error_counter_lane4[0x20];
11088  
11089  	u8         error_counter_lane5[0x20];
11090  
11091  	u8         error_counter_lane6[0x20];
11092  
11093  	u8         error_counter_lane7[0x20];
11094  
11095  	u8         error_counter_lane8[0x20];
11096  
11097  	u8         error_counter_lane9[0x20];
11098  
11099  	u8         error_counter_lane10[0x20];
11100  
11101  	u8         error_counter_lane11[0x20];
11102  
11103  	u8         error_counter_lane12[0x20];
11104  
11105  	u8         error_counter_lane13[0x20];
11106  
11107  	u8         error_counter_lane14[0x20];
11108  
11109  	u8         error_counter_lane15[0x20];
11110  
11111  	u8         reserved_at_240[0x580];
11112  };
11113  
11114  struct mlx5_ifc_pcie_perf_counters_bits {
11115  	u8         life_time_counter_high[0x20];
11116  
11117  	u8         life_time_counter_low[0x20];
11118  
11119  	u8         rx_errors[0x20];
11120  
11121  	u8         tx_errors[0x20];
11122  
11123  	u8         l0_to_recovery_eieos[0x20];
11124  
11125  	u8         l0_to_recovery_ts[0x20];
11126  
11127  	u8         l0_to_recovery_framing[0x20];
11128  
11129  	u8         l0_to_recovery_retrain[0x20];
11130  
11131  	u8         crc_error_dllp[0x20];
11132  
11133  	u8         crc_error_tlp[0x20];
11134  
11135  	u8         tx_overflow_buffer_pkt[0x40];
11136  
11137  	u8         outbound_stalled_reads[0x20];
11138  
11139  	u8         outbound_stalled_writes[0x20];
11140  
11141  	u8         outbound_stalled_reads_events[0x20];
11142  
11143  	u8         outbound_stalled_writes_events[0x20];
11144  
11145  	u8         tx_overflow_buffer_marked_pkt[0x40];
11146  
11147  	u8         reserved_at_240[0x580];
11148  };
11149  
11150  struct mlx5_ifc_pcie_perf_counters_ext_bits {
11151  	u8         reserved_at_0[0x40];
11152  
11153  	u8         rx_errors[0x20];
11154  
11155  	u8         tx_errors[0x20];
11156  
11157  	u8         reserved_at_80[0xc0];
11158  
11159  	u8         tx_overflow_buffer_pkt[0x40];
11160  
11161  	u8         outbound_stalled_reads[0x20];
11162  
11163  	u8         outbound_stalled_writes[0x20];
11164  
11165  	u8         outbound_stalled_reads_events[0x20];
11166  
11167  	u8         outbound_stalled_writes_events[0x20];
11168  
11169  	u8         tx_overflow_buffer_marked_pkt[0x40];
11170  
11171  	u8         reserved_at_240[0x580];
11172  };
11173  
11174  struct mlx5_ifc_pcie_timers_states_bits {
11175  	u8         life_time_counter_high[0x20];
11176  
11177  	u8         life_time_counter_low[0x20];
11178  
11179  	u8         time_to_boot_image_start[0x20];
11180  
11181  	u8         time_to_link_image[0x20];
11182  
11183  	u8         calibration_time[0x20];
11184  
11185  	u8         time_to_first_perst[0x20];
11186  
11187  	u8         time_to_detect_state[0x20];
11188  
11189  	u8         time_to_l0[0x20];
11190  
11191  	u8         time_to_crs_en[0x20];
11192  
11193  	u8         time_to_plastic_image_start[0x20];
11194  
11195  	u8         time_to_iron_image_start[0x20];
11196  
11197  	u8         perst_handler[0x20];
11198  
11199  	u8         times_in_l1[0x20];
11200  
11201  	u8         times_in_l23[0x20];
11202  
11203  	u8         dl_down[0x20];
11204  
11205  	u8         config_cycle1usec[0x20];
11206  
11207  	u8         config_cycle2to7usec[0x20];
11208  
11209  	u8         config_cycle8to15usec[0x20];
11210  
11211  	u8         config_cycle16to63usec[0x20];
11212  
11213  	u8         config_cycle64usec[0x20];
11214  
11215  	u8         correctable_err_msg_sent[0x20];
11216  
11217  	u8         non_fatal_err_msg_sent[0x20];
11218  
11219  	u8         fatal_err_msg_sent[0x20];
11220  
11221  	u8         reserved_at_2e0[0x4e0];
11222  };
11223  
11224  struct mlx5_ifc_pcie_timers_states_ext_bits {
11225  	u8         reserved_at_0[0x40];
11226  
11227  	u8         time_to_boot_image_start[0x20];
11228  
11229  	u8         time_to_link_image[0x20];
11230  
11231  	u8         calibration_time[0x20];
11232  
11233  	u8         time_to_first_perst[0x20];
11234  
11235  	u8         time_to_detect_state[0x20];
11236  
11237  	u8         time_to_l0[0x20];
11238  
11239  	u8         time_to_crs_en[0x20];
11240  
11241  	u8         time_to_plastic_image_start[0x20];
11242  
11243  	u8         time_to_iron_image_start[0x20];
11244  
11245  	u8         perst_handler[0x20];
11246  
11247  	u8         times_in_l1[0x20];
11248  
11249  	u8         times_in_l23[0x20];
11250  
11251  	u8         dl_down[0x20];
11252  
11253  	u8         config_cycle1usec[0x20];
11254  
11255  	u8         config_cycle2to7usec[0x20];
11256  
11257  	u8         config_cycle8to15usec[0x20];
11258  
11259  	u8         config_cycle16to63usec[0x20];
11260  
11261  	u8         config_cycle64usec[0x20];
11262  
11263  	u8         correctable_err_msg_sent[0x20];
11264  
11265  	u8         non_fatal_err_msg_sent[0x20];
11266  
11267  	u8         fatal_err_msg_sent[0x20];
11268  
11269  	u8         reserved_at_2e0[0x4e0];
11270  };
11271  
11272  union mlx5_ifc_mpcnt_reg_counter_set_auto_bits {
11273  	struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters;
11274  	struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters;
11275  	struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states;
11276  	u8         reserved_at_0[0x7c0];
11277  };
11278  
11279  union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits {
11280  	struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext;
11281  	struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext;
11282  	struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext;
11283  	u8         reserved_at_0[0x7c0];
11284  };
11285  
11286  struct mlx5_ifc_mpcnt_reg_bits {
11287  	u8         reserved_at_0[0x2];
11288  	u8         depth[0x6];
11289  	u8         pcie_index[0x8];
11290  	u8         node[0x8];
11291  	u8         reserved_at_18[0x2];
11292  	u8         grp[0x6];
11293  
11294  	u8         clr[0x1];
11295  	u8         reserved_at_21[0x1f];
11296  
11297  	union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set;
11298  };
11299  
11300  struct mlx5_ifc_mpcnt_reg_ext_bits {
11301  	u8         reserved_at_0[0x2];
11302  	u8         depth[0x6];
11303  	u8         pcie_index[0x8];
11304  	u8         node[0x8];
11305  	u8         reserved_at_18[0x2];
11306  	u8         grp[0x6];
11307  
11308  	u8         clr[0x1];
11309  	u8         reserved_at_21[0x1f];
11310  
11311  	union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set;
11312  };
11313  
11314  struct mlx5_ifc_monitor_opcodes_layout_bits {
11315  	u8         reserved_at_0[0x10];
11316  	u8         monitor_opcode[0x10];
11317  };
11318  
11319  union mlx5_ifc_pddr_status_opcode_bits {
11320  	struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes;
11321  	u8         reserved_at_0[0x20];
11322  };
11323  
11324  struct mlx5_ifc_troubleshooting_info_page_layout_bits {
11325  	u8         reserved_at_0[0x10];
11326  	u8         group_opcode[0x10];
11327  
11328  	union mlx5_ifc_pddr_status_opcode_bits status_opcode;
11329  
11330  	u8         user_feedback_data[0x10];
11331  	u8         user_feedback_index[0x10];
11332  
11333  	u8         status_message[0x760];
11334  };
11335  
11336  union mlx5_ifc_pddr_page_data_bits {
11337  	struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page;
11338  	struct mlx5_ifc_pddr_module_info_bits pddr_module_info;
11339  	u8         reserved_at_0[0x7c0];
11340  };
11341  
11342  struct mlx5_ifc_pddr_reg_bits {
11343  	u8         reserved_at_0[0x8];
11344  	u8         local_port[0x8];
11345  	u8         pnat[0x2];
11346  	u8         reserved_at_12[0xe];
11347  
11348  	u8         reserved_at_20[0x18];
11349  	u8         page_select[0x8];
11350  
11351  	union mlx5_ifc_pddr_page_data_bits page_data;
11352  };
11353  
11354  enum {
11355  	MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050,
11356  	MLX5_MPEIN_PWR_STATUS_INVALID = 0,
11357  	MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1,
11358  	MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2,
11359  };
11360  
11361  struct mlx5_ifc_mpein_reg_bits {
11362  	u8         reserved_at_0[0x2];
11363  	u8         depth[0x6];
11364  	u8         pcie_index[0x8];
11365  	u8         node[0x8];
11366  	u8         reserved_at_18[0x8];
11367  
11368  	u8         capability_mask[0x20];
11369  
11370  	u8         reserved_at_40[0x8];
11371  	u8         link_width_enabled[0x8];
11372  	u8         link_speed_enabled[0x10];
11373  
11374  	u8         lane0_physical_position[0x8];
11375  	u8         link_width_active[0x8];
11376  	u8         link_speed_active[0x10];
11377  
11378  	u8         num_of_pfs[0x10];
11379  	u8         num_of_vfs[0x10];
11380  
11381  	u8         bdf0[0x10];
11382  	u8         reserved_at_b0[0x10];
11383  
11384  	u8         max_read_request_size[0x4];
11385  	u8         max_payload_size[0x4];
11386  	u8         reserved_at_c8[0x5];
11387  	u8         pwr_status[0x3];
11388  	u8         port_type[0x4];
11389  	u8         reserved_at_d4[0xb];
11390  	u8         lane_reversal[0x1];
11391  
11392  	u8         reserved_at_e0[0x14];
11393  	u8         pci_power[0xc];
11394  
11395  	u8         reserved_at_100[0x20];
11396  
11397  	u8         device_status[0x10];
11398  	u8         port_state[0x8];
11399  	u8         reserved_at_138[0x8];
11400  
11401  	u8         reserved_at_140[0x10];
11402  	u8         receiver_detect_result[0x10];
11403  
11404  	u8         reserved_at_160[0x20];
11405  };
11406  
11407  struct mlx5_ifc_mpein_reg_ext_bits {
11408  	u8         reserved_at_0[0x2];
11409  	u8         depth[0x6];
11410  	u8         pcie_index[0x8];
11411  	u8         node[0x8];
11412  	u8         reserved_at_18[0x8];
11413  
11414  	u8         reserved_at_20[0x20];
11415  
11416  	u8         reserved_at_40[0x8];
11417  	u8         link_width_enabled[0x8];
11418  	u8         link_speed_enabled[0x10];
11419  
11420  	u8         lane0_physical_position[0x8];
11421  	u8         link_width_active[0x8];
11422  	u8         link_speed_active[0x10];
11423  
11424  	u8         num_of_pfs[0x10];
11425  	u8         num_of_vfs[0x10];
11426  
11427  	u8         bdf0[0x10];
11428  	u8         reserved_at_b0[0x10];
11429  
11430  	u8         max_read_request_size[0x4];
11431  	u8         max_payload_size[0x4];
11432  	u8         reserved_at_c8[0x5];
11433  	u8         pwr_status[0x3];
11434  	u8         port_type[0x4];
11435  	u8         reserved_at_d4[0xb];
11436  	u8         lane_reversal[0x1];
11437  };
11438  
11439  struct mlx5_ifc_mcqi_cap_bits {
11440  	u8         supported_info_bitmask[0x20];
11441  
11442  	u8         component_size[0x20];
11443  
11444  	u8         max_component_size[0x20];
11445  
11446  	u8         log_mcda_word_size[0x4];
11447  	u8         reserved_at_64[0xc];
11448  	u8         mcda_max_write_size[0x10];
11449  
11450  	u8         rd_en[0x1];
11451  	u8         reserved_at_81[0x1];
11452  	u8         match_chip_id[0x1];
11453  	u8         match_psid[0x1];
11454  	u8         check_user_timestamp[0x1];
11455  	u8         match_base_guid_mac[0x1];
11456  	u8         reserved_at_86[0x1a];
11457  };
11458  
11459  struct mlx5_ifc_mcqi_reg_bits {
11460  	u8         read_pending_component[0x1];
11461  	u8         reserved_at_1[0xf];
11462  	u8         component_index[0x10];
11463  
11464  	u8         reserved_at_20[0x20];
11465  
11466  	u8         reserved_at_40[0x1b];
11467  	u8         info_type[0x5];
11468  
11469  	u8         info_size[0x20];
11470  
11471  	u8         offset[0x20];
11472  
11473  	u8         reserved_at_a0[0x10];
11474  	u8         data_size[0x10];
11475  
11476  	u8         data[0][0x20];
11477  };
11478  
11479  struct mlx5_ifc_mcc_reg_bits {
11480  	u8         reserved_at_0[0x4];
11481  	u8         time_elapsed_since_last_cmd[0xc];
11482  	u8         reserved_at_10[0x8];
11483  	u8         instruction[0x8];
11484  
11485  	u8         reserved_at_20[0x10];
11486  	u8         component_index[0x10];
11487  
11488  	u8         reserved_at_40[0x8];
11489  	u8         update_handle[0x18];
11490  
11491  	u8         handle_owner_type[0x4];
11492  	u8         handle_owner_host_id[0x4];
11493  	u8         reserved_at_68[0x1];
11494  	u8         control_progress[0x7];
11495  	u8         error_code[0x8];
11496  	u8         reserved_at_78[0x4];
11497  	u8         control_state[0x4];
11498  
11499  	u8         component_size[0x20];
11500  
11501  	u8         reserved_at_a0[0x60];
11502  };
11503  
11504  struct mlx5_ifc_mcda_reg_bits {
11505  	u8         reserved_at_0[0x8];
11506  	u8         update_handle[0x18];
11507  
11508  	u8         offset[0x20];
11509  
11510  	u8         reserved_at_40[0x10];
11511  	u8         size[0x10];
11512  
11513  	u8         reserved_at_60[0x20];
11514  
11515  	u8         data[0][0x20];
11516  };
11517  
11518  union mlx5_ifc_ports_control_registers_document_bits {
11519  	struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
11520  	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
11521  	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11522  	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11523  	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11524  	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11525  	struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
11526  	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11527  	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11528  	struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
11529  	struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
11530  	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
11531  	struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
11532  	struct mlx5_ifc_pamp_reg_bits pamp_reg;
11533  	struct mlx5_ifc_paos_reg_bits paos_reg;
11534  	struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
11535  	struct mlx5_ifc_pcap_reg_bits pcap_reg;
11536  	struct mlx5_ifc_peir_reg_bits peir_reg;
11537  	struct mlx5_ifc_pelc_reg_bits pelc_reg;
11538  	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
11539  	struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
11540  	struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
11541  	struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
11542  	struct mlx5_ifc_phrr_reg_bits phrr_reg;
11543  	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11544  	struct mlx5_ifc_pifr_reg_bits pifr_reg;
11545  	struct mlx5_ifc_pipg_reg_bits pipg_reg;
11546  	struct mlx5_ifc_plbf_reg_bits plbf_reg;
11547  	struct mlx5_ifc_plib_reg_bits plib_reg;
11548  	struct mlx5_ifc_pll_status_data_bits pll_status_data;
11549  	struct mlx5_ifc_plpc_reg_bits plpc_reg;
11550  	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11551  	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11552  	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11553  	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11554  	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11555  	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11556  	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11557  	struct mlx5_ifc_ppad_reg_bits ppad_reg;
11558  	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11559  	struct mlx5_ifc_ppll_reg_bits ppll_reg;
11560  	struct mlx5_ifc_pplm_reg_bits pplm_reg;
11561  	struct mlx5_ifc_pplr_reg_bits pplr_reg;
11562  	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11563  	struct mlx5_ifc_pspa_reg_bits pspa_reg;
11564  	struct mlx5_ifc_ptas_reg_bits ptas_reg;
11565  	struct mlx5_ifc_ptys_reg_bits ptys_reg;
11566  	struct mlx5_ifc_pude_reg_bits pude_reg;
11567  	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11568  	struct mlx5_ifc_slrg_reg_bits slrg_reg;
11569  	struct mlx5_ifc_slrp_reg_bits slrp_reg;
11570  	struct mlx5_ifc_sltp_reg_bits sltp_reg;
11571  	u8         reserved_0[0x7880];
11572  };
11573  
11574  union mlx5_ifc_debug_enhancements_document_bits {
11575  	struct mlx5_ifc_health_buffer_bits health_buffer;
11576  	u8         reserved_0[0x200];
11577  };
11578  
11579  union mlx5_ifc_no_dram_nic_document_bits {
11580  	struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
11581  	struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
11582  	struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
11583  	struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
11584  	struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
11585  	struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
11586  	struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
11587  	struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
11588  	u8         reserved_0[0x3160];
11589  };
11590  
11591  union mlx5_ifc_uplink_pci_interface_document_bits {
11592  	struct mlx5_ifc_initial_seg_bits initial_seg;
11593  	struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
11594  	u8         reserved_0[0x20120];
11595  };
11596  
11597  struct mlx5_ifc_qpdpm_dscp_reg_bits {
11598  	u8         e[0x1];
11599  	u8         reserved_at_01[0x0b];
11600  	u8         prio[0x04];
11601  };
11602  
11603  struct mlx5_ifc_qpdpm_reg_bits {
11604  	u8                                     reserved_at_0[0x8];
11605  	u8                                     local_port[0x8];
11606  	u8                                     reserved_at_10[0x10];
11607  	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11608  };
11609  
11610  struct mlx5_ifc_qpts_reg_bits {
11611  	u8         reserved_at_0[0x8];
11612  	u8         local_port[0x8];
11613  	u8         reserved_at_10[0x2d];
11614  	u8         trust_state[0x3];
11615  };
11616  
11617  struct mlx5_ifc_mfrl_reg_bits {
11618  	u8         reserved_at_0[0x38];
11619  	u8         reset_level[0x8];
11620  };
11621  
11622  enum {
11623        MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP	= 0x9009,
11624        MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR	= 0x9109,
11625        MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP	= 0x900a,
11626        MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE	= 0x900b,
11627        MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR	= 0x900f,
11628        MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE	= 0x910b,
11629        MLX5_MAX_TEMPERATURE = 16,
11630  };
11631  
11632  struct mlx5_ifc_mtbr_temp_record_bits {
11633  	u8         max_temperature[0x10];
11634  	u8         temperature[0x10];
11635  };
11636  
11637  struct mlx5_ifc_mtbr_reg_bits {
11638  	u8         reserved_at_0[0x14];
11639  	u8         base_sensor_index[0xc];
11640  
11641  	u8         reserved_at_20[0x18];
11642  	u8         num_rec[0x8];
11643  
11644  	u8         reserved_at_40[0x40];
11645  
11646  	struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
11647  };
11648  
11649  struct mlx5_ifc_mtbr_reg_ext_bits {
11650  	u8         reserved_at_0[0x14];
11651  	u8         base_sensor_index[0xc];
11652  
11653  	u8         reserved_at_20[0x18];
11654  	u8         num_rec[0x8];
11655  
11656  	u8         reserved_at_40[0x40];
11657  
11658      struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
11659  };
11660  
11661  struct mlx5_ifc_mtcap_bits {
11662  	u8         reserved_at_0[0x19];
11663  	u8         sensor_count[0x7];
11664  
11665  	u8         reserved_at_20[0x19];
11666  	u8         internal_sensor_count[0x7];
11667  
11668  	u8         sensor_map[0x40];
11669  };
11670  
11671  struct mlx5_ifc_mtcap_ext_bits {
11672  	u8         reserved_at_0[0x19];
11673  	u8         sensor_count[0x7];
11674  
11675  	u8         reserved_at_20[0x20];
11676  
11677  	u8         sensor_map[0x40];
11678  };
11679  
11680  struct mlx5_ifc_mtecr_bits {
11681  	u8         reserved_at_0[0x4];
11682  	u8         last_sensor[0xc];
11683  	u8         reserved_at_10[0x4];
11684  	u8         sensor_count[0xc];
11685  
11686  	u8         reserved_at_20[0x19];
11687  	u8         internal_sensor_count[0x7];
11688  
11689  	u8         sensor_map_0[0x20];
11690  
11691  	u8         reserved_at_60[0x2a0];
11692  };
11693  
11694  struct mlx5_ifc_mtecr_ext_bits {
11695  	u8         reserved_at_0[0x4];
11696  	u8         last_sensor[0xc];
11697  	u8         reserved_at_10[0x4];
11698  	u8         sensor_count[0xc];
11699  
11700  	u8         reserved_at_20[0x20];
11701  
11702  	u8         sensor_map_0[0x20];
11703  
11704  	u8         reserved_at_60[0x2a0];
11705  };
11706  
11707  struct mlx5_ifc_mtewe_bits {
11708  	u8         reserved_at_0[0x4];
11709  	u8         last_sensor[0xc];
11710  	u8         reserved_at_10[0x4];
11711  	u8         sensor_count[0xc];
11712  
11713  	u8         sensor_warning_0[0x20];
11714  
11715  	u8         reserved_at_40[0x2a0];
11716  };
11717  
11718  struct mlx5_ifc_mtewe_ext_bits {
11719  	u8         reserved_at_0[0x4];
11720  	u8         last_sensor[0xc];
11721  	u8         reserved_at_10[0x4];
11722  	u8         sensor_count[0xc];
11723  
11724  	u8         sensor_warning_0[0x20];
11725  
11726  	u8         reserved_at_40[0x2a0];
11727  };
11728  
11729  struct mlx5_ifc_mtmp_bits {
11730  	u8         reserved_at_0[0x14];
11731  	u8         sensor_index[0xc];
11732  
11733  	u8         reserved_at_20[0x10];
11734  	u8         temperature[0x10];
11735  
11736  	u8         mte[0x1];
11737  	u8         mtr[0x1];
11738  	u8         reserved_at_42[0xe];
11739  	u8         max_temperature[0x10];
11740  
11741  	u8         tee[0x2];
11742  	u8         reserved_at_62[0xe];
11743  	u8         temperature_threshold_hi[0x10];
11744  
11745  	u8         reserved_at_80[0x10];
11746  	u8         temperature_threshold_lo[0x10];
11747  
11748  	u8         reserved_at_a0[0x20];
11749  
11750  	u8         sensor_name_hi[0x20];
11751  
11752  	u8         sensor_name_lo[0x20];
11753  };
11754  
11755  struct mlx5_ifc_mtmp_ext_bits {
11756  	u8         reserved_at_0[0x14];
11757  	u8         sensor_index[0xc];
11758  
11759  	u8         reserved_at_20[0x10];
11760  	u8         temperature[0x10];
11761  
11762  	u8         mte[0x1];
11763  	u8         mtr[0x1];
11764  	u8         reserved_at_42[0xe];
11765  	u8         max_temperature[0x10];
11766  
11767  	u8         tee[0x2];
11768  	u8         reserved_at_62[0xe];
11769  	u8         temperature_threshold_hi[0x10];
11770  
11771  	u8         reserved_at_80[0x10];
11772  	u8         temperature_threshold_lo[0x10];
11773  
11774  	u8         reserved_at_a0[0x20];
11775  
11776  	u8         sensor_name_hi[0x20];
11777  
11778  	u8         sensor_name_lo[0x20];
11779  };
11780  
11781  struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
11782  	u8         opcode[0x10];
11783  	u8         uid[0x10];
11784  
11785  	u8         vhca_tunnel_id[0x10];
11786  	u8         obj_type[0x10];
11787  
11788  	u8         obj_id[0x20];
11789  
11790  	u8         reserved_at_60[0x20];
11791  };
11792  
11793  struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
11794  	u8         status[0x8];
11795  	u8         reserved_at_8[0x18];
11796  
11797  	u8         syndrome[0x20];
11798  
11799  	u8         obj_id[0x20];
11800  
11801  	u8         reserved_at_60[0x20];
11802  };
11803  
11804  struct mlx5_ifc_umem_bits {
11805  	u8         reserved_at_0[0x80];
11806  
11807  	u8         reserved_at_80[0x1b];
11808  	u8         log_page_size[0x5];
11809  
11810  	u8         page_offset[0x20];
11811  
11812  	u8         num_of_mtt[0x40];
11813  
11814  	struct mlx5_ifc_mtt_bits  mtt[0];
11815  };
11816  
11817  struct mlx5_ifc_uctx_bits {
11818  	u8         cap[0x20];
11819  
11820  	u8         reserved_at_20[0x160];
11821  };
11822  
11823  struct mlx5_ifc_create_umem_in_bits {
11824  	u8         opcode[0x10];
11825  	u8         uid[0x10];
11826  
11827  	u8         reserved_at_20[0x10];
11828  	u8         op_mod[0x10];
11829  
11830  	u8         reserved_at_40[0x40];
11831  
11832  	struct mlx5_ifc_umem_bits  umem;
11833  };
11834  
11835  struct mlx5_ifc_create_uctx_in_bits {
11836  	u8         opcode[0x10];
11837  	u8         reserved_at_10[0x10];
11838  
11839  	u8         reserved_at_20[0x10];
11840  	u8         op_mod[0x10];
11841  
11842  	u8         reserved_at_40[0x40];
11843  
11844  	struct mlx5_ifc_uctx_bits  uctx;
11845  };
11846  
11847  struct mlx5_ifc_destroy_uctx_in_bits {
11848  	u8         opcode[0x10];
11849  	u8         reserved_at_10[0x10];
11850  
11851  	u8         reserved_at_20[0x10];
11852  	u8         op_mod[0x10];
11853  
11854  	u8         reserved_at_40[0x10];
11855  	u8         uid[0x10];
11856  
11857  	u8         reserved_at_60[0x20];
11858  };
11859  
11860  struct mlx5_ifc_mtrc_string_db_param_bits {
11861  	u8         string_db_base_address[0x20];
11862  
11863  	u8         reserved_at_20[0x8];
11864  	u8         string_db_size[0x18];
11865  };
11866  
11867  struct mlx5_ifc_mtrc_cap_bits {
11868  	u8         trace_owner[0x1];
11869  	u8         trace_to_memory[0x1];
11870  	u8         reserved_at_2[0x4];
11871  	u8         trc_ver[0x2];
11872  	u8         reserved_at_8[0x14];
11873  	u8         num_string_db[0x4];
11874  
11875  	u8         first_string_trace[0x8];
11876  	u8         num_string_trace[0x8];
11877  	u8         reserved_at_30[0x28];
11878  
11879  	u8         log_max_trace_buffer_size[0x8];
11880  
11881  	u8         reserved_at_60[0x20];
11882  
11883  	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11884  
11885  	u8         reserved_at_280[0x180];
11886  };
11887  
11888  struct mlx5_ifc_mtrc_conf_bits {
11889  	u8         reserved_at_0[0x1c];
11890  	u8         trace_mode[0x4];
11891  	u8         reserved_at_20[0x18];
11892  	u8         log_trace_buffer_size[0x8];
11893  	u8         trace_mkey[0x20];
11894  	u8         reserved_at_60[0x3a0];
11895  };
11896  
11897  struct mlx5_ifc_mtrc_stdb_bits {
11898  	u8         string_db_index[0x4];
11899  	u8         reserved_at_4[0x4];
11900  	u8         read_size[0x18];
11901  	u8         start_offset[0x20];
11902  	u8         string_db_data[0];
11903  };
11904  
11905  struct mlx5_ifc_mtrc_ctrl_bits {
11906  	u8         trace_status[0x2];
11907  	u8         reserved_at_2[0x2];
11908  	u8         arm_event[0x1];
11909  	u8         reserved_at_5[0xb];
11910  	u8         modify_field_select[0x10];
11911  	u8         reserved_at_20[0x2b];
11912  	u8         current_timestamp52_32[0x15];
11913  	u8         current_timestamp31_0[0x20];
11914  	u8         reserved_at_80[0x180];
11915  };
11916  
11917  struct mlx5_ifc_affiliated_event_header_bits {
11918  	u8         reserved_at_0[0x10];
11919  	u8         obj_type[0x10];
11920  
11921  	u8         obj_id[0x20];
11922  };
11923  
11924  #define MLX5_FC_BULK_SIZE_FACTOR 128
11925  
11926  enum mlx5_fc_bulk_alloc_bitmask {
11927  	MLX5_FC_BULK_128   = (1 << 0),
11928  	MLX5_FC_BULK_256   = (1 << 1),
11929  	MLX5_FC_BULK_512   = (1 << 2),
11930  	MLX5_FC_BULK_1024  = (1 << 3),
11931  	MLX5_FC_BULK_2048  = (1 << 4),
11932  	MLX5_FC_BULK_4096  = (1 << 5),
11933  	MLX5_FC_BULK_8192  = (1 << 6),
11934  	MLX5_FC_BULK_16384 = (1 << 7),
11935  };
11936  
11937  #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
11938  
11939  struct mlx5_ifc_ipsec_cap_bits {
11940  	u8         ipsec_full_offload[0x1];
11941  	u8         ipsec_crypto_offload[0x1];
11942  	u8         ipsec_esn[0x1];
11943  	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
11944  	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
11945  	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
11946  	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
11947  	u8         reserved_at_7[0x4];
11948  	u8         log_max_ipsec_offload[0x5];
11949  	u8         reserved_at_10[0x10];
11950  
11951  	u8         min_log_ipsec_full_replay_window[0x8];
11952  	u8         max_log_ipsec_full_replay_window[0x8];
11953  	u8         reserved_at_30[0x7d0];
11954  };
11955  
11956  enum {
11957  	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
11958  };
11959  
11960  enum {
11961  	MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
11962  	MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
11963  	MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
11964  	MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
11965  };
11966  
11967  enum {
11968  	MLX5_IPSEC_ASO_MODE              = 0x0,
11969  	MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
11970  	MLX5_IPSEC_ASO_INC_SN            = 0x2,
11971  };
11972  
11973  enum {
11974  	MLX5_IPSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
11975  	MLX5_IPSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
11976  	MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
11977  	MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
11978  };
11979  
11980  struct mlx5_ifc_ipsec_aso_bits {
11981  	u8         valid[0x1];
11982  	u8         reserved_at_201[0x1];
11983  	u8         mode[0x2];
11984  	u8         window_sz[0x2];
11985  	u8         soft_lft_arm[0x1];
11986  	u8         hard_lft_arm[0x1];
11987  	u8         remove_flow_enable[0x1];
11988  	u8         esn_event_arm[0x1];
11989  	u8         reserved_at_20a[0x16];
11990  
11991  	u8         remove_flow_pkt_cnt[0x20];
11992  
11993  	u8         remove_flow_soft_lft[0x20];
11994  
11995  	u8         reserved_at_260[0x80];
11996  
11997  	u8         mode_parameter[0x20];
11998  
11999  	u8         replay_protection_window[0x100];
12000  };
12001  
12002  struct mlx5_ifc_ipsec_obj_bits {
12003  	u8         modify_field_select[0x40];
12004  	u8         full_offload[0x1];
12005  	u8         reserved_at_41[0x1];
12006  	u8         esn_en[0x1];
12007  	u8         esn_overlap[0x1];
12008  	u8         reserved_at_44[0x2];
12009  	u8         icv_length[0x2];
12010  	u8         reserved_at_48[0x4];
12011  	u8         aso_return_reg[0x4];
12012  	u8         reserved_at_50[0x10];
12013  
12014  	u8         esn_msb[0x20];
12015  
12016  	u8         reserved_at_80[0x8];
12017  	u8         dekn[0x18];
12018  
12019  	u8         salt[0x20];
12020  
12021  	u8         implicit_iv[0x40];
12022  
12023  	u8         reserved_at_100[0x8];
12024  	u8         ipsec_aso_access_pd[0x18];
12025  	u8         reserved_at_120[0xe0];
12026  
12027  	struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12028  };
12029  
12030  struct mlx5_ifc_create_ipsec_obj_in_bits {
12031  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12032  	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12033  };
12034  
12035  enum {
12036  	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = 1 << 0,
12037  	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = 1 << 1,
12038  };
12039  
12040  struct mlx5_ifc_query_ipsec_obj_out_bits {
12041  	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12042  	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12043  };
12044  
12045  struct mlx5_ifc_modify_ipsec_obj_in_bits {
12046  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12047  	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12048  };
12049  
12050  enum {
12051  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12052  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12053  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12054  };
12055  #endif /* MLX5_IFC_H */
12056