1 /*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_IFC_H 29 #define MLX5_IFC_H 30 31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> 32 33 enum { 34 MLX5_EVENT_TYPE_COMP = 0x0, 35 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 36 MLX5_EVENT_TYPE_COMM_EST = 0x2, 37 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 38 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 39 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 40 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 41 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 42 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 43 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 44 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 45 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 46 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 47 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 48 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 49 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 50 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 51 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 52 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 53 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 54 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 55 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 56 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 57 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 58 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 59 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 60 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 61 MLX5_EVENT_TYPE_CMD = 0xa, 62 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 63 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 64 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 65 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 66 MLX5_EVENT_TYPE_CODING_GENERAL_OBJ_EVENT = 0x27, 67 }; 68 69 enum { 70 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 71 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 72 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 73 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 74 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 75 }; 76 77 enum { 78 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 79 }; 80 81 enum { 82 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 83 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 84 }; 85 86 enum { 87 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 88 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 89 MLX5_CMD_OP_INIT_HCA = 0x102, 90 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 91 MLX5_CMD_OP_ENABLE_HCA = 0x104, 92 MLX5_CMD_OP_DISABLE_HCA = 0x105, 93 MLX5_CMD_OP_QUERY_PAGES = 0x107, 94 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 95 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 96 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 97 MLX5_CMD_OP_SET_ISSI = 0x10b, 98 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 99 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 100 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 101 MLX5_CMD_OP_CREATE_MKEY = 0x200, 102 MLX5_CMD_OP_QUERY_MKEY = 0x201, 103 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 104 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 105 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 106 MLX5_CMD_OP_CREATE_EQ = 0x301, 107 MLX5_CMD_OP_DESTROY_EQ = 0x302, 108 MLX5_CMD_OP_QUERY_EQ = 0x303, 109 MLX5_CMD_OP_GEN_EQE = 0x304, 110 MLX5_CMD_OP_CREATE_CQ = 0x400, 111 MLX5_CMD_OP_DESTROY_CQ = 0x401, 112 MLX5_CMD_OP_QUERY_CQ = 0x402, 113 MLX5_CMD_OP_MODIFY_CQ = 0x403, 114 MLX5_CMD_OP_CREATE_QP = 0x500, 115 MLX5_CMD_OP_DESTROY_QP = 0x501, 116 MLX5_CMD_OP_RST2INIT_QP = 0x502, 117 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 118 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 119 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 120 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 121 MLX5_CMD_OP_2ERR_QP = 0x507, 122 MLX5_CMD_OP_2RST_QP = 0x50a, 123 MLX5_CMD_OP_QUERY_QP = 0x50b, 124 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 125 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 126 MLX5_CMD_OP_CREATE_PSV = 0x600, 127 MLX5_CMD_OP_DESTROY_PSV = 0x601, 128 MLX5_CMD_OP_CREATE_SRQ = 0x700, 129 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 130 MLX5_CMD_OP_QUERY_SRQ = 0x702, 131 MLX5_CMD_OP_ARM_RQ = 0x703, 132 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 133 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 134 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 135 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 136 MLX5_CMD_OP_CREATE_DCT = 0x710, 137 MLX5_CMD_OP_DESTROY_DCT = 0x711, 138 MLX5_CMD_OP_DRAIN_DCT = 0x712, 139 MLX5_CMD_OP_QUERY_DCT = 0x713, 140 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 141 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 142 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 143 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 144 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 145 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 146 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 147 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 148 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 149 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 150 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 151 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 152 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 153 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 154 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 155 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 156 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 157 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 158 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 159 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 160 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 161 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 162 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 163 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 164 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 165 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 166 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 167 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 168 MLX5_CMD_OP_ALLOC_PD = 0x800, 169 MLX5_CMD_OP_DEALLOC_PD = 0x801, 170 MLX5_CMD_OP_ALLOC_UAR = 0x802, 171 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 172 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 173 MLX5_CMD_OP_ACCESS_REG = 0x805, 174 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 175 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 176 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 177 MLX5_CMD_OP_MAD_IFC = 0x50d, 178 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 179 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 180 MLX5_CMD_OP_NOP = 0x80d, 181 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 182 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 183 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 184 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 185 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 186 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 187 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 188 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 189 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 190 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 191 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 192 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 193 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 194 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 195 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 196 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 197 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 198 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 199 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 200 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 201 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 202 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 203 MLX5_CMD_OP_CREATE_LAG = 0x840, 204 MLX5_CMD_OP_MODIFY_LAG = 0x841, 205 MLX5_CMD_OP_QUERY_LAG = 0x842, 206 MLX5_CMD_OP_DESTROY_LAG = 0x843, 207 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 208 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 209 MLX5_CMD_OP_CREATE_TIR = 0x900, 210 MLX5_CMD_OP_MODIFY_TIR = 0x901, 211 MLX5_CMD_OP_DESTROY_TIR = 0x902, 212 MLX5_CMD_OP_QUERY_TIR = 0x903, 213 MLX5_CMD_OP_CREATE_SQ = 0x904, 214 MLX5_CMD_OP_MODIFY_SQ = 0x905, 215 MLX5_CMD_OP_DESTROY_SQ = 0x906, 216 MLX5_CMD_OP_QUERY_SQ = 0x907, 217 MLX5_CMD_OP_CREATE_RQ = 0x908, 218 MLX5_CMD_OP_MODIFY_RQ = 0x909, 219 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 220 MLX5_CMD_OP_QUERY_RQ = 0x90b, 221 MLX5_CMD_OP_CREATE_RMP = 0x90c, 222 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 223 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 224 MLX5_CMD_OP_QUERY_RMP = 0x90f, 225 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 226 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 227 MLX5_CMD_OP_CREATE_TIS = 0x912, 228 MLX5_CMD_OP_MODIFY_TIS = 0x913, 229 MLX5_CMD_OP_DESTROY_TIS = 0x914, 230 MLX5_CMD_OP_QUERY_TIS = 0x915, 231 MLX5_CMD_OP_CREATE_RQT = 0x916, 232 MLX5_CMD_OP_MODIFY_RQT = 0x917, 233 MLX5_CMD_OP_DESTROY_RQT = 0x918, 234 MLX5_CMD_OP_QUERY_RQT = 0x919, 235 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 236 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 237 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 238 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 239 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 240 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 241 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 242 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 243 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 244 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 245 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 246 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 247 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 248 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 249 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 250 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 251 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 252 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 253 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 254 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 255 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 256 MLX5_CMD_OP_CREATE_GENERAL_OBJ = 0xa00, 257 MLX5_CMD_OP_MODIFY_GENERAL_OBJ = 0xa01, 258 MLX5_CMD_OP_QUERY_GENERAL_OBJ = 0xa02, 259 MLX5_CMD_OP_DESTROY_GENERAL_OBJ = 0xa03, 260 261 }; 262 263 enum { 264 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 265 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 266 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 267 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 268 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 269 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 270 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 271 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 272 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 273 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 274 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 275 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 276 }; 277 278 enum { 279 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 280 }; 281 282 enum { 283 MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc, 284 }; 285 286 enum { 287 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 288 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 289 }; 290 291 enum { 292 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1, 293 }; 294 295 struct mlx5_ifc_flow_table_fields_supported_bits { 296 u8 outer_dmac[0x1]; 297 u8 outer_smac[0x1]; 298 u8 outer_ether_type[0x1]; 299 u8 reserved_0[0x1]; 300 u8 outer_first_prio[0x1]; 301 u8 outer_first_cfi[0x1]; 302 u8 outer_first_vid[0x1]; 303 u8 reserved_1[0x1]; 304 u8 outer_second_prio[0x1]; 305 u8 outer_second_cfi[0x1]; 306 u8 outer_second_vid[0x1]; 307 u8 outer_ipv6_flow_label[0x1]; 308 u8 outer_sip[0x1]; 309 u8 outer_dip[0x1]; 310 u8 outer_frag[0x1]; 311 u8 outer_ip_protocol[0x1]; 312 u8 outer_ip_ecn[0x1]; 313 u8 outer_ip_dscp[0x1]; 314 u8 outer_udp_sport[0x1]; 315 u8 outer_udp_dport[0x1]; 316 u8 outer_tcp_sport[0x1]; 317 u8 outer_tcp_dport[0x1]; 318 u8 outer_tcp_flags[0x1]; 319 u8 outer_gre_protocol[0x1]; 320 u8 outer_gre_key[0x1]; 321 u8 outer_vxlan_vni[0x1]; 322 u8 outer_geneve_vni[0x1]; 323 u8 outer_geneve_oam[0x1]; 324 u8 outer_geneve_protocol_type[0x1]; 325 u8 outer_geneve_opt_len[0x1]; 326 u8 reserved_2[0x1]; 327 u8 source_eswitch_port[0x1]; 328 329 u8 inner_dmac[0x1]; 330 u8 inner_smac[0x1]; 331 u8 inner_ether_type[0x1]; 332 u8 reserved_3[0x1]; 333 u8 inner_first_prio[0x1]; 334 u8 inner_first_cfi[0x1]; 335 u8 inner_first_vid[0x1]; 336 u8 reserved_4[0x1]; 337 u8 inner_second_prio[0x1]; 338 u8 inner_second_cfi[0x1]; 339 u8 inner_second_vid[0x1]; 340 u8 inner_ipv6_flow_label[0x1]; 341 u8 inner_sip[0x1]; 342 u8 inner_dip[0x1]; 343 u8 inner_frag[0x1]; 344 u8 inner_ip_protocol[0x1]; 345 u8 inner_ip_ecn[0x1]; 346 u8 inner_ip_dscp[0x1]; 347 u8 inner_udp_sport[0x1]; 348 u8 inner_udp_dport[0x1]; 349 u8 inner_tcp_sport[0x1]; 350 u8 inner_tcp_dport[0x1]; 351 u8 inner_tcp_flags[0x1]; 352 u8 reserved_5[0x9]; 353 354 u8 reserved_6[0x1a]; 355 u8 bth_dst_qp[0x1]; 356 u8 reserved_7[0x4]; 357 u8 source_sqn[0x1]; 358 359 u8 reserved_8[0x20]; 360 }; 361 362 struct mlx5_ifc_eth_discard_cntrs_grp_bits { 363 u8 ingress_general_high[0x20]; 364 365 u8 ingress_general_low[0x20]; 366 367 u8 ingress_policy_engine_high[0x20]; 368 369 u8 ingress_policy_engine_low[0x20]; 370 371 u8 ingress_vlan_membership_high[0x20]; 372 373 u8 ingress_vlan_membership_low[0x20]; 374 375 u8 ingress_tag_frame_type_high[0x20]; 376 377 u8 ingress_tag_frame_type_low[0x20]; 378 379 u8 egress_vlan_membership_high[0x20]; 380 381 u8 egress_vlan_membership_low[0x20]; 382 383 u8 loopback_filter_high[0x20]; 384 385 u8 loopback_filter_low[0x20]; 386 387 u8 egress_general_high[0x20]; 388 389 u8 egress_general_low[0x20]; 390 391 u8 reserved_at_1c0[0x40]; 392 393 u8 egress_hoq_high[0x20]; 394 395 u8 egress_hoq_low[0x20]; 396 397 u8 port_isolation_high[0x20]; 398 399 u8 port_isolation_low[0x20]; 400 401 u8 egress_policy_engine_high[0x20]; 402 403 u8 egress_policy_engine_low[0x20]; 404 405 u8 ingress_tx_link_down_high[0x20]; 406 407 u8 ingress_tx_link_down_low[0x20]; 408 409 u8 egress_stp_filter_high[0x20]; 410 411 u8 egress_stp_filter_low[0x20]; 412 413 u8 egress_hoq_stall_high[0x20]; 414 415 u8 egress_hoq_stall_low[0x20]; 416 417 u8 reserved_at_340[0x440]; 418 }; 419 struct mlx5_ifc_flow_table_prop_layout_bits { 420 u8 ft_support[0x1]; 421 u8 flow_tag[0x1]; 422 u8 flow_counter[0x1]; 423 u8 flow_modify_en[0x1]; 424 u8 modify_root[0x1]; 425 u8 identified_miss_table[0x1]; 426 u8 flow_table_modify[0x1]; 427 u8 encap[0x1]; 428 u8 decap[0x1]; 429 u8 reset_root_to_default[0x1]; 430 u8 reserved_at_a[0x16]; 431 432 u8 reserved_at_20[0x2]; 433 u8 log_max_ft_size[0x6]; 434 u8 reserved_at_28[0x10]; 435 u8 max_ft_level[0x8]; 436 437 u8 reserved_at_40[0x20]; 438 439 u8 reserved_at_60[0x18]; 440 u8 log_max_ft_num[0x8]; 441 442 u8 reserved_at_80[0x10]; 443 u8 log_max_flow_counter[0x8]; 444 u8 log_max_destination[0x8]; 445 446 u8 reserved_at_a0[0x18]; 447 u8 log_max_flow[0x8]; 448 449 u8 reserved_at_c0[0x40]; 450 451 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 452 453 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 454 }; 455 456 struct mlx5_ifc_odp_per_transport_service_cap_bits { 457 u8 send[0x1]; 458 u8 receive[0x1]; 459 u8 write[0x1]; 460 u8 read[0x1]; 461 u8 atomic[0x1]; 462 u8 srq_receive[0x1]; 463 u8 reserved_0[0x1a]; 464 }; 465 466 struct mlx5_ifc_flow_counter_list_bits { 467 u8 reserved_0[0x10]; 468 u8 flow_counter_id[0x10]; 469 470 u8 reserved_1[0x20]; 471 }; 472 473 enum { 474 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 475 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 476 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 477 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 478 }; 479 480 struct mlx5_ifc_dest_format_struct_bits { 481 u8 destination_type[0x8]; 482 u8 destination_id[0x18]; 483 484 u8 reserved_0[0x20]; 485 }; 486 487 struct mlx5_ifc_ipv4_layout_bits { 488 u8 reserved_at_0[0x60]; 489 490 u8 ipv4[0x20]; 491 }; 492 493 struct mlx5_ifc_ipv6_layout_bits { 494 u8 ipv6[16][0x8]; 495 }; 496 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 498 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 499 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 500 u8 reserved_at_0[0x80]; 501 }; 502 503 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 504 u8 smac_47_16[0x20]; 505 506 u8 smac_15_0[0x10]; 507 u8 ethertype[0x10]; 508 509 u8 dmac_47_16[0x20]; 510 511 u8 dmac_15_0[0x10]; 512 u8 first_prio[0x3]; 513 u8 first_cfi[0x1]; 514 u8 first_vid[0xc]; 515 516 u8 ip_protocol[0x8]; 517 u8 ip_dscp[0x6]; 518 u8 ip_ecn[0x2]; 519 u8 cvlan_tag[0x1]; 520 u8 svlan_tag[0x1]; 521 u8 frag[0x1]; 522 u8 reserved_1[0x4]; 523 u8 tcp_flags[0x9]; 524 525 u8 tcp_sport[0x10]; 526 u8 tcp_dport[0x10]; 527 528 u8 reserved_2[0x20]; 529 530 u8 udp_sport[0x10]; 531 u8 udp_dport[0x10]; 532 533 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 534 535 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 536 }; 537 538 struct mlx5_ifc_fte_match_set_misc_bits { 539 u8 reserved_0[0x8]; 540 u8 source_sqn[0x18]; 541 542 u8 reserved_1[0x10]; 543 u8 source_port[0x10]; 544 545 u8 outer_second_prio[0x3]; 546 u8 outer_second_cfi[0x1]; 547 u8 outer_second_vid[0xc]; 548 u8 inner_second_prio[0x3]; 549 u8 inner_second_cfi[0x1]; 550 u8 inner_second_vid[0xc]; 551 552 u8 outer_second_vlan_tag[0x1]; 553 u8 inner_second_vlan_tag[0x1]; 554 u8 reserved_2[0xe]; 555 u8 gre_protocol[0x10]; 556 557 u8 gre_key_h[0x18]; 558 u8 gre_key_l[0x8]; 559 560 u8 vxlan_vni[0x18]; 561 u8 reserved_3[0x8]; 562 563 u8 geneve_vni[0x18]; 564 u8 reserved4[0x7]; 565 u8 geneve_oam[0x1]; 566 567 u8 reserved_5[0xc]; 568 u8 outer_ipv6_flow_label[0x14]; 569 570 u8 reserved_6[0xc]; 571 u8 inner_ipv6_flow_label[0x14]; 572 573 u8 reserved_7[0xa]; 574 u8 geneve_opt_len[0x6]; 575 u8 geneve_protocol_type[0x10]; 576 577 u8 reserved_8[0x8]; 578 u8 bth_dst_qp[0x18]; 579 580 u8 reserved_9[0xa0]; 581 }; 582 583 struct mlx5_ifc_cmd_pas_bits { 584 u8 pa_h[0x20]; 585 586 u8 pa_l[0x14]; 587 u8 reserved_0[0xc]; 588 }; 589 590 struct mlx5_ifc_uint64_bits { 591 u8 hi[0x20]; 592 593 u8 lo[0x20]; 594 }; 595 596 struct mlx5_ifc_application_prio_entry_bits { 597 u8 reserved_0[0x8]; 598 u8 priority[0x3]; 599 u8 reserved_1[0x2]; 600 u8 sel[0x3]; 601 u8 protocol_id[0x10]; 602 }; 603 604 struct mlx5_ifc_nodnic_ring_doorbell_bits { 605 u8 reserved_0[0x8]; 606 u8 ring_pi[0x10]; 607 u8 reserved_1[0x8]; 608 }; 609 610 enum { 611 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 612 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 613 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 614 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 615 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 616 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 617 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 618 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 619 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 620 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 621 }; 622 623 struct mlx5_ifc_ads_bits { 624 u8 fl[0x1]; 625 u8 free_ar[0x1]; 626 u8 reserved_0[0xe]; 627 u8 pkey_index[0x10]; 628 629 u8 reserved_1[0x8]; 630 u8 grh[0x1]; 631 u8 mlid[0x7]; 632 u8 rlid[0x10]; 633 634 u8 ack_timeout[0x5]; 635 u8 reserved_2[0x3]; 636 u8 src_addr_index[0x8]; 637 u8 log_rtm[0x4]; 638 u8 stat_rate[0x4]; 639 u8 hop_limit[0x8]; 640 641 u8 reserved_3[0x4]; 642 u8 tclass[0x8]; 643 u8 flow_label[0x14]; 644 645 u8 rgid_rip[16][0x8]; 646 647 u8 reserved_4[0x4]; 648 u8 f_dscp[0x1]; 649 u8 f_ecn[0x1]; 650 u8 reserved_5[0x1]; 651 u8 f_eth_prio[0x1]; 652 u8 ecn[0x2]; 653 u8 dscp[0x6]; 654 u8 udp_sport[0x10]; 655 656 u8 dei_cfi[0x1]; 657 u8 eth_prio[0x3]; 658 u8 sl[0x4]; 659 u8 port[0x8]; 660 u8 rmac_47_32[0x10]; 661 662 u8 rmac_31_0[0x20]; 663 }; 664 665 struct mlx5_ifc_diagnostic_counter_cap_bits { 666 u8 sync[0x1]; 667 u8 reserved_0[0xf]; 668 u8 counter_id[0x10]; 669 }; 670 671 struct mlx5_ifc_debug_cap_bits { 672 u8 reserved_0[0x18]; 673 u8 log_max_samples[0x8]; 674 675 u8 single[0x1]; 676 u8 repetitive[0x1]; 677 u8 health_mon_rx_activity[0x1]; 678 u8 reserved_1[0x15]; 679 u8 log_min_sample_period[0x8]; 680 681 u8 reserved_2[0x1c0]; 682 683 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 684 }; 685 686 struct mlx5_ifc_qos_cap_bits { 687 u8 packet_pacing[0x1]; 688 u8 esw_scheduling[0x1]; 689 u8 esw_bw_share[0x1]; 690 u8 esw_rate_limit[0x1]; 691 u8 hll[0x1]; 692 u8 packet_pacing_burst_bound[0x1]; 693 u8 packet_pacing_typical_size[0x1]; 694 u8 reserved_at_7[0x19]; 695 696 u8 reserved_at_20[0x20]; 697 698 u8 packet_pacing_max_rate[0x20]; 699 700 u8 packet_pacing_min_rate[0x20]; 701 702 u8 reserved_at_80[0x10]; 703 u8 packet_pacing_rate_table_size[0x10]; 704 705 u8 esw_element_type[0x10]; 706 u8 esw_tsar_type[0x10]; 707 708 u8 reserved_at_c0[0x10]; 709 u8 max_qos_para_vport[0x10]; 710 711 u8 max_tsar_bw_share[0x20]; 712 713 u8 reserved_at_100[0x700]; 714 }; 715 716 struct mlx5_ifc_snapshot_cap_bits { 717 u8 reserved_0[0x1d]; 718 u8 suspend_qp_uc[0x1]; 719 u8 suspend_qp_ud[0x1]; 720 u8 suspend_qp_rc[0x1]; 721 722 u8 reserved_1[0x1c]; 723 u8 restore_pd[0x1]; 724 u8 restore_uar[0x1]; 725 u8 restore_mkey[0x1]; 726 u8 restore_qp[0x1]; 727 728 u8 reserved_2[0x1e]; 729 u8 named_mkey[0x1]; 730 u8 named_qp[0x1]; 731 732 u8 reserved_3[0x7a0]; 733 }; 734 735 struct mlx5_ifc_e_switch_cap_bits { 736 u8 vport_svlan_strip[0x1]; 737 u8 vport_cvlan_strip[0x1]; 738 u8 vport_svlan_insert[0x1]; 739 u8 vport_cvlan_insert_if_not_exist[0x1]; 740 u8 vport_cvlan_insert_overwrite[0x1]; 741 742 u8 reserved_0[0x19]; 743 744 u8 nic_vport_node_guid_modify[0x1]; 745 u8 nic_vport_port_guid_modify[0x1]; 746 747 u8 reserved_1[0x7e0]; 748 }; 749 750 struct mlx5_ifc_flow_table_eswitch_cap_bits { 751 u8 reserved_0[0x200]; 752 753 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 754 755 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 756 757 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 758 759 u8 reserved_1[0x7800]; 760 }; 761 762 struct mlx5_ifc_flow_table_nic_cap_bits { 763 u8 nic_rx_multi_path_tirs[0x1]; 764 u8 nic_rx_multi_path_tirs_fts[0x1]; 765 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 766 u8 reserved_at_3[0x1fd]; 767 768 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 769 770 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 771 772 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 773 774 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 775 776 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 777 778 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 779 780 u8 reserved_1[0x7200]; 781 }; 782 783 struct mlx5_ifc_pddr_module_info_bits { 784 u8 cable_technology[0x8]; 785 u8 cable_breakout[0x8]; 786 u8 ext_ethernet_compliance_code[0x8]; 787 u8 ethernet_compliance_code[0x8]; 788 789 u8 cable_type[0x4]; 790 u8 cable_vendor[0x4]; 791 u8 cable_length[0x8]; 792 u8 cable_identifier[0x8]; 793 u8 cable_power_class[0x8]; 794 795 u8 reserved_at_40[0x8]; 796 u8 cable_rx_amp[0x8]; 797 u8 cable_rx_emphasis[0x8]; 798 u8 cable_tx_equalization[0x8]; 799 800 u8 reserved_at_60[0x8]; 801 u8 cable_attenuation_12g[0x8]; 802 u8 cable_attenuation_7g[0x8]; 803 u8 cable_attenuation_5g[0x8]; 804 805 u8 reserved_at_80[0x8]; 806 u8 rx_cdr_cap[0x4]; 807 u8 tx_cdr_cap[0x4]; 808 u8 reserved_at_90[0x4]; 809 u8 rx_cdr_state[0x4]; 810 u8 reserved_at_98[0x4]; 811 u8 tx_cdr_state[0x4]; 812 813 u8 vendor_name[16][0x8]; 814 815 u8 vendor_pn[16][0x8]; 816 817 u8 vendor_rev[0x20]; 818 819 u8 fw_version[0x20]; 820 821 u8 vendor_sn[16][0x8]; 822 823 u8 temperature[0x10]; 824 u8 voltage[0x10]; 825 826 u8 rx_power_lane0[0x10]; 827 u8 rx_power_lane1[0x10]; 828 829 u8 rx_power_lane2[0x10]; 830 u8 rx_power_lane3[0x10]; 831 832 u8 reserved_at_2c0[0x40]; 833 834 u8 tx_power_lane0[0x10]; 835 u8 tx_power_lane1[0x10]; 836 837 u8 tx_power_lane2[0x10]; 838 u8 tx_power_lane3[0x10]; 839 840 u8 reserved_at_340[0x40]; 841 842 u8 tx_bias_lane0[0x10]; 843 u8 tx_bias_lane1[0x10]; 844 845 u8 tx_bias_lane2[0x10]; 846 u8 tx_bias_lane3[0x10]; 847 848 u8 reserved_at_3c0[0x40]; 849 850 u8 temperature_high_th[0x10]; 851 u8 temperature_low_th[0x10]; 852 853 u8 voltage_high_th[0x10]; 854 u8 voltage_low_th[0x10]; 855 856 u8 rx_power_high_th[0x10]; 857 u8 rx_power_low_th[0x10]; 858 859 u8 tx_power_high_th[0x10]; 860 u8 tx_power_low_th[0x10]; 861 862 u8 tx_bias_high_th[0x10]; 863 u8 tx_bias_low_th[0x10]; 864 865 u8 reserved_at_4a0[0x10]; 866 u8 wavelength[0x10]; 867 868 u8 reserved_at_4c0[0x300]; 869 }; 870 871 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 872 u8 csum_cap[0x1]; 873 u8 vlan_cap[0x1]; 874 u8 lro_cap[0x1]; 875 u8 lro_psh_flag[0x1]; 876 u8 lro_time_stamp[0x1]; 877 u8 lro_max_msg_sz_mode[0x2]; 878 u8 wqe_vlan_insert[0x1]; 879 u8 self_lb_en_modifiable[0x1]; 880 u8 self_lb_mc[0x1]; 881 u8 self_lb_uc[0x1]; 882 u8 max_lso_cap[0x5]; 883 u8 multi_pkt_send_wqe[0x2]; 884 u8 wqe_inline_mode[0x2]; 885 u8 rss_ind_tbl_cap[0x4]; 886 u8 scatter_fcs[0x1]; 887 u8 reserved_1[0x2]; 888 u8 tunnel_lso_const_out_ip_id[0x1]; 889 u8 tunnel_lro_gre[0x1]; 890 u8 tunnel_lro_vxlan[0x1]; 891 u8 tunnel_statless_gre[0x1]; 892 u8 tunnel_stateless_vxlan[0x1]; 893 894 u8 swp[0x1]; 895 u8 swp_csum[0x1]; 896 u8 swp_lso[0x1]; 897 u8 reserved_2[0x1b]; 898 u8 max_geneve_opt_len[0x1]; 899 u8 tunnel_stateless_geneve_rx[0x1]; 900 901 u8 reserved_3[0x10]; 902 u8 lro_min_mss_size[0x10]; 903 904 u8 reserved_4[0x120]; 905 906 u8 lro_timer_supported_periods[4][0x20]; 907 908 u8 reserved_5[0x600]; 909 }; 910 911 enum { 912 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 913 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 914 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 915 }; 916 917 enum { 918 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 919 MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 920 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 921 }; 922 923 struct mlx5_ifc_roce_cap_bits { 924 u8 roce_apm[0x1]; 925 u8 rts2rts_primary_eth_prio[0x1]; 926 u8 roce_rx_allow_untagged[0x1]; 927 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 928 u8 reserved_at_4[0x1a]; 929 u8 qp_ts_format[0x2]; 930 931 u8 reserved_1[0x60]; 932 933 u8 reserved_2[0xc]; 934 u8 l3_type[0x4]; 935 u8 reserved_3[0x8]; 936 u8 roce_version[0x8]; 937 938 u8 reserved_4[0x10]; 939 u8 r_roce_dest_udp_port[0x10]; 940 941 u8 r_roce_max_src_udp_port[0x10]; 942 u8 r_roce_min_src_udp_port[0x10]; 943 944 u8 reserved_5[0x10]; 945 u8 roce_address_table_size[0x10]; 946 947 u8 reserved_6[0x700]; 948 }; 949 950 enum { 951 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 952 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 953 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 954 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 955 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 956 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 957 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 958 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 959 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 960 }; 961 962 enum { 963 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 964 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 965 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 966 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 967 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 968 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 969 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 970 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 971 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 972 }; 973 974 struct mlx5_ifc_atomic_caps_bits { 975 u8 reserved_0[0x40]; 976 977 u8 atomic_req_8B_endianess_mode[0x2]; 978 u8 reserved_1[0x4]; 979 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 980 981 u8 reserved_2[0x19]; 982 983 u8 reserved_3[0x20]; 984 985 u8 reserved_4[0x10]; 986 u8 atomic_operations[0x10]; 987 988 u8 reserved_5[0x10]; 989 u8 atomic_size_qp[0x10]; 990 991 u8 reserved_6[0x10]; 992 u8 atomic_size_dc[0x10]; 993 994 u8 reserved_7[0x720]; 995 }; 996 997 struct mlx5_ifc_odp_cap_bits { 998 u8 reserved_0[0x40]; 999 1000 u8 sig[0x1]; 1001 u8 reserved_1[0x1f]; 1002 1003 u8 reserved_2[0x20]; 1004 1005 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1006 1007 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1008 1009 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1010 1011 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1012 1013 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1014 1015 u8 reserved_3[0x6e0]; 1016 }; 1017 1018 enum { 1019 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1020 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1021 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1022 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1023 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1024 }; 1025 1026 enum { 1027 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1028 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1029 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1030 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1031 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1032 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1033 }; 1034 1035 enum { 1036 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1037 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1038 }; 1039 1040 enum { 1041 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1042 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1043 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1044 }; 1045 1046 enum { 1047 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1048 MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1049 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1050 }; 1051 1052 enum { 1053 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1054 MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1055 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1056 }; 1057 1058 struct mlx5_ifc_cmd_hca_cap_bits { 1059 u8 reserved_0[0x80]; 1060 1061 u8 log_max_srq_sz[0x8]; 1062 u8 log_max_qp_sz[0x8]; 1063 u8 reserved_1[0xb]; 1064 u8 log_max_qp[0x5]; 1065 1066 u8 reserved_2[0xb]; 1067 u8 log_max_srq[0x5]; 1068 u8 reserved_3[0x10]; 1069 1070 u8 reserved_4[0x8]; 1071 u8 log_max_cq_sz[0x8]; 1072 u8 relaxed_ordering_write_umr[0x1]; 1073 u8 relaxed_ordering_read_umr[0x1]; 1074 u8 reserved_5[0x9]; 1075 u8 log_max_cq[0x5]; 1076 1077 u8 log_max_eq_sz[0x8]; 1078 u8 relaxed_ordering_write[0x1]; 1079 u8 relaxed_ordering_read[0x1]; 1080 u8 log_max_mkey[0x6]; 1081 u8 reserved_7[0xb]; 1082 u8 fast_teardown[0x1]; 1083 u8 log_max_eq[0x4]; 1084 1085 u8 max_indirection[0x8]; 1086 u8 reserved_8[0x1]; 1087 u8 log_max_mrw_sz[0x7]; 1088 u8 force_teardown[0x1]; 1089 u8 reserved_9[0x1]; 1090 u8 log_max_bsf_list_size[0x6]; 1091 u8 reserved_10[0x2]; 1092 u8 log_max_klm_list_size[0x6]; 1093 1094 u8 reserved_11[0xa]; 1095 u8 log_max_ra_req_dc[0x6]; 1096 u8 reserved_12[0xa]; 1097 u8 log_max_ra_res_dc[0x6]; 1098 1099 u8 reserved_13[0xa]; 1100 u8 log_max_ra_req_qp[0x6]; 1101 u8 reserved_14[0xa]; 1102 u8 log_max_ra_res_qp[0x6]; 1103 1104 u8 pad_cap[0x1]; 1105 u8 cc_query_allowed[0x1]; 1106 u8 cc_modify_allowed[0x1]; 1107 u8 start_pad[0x1]; 1108 u8 cache_line_128byte[0x1]; 1109 u8 reserved_at_165[0xa]; 1110 u8 qcam_reg[0x1]; 1111 u8 gid_table_size[0x10]; 1112 1113 u8 out_of_seq_cnt[0x1]; 1114 u8 vport_counters[0x1]; 1115 u8 retransmission_q_counters[0x1]; 1116 u8 debug[0x1]; 1117 u8 modify_rq_counters_set_id[0x1]; 1118 u8 rq_delay_drop[0x1]; 1119 u8 max_qp_cnt[0xa]; 1120 u8 pkey_table_size[0x10]; 1121 1122 u8 vport_group_manager[0x1]; 1123 u8 vhca_group_manager[0x1]; 1124 u8 ib_virt[0x1]; 1125 u8 eth_virt[0x1]; 1126 u8 reserved_17[0x1]; 1127 u8 ets[0x1]; 1128 u8 nic_flow_table[0x1]; 1129 u8 eswitch_flow_table[0x1]; 1130 u8 reserved_18[0x1]; 1131 u8 mcam_reg[0x1]; 1132 u8 pcam_reg[0x1]; 1133 u8 local_ca_ack_delay[0x5]; 1134 u8 port_module_event[0x1]; 1135 u8 reserved_19[0x5]; 1136 u8 port_type[0x2]; 1137 u8 num_ports[0x8]; 1138 1139 u8 snapshot[0x1]; 1140 u8 reserved_20[0x2]; 1141 u8 log_max_msg[0x5]; 1142 u8 reserved_21[0x4]; 1143 u8 max_tc[0x4]; 1144 u8 temp_warn_event[0x1]; 1145 u8 dcbx[0x1]; 1146 u8 general_notification_event[0x1]; 1147 u8 reserved_at_1d3[0x2]; 1148 u8 fpga[0x1]; 1149 u8 rol_s[0x1]; 1150 u8 rol_g[0x1]; 1151 u8 reserved_23[0x1]; 1152 u8 wol_s[0x1]; 1153 u8 wol_g[0x1]; 1154 u8 wol_a[0x1]; 1155 u8 wol_b[0x1]; 1156 u8 wol_m[0x1]; 1157 u8 wol_u[0x1]; 1158 u8 wol_p[0x1]; 1159 1160 u8 stat_rate_support[0x10]; 1161 u8 reserved_24[0xc]; 1162 u8 cqe_version[0x4]; 1163 1164 u8 compact_address_vector[0x1]; 1165 u8 striding_rq[0x1]; 1166 u8 reserved_25[0x1]; 1167 u8 ipoib_enhanced_offloads[0x1]; 1168 u8 ipoib_ipoib_offloads[0x1]; 1169 u8 reserved_26[0x8]; 1170 u8 dc_connect_qp[0x1]; 1171 u8 dc_cnak_trace[0x1]; 1172 u8 drain_sigerr[0x1]; 1173 u8 cmdif_checksum[0x2]; 1174 u8 sigerr_cqe[0x1]; 1175 u8 reserved_27[0x1]; 1176 u8 wq_signature[0x1]; 1177 u8 sctr_data_cqe[0x1]; 1178 u8 reserved_28[0x1]; 1179 u8 sho[0x1]; 1180 u8 tph[0x1]; 1181 u8 rf[0x1]; 1182 u8 dct[0x1]; 1183 u8 qos[0x1]; 1184 u8 eth_net_offloads[0x1]; 1185 u8 roce[0x1]; 1186 u8 atomic[0x1]; 1187 u8 reserved_30[0x1]; 1188 1189 u8 cq_oi[0x1]; 1190 u8 cq_resize[0x1]; 1191 u8 cq_moderation[0x1]; 1192 u8 cq_period_mode_modify[0x1]; 1193 u8 cq_invalidate[0x1]; 1194 u8 reserved_at_225[0x1]; 1195 u8 cq_eq_remap[0x1]; 1196 u8 pg[0x1]; 1197 u8 block_lb_mc[0x1]; 1198 u8 exponential_backoff[0x1]; 1199 u8 scqe_break_moderation[0x1]; 1200 u8 cq_period_start_from_cqe[0x1]; 1201 u8 cd[0x1]; 1202 u8 atm[0x1]; 1203 u8 apm[0x1]; 1204 u8 imaicl[0x1]; 1205 u8 reserved_32[0x6]; 1206 u8 qkv[0x1]; 1207 u8 pkv[0x1]; 1208 u8 set_deth_sqpn[0x1]; 1209 u8 reserved_33[0x3]; 1210 u8 xrc[0x1]; 1211 u8 ud[0x1]; 1212 u8 uc[0x1]; 1213 u8 rc[0x1]; 1214 1215 u8 uar_4k[0x1]; 1216 u8 reserved_at_241[0x9]; 1217 u8 uar_sz[0x6]; 1218 u8 reserved_35[0x8]; 1219 u8 log_pg_sz[0x8]; 1220 1221 u8 bf[0x1]; 1222 u8 driver_version[0x1]; 1223 u8 pad_tx_eth_packet[0x1]; 1224 u8 reserved_36[0x8]; 1225 u8 log_bf_reg_size[0x5]; 1226 u8 reserved_37[0x10]; 1227 1228 u8 num_of_diagnostic_counters[0x10]; 1229 u8 max_wqe_sz_sq[0x10]; 1230 1231 u8 reserved_38[0x10]; 1232 u8 max_wqe_sz_rq[0x10]; 1233 1234 u8 reserved_39[0x10]; 1235 u8 max_wqe_sz_sq_dc[0x10]; 1236 1237 u8 reserved_40[0x7]; 1238 u8 max_qp_mcg[0x19]; 1239 1240 u8 reserved_41[0x18]; 1241 u8 log_max_mcg[0x8]; 1242 1243 u8 reserved_42[0x3]; 1244 u8 log_max_transport_domain[0x5]; 1245 u8 reserved_43[0x3]; 1246 u8 log_max_pd[0x5]; 1247 u8 reserved_44[0xb]; 1248 u8 log_max_xrcd[0x5]; 1249 1250 u8 nic_receive_steering_discard[0x1]; 1251 u8 reserved_45[0x7]; 1252 u8 log_max_flow_counter_bulk[0x8]; 1253 u8 max_flow_counter[0x10]; 1254 1255 u8 reserved_46[0x3]; 1256 u8 log_max_rq[0x5]; 1257 u8 reserved_47[0x3]; 1258 u8 log_max_sq[0x5]; 1259 u8 reserved_48[0x3]; 1260 u8 log_max_tir[0x5]; 1261 u8 reserved_49[0x3]; 1262 u8 log_max_tis[0x5]; 1263 1264 u8 basic_cyclic_rcv_wqe[0x1]; 1265 u8 reserved_50[0x2]; 1266 u8 log_max_rmp[0x5]; 1267 u8 reserved_51[0x3]; 1268 u8 log_max_rqt[0x5]; 1269 u8 reserved_52[0x3]; 1270 u8 log_max_rqt_size[0x5]; 1271 u8 reserved_53[0x3]; 1272 u8 log_max_tis_per_sq[0x5]; 1273 1274 u8 reserved_54[0x3]; 1275 u8 log_max_stride_sz_rq[0x5]; 1276 u8 reserved_55[0x3]; 1277 u8 log_min_stride_sz_rq[0x5]; 1278 u8 reserved_56[0x3]; 1279 u8 log_max_stride_sz_sq[0x5]; 1280 u8 reserved_57[0x3]; 1281 u8 log_min_stride_sz_sq[0x5]; 1282 1283 u8 reserved_58[0x1b]; 1284 u8 log_max_wq_sz[0x5]; 1285 1286 u8 nic_vport_change_event[0x1]; 1287 u8 disable_local_lb[0x1]; 1288 u8 reserved_59[0x9]; 1289 u8 log_max_vlan_list[0x5]; 1290 u8 reserved_60[0x3]; 1291 u8 log_max_current_mc_list[0x5]; 1292 u8 reserved_61[0x3]; 1293 u8 log_max_current_uc_list[0x5]; 1294 1295 u8 general_obj_types[0x40]; 1296 1297 u8 sq_ts_format[0x2]; 1298 u8 rq_ts_format[0x2]; 1299 u8 reserved_at_444[0x4]; 1300 u8 create_qp_start_hint[0x18]; 1301 1302 u8 reserved_at_460[0x3]; 1303 u8 log_max_uctx[0x5]; 1304 u8 reserved_at_468[0x3]; 1305 u8 log_max_umem[0x5]; 1306 u8 max_num_eqs[0x10]; 1307 1308 u8 reserved_at_480[0x1]; 1309 u8 tls_tx[0x1]; 1310 u8 reserved_at_482[0x1]; 1311 u8 log_max_l2_table[0x5]; 1312 u8 reserved_64[0x8]; 1313 u8 log_uar_page_sz[0x10]; 1314 1315 u8 reserved_65[0x20]; 1316 1317 u8 device_frequency_mhz[0x20]; 1318 1319 u8 device_frequency_khz[0x20]; 1320 1321 u8 reserved_at_500[0x20]; 1322 u8 num_of_uars_per_page[0x20]; 1323 u8 reserved_at_540[0x40]; 1324 1325 u8 log_max_atomic_size_qp[0x8]; 1326 u8 reserved_67[0x10]; 1327 u8 log_max_atomic_size_dc[0x8]; 1328 1329 u8 reserved_at_5a0[0x13]; 1330 u8 log_max_dek[0x5]; 1331 u8 reserved_at_5b8[0x4]; 1332 u8 mini_cqe_resp_stride_index[0x1]; 1333 u8 cqe_128_always[0x1]; 1334 u8 cqe_compression_128b[0x1]; 1335 1336 u8 cqe_compression[0x1]; 1337 1338 u8 cqe_compression_timeout[0x10]; 1339 u8 cqe_compression_max_num[0x10]; 1340 1341 u8 reserved_69[0x220]; 1342 }; 1343 1344 enum mlx5_flow_destination_type { 1345 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1346 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1347 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1348 }; 1349 1350 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1351 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1352 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1353 u8 reserved_0[0x40]; 1354 }; 1355 1356 struct mlx5_ifc_fte_match_param_bits { 1357 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1358 1359 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1360 1361 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1362 1363 u8 reserved_0[0xa00]; 1364 }; 1365 1366 enum { 1367 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1368 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1369 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1370 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1371 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1372 }; 1373 1374 struct mlx5_ifc_rx_hash_field_select_bits { 1375 u8 l3_prot_type[0x1]; 1376 u8 l4_prot_type[0x1]; 1377 u8 selected_fields[0x1e]; 1378 }; 1379 1380 struct mlx5_ifc_tls_capabilities_bits { 1381 u8 tls_1_2_aes_gcm_128[0x1]; 1382 u8 tls_1_3_aes_gcm_128[0x1]; 1383 u8 tls_1_2_aes_gcm_256[0x1]; 1384 u8 tls_1_3_aes_gcm_256[0x1]; 1385 u8 reserved_at_4[0x1c]; 1386 1387 u8 reserved_at_20[0x7e0]; 1388 }; 1389 1390 enum { 1391 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1392 MLX5_WQ_TYPE_CYCLIC = 0x1, 1393 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1394 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1395 }; 1396 1397 enum rq_type { 1398 RQ_TYPE_NONE, 1399 RQ_TYPE_STRIDE, 1400 }; 1401 1402 enum { 1403 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1404 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1405 }; 1406 1407 struct mlx5_ifc_wq_bits { 1408 u8 wq_type[0x4]; 1409 u8 wq_signature[0x1]; 1410 u8 end_padding_mode[0x2]; 1411 u8 cd_slave[0x1]; 1412 u8 reserved_0[0x18]; 1413 1414 u8 hds_skip_first_sge[0x1]; 1415 u8 log2_hds_buf_size[0x3]; 1416 u8 reserved_1[0x7]; 1417 u8 page_offset[0x5]; 1418 u8 lwm[0x10]; 1419 1420 u8 reserved_2[0x8]; 1421 u8 pd[0x18]; 1422 1423 u8 reserved_3[0x8]; 1424 u8 uar_page[0x18]; 1425 1426 u8 dbr_addr[0x40]; 1427 1428 u8 hw_counter[0x20]; 1429 1430 u8 sw_counter[0x20]; 1431 1432 u8 reserved_4[0xc]; 1433 u8 log_wq_stride[0x4]; 1434 u8 reserved_5[0x3]; 1435 u8 log_wq_pg_sz[0x5]; 1436 u8 reserved_6[0x3]; 1437 u8 log_wq_sz[0x5]; 1438 1439 u8 reserved_7[0x15]; 1440 u8 single_wqe_log_num_of_strides[0x3]; 1441 u8 two_byte_shift_en[0x1]; 1442 u8 reserved_8[0x4]; 1443 u8 single_stride_log_num_of_bytes[0x3]; 1444 1445 u8 reserved_9[0x4c0]; 1446 1447 struct mlx5_ifc_cmd_pas_bits pas[0]; 1448 }; 1449 1450 struct mlx5_ifc_rq_num_bits { 1451 u8 reserved_0[0x8]; 1452 u8 rq_num[0x18]; 1453 }; 1454 1455 struct mlx5_ifc_mac_address_layout_bits { 1456 u8 reserved_0[0x10]; 1457 u8 mac_addr_47_32[0x10]; 1458 1459 u8 mac_addr_31_0[0x20]; 1460 }; 1461 1462 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1463 u8 reserved_0[0xa0]; 1464 1465 u8 min_time_between_cnps[0x20]; 1466 1467 u8 reserved_1[0x12]; 1468 u8 cnp_dscp[0x6]; 1469 u8 reserved_2[0x4]; 1470 u8 cnp_prio_mode[0x1]; 1471 u8 cnp_802p_prio[0x3]; 1472 1473 u8 reserved_3[0x720]; 1474 }; 1475 1476 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1477 u8 reserved_0[0x60]; 1478 1479 u8 reserved_1[0x4]; 1480 u8 clamp_tgt_rate[0x1]; 1481 u8 reserved_2[0x3]; 1482 u8 clamp_tgt_rate_after_time_inc[0x1]; 1483 u8 reserved_3[0x17]; 1484 1485 u8 reserved_4[0x20]; 1486 1487 u8 rpg_time_reset[0x20]; 1488 1489 u8 rpg_byte_reset[0x20]; 1490 1491 u8 rpg_threshold[0x20]; 1492 1493 u8 rpg_max_rate[0x20]; 1494 1495 u8 rpg_ai_rate[0x20]; 1496 1497 u8 rpg_hai_rate[0x20]; 1498 1499 u8 rpg_gd[0x20]; 1500 1501 u8 rpg_min_dec_fac[0x20]; 1502 1503 u8 rpg_min_rate[0x20]; 1504 1505 u8 reserved_5[0xe0]; 1506 1507 u8 rate_to_set_on_first_cnp[0x20]; 1508 1509 u8 dce_tcp_g[0x20]; 1510 1511 u8 dce_tcp_rtt[0x20]; 1512 1513 u8 rate_reduce_monitor_period[0x20]; 1514 1515 u8 reserved_6[0x20]; 1516 1517 u8 initial_alpha_value[0x20]; 1518 1519 u8 reserved_7[0x4a0]; 1520 }; 1521 1522 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1523 u8 reserved_0[0x80]; 1524 1525 u8 rppp_max_rps[0x20]; 1526 1527 u8 rpg_time_reset[0x20]; 1528 1529 u8 rpg_byte_reset[0x20]; 1530 1531 u8 rpg_threshold[0x20]; 1532 1533 u8 rpg_max_rate[0x20]; 1534 1535 u8 rpg_ai_rate[0x20]; 1536 1537 u8 rpg_hai_rate[0x20]; 1538 1539 u8 rpg_gd[0x20]; 1540 1541 u8 rpg_min_dec_fac[0x20]; 1542 1543 u8 rpg_min_rate[0x20]; 1544 1545 u8 reserved_1[0x640]; 1546 }; 1547 1548 enum { 1549 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1550 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1551 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1552 }; 1553 1554 struct mlx5_ifc_resize_field_select_bits { 1555 u8 resize_field_select[0x20]; 1556 }; 1557 1558 enum { 1559 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1560 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1561 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1562 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1563 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1564 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1565 }; 1566 1567 struct mlx5_ifc_modify_field_select_bits { 1568 u8 modify_field_select[0x20]; 1569 }; 1570 1571 struct mlx5_ifc_field_select_r_roce_np_bits { 1572 u8 field_select_r_roce_np[0x20]; 1573 }; 1574 1575 enum { 1576 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1577 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1578 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1579 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1580 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1581 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1582 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1583 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1584 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1585 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1586 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1587 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1588 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1589 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1590 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1591 }; 1592 1593 struct mlx5_ifc_field_select_r_roce_rp_bits { 1594 u8 field_select_r_roce_rp[0x20]; 1595 }; 1596 1597 enum { 1598 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1599 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1600 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1601 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1602 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1603 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1604 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1605 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1606 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1607 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1608 }; 1609 1610 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1611 u8 field_select_8021qaurp[0x20]; 1612 }; 1613 1614 struct mlx5_ifc_pptb_reg_bits { 1615 u8 reserved_at_0[0x2]; 1616 u8 mm[0x2]; 1617 u8 reserved_at_4[0x4]; 1618 u8 local_port[0x8]; 1619 u8 reserved_at_10[0x6]; 1620 u8 cm[0x1]; 1621 u8 um[0x1]; 1622 u8 pm[0x8]; 1623 1624 u8 prio_x_buff[0x20]; 1625 1626 u8 pm_msb[0x8]; 1627 u8 reserved_at_48[0x10]; 1628 u8 ctrl_buff[0x4]; 1629 u8 untagged_buff[0x4]; 1630 }; 1631 1632 struct mlx5_ifc_dcbx_app_reg_bits { 1633 u8 reserved_0[0x8]; 1634 u8 port_number[0x8]; 1635 u8 reserved_1[0x10]; 1636 1637 u8 reserved_2[0x1a]; 1638 u8 num_app_prio[0x6]; 1639 1640 u8 reserved_3[0x40]; 1641 1642 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1643 }; 1644 1645 struct mlx5_ifc_dcbx_param_reg_bits { 1646 u8 dcbx_cee_cap[0x1]; 1647 u8 dcbx_ieee_cap[0x1]; 1648 u8 dcbx_standby_cap[0x1]; 1649 u8 reserved_0[0x5]; 1650 u8 port_number[0x8]; 1651 u8 reserved_1[0xa]; 1652 u8 max_application_table_size[0x6]; 1653 1654 u8 reserved_2[0x15]; 1655 u8 version_oper[0x3]; 1656 u8 reserved_3[0x5]; 1657 u8 version_admin[0x3]; 1658 1659 u8 willing_admin[0x1]; 1660 u8 reserved_4[0x3]; 1661 u8 pfc_cap_oper[0x4]; 1662 u8 reserved_5[0x4]; 1663 u8 pfc_cap_admin[0x4]; 1664 u8 reserved_6[0x4]; 1665 u8 num_of_tc_oper[0x4]; 1666 u8 reserved_7[0x4]; 1667 u8 num_of_tc_admin[0x4]; 1668 1669 u8 remote_willing[0x1]; 1670 u8 reserved_8[0x3]; 1671 u8 remote_pfc_cap[0x4]; 1672 u8 reserved_9[0x14]; 1673 u8 remote_num_of_tc[0x4]; 1674 1675 u8 reserved_10[0x18]; 1676 u8 error[0x8]; 1677 1678 u8 reserved_11[0x160]; 1679 }; 1680 1681 struct mlx5_ifc_qhll_bits { 1682 u8 reserved_at_0[0x8]; 1683 u8 local_port[0x8]; 1684 u8 reserved_at_10[0x10]; 1685 1686 u8 reserved_at_20[0x1b]; 1687 u8 hll_time[0x5]; 1688 1689 u8 stall_en[0x1]; 1690 u8 reserved_at_41[0x1c]; 1691 u8 stall_cnt[0x3]; 1692 }; 1693 1694 struct mlx5_ifc_qetcr_reg_bits { 1695 u8 operation_type[0x2]; 1696 u8 cap_local_admin[0x1]; 1697 u8 cap_remote_admin[0x1]; 1698 u8 reserved_0[0x4]; 1699 u8 port_number[0x8]; 1700 u8 reserved_1[0x10]; 1701 1702 u8 reserved_2[0x20]; 1703 1704 u8 tc[8][0x40]; 1705 1706 u8 global_configuration[0x40]; 1707 }; 1708 1709 struct mlx5_ifc_nodnic_ring_config_reg_bits { 1710 u8 queue_address_63_32[0x20]; 1711 1712 u8 queue_address_31_12[0x14]; 1713 u8 reserved_0[0x6]; 1714 u8 log_size[0x6]; 1715 1716 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1717 1718 u8 reserved_1[0x8]; 1719 u8 queue_number[0x18]; 1720 1721 u8 q_key[0x20]; 1722 1723 u8 reserved_2[0x10]; 1724 u8 pkey_index[0x10]; 1725 1726 u8 reserved_3[0x40]; 1727 }; 1728 1729 struct mlx5_ifc_nodnic_cq_arming_word_bits { 1730 u8 reserved_0[0x8]; 1731 u8 cq_ci[0x10]; 1732 u8 reserved_1[0x8]; 1733 }; 1734 1735 enum { 1736 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1737 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1738 }; 1739 1740 enum { 1741 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1742 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1743 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1744 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1745 }; 1746 1747 struct mlx5_ifc_nodnic_event_word_bits { 1748 u8 driver_reset_needed[0x1]; 1749 u8 port_management_change_event[0x1]; 1750 u8 reserved_0[0x19]; 1751 u8 link_type[0x1]; 1752 u8 port_state[0x4]; 1753 }; 1754 1755 struct mlx5_ifc_nic_vport_change_event_bits { 1756 u8 reserved_0[0x10]; 1757 u8 vport_num[0x10]; 1758 1759 u8 reserved_1[0xc0]; 1760 }; 1761 1762 struct mlx5_ifc_pages_req_event_bits { 1763 u8 reserved_0[0x10]; 1764 u8 function_id[0x10]; 1765 1766 u8 num_pages[0x20]; 1767 1768 u8 reserved_1[0xa0]; 1769 }; 1770 1771 struct mlx5_ifc_cmd_inter_comp_event_bits { 1772 u8 command_completion_vector[0x20]; 1773 1774 u8 reserved_0[0xc0]; 1775 }; 1776 1777 struct mlx5_ifc_stall_vl_event_bits { 1778 u8 reserved_0[0x18]; 1779 u8 port_num[0x1]; 1780 u8 reserved_1[0x3]; 1781 u8 vl[0x4]; 1782 1783 u8 reserved_2[0xa0]; 1784 }; 1785 1786 struct mlx5_ifc_db_bf_congestion_event_bits { 1787 u8 event_subtype[0x8]; 1788 u8 reserved_0[0x8]; 1789 u8 congestion_level[0x8]; 1790 u8 reserved_1[0x8]; 1791 1792 u8 reserved_2[0xa0]; 1793 }; 1794 1795 struct mlx5_ifc_gpio_event_bits { 1796 u8 reserved_0[0x60]; 1797 1798 u8 gpio_event_hi[0x20]; 1799 1800 u8 gpio_event_lo[0x20]; 1801 1802 u8 reserved_1[0x40]; 1803 }; 1804 1805 struct mlx5_ifc_port_state_change_event_bits { 1806 u8 reserved_0[0x40]; 1807 1808 u8 port_num[0x4]; 1809 u8 reserved_1[0x1c]; 1810 1811 u8 reserved_2[0x80]; 1812 }; 1813 1814 struct mlx5_ifc_dropped_packet_logged_bits { 1815 u8 reserved_0[0xe0]; 1816 }; 1817 1818 enum { 1819 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1820 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1821 }; 1822 1823 struct mlx5_ifc_cq_error_bits { 1824 u8 reserved_0[0x8]; 1825 u8 cqn[0x18]; 1826 1827 u8 reserved_1[0x20]; 1828 1829 u8 reserved_2[0x18]; 1830 u8 syndrome[0x8]; 1831 1832 u8 reserved_3[0x80]; 1833 }; 1834 1835 struct mlx5_ifc_rdma_page_fault_event_bits { 1836 u8 bytes_commited[0x20]; 1837 1838 u8 r_key[0x20]; 1839 1840 u8 reserved_0[0x10]; 1841 u8 packet_len[0x10]; 1842 1843 u8 rdma_op_len[0x20]; 1844 1845 u8 rdma_va[0x40]; 1846 1847 u8 reserved_1[0x5]; 1848 u8 rdma[0x1]; 1849 u8 write[0x1]; 1850 u8 requestor[0x1]; 1851 u8 qp_number[0x18]; 1852 }; 1853 1854 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1855 u8 bytes_committed[0x20]; 1856 1857 u8 reserved_0[0x10]; 1858 u8 wqe_index[0x10]; 1859 1860 u8 reserved_1[0x10]; 1861 u8 len[0x10]; 1862 1863 u8 reserved_2[0x60]; 1864 1865 u8 reserved_3[0x5]; 1866 u8 rdma[0x1]; 1867 u8 write_read[0x1]; 1868 u8 requestor[0x1]; 1869 u8 qpn[0x18]; 1870 }; 1871 1872 enum { 1873 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1874 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1875 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1876 }; 1877 1878 struct mlx5_ifc_qp_events_bits { 1879 u8 reserved_0[0xa0]; 1880 1881 u8 type[0x8]; 1882 u8 reserved_1[0x18]; 1883 1884 u8 reserved_2[0x8]; 1885 u8 qpn_rqn_sqn[0x18]; 1886 }; 1887 1888 struct mlx5_ifc_dct_events_bits { 1889 u8 reserved_0[0xc0]; 1890 1891 u8 reserved_1[0x8]; 1892 u8 dct_number[0x18]; 1893 }; 1894 1895 struct mlx5_ifc_comp_event_bits { 1896 u8 reserved_0[0xc0]; 1897 1898 u8 reserved_1[0x8]; 1899 u8 cq_number[0x18]; 1900 }; 1901 1902 struct mlx5_ifc_fw_version_bits { 1903 u8 major[0x10]; 1904 u8 reserved_0[0x10]; 1905 1906 u8 minor[0x10]; 1907 u8 subminor[0x10]; 1908 1909 u8 second[0x8]; 1910 u8 minute[0x8]; 1911 u8 hour[0x8]; 1912 u8 reserved_1[0x8]; 1913 1914 u8 year[0x10]; 1915 u8 month[0x8]; 1916 u8 day[0x8]; 1917 }; 1918 1919 enum { 1920 MLX5_QPC_STATE_RST = 0x0, 1921 MLX5_QPC_STATE_INIT = 0x1, 1922 MLX5_QPC_STATE_RTR = 0x2, 1923 MLX5_QPC_STATE_RTS = 0x3, 1924 MLX5_QPC_STATE_SQER = 0x4, 1925 MLX5_QPC_STATE_SQD = 0x5, 1926 MLX5_QPC_STATE_ERR = 0x6, 1927 MLX5_QPC_STATE_SUSPENDED = 0x9, 1928 }; 1929 1930 enum { 1931 MLX5_QPC_ST_RC = 0x0, 1932 MLX5_QPC_ST_UC = 0x1, 1933 MLX5_QPC_ST_UD = 0x2, 1934 MLX5_QPC_ST_XRC = 0x3, 1935 MLX5_QPC_ST_DCI = 0x5, 1936 MLX5_QPC_ST_QP0 = 0x7, 1937 MLX5_QPC_ST_QP1 = 0x8, 1938 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1939 MLX5_QPC_ST_REG_UMR = 0xc, 1940 }; 1941 1942 enum { 1943 MLX5_QP_PM_ARMED = 0x0, 1944 MLX5_QP_PM_REARM = 0x1, 1945 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1946 MLX5_QP_PM_MIGRATED = 0x3, 1947 }; 1948 1949 enum { 1950 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1951 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1952 }; 1953 1954 enum { 1955 MLX5_QPC_MTU_256_BYTES = 0x1, 1956 MLX5_QPC_MTU_512_BYTES = 0x2, 1957 MLX5_QPC_MTU_1K_BYTES = 0x3, 1958 MLX5_QPC_MTU_2K_BYTES = 0x4, 1959 MLX5_QPC_MTU_4K_BYTES = 0x5, 1960 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1961 }; 1962 1963 enum { 1964 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1965 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1966 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1967 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1968 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1969 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1970 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1971 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1972 }; 1973 1974 enum { 1975 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1976 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1977 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1978 }; 1979 1980 enum { 1981 MLX5_QPC_CS_RES_DISABLE = 0x0, 1982 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1983 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1984 }; 1985 1986 enum { 1987 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 1988 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 1989 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 1990 }; 1991 1992 struct mlx5_ifc_qpc_bits { 1993 u8 state[0x4]; 1994 u8 lag_tx_port_affinity[0x4]; 1995 u8 st[0x8]; 1996 u8 reserved_1[0x3]; 1997 u8 pm_state[0x2]; 1998 u8 reserved_2[0x7]; 1999 u8 end_padding_mode[0x2]; 2000 u8 reserved_3[0x2]; 2001 2002 u8 wq_signature[0x1]; 2003 u8 block_lb_mc[0x1]; 2004 u8 atomic_like_write_en[0x1]; 2005 u8 latency_sensitive[0x1]; 2006 u8 reserved_4[0x1]; 2007 u8 drain_sigerr[0x1]; 2008 u8 reserved_5[0x2]; 2009 u8 pd[0x18]; 2010 2011 u8 mtu[0x3]; 2012 u8 log_msg_max[0x5]; 2013 u8 reserved_6[0x1]; 2014 u8 log_rq_size[0x4]; 2015 u8 log_rq_stride[0x3]; 2016 u8 no_sq[0x1]; 2017 u8 log_sq_size[0x4]; 2018 u8 reserved_at_55[0x3]; 2019 u8 ts_format[0x2]; 2020 u8 reserved_at_5a[0x1]; 2021 u8 rlky[0x1]; 2022 u8 ulp_stateless_offload_mode[0x4]; 2023 2024 u8 counter_set_id[0x8]; 2025 u8 uar_page[0x18]; 2026 2027 u8 reserved_8[0x8]; 2028 u8 user_index[0x18]; 2029 2030 u8 reserved_9[0x3]; 2031 u8 log_page_size[0x5]; 2032 u8 remote_qpn[0x18]; 2033 2034 struct mlx5_ifc_ads_bits primary_address_path; 2035 2036 struct mlx5_ifc_ads_bits secondary_address_path; 2037 2038 u8 log_ack_req_freq[0x4]; 2039 u8 reserved_10[0x4]; 2040 u8 log_sra_max[0x3]; 2041 u8 reserved_11[0x2]; 2042 u8 retry_count[0x3]; 2043 u8 rnr_retry[0x3]; 2044 u8 reserved_12[0x1]; 2045 u8 fre[0x1]; 2046 u8 cur_rnr_retry[0x3]; 2047 u8 cur_retry_count[0x3]; 2048 u8 reserved_13[0x5]; 2049 2050 u8 reserved_14[0x20]; 2051 2052 u8 reserved_15[0x8]; 2053 u8 next_send_psn[0x18]; 2054 2055 u8 reserved_16[0x8]; 2056 u8 cqn_snd[0x18]; 2057 2058 u8 reserved_at_400[0x8]; 2059 2060 u8 deth_sqpn[0x18]; 2061 u8 reserved_17[0x20]; 2062 2063 u8 reserved_18[0x8]; 2064 u8 last_acked_psn[0x18]; 2065 2066 u8 reserved_19[0x8]; 2067 u8 ssn[0x18]; 2068 2069 u8 reserved_20[0x8]; 2070 u8 log_rra_max[0x3]; 2071 u8 reserved_21[0x1]; 2072 u8 atomic_mode[0x4]; 2073 u8 rre[0x1]; 2074 u8 rwe[0x1]; 2075 u8 rae[0x1]; 2076 u8 reserved_22[0x1]; 2077 u8 page_offset[0x6]; 2078 u8 reserved_23[0x3]; 2079 u8 cd_slave_receive[0x1]; 2080 u8 cd_slave_send[0x1]; 2081 u8 cd_master[0x1]; 2082 2083 u8 reserved_24[0x3]; 2084 u8 min_rnr_nak[0x5]; 2085 u8 next_rcv_psn[0x18]; 2086 2087 u8 reserved_25[0x8]; 2088 u8 xrcd[0x18]; 2089 2090 u8 reserved_26[0x8]; 2091 u8 cqn_rcv[0x18]; 2092 2093 u8 dbr_addr[0x40]; 2094 2095 u8 q_key[0x20]; 2096 2097 u8 reserved_27[0x5]; 2098 u8 rq_type[0x3]; 2099 u8 srqn_rmpn[0x18]; 2100 2101 u8 reserved_28[0x8]; 2102 u8 rmsn[0x18]; 2103 2104 u8 hw_sq_wqebb_counter[0x10]; 2105 u8 sw_sq_wqebb_counter[0x10]; 2106 2107 u8 hw_rq_counter[0x20]; 2108 2109 u8 sw_rq_counter[0x20]; 2110 2111 u8 reserved_29[0x20]; 2112 2113 u8 reserved_30[0xf]; 2114 u8 cgs[0x1]; 2115 u8 cs_req[0x8]; 2116 u8 cs_res[0x8]; 2117 2118 u8 dc_access_key[0x40]; 2119 2120 u8 rdma_active[0x1]; 2121 u8 comm_est[0x1]; 2122 u8 suspended[0x1]; 2123 u8 reserved_31[0x5]; 2124 u8 send_msg_psn[0x18]; 2125 2126 u8 reserved_32[0x8]; 2127 u8 rcv_msg_psn[0x18]; 2128 2129 u8 rdma_va[0x40]; 2130 2131 u8 rdma_key[0x20]; 2132 2133 u8 reserved_33[0x20]; 2134 }; 2135 2136 struct mlx5_ifc_roce_addr_layout_bits { 2137 u8 source_l3_address[16][0x8]; 2138 2139 u8 reserved_0[0x3]; 2140 u8 vlan_valid[0x1]; 2141 u8 vlan_id[0xc]; 2142 u8 source_mac_47_32[0x10]; 2143 2144 u8 source_mac_31_0[0x20]; 2145 2146 u8 reserved_1[0x14]; 2147 u8 roce_l3_type[0x4]; 2148 u8 roce_version[0x8]; 2149 2150 u8 reserved_2[0x20]; 2151 }; 2152 2153 struct mlx5_ifc_rdbc_bits { 2154 u8 reserved_0[0x1c]; 2155 u8 type[0x4]; 2156 2157 u8 reserved_1[0x20]; 2158 2159 u8 reserved_2[0x8]; 2160 u8 psn[0x18]; 2161 2162 u8 rkey[0x20]; 2163 2164 u8 address[0x40]; 2165 2166 u8 byte_count[0x20]; 2167 2168 u8 reserved_3[0x20]; 2169 2170 u8 atomic_resp[32][0x8]; 2171 }; 2172 2173 enum { 2174 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2175 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2176 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2177 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2178 }; 2179 2180 struct mlx5_ifc_flow_context_bits { 2181 u8 reserved_0[0x20]; 2182 2183 u8 group_id[0x20]; 2184 2185 u8 reserved_1[0x8]; 2186 u8 flow_tag[0x18]; 2187 2188 u8 reserved_2[0x10]; 2189 u8 action[0x10]; 2190 2191 u8 reserved_3[0x8]; 2192 u8 destination_list_size[0x18]; 2193 2194 u8 reserved_4[0x8]; 2195 u8 flow_counter_list_size[0x18]; 2196 2197 u8 reserved_5[0x140]; 2198 2199 struct mlx5_ifc_fte_match_param_bits match_value; 2200 2201 u8 reserved_6[0x600]; 2202 2203 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2204 }; 2205 2206 enum { 2207 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2208 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2209 }; 2210 2211 struct mlx5_ifc_xrc_srqc_bits { 2212 u8 state[0x4]; 2213 u8 log_xrc_srq_size[0x4]; 2214 u8 reserved_0[0x18]; 2215 2216 u8 wq_signature[0x1]; 2217 u8 cont_srq[0x1]; 2218 u8 reserved_1[0x1]; 2219 u8 rlky[0x1]; 2220 u8 basic_cyclic_rcv_wqe[0x1]; 2221 u8 log_rq_stride[0x3]; 2222 u8 xrcd[0x18]; 2223 2224 u8 page_offset[0x6]; 2225 u8 reserved_2[0x2]; 2226 u8 cqn[0x18]; 2227 2228 u8 reserved_3[0x20]; 2229 2230 u8 reserved_4[0x2]; 2231 u8 log_page_size[0x6]; 2232 u8 user_index[0x18]; 2233 2234 u8 reserved_5[0x20]; 2235 2236 u8 reserved_6[0x8]; 2237 u8 pd[0x18]; 2238 2239 u8 lwm[0x10]; 2240 u8 wqe_cnt[0x10]; 2241 2242 u8 reserved_7[0x40]; 2243 2244 u8 db_record_addr_h[0x20]; 2245 2246 u8 db_record_addr_l[0x1e]; 2247 u8 reserved_8[0x2]; 2248 2249 u8 reserved_9[0x80]; 2250 }; 2251 2252 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2253 u8 counter_error_queues[0x20]; 2254 2255 u8 total_error_queues[0x20]; 2256 2257 u8 send_queue_priority_update_flow[0x20]; 2258 2259 u8 reserved_at_60[0x20]; 2260 2261 u8 nic_receive_steering_discard[0x40]; 2262 2263 u8 receive_discard_vport_down[0x40]; 2264 2265 u8 transmit_discard_vport_down[0x40]; 2266 2267 u8 reserved_at_140[0xec0]; 2268 }; 2269 2270 struct mlx5_ifc_traffic_counter_bits { 2271 u8 packets[0x40]; 2272 2273 u8 octets[0x40]; 2274 }; 2275 2276 struct mlx5_ifc_tisc_bits { 2277 u8 strict_lag_tx_port_affinity[0x1]; 2278 u8 tls_en[0x1]; 2279 u8 reserved_at_2[0x2]; 2280 u8 lag_tx_port_affinity[0x04]; 2281 2282 u8 reserved_at_8[0x4]; 2283 u8 prio[0x4]; 2284 u8 reserved_1[0x10]; 2285 2286 u8 reserved_2[0x100]; 2287 2288 u8 reserved_3[0x8]; 2289 u8 transport_domain[0x18]; 2290 2291 u8 reserved_4[0x8]; 2292 u8 underlay_qpn[0x18]; 2293 2294 u8 reserved_5[0x8]; 2295 u8 pd[0x18]; 2296 2297 u8 reserved_6[0x380]; 2298 }; 2299 2300 enum { 2301 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2302 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2303 }; 2304 2305 enum { 2306 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2307 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2308 }; 2309 2310 enum { 2311 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2312 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2313 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2314 }; 2315 2316 enum { 2317 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2318 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2319 }; 2320 2321 struct mlx5_ifc_tirc_bits { 2322 u8 reserved_0[0x20]; 2323 2324 u8 disp_type[0x4]; 2325 u8 tls_en[0x1]; 2326 u8 reserved_at_25[0x1b]; 2327 2328 u8 reserved_2[0x40]; 2329 2330 u8 reserved_3[0x4]; 2331 u8 lro_timeout_period_usecs[0x10]; 2332 u8 lro_enable_mask[0x4]; 2333 u8 lro_max_msg_sz[0x8]; 2334 2335 u8 reserved_4[0x40]; 2336 2337 u8 reserved_5[0x8]; 2338 u8 inline_rqn[0x18]; 2339 2340 u8 rx_hash_symmetric[0x1]; 2341 u8 reserved_6[0x1]; 2342 u8 tunneled_offload_en[0x1]; 2343 u8 reserved_7[0x5]; 2344 u8 indirect_table[0x18]; 2345 2346 u8 rx_hash_fn[0x4]; 2347 u8 reserved_8[0x2]; 2348 u8 self_lb_en[0x2]; 2349 u8 transport_domain[0x18]; 2350 2351 u8 rx_hash_toeplitz_key[10][0x20]; 2352 2353 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2354 2355 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2356 2357 u8 reserved_9[0x4c0]; 2358 }; 2359 2360 enum { 2361 MLX5_SRQC_STATE_GOOD = 0x0, 2362 MLX5_SRQC_STATE_ERROR = 0x1, 2363 }; 2364 2365 struct mlx5_ifc_srqc_bits { 2366 u8 state[0x4]; 2367 u8 log_srq_size[0x4]; 2368 u8 reserved_0[0x18]; 2369 2370 u8 wq_signature[0x1]; 2371 u8 cont_srq[0x1]; 2372 u8 reserved_1[0x1]; 2373 u8 rlky[0x1]; 2374 u8 reserved_2[0x1]; 2375 u8 log_rq_stride[0x3]; 2376 u8 xrcd[0x18]; 2377 2378 u8 page_offset[0x6]; 2379 u8 reserved_3[0x2]; 2380 u8 cqn[0x18]; 2381 2382 u8 reserved_4[0x20]; 2383 2384 u8 reserved_5[0x2]; 2385 u8 log_page_size[0x6]; 2386 u8 reserved_6[0x18]; 2387 2388 u8 reserved_7[0x20]; 2389 2390 u8 reserved_8[0x8]; 2391 u8 pd[0x18]; 2392 2393 u8 lwm[0x10]; 2394 u8 wqe_cnt[0x10]; 2395 2396 u8 reserved_9[0x40]; 2397 2398 u8 dbr_addr[0x40]; 2399 2400 u8 reserved_10[0x80]; 2401 }; 2402 2403 enum { 2404 MLX5_SQC_STATE_RST = 0x0, 2405 MLX5_SQC_STATE_RDY = 0x1, 2406 MLX5_SQC_STATE_ERR = 0x3, 2407 }; 2408 2409 enum { 2410 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2411 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2412 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2413 }; 2414 2415 struct mlx5_ifc_sqc_bits { 2416 u8 rlkey[0x1]; 2417 u8 cd_master[0x1]; 2418 u8 fre[0x1]; 2419 u8 flush_in_error_en[0x1]; 2420 u8 allow_multi_pkt_send_wqe[0x1]; 2421 u8 min_wqe_inline_mode[0x3]; 2422 u8 state[0x4]; 2423 u8 reg_umr[0x1]; 2424 u8 allow_swp[0x1]; 2425 u8 reserved_at_e[0xc]; 2426 u8 ts_format[0x2]; 2427 u8 reserved_at_1c[0x4]; 2428 2429 u8 reserved_1[0x8]; 2430 u8 user_index[0x18]; 2431 2432 u8 reserved_2[0x8]; 2433 u8 cqn[0x18]; 2434 2435 u8 reserved_3[0x80]; 2436 2437 u8 qos_para_vport_number[0x10]; 2438 u8 packet_pacing_rate_limit_index[0x10]; 2439 2440 u8 tis_lst_sz[0x10]; 2441 u8 reserved_4[0x10]; 2442 2443 u8 reserved_5[0x40]; 2444 2445 u8 reserved_6[0x8]; 2446 u8 tis_num_0[0x18]; 2447 2448 struct mlx5_ifc_wq_bits wq; 2449 }; 2450 2451 enum { 2452 MLX5_TSAR_TYPE_DWRR = 0, 2453 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2454 MLX5_TSAR_TYPE_ETS = 2 2455 }; 2456 2457 struct mlx5_ifc_tsar_element_attributes_bits { 2458 u8 reserved_0[0x8]; 2459 u8 tsar_type[0x8]; 2460 u8 reserved_1[0x10]; 2461 }; 2462 2463 struct mlx5_ifc_vport_element_attributes_bits { 2464 u8 reserved_0[0x10]; 2465 u8 vport_number[0x10]; 2466 }; 2467 2468 struct mlx5_ifc_vport_tc_element_attributes_bits { 2469 u8 traffic_class[0x10]; 2470 u8 vport_number[0x10]; 2471 }; 2472 2473 struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2474 u8 reserved_0[0x0C]; 2475 u8 traffic_class[0x04]; 2476 u8 qos_para_vport_number[0x10]; 2477 }; 2478 2479 enum { 2480 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2481 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2482 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2483 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2484 }; 2485 2486 struct mlx5_ifc_scheduling_context_bits { 2487 u8 element_type[0x8]; 2488 u8 reserved_at_8[0x18]; 2489 2490 u8 element_attributes[0x20]; 2491 2492 u8 parent_element_id[0x20]; 2493 2494 u8 reserved_at_60[0x40]; 2495 2496 u8 bw_share[0x20]; 2497 2498 u8 max_average_bw[0x20]; 2499 2500 u8 reserved_at_e0[0x120]; 2501 }; 2502 2503 struct mlx5_ifc_rqtc_bits { 2504 u8 reserved_0[0xa0]; 2505 2506 u8 reserved_1[0x10]; 2507 u8 rqt_max_size[0x10]; 2508 2509 u8 reserved_2[0x10]; 2510 u8 rqt_actual_size[0x10]; 2511 2512 u8 reserved_3[0x6a0]; 2513 2514 struct mlx5_ifc_rq_num_bits rq_num[0]; 2515 }; 2516 2517 enum { 2518 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2519 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2520 }; 2521 2522 enum { 2523 MLX5_RQC_STATE_RST = 0x0, 2524 MLX5_RQC_STATE_RDY = 0x1, 2525 MLX5_RQC_STATE_ERR = 0x3, 2526 }; 2527 2528 enum { 2529 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2530 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2531 }; 2532 2533 enum { 2534 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2535 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2536 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2537 }; 2538 2539 struct mlx5_ifc_rqc_bits { 2540 u8 rlkey[0x1]; 2541 u8 delay_drop_en[0x1]; 2542 u8 scatter_fcs[0x1]; 2543 u8 vlan_strip_disable[0x1]; 2544 u8 mem_rq_type[0x4]; 2545 u8 state[0x4]; 2546 u8 reserved_1[0x1]; 2547 u8 flush_in_error_en[0x1]; 2548 u8 reserved_at_e[0xc]; 2549 u8 ts_format[0x2]; 2550 u8 reserved_at_1c[0x4]; 2551 2552 u8 reserved_3[0x8]; 2553 u8 user_index[0x18]; 2554 2555 u8 reserved_4[0x8]; 2556 u8 cqn[0x18]; 2557 2558 u8 counter_set_id[0x8]; 2559 u8 reserved_5[0x18]; 2560 2561 u8 reserved_6[0x8]; 2562 u8 rmpn[0x18]; 2563 2564 u8 reserved_7[0xe0]; 2565 2566 struct mlx5_ifc_wq_bits wq; 2567 }; 2568 2569 enum { 2570 MLX5_RMPC_STATE_RDY = 0x1, 2571 MLX5_RMPC_STATE_ERR = 0x3, 2572 }; 2573 2574 struct mlx5_ifc_rmpc_bits { 2575 u8 reserved_0[0x8]; 2576 u8 state[0x4]; 2577 u8 reserved_1[0x14]; 2578 2579 u8 basic_cyclic_rcv_wqe[0x1]; 2580 u8 reserved_2[0x1f]; 2581 2582 u8 reserved_3[0x140]; 2583 2584 struct mlx5_ifc_wq_bits wq; 2585 }; 2586 2587 enum { 2588 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2589 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2590 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2591 }; 2592 2593 struct mlx5_ifc_nic_vport_context_bits { 2594 u8 reserved_0[0x5]; 2595 u8 min_wqe_inline_mode[0x3]; 2596 u8 reserved_1[0x15]; 2597 u8 disable_mc_local_lb[0x1]; 2598 u8 disable_uc_local_lb[0x1]; 2599 u8 roce_en[0x1]; 2600 2601 u8 arm_change_event[0x1]; 2602 u8 reserved_2[0x1a]; 2603 u8 event_on_mtu[0x1]; 2604 u8 event_on_promisc_change[0x1]; 2605 u8 event_on_vlan_change[0x1]; 2606 u8 event_on_mc_address_change[0x1]; 2607 u8 event_on_uc_address_change[0x1]; 2608 2609 u8 reserved_3[0xe0]; 2610 2611 u8 reserved_4[0x10]; 2612 u8 mtu[0x10]; 2613 2614 u8 system_image_guid[0x40]; 2615 2616 u8 port_guid[0x40]; 2617 2618 u8 node_guid[0x40]; 2619 2620 u8 reserved_5[0x140]; 2621 2622 u8 qkey_violation_counter[0x10]; 2623 u8 reserved_6[0x10]; 2624 2625 u8 reserved_7[0x420]; 2626 2627 u8 promisc_uc[0x1]; 2628 u8 promisc_mc[0x1]; 2629 u8 promisc_all[0x1]; 2630 u8 reserved_8[0x2]; 2631 u8 allowed_list_type[0x3]; 2632 u8 reserved_9[0xc]; 2633 u8 allowed_list_size[0xc]; 2634 2635 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2636 2637 u8 reserved_10[0x20]; 2638 2639 u8 current_uc_mac_address[0][0x40]; 2640 }; 2641 2642 enum { 2643 MLX5_ACCESS_MODE_PA = 0x0, 2644 MLX5_ACCESS_MODE_MTT = 0x1, 2645 MLX5_ACCESS_MODE_KLM = 0x2, 2646 }; 2647 2648 struct mlx5_ifc_mkc_bits { 2649 u8 reserved_at_0[0x1]; 2650 u8 free[0x1]; 2651 u8 reserved_at_2[0x1]; 2652 u8 access_mode_4_2[0x3]; 2653 u8 reserved_at_6[0x7]; 2654 u8 relaxed_ordering_write[0x1]; 2655 u8 reserved_at_e[0x1]; 2656 u8 small_fence_on_rdma_read_response[0x1]; 2657 u8 umr_en[0x1]; 2658 u8 a[0x1]; 2659 u8 rw[0x1]; 2660 u8 rr[0x1]; 2661 u8 lw[0x1]; 2662 u8 lr[0x1]; 2663 u8 access_mode[0x2]; 2664 u8 reserved_2[0x8]; 2665 2666 u8 qpn[0x18]; 2667 u8 mkey_7_0[0x8]; 2668 2669 u8 reserved_3[0x20]; 2670 2671 u8 length64[0x1]; 2672 u8 bsf_en[0x1]; 2673 u8 sync_umr[0x1]; 2674 u8 reserved_4[0x2]; 2675 u8 expected_sigerr_count[0x1]; 2676 u8 reserved_5[0x1]; 2677 u8 en_rinval[0x1]; 2678 u8 pd[0x18]; 2679 2680 u8 start_addr[0x40]; 2681 2682 u8 len[0x40]; 2683 2684 u8 bsf_octword_size[0x20]; 2685 2686 u8 reserved_6[0x80]; 2687 2688 u8 translations_octword_size[0x20]; 2689 2690 u8 reserved_at_1c0[0x19]; 2691 u8 relaxed_ordering_read[0x1]; 2692 u8 reserved_at_1d9[0x1]; 2693 u8 log_page_size[0x5]; 2694 2695 u8 reserved_8[0x20]; 2696 }; 2697 2698 struct mlx5_ifc_pkey_bits { 2699 u8 reserved_0[0x10]; 2700 u8 pkey[0x10]; 2701 }; 2702 2703 struct mlx5_ifc_array128_auto_bits { 2704 u8 array128_auto[16][0x8]; 2705 }; 2706 2707 enum { 2708 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2709 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2710 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2711 }; 2712 2713 enum { 2714 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2715 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2716 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2717 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2718 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2719 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2720 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2721 }; 2722 2723 enum { 2724 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2725 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2726 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2727 }; 2728 2729 enum { 2730 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2731 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2732 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2733 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2734 }; 2735 2736 enum { 2737 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2738 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2739 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2740 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2741 }; 2742 2743 struct mlx5_ifc_hca_vport_context_bits { 2744 u8 field_select[0x20]; 2745 2746 u8 reserved_0[0xe0]; 2747 2748 u8 sm_virt_aware[0x1]; 2749 u8 has_smi[0x1]; 2750 u8 has_raw[0x1]; 2751 u8 grh_required[0x1]; 2752 u8 reserved_1[0x1]; 2753 u8 min_wqe_inline_mode[0x3]; 2754 u8 reserved_2[0x8]; 2755 u8 port_physical_state[0x4]; 2756 u8 vport_state_policy[0x4]; 2757 u8 port_state[0x4]; 2758 u8 vport_state[0x4]; 2759 2760 u8 reserved_3[0x20]; 2761 2762 u8 system_image_guid[0x40]; 2763 2764 u8 port_guid[0x40]; 2765 2766 u8 node_guid[0x40]; 2767 2768 u8 cap_mask1[0x20]; 2769 2770 u8 cap_mask1_field_select[0x20]; 2771 2772 u8 cap_mask2[0x20]; 2773 2774 u8 cap_mask2_field_select[0x20]; 2775 2776 u8 reserved_4[0x80]; 2777 2778 u8 lid[0x10]; 2779 u8 reserved_5[0x4]; 2780 u8 init_type_reply[0x4]; 2781 u8 lmc[0x3]; 2782 u8 subnet_timeout[0x5]; 2783 2784 u8 sm_lid[0x10]; 2785 u8 sm_sl[0x4]; 2786 u8 reserved_6[0xc]; 2787 2788 u8 qkey_violation_counter[0x10]; 2789 u8 pkey_violation_counter[0x10]; 2790 2791 u8 reserved_7[0xca0]; 2792 }; 2793 2794 union mlx5_ifc_hca_cap_union_bits { 2795 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2796 struct mlx5_ifc_odp_cap_bits odp_cap; 2797 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2798 struct mlx5_ifc_roce_cap_bits roce_cap; 2799 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2800 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2801 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2802 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2803 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2804 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2805 struct mlx5_ifc_qos_cap_bits qos_cap; 2806 struct mlx5_ifc_tls_capabilities_bits tls_capabilities; 2807 u8 reserved_0[0x8000]; 2808 }; 2809 2810 enum { 2811 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 2812 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 2813 }; 2814 2815 struct mlx5_ifc_flow_table_context_bits { 2816 u8 encap_en[0x1]; 2817 u8 decap_en[0x1]; 2818 u8 reserved_at_2[0x2]; 2819 u8 table_miss_action[0x4]; 2820 u8 level[0x8]; 2821 u8 reserved_at_10[0x8]; 2822 u8 log_size[0x8]; 2823 2824 u8 reserved_at_20[0x8]; 2825 u8 table_miss_id[0x18]; 2826 2827 u8 reserved_at_40[0x8]; 2828 u8 lag_master_next_table_id[0x18]; 2829 2830 u8 reserved_at_60[0xe0]; 2831 }; 2832 2833 struct mlx5_ifc_esw_vport_context_bits { 2834 u8 reserved_0[0x3]; 2835 u8 vport_svlan_strip[0x1]; 2836 u8 vport_cvlan_strip[0x1]; 2837 u8 vport_svlan_insert[0x1]; 2838 u8 vport_cvlan_insert[0x2]; 2839 u8 reserved_1[0x18]; 2840 2841 u8 reserved_2[0x20]; 2842 2843 u8 svlan_cfi[0x1]; 2844 u8 svlan_pcp[0x3]; 2845 u8 svlan_id[0xc]; 2846 u8 cvlan_cfi[0x1]; 2847 u8 cvlan_pcp[0x3]; 2848 u8 cvlan_id[0xc]; 2849 2850 u8 reserved_3[0x7a0]; 2851 }; 2852 2853 enum { 2854 MLX5_EQC_STATUS_OK = 0x0, 2855 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2856 }; 2857 2858 enum { 2859 MLX5_EQ_STATE_ARMED = 0x9, 2860 MLX5_EQ_STATE_FIRED = 0xa, 2861 }; 2862 2863 struct mlx5_ifc_eqc_bits { 2864 u8 status[0x4]; 2865 u8 reserved_0[0x9]; 2866 u8 ec[0x1]; 2867 u8 oi[0x1]; 2868 u8 reserved_1[0x5]; 2869 u8 st[0x4]; 2870 u8 reserved_2[0x8]; 2871 2872 u8 reserved_3[0x20]; 2873 2874 u8 reserved_4[0x14]; 2875 u8 page_offset[0x6]; 2876 u8 reserved_5[0x6]; 2877 2878 u8 reserved_6[0x3]; 2879 u8 log_eq_size[0x5]; 2880 u8 uar_page[0x18]; 2881 2882 u8 reserved_7[0x20]; 2883 2884 u8 reserved_8[0x18]; 2885 u8 intr[0x8]; 2886 2887 u8 reserved_9[0x3]; 2888 u8 log_page_size[0x5]; 2889 u8 reserved_10[0x18]; 2890 2891 u8 reserved_11[0x60]; 2892 2893 u8 reserved_12[0x8]; 2894 u8 consumer_counter[0x18]; 2895 2896 u8 reserved_13[0x8]; 2897 u8 producer_counter[0x18]; 2898 2899 u8 reserved_14[0x80]; 2900 }; 2901 2902 enum { 2903 MLX5_DCTC_STATE_ACTIVE = 0x0, 2904 MLX5_DCTC_STATE_DRAINING = 0x1, 2905 MLX5_DCTC_STATE_DRAINED = 0x2, 2906 }; 2907 2908 enum { 2909 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2910 MLX5_DCTC_CS_RES_NA = 0x1, 2911 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2912 }; 2913 2914 enum { 2915 MLX5_DCTC_MTU_256_BYTES = 0x1, 2916 MLX5_DCTC_MTU_512_BYTES = 0x2, 2917 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2918 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2919 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2920 }; 2921 2922 struct mlx5_ifc_dctc_bits { 2923 u8 reserved_0[0x4]; 2924 u8 state[0x4]; 2925 u8 reserved_1[0x18]; 2926 2927 u8 reserved_2[0x8]; 2928 u8 user_index[0x18]; 2929 2930 u8 reserved_3[0x8]; 2931 u8 cqn[0x18]; 2932 2933 u8 counter_set_id[0x8]; 2934 u8 atomic_mode[0x4]; 2935 u8 rre[0x1]; 2936 u8 rwe[0x1]; 2937 u8 rae[0x1]; 2938 u8 atomic_like_write_en[0x1]; 2939 u8 latency_sensitive[0x1]; 2940 u8 rlky[0x1]; 2941 u8 reserved_4[0xe]; 2942 2943 u8 reserved_5[0x8]; 2944 u8 cs_res[0x8]; 2945 u8 reserved_6[0x3]; 2946 u8 min_rnr_nak[0x5]; 2947 u8 reserved_7[0x8]; 2948 2949 u8 reserved_8[0x8]; 2950 u8 srqn[0x18]; 2951 2952 u8 reserved_9[0x8]; 2953 u8 pd[0x18]; 2954 2955 u8 tclass[0x8]; 2956 u8 reserved_10[0x4]; 2957 u8 flow_label[0x14]; 2958 2959 u8 dc_access_key[0x40]; 2960 2961 u8 reserved_11[0x5]; 2962 u8 mtu[0x3]; 2963 u8 port[0x8]; 2964 u8 pkey_index[0x10]; 2965 2966 u8 reserved_12[0x8]; 2967 u8 my_addr_index[0x8]; 2968 u8 reserved_13[0x8]; 2969 u8 hop_limit[0x8]; 2970 2971 u8 dc_access_key_violation_count[0x20]; 2972 2973 u8 reserved_14[0x14]; 2974 u8 dei_cfi[0x1]; 2975 u8 eth_prio[0x3]; 2976 u8 ecn[0x2]; 2977 u8 dscp[0x6]; 2978 2979 u8 reserved_15[0x40]; 2980 }; 2981 2982 enum { 2983 MLX5_CQC_STATUS_OK = 0x0, 2984 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2985 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2986 }; 2987 2988 enum { 2989 CQE_SIZE_64 = 0x0, 2990 CQE_SIZE_128 = 0x1, 2991 }; 2992 2993 enum { 2994 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2995 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2996 }; 2997 2998 enum { 2999 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 3000 MLX5_CQ_STATE_ARMED = 0x9, 3001 MLX5_CQ_STATE_FIRED = 0xa, 3002 }; 3003 3004 struct mlx5_ifc_cqc_bits { 3005 u8 status[0x4]; 3006 u8 reserved_0[0x4]; 3007 u8 cqe_sz[0x3]; 3008 u8 cc[0x1]; 3009 u8 reserved_1[0x1]; 3010 u8 scqe_break_moderation_en[0x1]; 3011 u8 oi[0x1]; 3012 u8 cq_period_mode[0x2]; 3013 u8 cqe_compression_en[0x1]; 3014 u8 mini_cqe_res_format[0x2]; 3015 u8 st[0x4]; 3016 u8 reserved_2[0x8]; 3017 3018 u8 reserved_3[0x20]; 3019 3020 u8 reserved_4[0x14]; 3021 u8 page_offset[0x6]; 3022 u8 reserved_5[0x6]; 3023 3024 u8 reserved_6[0x3]; 3025 u8 log_cq_size[0x5]; 3026 u8 uar_page[0x18]; 3027 3028 u8 reserved_7[0x4]; 3029 u8 cq_period[0xc]; 3030 u8 cq_max_count[0x10]; 3031 3032 u8 reserved_8[0x18]; 3033 u8 c_eqn[0x8]; 3034 3035 u8 reserved_9[0x3]; 3036 u8 log_page_size[0x5]; 3037 u8 reserved_10[0x18]; 3038 3039 u8 reserved_11[0x20]; 3040 3041 u8 reserved_12[0x8]; 3042 u8 last_notified_index[0x18]; 3043 3044 u8 reserved_13[0x8]; 3045 u8 last_solicit_index[0x18]; 3046 3047 u8 reserved_14[0x8]; 3048 u8 consumer_counter[0x18]; 3049 3050 u8 reserved_15[0x8]; 3051 u8 producer_counter[0x18]; 3052 3053 u8 reserved_16[0x40]; 3054 3055 u8 dbr_addr[0x40]; 3056 }; 3057 3058 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3059 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3060 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3061 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3062 u8 reserved_0[0x800]; 3063 }; 3064 3065 struct mlx5_ifc_query_adapter_param_block_bits { 3066 u8 reserved_0[0xc0]; 3067 3068 u8 reserved_1[0x8]; 3069 u8 ieee_vendor_id[0x18]; 3070 3071 u8 reserved_2[0x10]; 3072 u8 vsd_vendor_id[0x10]; 3073 3074 u8 vsd[208][0x8]; 3075 3076 u8 vsd_contd_psid[16][0x8]; 3077 }; 3078 3079 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3080 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3081 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3082 u8 reserved_0[0x20]; 3083 }; 3084 3085 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3086 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3087 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3088 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3089 u8 reserved_0[0x20]; 3090 }; 3091 3092 struct mlx5_ifc_bufferx_reg_bits { 3093 u8 reserved_0[0x6]; 3094 u8 lossy[0x1]; 3095 u8 epsb[0x1]; 3096 u8 reserved_1[0xc]; 3097 u8 size[0xc]; 3098 3099 u8 xoff_threshold[0x10]; 3100 u8 xon_threshold[0x10]; 3101 }; 3102 3103 struct mlx5_ifc_config_item_bits { 3104 u8 valid[0x2]; 3105 u8 reserved_0[0x2]; 3106 u8 header_type[0x2]; 3107 u8 reserved_1[0x2]; 3108 u8 default_location[0x1]; 3109 u8 reserved_2[0x7]; 3110 u8 version[0x4]; 3111 u8 reserved_3[0x3]; 3112 u8 length[0x9]; 3113 3114 u8 type[0x20]; 3115 3116 u8 reserved_4[0x10]; 3117 u8 crc16[0x10]; 3118 }; 3119 3120 struct mlx5_ifc_nodnic_port_config_reg_bits { 3121 struct mlx5_ifc_nodnic_event_word_bits event; 3122 3123 u8 network_en[0x1]; 3124 u8 dma_en[0x1]; 3125 u8 promisc_en[0x1]; 3126 u8 promisc_multicast_en[0x1]; 3127 u8 reserved_0[0x17]; 3128 u8 receive_filter_en[0x5]; 3129 3130 u8 reserved_1[0x10]; 3131 u8 mac_47_32[0x10]; 3132 3133 u8 mac_31_0[0x20]; 3134 3135 u8 receive_filters_mgid_mac[64][0x8]; 3136 3137 u8 gid[16][0x8]; 3138 3139 u8 reserved_2[0x10]; 3140 u8 lid[0x10]; 3141 3142 u8 reserved_3[0xc]; 3143 u8 sm_sl[0x4]; 3144 u8 sm_lid[0x10]; 3145 3146 u8 completion_address_63_32[0x20]; 3147 3148 u8 completion_address_31_12[0x14]; 3149 u8 reserved_4[0x6]; 3150 u8 log_cq_size[0x6]; 3151 3152 u8 working_buffer_address_63_32[0x20]; 3153 3154 u8 working_buffer_address_31_12[0x14]; 3155 u8 reserved_5[0xc]; 3156 3157 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 3158 3159 u8 pkey_index[0x10]; 3160 u8 pkey[0x10]; 3161 3162 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 3163 3164 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 3165 3166 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 3167 3168 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 3169 3170 u8 reserved_6[0x400]; 3171 }; 3172 3173 union mlx5_ifc_event_auto_bits { 3174 struct mlx5_ifc_comp_event_bits comp_event; 3175 struct mlx5_ifc_dct_events_bits dct_events; 3176 struct mlx5_ifc_qp_events_bits qp_events; 3177 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3178 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3179 struct mlx5_ifc_cq_error_bits cq_error; 3180 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3181 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3182 struct mlx5_ifc_gpio_event_bits gpio_event; 3183 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3184 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3185 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3186 struct mlx5_ifc_pages_req_event_bits pages_req_event; 3187 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 3188 u8 reserved_0[0xe0]; 3189 }; 3190 3191 struct mlx5_ifc_health_buffer_bits { 3192 u8 reserved_0[0x100]; 3193 3194 u8 assert_existptr[0x20]; 3195 3196 u8 assert_callra[0x20]; 3197 3198 u8 reserved_1[0x40]; 3199 3200 u8 fw_version[0x20]; 3201 3202 u8 hw_id[0x20]; 3203 3204 u8 reserved_2[0x20]; 3205 3206 u8 irisc_index[0x8]; 3207 u8 synd[0x8]; 3208 u8 ext_synd[0x10]; 3209 }; 3210 3211 struct mlx5_ifc_register_loopback_control_bits { 3212 u8 no_lb[0x1]; 3213 u8 reserved_0[0x7]; 3214 u8 port[0x8]; 3215 u8 reserved_1[0x10]; 3216 3217 u8 reserved_2[0x60]; 3218 }; 3219 3220 struct mlx5_ifc_lrh_bits { 3221 u8 vl[4]; 3222 u8 lver[4]; 3223 u8 sl[4]; 3224 u8 reserved2[2]; 3225 u8 lnh[2]; 3226 u8 dlid[16]; 3227 u8 reserved5[5]; 3228 u8 pkt_len[11]; 3229 u8 slid[16]; 3230 }; 3231 3232 struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3233 u8 reserved_0[0x40]; 3234 3235 u8 reserved_1[0x10]; 3236 u8 rol_mode[0x8]; 3237 u8 wol_mode[0x8]; 3238 }; 3239 3240 struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3241 u8 reserved_0[0x40]; 3242 3243 u8 rol_mode_valid[0x1]; 3244 u8 wol_mode_valid[0x1]; 3245 u8 reserved_1[0xe]; 3246 u8 rol_mode[0x8]; 3247 u8 wol_mode[0x8]; 3248 3249 u8 reserved_2[0x7a0]; 3250 }; 3251 3252 struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3253 u8 virtual_mac_en[0x1]; 3254 u8 mac_aux_v[0x1]; 3255 u8 reserved_0[0x1e]; 3256 3257 u8 reserved_1[0x40]; 3258 3259 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3260 3261 u8 reserved_2[0x760]; 3262 }; 3263 3264 struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3265 u8 virtual_mac_en[0x1]; 3266 u8 mac_aux_v[0x1]; 3267 u8 reserved_0[0x1e]; 3268 3269 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3270 3271 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3272 3273 u8 reserved_1[0x760]; 3274 }; 3275 3276 struct mlx5_ifc_icmd_query_fw_info_out_bits { 3277 struct mlx5_ifc_fw_version_bits fw_version; 3278 3279 u8 reserved_0[0x10]; 3280 u8 hash_signature[0x10]; 3281 3282 u8 psid[16][0x8]; 3283 3284 u8 reserved_1[0x6e0]; 3285 }; 3286 3287 struct mlx5_ifc_icmd_query_cap_in_bits { 3288 u8 reserved_0[0x10]; 3289 u8 capability_group[0x10]; 3290 }; 3291 3292 struct mlx5_ifc_icmd_query_cap_general_bits { 3293 u8 nv_access[0x1]; 3294 u8 fw_info_psid[0x1]; 3295 u8 reserved_0[0x1e]; 3296 3297 u8 reserved_1[0x16]; 3298 u8 rol_s[0x1]; 3299 u8 rol_g[0x1]; 3300 u8 reserved_2[0x1]; 3301 u8 wol_s[0x1]; 3302 u8 wol_g[0x1]; 3303 u8 wol_a[0x1]; 3304 u8 wol_b[0x1]; 3305 u8 wol_m[0x1]; 3306 u8 wol_u[0x1]; 3307 u8 wol_p[0x1]; 3308 }; 3309 3310 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3311 u8 status[0x8]; 3312 u8 reserved_0[0x18]; 3313 3314 u8 reserved_1[0x7e0]; 3315 }; 3316 3317 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3318 u8 status[0x8]; 3319 u8 reserved_0[0x18]; 3320 3321 u8 reserved_1[0x7e0]; 3322 }; 3323 3324 struct mlx5_ifc_icmd_ocbb_init_in_bits { 3325 u8 address_hi[0x20]; 3326 3327 u8 address_lo[0x20]; 3328 3329 u8 reserved_0[0x7c0]; 3330 }; 3331 3332 struct mlx5_ifc_icmd_init_ocsd_in_bits { 3333 u8 reserved_0[0x20]; 3334 3335 u8 address_hi[0x20]; 3336 3337 u8 address_lo[0x20]; 3338 3339 u8 reserved_1[0x7a0]; 3340 }; 3341 3342 struct mlx5_ifc_icmd_access_reg_out_bits { 3343 u8 reserved_0[0x11]; 3344 u8 status[0x7]; 3345 u8 reserved_1[0x8]; 3346 3347 u8 register_id[0x10]; 3348 u8 reserved_2[0x10]; 3349 3350 u8 reserved_3[0x40]; 3351 3352 u8 reserved_4[0x5]; 3353 u8 len[0xb]; 3354 u8 reserved_5[0x10]; 3355 3356 u8 register_data[0][0x20]; 3357 }; 3358 3359 enum { 3360 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3361 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3362 }; 3363 3364 struct mlx5_ifc_icmd_access_reg_in_bits { 3365 u8 constant_1[0x5]; 3366 u8 constant_2[0xb]; 3367 u8 reserved_0[0x10]; 3368 3369 u8 register_id[0x10]; 3370 u8 reserved_1[0x1]; 3371 u8 method[0x7]; 3372 u8 constant_3[0x8]; 3373 3374 u8 reserved_2[0x40]; 3375 3376 u8 constant_4[0x5]; 3377 u8 len[0xb]; 3378 u8 reserved_3[0x10]; 3379 3380 u8 register_data[0][0x20]; 3381 }; 3382 3383 enum { 3384 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3385 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3386 }; 3387 3388 struct mlx5_ifc_teardown_hca_out_bits { 3389 u8 status[0x8]; 3390 u8 reserved_0[0x18]; 3391 3392 u8 syndrome[0x20]; 3393 3394 u8 reserved_1[0x3f]; 3395 3396 u8 state[0x1]; 3397 }; 3398 3399 enum { 3400 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3401 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3402 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3403 }; 3404 3405 struct mlx5_ifc_teardown_hca_in_bits { 3406 u8 opcode[0x10]; 3407 u8 reserved_0[0x10]; 3408 3409 u8 reserved_1[0x10]; 3410 u8 op_mod[0x10]; 3411 3412 u8 reserved_2[0x10]; 3413 u8 profile[0x10]; 3414 3415 u8 reserved_3[0x20]; 3416 }; 3417 3418 struct mlx5_ifc_set_delay_drop_params_out_bits { 3419 u8 status[0x8]; 3420 u8 reserved_at_8[0x18]; 3421 3422 u8 syndrome[0x20]; 3423 3424 u8 reserved_at_40[0x40]; 3425 }; 3426 3427 struct mlx5_ifc_set_delay_drop_params_in_bits { 3428 u8 opcode[0x10]; 3429 u8 reserved_at_10[0x10]; 3430 3431 u8 reserved_at_20[0x10]; 3432 u8 op_mod[0x10]; 3433 3434 u8 reserved_at_40[0x20]; 3435 3436 u8 reserved_at_60[0x10]; 3437 u8 delay_drop_timeout[0x10]; 3438 }; 3439 3440 struct mlx5_ifc_query_delay_drop_params_out_bits { 3441 u8 status[0x8]; 3442 u8 reserved_at_8[0x18]; 3443 3444 u8 syndrome[0x20]; 3445 3446 u8 reserved_at_40[0x20]; 3447 3448 u8 reserved_at_60[0x10]; 3449 u8 delay_drop_timeout[0x10]; 3450 }; 3451 3452 struct mlx5_ifc_query_delay_drop_params_in_bits { 3453 u8 opcode[0x10]; 3454 u8 reserved_at_10[0x10]; 3455 3456 u8 reserved_at_20[0x10]; 3457 u8 op_mod[0x10]; 3458 3459 u8 reserved_at_40[0x40]; 3460 }; 3461 3462 struct mlx5_ifc_suspend_qp_out_bits { 3463 u8 status[0x8]; 3464 u8 reserved_0[0x18]; 3465 3466 u8 syndrome[0x20]; 3467 3468 u8 reserved_1[0x40]; 3469 }; 3470 3471 struct mlx5_ifc_suspend_qp_in_bits { 3472 u8 opcode[0x10]; 3473 u8 reserved_0[0x10]; 3474 3475 u8 reserved_1[0x10]; 3476 u8 op_mod[0x10]; 3477 3478 u8 reserved_2[0x8]; 3479 u8 qpn[0x18]; 3480 3481 u8 reserved_3[0x20]; 3482 }; 3483 3484 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3485 u8 status[0x8]; 3486 u8 reserved_0[0x18]; 3487 3488 u8 syndrome[0x20]; 3489 3490 u8 reserved_1[0x40]; 3491 }; 3492 3493 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3494 u8 opcode[0x10]; 3495 u8 uid[0x10]; 3496 3497 u8 reserved_1[0x10]; 3498 u8 op_mod[0x10]; 3499 3500 u8 reserved_2[0x8]; 3501 u8 qpn[0x18]; 3502 3503 u8 reserved_3[0x20]; 3504 3505 u8 opt_param_mask[0x20]; 3506 3507 u8 reserved_4[0x20]; 3508 3509 struct mlx5_ifc_qpc_bits qpc; 3510 3511 u8 reserved_5[0x80]; 3512 }; 3513 3514 struct mlx5_ifc_sqd2rts_qp_out_bits { 3515 u8 status[0x8]; 3516 u8 reserved_0[0x18]; 3517 3518 u8 syndrome[0x20]; 3519 3520 u8 reserved_1[0x40]; 3521 }; 3522 3523 struct mlx5_ifc_sqd2rts_qp_in_bits { 3524 u8 opcode[0x10]; 3525 u8 reserved_0[0x10]; 3526 3527 u8 reserved_1[0x10]; 3528 u8 op_mod[0x10]; 3529 3530 u8 reserved_2[0x8]; 3531 u8 qpn[0x18]; 3532 3533 u8 reserved_3[0x20]; 3534 3535 u8 opt_param_mask[0x20]; 3536 3537 u8 reserved_4[0x20]; 3538 3539 struct mlx5_ifc_qpc_bits qpc; 3540 3541 u8 reserved_5[0x80]; 3542 }; 3543 3544 struct mlx5_ifc_set_wol_rol_out_bits { 3545 u8 status[0x8]; 3546 u8 reserved_0[0x18]; 3547 3548 u8 syndrome[0x20]; 3549 3550 u8 reserved_1[0x40]; 3551 }; 3552 3553 struct mlx5_ifc_set_wol_rol_in_bits { 3554 u8 opcode[0x10]; 3555 u8 reserved_0[0x10]; 3556 3557 u8 reserved_1[0x10]; 3558 u8 op_mod[0x10]; 3559 3560 u8 rol_mode_valid[0x1]; 3561 u8 wol_mode_valid[0x1]; 3562 u8 reserved_2[0xe]; 3563 u8 rol_mode[0x8]; 3564 u8 wol_mode[0x8]; 3565 3566 u8 reserved_3[0x20]; 3567 }; 3568 3569 struct mlx5_ifc_set_roce_address_out_bits { 3570 u8 status[0x8]; 3571 u8 reserved_0[0x18]; 3572 3573 u8 syndrome[0x20]; 3574 3575 u8 reserved_1[0x40]; 3576 }; 3577 3578 struct mlx5_ifc_set_roce_address_in_bits { 3579 u8 opcode[0x10]; 3580 u8 reserved_0[0x10]; 3581 3582 u8 reserved_1[0x10]; 3583 u8 op_mod[0x10]; 3584 3585 u8 roce_address_index[0x10]; 3586 u8 reserved_2[0x10]; 3587 3588 u8 reserved_3[0x20]; 3589 3590 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3591 }; 3592 3593 struct mlx5_ifc_set_rdb_out_bits { 3594 u8 status[0x8]; 3595 u8 reserved_0[0x18]; 3596 3597 u8 syndrome[0x20]; 3598 3599 u8 reserved_1[0x40]; 3600 }; 3601 3602 struct mlx5_ifc_set_rdb_in_bits { 3603 u8 opcode[0x10]; 3604 u8 reserved_0[0x10]; 3605 3606 u8 reserved_1[0x10]; 3607 u8 op_mod[0x10]; 3608 3609 u8 reserved_2[0x8]; 3610 u8 qpn[0x18]; 3611 3612 u8 reserved_3[0x18]; 3613 u8 rdb_list_size[0x8]; 3614 3615 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3616 }; 3617 3618 struct mlx5_ifc_set_mad_demux_out_bits { 3619 u8 status[0x8]; 3620 u8 reserved_0[0x18]; 3621 3622 u8 syndrome[0x20]; 3623 3624 u8 reserved_1[0x40]; 3625 }; 3626 3627 enum { 3628 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3629 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3630 }; 3631 3632 struct mlx5_ifc_set_mad_demux_in_bits { 3633 u8 opcode[0x10]; 3634 u8 reserved_0[0x10]; 3635 3636 u8 reserved_1[0x10]; 3637 u8 op_mod[0x10]; 3638 3639 u8 reserved_2[0x20]; 3640 3641 u8 reserved_3[0x6]; 3642 u8 demux_mode[0x2]; 3643 u8 reserved_4[0x18]; 3644 }; 3645 3646 struct mlx5_ifc_set_l2_table_entry_out_bits { 3647 u8 status[0x8]; 3648 u8 reserved_0[0x18]; 3649 3650 u8 syndrome[0x20]; 3651 3652 u8 reserved_1[0x40]; 3653 }; 3654 3655 struct mlx5_ifc_set_l2_table_entry_in_bits { 3656 u8 opcode[0x10]; 3657 u8 reserved_0[0x10]; 3658 3659 u8 reserved_1[0x10]; 3660 u8 op_mod[0x10]; 3661 3662 u8 reserved_2[0x60]; 3663 3664 u8 reserved_3[0x8]; 3665 u8 table_index[0x18]; 3666 3667 u8 reserved_4[0x20]; 3668 3669 u8 reserved_5[0x13]; 3670 u8 vlan_valid[0x1]; 3671 u8 vlan[0xc]; 3672 3673 struct mlx5_ifc_mac_address_layout_bits mac_address; 3674 3675 u8 reserved_6[0xc0]; 3676 }; 3677 3678 struct mlx5_ifc_set_issi_out_bits { 3679 u8 status[0x8]; 3680 u8 reserved_0[0x18]; 3681 3682 u8 syndrome[0x20]; 3683 3684 u8 reserved_1[0x40]; 3685 }; 3686 3687 struct mlx5_ifc_set_issi_in_bits { 3688 u8 opcode[0x10]; 3689 u8 reserved_0[0x10]; 3690 3691 u8 reserved_1[0x10]; 3692 u8 op_mod[0x10]; 3693 3694 u8 reserved_2[0x10]; 3695 u8 current_issi[0x10]; 3696 3697 u8 reserved_3[0x20]; 3698 }; 3699 3700 struct mlx5_ifc_set_hca_cap_out_bits { 3701 u8 status[0x8]; 3702 u8 reserved_0[0x18]; 3703 3704 u8 syndrome[0x20]; 3705 3706 u8 reserved_1[0x40]; 3707 }; 3708 3709 struct mlx5_ifc_set_hca_cap_in_bits { 3710 u8 opcode[0x10]; 3711 u8 reserved_0[0x10]; 3712 3713 u8 reserved_1[0x10]; 3714 u8 op_mod[0x10]; 3715 3716 u8 reserved_2[0x40]; 3717 3718 union mlx5_ifc_hca_cap_union_bits capability; 3719 }; 3720 3721 enum { 3722 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3723 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3724 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3725 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3726 }; 3727 3728 struct mlx5_ifc_set_flow_table_root_out_bits { 3729 u8 status[0x8]; 3730 u8 reserved_0[0x18]; 3731 3732 u8 syndrome[0x20]; 3733 3734 u8 reserved_1[0x40]; 3735 }; 3736 3737 struct mlx5_ifc_set_flow_table_root_in_bits { 3738 u8 opcode[0x10]; 3739 u8 reserved_0[0x10]; 3740 3741 u8 reserved_1[0x10]; 3742 u8 op_mod[0x10]; 3743 3744 u8 other_vport[0x1]; 3745 u8 reserved_2[0xf]; 3746 u8 vport_number[0x10]; 3747 3748 u8 reserved_3[0x20]; 3749 3750 u8 table_type[0x8]; 3751 u8 reserved_4[0x18]; 3752 3753 u8 reserved_5[0x8]; 3754 u8 table_id[0x18]; 3755 3756 u8 reserved_6[0x8]; 3757 u8 underlay_qpn[0x18]; 3758 3759 u8 reserved_7[0x120]; 3760 }; 3761 3762 struct mlx5_ifc_set_fte_out_bits { 3763 u8 status[0x8]; 3764 u8 reserved_0[0x18]; 3765 3766 u8 syndrome[0x20]; 3767 3768 u8 reserved_1[0x40]; 3769 }; 3770 3771 struct mlx5_ifc_set_fte_in_bits { 3772 u8 opcode[0x10]; 3773 u8 reserved_0[0x10]; 3774 3775 u8 reserved_1[0x10]; 3776 u8 op_mod[0x10]; 3777 3778 u8 other_vport[0x1]; 3779 u8 reserved_2[0xf]; 3780 u8 vport_number[0x10]; 3781 3782 u8 reserved_3[0x20]; 3783 3784 u8 table_type[0x8]; 3785 u8 reserved_4[0x18]; 3786 3787 u8 reserved_5[0x8]; 3788 u8 table_id[0x18]; 3789 3790 u8 reserved_6[0x18]; 3791 u8 modify_enable_mask[0x8]; 3792 3793 u8 reserved_7[0x20]; 3794 3795 u8 flow_index[0x20]; 3796 3797 u8 reserved_8[0xe0]; 3798 3799 struct mlx5_ifc_flow_context_bits flow_context; 3800 }; 3801 3802 struct mlx5_ifc_set_driver_version_out_bits { 3803 u8 status[0x8]; 3804 u8 reserved_0[0x18]; 3805 3806 u8 syndrome[0x20]; 3807 3808 u8 reserved_1[0x40]; 3809 }; 3810 3811 struct mlx5_ifc_set_driver_version_in_bits { 3812 u8 opcode[0x10]; 3813 u8 reserved_0[0x10]; 3814 3815 u8 reserved_1[0x10]; 3816 u8 op_mod[0x10]; 3817 3818 u8 reserved_2[0x40]; 3819 3820 u8 driver_version[64][0x8]; 3821 }; 3822 3823 struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3824 u8 status[0x8]; 3825 u8 reserved_0[0x18]; 3826 3827 u8 syndrome[0x20]; 3828 3829 u8 reserved_1[0x40]; 3830 }; 3831 3832 struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3833 u8 opcode[0x10]; 3834 u8 reserved_0[0x10]; 3835 3836 u8 reserved_1[0x10]; 3837 u8 op_mod[0x10]; 3838 3839 u8 enable[0x1]; 3840 u8 reserved_2[0x1f]; 3841 3842 u8 reserved_3[0x160]; 3843 3844 struct mlx5_ifc_cmd_pas_bits pas; 3845 }; 3846 3847 struct mlx5_ifc_set_burst_size_out_bits { 3848 u8 status[0x8]; 3849 u8 reserved_0[0x18]; 3850 3851 u8 syndrome[0x20]; 3852 3853 u8 reserved_1[0x40]; 3854 }; 3855 3856 struct mlx5_ifc_set_burst_size_in_bits { 3857 u8 opcode[0x10]; 3858 u8 reserved_0[0x10]; 3859 3860 u8 reserved_1[0x10]; 3861 u8 op_mod[0x10]; 3862 3863 u8 reserved_2[0x20]; 3864 3865 u8 reserved_3[0x9]; 3866 u8 device_burst_size[0x17]; 3867 }; 3868 3869 struct mlx5_ifc_rts2rts_qp_out_bits { 3870 u8 status[0x8]; 3871 u8 reserved_0[0x18]; 3872 3873 u8 syndrome[0x20]; 3874 3875 u8 reserved_1[0x40]; 3876 }; 3877 3878 struct mlx5_ifc_rts2rts_qp_in_bits { 3879 u8 opcode[0x10]; 3880 u8 uid[0x10]; 3881 3882 u8 reserved_1[0x10]; 3883 u8 op_mod[0x10]; 3884 3885 u8 reserved_2[0x8]; 3886 u8 qpn[0x18]; 3887 3888 u8 reserved_3[0x20]; 3889 3890 u8 opt_param_mask[0x20]; 3891 3892 u8 reserved_4[0x20]; 3893 3894 struct mlx5_ifc_qpc_bits qpc; 3895 3896 u8 reserved_5[0x80]; 3897 }; 3898 3899 struct mlx5_ifc_rtr2rts_qp_out_bits { 3900 u8 status[0x8]; 3901 u8 reserved_0[0x18]; 3902 3903 u8 syndrome[0x20]; 3904 3905 u8 reserved_1[0x40]; 3906 }; 3907 3908 struct mlx5_ifc_rtr2rts_qp_in_bits { 3909 u8 opcode[0x10]; 3910 u8 uid[0x10]; 3911 3912 u8 reserved_1[0x10]; 3913 u8 op_mod[0x10]; 3914 3915 u8 reserved_2[0x8]; 3916 u8 qpn[0x18]; 3917 3918 u8 reserved_3[0x20]; 3919 3920 u8 opt_param_mask[0x20]; 3921 3922 u8 reserved_4[0x20]; 3923 3924 struct mlx5_ifc_qpc_bits qpc; 3925 3926 u8 reserved_5[0x80]; 3927 }; 3928 3929 struct mlx5_ifc_rst2init_qp_out_bits { 3930 u8 status[0x8]; 3931 u8 reserved_0[0x18]; 3932 3933 u8 syndrome[0x20]; 3934 3935 u8 reserved_1[0x40]; 3936 }; 3937 3938 struct mlx5_ifc_rst2init_qp_in_bits { 3939 u8 opcode[0x10]; 3940 u8 uid[0x10]; 3941 3942 u8 reserved_1[0x10]; 3943 u8 op_mod[0x10]; 3944 3945 u8 reserved_2[0x8]; 3946 u8 qpn[0x18]; 3947 3948 u8 reserved_3[0x20]; 3949 3950 u8 opt_param_mask[0x20]; 3951 3952 u8 reserved_4[0x20]; 3953 3954 struct mlx5_ifc_qpc_bits qpc; 3955 3956 u8 reserved_5[0x80]; 3957 }; 3958 3959 struct mlx5_ifc_resume_qp_out_bits { 3960 u8 status[0x8]; 3961 u8 reserved_0[0x18]; 3962 3963 u8 syndrome[0x20]; 3964 3965 u8 reserved_1[0x40]; 3966 }; 3967 3968 struct mlx5_ifc_resume_qp_in_bits { 3969 u8 opcode[0x10]; 3970 u8 reserved_0[0x10]; 3971 3972 u8 reserved_1[0x10]; 3973 u8 op_mod[0x10]; 3974 3975 u8 reserved_2[0x8]; 3976 u8 qpn[0x18]; 3977 3978 u8 reserved_3[0x20]; 3979 }; 3980 3981 struct mlx5_ifc_query_xrc_srq_out_bits { 3982 u8 status[0x8]; 3983 u8 reserved_0[0x18]; 3984 3985 u8 syndrome[0x20]; 3986 3987 u8 reserved_1[0x40]; 3988 3989 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3990 3991 u8 reserved_2[0x600]; 3992 3993 u8 pas[0][0x40]; 3994 }; 3995 3996 struct mlx5_ifc_query_xrc_srq_in_bits { 3997 u8 opcode[0x10]; 3998 u8 reserved_0[0x10]; 3999 4000 u8 reserved_1[0x10]; 4001 u8 op_mod[0x10]; 4002 4003 u8 reserved_2[0x8]; 4004 u8 xrc_srqn[0x18]; 4005 4006 u8 reserved_3[0x20]; 4007 }; 4008 4009 struct mlx5_ifc_query_wol_rol_out_bits { 4010 u8 status[0x8]; 4011 u8 reserved_0[0x18]; 4012 4013 u8 syndrome[0x20]; 4014 4015 u8 reserved_1[0x10]; 4016 u8 rol_mode[0x8]; 4017 u8 wol_mode[0x8]; 4018 4019 u8 reserved_2[0x20]; 4020 }; 4021 4022 struct mlx5_ifc_query_wol_rol_in_bits { 4023 u8 opcode[0x10]; 4024 u8 reserved_0[0x10]; 4025 4026 u8 reserved_1[0x10]; 4027 u8 op_mod[0x10]; 4028 4029 u8 reserved_2[0x40]; 4030 }; 4031 4032 enum { 4033 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4034 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4035 }; 4036 4037 struct mlx5_ifc_query_vport_state_out_bits { 4038 u8 status[0x8]; 4039 u8 reserved_0[0x18]; 4040 4041 u8 syndrome[0x20]; 4042 4043 u8 reserved_1[0x20]; 4044 4045 u8 reserved_2[0x18]; 4046 u8 admin_state[0x4]; 4047 u8 state[0x4]; 4048 }; 4049 4050 enum { 4051 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 4052 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 4053 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 4054 }; 4055 4056 struct mlx5_ifc_query_vport_state_in_bits { 4057 u8 opcode[0x10]; 4058 u8 reserved_0[0x10]; 4059 4060 u8 reserved_1[0x10]; 4061 u8 op_mod[0x10]; 4062 4063 u8 other_vport[0x1]; 4064 u8 reserved_2[0xf]; 4065 u8 vport_number[0x10]; 4066 4067 u8 reserved_3[0x20]; 4068 }; 4069 4070 struct mlx5_ifc_query_vnic_env_out_bits { 4071 u8 status[0x8]; 4072 u8 reserved_at_8[0x18]; 4073 4074 u8 syndrome[0x20]; 4075 4076 u8 reserved_at_40[0x40]; 4077 4078 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4079 }; 4080 4081 enum { 4082 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4083 }; 4084 4085 struct mlx5_ifc_query_vnic_env_in_bits { 4086 u8 opcode[0x10]; 4087 u8 reserved_at_10[0x10]; 4088 4089 u8 reserved_at_20[0x10]; 4090 u8 op_mod[0x10]; 4091 4092 u8 other_vport[0x1]; 4093 u8 reserved_at_41[0xf]; 4094 u8 vport_number[0x10]; 4095 4096 u8 reserved_at_60[0x20]; 4097 }; 4098 4099 struct mlx5_ifc_query_vport_counter_out_bits { 4100 u8 status[0x8]; 4101 u8 reserved_0[0x18]; 4102 4103 u8 syndrome[0x20]; 4104 4105 u8 reserved_1[0x40]; 4106 4107 struct mlx5_ifc_traffic_counter_bits received_errors; 4108 4109 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4110 4111 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4112 4113 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4114 4115 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4116 4117 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4118 4119 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4120 4121 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4122 4123 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4124 4125 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4126 4127 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4128 4129 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4130 4131 u8 reserved_2[0xa00]; 4132 }; 4133 4134 enum { 4135 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4136 }; 4137 4138 struct mlx5_ifc_query_vport_counter_in_bits { 4139 u8 opcode[0x10]; 4140 u8 reserved_0[0x10]; 4141 4142 u8 reserved_1[0x10]; 4143 u8 op_mod[0x10]; 4144 4145 u8 other_vport[0x1]; 4146 u8 reserved_2[0xb]; 4147 u8 port_num[0x4]; 4148 u8 vport_number[0x10]; 4149 4150 u8 reserved_3[0x60]; 4151 4152 u8 clear[0x1]; 4153 u8 reserved_4[0x1f]; 4154 4155 u8 reserved_5[0x20]; 4156 }; 4157 4158 struct mlx5_ifc_query_tis_out_bits { 4159 u8 status[0x8]; 4160 u8 reserved_0[0x18]; 4161 4162 u8 syndrome[0x20]; 4163 4164 u8 reserved_1[0x40]; 4165 4166 struct mlx5_ifc_tisc_bits tis_context; 4167 }; 4168 4169 struct mlx5_ifc_query_tis_in_bits { 4170 u8 opcode[0x10]; 4171 u8 reserved_0[0x10]; 4172 4173 u8 reserved_1[0x10]; 4174 u8 op_mod[0x10]; 4175 4176 u8 reserved_2[0x8]; 4177 u8 tisn[0x18]; 4178 4179 u8 reserved_3[0x20]; 4180 }; 4181 4182 struct mlx5_ifc_query_tir_out_bits { 4183 u8 status[0x8]; 4184 u8 reserved_0[0x18]; 4185 4186 u8 syndrome[0x20]; 4187 4188 u8 reserved_1[0xc0]; 4189 4190 struct mlx5_ifc_tirc_bits tir_context; 4191 }; 4192 4193 struct mlx5_ifc_query_tir_in_bits { 4194 u8 opcode[0x10]; 4195 u8 reserved_0[0x10]; 4196 4197 u8 reserved_1[0x10]; 4198 u8 op_mod[0x10]; 4199 4200 u8 reserved_2[0x8]; 4201 u8 tirn[0x18]; 4202 4203 u8 reserved_3[0x20]; 4204 }; 4205 4206 struct mlx5_ifc_query_srq_out_bits { 4207 u8 status[0x8]; 4208 u8 reserved_0[0x18]; 4209 4210 u8 syndrome[0x20]; 4211 4212 u8 reserved_1[0x40]; 4213 4214 struct mlx5_ifc_srqc_bits srq_context_entry; 4215 4216 u8 reserved_2[0x600]; 4217 4218 u8 pas[0][0x40]; 4219 }; 4220 4221 struct mlx5_ifc_query_srq_in_bits { 4222 u8 opcode[0x10]; 4223 u8 reserved_0[0x10]; 4224 4225 u8 reserved_1[0x10]; 4226 u8 op_mod[0x10]; 4227 4228 u8 reserved_2[0x8]; 4229 u8 srqn[0x18]; 4230 4231 u8 reserved_3[0x20]; 4232 }; 4233 4234 struct mlx5_ifc_query_sq_out_bits { 4235 u8 status[0x8]; 4236 u8 reserved_0[0x18]; 4237 4238 u8 syndrome[0x20]; 4239 4240 u8 reserved_1[0xc0]; 4241 4242 struct mlx5_ifc_sqc_bits sq_context; 4243 }; 4244 4245 struct mlx5_ifc_query_sq_in_bits { 4246 u8 opcode[0x10]; 4247 u8 reserved_0[0x10]; 4248 4249 u8 reserved_1[0x10]; 4250 u8 op_mod[0x10]; 4251 4252 u8 reserved_2[0x8]; 4253 u8 sqn[0x18]; 4254 4255 u8 reserved_3[0x20]; 4256 }; 4257 4258 struct mlx5_ifc_query_special_contexts_out_bits { 4259 u8 status[0x8]; 4260 u8 reserved_0[0x18]; 4261 4262 u8 syndrome[0x20]; 4263 4264 u8 dump_fill_mkey[0x20]; 4265 4266 u8 resd_lkey[0x20]; 4267 }; 4268 4269 struct mlx5_ifc_query_special_contexts_in_bits { 4270 u8 opcode[0x10]; 4271 u8 reserved_0[0x10]; 4272 4273 u8 reserved_1[0x10]; 4274 u8 op_mod[0x10]; 4275 4276 u8 reserved_2[0x40]; 4277 }; 4278 4279 struct mlx5_ifc_query_scheduling_element_out_bits { 4280 u8 status[0x8]; 4281 u8 reserved_at_8[0x18]; 4282 4283 u8 syndrome[0x20]; 4284 4285 u8 reserved_at_40[0xc0]; 4286 4287 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4288 4289 u8 reserved_at_300[0x100]; 4290 }; 4291 4292 enum { 4293 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4294 }; 4295 4296 struct mlx5_ifc_query_scheduling_element_in_bits { 4297 u8 opcode[0x10]; 4298 u8 reserved_at_10[0x10]; 4299 4300 u8 reserved_at_20[0x10]; 4301 u8 op_mod[0x10]; 4302 4303 u8 scheduling_hierarchy[0x8]; 4304 u8 reserved_at_48[0x18]; 4305 4306 u8 scheduling_element_id[0x20]; 4307 4308 u8 reserved_at_80[0x180]; 4309 }; 4310 4311 struct mlx5_ifc_query_rqt_out_bits { 4312 u8 status[0x8]; 4313 u8 reserved_0[0x18]; 4314 4315 u8 syndrome[0x20]; 4316 4317 u8 reserved_1[0xc0]; 4318 4319 struct mlx5_ifc_rqtc_bits rqt_context; 4320 }; 4321 4322 struct mlx5_ifc_query_rqt_in_bits { 4323 u8 opcode[0x10]; 4324 u8 reserved_0[0x10]; 4325 4326 u8 reserved_1[0x10]; 4327 u8 op_mod[0x10]; 4328 4329 u8 reserved_2[0x8]; 4330 u8 rqtn[0x18]; 4331 4332 u8 reserved_3[0x20]; 4333 }; 4334 4335 struct mlx5_ifc_query_rq_out_bits { 4336 u8 status[0x8]; 4337 u8 reserved_0[0x18]; 4338 4339 u8 syndrome[0x20]; 4340 4341 u8 reserved_1[0xc0]; 4342 4343 struct mlx5_ifc_rqc_bits rq_context; 4344 }; 4345 4346 struct mlx5_ifc_query_rq_in_bits { 4347 u8 opcode[0x10]; 4348 u8 reserved_0[0x10]; 4349 4350 u8 reserved_1[0x10]; 4351 u8 op_mod[0x10]; 4352 4353 u8 reserved_2[0x8]; 4354 u8 rqn[0x18]; 4355 4356 u8 reserved_3[0x20]; 4357 }; 4358 4359 struct mlx5_ifc_query_roce_address_out_bits { 4360 u8 status[0x8]; 4361 u8 reserved_0[0x18]; 4362 4363 u8 syndrome[0x20]; 4364 4365 u8 reserved_1[0x40]; 4366 4367 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4368 }; 4369 4370 struct mlx5_ifc_query_roce_address_in_bits { 4371 u8 opcode[0x10]; 4372 u8 reserved_0[0x10]; 4373 4374 u8 reserved_1[0x10]; 4375 u8 op_mod[0x10]; 4376 4377 u8 roce_address_index[0x10]; 4378 u8 reserved_2[0x10]; 4379 4380 u8 reserved_3[0x20]; 4381 }; 4382 4383 struct mlx5_ifc_query_rmp_out_bits { 4384 u8 status[0x8]; 4385 u8 reserved_0[0x18]; 4386 4387 u8 syndrome[0x20]; 4388 4389 u8 reserved_1[0xc0]; 4390 4391 struct mlx5_ifc_rmpc_bits rmp_context; 4392 }; 4393 4394 struct mlx5_ifc_query_rmp_in_bits { 4395 u8 opcode[0x10]; 4396 u8 reserved_0[0x10]; 4397 4398 u8 reserved_1[0x10]; 4399 u8 op_mod[0x10]; 4400 4401 u8 reserved_2[0x8]; 4402 u8 rmpn[0x18]; 4403 4404 u8 reserved_3[0x20]; 4405 }; 4406 4407 struct mlx5_ifc_query_rdb_out_bits { 4408 u8 status[0x8]; 4409 u8 reserved_0[0x18]; 4410 4411 u8 syndrome[0x20]; 4412 4413 u8 reserved_1[0x20]; 4414 4415 u8 reserved_2[0x18]; 4416 u8 rdb_list_size[0x8]; 4417 4418 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4419 }; 4420 4421 struct mlx5_ifc_query_rdb_in_bits { 4422 u8 opcode[0x10]; 4423 u8 reserved_0[0x10]; 4424 4425 u8 reserved_1[0x10]; 4426 u8 op_mod[0x10]; 4427 4428 u8 reserved_2[0x8]; 4429 u8 qpn[0x18]; 4430 4431 u8 reserved_3[0x20]; 4432 }; 4433 4434 struct mlx5_ifc_query_qp_out_bits { 4435 u8 status[0x8]; 4436 u8 reserved_0[0x18]; 4437 4438 u8 syndrome[0x20]; 4439 4440 u8 reserved_1[0x40]; 4441 4442 u8 opt_param_mask[0x20]; 4443 4444 u8 reserved_2[0x20]; 4445 4446 struct mlx5_ifc_qpc_bits qpc; 4447 4448 u8 reserved_3[0x80]; 4449 4450 u8 pas[0][0x40]; 4451 }; 4452 4453 struct mlx5_ifc_query_qp_in_bits { 4454 u8 opcode[0x10]; 4455 u8 reserved_0[0x10]; 4456 4457 u8 reserved_1[0x10]; 4458 u8 op_mod[0x10]; 4459 4460 u8 reserved_2[0x8]; 4461 u8 qpn[0x18]; 4462 4463 u8 reserved_3[0x20]; 4464 }; 4465 4466 struct mlx5_ifc_query_q_counter_out_bits { 4467 u8 status[0x8]; 4468 u8 reserved_0[0x18]; 4469 4470 u8 syndrome[0x20]; 4471 4472 u8 reserved_1[0x40]; 4473 4474 u8 rx_write_requests[0x20]; 4475 4476 u8 reserved_2[0x20]; 4477 4478 u8 rx_read_requests[0x20]; 4479 4480 u8 reserved_3[0x20]; 4481 4482 u8 rx_atomic_requests[0x20]; 4483 4484 u8 reserved_4[0x20]; 4485 4486 u8 rx_dct_connect[0x20]; 4487 4488 u8 reserved_5[0x20]; 4489 4490 u8 out_of_buffer[0x20]; 4491 4492 u8 reserved_7[0x20]; 4493 4494 u8 out_of_sequence[0x20]; 4495 4496 u8 reserved_8[0x20]; 4497 4498 u8 duplicate_request[0x20]; 4499 4500 u8 reserved_9[0x20]; 4501 4502 u8 rnr_nak_retry_err[0x20]; 4503 4504 u8 reserved_10[0x20]; 4505 4506 u8 packet_seq_err[0x20]; 4507 4508 u8 reserved_11[0x20]; 4509 4510 u8 implied_nak_seq_err[0x20]; 4511 4512 u8 reserved_12[0x20]; 4513 4514 u8 local_ack_timeout_err[0x20]; 4515 4516 u8 reserved_13[0x20]; 4517 4518 u8 resp_rnr_nak[0x20]; 4519 4520 u8 reserved_14[0x20]; 4521 4522 u8 req_rnr_retries_exceeded[0x20]; 4523 4524 u8 reserved_15[0x460]; 4525 }; 4526 4527 struct mlx5_ifc_query_q_counter_in_bits { 4528 u8 opcode[0x10]; 4529 u8 reserved_0[0x10]; 4530 4531 u8 reserved_1[0x10]; 4532 u8 op_mod[0x10]; 4533 4534 u8 reserved_2[0x80]; 4535 4536 u8 clear[0x1]; 4537 u8 reserved_3[0x1f]; 4538 4539 u8 reserved_4[0x18]; 4540 u8 counter_set_id[0x8]; 4541 }; 4542 4543 struct mlx5_ifc_query_pages_out_bits { 4544 u8 status[0x8]; 4545 u8 reserved_0[0x18]; 4546 4547 u8 syndrome[0x20]; 4548 4549 u8 reserved_1[0x10]; 4550 u8 function_id[0x10]; 4551 4552 u8 num_pages[0x20]; 4553 }; 4554 4555 enum { 4556 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4557 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4558 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4559 }; 4560 4561 struct mlx5_ifc_query_pages_in_bits { 4562 u8 opcode[0x10]; 4563 u8 reserved_0[0x10]; 4564 4565 u8 reserved_1[0x10]; 4566 u8 op_mod[0x10]; 4567 4568 u8 reserved_2[0x10]; 4569 u8 function_id[0x10]; 4570 4571 u8 reserved_3[0x20]; 4572 }; 4573 4574 struct mlx5_ifc_query_nic_vport_context_out_bits { 4575 u8 status[0x8]; 4576 u8 reserved_0[0x18]; 4577 4578 u8 syndrome[0x20]; 4579 4580 u8 reserved_1[0x40]; 4581 4582 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4583 }; 4584 4585 struct mlx5_ifc_query_nic_vport_context_in_bits { 4586 u8 opcode[0x10]; 4587 u8 reserved_0[0x10]; 4588 4589 u8 reserved_1[0x10]; 4590 u8 op_mod[0x10]; 4591 4592 u8 other_vport[0x1]; 4593 u8 reserved_2[0xf]; 4594 u8 vport_number[0x10]; 4595 4596 u8 reserved_3[0x5]; 4597 u8 allowed_list_type[0x3]; 4598 u8 reserved_4[0x18]; 4599 }; 4600 4601 struct mlx5_ifc_query_mkey_out_bits { 4602 u8 status[0x8]; 4603 u8 reserved_0[0x18]; 4604 4605 u8 syndrome[0x20]; 4606 4607 u8 reserved_1[0x40]; 4608 4609 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4610 4611 u8 reserved_2[0x600]; 4612 4613 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4614 4615 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4616 }; 4617 4618 struct mlx5_ifc_query_mkey_in_bits { 4619 u8 opcode[0x10]; 4620 u8 reserved_0[0x10]; 4621 4622 u8 reserved_1[0x10]; 4623 u8 op_mod[0x10]; 4624 4625 u8 reserved_2[0x8]; 4626 u8 mkey_index[0x18]; 4627 4628 u8 pg_access[0x1]; 4629 u8 reserved_3[0x1f]; 4630 }; 4631 4632 struct mlx5_ifc_query_mad_demux_out_bits { 4633 u8 status[0x8]; 4634 u8 reserved_0[0x18]; 4635 4636 u8 syndrome[0x20]; 4637 4638 u8 reserved_1[0x40]; 4639 4640 u8 mad_dumux_parameters_block[0x20]; 4641 }; 4642 4643 struct mlx5_ifc_query_mad_demux_in_bits { 4644 u8 opcode[0x10]; 4645 u8 reserved_0[0x10]; 4646 4647 u8 reserved_1[0x10]; 4648 u8 op_mod[0x10]; 4649 4650 u8 reserved_2[0x40]; 4651 }; 4652 4653 struct mlx5_ifc_query_l2_table_entry_out_bits { 4654 u8 status[0x8]; 4655 u8 reserved_0[0x18]; 4656 4657 u8 syndrome[0x20]; 4658 4659 u8 reserved_1[0xa0]; 4660 4661 u8 reserved_2[0x13]; 4662 u8 vlan_valid[0x1]; 4663 u8 vlan[0xc]; 4664 4665 struct mlx5_ifc_mac_address_layout_bits mac_address; 4666 4667 u8 reserved_3[0xc0]; 4668 }; 4669 4670 struct mlx5_ifc_query_l2_table_entry_in_bits { 4671 u8 opcode[0x10]; 4672 u8 reserved_0[0x10]; 4673 4674 u8 reserved_1[0x10]; 4675 u8 op_mod[0x10]; 4676 4677 u8 reserved_2[0x60]; 4678 4679 u8 reserved_3[0x8]; 4680 u8 table_index[0x18]; 4681 4682 u8 reserved_4[0x140]; 4683 }; 4684 4685 struct mlx5_ifc_query_issi_out_bits { 4686 u8 status[0x8]; 4687 u8 reserved_0[0x18]; 4688 4689 u8 syndrome[0x20]; 4690 4691 u8 reserved_1[0x10]; 4692 u8 current_issi[0x10]; 4693 4694 u8 reserved_2[0xa0]; 4695 4696 u8 supported_issi_reserved[76][0x8]; 4697 u8 supported_issi_dw0[0x20]; 4698 }; 4699 4700 struct mlx5_ifc_query_issi_in_bits { 4701 u8 opcode[0x10]; 4702 u8 reserved_0[0x10]; 4703 4704 u8 reserved_1[0x10]; 4705 u8 op_mod[0x10]; 4706 4707 u8 reserved_2[0x40]; 4708 }; 4709 4710 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4711 u8 status[0x8]; 4712 u8 reserved_0[0x18]; 4713 4714 u8 syndrome[0x20]; 4715 4716 u8 reserved_1[0x40]; 4717 4718 struct mlx5_ifc_pkey_bits pkey[0]; 4719 }; 4720 4721 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4722 u8 opcode[0x10]; 4723 u8 reserved_0[0x10]; 4724 4725 u8 reserved_1[0x10]; 4726 u8 op_mod[0x10]; 4727 4728 u8 other_vport[0x1]; 4729 u8 reserved_2[0xb]; 4730 u8 port_num[0x4]; 4731 u8 vport_number[0x10]; 4732 4733 u8 reserved_3[0x10]; 4734 u8 pkey_index[0x10]; 4735 }; 4736 4737 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4738 u8 status[0x8]; 4739 u8 reserved_0[0x18]; 4740 4741 u8 syndrome[0x20]; 4742 4743 u8 reserved_1[0x20]; 4744 4745 u8 gids_num[0x10]; 4746 u8 reserved_2[0x10]; 4747 4748 struct mlx5_ifc_array128_auto_bits gid[0]; 4749 }; 4750 4751 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4752 u8 opcode[0x10]; 4753 u8 reserved_0[0x10]; 4754 4755 u8 reserved_1[0x10]; 4756 u8 op_mod[0x10]; 4757 4758 u8 other_vport[0x1]; 4759 u8 reserved_2[0xb]; 4760 u8 port_num[0x4]; 4761 u8 vport_number[0x10]; 4762 4763 u8 reserved_3[0x10]; 4764 u8 gid_index[0x10]; 4765 }; 4766 4767 struct mlx5_ifc_query_hca_vport_context_out_bits { 4768 u8 status[0x8]; 4769 u8 reserved_0[0x18]; 4770 4771 u8 syndrome[0x20]; 4772 4773 u8 reserved_1[0x40]; 4774 4775 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4776 }; 4777 4778 struct mlx5_ifc_query_hca_vport_context_in_bits { 4779 u8 opcode[0x10]; 4780 u8 reserved_0[0x10]; 4781 4782 u8 reserved_1[0x10]; 4783 u8 op_mod[0x10]; 4784 4785 u8 other_vport[0x1]; 4786 u8 reserved_2[0xb]; 4787 u8 port_num[0x4]; 4788 u8 vport_number[0x10]; 4789 4790 u8 reserved_3[0x20]; 4791 }; 4792 4793 struct mlx5_ifc_query_hca_cap_out_bits { 4794 u8 status[0x8]; 4795 u8 reserved_0[0x18]; 4796 4797 u8 syndrome[0x20]; 4798 4799 u8 reserved_1[0x40]; 4800 4801 union mlx5_ifc_hca_cap_union_bits capability; 4802 }; 4803 4804 struct mlx5_ifc_query_hca_cap_in_bits { 4805 u8 opcode[0x10]; 4806 u8 reserved_0[0x10]; 4807 4808 u8 reserved_1[0x10]; 4809 u8 op_mod[0x10]; 4810 4811 u8 reserved_2[0x40]; 4812 }; 4813 4814 struct mlx5_ifc_query_flow_table_out_bits { 4815 u8 status[0x8]; 4816 u8 reserved_at_8[0x18]; 4817 4818 u8 syndrome[0x20]; 4819 4820 u8 reserved_at_40[0x80]; 4821 4822 struct mlx5_ifc_flow_table_context_bits flow_table_context; 4823 }; 4824 4825 struct mlx5_ifc_query_flow_table_in_bits { 4826 u8 opcode[0x10]; 4827 u8 reserved_0[0x10]; 4828 4829 u8 reserved_1[0x10]; 4830 u8 op_mod[0x10]; 4831 4832 u8 other_vport[0x1]; 4833 u8 reserved_2[0xf]; 4834 u8 vport_number[0x10]; 4835 4836 u8 reserved_3[0x20]; 4837 4838 u8 table_type[0x8]; 4839 u8 reserved_4[0x18]; 4840 4841 u8 reserved_5[0x8]; 4842 u8 table_id[0x18]; 4843 4844 u8 reserved_6[0x140]; 4845 }; 4846 4847 struct mlx5_ifc_query_fte_out_bits { 4848 u8 status[0x8]; 4849 u8 reserved_0[0x18]; 4850 4851 u8 syndrome[0x20]; 4852 4853 u8 reserved_1[0x1c0]; 4854 4855 struct mlx5_ifc_flow_context_bits flow_context; 4856 }; 4857 4858 struct mlx5_ifc_query_fte_in_bits { 4859 u8 opcode[0x10]; 4860 u8 reserved_0[0x10]; 4861 4862 u8 reserved_1[0x10]; 4863 u8 op_mod[0x10]; 4864 4865 u8 other_vport[0x1]; 4866 u8 reserved_2[0xf]; 4867 u8 vport_number[0x10]; 4868 4869 u8 reserved_3[0x20]; 4870 4871 u8 table_type[0x8]; 4872 u8 reserved_4[0x18]; 4873 4874 u8 reserved_5[0x8]; 4875 u8 table_id[0x18]; 4876 4877 u8 reserved_6[0x40]; 4878 4879 u8 flow_index[0x20]; 4880 4881 u8 reserved_7[0xe0]; 4882 }; 4883 4884 enum { 4885 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4886 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4887 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4888 }; 4889 4890 struct mlx5_ifc_query_flow_group_out_bits { 4891 u8 status[0x8]; 4892 u8 reserved_0[0x18]; 4893 4894 u8 syndrome[0x20]; 4895 4896 u8 reserved_1[0xa0]; 4897 4898 u8 start_flow_index[0x20]; 4899 4900 u8 reserved_2[0x20]; 4901 4902 u8 end_flow_index[0x20]; 4903 4904 u8 reserved_3[0xa0]; 4905 4906 u8 reserved_4[0x18]; 4907 u8 match_criteria_enable[0x8]; 4908 4909 struct mlx5_ifc_fte_match_param_bits match_criteria; 4910 4911 u8 reserved_5[0xe00]; 4912 }; 4913 4914 struct mlx5_ifc_query_flow_group_in_bits { 4915 u8 opcode[0x10]; 4916 u8 reserved_0[0x10]; 4917 4918 u8 reserved_1[0x10]; 4919 u8 op_mod[0x10]; 4920 4921 u8 other_vport[0x1]; 4922 u8 reserved_2[0xf]; 4923 u8 vport_number[0x10]; 4924 4925 u8 reserved_3[0x20]; 4926 4927 u8 table_type[0x8]; 4928 u8 reserved_4[0x18]; 4929 4930 u8 reserved_5[0x8]; 4931 u8 table_id[0x18]; 4932 4933 u8 group_id[0x20]; 4934 4935 u8 reserved_6[0x120]; 4936 }; 4937 4938 struct mlx5_ifc_query_flow_counter_out_bits { 4939 u8 status[0x8]; 4940 u8 reserved_at_8[0x18]; 4941 4942 u8 syndrome[0x20]; 4943 4944 u8 reserved_at_40[0x40]; 4945 4946 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4947 }; 4948 4949 struct mlx5_ifc_query_flow_counter_in_bits { 4950 u8 opcode[0x10]; 4951 u8 reserved_at_10[0x10]; 4952 4953 u8 reserved_at_20[0x10]; 4954 u8 op_mod[0x10]; 4955 4956 u8 reserved_at_40[0x80]; 4957 4958 u8 clear[0x1]; 4959 u8 reserved_at_c1[0xf]; 4960 u8 num_of_counters[0x10]; 4961 4962 u8 reserved_at_e0[0x10]; 4963 u8 flow_counter_id[0x10]; 4964 }; 4965 4966 struct mlx5_ifc_query_esw_vport_context_out_bits { 4967 u8 status[0x8]; 4968 u8 reserved_0[0x18]; 4969 4970 u8 syndrome[0x20]; 4971 4972 u8 reserved_1[0x40]; 4973 4974 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4975 }; 4976 4977 struct mlx5_ifc_query_esw_vport_context_in_bits { 4978 u8 opcode[0x10]; 4979 u8 reserved_0[0x10]; 4980 4981 u8 reserved_1[0x10]; 4982 u8 op_mod[0x10]; 4983 4984 u8 other_vport[0x1]; 4985 u8 reserved_2[0xf]; 4986 u8 vport_number[0x10]; 4987 4988 u8 reserved_3[0x20]; 4989 }; 4990 4991 struct mlx5_ifc_query_eq_out_bits { 4992 u8 status[0x8]; 4993 u8 reserved_0[0x18]; 4994 4995 u8 syndrome[0x20]; 4996 4997 u8 reserved_1[0x40]; 4998 4999 struct mlx5_ifc_eqc_bits eq_context_entry; 5000 5001 u8 reserved_2[0x40]; 5002 5003 u8 event_bitmask[0x40]; 5004 5005 u8 reserved_3[0x580]; 5006 5007 u8 pas[0][0x40]; 5008 }; 5009 5010 struct mlx5_ifc_query_eq_in_bits { 5011 u8 opcode[0x10]; 5012 u8 reserved_0[0x10]; 5013 5014 u8 reserved_1[0x10]; 5015 u8 op_mod[0x10]; 5016 5017 u8 reserved_2[0x18]; 5018 u8 eq_number[0x8]; 5019 5020 u8 reserved_3[0x20]; 5021 }; 5022 5023 struct mlx5_ifc_query_dct_out_bits { 5024 u8 status[0x8]; 5025 u8 reserved_0[0x18]; 5026 5027 u8 syndrome[0x20]; 5028 5029 u8 reserved_1[0x40]; 5030 5031 struct mlx5_ifc_dctc_bits dct_context_entry; 5032 5033 u8 reserved_2[0x180]; 5034 }; 5035 5036 struct mlx5_ifc_query_dct_in_bits { 5037 u8 opcode[0x10]; 5038 u8 reserved_0[0x10]; 5039 5040 u8 reserved_1[0x10]; 5041 u8 op_mod[0x10]; 5042 5043 u8 reserved_2[0x8]; 5044 u8 dctn[0x18]; 5045 5046 u8 reserved_3[0x20]; 5047 }; 5048 5049 struct mlx5_ifc_query_dc_cnak_trace_out_bits { 5050 u8 status[0x8]; 5051 u8 reserved_0[0x18]; 5052 5053 u8 syndrome[0x20]; 5054 5055 u8 enable[0x1]; 5056 u8 reserved_1[0x1f]; 5057 5058 u8 reserved_2[0x160]; 5059 5060 struct mlx5_ifc_cmd_pas_bits pas; 5061 }; 5062 5063 struct mlx5_ifc_query_dc_cnak_trace_in_bits { 5064 u8 opcode[0x10]; 5065 u8 reserved_0[0x10]; 5066 5067 u8 reserved_1[0x10]; 5068 u8 op_mod[0x10]; 5069 5070 u8 reserved_2[0x40]; 5071 }; 5072 5073 struct mlx5_ifc_query_cq_out_bits { 5074 u8 status[0x8]; 5075 u8 reserved_0[0x18]; 5076 5077 u8 syndrome[0x20]; 5078 5079 u8 reserved_1[0x40]; 5080 5081 struct mlx5_ifc_cqc_bits cq_context; 5082 5083 u8 reserved_2[0x600]; 5084 5085 u8 pas[0][0x40]; 5086 }; 5087 5088 struct mlx5_ifc_query_cq_in_bits { 5089 u8 opcode[0x10]; 5090 u8 reserved_0[0x10]; 5091 5092 u8 reserved_1[0x10]; 5093 u8 op_mod[0x10]; 5094 5095 u8 reserved_2[0x8]; 5096 u8 cqn[0x18]; 5097 5098 u8 reserved_3[0x20]; 5099 }; 5100 5101 struct mlx5_ifc_query_cong_status_out_bits { 5102 u8 status[0x8]; 5103 u8 reserved_0[0x18]; 5104 5105 u8 syndrome[0x20]; 5106 5107 u8 reserved_1[0x20]; 5108 5109 u8 enable[0x1]; 5110 u8 tag_enable[0x1]; 5111 u8 reserved_2[0x1e]; 5112 }; 5113 5114 struct mlx5_ifc_query_cong_status_in_bits { 5115 u8 opcode[0x10]; 5116 u8 reserved_0[0x10]; 5117 5118 u8 reserved_1[0x10]; 5119 u8 op_mod[0x10]; 5120 5121 u8 reserved_2[0x18]; 5122 u8 priority[0x4]; 5123 u8 cong_protocol[0x4]; 5124 5125 u8 reserved_3[0x20]; 5126 }; 5127 5128 struct mlx5_ifc_query_cong_statistics_out_bits { 5129 u8 status[0x8]; 5130 u8 reserved_0[0x18]; 5131 5132 u8 syndrome[0x20]; 5133 5134 u8 reserved_1[0x40]; 5135 5136 u8 rp_cur_flows[0x20]; 5137 5138 u8 sum_flows[0x20]; 5139 5140 u8 rp_cnp_ignored_high[0x20]; 5141 5142 u8 rp_cnp_ignored_low[0x20]; 5143 5144 u8 rp_cnp_handled_high[0x20]; 5145 5146 u8 rp_cnp_handled_low[0x20]; 5147 5148 u8 reserved_2[0x100]; 5149 5150 u8 time_stamp_high[0x20]; 5151 5152 u8 time_stamp_low[0x20]; 5153 5154 u8 accumulators_period[0x20]; 5155 5156 u8 np_ecn_marked_roce_packets_high[0x20]; 5157 5158 u8 np_ecn_marked_roce_packets_low[0x20]; 5159 5160 u8 np_cnp_sent_high[0x20]; 5161 5162 u8 np_cnp_sent_low[0x20]; 5163 5164 u8 reserved_3[0x560]; 5165 }; 5166 5167 struct mlx5_ifc_query_cong_statistics_in_bits { 5168 u8 opcode[0x10]; 5169 u8 reserved_0[0x10]; 5170 5171 u8 reserved_1[0x10]; 5172 u8 op_mod[0x10]; 5173 5174 u8 clear[0x1]; 5175 u8 reserved_2[0x1f]; 5176 5177 u8 reserved_3[0x20]; 5178 }; 5179 5180 struct mlx5_ifc_query_cong_params_out_bits { 5181 u8 status[0x8]; 5182 u8 reserved_0[0x18]; 5183 5184 u8 syndrome[0x20]; 5185 5186 u8 reserved_1[0x40]; 5187 5188 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5189 }; 5190 5191 struct mlx5_ifc_query_cong_params_in_bits { 5192 u8 opcode[0x10]; 5193 u8 reserved_0[0x10]; 5194 5195 u8 reserved_1[0x10]; 5196 u8 op_mod[0x10]; 5197 5198 u8 reserved_2[0x1c]; 5199 u8 cong_protocol[0x4]; 5200 5201 u8 reserved_3[0x20]; 5202 }; 5203 5204 struct mlx5_ifc_query_burst_size_out_bits { 5205 u8 status[0x8]; 5206 u8 reserved_0[0x18]; 5207 5208 u8 syndrome[0x20]; 5209 5210 u8 reserved_1[0x20]; 5211 5212 u8 reserved_2[0x9]; 5213 u8 device_burst_size[0x17]; 5214 }; 5215 5216 struct mlx5_ifc_query_burst_size_in_bits { 5217 u8 opcode[0x10]; 5218 u8 reserved_0[0x10]; 5219 5220 u8 reserved_1[0x10]; 5221 u8 op_mod[0x10]; 5222 5223 u8 reserved_2[0x40]; 5224 }; 5225 5226 struct mlx5_ifc_query_adapter_out_bits { 5227 u8 status[0x8]; 5228 u8 reserved_0[0x18]; 5229 5230 u8 syndrome[0x20]; 5231 5232 u8 reserved_1[0x40]; 5233 5234 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5235 }; 5236 5237 struct mlx5_ifc_query_adapter_in_bits { 5238 u8 opcode[0x10]; 5239 u8 reserved_0[0x10]; 5240 5241 u8 reserved_1[0x10]; 5242 u8 op_mod[0x10]; 5243 5244 u8 reserved_2[0x40]; 5245 }; 5246 5247 struct mlx5_ifc_qp_2rst_out_bits { 5248 u8 status[0x8]; 5249 u8 reserved_0[0x18]; 5250 5251 u8 syndrome[0x20]; 5252 5253 u8 reserved_1[0x40]; 5254 }; 5255 5256 struct mlx5_ifc_qp_2rst_in_bits { 5257 u8 opcode[0x10]; 5258 u8 uid[0x10]; 5259 5260 u8 reserved_1[0x10]; 5261 u8 op_mod[0x10]; 5262 5263 u8 reserved_2[0x8]; 5264 u8 qpn[0x18]; 5265 5266 u8 reserved_3[0x20]; 5267 }; 5268 5269 struct mlx5_ifc_qp_2err_out_bits { 5270 u8 status[0x8]; 5271 u8 reserved_0[0x18]; 5272 5273 u8 syndrome[0x20]; 5274 5275 u8 reserved_1[0x40]; 5276 }; 5277 5278 struct mlx5_ifc_qp_2err_in_bits { 5279 u8 opcode[0x10]; 5280 u8 uid[0x10]; 5281 5282 u8 reserved_1[0x10]; 5283 u8 op_mod[0x10]; 5284 5285 u8 reserved_2[0x8]; 5286 u8 qpn[0x18]; 5287 5288 u8 reserved_3[0x20]; 5289 }; 5290 5291 struct mlx5_ifc_para_vport_element_bits { 5292 u8 reserved_at_0[0xc]; 5293 u8 traffic_class[0x4]; 5294 u8 qos_para_vport_number[0x10]; 5295 }; 5296 5297 struct mlx5_ifc_page_fault_resume_out_bits { 5298 u8 status[0x8]; 5299 u8 reserved_0[0x18]; 5300 5301 u8 syndrome[0x20]; 5302 5303 u8 reserved_1[0x40]; 5304 }; 5305 5306 struct mlx5_ifc_page_fault_resume_in_bits { 5307 u8 opcode[0x10]; 5308 u8 reserved_0[0x10]; 5309 5310 u8 reserved_1[0x10]; 5311 u8 op_mod[0x10]; 5312 5313 u8 error[0x1]; 5314 u8 reserved_2[0x4]; 5315 u8 rdma[0x1]; 5316 u8 read_write[0x1]; 5317 u8 req_res[0x1]; 5318 u8 qpn[0x18]; 5319 5320 u8 reserved_3[0x20]; 5321 }; 5322 5323 struct mlx5_ifc_nop_out_bits { 5324 u8 status[0x8]; 5325 u8 reserved_0[0x18]; 5326 5327 u8 syndrome[0x20]; 5328 5329 u8 reserved_1[0x40]; 5330 }; 5331 5332 struct mlx5_ifc_nop_in_bits { 5333 u8 opcode[0x10]; 5334 u8 reserved_0[0x10]; 5335 5336 u8 reserved_1[0x10]; 5337 u8 op_mod[0x10]; 5338 5339 u8 reserved_2[0x40]; 5340 }; 5341 5342 struct mlx5_ifc_modify_vport_state_out_bits { 5343 u8 status[0x8]; 5344 u8 reserved_0[0x18]; 5345 5346 u8 syndrome[0x20]; 5347 5348 u8 reserved_1[0x40]; 5349 }; 5350 5351 enum { 5352 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5353 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5354 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5355 }; 5356 5357 enum { 5358 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5359 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5360 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5361 }; 5362 5363 struct mlx5_ifc_modify_vport_state_in_bits { 5364 u8 opcode[0x10]; 5365 u8 reserved_0[0x10]; 5366 5367 u8 reserved_1[0x10]; 5368 u8 op_mod[0x10]; 5369 5370 u8 other_vport[0x1]; 5371 u8 reserved_2[0xf]; 5372 u8 vport_number[0x10]; 5373 5374 u8 reserved_3[0x18]; 5375 u8 admin_state[0x4]; 5376 u8 reserved_4[0x4]; 5377 }; 5378 5379 struct mlx5_ifc_modify_tis_out_bits { 5380 u8 status[0x8]; 5381 u8 reserved_0[0x18]; 5382 5383 u8 syndrome[0x20]; 5384 5385 u8 reserved_1[0x40]; 5386 }; 5387 5388 struct mlx5_ifc_modify_tis_bitmask_bits { 5389 u8 reserved_at_0[0x20]; 5390 5391 u8 reserved_at_20[0x1d]; 5392 u8 lag_tx_port_affinity[0x1]; 5393 u8 strict_lag_tx_port_affinity[0x1]; 5394 u8 prio[0x1]; 5395 }; 5396 5397 struct mlx5_ifc_modify_tis_in_bits { 5398 u8 opcode[0x10]; 5399 u8 reserved_0[0x10]; 5400 5401 u8 reserved_1[0x10]; 5402 u8 op_mod[0x10]; 5403 5404 u8 reserved_2[0x8]; 5405 u8 tisn[0x18]; 5406 5407 u8 reserved_3[0x20]; 5408 5409 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5410 5411 u8 reserved_4[0x40]; 5412 5413 struct mlx5_ifc_tisc_bits ctx; 5414 }; 5415 5416 struct mlx5_ifc_modify_tir_out_bits { 5417 u8 status[0x8]; 5418 u8 reserved_0[0x18]; 5419 5420 u8 syndrome[0x20]; 5421 5422 u8 reserved_1[0x40]; 5423 }; 5424 5425 enum 5426 { 5427 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5428 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5429 }; 5430 5431 struct mlx5_ifc_modify_tir_in_bits { 5432 u8 opcode[0x10]; 5433 u8 reserved_0[0x10]; 5434 5435 u8 reserved_1[0x10]; 5436 u8 op_mod[0x10]; 5437 5438 u8 reserved_2[0x8]; 5439 u8 tirn[0x18]; 5440 5441 u8 reserved_3[0x20]; 5442 5443 u8 modify_bitmask[0x40]; 5444 5445 u8 reserved_4[0x40]; 5446 5447 struct mlx5_ifc_tirc_bits tir_context; 5448 }; 5449 5450 struct mlx5_ifc_modify_sq_out_bits { 5451 u8 status[0x8]; 5452 u8 reserved_0[0x18]; 5453 5454 u8 syndrome[0x20]; 5455 5456 u8 reserved_1[0x40]; 5457 }; 5458 5459 struct mlx5_ifc_modify_sq_in_bits { 5460 u8 opcode[0x10]; 5461 u8 reserved_0[0x10]; 5462 5463 u8 reserved_1[0x10]; 5464 u8 op_mod[0x10]; 5465 5466 u8 sq_state[0x4]; 5467 u8 reserved_2[0x4]; 5468 u8 sqn[0x18]; 5469 5470 u8 reserved_3[0x20]; 5471 5472 u8 modify_bitmask[0x40]; 5473 5474 u8 reserved_4[0x40]; 5475 5476 struct mlx5_ifc_sqc_bits ctx; 5477 }; 5478 5479 struct mlx5_ifc_modify_scheduling_element_out_bits { 5480 u8 status[0x8]; 5481 u8 reserved_at_8[0x18]; 5482 5483 u8 syndrome[0x20]; 5484 5485 u8 reserved_at_40[0x1c0]; 5486 }; 5487 5488 enum { 5489 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5490 }; 5491 5492 enum { 5493 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5494 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5495 }; 5496 5497 struct mlx5_ifc_modify_scheduling_element_in_bits { 5498 u8 opcode[0x10]; 5499 u8 reserved_at_10[0x10]; 5500 5501 u8 reserved_at_20[0x10]; 5502 u8 op_mod[0x10]; 5503 5504 u8 scheduling_hierarchy[0x8]; 5505 u8 reserved_at_48[0x18]; 5506 5507 u8 scheduling_element_id[0x20]; 5508 5509 u8 reserved_at_80[0x20]; 5510 5511 u8 modify_bitmask[0x20]; 5512 5513 u8 reserved_at_c0[0x40]; 5514 5515 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5516 5517 u8 reserved_at_300[0x100]; 5518 }; 5519 5520 struct mlx5_ifc_modify_rqt_out_bits { 5521 u8 status[0x8]; 5522 u8 reserved_0[0x18]; 5523 5524 u8 syndrome[0x20]; 5525 5526 u8 reserved_1[0x40]; 5527 }; 5528 5529 struct mlx5_ifc_modify_rqt_in_bits { 5530 u8 opcode[0x10]; 5531 u8 reserved_0[0x10]; 5532 5533 u8 reserved_1[0x10]; 5534 u8 op_mod[0x10]; 5535 5536 u8 reserved_2[0x8]; 5537 u8 rqtn[0x18]; 5538 5539 u8 reserved_3[0x20]; 5540 5541 u8 modify_bitmask[0x40]; 5542 5543 u8 reserved_4[0x40]; 5544 5545 struct mlx5_ifc_rqtc_bits ctx; 5546 }; 5547 5548 struct mlx5_ifc_modify_rq_out_bits { 5549 u8 status[0x8]; 5550 u8 reserved_0[0x18]; 5551 5552 u8 syndrome[0x20]; 5553 5554 u8 reserved_1[0x40]; 5555 }; 5556 5557 enum { 5558 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5559 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5560 }; 5561 5562 struct mlx5_ifc_modify_rq_in_bits { 5563 u8 opcode[0x10]; 5564 u8 reserved_0[0x10]; 5565 5566 u8 reserved_1[0x10]; 5567 u8 op_mod[0x10]; 5568 5569 u8 rq_state[0x4]; 5570 u8 reserved_2[0x4]; 5571 u8 rqn[0x18]; 5572 5573 u8 reserved_3[0x20]; 5574 5575 u8 modify_bitmask[0x40]; 5576 5577 u8 reserved_4[0x40]; 5578 5579 struct mlx5_ifc_rqc_bits ctx; 5580 }; 5581 5582 struct mlx5_ifc_modify_rmp_out_bits { 5583 u8 status[0x8]; 5584 u8 reserved_0[0x18]; 5585 5586 u8 syndrome[0x20]; 5587 5588 u8 reserved_1[0x40]; 5589 }; 5590 5591 struct mlx5_ifc_rmp_bitmask_bits { 5592 u8 reserved[0x20]; 5593 5594 u8 reserved1[0x1f]; 5595 u8 lwm[0x1]; 5596 }; 5597 5598 struct mlx5_ifc_modify_rmp_in_bits { 5599 u8 opcode[0x10]; 5600 u8 reserved_0[0x10]; 5601 5602 u8 reserved_1[0x10]; 5603 u8 op_mod[0x10]; 5604 5605 u8 rmp_state[0x4]; 5606 u8 reserved_2[0x4]; 5607 u8 rmpn[0x18]; 5608 5609 u8 reserved_3[0x20]; 5610 5611 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5612 5613 u8 reserved_4[0x40]; 5614 5615 struct mlx5_ifc_rmpc_bits ctx; 5616 }; 5617 5618 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5619 u8 status[0x8]; 5620 u8 reserved_0[0x18]; 5621 5622 u8 syndrome[0x20]; 5623 5624 u8 reserved_1[0x40]; 5625 }; 5626 5627 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5628 u8 reserved_0[0x14]; 5629 u8 disable_uc_local_lb[0x1]; 5630 u8 disable_mc_local_lb[0x1]; 5631 u8 node_guid[0x1]; 5632 u8 port_guid[0x1]; 5633 u8 min_wqe_inline_mode[0x1]; 5634 u8 mtu[0x1]; 5635 u8 change_event[0x1]; 5636 u8 promisc[0x1]; 5637 u8 permanent_address[0x1]; 5638 u8 addresses_list[0x1]; 5639 u8 roce_en[0x1]; 5640 u8 reserved_1[0x1]; 5641 }; 5642 5643 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5644 u8 opcode[0x10]; 5645 u8 reserved_0[0x10]; 5646 5647 u8 reserved_1[0x10]; 5648 u8 op_mod[0x10]; 5649 5650 u8 other_vport[0x1]; 5651 u8 reserved_2[0xf]; 5652 u8 vport_number[0x10]; 5653 5654 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5655 5656 u8 reserved_3[0x780]; 5657 5658 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5659 }; 5660 5661 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5662 u8 status[0x8]; 5663 u8 reserved_0[0x18]; 5664 5665 u8 syndrome[0x20]; 5666 5667 u8 reserved_1[0x40]; 5668 }; 5669 5670 struct mlx5_ifc_grh_bits { 5671 u8 ip_version[4]; 5672 u8 traffic_class[8]; 5673 u8 flow_label[20]; 5674 u8 payload_length[16]; 5675 u8 next_header[8]; 5676 u8 hop_limit[8]; 5677 u8 sgid[128]; 5678 u8 dgid[128]; 5679 }; 5680 5681 struct mlx5_ifc_bth_bits { 5682 u8 opcode[8]; 5683 u8 se[1]; 5684 u8 migreq[1]; 5685 u8 pad_count[2]; 5686 u8 tver[4]; 5687 u8 p_key[16]; 5688 u8 reserved8[8]; 5689 u8 dest_qp[24]; 5690 u8 ack_req[1]; 5691 u8 reserved7[7]; 5692 u8 psn[24]; 5693 }; 5694 5695 struct mlx5_ifc_aeth_bits { 5696 u8 syndrome[8]; 5697 u8 msn[24]; 5698 }; 5699 5700 struct mlx5_ifc_dceth_bits { 5701 u8 reserved0[8]; 5702 u8 session_id[24]; 5703 u8 reserved1[8]; 5704 u8 dci_dct[24]; 5705 }; 5706 5707 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5708 u8 opcode[0x10]; 5709 u8 reserved_0[0x10]; 5710 5711 u8 reserved_1[0x10]; 5712 u8 op_mod[0x10]; 5713 5714 u8 other_vport[0x1]; 5715 u8 reserved_2[0xb]; 5716 u8 port_num[0x4]; 5717 u8 vport_number[0x10]; 5718 5719 u8 reserved_3[0x20]; 5720 5721 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5722 }; 5723 5724 struct mlx5_ifc_modify_flow_table_out_bits { 5725 u8 status[0x8]; 5726 u8 reserved_at_8[0x18]; 5727 5728 u8 syndrome[0x20]; 5729 5730 u8 reserved_at_40[0x40]; 5731 }; 5732 5733 enum { 5734 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 5735 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 5736 }; 5737 5738 struct mlx5_ifc_modify_flow_table_in_bits { 5739 u8 opcode[0x10]; 5740 u8 reserved_at_10[0x10]; 5741 5742 u8 reserved_at_20[0x10]; 5743 u8 op_mod[0x10]; 5744 5745 u8 other_vport[0x1]; 5746 u8 reserved_at_41[0xf]; 5747 u8 vport_number[0x10]; 5748 5749 u8 reserved_at_60[0x10]; 5750 u8 modify_field_select[0x10]; 5751 5752 u8 table_type[0x8]; 5753 u8 reserved_at_88[0x18]; 5754 5755 u8 reserved_at_a0[0x8]; 5756 u8 table_id[0x18]; 5757 5758 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5759 }; 5760 5761 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5762 u8 status[0x8]; 5763 u8 reserved_0[0x18]; 5764 5765 u8 syndrome[0x20]; 5766 5767 u8 reserved_1[0x40]; 5768 }; 5769 5770 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5771 u8 reserved[0x1c]; 5772 u8 vport_cvlan_insert[0x1]; 5773 u8 vport_svlan_insert[0x1]; 5774 u8 vport_cvlan_strip[0x1]; 5775 u8 vport_svlan_strip[0x1]; 5776 }; 5777 5778 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5779 u8 opcode[0x10]; 5780 u8 reserved_0[0x10]; 5781 5782 u8 reserved_1[0x10]; 5783 u8 op_mod[0x10]; 5784 5785 u8 other_vport[0x1]; 5786 u8 reserved_2[0xf]; 5787 u8 vport_number[0x10]; 5788 5789 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5790 5791 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5792 }; 5793 5794 struct mlx5_ifc_modify_cq_out_bits { 5795 u8 status[0x8]; 5796 u8 reserved_0[0x18]; 5797 5798 u8 syndrome[0x20]; 5799 5800 u8 reserved_1[0x40]; 5801 }; 5802 5803 enum { 5804 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5805 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5806 }; 5807 5808 struct mlx5_ifc_modify_cq_in_bits { 5809 u8 opcode[0x10]; 5810 u8 reserved_0[0x10]; 5811 5812 u8 reserved_1[0x10]; 5813 u8 op_mod[0x10]; 5814 5815 u8 reserved_2[0x8]; 5816 u8 cqn[0x18]; 5817 5818 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5819 5820 struct mlx5_ifc_cqc_bits cq_context; 5821 5822 u8 reserved_3[0x600]; 5823 5824 u8 pas[0][0x40]; 5825 }; 5826 5827 struct mlx5_ifc_modify_cong_status_out_bits { 5828 u8 status[0x8]; 5829 u8 reserved_0[0x18]; 5830 5831 u8 syndrome[0x20]; 5832 5833 u8 reserved_1[0x40]; 5834 }; 5835 5836 struct mlx5_ifc_modify_cong_status_in_bits { 5837 u8 opcode[0x10]; 5838 u8 reserved_0[0x10]; 5839 5840 u8 reserved_1[0x10]; 5841 u8 op_mod[0x10]; 5842 5843 u8 reserved_2[0x18]; 5844 u8 priority[0x4]; 5845 u8 cong_protocol[0x4]; 5846 5847 u8 enable[0x1]; 5848 u8 tag_enable[0x1]; 5849 u8 reserved_3[0x1e]; 5850 }; 5851 5852 struct mlx5_ifc_modify_cong_params_out_bits { 5853 u8 status[0x8]; 5854 u8 reserved_0[0x18]; 5855 5856 u8 syndrome[0x20]; 5857 5858 u8 reserved_1[0x40]; 5859 }; 5860 5861 struct mlx5_ifc_modify_cong_params_in_bits { 5862 u8 opcode[0x10]; 5863 u8 reserved_0[0x10]; 5864 5865 u8 reserved_1[0x10]; 5866 u8 op_mod[0x10]; 5867 5868 u8 reserved_2[0x1c]; 5869 u8 cong_protocol[0x4]; 5870 5871 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5872 5873 u8 reserved_3[0x80]; 5874 5875 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5876 }; 5877 5878 struct mlx5_ifc_manage_pages_out_bits { 5879 u8 status[0x8]; 5880 u8 reserved_0[0x18]; 5881 5882 u8 syndrome[0x20]; 5883 5884 u8 output_num_entries[0x20]; 5885 5886 u8 reserved_1[0x20]; 5887 5888 u8 pas[0][0x40]; 5889 }; 5890 5891 enum { 5892 MLX5_PAGES_CANT_GIVE = 0x0, 5893 MLX5_PAGES_GIVE = 0x1, 5894 MLX5_PAGES_TAKE = 0x2, 5895 }; 5896 5897 struct mlx5_ifc_manage_pages_in_bits { 5898 u8 opcode[0x10]; 5899 u8 reserved_0[0x10]; 5900 5901 u8 reserved_1[0x10]; 5902 u8 op_mod[0x10]; 5903 5904 u8 reserved_2[0x10]; 5905 u8 function_id[0x10]; 5906 5907 u8 input_num_entries[0x20]; 5908 5909 u8 pas[0][0x40]; 5910 }; 5911 5912 struct mlx5_ifc_mad_ifc_out_bits { 5913 u8 status[0x8]; 5914 u8 reserved_0[0x18]; 5915 5916 u8 syndrome[0x20]; 5917 5918 u8 reserved_1[0x40]; 5919 5920 u8 response_mad_packet[256][0x8]; 5921 }; 5922 5923 struct mlx5_ifc_mad_ifc_in_bits { 5924 u8 opcode[0x10]; 5925 u8 reserved_0[0x10]; 5926 5927 u8 reserved_1[0x10]; 5928 u8 op_mod[0x10]; 5929 5930 u8 remote_lid[0x10]; 5931 u8 reserved_2[0x8]; 5932 u8 port[0x8]; 5933 5934 u8 reserved_3[0x20]; 5935 5936 u8 mad[256][0x8]; 5937 }; 5938 5939 struct mlx5_ifc_init_hca_out_bits { 5940 u8 status[0x8]; 5941 u8 reserved_0[0x18]; 5942 5943 u8 syndrome[0x20]; 5944 5945 u8 reserved_1[0x40]; 5946 }; 5947 5948 enum { 5949 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 5950 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 5951 }; 5952 5953 struct mlx5_ifc_init_hca_in_bits { 5954 u8 opcode[0x10]; 5955 u8 reserved_0[0x10]; 5956 5957 u8 reserved_1[0x10]; 5958 u8 op_mod[0x10]; 5959 5960 u8 reserved_2[0x40]; 5961 }; 5962 5963 struct mlx5_ifc_init2rtr_qp_out_bits { 5964 u8 status[0x8]; 5965 u8 reserved_0[0x18]; 5966 5967 u8 syndrome[0x20]; 5968 5969 u8 reserved_1[0x40]; 5970 }; 5971 5972 struct mlx5_ifc_init2rtr_qp_in_bits { 5973 u8 opcode[0x10]; 5974 u8 uid[0x10]; 5975 5976 u8 reserved_1[0x10]; 5977 u8 op_mod[0x10]; 5978 5979 u8 reserved_2[0x8]; 5980 u8 qpn[0x18]; 5981 5982 u8 reserved_3[0x20]; 5983 5984 u8 opt_param_mask[0x20]; 5985 5986 u8 reserved_4[0x20]; 5987 5988 struct mlx5_ifc_qpc_bits qpc; 5989 5990 u8 reserved_5[0x80]; 5991 }; 5992 5993 struct mlx5_ifc_init2init_qp_out_bits { 5994 u8 status[0x8]; 5995 u8 reserved_0[0x18]; 5996 5997 u8 syndrome[0x20]; 5998 5999 u8 reserved_1[0x40]; 6000 }; 6001 6002 struct mlx5_ifc_init2init_qp_in_bits { 6003 u8 opcode[0x10]; 6004 u8 uid[0x10]; 6005 6006 u8 reserved_1[0x10]; 6007 u8 op_mod[0x10]; 6008 6009 u8 reserved_2[0x8]; 6010 u8 qpn[0x18]; 6011 6012 u8 reserved_3[0x20]; 6013 6014 u8 opt_param_mask[0x20]; 6015 6016 u8 reserved_4[0x20]; 6017 6018 struct mlx5_ifc_qpc_bits qpc; 6019 6020 u8 reserved_5[0x80]; 6021 }; 6022 6023 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6024 u8 status[0x8]; 6025 u8 reserved_0[0x18]; 6026 6027 u8 syndrome[0x20]; 6028 6029 u8 reserved_1[0x40]; 6030 6031 u8 packet_headers_log[128][0x8]; 6032 6033 u8 packet_syndrome[64][0x8]; 6034 }; 6035 6036 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6037 u8 opcode[0x10]; 6038 u8 reserved_0[0x10]; 6039 6040 u8 reserved_1[0x10]; 6041 u8 op_mod[0x10]; 6042 6043 u8 reserved_2[0x40]; 6044 }; 6045 6046 struct mlx5_ifc_encryption_key_obj_bits { 6047 u8 modify_field_select[0x40]; 6048 6049 u8 reserved_at_40[0x14]; 6050 u8 key_size[0x4]; 6051 u8 reserved_at_58[0x4]; 6052 u8 key_type[0x4]; 6053 6054 u8 reserved_at_60[0x8]; 6055 u8 pd[0x18]; 6056 6057 u8 reserved_at_80[0x180]; 6058 6059 u8 key[8][0x20]; 6060 6061 u8 reserved_at_300[0x500]; 6062 }; 6063 6064 struct mlx5_ifc_gen_eqe_in_bits { 6065 u8 opcode[0x10]; 6066 u8 reserved_0[0x10]; 6067 6068 u8 reserved_1[0x10]; 6069 u8 op_mod[0x10]; 6070 6071 u8 reserved_2[0x18]; 6072 u8 eq_number[0x8]; 6073 6074 u8 reserved_3[0x20]; 6075 6076 u8 eqe[64][0x8]; 6077 }; 6078 6079 struct mlx5_ifc_gen_eq_out_bits { 6080 u8 status[0x8]; 6081 u8 reserved_0[0x18]; 6082 6083 u8 syndrome[0x20]; 6084 6085 u8 reserved_1[0x40]; 6086 }; 6087 6088 struct mlx5_ifc_enable_hca_out_bits { 6089 u8 status[0x8]; 6090 u8 reserved_0[0x18]; 6091 6092 u8 syndrome[0x20]; 6093 6094 u8 reserved_1[0x20]; 6095 }; 6096 6097 struct mlx5_ifc_enable_hca_in_bits { 6098 u8 opcode[0x10]; 6099 u8 reserved_0[0x10]; 6100 6101 u8 reserved_1[0x10]; 6102 u8 op_mod[0x10]; 6103 6104 u8 reserved_2[0x10]; 6105 u8 function_id[0x10]; 6106 6107 u8 reserved_3[0x20]; 6108 }; 6109 6110 struct mlx5_ifc_drain_dct_out_bits { 6111 u8 status[0x8]; 6112 u8 reserved_0[0x18]; 6113 6114 u8 syndrome[0x20]; 6115 6116 u8 reserved_1[0x40]; 6117 }; 6118 6119 struct mlx5_ifc_drain_dct_in_bits { 6120 u8 opcode[0x10]; 6121 u8 uid[0x10]; 6122 6123 u8 reserved_1[0x10]; 6124 u8 op_mod[0x10]; 6125 6126 u8 reserved_2[0x8]; 6127 u8 dctn[0x18]; 6128 6129 u8 reserved_3[0x20]; 6130 }; 6131 6132 struct mlx5_ifc_disable_hca_out_bits { 6133 u8 status[0x8]; 6134 u8 reserved_0[0x18]; 6135 6136 u8 syndrome[0x20]; 6137 6138 u8 reserved_1[0x20]; 6139 }; 6140 6141 struct mlx5_ifc_disable_hca_in_bits { 6142 u8 opcode[0x10]; 6143 u8 reserved_0[0x10]; 6144 6145 u8 reserved_1[0x10]; 6146 u8 op_mod[0x10]; 6147 6148 u8 reserved_2[0x10]; 6149 u8 function_id[0x10]; 6150 6151 u8 reserved_3[0x20]; 6152 }; 6153 6154 struct mlx5_ifc_detach_from_mcg_out_bits { 6155 u8 status[0x8]; 6156 u8 reserved_0[0x18]; 6157 6158 u8 syndrome[0x20]; 6159 6160 u8 reserved_1[0x40]; 6161 }; 6162 6163 struct mlx5_ifc_detach_from_mcg_in_bits { 6164 u8 opcode[0x10]; 6165 u8 reserved_0[0x10]; 6166 6167 u8 reserved_1[0x10]; 6168 u8 op_mod[0x10]; 6169 6170 u8 reserved_2[0x8]; 6171 u8 qpn[0x18]; 6172 6173 u8 reserved_3[0x20]; 6174 6175 u8 multicast_gid[16][0x8]; 6176 }; 6177 6178 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6179 u8 status[0x8]; 6180 u8 reserved_0[0x18]; 6181 6182 u8 syndrome[0x20]; 6183 6184 u8 reserved_1[0x40]; 6185 }; 6186 6187 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6188 u8 opcode[0x10]; 6189 u8 reserved_0[0x10]; 6190 6191 u8 reserved_1[0x10]; 6192 u8 op_mod[0x10]; 6193 6194 u8 reserved_2[0x8]; 6195 u8 xrc_srqn[0x18]; 6196 6197 u8 reserved_3[0x20]; 6198 }; 6199 6200 struct mlx5_ifc_destroy_tis_out_bits { 6201 u8 status[0x8]; 6202 u8 reserved_0[0x18]; 6203 6204 u8 syndrome[0x20]; 6205 6206 u8 reserved_1[0x40]; 6207 }; 6208 6209 struct mlx5_ifc_destroy_tis_in_bits { 6210 u8 opcode[0x10]; 6211 u8 reserved_0[0x10]; 6212 6213 u8 reserved_1[0x10]; 6214 u8 op_mod[0x10]; 6215 6216 u8 reserved_2[0x8]; 6217 u8 tisn[0x18]; 6218 6219 u8 reserved_3[0x20]; 6220 }; 6221 6222 struct mlx5_ifc_destroy_tir_out_bits { 6223 u8 status[0x8]; 6224 u8 reserved_0[0x18]; 6225 6226 u8 syndrome[0x20]; 6227 6228 u8 reserved_1[0x40]; 6229 }; 6230 6231 struct mlx5_ifc_destroy_tir_in_bits { 6232 u8 opcode[0x10]; 6233 u8 reserved_0[0x10]; 6234 6235 u8 reserved_1[0x10]; 6236 u8 op_mod[0x10]; 6237 6238 u8 reserved_2[0x8]; 6239 u8 tirn[0x18]; 6240 6241 u8 reserved_3[0x20]; 6242 }; 6243 6244 struct mlx5_ifc_destroy_srq_out_bits { 6245 u8 status[0x8]; 6246 u8 reserved_0[0x18]; 6247 6248 u8 syndrome[0x20]; 6249 6250 u8 reserved_1[0x40]; 6251 }; 6252 6253 struct mlx5_ifc_destroy_srq_in_bits { 6254 u8 opcode[0x10]; 6255 u8 reserved_0[0x10]; 6256 6257 u8 reserved_1[0x10]; 6258 u8 op_mod[0x10]; 6259 6260 u8 reserved_2[0x8]; 6261 u8 srqn[0x18]; 6262 6263 u8 reserved_3[0x20]; 6264 }; 6265 6266 struct mlx5_ifc_destroy_sq_out_bits { 6267 u8 status[0x8]; 6268 u8 reserved_0[0x18]; 6269 6270 u8 syndrome[0x20]; 6271 6272 u8 reserved_1[0x40]; 6273 }; 6274 6275 struct mlx5_ifc_destroy_sq_in_bits { 6276 u8 opcode[0x10]; 6277 u8 uid[0x10]; 6278 6279 u8 reserved_1[0x10]; 6280 u8 op_mod[0x10]; 6281 6282 u8 reserved_2[0x8]; 6283 u8 sqn[0x18]; 6284 6285 u8 reserved_3[0x20]; 6286 }; 6287 6288 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6289 u8 status[0x8]; 6290 u8 reserved_at_8[0x18]; 6291 6292 u8 syndrome[0x20]; 6293 6294 u8 reserved_at_40[0x1c0]; 6295 }; 6296 6297 enum { 6298 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6299 }; 6300 6301 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6302 u8 opcode[0x10]; 6303 u8 reserved_at_10[0x10]; 6304 6305 u8 reserved_at_20[0x10]; 6306 u8 op_mod[0x10]; 6307 6308 u8 scheduling_hierarchy[0x8]; 6309 u8 reserved_at_48[0x18]; 6310 6311 u8 scheduling_element_id[0x20]; 6312 6313 u8 reserved_at_80[0x180]; 6314 }; 6315 6316 struct mlx5_ifc_destroy_rqt_out_bits { 6317 u8 status[0x8]; 6318 u8 reserved_0[0x18]; 6319 6320 u8 syndrome[0x20]; 6321 6322 u8 reserved_1[0x40]; 6323 }; 6324 6325 struct mlx5_ifc_destroy_rqt_in_bits { 6326 u8 opcode[0x10]; 6327 u8 reserved_0[0x10]; 6328 6329 u8 reserved_1[0x10]; 6330 u8 op_mod[0x10]; 6331 6332 u8 reserved_2[0x8]; 6333 u8 rqtn[0x18]; 6334 6335 u8 reserved_3[0x20]; 6336 }; 6337 6338 struct mlx5_ifc_destroy_rq_out_bits { 6339 u8 status[0x8]; 6340 u8 reserved_0[0x18]; 6341 6342 u8 syndrome[0x20]; 6343 6344 u8 reserved_1[0x40]; 6345 }; 6346 6347 struct mlx5_ifc_destroy_rq_in_bits { 6348 u8 opcode[0x10]; 6349 u8 uid[0x10]; 6350 6351 u8 reserved_1[0x10]; 6352 u8 op_mod[0x10]; 6353 6354 u8 reserved_2[0x8]; 6355 u8 rqn[0x18]; 6356 6357 u8 reserved_3[0x20]; 6358 }; 6359 6360 struct mlx5_ifc_destroy_rmp_out_bits { 6361 u8 status[0x8]; 6362 u8 reserved_0[0x18]; 6363 6364 u8 syndrome[0x20]; 6365 6366 u8 reserved_1[0x40]; 6367 }; 6368 6369 struct mlx5_ifc_destroy_rmp_in_bits { 6370 u8 opcode[0x10]; 6371 u8 reserved_0[0x10]; 6372 6373 u8 reserved_1[0x10]; 6374 u8 op_mod[0x10]; 6375 6376 u8 reserved_2[0x8]; 6377 u8 rmpn[0x18]; 6378 6379 u8 reserved_3[0x20]; 6380 }; 6381 6382 struct mlx5_ifc_destroy_qp_out_bits { 6383 u8 status[0x8]; 6384 u8 reserved_0[0x18]; 6385 6386 u8 syndrome[0x20]; 6387 6388 u8 reserved_1[0x40]; 6389 }; 6390 6391 struct mlx5_ifc_destroy_qp_in_bits { 6392 u8 opcode[0x10]; 6393 u8 uid[0x10]; 6394 6395 u8 reserved_1[0x10]; 6396 u8 op_mod[0x10]; 6397 6398 u8 reserved_2[0x8]; 6399 u8 qpn[0x18]; 6400 6401 u8 reserved_3[0x20]; 6402 }; 6403 6404 struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6405 u8 status[0x8]; 6406 u8 reserved_at_8[0x18]; 6407 6408 u8 syndrome[0x20]; 6409 6410 u8 reserved_at_40[0x1c0]; 6411 }; 6412 6413 struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6414 u8 opcode[0x10]; 6415 u8 reserved_at_10[0x10]; 6416 6417 u8 reserved_at_20[0x10]; 6418 u8 op_mod[0x10]; 6419 6420 u8 reserved_at_40[0x20]; 6421 6422 u8 reserved_at_60[0x10]; 6423 u8 qos_para_vport_number[0x10]; 6424 6425 u8 reserved_at_80[0x180]; 6426 }; 6427 6428 struct mlx5_ifc_destroy_psv_out_bits { 6429 u8 status[0x8]; 6430 u8 reserved_0[0x18]; 6431 6432 u8 syndrome[0x20]; 6433 6434 u8 reserved_1[0x40]; 6435 }; 6436 6437 struct mlx5_ifc_destroy_psv_in_bits { 6438 u8 opcode[0x10]; 6439 u8 reserved_0[0x10]; 6440 6441 u8 reserved_1[0x10]; 6442 u8 op_mod[0x10]; 6443 6444 u8 reserved_2[0x8]; 6445 u8 psvn[0x18]; 6446 6447 u8 reserved_3[0x20]; 6448 }; 6449 6450 struct mlx5_ifc_destroy_mkey_out_bits { 6451 u8 status[0x8]; 6452 u8 reserved_0[0x18]; 6453 6454 u8 syndrome[0x20]; 6455 6456 u8 reserved_1[0x40]; 6457 }; 6458 6459 struct mlx5_ifc_destroy_mkey_in_bits { 6460 u8 opcode[0x10]; 6461 u8 reserved_0[0x10]; 6462 6463 u8 reserved_1[0x10]; 6464 u8 op_mod[0x10]; 6465 6466 u8 reserved_2[0x8]; 6467 u8 mkey_index[0x18]; 6468 6469 u8 reserved_3[0x20]; 6470 }; 6471 6472 struct mlx5_ifc_destroy_flow_table_out_bits { 6473 u8 status[0x8]; 6474 u8 reserved_0[0x18]; 6475 6476 u8 syndrome[0x20]; 6477 6478 u8 reserved_1[0x40]; 6479 }; 6480 6481 struct mlx5_ifc_destroy_flow_table_in_bits { 6482 u8 opcode[0x10]; 6483 u8 reserved_0[0x10]; 6484 6485 u8 reserved_1[0x10]; 6486 u8 op_mod[0x10]; 6487 6488 u8 other_vport[0x1]; 6489 u8 reserved_2[0xf]; 6490 u8 vport_number[0x10]; 6491 6492 u8 reserved_3[0x20]; 6493 6494 u8 table_type[0x8]; 6495 u8 reserved_4[0x18]; 6496 6497 u8 reserved_5[0x8]; 6498 u8 table_id[0x18]; 6499 6500 u8 reserved_6[0x140]; 6501 }; 6502 6503 struct mlx5_ifc_destroy_flow_group_out_bits { 6504 u8 status[0x8]; 6505 u8 reserved_0[0x18]; 6506 6507 u8 syndrome[0x20]; 6508 6509 u8 reserved_1[0x40]; 6510 }; 6511 6512 struct mlx5_ifc_destroy_flow_group_in_bits { 6513 u8 opcode[0x10]; 6514 u8 reserved_0[0x10]; 6515 6516 u8 reserved_1[0x10]; 6517 u8 op_mod[0x10]; 6518 6519 u8 other_vport[0x1]; 6520 u8 reserved_2[0xf]; 6521 u8 vport_number[0x10]; 6522 6523 u8 reserved_3[0x20]; 6524 6525 u8 table_type[0x8]; 6526 u8 reserved_4[0x18]; 6527 6528 u8 reserved_5[0x8]; 6529 u8 table_id[0x18]; 6530 6531 u8 group_id[0x20]; 6532 6533 u8 reserved_6[0x120]; 6534 }; 6535 6536 struct mlx5_ifc_destroy_encryption_key_out_bits { 6537 u8 status[0x8]; 6538 u8 reserved_at_8[0x18]; 6539 6540 u8 syndrome[0x20]; 6541 6542 u8 reserved_at_40[0x40]; 6543 }; 6544 6545 struct mlx5_ifc_destroy_encryption_key_in_bits { 6546 u8 opcode[0x10]; 6547 u8 reserved_at_10[0x10]; 6548 6549 u8 reserved_at_20[0x10]; 6550 u8 obj_type[0x10]; 6551 6552 u8 obj_id[0x20]; 6553 6554 u8 reserved_at_60[0x20]; 6555 }; 6556 6557 struct mlx5_ifc_destroy_eq_out_bits { 6558 u8 status[0x8]; 6559 u8 reserved_0[0x18]; 6560 6561 u8 syndrome[0x20]; 6562 6563 u8 reserved_1[0x40]; 6564 }; 6565 6566 struct mlx5_ifc_destroy_eq_in_bits { 6567 u8 opcode[0x10]; 6568 u8 reserved_0[0x10]; 6569 6570 u8 reserved_1[0x10]; 6571 u8 op_mod[0x10]; 6572 6573 u8 reserved_2[0x18]; 6574 u8 eq_number[0x8]; 6575 6576 u8 reserved_3[0x20]; 6577 }; 6578 6579 struct mlx5_ifc_destroy_dct_out_bits { 6580 u8 status[0x8]; 6581 u8 reserved_0[0x18]; 6582 6583 u8 syndrome[0x20]; 6584 6585 u8 reserved_1[0x40]; 6586 }; 6587 6588 struct mlx5_ifc_destroy_dct_in_bits { 6589 u8 opcode[0x10]; 6590 u8 uid[0x10]; 6591 6592 u8 reserved_1[0x10]; 6593 u8 op_mod[0x10]; 6594 6595 u8 reserved_2[0x8]; 6596 u8 dctn[0x18]; 6597 6598 u8 reserved_3[0x20]; 6599 }; 6600 6601 struct mlx5_ifc_destroy_cq_out_bits { 6602 u8 status[0x8]; 6603 u8 reserved_0[0x18]; 6604 6605 u8 syndrome[0x20]; 6606 6607 u8 reserved_1[0x40]; 6608 }; 6609 6610 struct mlx5_ifc_destroy_cq_in_bits { 6611 u8 opcode[0x10]; 6612 u8 reserved_0[0x10]; 6613 6614 u8 reserved_1[0x10]; 6615 u8 op_mod[0x10]; 6616 6617 u8 reserved_2[0x8]; 6618 u8 cqn[0x18]; 6619 6620 u8 reserved_3[0x20]; 6621 }; 6622 6623 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6624 u8 status[0x8]; 6625 u8 reserved_0[0x18]; 6626 6627 u8 syndrome[0x20]; 6628 6629 u8 reserved_1[0x40]; 6630 }; 6631 6632 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6633 u8 opcode[0x10]; 6634 u8 reserved_0[0x10]; 6635 6636 u8 reserved_1[0x10]; 6637 u8 op_mod[0x10]; 6638 6639 u8 reserved_2[0x20]; 6640 6641 u8 reserved_3[0x10]; 6642 u8 vxlan_udp_port[0x10]; 6643 }; 6644 6645 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6646 u8 status[0x8]; 6647 u8 reserved_0[0x18]; 6648 6649 u8 syndrome[0x20]; 6650 6651 u8 reserved_1[0x40]; 6652 }; 6653 6654 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6655 u8 opcode[0x10]; 6656 u8 reserved_0[0x10]; 6657 6658 u8 reserved_1[0x10]; 6659 u8 op_mod[0x10]; 6660 6661 u8 reserved_2[0x60]; 6662 6663 u8 reserved_3[0x8]; 6664 u8 table_index[0x18]; 6665 6666 u8 reserved_4[0x140]; 6667 }; 6668 6669 struct mlx5_ifc_delete_fte_out_bits { 6670 u8 status[0x8]; 6671 u8 reserved_0[0x18]; 6672 6673 u8 syndrome[0x20]; 6674 6675 u8 reserved_1[0x40]; 6676 }; 6677 6678 struct mlx5_ifc_delete_fte_in_bits { 6679 u8 opcode[0x10]; 6680 u8 reserved_0[0x10]; 6681 6682 u8 reserved_1[0x10]; 6683 u8 op_mod[0x10]; 6684 6685 u8 other_vport[0x1]; 6686 u8 reserved_2[0xf]; 6687 u8 vport_number[0x10]; 6688 6689 u8 reserved_3[0x20]; 6690 6691 u8 table_type[0x8]; 6692 u8 reserved_4[0x18]; 6693 6694 u8 reserved_5[0x8]; 6695 u8 table_id[0x18]; 6696 6697 u8 reserved_6[0x40]; 6698 6699 u8 flow_index[0x20]; 6700 6701 u8 reserved_7[0xe0]; 6702 }; 6703 6704 struct mlx5_ifc_dealloc_xrcd_out_bits { 6705 u8 status[0x8]; 6706 u8 reserved_0[0x18]; 6707 6708 u8 syndrome[0x20]; 6709 6710 u8 reserved_1[0x40]; 6711 }; 6712 6713 struct mlx5_ifc_dealloc_xrcd_in_bits { 6714 u8 opcode[0x10]; 6715 u8 reserved_0[0x10]; 6716 6717 u8 reserved_1[0x10]; 6718 u8 op_mod[0x10]; 6719 6720 u8 reserved_2[0x8]; 6721 u8 xrcd[0x18]; 6722 6723 u8 reserved_3[0x20]; 6724 }; 6725 6726 struct mlx5_ifc_dealloc_uar_out_bits { 6727 u8 status[0x8]; 6728 u8 reserved_0[0x18]; 6729 6730 u8 syndrome[0x20]; 6731 6732 u8 reserved_1[0x40]; 6733 }; 6734 6735 struct mlx5_ifc_dealloc_uar_in_bits { 6736 u8 opcode[0x10]; 6737 u8 reserved_0[0x10]; 6738 6739 u8 reserved_1[0x10]; 6740 u8 op_mod[0x10]; 6741 6742 u8 reserved_2[0x8]; 6743 u8 uar[0x18]; 6744 6745 u8 reserved_3[0x20]; 6746 }; 6747 6748 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6749 u8 status[0x8]; 6750 u8 reserved_0[0x18]; 6751 6752 u8 syndrome[0x20]; 6753 6754 u8 reserved_1[0x40]; 6755 }; 6756 6757 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6758 u8 opcode[0x10]; 6759 u8 reserved_0[0x10]; 6760 6761 u8 reserved_1[0x10]; 6762 u8 op_mod[0x10]; 6763 6764 u8 reserved_2[0x8]; 6765 u8 transport_domain[0x18]; 6766 6767 u8 reserved_3[0x20]; 6768 }; 6769 6770 struct mlx5_ifc_dealloc_q_counter_out_bits { 6771 u8 status[0x8]; 6772 u8 reserved_0[0x18]; 6773 6774 u8 syndrome[0x20]; 6775 6776 u8 reserved_1[0x40]; 6777 }; 6778 6779 struct mlx5_ifc_counter_id_bits { 6780 u8 reserved[0x10]; 6781 u8 counter_id[0x10]; 6782 }; 6783 6784 struct mlx5_ifc_diagnostic_params_context_bits { 6785 u8 num_of_counters[0x10]; 6786 u8 reserved_2[0x8]; 6787 u8 log_num_of_samples[0x8]; 6788 6789 u8 single[0x1]; 6790 u8 repetitive[0x1]; 6791 u8 sync[0x1]; 6792 u8 clear[0x1]; 6793 u8 on_demand[0x1]; 6794 u8 enable[0x1]; 6795 u8 reserved_3[0x12]; 6796 u8 log_sample_period[0x8]; 6797 6798 u8 reserved_4[0x80]; 6799 6800 struct mlx5_ifc_counter_id_bits counter_id[0]; 6801 }; 6802 6803 struct mlx5_ifc_set_diagnostic_params_in_bits { 6804 u8 opcode[0x10]; 6805 u8 reserved_0[0x10]; 6806 6807 u8 reserved_1[0x10]; 6808 u8 op_mod[0x10]; 6809 6810 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 6811 }; 6812 6813 struct mlx5_ifc_set_diagnostic_params_out_bits { 6814 u8 status[0x8]; 6815 u8 reserved_0[0x18]; 6816 6817 u8 syndrome[0x20]; 6818 6819 u8 reserved_1[0x40]; 6820 }; 6821 6822 struct mlx5_ifc_query_diagnostic_counters_in_bits { 6823 u8 opcode[0x10]; 6824 u8 reserved_0[0x10]; 6825 6826 u8 reserved_1[0x10]; 6827 u8 op_mod[0x10]; 6828 6829 u8 num_of_samples[0x10]; 6830 u8 sample_index[0x10]; 6831 6832 u8 reserved_2[0x20]; 6833 }; 6834 6835 struct mlx5_ifc_diagnostic_counter_bits { 6836 u8 counter_id[0x10]; 6837 u8 sample_id[0x10]; 6838 6839 u8 time_stamp_31_0[0x20]; 6840 6841 u8 counter_value_h[0x20]; 6842 6843 u8 counter_value_l[0x20]; 6844 }; 6845 6846 struct mlx5_ifc_query_diagnostic_counters_out_bits { 6847 u8 status[0x8]; 6848 u8 reserved_0[0x18]; 6849 6850 u8 syndrome[0x20]; 6851 6852 u8 reserved_1[0x40]; 6853 6854 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 6855 }; 6856 6857 struct mlx5_ifc_dealloc_q_counter_in_bits { 6858 u8 opcode[0x10]; 6859 u8 reserved_0[0x10]; 6860 6861 u8 reserved_1[0x10]; 6862 u8 op_mod[0x10]; 6863 6864 u8 reserved_2[0x18]; 6865 u8 counter_set_id[0x8]; 6866 6867 u8 reserved_3[0x20]; 6868 }; 6869 6870 struct mlx5_ifc_dealloc_pd_out_bits { 6871 u8 status[0x8]; 6872 u8 reserved_0[0x18]; 6873 6874 u8 syndrome[0x20]; 6875 6876 u8 reserved_1[0x40]; 6877 }; 6878 6879 struct mlx5_ifc_dealloc_pd_in_bits { 6880 u8 opcode[0x10]; 6881 u8 reserved_0[0x10]; 6882 6883 u8 reserved_1[0x10]; 6884 u8 op_mod[0x10]; 6885 6886 u8 reserved_2[0x8]; 6887 u8 pd[0x18]; 6888 6889 u8 reserved_3[0x20]; 6890 }; 6891 6892 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6893 u8 status[0x8]; 6894 u8 reserved_0[0x18]; 6895 6896 u8 syndrome[0x20]; 6897 6898 u8 reserved_1[0x40]; 6899 }; 6900 6901 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6902 u8 opcode[0x10]; 6903 u8 reserved_0[0x10]; 6904 6905 u8 reserved_1[0x10]; 6906 u8 op_mod[0x10]; 6907 6908 u8 reserved_2[0x10]; 6909 u8 flow_counter_id[0x10]; 6910 6911 u8 reserved_3[0x20]; 6912 }; 6913 6914 struct mlx5_ifc_deactivate_tracer_out_bits { 6915 u8 status[0x8]; 6916 u8 reserved_0[0x18]; 6917 6918 u8 syndrome[0x20]; 6919 6920 u8 reserved_1[0x40]; 6921 }; 6922 6923 struct mlx5_ifc_deactivate_tracer_in_bits { 6924 u8 opcode[0x10]; 6925 u8 reserved_0[0x10]; 6926 6927 u8 reserved_1[0x10]; 6928 u8 op_mod[0x10]; 6929 6930 u8 mkey[0x20]; 6931 6932 u8 reserved_2[0x20]; 6933 }; 6934 6935 struct mlx5_ifc_create_xrc_srq_out_bits { 6936 u8 status[0x8]; 6937 u8 reserved_0[0x18]; 6938 6939 u8 syndrome[0x20]; 6940 6941 u8 reserved_1[0x8]; 6942 u8 xrc_srqn[0x18]; 6943 6944 u8 reserved_2[0x20]; 6945 }; 6946 6947 struct mlx5_ifc_create_xrc_srq_in_bits { 6948 u8 opcode[0x10]; 6949 u8 reserved_0[0x10]; 6950 6951 u8 reserved_1[0x10]; 6952 u8 op_mod[0x10]; 6953 6954 u8 reserved_2[0x40]; 6955 6956 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6957 6958 u8 reserved_3[0x600]; 6959 6960 u8 pas[0][0x40]; 6961 }; 6962 6963 struct mlx5_ifc_create_tis_out_bits { 6964 u8 status[0x8]; 6965 u8 reserved_0[0x18]; 6966 6967 u8 syndrome[0x20]; 6968 6969 u8 reserved_1[0x8]; 6970 u8 tisn[0x18]; 6971 6972 u8 reserved_2[0x20]; 6973 }; 6974 6975 struct mlx5_ifc_create_tis_in_bits { 6976 u8 opcode[0x10]; 6977 u8 reserved_0[0x10]; 6978 6979 u8 reserved_1[0x10]; 6980 u8 op_mod[0x10]; 6981 6982 u8 reserved_2[0xc0]; 6983 6984 struct mlx5_ifc_tisc_bits ctx; 6985 }; 6986 6987 struct mlx5_ifc_create_tir_out_bits { 6988 u8 status[0x8]; 6989 u8 reserved_0[0x18]; 6990 6991 u8 syndrome[0x20]; 6992 6993 u8 reserved_1[0x8]; 6994 u8 tirn[0x18]; 6995 6996 u8 reserved_2[0x20]; 6997 }; 6998 6999 struct mlx5_ifc_create_tir_in_bits { 7000 u8 opcode[0x10]; 7001 u8 reserved_0[0x10]; 7002 7003 u8 reserved_1[0x10]; 7004 u8 op_mod[0x10]; 7005 7006 u8 reserved_2[0xc0]; 7007 7008 struct mlx5_ifc_tirc_bits tir_context; 7009 }; 7010 7011 struct mlx5_ifc_create_srq_out_bits { 7012 u8 status[0x8]; 7013 u8 reserved_0[0x18]; 7014 7015 u8 syndrome[0x20]; 7016 7017 u8 reserved_1[0x8]; 7018 u8 srqn[0x18]; 7019 7020 u8 reserved_2[0x20]; 7021 }; 7022 7023 struct mlx5_ifc_create_srq_in_bits { 7024 u8 opcode[0x10]; 7025 u8 reserved_0[0x10]; 7026 7027 u8 reserved_1[0x10]; 7028 u8 op_mod[0x10]; 7029 7030 u8 reserved_2[0x40]; 7031 7032 struct mlx5_ifc_srqc_bits srq_context_entry; 7033 7034 u8 reserved_3[0x600]; 7035 7036 u8 pas[0][0x40]; 7037 }; 7038 7039 struct mlx5_ifc_create_sq_out_bits { 7040 u8 status[0x8]; 7041 u8 reserved_0[0x18]; 7042 7043 u8 syndrome[0x20]; 7044 7045 u8 reserved_1[0x8]; 7046 u8 sqn[0x18]; 7047 7048 u8 reserved_2[0x20]; 7049 }; 7050 7051 struct mlx5_ifc_create_sq_in_bits { 7052 u8 opcode[0x10]; 7053 u8 uid[0x10]; 7054 7055 u8 reserved_1[0x10]; 7056 u8 op_mod[0x10]; 7057 7058 u8 reserved_2[0xc0]; 7059 7060 struct mlx5_ifc_sqc_bits ctx; 7061 }; 7062 7063 struct mlx5_ifc_create_scheduling_element_out_bits { 7064 u8 status[0x8]; 7065 u8 reserved_at_8[0x18]; 7066 7067 u8 syndrome[0x20]; 7068 7069 u8 reserved_at_40[0x40]; 7070 7071 u8 scheduling_element_id[0x20]; 7072 7073 u8 reserved_at_a0[0x160]; 7074 }; 7075 7076 enum { 7077 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 7078 }; 7079 7080 struct mlx5_ifc_create_scheduling_element_in_bits { 7081 u8 opcode[0x10]; 7082 u8 reserved_at_10[0x10]; 7083 7084 u8 reserved_at_20[0x10]; 7085 u8 op_mod[0x10]; 7086 7087 u8 scheduling_hierarchy[0x8]; 7088 u8 reserved_at_48[0x18]; 7089 7090 u8 reserved_at_60[0xa0]; 7091 7092 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7093 7094 u8 reserved_at_300[0x100]; 7095 }; 7096 7097 struct mlx5_ifc_create_rqt_out_bits { 7098 u8 status[0x8]; 7099 u8 reserved_0[0x18]; 7100 7101 u8 syndrome[0x20]; 7102 7103 u8 reserved_1[0x8]; 7104 u8 rqtn[0x18]; 7105 7106 u8 reserved_2[0x20]; 7107 }; 7108 7109 struct mlx5_ifc_create_rqt_in_bits { 7110 u8 opcode[0x10]; 7111 u8 reserved_0[0x10]; 7112 7113 u8 reserved_1[0x10]; 7114 u8 op_mod[0x10]; 7115 7116 u8 reserved_2[0xc0]; 7117 7118 struct mlx5_ifc_rqtc_bits rqt_context; 7119 }; 7120 7121 struct mlx5_ifc_create_rq_out_bits { 7122 u8 status[0x8]; 7123 u8 reserved_0[0x18]; 7124 7125 u8 syndrome[0x20]; 7126 7127 u8 reserved_1[0x8]; 7128 u8 rqn[0x18]; 7129 7130 u8 reserved_2[0x20]; 7131 }; 7132 7133 struct mlx5_ifc_create_rq_in_bits { 7134 u8 opcode[0x10]; 7135 u8 uid[0x10]; 7136 7137 u8 reserved_1[0x10]; 7138 u8 op_mod[0x10]; 7139 7140 u8 reserved_2[0xc0]; 7141 7142 struct mlx5_ifc_rqc_bits ctx; 7143 }; 7144 7145 struct mlx5_ifc_create_rmp_out_bits { 7146 u8 status[0x8]; 7147 u8 reserved_0[0x18]; 7148 7149 u8 syndrome[0x20]; 7150 7151 u8 reserved_1[0x8]; 7152 u8 rmpn[0x18]; 7153 7154 u8 reserved_2[0x20]; 7155 }; 7156 7157 struct mlx5_ifc_create_rmp_in_bits { 7158 u8 opcode[0x10]; 7159 u8 reserved_0[0x10]; 7160 7161 u8 reserved_1[0x10]; 7162 u8 op_mod[0x10]; 7163 7164 u8 reserved_2[0xc0]; 7165 7166 struct mlx5_ifc_rmpc_bits ctx; 7167 }; 7168 7169 struct mlx5_ifc_create_qp_out_bits { 7170 u8 status[0x8]; 7171 u8 reserved_0[0x18]; 7172 7173 u8 syndrome[0x20]; 7174 7175 u8 reserved_1[0x8]; 7176 u8 qpn[0x18]; 7177 7178 u8 reserved_2[0x20]; 7179 }; 7180 7181 struct mlx5_ifc_create_qp_in_bits { 7182 u8 opcode[0x10]; 7183 u8 uid[0x10]; 7184 7185 u8 reserved_1[0x10]; 7186 u8 op_mod[0x10]; 7187 7188 u8 reserved_2[0x8]; 7189 u8 input_qpn[0x18]; 7190 7191 u8 reserved_3[0x20]; 7192 7193 u8 opt_param_mask[0x20]; 7194 7195 u8 reserved_4[0x20]; 7196 7197 struct mlx5_ifc_qpc_bits qpc; 7198 7199 u8 reserved_5[0x80]; 7200 7201 u8 pas[0][0x40]; 7202 }; 7203 7204 struct mlx5_ifc_create_qos_para_vport_out_bits { 7205 u8 status[0x8]; 7206 u8 reserved_at_8[0x18]; 7207 7208 u8 syndrome[0x20]; 7209 7210 u8 reserved_at_40[0x20]; 7211 7212 u8 reserved_at_60[0x10]; 7213 u8 qos_para_vport_number[0x10]; 7214 7215 u8 reserved_at_80[0x180]; 7216 }; 7217 7218 struct mlx5_ifc_create_qos_para_vport_in_bits { 7219 u8 opcode[0x10]; 7220 u8 reserved_at_10[0x10]; 7221 7222 u8 reserved_at_20[0x10]; 7223 u8 op_mod[0x10]; 7224 7225 u8 reserved_at_40[0x1c0]; 7226 }; 7227 7228 struct mlx5_ifc_create_psv_out_bits { 7229 u8 status[0x8]; 7230 u8 reserved_0[0x18]; 7231 7232 u8 syndrome[0x20]; 7233 7234 u8 reserved_1[0x40]; 7235 7236 u8 reserved_2[0x8]; 7237 u8 psv0_index[0x18]; 7238 7239 u8 reserved_3[0x8]; 7240 u8 psv1_index[0x18]; 7241 7242 u8 reserved_4[0x8]; 7243 u8 psv2_index[0x18]; 7244 7245 u8 reserved_5[0x8]; 7246 u8 psv3_index[0x18]; 7247 }; 7248 7249 struct mlx5_ifc_create_psv_in_bits { 7250 u8 opcode[0x10]; 7251 u8 reserved_0[0x10]; 7252 7253 u8 reserved_1[0x10]; 7254 u8 op_mod[0x10]; 7255 7256 u8 num_psv[0x4]; 7257 u8 reserved_2[0x4]; 7258 u8 pd[0x18]; 7259 7260 u8 reserved_3[0x20]; 7261 }; 7262 7263 struct mlx5_ifc_create_mkey_out_bits { 7264 u8 status[0x8]; 7265 u8 reserved_0[0x18]; 7266 7267 u8 syndrome[0x20]; 7268 7269 u8 reserved_1[0x8]; 7270 u8 mkey_index[0x18]; 7271 7272 u8 reserved_2[0x20]; 7273 }; 7274 7275 struct mlx5_ifc_create_mkey_in_bits { 7276 u8 opcode[0x10]; 7277 u8 reserved_0[0x10]; 7278 7279 u8 reserved_1[0x10]; 7280 u8 op_mod[0x10]; 7281 7282 u8 reserved_2[0x20]; 7283 7284 u8 pg_access[0x1]; 7285 u8 reserved_3[0x1f]; 7286 7287 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7288 7289 u8 reserved_4[0x80]; 7290 7291 u8 translations_octword_actual_size[0x20]; 7292 7293 u8 reserved_5[0x560]; 7294 7295 u8 klm_pas_mtt[0][0x20]; 7296 }; 7297 7298 struct mlx5_ifc_create_flow_table_out_bits { 7299 u8 status[0x8]; 7300 u8 reserved_0[0x18]; 7301 7302 u8 syndrome[0x20]; 7303 7304 u8 reserved_1[0x8]; 7305 u8 table_id[0x18]; 7306 7307 u8 reserved_2[0x20]; 7308 }; 7309 7310 struct mlx5_ifc_create_flow_table_in_bits { 7311 u8 opcode[0x10]; 7312 u8 reserved_at_10[0x10]; 7313 7314 u8 reserved_at_20[0x10]; 7315 u8 op_mod[0x10]; 7316 7317 u8 other_vport[0x1]; 7318 u8 reserved_at_41[0xf]; 7319 u8 vport_number[0x10]; 7320 7321 u8 reserved_at_60[0x20]; 7322 7323 u8 table_type[0x8]; 7324 u8 reserved_at_88[0x18]; 7325 7326 u8 reserved_at_a0[0x20]; 7327 7328 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7329 }; 7330 7331 struct mlx5_ifc_create_flow_group_out_bits { 7332 u8 status[0x8]; 7333 u8 reserved_0[0x18]; 7334 7335 u8 syndrome[0x20]; 7336 7337 u8 reserved_1[0x8]; 7338 u8 group_id[0x18]; 7339 7340 u8 reserved_2[0x20]; 7341 }; 7342 7343 enum { 7344 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7345 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7346 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7347 }; 7348 7349 struct mlx5_ifc_create_flow_group_in_bits { 7350 u8 opcode[0x10]; 7351 u8 reserved_0[0x10]; 7352 7353 u8 reserved_1[0x10]; 7354 u8 op_mod[0x10]; 7355 7356 u8 other_vport[0x1]; 7357 u8 reserved_2[0xf]; 7358 u8 vport_number[0x10]; 7359 7360 u8 reserved_3[0x20]; 7361 7362 u8 table_type[0x8]; 7363 u8 reserved_4[0x18]; 7364 7365 u8 reserved_5[0x8]; 7366 u8 table_id[0x18]; 7367 7368 u8 reserved_6[0x20]; 7369 7370 u8 start_flow_index[0x20]; 7371 7372 u8 reserved_7[0x20]; 7373 7374 u8 end_flow_index[0x20]; 7375 7376 u8 reserved_8[0xa0]; 7377 7378 u8 reserved_9[0x18]; 7379 u8 match_criteria_enable[0x8]; 7380 7381 struct mlx5_ifc_fte_match_param_bits match_criteria; 7382 7383 u8 reserved_10[0xe00]; 7384 }; 7385 7386 struct mlx5_ifc_create_encryption_key_out_bits { 7387 u8 status[0x8]; 7388 u8 reserved_at_8[0x18]; 7389 7390 u8 syndrome[0x20]; 7391 7392 u8 obj_id[0x20]; 7393 7394 u8 reserved_at_60[0x20]; 7395 }; 7396 7397 struct mlx5_ifc_create_encryption_key_in_bits { 7398 u8 opcode[0x10]; 7399 u8 reserved_at_10[0x10]; 7400 7401 u8 reserved_at_20[0x10]; 7402 u8 obj_type[0x10]; 7403 7404 u8 reserved_at_40[0x40]; 7405 7406 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 7407 }; 7408 7409 struct mlx5_ifc_create_eq_out_bits { 7410 u8 status[0x8]; 7411 u8 reserved_0[0x18]; 7412 7413 u8 syndrome[0x20]; 7414 7415 u8 reserved_1[0x18]; 7416 u8 eq_number[0x8]; 7417 7418 u8 reserved_2[0x20]; 7419 }; 7420 7421 struct mlx5_ifc_create_eq_in_bits { 7422 u8 opcode[0x10]; 7423 u8 reserved_0[0x10]; 7424 7425 u8 reserved_1[0x10]; 7426 u8 op_mod[0x10]; 7427 7428 u8 reserved_2[0x40]; 7429 7430 struct mlx5_ifc_eqc_bits eq_context_entry; 7431 7432 u8 reserved_3[0x40]; 7433 7434 u8 event_bitmask[0x40]; 7435 7436 u8 reserved_4[0x580]; 7437 7438 u8 pas[0][0x40]; 7439 }; 7440 7441 struct mlx5_ifc_create_dct_out_bits { 7442 u8 status[0x8]; 7443 u8 reserved_0[0x18]; 7444 7445 u8 syndrome[0x20]; 7446 7447 u8 reserved_1[0x8]; 7448 u8 dctn[0x18]; 7449 7450 u8 reserved_2[0x20]; 7451 }; 7452 7453 struct mlx5_ifc_create_dct_in_bits { 7454 u8 opcode[0x10]; 7455 u8 uid[0x10]; 7456 7457 u8 reserved_1[0x10]; 7458 u8 op_mod[0x10]; 7459 7460 u8 reserved_2[0x40]; 7461 7462 struct mlx5_ifc_dctc_bits dct_context_entry; 7463 7464 u8 reserved_3[0x180]; 7465 }; 7466 7467 struct mlx5_ifc_create_cq_out_bits { 7468 u8 status[0x8]; 7469 u8 reserved_0[0x18]; 7470 7471 u8 syndrome[0x20]; 7472 7473 u8 reserved_1[0x8]; 7474 u8 cqn[0x18]; 7475 7476 u8 reserved_2[0x20]; 7477 }; 7478 7479 struct mlx5_ifc_create_cq_in_bits { 7480 u8 opcode[0x10]; 7481 u8 reserved_0[0x10]; 7482 7483 u8 reserved_1[0x10]; 7484 u8 op_mod[0x10]; 7485 7486 u8 reserved_2[0x40]; 7487 7488 struct mlx5_ifc_cqc_bits cq_context; 7489 7490 u8 reserved_3[0x600]; 7491 7492 u8 pas[0][0x40]; 7493 }; 7494 7495 struct mlx5_ifc_config_int_moderation_out_bits { 7496 u8 status[0x8]; 7497 u8 reserved_0[0x18]; 7498 7499 u8 syndrome[0x20]; 7500 7501 u8 reserved_1[0x4]; 7502 u8 min_delay[0xc]; 7503 u8 int_vector[0x10]; 7504 7505 u8 reserved_2[0x20]; 7506 }; 7507 7508 enum { 7509 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7510 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7511 }; 7512 7513 struct mlx5_ifc_config_int_moderation_in_bits { 7514 u8 opcode[0x10]; 7515 u8 reserved_0[0x10]; 7516 7517 u8 reserved_1[0x10]; 7518 u8 op_mod[0x10]; 7519 7520 u8 reserved_2[0x4]; 7521 u8 min_delay[0xc]; 7522 u8 int_vector[0x10]; 7523 7524 u8 reserved_3[0x20]; 7525 }; 7526 7527 struct mlx5_ifc_attach_to_mcg_out_bits { 7528 u8 status[0x8]; 7529 u8 reserved_0[0x18]; 7530 7531 u8 syndrome[0x20]; 7532 7533 u8 reserved_1[0x40]; 7534 }; 7535 7536 struct mlx5_ifc_attach_to_mcg_in_bits { 7537 u8 opcode[0x10]; 7538 u8 reserved_0[0x10]; 7539 7540 u8 reserved_1[0x10]; 7541 u8 op_mod[0x10]; 7542 7543 u8 reserved_2[0x8]; 7544 u8 qpn[0x18]; 7545 7546 u8 reserved_3[0x20]; 7547 7548 u8 multicast_gid[16][0x8]; 7549 }; 7550 7551 struct mlx5_ifc_arm_xrc_srq_out_bits { 7552 u8 status[0x8]; 7553 u8 reserved_0[0x18]; 7554 7555 u8 syndrome[0x20]; 7556 7557 u8 reserved_1[0x40]; 7558 }; 7559 7560 enum { 7561 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7562 }; 7563 7564 struct mlx5_ifc_arm_xrc_srq_in_bits { 7565 u8 opcode[0x10]; 7566 u8 reserved_0[0x10]; 7567 7568 u8 reserved_1[0x10]; 7569 u8 op_mod[0x10]; 7570 7571 u8 reserved_2[0x8]; 7572 u8 xrc_srqn[0x18]; 7573 7574 u8 reserved_3[0x10]; 7575 u8 lwm[0x10]; 7576 }; 7577 7578 struct mlx5_ifc_arm_rq_out_bits { 7579 u8 status[0x8]; 7580 u8 reserved_0[0x18]; 7581 7582 u8 syndrome[0x20]; 7583 7584 u8 reserved_1[0x40]; 7585 }; 7586 7587 enum { 7588 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7589 }; 7590 7591 struct mlx5_ifc_arm_rq_in_bits { 7592 u8 opcode[0x10]; 7593 u8 reserved_0[0x10]; 7594 7595 u8 reserved_1[0x10]; 7596 u8 op_mod[0x10]; 7597 7598 u8 reserved_2[0x8]; 7599 u8 srq_number[0x18]; 7600 7601 u8 reserved_3[0x10]; 7602 u8 lwm[0x10]; 7603 }; 7604 7605 struct mlx5_ifc_arm_dct_out_bits { 7606 u8 status[0x8]; 7607 u8 reserved_0[0x18]; 7608 7609 u8 syndrome[0x20]; 7610 7611 u8 reserved_1[0x40]; 7612 }; 7613 7614 struct mlx5_ifc_arm_dct_in_bits { 7615 u8 opcode[0x10]; 7616 u8 reserved_0[0x10]; 7617 7618 u8 reserved_1[0x10]; 7619 u8 op_mod[0x10]; 7620 7621 u8 reserved_2[0x8]; 7622 u8 dctn[0x18]; 7623 7624 u8 reserved_3[0x20]; 7625 }; 7626 7627 struct mlx5_ifc_alloc_xrcd_out_bits { 7628 u8 status[0x8]; 7629 u8 reserved_0[0x18]; 7630 7631 u8 syndrome[0x20]; 7632 7633 u8 reserved_1[0x8]; 7634 u8 xrcd[0x18]; 7635 7636 u8 reserved_2[0x20]; 7637 }; 7638 7639 struct mlx5_ifc_alloc_xrcd_in_bits { 7640 u8 opcode[0x10]; 7641 u8 reserved_0[0x10]; 7642 7643 u8 reserved_1[0x10]; 7644 u8 op_mod[0x10]; 7645 7646 u8 reserved_2[0x40]; 7647 }; 7648 7649 struct mlx5_ifc_alloc_uar_out_bits { 7650 u8 status[0x8]; 7651 u8 reserved_0[0x18]; 7652 7653 u8 syndrome[0x20]; 7654 7655 u8 reserved_1[0x8]; 7656 u8 uar[0x18]; 7657 7658 u8 reserved_2[0x20]; 7659 }; 7660 7661 struct mlx5_ifc_alloc_uar_in_bits { 7662 u8 opcode[0x10]; 7663 u8 reserved_0[0x10]; 7664 7665 u8 reserved_1[0x10]; 7666 u8 op_mod[0x10]; 7667 7668 u8 reserved_2[0x40]; 7669 }; 7670 7671 struct mlx5_ifc_alloc_transport_domain_out_bits { 7672 u8 status[0x8]; 7673 u8 reserved_0[0x18]; 7674 7675 u8 syndrome[0x20]; 7676 7677 u8 reserved_1[0x8]; 7678 u8 transport_domain[0x18]; 7679 7680 u8 reserved_2[0x20]; 7681 }; 7682 7683 struct mlx5_ifc_alloc_transport_domain_in_bits { 7684 u8 opcode[0x10]; 7685 u8 reserved_0[0x10]; 7686 7687 u8 reserved_1[0x10]; 7688 u8 op_mod[0x10]; 7689 7690 u8 reserved_2[0x40]; 7691 }; 7692 7693 struct mlx5_ifc_alloc_q_counter_out_bits { 7694 u8 status[0x8]; 7695 u8 reserved_0[0x18]; 7696 7697 u8 syndrome[0x20]; 7698 7699 u8 reserved_1[0x18]; 7700 u8 counter_set_id[0x8]; 7701 7702 u8 reserved_2[0x20]; 7703 }; 7704 7705 struct mlx5_ifc_alloc_q_counter_in_bits { 7706 u8 opcode[0x10]; 7707 u8 reserved_0[0x10]; 7708 7709 u8 reserved_1[0x10]; 7710 u8 op_mod[0x10]; 7711 7712 u8 reserved_2[0x40]; 7713 }; 7714 7715 struct mlx5_ifc_alloc_pd_out_bits { 7716 u8 status[0x8]; 7717 u8 reserved_0[0x18]; 7718 7719 u8 syndrome[0x20]; 7720 7721 u8 reserved_1[0x8]; 7722 u8 pd[0x18]; 7723 7724 u8 reserved_2[0x20]; 7725 }; 7726 7727 struct mlx5_ifc_alloc_pd_in_bits { 7728 u8 opcode[0x10]; 7729 u8 reserved_0[0x10]; 7730 7731 u8 reserved_1[0x10]; 7732 u8 op_mod[0x10]; 7733 7734 u8 reserved_2[0x40]; 7735 }; 7736 7737 struct mlx5_ifc_alloc_flow_counter_out_bits { 7738 u8 status[0x8]; 7739 u8 reserved_0[0x18]; 7740 7741 u8 syndrome[0x20]; 7742 7743 u8 reserved_1[0x10]; 7744 u8 flow_counter_id[0x10]; 7745 7746 u8 reserved_2[0x20]; 7747 }; 7748 7749 struct mlx5_ifc_alloc_flow_counter_in_bits { 7750 u8 opcode[0x10]; 7751 u8 reserved_0[0x10]; 7752 7753 u8 reserved_1[0x10]; 7754 u8 op_mod[0x10]; 7755 7756 u8 reserved_2[0x40]; 7757 }; 7758 7759 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7760 u8 status[0x8]; 7761 u8 reserved_0[0x18]; 7762 7763 u8 syndrome[0x20]; 7764 7765 u8 reserved_1[0x40]; 7766 }; 7767 7768 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7769 u8 opcode[0x10]; 7770 u8 reserved_0[0x10]; 7771 7772 u8 reserved_1[0x10]; 7773 u8 op_mod[0x10]; 7774 7775 u8 reserved_2[0x20]; 7776 7777 u8 reserved_3[0x10]; 7778 u8 vxlan_udp_port[0x10]; 7779 }; 7780 7781 struct mlx5_ifc_activate_tracer_out_bits { 7782 u8 status[0x8]; 7783 u8 reserved_0[0x18]; 7784 7785 u8 syndrome[0x20]; 7786 7787 u8 reserved_1[0x40]; 7788 }; 7789 7790 struct mlx5_ifc_activate_tracer_in_bits { 7791 u8 opcode[0x10]; 7792 u8 reserved_0[0x10]; 7793 7794 u8 reserved_1[0x10]; 7795 u8 op_mod[0x10]; 7796 7797 u8 mkey[0x20]; 7798 7799 u8 reserved_2[0x20]; 7800 }; 7801 7802 struct mlx5_ifc_set_rate_limit_out_bits { 7803 u8 status[0x8]; 7804 u8 reserved_at_8[0x18]; 7805 7806 u8 syndrome[0x20]; 7807 7808 u8 reserved_at_40[0x40]; 7809 }; 7810 7811 struct mlx5_ifc_set_rate_limit_in_bits { 7812 u8 opcode[0x10]; 7813 u8 reserved_at_10[0x10]; 7814 7815 u8 reserved_at_20[0x10]; 7816 u8 op_mod[0x10]; 7817 7818 u8 reserved_at_40[0x10]; 7819 u8 rate_limit_index[0x10]; 7820 7821 u8 reserved_at_60[0x20]; 7822 7823 u8 rate_limit[0x20]; 7824 7825 u8 burst_upper_bound[0x20]; 7826 7827 u8 reserved_at_c0[0x10]; 7828 u8 typical_packet_size[0x10]; 7829 7830 u8 reserved_at_e0[0x120]; 7831 }; 7832 7833 struct mlx5_ifc_access_register_out_bits { 7834 u8 status[0x8]; 7835 u8 reserved_0[0x18]; 7836 7837 u8 syndrome[0x20]; 7838 7839 u8 reserved_1[0x40]; 7840 7841 u8 register_data[0][0x20]; 7842 }; 7843 7844 enum { 7845 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7846 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7847 }; 7848 7849 struct mlx5_ifc_access_register_in_bits { 7850 u8 opcode[0x10]; 7851 u8 reserved_0[0x10]; 7852 7853 u8 reserved_1[0x10]; 7854 u8 op_mod[0x10]; 7855 7856 u8 reserved_2[0x10]; 7857 u8 register_id[0x10]; 7858 7859 u8 argument[0x20]; 7860 7861 u8 register_data[0][0x20]; 7862 }; 7863 7864 struct mlx5_ifc_sltp_reg_bits { 7865 u8 status[0x4]; 7866 u8 version[0x4]; 7867 u8 local_port[0x8]; 7868 u8 pnat[0x2]; 7869 u8 reserved_0[0x2]; 7870 u8 lane[0x4]; 7871 u8 reserved_1[0x8]; 7872 7873 u8 reserved_2[0x20]; 7874 7875 u8 reserved_3[0x7]; 7876 u8 polarity[0x1]; 7877 u8 ob_tap0[0x8]; 7878 u8 ob_tap1[0x8]; 7879 u8 ob_tap2[0x8]; 7880 7881 u8 reserved_4[0xc]; 7882 u8 ob_preemp_mode[0x4]; 7883 u8 ob_reg[0x8]; 7884 u8 ob_bias[0x8]; 7885 7886 u8 reserved_5[0x20]; 7887 }; 7888 7889 struct mlx5_ifc_slrp_reg_bits { 7890 u8 status[0x4]; 7891 u8 version[0x4]; 7892 u8 local_port[0x8]; 7893 u8 pnat[0x2]; 7894 u8 reserved_0[0x2]; 7895 u8 lane[0x4]; 7896 u8 reserved_1[0x8]; 7897 7898 u8 ib_sel[0x2]; 7899 u8 reserved_2[0x11]; 7900 u8 dp_sel[0x1]; 7901 u8 dp90sel[0x4]; 7902 u8 mix90phase[0x8]; 7903 7904 u8 ffe_tap0[0x8]; 7905 u8 ffe_tap1[0x8]; 7906 u8 ffe_tap2[0x8]; 7907 u8 ffe_tap3[0x8]; 7908 7909 u8 ffe_tap4[0x8]; 7910 u8 ffe_tap5[0x8]; 7911 u8 ffe_tap6[0x8]; 7912 u8 ffe_tap7[0x8]; 7913 7914 u8 ffe_tap8[0x8]; 7915 u8 mixerbias_tap_amp[0x8]; 7916 u8 reserved_3[0x7]; 7917 u8 ffe_tap_en[0x9]; 7918 7919 u8 ffe_tap_offset0[0x8]; 7920 u8 ffe_tap_offset1[0x8]; 7921 u8 slicer_offset0[0x10]; 7922 7923 u8 mixer_offset0[0x10]; 7924 u8 mixer_offset1[0x10]; 7925 7926 u8 mixerbgn_inp[0x8]; 7927 u8 mixerbgn_inn[0x8]; 7928 u8 mixerbgn_refp[0x8]; 7929 u8 mixerbgn_refn[0x8]; 7930 7931 u8 sel_slicer_lctrl_h[0x1]; 7932 u8 sel_slicer_lctrl_l[0x1]; 7933 u8 reserved_4[0x1]; 7934 u8 ref_mixer_vreg[0x5]; 7935 u8 slicer_gctrl[0x8]; 7936 u8 lctrl_input[0x8]; 7937 u8 mixer_offset_cm1[0x8]; 7938 7939 u8 common_mode[0x6]; 7940 u8 reserved_5[0x1]; 7941 u8 mixer_offset_cm0[0x9]; 7942 u8 reserved_6[0x7]; 7943 u8 slicer_offset_cm[0x9]; 7944 }; 7945 7946 struct mlx5_ifc_slrg_reg_bits { 7947 u8 status[0x4]; 7948 u8 version[0x4]; 7949 u8 local_port[0x8]; 7950 u8 pnat[0x2]; 7951 u8 reserved_0[0x2]; 7952 u8 lane[0x4]; 7953 u8 reserved_1[0x8]; 7954 7955 u8 time_to_link_up[0x10]; 7956 u8 reserved_2[0xc]; 7957 u8 grade_lane_speed[0x4]; 7958 7959 u8 grade_version[0x8]; 7960 u8 grade[0x18]; 7961 7962 u8 reserved_3[0x4]; 7963 u8 height_grade_type[0x4]; 7964 u8 height_grade[0x18]; 7965 7966 u8 height_dz[0x10]; 7967 u8 height_dv[0x10]; 7968 7969 u8 reserved_4[0x10]; 7970 u8 height_sigma[0x10]; 7971 7972 u8 reserved_5[0x20]; 7973 7974 u8 reserved_6[0x4]; 7975 u8 phase_grade_type[0x4]; 7976 u8 phase_grade[0x18]; 7977 7978 u8 reserved_7[0x8]; 7979 u8 phase_eo_pos[0x8]; 7980 u8 reserved_8[0x8]; 7981 u8 phase_eo_neg[0x8]; 7982 7983 u8 ffe_set_tested[0x10]; 7984 u8 test_errors_per_lane[0x10]; 7985 }; 7986 7987 struct mlx5_ifc_pvlc_reg_bits { 7988 u8 reserved_0[0x8]; 7989 u8 local_port[0x8]; 7990 u8 reserved_1[0x10]; 7991 7992 u8 reserved_2[0x1c]; 7993 u8 vl_hw_cap[0x4]; 7994 7995 u8 reserved_3[0x1c]; 7996 u8 vl_admin[0x4]; 7997 7998 u8 reserved_4[0x1c]; 7999 u8 vl_operational[0x4]; 8000 }; 8001 8002 struct mlx5_ifc_pude_reg_bits { 8003 u8 swid[0x8]; 8004 u8 local_port[0x8]; 8005 u8 reserved_0[0x4]; 8006 u8 admin_status[0x4]; 8007 u8 reserved_1[0x4]; 8008 u8 oper_status[0x4]; 8009 8010 u8 reserved_2[0x60]; 8011 }; 8012 8013 enum { 8014 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 8015 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 8016 }; 8017 8018 struct mlx5_ifc_ptys_reg_bits { 8019 u8 reserved_0[0x1]; 8020 u8 an_disable_admin[0x1]; 8021 u8 an_disable_cap[0x1]; 8022 u8 reserved_1[0x4]; 8023 u8 force_tx_aba_param[0x1]; 8024 u8 local_port[0x8]; 8025 u8 reserved_2[0xd]; 8026 u8 proto_mask[0x3]; 8027 8028 u8 an_status[0x4]; 8029 u8 reserved_3[0xc]; 8030 u8 data_rate_oper[0x10]; 8031 8032 u8 ext_eth_proto_capability[0x20]; 8033 8034 u8 eth_proto_capability[0x20]; 8035 8036 u8 ib_link_width_capability[0x10]; 8037 u8 ib_proto_capability[0x10]; 8038 8039 u8 ext_eth_proto_admin[0x20]; 8040 8041 u8 eth_proto_admin[0x20]; 8042 8043 u8 ib_link_width_admin[0x10]; 8044 u8 ib_proto_admin[0x10]; 8045 8046 u8 ext_eth_proto_oper[0x20]; 8047 8048 u8 eth_proto_oper[0x20]; 8049 8050 u8 ib_link_width_oper[0x10]; 8051 u8 ib_proto_oper[0x10]; 8052 8053 u8 reserved_4[0x1c]; 8054 u8 connector_type[0x4]; 8055 8056 u8 eth_proto_lp_advertise[0x20]; 8057 8058 u8 reserved_5[0x60]; 8059 }; 8060 8061 struct mlx5_ifc_ptas_reg_bits { 8062 u8 reserved_0[0x20]; 8063 8064 u8 algorithm_options[0x10]; 8065 u8 reserved_1[0x4]; 8066 u8 repetitions_mode[0x4]; 8067 u8 num_of_repetitions[0x8]; 8068 8069 u8 grade_version[0x8]; 8070 u8 height_grade_type[0x4]; 8071 u8 phase_grade_type[0x4]; 8072 u8 height_grade_weight[0x8]; 8073 u8 phase_grade_weight[0x8]; 8074 8075 u8 gisim_measure_bits[0x10]; 8076 u8 adaptive_tap_measure_bits[0x10]; 8077 8078 u8 ber_bath_high_error_threshold[0x10]; 8079 u8 ber_bath_mid_error_threshold[0x10]; 8080 8081 u8 ber_bath_low_error_threshold[0x10]; 8082 u8 one_ratio_high_threshold[0x10]; 8083 8084 u8 one_ratio_high_mid_threshold[0x10]; 8085 u8 one_ratio_low_mid_threshold[0x10]; 8086 8087 u8 one_ratio_low_threshold[0x10]; 8088 u8 ndeo_error_threshold[0x10]; 8089 8090 u8 mixer_offset_step_size[0x10]; 8091 u8 reserved_2[0x8]; 8092 u8 mix90_phase_for_voltage_bath[0x8]; 8093 8094 u8 mixer_offset_start[0x10]; 8095 u8 mixer_offset_end[0x10]; 8096 8097 u8 reserved_3[0x15]; 8098 u8 ber_test_time[0xb]; 8099 }; 8100 8101 struct mlx5_ifc_pspa_reg_bits { 8102 u8 swid[0x8]; 8103 u8 local_port[0x8]; 8104 u8 sub_port[0x8]; 8105 u8 reserved_0[0x8]; 8106 8107 u8 reserved_1[0x20]; 8108 }; 8109 8110 struct mlx5_ifc_ppsc_reg_bits { 8111 u8 reserved_0[0x8]; 8112 u8 local_port[0x8]; 8113 u8 reserved_1[0x10]; 8114 8115 u8 reserved_2[0x60]; 8116 8117 u8 reserved_3[0x1c]; 8118 u8 wrps_admin[0x4]; 8119 8120 u8 reserved_4[0x1c]; 8121 u8 wrps_status[0x4]; 8122 8123 u8 up_th_vld[0x1]; 8124 u8 down_th_vld[0x1]; 8125 u8 reserved_5[0x6]; 8126 u8 up_threshold[0x8]; 8127 u8 reserved_6[0x8]; 8128 u8 down_threshold[0x8]; 8129 8130 u8 reserved_7[0x20]; 8131 8132 u8 reserved_8[0x1c]; 8133 u8 srps_admin[0x4]; 8134 8135 u8 reserved_9[0x60]; 8136 }; 8137 8138 struct mlx5_ifc_pplr_reg_bits { 8139 u8 reserved_0[0x8]; 8140 u8 local_port[0x8]; 8141 u8 reserved_1[0x10]; 8142 8143 u8 reserved_2[0x8]; 8144 u8 lb_cap[0x8]; 8145 u8 reserved_3[0x8]; 8146 u8 lb_en[0x8]; 8147 }; 8148 8149 struct mlx5_ifc_pplm_reg_bits { 8150 u8 reserved_at_0[0x8]; 8151 u8 local_port[0x8]; 8152 u8 reserved_at_10[0x10]; 8153 8154 u8 reserved_at_20[0x20]; 8155 8156 u8 port_profile_mode[0x8]; 8157 u8 static_port_profile[0x8]; 8158 u8 active_port_profile[0x8]; 8159 u8 reserved_at_58[0x8]; 8160 8161 u8 retransmission_active[0x8]; 8162 u8 fec_mode_active[0x18]; 8163 8164 u8 rs_fec_correction_bypass_cap[0x4]; 8165 u8 reserved_at_84[0x8]; 8166 u8 fec_override_cap_56g[0x4]; 8167 u8 fec_override_cap_100g[0x4]; 8168 u8 fec_override_cap_50g[0x4]; 8169 u8 fec_override_cap_25g[0x4]; 8170 u8 fec_override_cap_10g_40g[0x4]; 8171 8172 u8 rs_fec_correction_bypass_admin[0x4]; 8173 u8 reserved_at_a4[0x8]; 8174 u8 fec_override_admin_56g[0x4]; 8175 u8 fec_override_admin_100g[0x4]; 8176 u8 fec_override_admin_50g[0x4]; 8177 u8 fec_override_admin_25g[0x4]; 8178 u8 fec_override_admin_10g_40g[0x4]; 8179 8180 u8 fec_override_cap_400g_8x[0x10]; 8181 u8 fec_override_cap_200g_4x[0x10]; 8182 u8 fec_override_cap_100g_2x[0x10]; 8183 u8 fec_override_cap_50g_1x[0x10]; 8184 8185 u8 fec_override_admin_400g_8x[0x10]; 8186 u8 fec_override_admin_200g_4x[0x10]; 8187 u8 fec_override_admin_100g_2x[0x10]; 8188 u8 fec_override_admin_50g_1x[0x10]; 8189 8190 u8 reserved_at_140[0x140]; 8191 }; 8192 8193 struct mlx5_ifc_ppll_reg_bits { 8194 u8 num_pll_groups[0x8]; 8195 u8 pll_group[0x8]; 8196 u8 reserved_0[0x4]; 8197 u8 num_plls[0x4]; 8198 u8 reserved_1[0x8]; 8199 8200 u8 reserved_2[0x1f]; 8201 u8 ae[0x1]; 8202 8203 u8 pll_status[4][0x40]; 8204 }; 8205 8206 struct mlx5_ifc_ppad_reg_bits { 8207 u8 reserved_0[0x3]; 8208 u8 single_mac[0x1]; 8209 u8 reserved_1[0x4]; 8210 u8 local_port[0x8]; 8211 u8 mac_47_32[0x10]; 8212 8213 u8 mac_31_0[0x20]; 8214 8215 u8 reserved_2[0x40]; 8216 }; 8217 8218 struct mlx5_ifc_pmtu_reg_bits { 8219 u8 reserved_0[0x8]; 8220 u8 local_port[0x8]; 8221 u8 reserved_1[0x10]; 8222 8223 u8 max_mtu[0x10]; 8224 u8 reserved_2[0x10]; 8225 8226 u8 admin_mtu[0x10]; 8227 u8 reserved_3[0x10]; 8228 8229 u8 oper_mtu[0x10]; 8230 u8 reserved_4[0x10]; 8231 }; 8232 8233 struct mlx5_ifc_pmpr_reg_bits { 8234 u8 reserved_0[0x8]; 8235 u8 module[0x8]; 8236 u8 reserved_1[0x10]; 8237 8238 u8 reserved_2[0x18]; 8239 u8 attenuation_5g[0x8]; 8240 8241 u8 reserved_3[0x18]; 8242 u8 attenuation_7g[0x8]; 8243 8244 u8 reserved_4[0x18]; 8245 u8 attenuation_12g[0x8]; 8246 }; 8247 8248 struct mlx5_ifc_pmpe_reg_bits { 8249 u8 reserved_0[0x8]; 8250 u8 module[0x8]; 8251 u8 reserved_1[0xc]; 8252 u8 module_status[0x4]; 8253 8254 u8 reserved_2[0x14]; 8255 u8 error_type[0x4]; 8256 u8 reserved_3[0x8]; 8257 8258 u8 reserved_4[0x40]; 8259 }; 8260 8261 struct mlx5_ifc_pmpc_reg_bits { 8262 u8 module_state_updated[32][0x8]; 8263 }; 8264 8265 struct mlx5_ifc_pmlpn_reg_bits { 8266 u8 reserved_0[0x4]; 8267 u8 mlpn_status[0x4]; 8268 u8 local_port[0x8]; 8269 u8 reserved_1[0x10]; 8270 8271 u8 e[0x1]; 8272 u8 reserved_2[0x1f]; 8273 }; 8274 8275 struct mlx5_ifc_pmlp_reg_bits { 8276 u8 rxtx[0x1]; 8277 u8 reserved_0[0x7]; 8278 u8 local_port[0x8]; 8279 u8 reserved_1[0x8]; 8280 u8 width[0x8]; 8281 8282 u8 lane0_module_mapping[0x20]; 8283 8284 u8 lane1_module_mapping[0x20]; 8285 8286 u8 lane2_module_mapping[0x20]; 8287 8288 u8 lane3_module_mapping[0x20]; 8289 8290 u8 reserved_2[0x160]; 8291 }; 8292 8293 struct mlx5_ifc_pmaos_reg_bits { 8294 u8 reserved_0[0x8]; 8295 u8 module[0x8]; 8296 u8 reserved_1[0x4]; 8297 u8 admin_status[0x4]; 8298 u8 reserved_2[0x4]; 8299 u8 oper_status[0x4]; 8300 8301 u8 ase[0x1]; 8302 u8 ee[0x1]; 8303 u8 reserved_3[0x12]; 8304 u8 error_type[0x4]; 8305 u8 reserved_4[0x6]; 8306 u8 e[0x2]; 8307 8308 u8 reserved_5[0x40]; 8309 }; 8310 8311 struct mlx5_ifc_plpc_reg_bits { 8312 u8 reserved_0[0x4]; 8313 u8 profile_id[0xc]; 8314 u8 reserved_1[0x4]; 8315 u8 proto_mask[0x4]; 8316 u8 reserved_2[0x8]; 8317 8318 u8 reserved_3[0x10]; 8319 u8 lane_speed[0x10]; 8320 8321 u8 reserved_4[0x17]; 8322 u8 lpbf[0x1]; 8323 u8 fec_mode_policy[0x8]; 8324 8325 u8 retransmission_capability[0x8]; 8326 u8 fec_mode_capability[0x18]; 8327 8328 u8 retransmission_support_admin[0x8]; 8329 u8 fec_mode_support_admin[0x18]; 8330 8331 u8 retransmission_request_admin[0x8]; 8332 u8 fec_mode_request_admin[0x18]; 8333 8334 u8 reserved_5[0x80]; 8335 }; 8336 8337 struct mlx5_ifc_pll_status_data_bits { 8338 u8 reserved_0[0x1]; 8339 u8 lock_cal[0x1]; 8340 u8 lock_status[0x2]; 8341 u8 reserved_1[0x2]; 8342 u8 algo_f_ctrl[0xa]; 8343 u8 analog_algo_num_var[0x6]; 8344 u8 f_ctrl_measure[0xa]; 8345 8346 u8 reserved_2[0x2]; 8347 u8 analog_var[0x6]; 8348 u8 reserved_3[0x2]; 8349 u8 high_var[0x6]; 8350 u8 reserved_4[0x2]; 8351 u8 low_var[0x6]; 8352 u8 reserved_5[0x2]; 8353 u8 mid_val[0x6]; 8354 }; 8355 8356 struct mlx5_ifc_plib_reg_bits { 8357 u8 reserved_0[0x8]; 8358 u8 local_port[0x8]; 8359 u8 reserved_1[0x8]; 8360 u8 ib_port[0x8]; 8361 8362 u8 reserved_2[0x60]; 8363 }; 8364 8365 struct mlx5_ifc_plbf_reg_bits { 8366 u8 reserved_0[0x8]; 8367 u8 local_port[0x8]; 8368 u8 reserved_1[0xd]; 8369 u8 lbf_mode[0x3]; 8370 8371 u8 reserved_2[0x20]; 8372 }; 8373 8374 struct mlx5_ifc_pipg_reg_bits { 8375 u8 reserved_0[0x8]; 8376 u8 local_port[0x8]; 8377 u8 reserved_1[0x10]; 8378 8379 u8 dic[0x1]; 8380 u8 reserved_2[0x19]; 8381 u8 ipg[0x4]; 8382 u8 reserved_3[0x2]; 8383 }; 8384 8385 struct mlx5_ifc_pifr_reg_bits { 8386 u8 reserved_0[0x8]; 8387 u8 local_port[0x8]; 8388 u8 reserved_1[0x10]; 8389 8390 u8 reserved_2[0xe0]; 8391 8392 u8 port_filter[8][0x20]; 8393 8394 u8 port_filter_update_en[8][0x20]; 8395 }; 8396 8397 struct mlx5_ifc_phys_layer_cntrs_bits { 8398 u8 time_since_last_clear_high[0x20]; 8399 8400 u8 time_since_last_clear_low[0x20]; 8401 8402 u8 symbol_errors_high[0x20]; 8403 8404 u8 symbol_errors_low[0x20]; 8405 8406 u8 sync_headers_errors_high[0x20]; 8407 8408 u8 sync_headers_errors_low[0x20]; 8409 8410 u8 edpl_bip_errors_lane0_high[0x20]; 8411 8412 u8 edpl_bip_errors_lane0_low[0x20]; 8413 8414 u8 edpl_bip_errors_lane1_high[0x20]; 8415 8416 u8 edpl_bip_errors_lane1_low[0x20]; 8417 8418 u8 edpl_bip_errors_lane2_high[0x20]; 8419 8420 u8 edpl_bip_errors_lane2_low[0x20]; 8421 8422 u8 edpl_bip_errors_lane3_high[0x20]; 8423 8424 u8 edpl_bip_errors_lane3_low[0x20]; 8425 8426 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 8427 8428 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 8429 8430 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 8431 8432 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 8433 8434 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 8435 8436 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 8437 8438 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 8439 8440 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 8441 8442 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 8443 8444 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 8445 8446 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 8447 8448 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 8449 8450 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 8451 8452 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 8453 8454 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 8455 8456 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 8457 8458 u8 rs_fec_corrected_blocks_high[0x20]; 8459 8460 u8 rs_fec_corrected_blocks_low[0x20]; 8461 8462 u8 rs_fec_uncorrectable_blocks_high[0x20]; 8463 8464 u8 rs_fec_uncorrectable_blocks_low[0x20]; 8465 8466 u8 rs_fec_no_errors_blocks_high[0x20]; 8467 8468 u8 rs_fec_no_errors_blocks_low[0x20]; 8469 8470 u8 rs_fec_single_error_blocks_high[0x20]; 8471 8472 u8 rs_fec_single_error_blocks_low[0x20]; 8473 8474 u8 rs_fec_corrected_symbols_total_high[0x20]; 8475 8476 u8 rs_fec_corrected_symbols_total_low[0x20]; 8477 8478 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 8479 8480 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 8481 8482 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 8483 8484 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 8485 8486 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 8487 8488 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 8489 8490 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 8491 8492 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 8493 8494 u8 link_down_events[0x20]; 8495 8496 u8 successful_recovery_events[0x20]; 8497 8498 u8 reserved_0[0x180]; 8499 }; 8500 8501 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 8502 u8 symbol_error_counter[0x10]; 8503 8504 u8 link_error_recovery_counter[0x8]; 8505 8506 u8 link_downed_counter[0x8]; 8507 8508 u8 port_rcv_errors[0x10]; 8509 8510 u8 port_rcv_remote_physical_errors[0x10]; 8511 8512 u8 port_rcv_switch_relay_errors[0x10]; 8513 8514 u8 port_xmit_discards[0x10]; 8515 8516 u8 port_xmit_constraint_errors[0x8]; 8517 8518 u8 port_rcv_constraint_errors[0x8]; 8519 8520 u8 reserved_at_70[0x8]; 8521 8522 u8 link_overrun_errors[0x8]; 8523 8524 u8 reserved_at_80[0x10]; 8525 8526 u8 vl_15_dropped[0x10]; 8527 8528 u8 reserved_at_a0[0xa0]; 8529 }; 8530 8531 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 8532 u8 time_since_last_clear_high[0x20]; 8533 8534 u8 time_since_last_clear_low[0x20]; 8535 8536 u8 phy_received_bits_high[0x20]; 8537 8538 u8 phy_received_bits_low[0x20]; 8539 8540 u8 phy_symbol_errors_high[0x20]; 8541 8542 u8 phy_symbol_errors_low[0x20]; 8543 8544 u8 phy_corrected_bits_high[0x20]; 8545 8546 u8 phy_corrected_bits_low[0x20]; 8547 8548 u8 phy_corrected_bits_lane0_high[0x20]; 8549 8550 u8 phy_corrected_bits_lane0_low[0x20]; 8551 8552 u8 phy_corrected_bits_lane1_high[0x20]; 8553 8554 u8 phy_corrected_bits_lane1_low[0x20]; 8555 8556 u8 phy_corrected_bits_lane2_high[0x20]; 8557 8558 u8 phy_corrected_bits_lane2_low[0x20]; 8559 8560 u8 phy_corrected_bits_lane3_high[0x20]; 8561 8562 u8 phy_corrected_bits_lane3_low[0x20]; 8563 8564 u8 reserved_at_200[0x5c0]; 8565 }; 8566 8567 struct mlx5_ifc_infiniband_port_cntrs_bits { 8568 u8 symbol_error_counter[0x10]; 8569 u8 link_error_recovery_counter[0x8]; 8570 u8 link_downed_counter[0x8]; 8571 8572 u8 port_rcv_errors[0x10]; 8573 u8 port_rcv_remote_physical_errors[0x10]; 8574 8575 u8 port_rcv_switch_relay_errors[0x10]; 8576 u8 port_xmit_discards[0x10]; 8577 8578 u8 port_xmit_constraint_errors[0x8]; 8579 u8 port_rcv_constraint_errors[0x8]; 8580 u8 reserved_0[0x8]; 8581 u8 local_link_integrity_errors[0x4]; 8582 u8 excessive_buffer_overrun_errors[0x4]; 8583 8584 u8 reserved_1[0x10]; 8585 u8 vl_15_dropped[0x10]; 8586 8587 u8 port_xmit_data[0x20]; 8588 8589 u8 port_rcv_data[0x20]; 8590 8591 u8 port_xmit_pkts[0x20]; 8592 8593 u8 port_rcv_pkts[0x20]; 8594 8595 u8 port_xmit_wait[0x20]; 8596 8597 u8 reserved_2[0x680]; 8598 }; 8599 8600 struct mlx5_ifc_phrr_reg_bits { 8601 u8 clr[0x1]; 8602 u8 reserved_0[0x7]; 8603 u8 local_port[0x8]; 8604 u8 reserved_1[0x10]; 8605 8606 u8 hist_group[0x8]; 8607 u8 reserved_2[0x10]; 8608 u8 hist_id[0x8]; 8609 8610 u8 reserved_3[0x40]; 8611 8612 u8 time_since_last_clear_high[0x20]; 8613 8614 u8 time_since_last_clear_low[0x20]; 8615 8616 u8 bin[10][0x20]; 8617 }; 8618 8619 struct mlx5_ifc_phbr_for_prio_reg_bits { 8620 u8 reserved_0[0x18]; 8621 u8 prio[0x8]; 8622 }; 8623 8624 struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8625 u8 reserved_0[0x18]; 8626 u8 tclass[0x8]; 8627 }; 8628 8629 struct mlx5_ifc_phbr_binding_reg_bits { 8630 u8 opcode[0x4]; 8631 u8 reserved_0[0x4]; 8632 u8 local_port[0x8]; 8633 u8 pnat[0x2]; 8634 u8 reserved_1[0xe]; 8635 8636 u8 hist_group[0x8]; 8637 u8 reserved_2[0x10]; 8638 u8 hist_id[0x8]; 8639 8640 u8 reserved_3[0x10]; 8641 u8 hist_type[0x10]; 8642 8643 u8 hist_parameters[0x20]; 8644 8645 u8 hist_min_value[0x20]; 8646 8647 u8 hist_max_value[0x20]; 8648 8649 u8 sample_time[0x20]; 8650 }; 8651 8652 enum { 8653 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 8654 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 8655 }; 8656 8657 struct mlx5_ifc_pfcc_reg_bits { 8658 u8 dcbx_operation_type[0x2]; 8659 u8 cap_local_admin[0x1]; 8660 u8 cap_remote_admin[0x1]; 8661 u8 reserved_0[0x4]; 8662 u8 local_port[0x8]; 8663 u8 pnat[0x2]; 8664 u8 reserved_1[0xc]; 8665 u8 shl_cap[0x1]; 8666 u8 shl_opr[0x1]; 8667 8668 u8 ppan[0x4]; 8669 u8 reserved_2[0x4]; 8670 u8 prio_mask_tx[0x8]; 8671 u8 reserved_3[0x8]; 8672 u8 prio_mask_rx[0x8]; 8673 8674 u8 pptx[0x1]; 8675 u8 aptx[0x1]; 8676 u8 reserved_4[0x6]; 8677 u8 pfctx[0x8]; 8678 u8 reserved_5[0x8]; 8679 u8 cbftx[0x8]; 8680 8681 u8 pprx[0x1]; 8682 u8 aprx[0x1]; 8683 u8 reserved_6[0x6]; 8684 u8 pfcrx[0x8]; 8685 u8 reserved_7[0x8]; 8686 u8 cbfrx[0x8]; 8687 8688 u8 device_stall_minor_watermark[0x10]; 8689 u8 device_stall_critical_watermark[0x10]; 8690 8691 u8 reserved_8[0x60]; 8692 }; 8693 8694 struct mlx5_ifc_pelc_reg_bits { 8695 u8 op[0x4]; 8696 u8 reserved_0[0x4]; 8697 u8 local_port[0x8]; 8698 u8 reserved_1[0x10]; 8699 8700 u8 op_admin[0x8]; 8701 u8 op_capability[0x8]; 8702 u8 op_request[0x8]; 8703 u8 op_active[0x8]; 8704 8705 u8 admin[0x40]; 8706 8707 u8 capability[0x40]; 8708 8709 u8 request[0x40]; 8710 8711 u8 active[0x40]; 8712 8713 u8 reserved_2[0x80]; 8714 }; 8715 8716 struct mlx5_ifc_peir_reg_bits { 8717 u8 reserved_0[0x8]; 8718 u8 local_port[0x8]; 8719 u8 reserved_1[0x10]; 8720 8721 u8 reserved_2[0xc]; 8722 u8 error_count[0x4]; 8723 u8 reserved_3[0x10]; 8724 8725 u8 reserved_4[0xc]; 8726 u8 lane[0x4]; 8727 u8 reserved_5[0x8]; 8728 u8 error_type[0x8]; 8729 }; 8730 8731 struct mlx5_ifc_qcam_access_reg_cap_mask { 8732 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8733 u8 qpdpm[0x1]; 8734 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8735 u8 qdpm[0x1]; 8736 u8 qpts[0x1]; 8737 u8 qcap[0x1]; 8738 u8 qcam_access_reg_cap_mask_0[0x1]; 8739 }; 8740 8741 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8742 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8743 u8 qpts_trust_both[0x1]; 8744 }; 8745 8746 struct mlx5_ifc_qcam_reg_bits { 8747 u8 reserved_at_0[0x8]; 8748 u8 feature_group[0x8]; 8749 u8 reserved_at_10[0x8]; 8750 u8 access_reg_group[0x8]; 8751 u8 reserved_at_20[0x20]; 8752 8753 union { 8754 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8755 u8 reserved_at_0[0x80]; 8756 } qos_access_reg_cap_mask; 8757 8758 u8 reserved_at_c0[0x80]; 8759 8760 union { 8761 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8762 u8 reserved_at_0[0x80]; 8763 } qos_feature_cap_mask; 8764 8765 u8 reserved_at_1c0[0x80]; 8766 }; 8767 8768 struct mlx5_ifc_pcam_enhanced_features_bits { 8769 u8 reserved_at_0[0x6d]; 8770 u8 rx_icrc_encapsulated_counter[0x1]; 8771 u8 reserved_at_6e[0x4]; 8772 u8 ptys_extended_ethernet[0x1]; 8773 u8 reserved_at_73[0x3]; 8774 u8 pfcc_mask[0x1]; 8775 u8 reserved_at_77[0x3]; 8776 u8 per_lane_error_counters[0x1]; 8777 u8 rx_buffer_fullness_counters[0x1]; 8778 u8 ptys_connector_type[0x1]; 8779 u8 reserved_at_7d[0x1]; 8780 u8 ppcnt_discard_group[0x1]; 8781 u8 ppcnt_statistical_group[0x1]; 8782 }; 8783 8784 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8785 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8786 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8787 8788 u8 reserved_at_40[0xe]; 8789 u8 pddr[0x1]; 8790 u8 reserved_at_4f[0xd]; 8791 8792 u8 pplm[0x1]; 8793 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8794 8795 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8796 u8 pbmc[0x1]; 8797 u8 pptb[0x1]; 8798 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8799 u8 ppcnt[0x1]; 8800 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8801 }; 8802 8803 struct mlx5_ifc_pcam_reg_bits { 8804 u8 reserved_at_0[0x8]; 8805 u8 feature_group[0x8]; 8806 u8 reserved_at_10[0x8]; 8807 u8 access_reg_group[0x8]; 8808 8809 u8 reserved_at_20[0x20]; 8810 8811 union { 8812 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8813 u8 reserved_at_0[0x80]; 8814 } port_access_reg_cap_mask; 8815 8816 u8 reserved_at_c0[0x80]; 8817 8818 union { 8819 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8820 u8 reserved_at_0[0x80]; 8821 } feature_cap_mask; 8822 8823 u8 reserved_at_1c0[0xc0]; 8824 }; 8825 8826 struct mlx5_ifc_mcam_enhanced_features_bits { 8827 u8 reserved_at_0[0x6e]; 8828 u8 pcie_status_and_power[0x1]; 8829 u8 reserved_at_111[0x10]; 8830 u8 pcie_performance_group[0x1]; 8831 }; 8832 8833 struct mlx5_ifc_mcam_access_reg_bits { 8834 u8 reserved_at_0[0x1c]; 8835 u8 mcda[0x1]; 8836 u8 mcc[0x1]; 8837 u8 mcqi[0x1]; 8838 u8 reserved_at_1f[0x1]; 8839 8840 u8 regs_95_to_64[0x20]; 8841 u8 regs_63_to_32[0x20]; 8842 u8 regs_31_to_0[0x20]; 8843 }; 8844 8845 struct mlx5_ifc_mcam_reg_bits { 8846 u8 reserved_at_0[0x8]; 8847 u8 feature_group[0x8]; 8848 u8 reserved_at_10[0x8]; 8849 u8 access_reg_group[0x8]; 8850 8851 u8 reserved_at_20[0x20]; 8852 8853 union { 8854 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8855 u8 reserved_at_0[0x80]; 8856 } mng_access_reg_cap_mask; 8857 8858 u8 reserved_at_c0[0x80]; 8859 8860 union { 8861 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8862 u8 reserved_at_0[0x80]; 8863 } mng_feature_cap_mask; 8864 8865 u8 reserved_at_1c0[0x80]; 8866 }; 8867 8868 struct mlx5_ifc_pcap_reg_bits { 8869 u8 reserved_0[0x8]; 8870 u8 local_port[0x8]; 8871 u8 reserved_1[0x10]; 8872 8873 u8 port_capability_mask[4][0x20]; 8874 }; 8875 8876 struct mlx5_ifc_pbmc_reg_bits { 8877 u8 reserved_at_0[0x8]; 8878 u8 local_port[0x8]; 8879 u8 reserved_at_10[0x10]; 8880 8881 u8 xoff_timer_value[0x10]; 8882 u8 xoff_refresh[0x10]; 8883 8884 u8 reserved_at_40[0x9]; 8885 u8 fullness_threshold[0x7]; 8886 u8 port_buffer_size[0x10]; 8887 8888 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8889 8890 u8 reserved_at_2e0[0x80]; 8891 }; 8892 8893 struct mlx5_ifc_paos_reg_bits { 8894 u8 swid[0x8]; 8895 u8 local_port[0x8]; 8896 u8 reserved_0[0x4]; 8897 u8 admin_status[0x4]; 8898 u8 reserved_1[0x4]; 8899 u8 oper_status[0x4]; 8900 8901 u8 ase[0x1]; 8902 u8 ee[0x1]; 8903 u8 reserved_2[0x1c]; 8904 u8 e[0x2]; 8905 8906 u8 reserved_3[0x40]; 8907 }; 8908 8909 struct mlx5_ifc_pamp_reg_bits { 8910 u8 reserved_0[0x8]; 8911 u8 opamp_group[0x8]; 8912 u8 reserved_1[0xc]; 8913 u8 opamp_group_type[0x4]; 8914 8915 u8 start_index[0x10]; 8916 u8 reserved_2[0x4]; 8917 u8 num_of_indices[0xc]; 8918 8919 u8 index_data[18][0x10]; 8920 }; 8921 8922 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 8923 u8 llr_rx_cells_high[0x20]; 8924 8925 u8 llr_rx_cells_low[0x20]; 8926 8927 u8 llr_rx_error_high[0x20]; 8928 8929 u8 llr_rx_error_low[0x20]; 8930 8931 u8 llr_rx_crc_error_high[0x20]; 8932 8933 u8 llr_rx_crc_error_low[0x20]; 8934 8935 u8 llr_tx_cells_high[0x20]; 8936 8937 u8 llr_tx_cells_low[0x20]; 8938 8939 u8 llr_tx_ret_cells_high[0x20]; 8940 8941 u8 llr_tx_ret_cells_low[0x20]; 8942 8943 u8 llr_tx_ret_events_high[0x20]; 8944 8945 u8 llr_tx_ret_events_low[0x20]; 8946 8947 u8 reserved_0[0x640]; 8948 }; 8949 8950 struct mlx5_ifc_mtmp_reg_bits { 8951 u8 i[0x1]; 8952 u8 reserved_at_1[0x18]; 8953 u8 sensor_index[0x7]; 8954 8955 u8 reserved_at_20[0x10]; 8956 u8 temperature[0x10]; 8957 8958 u8 mte[0x1]; 8959 u8 mtr[0x1]; 8960 u8 reserved_at_42[0x0e]; 8961 u8 max_temperature[0x10]; 8962 8963 u8 tee[0x2]; 8964 u8 reserved_at_62[0x0e]; 8965 u8 temperature_threshold_hi[0x10]; 8966 8967 u8 reserved_at_80[0x10]; 8968 u8 temperature_threshold_lo[0x10]; 8969 8970 u8 reserved_at_100[0x20]; 8971 8972 u8 sensor_name[0x40]; 8973 }; 8974 8975 struct mlx5_ifc_lane_2_module_mapping_bits { 8976 u8 reserved_0[0x6]; 8977 u8 rx_lane[0x2]; 8978 u8 reserved_1[0x6]; 8979 u8 tx_lane[0x2]; 8980 u8 reserved_2[0x8]; 8981 u8 module[0x8]; 8982 }; 8983 8984 struct mlx5_ifc_eth_per_traffic_class_layout_bits { 8985 u8 transmit_queue_high[0x20]; 8986 8987 u8 transmit_queue_low[0x20]; 8988 8989 u8 reserved_0[0x780]; 8990 }; 8991 8992 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 8993 u8 no_buffer_discard_uc_high[0x20]; 8994 8995 u8 no_buffer_discard_uc_low[0x20]; 8996 8997 u8 wred_discard_high[0x20]; 8998 8999 u8 wred_discard_low[0x20]; 9000 9001 u8 reserved_0[0x740]; 9002 }; 9003 9004 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 9005 u8 rx_octets_high[0x20]; 9006 9007 u8 rx_octets_low[0x20]; 9008 9009 u8 reserved_0[0xc0]; 9010 9011 u8 rx_frames_high[0x20]; 9012 9013 u8 rx_frames_low[0x20]; 9014 9015 u8 tx_octets_high[0x20]; 9016 9017 u8 tx_octets_low[0x20]; 9018 9019 u8 reserved_1[0xc0]; 9020 9021 u8 tx_frames_high[0x20]; 9022 9023 u8 tx_frames_low[0x20]; 9024 9025 u8 rx_pause_high[0x20]; 9026 9027 u8 rx_pause_low[0x20]; 9028 9029 u8 rx_pause_duration_high[0x20]; 9030 9031 u8 rx_pause_duration_low[0x20]; 9032 9033 u8 tx_pause_high[0x20]; 9034 9035 u8 tx_pause_low[0x20]; 9036 9037 u8 tx_pause_duration_high[0x20]; 9038 9039 u8 tx_pause_duration_low[0x20]; 9040 9041 u8 rx_pause_transition_high[0x20]; 9042 9043 u8 rx_pause_transition_low[0x20]; 9044 9045 u8 rx_discards_high[0x20]; 9046 9047 u8 rx_discards_low[0x20]; 9048 9049 u8 device_stall_minor_watermark_cnt_high[0x20]; 9050 9051 u8 device_stall_minor_watermark_cnt_low[0x20]; 9052 9053 u8 device_stall_critical_watermark_cnt_high[0x20]; 9054 9055 u8 device_stall_critical_watermark_cnt_low[0x20]; 9056 9057 u8 reserved_2[0x340]; 9058 }; 9059 9060 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 9061 u8 port_transmit_wait_high[0x20]; 9062 9063 u8 port_transmit_wait_low[0x20]; 9064 9065 u8 ecn_marked_high[0x20]; 9066 9067 u8 ecn_marked_low[0x20]; 9068 9069 u8 no_buffer_discard_mc_high[0x20]; 9070 9071 u8 no_buffer_discard_mc_low[0x20]; 9072 9073 u8 rx_ebp_high[0x20]; 9074 9075 u8 rx_ebp_low[0x20]; 9076 9077 u8 tx_ebp_high[0x20]; 9078 9079 u8 tx_ebp_low[0x20]; 9080 9081 u8 rx_buffer_almost_full_high[0x20]; 9082 9083 u8 rx_buffer_almost_full_low[0x20]; 9084 9085 u8 rx_buffer_full_high[0x20]; 9086 9087 u8 rx_buffer_full_low[0x20]; 9088 9089 u8 rx_icrc_encapsulated_high[0x20]; 9090 9091 u8 rx_icrc_encapsulated_low[0x20]; 9092 9093 u8 reserved_0[0x80]; 9094 9095 u8 tx_stats_pkts64octets_high[0x20]; 9096 9097 u8 tx_stats_pkts64octets_low[0x20]; 9098 9099 u8 tx_stats_pkts65to127octets_high[0x20]; 9100 9101 u8 tx_stats_pkts65to127octets_low[0x20]; 9102 9103 u8 tx_stats_pkts128to255octets_high[0x20]; 9104 9105 u8 tx_stats_pkts128to255octets_low[0x20]; 9106 9107 u8 tx_stats_pkts256to511octets_high[0x20]; 9108 9109 u8 tx_stats_pkts256to511octets_low[0x20]; 9110 9111 u8 tx_stats_pkts512to1023octets_high[0x20]; 9112 9113 u8 tx_stats_pkts512to1023octets_low[0x20]; 9114 9115 u8 tx_stats_pkts1024to1518octets_high[0x20]; 9116 9117 u8 tx_stats_pkts1024to1518octets_low[0x20]; 9118 9119 u8 tx_stats_pkts1519to2047octets_high[0x20]; 9120 9121 u8 tx_stats_pkts1519to2047octets_low[0x20]; 9122 9123 u8 tx_stats_pkts2048to4095octets_high[0x20]; 9124 9125 u8 tx_stats_pkts2048to4095octets_low[0x20]; 9126 9127 u8 tx_stats_pkts4096to8191octets_high[0x20]; 9128 9129 u8 tx_stats_pkts4096to8191octets_low[0x20]; 9130 9131 u8 tx_stats_pkts8192to10239octets_high[0x20]; 9132 9133 u8 tx_stats_pkts8192to10239octets_low[0x20]; 9134 9135 u8 reserved_1[0x2C0]; 9136 }; 9137 9138 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 9139 u8 a_frames_transmitted_ok_high[0x20]; 9140 9141 u8 a_frames_transmitted_ok_low[0x20]; 9142 9143 u8 a_frames_received_ok_high[0x20]; 9144 9145 u8 a_frames_received_ok_low[0x20]; 9146 9147 u8 a_frame_check_sequence_errors_high[0x20]; 9148 9149 u8 a_frame_check_sequence_errors_low[0x20]; 9150 9151 u8 a_alignment_errors_high[0x20]; 9152 9153 u8 a_alignment_errors_low[0x20]; 9154 9155 u8 a_octets_transmitted_ok_high[0x20]; 9156 9157 u8 a_octets_transmitted_ok_low[0x20]; 9158 9159 u8 a_octets_received_ok_high[0x20]; 9160 9161 u8 a_octets_received_ok_low[0x20]; 9162 9163 u8 a_multicast_frames_xmitted_ok_high[0x20]; 9164 9165 u8 a_multicast_frames_xmitted_ok_low[0x20]; 9166 9167 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 9168 9169 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 9170 9171 u8 a_multicast_frames_received_ok_high[0x20]; 9172 9173 u8 a_multicast_frames_received_ok_low[0x20]; 9174 9175 u8 a_broadcast_frames_recieved_ok_high[0x20]; 9176 9177 u8 a_broadcast_frames_recieved_ok_low[0x20]; 9178 9179 u8 a_in_range_length_errors_high[0x20]; 9180 9181 u8 a_in_range_length_errors_low[0x20]; 9182 9183 u8 a_out_of_range_length_field_high[0x20]; 9184 9185 u8 a_out_of_range_length_field_low[0x20]; 9186 9187 u8 a_frame_too_long_errors_high[0x20]; 9188 9189 u8 a_frame_too_long_errors_low[0x20]; 9190 9191 u8 a_symbol_error_during_carrier_high[0x20]; 9192 9193 u8 a_symbol_error_during_carrier_low[0x20]; 9194 9195 u8 a_mac_control_frames_transmitted_high[0x20]; 9196 9197 u8 a_mac_control_frames_transmitted_low[0x20]; 9198 9199 u8 a_mac_control_frames_received_high[0x20]; 9200 9201 u8 a_mac_control_frames_received_low[0x20]; 9202 9203 u8 a_unsupported_opcodes_received_high[0x20]; 9204 9205 u8 a_unsupported_opcodes_received_low[0x20]; 9206 9207 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 9208 9209 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 9210 9211 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 9212 9213 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 9214 9215 u8 reserved_0[0x300]; 9216 }; 9217 9218 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 9219 u8 dot3stats_alignment_errors_high[0x20]; 9220 9221 u8 dot3stats_alignment_errors_low[0x20]; 9222 9223 u8 dot3stats_fcs_errors_high[0x20]; 9224 9225 u8 dot3stats_fcs_errors_low[0x20]; 9226 9227 u8 dot3stats_single_collision_frames_high[0x20]; 9228 9229 u8 dot3stats_single_collision_frames_low[0x20]; 9230 9231 u8 dot3stats_multiple_collision_frames_high[0x20]; 9232 9233 u8 dot3stats_multiple_collision_frames_low[0x20]; 9234 9235 u8 dot3stats_sqe_test_errors_high[0x20]; 9236 9237 u8 dot3stats_sqe_test_errors_low[0x20]; 9238 9239 u8 dot3stats_deferred_transmissions_high[0x20]; 9240 9241 u8 dot3stats_deferred_transmissions_low[0x20]; 9242 9243 u8 dot3stats_late_collisions_high[0x20]; 9244 9245 u8 dot3stats_late_collisions_low[0x20]; 9246 9247 u8 dot3stats_excessive_collisions_high[0x20]; 9248 9249 u8 dot3stats_excessive_collisions_low[0x20]; 9250 9251 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 9252 9253 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 9254 9255 u8 dot3stats_carrier_sense_errors_high[0x20]; 9256 9257 u8 dot3stats_carrier_sense_errors_low[0x20]; 9258 9259 u8 dot3stats_frame_too_longs_high[0x20]; 9260 9261 u8 dot3stats_frame_too_longs_low[0x20]; 9262 9263 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 9264 9265 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 9266 9267 u8 dot3stats_symbol_errors_high[0x20]; 9268 9269 u8 dot3stats_symbol_errors_low[0x20]; 9270 9271 u8 dot3control_in_unknown_opcodes_high[0x20]; 9272 9273 u8 dot3control_in_unknown_opcodes_low[0x20]; 9274 9275 u8 dot3in_pause_frames_high[0x20]; 9276 9277 u8 dot3in_pause_frames_low[0x20]; 9278 9279 u8 dot3out_pause_frames_high[0x20]; 9280 9281 u8 dot3out_pause_frames_low[0x20]; 9282 9283 u8 reserved_0[0x3c0]; 9284 }; 9285 9286 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 9287 u8 if_in_octets_high[0x20]; 9288 9289 u8 if_in_octets_low[0x20]; 9290 9291 u8 if_in_ucast_pkts_high[0x20]; 9292 9293 u8 if_in_ucast_pkts_low[0x20]; 9294 9295 u8 if_in_discards_high[0x20]; 9296 9297 u8 if_in_discards_low[0x20]; 9298 9299 u8 if_in_errors_high[0x20]; 9300 9301 u8 if_in_errors_low[0x20]; 9302 9303 u8 if_in_unknown_protos_high[0x20]; 9304 9305 u8 if_in_unknown_protos_low[0x20]; 9306 9307 u8 if_out_octets_high[0x20]; 9308 9309 u8 if_out_octets_low[0x20]; 9310 9311 u8 if_out_ucast_pkts_high[0x20]; 9312 9313 u8 if_out_ucast_pkts_low[0x20]; 9314 9315 u8 if_out_discards_high[0x20]; 9316 9317 u8 if_out_discards_low[0x20]; 9318 9319 u8 if_out_errors_high[0x20]; 9320 9321 u8 if_out_errors_low[0x20]; 9322 9323 u8 if_in_multicast_pkts_high[0x20]; 9324 9325 u8 if_in_multicast_pkts_low[0x20]; 9326 9327 u8 if_in_broadcast_pkts_high[0x20]; 9328 9329 u8 if_in_broadcast_pkts_low[0x20]; 9330 9331 u8 if_out_multicast_pkts_high[0x20]; 9332 9333 u8 if_out_multicast_pkts_low[0x20]; 9334 9335 u8 if_out_broadcast_pkts_high[0x20]; 9336 9337 u8 if_out_broadcast_pkts_low[0x20]; 9338 9339 u8 reserved_0[0x480]; 9340 }; 9341 9342 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 9343 u8 ether_stats_drop_events_high[0x20]; 9344 9345 u8 ether_stats_drop_events_low[0x20]; 9346 9347 u8 ether_stats_octets_high[0x20]; 9348 9349 u8 ether_stats_octets_low[0x20]; 9350 9351 u8 ether_stats_pkts_high[0x20]; 9352 9353 u8 ether_stats_pkts_low[0x20]; 9354 9355 u8 ether_stats_broadcast_pkts_high[0x20]; 9356 9357 u8 ether_stats_broadcast_pkts_low[0x20]; 9358 9359 u8 ether_stats_multicast_pkts_high[0x20]; 9360 9361 u8 ether_stats_multicast_pkts_low[0x20]; 9362 9363 u8 ether_stats_crc_align_errors_high[0x20]; 9364 9365 u8 ether_stats_crc_align_errors_low[0x20]; 9366 9367 u8 ether_stats_undersize_pkts_high[0x20]; 9368 9369 u8 ether_stats_undersize_pkts_low[0x20]; 9370 9371 u8 ether_stats_oversize_pkts_high[0x20]; 9372 9373 u8 ether_stats_oversize_pkts_low[0x20]; 9374 9375 u8 ether_stats_fragments_high[0x20]; 9376 9377 u8 ether_stats_fragments_low[0x20]; 9378 9379 u8 ether_stats_jabbers_high[0x20]; 9380 9381 u8 ether_stats_jabbers_low[0x20]; 9382 9383 u8 ether_stats_collisions_high[0x20]; 9384 9385 u8 ether_stats_collisions_low[0x20]; 9386 9387 u8 ether_stats_pkts64octets_high[0x20]; 9388 9389 u8 ether_stats_pkts64octets_low[0x20]; 9390 9391 u8 ether_stats_pkts65to127octets_high[0x20]; 9392 9393 u8 ether_stats_pkts65to127octets_low[0x20]; 9394 9395 u8 ether_stats_pkts128to255octets_high[0x20]; 9396 9397 u8 ether_stats_pkts128to255octets_low[0x20]; 9398 9399 u8 ether_stats_pkts256to511octets_high[0x20]; 9400 9401 u8 ether_stats_pkts256to511octets_low[0x20]; 9402 9403 u8 ether_stats_pkts512to1023octets_high[0x20]; 9404 9405 u8 ether_stats_pkts512to1023octets_low[0x20]; 9406 9407 u8 ether_stats_pkts1024to1518octets_high[0x20]; 9408 9409 u8 ether_stats_pkts1024to1518octets_low[0x20]; 9410 9411 u8 ether_stats_pkts1519to2047octets_high[0x20]; 9412 9413 u8 ether_stats_pkts1519to2047octets_low[0x20]; 9414 9415 u8 ether_stats_pkts2048to4095octets_high[0x20]; 9416 9417 u8 ether_stats_pkts2048to4095octets_low[0x20]; 9418 9419 u8 ether_stats_pkts4096to8191octets_high[0x20]; 9420 9421 u8 ether_stats_pkts4096to8191octets_low[0x20]; 9422 9423 u8 ether_stats_pkts8192to10239octets_high[0x20]; 9424 9425 u8 ether_stats_pkts8192to10239octets_low[0x20]; 9426 9427 u8 reserved_0[0x280]; 9428 }; 9429 9430 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 9431 u8 symbol_error_counter[0x10]; 9432 u8 link_error_recovery_counter[0x8]; 9433 u8 link_downed_counter[0x8]; 9434 9435 u8 port_rcv_errors[0x10]; 9436 u8 port_rcv_remote_physical_errors[0x10]; 9437 9438 u8 port_rcv_switch_relay_errors[0x10]; 9439 u8 port_xmit_discards[0x10]; 9440 9441 u8 port_xmit_constraint_errors[0x8]; 9442 u8 port_rcv_constraint_errors[0x8]; 9443 u8 reserved_0[0x8]; 9444 u8 local_link_integrity_errors[0x4]; 9445 u8 excessive_buffer_overrun_errors[0x4]; 9446 9447 u8 reserved_1[0x10]; 9448 u8 vl_15_dropped[0x10]; 9449 9450 u8 port_xmit_data[0x20]; 9451 9452 u8 port_rcv_data[0x20]; 9453 9454 u8 port_xmit_pkts[0x20]; 9455 9456 u8 port_rcv_pkts[0x20]; 9457 9458 u8 port_xmit_wait[0x20]; 9459 9460 u8 reserved_2[0x680]; 9461 }; 9462 9463 struct mlx5_ifc_trc_tlb_reg_bits { 9464 u8 reserved_0[0x80]; 9465 9466 u8 tlb_addr[0][0x40]; 9467 }; 9468 9469 struct mlx5_ifc_trc_read_fifo_reg_bits { 9470 u8 reserved_0[0x10]; 9471 u8 requested_event_num[0x10]; 9472 9473 u8 reserved_1[0x20]; 9474 9475 u8 reserved_2[0x10]; 9476 u8 acual_event_num[0x10]; 9477 9478 u8 reserved_3[0x20]; 9479 9480 u8 event[0][0x40]; 9481 }; 9482 9483 struct mlx5_ifc_trc_lock_reg_bits { 9484 u8 reserved_0[0x1f]; 9485 u8 lock[0x1]; 9486 9487 u8 reserved_1[0x60]; 9488 }; 9489 9490 struct mlx5_ifc_trc_filter_reg_bits { 9491 u8 status[0x1]; 9492 u8 reserved_0[0xf]; 9493 u8 filter_index[0x10]; 9494 9495 u8 reserved_1[0x20]; 9496 9497 u8 filter_val[0x20]; 9498 9499 u8 reserved_2[0x1a0]; 9500 }; 9501 9502 struct mlx5_ifc_trc_event_reg_bits { 9503 u8 status[0x1]; 9504 u8 reserved_0[0xf]; 9505 u8 event_index[0x10]; 9506 9507 u8 reserved_1[0x20]; 9508 9509 u8 event_id[0x20]; 9510 9511 u8 event_selector_val[0x10]; 9512 u8 event_selector_size[0x10]; 9513 9514 u8 reserved_2[0x180]; 9515 }; 9516 9517 struct mlx5_ifc_trc_conf_reg_bits { 9518 u8 limit_en[0x1]; 9519 u8 reserved_0[0x3]; 9520 u8 dump_mode[0x4]; 9521 u8 reserved_1[0x15]; 9522 u8 state[0x3]; 9523 9524 u8 reserved_2[0x20]; 9525 9526 u8 limit_event_index[0x20]; 9527 9528 u8 mkey[0x20]; 9529 9530 u8 fifo_ready_ev_num[0x20]; 9531 9532 u8 reserved_3[0x160]; 9533 }; 9534 9535 struct mlx5_ifc_trc_cap_reg_bits { 9536 u8 reserved_0[0x18]; 9537 u8 dump_mode[0x8]; 9538 9539 u8 reserved_1[0x20]; 9540 9541 u8 num_of_events[0x10]; 9542 u8 num_of_filters[0x10]; 9543 9544 u8 fifo_size[0x20]; 9545 9546 u8 tlb_size[0x10]; 9547 u8 event_size[0x10]; 9548 9549 u8 reserved_2[0x160]; 9550 }; 9551 9552 struct mlx5_ifc_set_node_in_bits { 9553 u8 node_description[64][0x8]; 9554 }; 9555 9556 struct mlx5_ifc_register_power_settings_bits { 9557 u8 reserved_0[0x18]; 9558 u8 power_settings_level[0x8]; 9559 9560 u8 reserved_1[0x60]; 9561 }; 9562 9563 struct mlx5_ifc_register_host_endianess_bits { 9564 u8 he[0x1]; 9565 u8 reserved_0[0x1f]; 9566 9567 u8 reserved_1[0x60]; 9568 }; 9569 9570 struct mlx5_ifc_register_diag_buffer_ctrl_bits { 9571 u8 physical_address[0x40]; 9572 }; 9573 9574 struct mlx5_ifc_qtct_reg_bits { 9575 u8 operation_type[0x2]; 9576 u8 cap_local_admin[0x1]; 9577 u8 cap_remote_admin[0x1]; 9578 u8 reserved_0[0x4]; 9579 u8 port_number[0x8]; 9580 u8 reserved_1[0xd]; 9581 u8 prio[0x3]; 9582 9583 u8 reserved_2[0x1d]; 9584 u8 tclass[0x3]; 9585 }; 9586 9587 struct mlx5_ifc_qpdp_reg_bits { 9588 u8 reserved_0[0x8]; 9589 u8 port_number[0x8]; 9590 u8 reserved_1[0x10]; 9591 9592 u8 reserved_2[0x1d]; 9593 u8 pprio[0x3]; 9594 }; 9595 9596 struct mlx5_ifc_port_info_ro_fields_param_bits { 9597 u8 reserved_0[0x8]; 9598 u8 port[0x8]; 9599 u8 max_gid[0x10]; 9600 9601 u8 reserved_1[0x20]; 9602 9603 u8 port_guid[0x40]; 9604 }; 9605 9606 struct mlx5_ifc_nvqc_reg_bits { 9607 u8 type[0x20]; 9608 9609 u8 reserved_0[0x18]; 9610 u8 version[0x4]; 9611 u8 reserved_1[0x2]; 9612 u8 support_wr[0x1]; 9613 u8 support_rd[0x1]; 9614 }; 9615 9616 struct mlx5_ifc_nvia_reg_bits { 9617 u8 reserved_0[0x1d]; 9618 u8 target[0x3]; 9619 9620 u8 reserved_1[0x20]; 9621 }; 9622 9623 struct mlx5_ifc_nvdi_reg_bits { 9624 struct mlx5_ifc_config_item_bits configuration_item_header; 9625 }; 9626 9627 struct mlx5_ifc_nvda_reg_bits { 9628 struct mlx5_ifc_config_item_bits configuration_item_header; 9629 9630 u8 configuration_item_data[0x20]; 9631 }; 9632 9633 struct mlx5_ifc_node_info_ro_fields_param_bits { 9634 u8 system_image_guid[0x40]; 9635 9636 u8 reserved_0[0x40]; 9637 9638 u8 node_guid[0x40]; 9639 9640 u8 reserved_1[0x10]; 9641 u8 max_pkey[0x10]; 9642 9643 u8 reserved_2[0x20]; 9644 }; 9645 9646 struct mlx5_ifc_ets_tcn_config_reg_bits { 9647 u8 g[0x1]; 9648 u8 b[0x1]; 9649 u8 r[0x1]; 9650 u8 reserved_0[0x9]; 9651 u8 group[0x4]; 9652 u8 reserved_1[0x9]; 9653 u8 bw_allocation[0x7]; 9654 9655 u8 reserved_2[0xc]; 9656 u8 max_bw_units[0x4]; 9657 u8 reserved_3[0x8]; 9658 u8 max_bw_value[0x8]; 9659 }; 9660 9661 struct mlx5_ifc_ets_global_config_reg_bits { 9662 u8 reserved_0[0x2]; 9663 u8 r[0x1]; 9664 u8 reserved_1[0x1d]; 9665 9666 u8 reserved_2[0xc]; 9667 u8 max_bw_units[0x4]; 9668 u8 reserved_3[0x8]; 9669 u8 max_bw_value[0x8]; 9670 }; 9671 9672 struct mlx5_ifc_qetc_reg_bits { 9673 u8 reserved_at_0[0x8]; 9674 u8 port_number[0x8]; 9675 u8 reserved_at_10[0x30]; 9676 9677 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9678 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9679 }; 9680 9681 struct mlx5_ifc_nodnic_mac_filters_bits { 9682 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 9683 9684 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 9685 9686 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 9687 9688 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 9689 9690 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 9691 9692 u8 reserved_0[0xc0]; 9693 }; 9694 9695 struct mlx5_ifc_nodnic_gid_filters_bits { 9696 u8 mgid_filter0[16][0x8]; 9697 9698 u8 mgid_filter1[16][0x8]; 9699 9700 u8 mgid_filter2[16][0x8]; 9701 9702 u8 mgid_filter3[16][0x8]; 9703 }; 9704 9705 enum { 9706 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 9707 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 9708 }; 9709 9710 enum { 9711 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 9712 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 9713 }; 9714 9715 struct mlx5_ifc_nodnic_config_reg_bits { 9716 u8 no_dram_nic_revision[0x8]; 9717 u8 hardware_format[0x8]; 9718 u8 support_receive_filter[0x1]; 9719 u8 support_promisc_filter[0x1]; 9720 u8 support_promisc_multicast_filter[0x1]; 9721 u8 reserved_0[0x2]; 9722 u8 log_working_buffer_size[0x3]; 9723 u8 log_pkey_table_size[0x4]; 9724 u8 reserved_1[0x3]; 9725 u8 num_ports[0x1]; 9726 9727 u8 reserved_2[0x2]; 9728 u8 log_max_ring_size[0x6]; 9729 u8 reserved_3[0x18]; 9730 9731 u8 lkey[0x20]; 9732 9733 u8 cqe_format[0x4]; 9734 u8 reserved_4[0x1c]; 9735 9736 u8 node_guid[0x40]; 9737 9738 u8 reserved_5[0x740]; 9739 9740 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 9741 9742 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 9743 }; 9744 9745 struct mlx5_ifc_vlan_layout_bits { 9746 u8 reserved_0[0x14]; 9747 u8 vlan[0xc]; 9748 9749 u8 reserved_1[0x20]; 9750 }; 9751 9752 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9753 u8 reserved_0[0x20]; 9754 9755 u8 mkey[0x20]; 9756 9757 u8 addressh_63_32[0x20]; 9758 9759 u8 addressl_31_0[0x20]; 9760 }; 9761 9762 struct mlx5_ifc_ud_adrs_vector_bits { 9763 u8 dc_key[0x40]; 9764 9765 u8 ext[0x1]; 9766 u8 reserved_0[0x7]; 9767 u8 destination_qp_dct[0x18]; 9768 9769 u8 static_rate[0x4]; 9770 u8 sl_eth_prio[0x4]; 9771 u8 fl[0x1]; 9772 u8 mlid[0x7]; 9773 u8 rlid_udp_sport[0x10]; 9774 9775 u8 reserved_1[0x20]; 9776 9777 u8 rmac_47_16[0x20]; 9778 9779 u8 rmac_15_0[0x10]; 9780 u8 tclass[0x8]; 9781 u8 hop_limit[0x8]; 9782 9783 u8 reserved_2[0x1]; 9784 u8 grh[0x1]; 9785 u8 reserved_3[0x2]; 9786 u8 src_addr_index[0x8]; 9787 u8 flow_label[0x14]; 9788 9789 u8 rgid_rip[16][0x8]; 9790 }; 9791 9792 struct mlx5_ifc_port_module_event_bits { 9793 u8 reserved_0[0x8]; 9794 u8 module[0x8]; 9795 u8 reserved_1[0xc]; 9796 u8 module_status[0x4]; 9797 9798 u8 reserved_2[0x14]; 9799 u8 error_type[0x4]; 9800 u8 reserved_3[0x8]; 9801 9802 u8 reserved_4[0xa0]; 9803 }; 9804 9805 struct mlx5_ifc_icmd_control_bits { 9806 u8 opcode[0x10]; 9807 u8 status[0x8]; 9808 u8 reserved_0[0x7]; 9809 u8 busy[0x1]; 9810 }; 9811 9812 struct mlx5_ifc_eqe_bits { 9813 u8 reserved_0[0x8]; 9814 u8 event_type[0x8]; 9815 u8 reserved_1[0x8]; 9816 u8 event_sub_type[0x8]; 9817 9818 u8 reserved_2[0xe0]; 9819 9820 union mlx5_ifc_event_auto_bits event_data; 9821 9822 u8 reserved_3[0x10]; 9823 u8 signature[0x8]; 9824 u8 reserved_4[0x7]; 9825 u8 owner[0x1]; 9826 }; 9827 9828 enum { 9829 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9830 }; 9831 9832 struct mlx5_ifc_cmd_queue_entry_bits { 9833 u8 type[0x8]; 9834 u8 reserved_0[0x18]; 9835 9836 u8 input_length[0x20]; 9837 9838 u8 input_mailbox_pointer_63_32[0x20]; 9839 9840 u8 input_mailbox_pointer_31_9[0x17]; 9841 u8 reserved_1[0x9]; 9842 9843 u8 command_input_inline_data[16][0x8]; 9844 9845 u8 command_output_inline_data[16][0x8]; 9846 9847 u8 output_mailbox_pointer_63_32[0x20]; 9848 9849 u8 output_mailbox_pointer_31_9[0x17]; 9850 u8 reserved_2[0x9]; 9851 9852 u8 output_length[0x20]; 9853 9854 u8 token[0x8]; 9855 u8 signature[0x8]; 9856 u8 reserved_3[0x8]; 9857 u8 status[0x7]; 9858 u8 ownership[0x1]; 9859 }; 9860 9861 struct mlx5_ifc_cmd_out_bits { 9862 u8 status[0x8]; 9863 u8 reserved_0[0x18]; 9864 9865 u8 syndrome[0x20]; 9866 9867 u8 command_output[0x20]; 9868 }; 9869 9870 struct mlx5_ifc_cmd_in_bits { 9871 u8 opcode[0x10]; 9872 u8 reserved_0[0x10]; 9873 9874 u8 reserved_1[0x10]; 9875 u8 op_mod[0x10]; 9876 9877 u8 command[0][0x20]; 9878 }; 9879 9880 struct mlx5_ifc_cmd_if_box_bits { 9881 u8 mailbox_data[512][0x8]; 9882 9883 u8 reserved_0[0x180]; 9884 9885 u8 next_pointer_63_32[0x20]; 9886 9887 u8 next_pointer_31_10[0x16]; 9888 u8 reserved_1[0xa]; 9889 9890 u8 block_number[0x20]; 9891 9892 u8 reserved_2[0x8]; 9893 u8 token[0x8]; 9894 u8 ctrl_signature[0x8]; 9895 u8 signature[0x8]; 9896 }; 9897 9898 struct mlx5_ifc_mtt_bits { 9899 u8 ptag_63_32[0x20]; 9900 9901 u8 ptag_31_8[0x18]; 9902 u8 reserved_0[0x6]; 9903 u8 wr_en[0x1]; 9904 u8 rd_en[0x1]; 9905 }; 9906 9907 struct mlx5_ifc_tls_progress_params_bits { 9908 u8 valid[0x1]; 9909 u8 reserved_at_1[0x7]; 9910 u8 pd[0x18]; 9911 9912 u8 next_record_tcp_sn[0x20]; 9913 9914 u8 hw_resync_tcp_sn[0x20]; 9915 9916 u8 record_tracker_state[0x2]; 9917 u8 auth_state[0x2]; 9918 u8 reserved_at_64[0x4]; 9919 u8 hw_offset_record_number[0x18]; 9920 }; 9921 9922 struct mlx5_ifc_tls_static_params_bits { 9923 u8 const_2[0x2]; 9924 u8 tls_version[0x4]; 9925 u8 const_1[0x2]; 9926 u8 reserved_at_8[0x14]; 9927 u8 encryption_standard[0x4]; 9928 9929 u8 reserved_at_20[0x20]; 9930 9931 u8 initial_record_number[0x40]; 9932 9933 u8 resync_tcp_sn[0x20]; 9934 9935 u8 gcm_iv[0x20]; 9936 9937 u8 implicit_iv[0x40]; 9938 9939 u8 reserved_at_100[0x8]; 9940 u8 dek_index[0x18]; 9941 9942 u8 reserved_at_120[0xe0]; 9943 }; 9944 9945 /* Vendor Specific Capabilities, VSC */ 9946 enum { 9947 MLX5_VSC_DOMAIN_ICMD = 0x1, 9948 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 9949 MLX5_VSC_DOMAIN_SCAN_CRSPACE = 0x7, 9950 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 9951 }; 9952 9953 struct mlx5_ifc_vendor_specific_cap_bits { 9954 u8 type[0x8]; 9955 u8 length[0x8]; 9956 u8 next_pointer[0x8]; 9957 u8 capability_id[0x8]; 9958 9959 u8 status[0x3]; 9960 u8 reserved_0[0xd]; 9961 u8 space[0x10]; 9962 9963 u8 counter[0x20]; 9964 9965 u8 semaphore[0x20]; 9966 9967 u8 flag[0x1]; 9968 u8 reserved_1[0x1]; 9969 u8 address[0x1e]; 9970 9971 u8 data[0x20]; 9972 }; 9973 9974 struct mlx5_ifc_vsc_space_bits { 9975 u8 status[0x3]; 9976 u8 reserved0[0xd]; 9977 u8 space[0x10]; 9978 }; 9979 9980 struct mlx5_ifc_vsc_addr_bits { 9981 u8 flag[0x1]; 9982 u8 reserved0[0x1]; 9983 u8 address[0x1e]; 9984 }; 9985 9986 enum { 9987 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9988 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9989 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9990 }; 9991 9992 enum { 9993 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9994 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9995 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9996 }; 9997 9998 enum { 9999 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 10000 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 10001 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 10002 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 10003 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 10004 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 10005 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 10006 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 10007 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 10008 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 10009 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 10010 }; 10011 10012 struct mlx5_ifc_initial_seg_bits { 10013 u8 fw_rev_minor[0x10]; 10014 u8 fw_rev_major[0x10]; 10015 10016 u8 cmd_interface_rev[0x10]; 10017 u8 fw_rev_subminor[0x10]; 10018 10019 u8 reserved_0[0x40]; 10020 10021 u8 cmdq_phy_addr_63_32[0x20]; 10022 10023 u8 cmdq_phy_addr_31_12[0x14]; 10024 u8 reserved_1[0x2]; 10025 u8 nic_interface[0x2]; 10026 u8 log_cmdq_size[0x4]; 10027 u8 log_cmdq_stride[0x4]; 10028 10029 u8 command_doorbell_vector[0x20]; 10030 10031 u8 reserved_2[0xf00]; 10032 10033 u8 initializing[0x1]; 10034 u8 reserved_3[0x4]; 10035 u8 nic_interface_supported[0x3]; 10036 u8 reserved_4[0x18]; 10037 10038 struct mlx5_ifc_health_buffer_bits health_buffer; 10039 10040 u8 no_dram_nic_offset[0x20]; 10041 10042 u8 reserved_5[0x6de0]; 10043 10044 u8 internal_timer_h[0x20]; 10045 10046 u8 internal_timer_l[0x20]; 10047 10048 u8 reserved_6[0x20]; 10049 10050 u8 reserved_7[0x1f]; 10051 u8 clear_int[0x1]; 10052 10053 u8 health_syndrome[0x8]; 10054 u8 health_counter[0x18]; 10055 10056 u8 reserved_8[0x17fc0]; 10057 }; 10058 10059 union mlx5_ifc_icmd_interface_document_bits { 10060 struct mlx5_ifc_fw_version_bits fw_version; 10061 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 10062 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 10063 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 10064 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 10065 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 10066 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 10067 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 10068 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 10069 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 10070 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 10071 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 10072 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 10073 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 10074 u8 reserved_0[0x42c0]; 10075 }; 10076 10077 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 10078 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10079 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10080 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10081 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10082 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10083 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10084 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10085 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10086 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 10087 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 10088 u8 reserved_0[0x7c0]; 10089 }; 10090 10091 struct mlx5_ifc_ppcnt_reg_bits { 10092 u8 swid[0x8]; 10093 u8 local_port[0x8]; 10094 u8 pnat[0x2]; 10095 u8 reserved_0[0x8]; 10096 u8 grp[0x6]; 10097 10098 u8 clr[0x1]; 10099 u8 reserved_1[0x1c]; 10100 u8 prio_tc[0x3]; 10101 10102 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10103 }; 10104 10105 struct mlx5_ifc_pcie_lanes_counters_bits { 10106 u8 life_time_counter_high[0x20]; 10107 10108 u8 life_time_counter_low[0x20]; 10109 10110 u8 error_counter_lane0[0x20]; 10111 10112 u8 error_counter_lane1[0x20]; 10113 10114 u8 error_counter_lane2[0x20]; 10115 10116 u8 error_counter_lane3[0x20]; 10117 10118 u8 error_counter_lane4[0x20]; 10119 10120 u8 error_counter_lane5[0x20]; 10121 10122 u8 error_counter_lane6[0x20]; 10123 10124 u8 error_counter_lane7[0x20]; 10125 10126 u8 error_counter_lane8[0x20]; 10127 10128 u8 error_counter_lane9[0x20]; 10129 10130 u8 error_counter_lane10[0x20]; 10131 10132 u8 error_counter_lane11[0x20]; 10133 10134 u8 error_counter_lane12[0x20]; 10135 10136 u8 error_counter_lane13[0x20]; 10137 10138 u8 error_counter_lane14[0x20]; 10139 10140 u8 error_counter_lane15[0x20]; 10141 10142 u8 reserved_at_240[0x580]; 10143 }; 10144 10145 struct mlx5_ifc_pcie_lanes_counters_ext_bits { 10146 u8 reserved_at_0[0x40]; 10147 10148 u8 error_counter_lane0[0x20]; 10149 10150 u8 error_counter_lane1[0x20]; 10151 10152 u8 error_counter_lane2[0x20]; 10153 10154 u8 error_counter_lane3[0x20]; 10155 10156 u8 error_counter_lane4[0x20]; 10157 10158 u8 error_counter_lane5[0x20]; 10159 10160 u8 error_counter_lane6[0x20]; 10161 10162 u8 error_counter_lane7[0x20]; 10163 10164 u8 error_counter_lane8[0x20]; 10165 10166 u8 error_counter_lane9[0x20]; 10167 10168 u8 error_counter_lane10[0x20]; 10169 10170 u8 error_counter_lane11[0x20]; 10171 10172 u8 error_counter_lane12[0x20]; 10173 10174 u8 error_counter_lane13[0x20]; 10175 10176 u8 error_counter_lane14[0x20]; 10177 10178 u8 error_counter_lane15[0x20]; 10179 10180 u8 reserved_at_240[0x580]; 10181 }; 10182 10183 struct mlx5_ifc_pcie_perf_counters_bits { 10184 u8 life_time_counter_high[0x20]; 10185 10186 u8 life_time_counter_low[0x20]; 10187 10188 u8 rx_errors[0x20]; 10189 10190 u8 tx_errors[0x20]; 10191 10192 u8 l0_to_recovery_eieos[0x20]; 10193 10194 u8 l0_to_recovery_ts[0x20]; 10195 10196 u8 l0_to_recovery_framing[0x20]; 10197 10198 u8 l0_to_recovery_retrain[0x20]; 10199 10200 u8 crc_error_dllp[0x20]; 10201 10202 u8 crc_error_tlp[0x20]; 10203 10204 u8 tx_overflow_buffer_pkt[0x40]; 10205 10206 u8 outbound_stalled_reads[0x20]; 10207 10208 u8 outbound_stalled_writes[0x20]; 10209 10210 u8 outbound_stalled_reads_events[0x20]; 10211 10212 u8 outbound_stalled_writes_events[0x20]; 10213 10214 u8 tx_overflow_buffer_marked_pkt[0x40]; 10215 10216 u8 reserved_at_240[0x580]; 10217 }; 10218 10219 struct mlx5_ifc_pcie_perf_counters_ext_bits { 10220 u8 reserved_at_0[0x40]; 10221 10222 u8 rx_errors[0x20]; 10223 10224 u8 tx_errors[0x20]; 10225 10226 u8 reserved_at_80[0xc0]; 10227 10228 u8 tx_overflow_buffer_pkt[0x40]; 10229 10230 u8 outbound_stalled_reads[0x20]; 10231 10232 u8 outbound_stalled_writes[0x20]; 10233 10234 u8 outbound_stalled_reads_events[0x20]; 10235 10236 u8 outbound_stalled_writes_events[0x20]; 10237 10238 u8 tx_overflow_buffer_marked_pkt[0x40]; 10239 10240 u8 reserved_at_240[0x580]; 10241 }; 10242 10243 struct mlx5_ifc_pcie_timers_states_bits { 10244 u8 life_time_counter_high[0x20]; 10245 10246 u8 life_time_counter_low[0x20]; 10247 10248 u8 time_to_boot_image_start[0x20]; 10249 10250 u8 time_to_link_image[0x20]; 10251 10252 u8 calibration_time[0x20]; 10253 10254 u8 time_to_first_perst[0x20]; 10255 10256 u8 time_to_detect_state[0x20]; 10257 10258 u8 time_to_l0[0x20]; 10259 10260 u8 time_to_crs_en[0x20]; 10261 10262 u8 time_to_plastic_image_start[0x20]; 10263 10264 u8 time_to_iron_image_start[0x20]; 10265 10266 u8 perst_handler[0x20]; 10267 10268 u8 times_in_l1[0x20]; 10269 10270 u8 times_in_l23[0x20]; 10271 10272 u8 dl_down[0x20]; 10273 10274 u8 config_cycle1usec[0x20]; 10275 10276 u8 config_cycle2to7usec[0x20]; 10277 10278 u8 config_cycle8to15usec[0x20]; 10279 10280 u8 config_cycle16to63usec[0x20]; 10281 10282 u8 config_cycle64usec[0x20]; 10283 10284 u8 correctable_err_msg_sent[0x20]; 10285 10286 u8 non_fatal_err_msg_sent[0x20]; 10287 10288 u8 fatal_err_msg_sent[0x20]; 10289 10290 u8 reserved_at_2e0[0x4e0]; 10291 }; 10292 10293 struct mlx5_ifc_pcie_timers_states_ext_bits { 10294 u8 reserved_at_0[0x40]; 10295 10296 u8 time_to_boot_image_start[0x20]; 10297 10298 u8 time_to_link_image[0x20]; 10299 10300 u8 calibration_time[0x20]; 10301 10302 u8 time_to_first_perst[0x20]; 10303 10304 u8 time_to_detect_state[0x20]; 10305 10306 u8 time_to_l0[0x20]; 10307 10308 u8 time_to_crs_en[0x20]; 10309 10310 u8 time_to_plastic_image_start[0x20]; 10311 10312 u8 time_to_iron_image_start[0x20]; 10313 10314 u8 perst_handler[0x20]; 10315 10316 u8 times_in_l1[0x20]; 10317 10318 u8 times_in_l23[0x20]; 10319 10320 u8 dl_down[0x20]; 10321 10322 u8 config_cycle1usec[0x20]; 10323 10324 u8 config_cycle2to7usec[0x20]; 10325 10326 u8 config_cycle8to15usec[0x20]; 10327 10328 u8 config_cycle16to63usec[0x20]; 10329 10330 u8 config_cycle64usec[0x20]; 10331 10332 u8 correctable_err_msg_sent[0x20]; 10333 10334 u8 non_fatal_err_msg_sent[0x20]; 10335 10336 u8 fatal_err_msg_sent[0x20]; 10337 10338 u8 reserved_at_2e0[0x4e0]; 10339 }; 10340 10341 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits { 10342 struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters; 10343 struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters; 10344 struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states; 10345 u8 reserved_at_0[0x7c0]; 10346 }; 10347 10348 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits { 10349 struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext; 10350 struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext; 10351 struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext; 10352 u8 reserved_at_0[0x7c0]; 10353 }; 10354 10355 struct mlx5_ifc_mpcnt_reg_bits { 10356 u8 reserved_at_0[0x2]; 10357 u8 depth[0x6]; 10358 u8 pcie_index[0x8]; 10359 u8 node[0x8]; 10360 u8 reserved_at_18[0x2]; 10361 u8 grp[0x6]; 10362 10363 u8 clr[0x1]; 10364 u8 reserved_at_21[0x1f]; 10365 10366 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set; 10367 }; 10368 10369 struct mlx5_ifc_mpcnt_reg_ext_bits { 10370 u8 reserved_at_0[0x2]; 10371 u8 depth[0x6]; 10372 u8 pcie_index[0x8]; 10373 u8 node[0x8]; 10374 u8 reserved_at_18[0x2]; 10375 u8 grp[0x6]; 10376 10377 u8 clr[0x1]; 10378 u8 reserved_at_21[0x1f]; 10379 10380 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set; 10381 }; 10382 10383 struct mlx5_ifc_monitor_opcodes_layout_bits { 10384 u8 reserved_at_0[0x10]; 10385 u8 monitor_opcode[0x10]; 10386 }; 10387 10388 union mlx5_ifc_pddr_status_opcode_bits { 10389 struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes; 10390 u8 reserved_at_0[0x20]; 10391 }; 10392 10393 struct mlx5_ifc_troubleshooting_info_page_layout_bits { 10394 u8 reserved_at_0[0x10]; 10395 u8 group_opcode[0x10]; 10396 10397 union mlx5_ifc_pddr_status_opcode_bits status_opcode; 10398 10399 u8 user_feedback_data[0x10]; 10400 u8 user_feedback_index[0x10]; 10401 10402 u8 status_message[0x760]; 10403 }; 10404 10405 union mlx5_ifc_pddr_page_data_bits { 10406 struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page; 10407 struct mlx5_ifc_pddr_module_info_bits pddr_module_info; 10408 u8 reserved_at_0[0x7c0]; 10409 }; 10410 10411 struct mlx5_ifc_pddr_reg_bits { 10412 u8 reserved_at_0[0x8]; 10413 u8 local_port[0x8]; 10414 u8 pnat[0x2]; 10415 u8 reserved_at_12[0xe]; 10416 10417 u8 reserved_at_20[0x18]; 10418 u8 page_select[0x8]; 10419 10420 union mlx5_ifc_pddr_page_data_bits page_data; 10421 }; 10422 10423 enum { 10424 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050, 10425 MLX5_MPEIN_PWR_STATUS_INVALID = 0, 10426 MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1, 10427 MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2, 10428 }; 10429 10430 struct mlx5_ifc_mpein_reg_bits { 10431 u8 reserved_at_0[0x2]; 10432 u8 depth[0x6]; 10433 u8 pcie_index[0x8]; 10434 u8 node[0x8]; 10435 u8 reserved_at_18[0x8]; 10436 10437 u8 capability_mask[0x20]; 10438 10439 u8 reserved_at_40[0x8]; 10440 u8 link_width_enabled[0x8]; 10441 u8 link_speed_enabled[0x10]; 10442 10443 u8 lane0_physical_position[0x8]; 10444 u8 link_width_active[0x8]; 10445 u8 link_speed_active[0x10]; 10446 10447 u8 num_of_pfs[0x10]; 10448 u8 num_of_vfs[0x10]; 10449 10450 u8 bdf0[0x10]; 10451 u8 reserved_at_b0[0x10]; 10452 10453 u8 max_read_request_size[0x4]; 10454 u8 max_payload_size[0x4]; 10455 u8 reserved_at_c8[0x5]; 10456 u8 pwr_status[0x3]; 10457 u8 port_type[0x4]; 10458 u8 reserved_at_d4[0xb]; 10459 u8 lane_reversal[0x1]; 10460 10461 u8 reserved_at_e0[0x14]; 10462 u8 pci_power[0xc]; 10463 10464 u8 reserved_at_100[0x20]; 10465 10466 u8 device_status[0x10]; 10467 u8 port_state[0x8]; 10468 u8 reserved_at_138[0x8]; 10469 10470 u8 reserved_at_140[0x10]; 10471 u8 receiver_detect_result[0x10]; 10472 10473 u8 reserved_at_160[0x20]; 10474 }; 10475 10476 struct mlx5_ifc_mpein_reg_ext_bits { 10477 u8 reserved_at_0[0x2]; 10478 u8 depth[0x6]; 10479 u8 pcie_index[0x8]; 10480 u8 node[0x8]; 10481 u8 reserved_at_18[0x8]; 10482 10483 u8 reserved_at_20[0x20]; 10484 10485 u8 reserved_at_40[0x8]; 10486 u8 link_width_enabled[0x8]; 10487 u8 link_speed_enabled[0x10]; 10488 10489 u8 lane0_physical_position[0x8]; 10490 u8 link_width_active[0x8]; 10491 u8 link_speed_active[0x10]; 10492 10493 u8 num_of_pfs[0x10]; 10494 u8 num_of_vfs[0x10]; 10495 10496 u8 bdf0[0x10]; 10497 u8 reserved_at_b0[0x10]; 10498 10499 u8 max_read_request_size[0x4]; 10500 u8 max_payload_size[0x4]; 10501 u8 reserved_at_c8[0x5]; 10502 u8 pwr_status[0x3]; 10503 u8 port_type[0x4]; 10504 u8 reserved_at_d4[0xb]; 10505 u8 lane_reversal[0x1]; 10506 }; 10507 10508 struct mlx5_ifc_mcqi_cap_bits { 10509 u8 supported_info_bitmask[0x20]; 10510 10511 u8 component_size[0x20]; 10512 10513 u8 max_component_size[0x20]; 10514 10515 u8 log_mcda_word_size[0x4]; 10516 u8 reserved_at_64[0xc]; 10517 u8 mcda_max_write_size[0x10]; 10518 10519 u8 rd_en[0x1]; 10520 u8 reserved_at_81[0x1]; 10521 u8 match_chip_id[0x1]; 10522 u8 match_psid[0x1]; 10523 u8 check_user_timestamp[0x1]; 10524 u8 match_base_guid_mac[0x1]; 10525 u8 reserved_at_86[0x1a]; 10526 }; 10527 10528 struct mlx5_ifc_mcqi_reg_bits { 10529 u8 read_pending_component[0x1]; 10530 u8 reserved_at_1[0xf]; 10531 u8 component_index[0x10]; 10532 10533 u8 reserved_at_20[0x20]; 10534 10535 u8 reserved_at_40[0x1b]; 10536 u8 info_type[0x5]; 10537 10538 u8 info_size[0x20]; 10539 10540 u8 offset[0x20]; 10541 10542 u8 reserved_at_a0[0x10]; 10543 u8 data_size[0x10]; 10544 10545 u8 data[0][0x20]; 10546 }; 10547 10548 struct mlx5_ifc_mcc_reg_bits { 10549 u8 reserved_at_0[0x4]; 10550 u8 time_elapsed_since_last_cmd[0xc]; 10551 u8 reserved_at_10[0x8]; 10552 u8 instruction[0x8]; 10553 10554 u8 reserved_at_20[0x10]; 10555 u8 component_index[0x10]; 10556 10557 u8 reserved_at_40[0x8]; 10558 u8 update_handle[0x18]; 10559 10560 u8 handle_owner_type[0x4]; 10561 u8 handle_owner_host_id[0x4]; 10562 u8 reserved_at_68[0x1]; 10563 u8 control_progress[0x7]; 10564 u8 error_code[0x8]; 10565 u8 reserved_at_78[0x4]; 10566 u8 control_state[0x4]; 10567 10568 u8 component_size[0x20]; 10569 10570 u8 reserved_at_a0[0x60]; 10571 }; 10572 10573 struct mlx5_ifc_mcda_reg_bits { 10574 u8 reserved_at_0[0x8]; 10575 u8 update_handle[0x18]; 10576 10577 u8 offset[0x20]; 10578 10579 u8 reserved_at_40[0x10]; 10580 u8 size[0x10]; 10581 10582 u8 reserved_at_60[0x20]; 10583 10584 u8 data[0][0x20]; 10585 }; 10586 10587 union mlx5_ifc_ports_control_registers_document_bits { 10588 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 10589 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10590 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10591 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10592 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10593 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10594 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10595 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10596 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10597 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 10598 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 10599 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10600 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 10601 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10602 struct mlx5_ifc_paos_reg_bits paos_reg; 10603 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 10604 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10605 struct mlx5_ifc_peir_reg_bits peir_reg; 10606 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10607 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10608 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 10609 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 10610 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 10611 struct mlx5_ifc_phrr_reg_bits phrr_reg; 10612 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10613 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10614 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10615 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10616 struct mlx5_ifc_plib_reg_bits plib_reg; 10617 struct mlx5_ifc_pll_status_data_bits pll_status_data; 10618 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10619 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10620 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10621 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10622 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10623 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10624 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10625 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10626 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10627 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10628 struct mlx5_ifc_ppll_reg_bits ppll_reg; 10629 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10630 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10631 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10632 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10633 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10634 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10635 struct mlx5_ifc_pude_reg_bits pude_reg; 10636 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10637 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10638 struct mlx5_ifc_slrp_reg_bits slrp_reg; 10639 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10640 u8 reserved_0[0x7880]; 10641 }; 10642 10643 union mlx5_ifc_debug_enhancements_document_bits { 10644 struct mlx5_ifc_health_buffer_bits health_buffer; 10645 u8 reserved_0[0x200]; 10646 }; 10647 10648 union mlx5_ifc_no_dram_nic_document_bits { 10649 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 10650 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 10651 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 10652 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 10653 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 10654 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 10655 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 10656 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 10657 u8 reserved_0[0x3160]; 10658 }; 10659 10660 union mlx5_ifc_uplink_pci_interface_document_bits { 10661 struct mlx5_ifc_initial_seg_bits initial_seg; 10662 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 10663 u8 reserved_0[0x20120]; 10664 }; 10665 10666 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10667 u8 e[0x1]; 10668 u8 reserved_at_01[0x0b]; 10669 u8 prio[0x04]; 10670 }; 10671 10672 struct mlx5_ifc_qpdpm_reg_bits { 10673 u8 reserved_at_0[0x8]; 10674 u8 local_port[0x8]; 10675 u8 reserved_at_10[0x10]; 10676 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10677 }; 10678 10679 struct mlx5_ifc_qpts_reg_bits { 10680 u8 reserved_at_0[0x8]; 10681 u8 local_port[0x8]; 10682 u8 reserved_at_10[0x2d]; 10683 u8 trust_state[0x3]; 10684 }; 10685 10686 struct mlx5_ifc_mfrl_reg_bits { 10687 u8 reserved_at_0[0x38]; 10688 u8 reset_level[0x8]; 10689 }; 10690 10691 enum { 10692 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP = 0x9009, 10693 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR = 0x9109, 10694 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP = 0x900a, 10695 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE = 0x900b, 10696 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR = 0x900f, 10697 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE = 0x910b, 10698 MLX5_MAX_TEMPERATURE = 16, 10699 }; 10700 10701 struct mlx5_ifc_mtbr_temp_record_bits { 10702 u8 max_temperature[0x10]; 10703 u8 temperature[0x10]; 10704 }; 10705 10706 struct mlx5_ifc_mtbr_reg_bits { 10707 u8 reserved_at_0[0x14]; 10708 u8 base_sensor_index[0xc]; 10709 10710 u8 reserved_at_20[0x18]; 10711 u8 num_rec[0x8]; 10712 10713 u8 reserved_at_40[0x40]; 10714 10715 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 10716 }; 10717 10718 struct mlx5_ifc_mtbr_reg_ext_bits { 10719 u8 reserved_at_0[0x14]; 10720 u8 base_sensor_index[0xc]; 10721 10722 u8 reserved_at_20[0x18]; 10723 u8 num_rec[0x8]; 10724 10725 u8 reserved_at_40[0x40]; 10726 10727 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 10728 }; 10729 10730 struct mlx5_ifc_mtcap_bits { 10731 u8 reserved_at_0[0x19]; 10732 u8 sensor_count[0x7]; 10733 10734 u8 reserved_at_20[0x19]; 10735 u8 internal_sensor_count[0x7]; 10736 10737 u8 sensor_map[0x40]; 10738 }; 10739 10740 struct mlx5_ifc_mtcap_ext_bits { 10741 u8 reserved_at_0[0x19]; 10742 u8 sensor_count[0x7]; 10743 10744 u8 reserved_at_20[0x20]; 10745 10746 u8 sensor_map[0x40]; 10747 }; 10748 10749 struct mlx5_ifc_mtecr_bits { 10750 u8 reserved_at_0[0x4]; 10751 u8 last_sensor[0xc]; 10752 u8 reserved_at_10[0x4]; 10753 u8 sensor_count[0xc]; 10754 10755 u8 reserved_at_20[0x19]; 10756 u8 internal_sensor_count[0x7]; 10757 10758 u8 sensor_map_0[0x20]; 10759 10760 u8 reserved_at_60[0x2a0]; 10761 }; 10762 10763 struct mlx5_ifc_mtecr_ext_bits { 10764 u8 reserved_at_0[0x4]; 10765 u8 last_sensor[0xc]; 10766 u8 reserved_at_10[0x4]; 10767 u8 sensor_count[0xc]; 10768 10769 u8 reserved_at_20[0x20]; 10770 10771 u8 sensor_map_0[0x20]; 10772 10773 u8 reserved_at_60[0x2a0]; 10774 }; 10775 10776 struct mlx5_ifc_mtewe_bits { 10777 u8 reserved_at_0[0x4]; 10778 u8 last_sensor[0xc]; 10779 u8 reserved_at_10[0x4]; 10780 u8 sensor_count[0xc]; 10781 10782 u8 sensor_warning_0[0x20]; 10783 10784 u8 reserved_at_40[0x2a0]; 10785 }; 10786 10787 struct mlx5_ifc_mtewe_ext_bits { 10788 u8 reserved_at_0[0x4]; 10789 u8 last_sensor[0xc]; 10790 u8 reserved_at_10[0x4]; 10791 u8 sensor_count[0xc]; 10792 10793 u8 sensor_warning_0[0x20]; 10794 10795 u8 reserved_at_40[0x2a0]; 10796 }; 10797 10798 struct mlx5_ifc_mtmp_bits { 10799 u8 reserved_at_0[0x14]; 10800 u8 sensor_index[0xc]; 10801 10802 u8 reserved_at_20[0x10]; 10803 u8 temperature[0x10]; 10804 10805 u8 mte[0x1]; 10806 u8 mtr[0x1]; 10807 u8 reserved_at_42[0xe]; 10808 u8 max_temperature[0x10]; 10809 10810 u8 tee[0x2]; 10811 u8 reserved_at_62[0xe]; 10812 u8 temperature_threshold_hi[0x10]; 10813 10814 u8 reserved_at_80[0x10]; 10815 u8 temperature_threshold_lo[0x10]; 10816 10817 u8 reserved_at_a0[0x20]; 10818 10819 u8 sensor_name_hi[0x20]; 10820 10821 u8 sensor_name_lo[0x20]; 10822 }; 10823 10824 struct mlx5_ifc_mtmp_ext_bits { 10825 u8 reserved_at_0[0x14]; 10826 u8 sensor_index[0xc]; 10827 10828 u8 reserved_at_20[0x10]; 10829 u8 temperature[0x10]; 10830 10831 u8 mte[0x1]; 10832 u8 mtr[0x1]; 10833 u8 reserved_at_42[0xe]; 10834 u8 max_temperature[0x10]; 10835 10836 u8 tee[0x2]; 10837 u8 reserved_at_62[0xe]; 10838 u8 temperature_threshold_hi[0x10]; 10839 10840 u8 reserved_at_80[0x10]; 10841 u8 temperature_threshold_lo[0x10]; 10842 10843 u8 reserved_at_a0[0x20]; 10844 10845 u8 sensor_name_hi[0x20]; 10846 10847 u8 sensor_name_lo[0x20]; 10848 }; 10849 10850 #endif /* MLX5_IFC_H */ 10851