1 /*- 2 * Copyright (c) 2013-2020, Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #ifndef MLX5_IFC_H 27 #define MLX5_IFC_H 28 29 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> 30 31 enum { 32 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0, 33 MLX5_EVENT_TYPE_COMP = 0x0, 34 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 35 MLX5_EVENT_TYPE_COMM_EST = 0x2, 36 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 37 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 38 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 39 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 40 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 41 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 42 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 43 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 44 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 45 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 46 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 47 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 48 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 49 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 50 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 51 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 52 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 53 MLX5_EVENT_TYPE_XRQ_ERROR = 0x18, 54 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 55 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 56 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 57 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 58 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 59 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 60 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 61 MLX5_EVENT_TYPE_CMD = 0xa, 62 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 63 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 64 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 65 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 66 MLX5_EVENT_TYPE_CODING_GENERAL_OBJ_EVENT = 0x27, 67 }; 68 69 enum { 70 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 71 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 72 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 73 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 74 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 75 }; 76 77 enum { 78 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 79 }; 80 81 enum { 82 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 83 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 84 }; 85 86 enum { 87 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 88 MLX5_OBJ_TYPE_MKEY = 0xff01, 89 MLX5_OBJ_TYPE_QP = 0xff02, 90 MLX5_OBJ_TYPE_PSV = 0xff03, 91 MLX5_OBJ_TYPE_RMP = 0xff04, 92 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 93 MLX5_OBJ_TYPE_RQ = 0xff06, 94 MLX5_OBJ_TYPE_SQ = 0xff07, 95 MLX5_OBJ_TYPE_TIR = 0xff08, 96 MLX5_OBJ_TYPE_TIS = 0xff09, 97 MLX5_OBJ_TYPE_DCT = 0xff0a, 98 MLX5_OBJ_TYPE_XRQ = 0xff0b, 99 MLX5_OBJ_TYPE_RQT = 0xff0e, 100 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 101 MLX5_OBJ_TYPE_CQ = 0xff10, 102 }; 103 104 enum { 105 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 106 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 107 MLX5_CMD_OP_INIT_HCA = 0x102, 108 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 109 MLX5_CMD_OP_ENABLE_HCA = 0x104, 110 MLX5_CMD_OP_DISABLE_HCA = 0x105, 111 MLX5_CMD_OP_QUERY_PAGES = 0x107, 112 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 113 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 114 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 115 MLX5_CMD_OP_SET_ISSI = 0x10b, 116 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 117 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 118 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 119 MLX5_CMD_OP_CREATE_MKEY = 0x200, 120 MLX5_CMD_OP_QUERY_MKEY = 0x201, 121 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 122 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 123 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 124 MLX5_CMD_OP_CREATE_EQ = 0x301, 125 MLX5_CMD_OP_DESTROY_EQ = 0x302, 126 MLX5_CMD_OP_QUERY_EQ = 0x303, 127 MLX5_CMD_OP_GEN_EQE = 0x304, 128 MLX5_CMD_OP_CREATE_CQ = 0x400, 129 MLX5_CMD_OP_DESTROY_CQ = 0x401, 130 MLX5_CMD_OP_QUERY_CQ = 0x402, 131 MLX5_CMD_OP_MODIFY_CQ = 0x403, 132 MLX5_CMD_OP_CREATE_QP = 0x500, 133 MLX5_CMD_OP_DESTROY_QP = 0x501, 134 MLX5_CMD_OP_RST2INIT_QP = 0x502, 135 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 136 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 137 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 138 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 139 MLX5_CMD_OP_2ERR_QP = 0x507, 140 MLX5_CMD_OP_2RST_QP = 0x50a, 141 MLX5_CMD_OP_QUERY_QP = 0x50b, 142 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 143 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 144 MLX5_CMD_OP_CREATE_PSV = 0x600, 145 MLX5_CMD_OP_DESTROY_PSV = 0x601, 146 MLX5_CMD_OP_CREATE_SRQ = 0x700, 147 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 148 MLX5_CMD_OP_QUERY_SRQ = 0x702, 149 MLX5_CMD_OP_ARM_RQ = 0x703, 150 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 151 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 152 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 153 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 154 MLX5_CMD_OP_CREATE_DCT = 0x710, 155 MLX5_CMD_OP_DESTROY_DCT = 0x711, 156 MLX5_CMD_OP_DRAIN_DCT = 0x712, 157 MLX5_CMD_OP_QUERY_DCT = 0x713, 158 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 159 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 160 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 161 MLX5_CMD_OP_CREATE_XRQ = 0x717, 162 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 163 MLX5_CMD_OP_QUERY_XRQ = 0x719, 164 MLX5_CMD_OP_ARM_XRQ = 0x71a, 165 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 166 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 167 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 168 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 169 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 170 171 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 172 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 173 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 174 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 175 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 176 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 177 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 178 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 179 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 180 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 181 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 182 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 183 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 184 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 185 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 186 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 187 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 188 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 189 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 190 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 191 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 192 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 193 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 194 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 195 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 196 MLX5_CMD_OP_ALLOC_PD = 0x800, 197 MLX5_CMD_OP_DEALLOC_PD = 0x801, 198 MLX5_CMD_OP_ALLOC_UAR = 0x802, 199 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 200 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 201 MLX5_CMD_OP_ACCESS_REG = 0x805, 202 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 203 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 204 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 205 MLX5_CMD_OP_MAD_IFC = 0x50d, 206 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 207 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 208 MLX5_CMD_OP_NOP = 0x80d, 209 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 210 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 211 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 212 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 213 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 214 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 215 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 216 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 217 MLX5_CMD_OP_QUERY_DIAGNOSTIC_PARAMS = 0x819, 218 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 219 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 220 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 221 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 222 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 223 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 224 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 225 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 226 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 227 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 228 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 229 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 230 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 231 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 232 MLX5_CMD_OP_CREATE_LAG = 0x840, 233 MLX5_CMD_OP_MODIFY_LAG = 0x841, 234 MLX5_CMD_OP_QUERY_LAG = 0x842, 235 MLX5_CMD_OP_DESTROY_LAG = 0x843, 236 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 237 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 238 MLX5_CMD_OP_CREATE_TIR = 0x900, 239 MLX5_CMD_OP_MODIFY_TIR = 0x901, 240 MLX5_CMD_OP_DESTROY_TIR = 0x902, 241 MLX5_CMD_OP_QUERY_TIR = 0x903, 242 MLX5_CMD_OP_CREATE_SQ = 0x904, 243 MLX5_CMD_OP_MODIFY_SQ = 0x905, 244 MLX5_CMD_OP_DESTROY_SQ = 0x906, 245 MLX5_CMD_OP_QUERY_SQ = 0x907, 246 MLX5_CMD_OP_CREATE_RQ = 0x908, 247 MLX5_CMD_OP_MODIFY_RQ = 0x909, 248 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 249 MLX5_CMD_OP_QUERY_RQ = 0x90b, 250 MLX5_CMD_OP_CREATE_RMP = 0x90c, 251 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 252 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 253 MLX5_CMD_OP_QUERY_RMP = 0x90f, 254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 255 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 256 MLX5_CMD_OP_CREATE_TIS = 0x912, 257 MLX5_CMD_OP_MODIFY_TIS = 0x913, 258 MLX5_CMD_OP_DESTROY_TIS = 0x914, 259 MLX5_CMD_OP_QUERY_TIS = 0x915, 260 MLX5_CMD_OP_CREATE_RQT = 0x916, 261 MLX5_CMD_OP_MODIFY_RQT = 0x917, 262 MLX5_CMD_OP_DESTROY_RQT = 0x918, 263 MLX5_CMD_OP_QUERY_RQT = 0x919, 264 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 265 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 266 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 267 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 268 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 269 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 270 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 271 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 272 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 273 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 274 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 275 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 276 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 277 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 278 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 279 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 280 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 281 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 282 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 283 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 284 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 285 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 286 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 287 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 288 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 289 MLX5_CMD_OP_CREATE_GENERAL_OBJ = 0xa00, 290 MLX5_CMD_OP_MODIFY_GENERAL_OBJ = 0xa01, 291 MLX5_CMD_OP_QUERY_GENERAL_OBJ = 0xa02, 292 MLX5_CMD_OP_DESTROY_GENERAL_OBJ = 0xa03, 293 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 294 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 295 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 296 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 297 }; 298 299 /* Valid range for general commands that don't work over an object */ 300 enum { 301 MLX5_CMD_OP_GENERAL_START = 0xb00, 302 MLX5_CMD_OP_GENERAL_END = 0xd00, 303 }; 304 305 enum { 306 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 307 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 308 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 309 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 310 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 311 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 312 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 313 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 314 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 315 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 316 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 317 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 318 }; 319 320 enum { 321 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 322 }; 323 324 enum { 325 MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc, 326 }; 327 328 enum { 329 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 330 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 331 }; 332 333 enum { 334 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1, 335 }; 336 337 struct mlx5_ifc_flow_table_fields_supported_bits { 338 u8 outer_dmac[0x1]; 339 u8 outer_smac[0x1]; 340 u8 outer_ether_type[0x1]; 341 u8 outer_ip_version[0x1]; 342 u8 outer_first_prio[0x1]; 343 u8 outer_first_cfi[0x1]; 344 u8 outer_first_vid[0x1]; 345 u8 reserved_1[0x1]; 346 u8 outer_second_prio[0x1]; 347 u8 outer_second_cfi[0x1]; 348 u8 outer_second_vid[0x1]; 349 u8 outer_ipv6_flow_label[0x1]; 350 u8 outer_sip[0x1]; 351 u8 outer_dip[0x1]; 352 u8 outer_frag[0x1]; 353 u8 outer_ip_protocol[0x1]; 354 u8 outer_ip_ecn[0x1]; 355 u8 outer_ip_dscp[0x1]; 356 u8 outer_udp_sport[0x1]; 357 u8 outer_udp_dport[0x1]; 358 u8 outer_tcp_sport[0x1]; 359 u8 outer_tcp_dport[0x1]; 360 u8 outer_tcp_flags[0x1]; 361 u8 outer_gre_protocol[0x1]; 362 u8 outer_gre_key[0x1]; 363 u8 outer_vxlan_vni[0x1]; 364 u8 outer_geneve_vni[0x1]; 365 u8 outer_geneve_oam[0x1]; 366 u8 outer_geneve_protocol_type[0x1]; 367 u8 outer_geneve_opt_len[0x1]; 368 u8 reserved_2[0x1]; 369 u8 source_eswitch_port[0x1]; 370 371 u8 inner_dmac[0x1]; 372 u8 inner_smac[0x1]; 373 u8 inner_ether_type[0x1]; 374 u8 inner_ip_version[0x1]; 375 u8 inner_first_prio[0x1]; 376 u8 inner_first_cfi[0x1]; 377 u8 inner_first_vid[0x1]; 378 u8 reserved_4[0x1]; 379 u8 inner_second_prio[0x1]; 380 u8 inner_second_cfi[0x1]; 381 u8 inner_second_vid[0x1]; 382 u8 inner_ipv6_flow_label[0x1]; 383 u8 inner_sip[0x1]; 384 u8 inner_dip[0x1]; 385 u8 inner_frag[0x1]; 386 u8 inner_ip_protocol[0x1]; 387 u8 inner_ip_ecn[0x1]; 388 u8 inner_ip_dscp[0x1]; 389 u8 inner_udp_sport[0x1]; 390 u8 inner_udp_dport[0x1]; 391 u8 inner_tcp_sport[0x1]; 392 u8 inner_tcp_dport[0x1]; 393 u8 inner_tcp_flags[0x1]; 394 u8 reserved_5[0x9]; 395 396 u8 reserved_6[0x1a]; 397 u8 bth_dst_qp[0x1]; 398 u8 reserved_7[0x4]; 399 u8 source_sqn[0x1]; 400 401 u8 reserved_8[0x20]; 402 }; 403 404 struct mlx5_ifc_eth_discard_cntrs_grp_bits { 405 u8 ingress_general_high[0x20]; 406 407 u8 ingress_general_low[0x20]; 408 409 u8 ingress_policy_engine_high[0x20]; 410 411 u8 ingress_policy_engine_low[0x20]; 412 413 u8 ingress_vlan_membership_high[0x20]; 414 415 u8 ingress_vlan_membership_low[0x20]; 416 417 u8 ingress_tag_frame_type_high[0x20]; 418 419 u8 ingress_tag_frame_type_low[0x20]; 420 421 u8 egress_vlan_membership_high[0x20]; 422 423 u8 egress_vlan_membership_low[0x20]; 424 425 u8 loopback_filter_high[0x20]; 426 427 u8 loopback_filter_low[0x20]; 428 429 u8 egress_general_high[0x20]; 430 431 u8 egress_general_low[0x20]; 432 433 u8 reserved_at_1c0[0x40]; 434 435 u8 egress_hoq_high[0x20]; 436 437 u8 egress_hoq_low[0x20]; 438 439 u8 port_isolation_high[0x20]; 440 441 u8 port_isolation_low[0x20]; 442 443 u8 egress_policy_engine_high[0x20]; 444 445 u8 egress_policy_engine_low[0x20]; 446 447 u8 ingress_tx_link_down_high[0x20]; 448 449 u8 ingress_tx_link_down_low[0x20]; 450 451 u8 egress_stp_filter_high[0x20]; 452 453 u8 egress_stp_filter_low[0x20]; 454 455 u8 egress_hoq_stall_high[0x20]; 456 457 u8 egress_hoq_stall_low[0x20]; 458 459 u8 reserved_at_340[0x440]; 460 }; 461 struct mlx5_ifc_flow_table_prop_layout_bits { 462 u8 ft_support[0x1]; 463 u8 flow_tag[0x1]; 464 u8 flow_counter[0x1]; 465 u8 flow_modify_en[0x1]; 466 u8 modify_root[0x1]; 467 u8 identified_miss_table[0x1]; 468 u8 flow_table_modify[0x1]; 469 u8 encap[0x1]; 470 u8 decap[0x1]; 471 u8 reset_root_to_default[0x1]; 472 u8 reserved_at_a[0x16]; 473 474 u8 reserved_at_20[0x2]; 475 u8 log_max_ft_size[0x6]; 476 u8 reserved_at_28[0x10]; 477 u8 max_ft_level[0x8]; 478 479 u8 reserved_at_40[0x20]; 480 481 u8 reserved_at_60[0x18]; 482 u8 log_max_ft_num[0x8]; 483 484 u8 reserved_at_80[0x10]; 485 u8 log_max_flow_counter[0x8]; 486 u8 log_max_destination[0x8]; 487 488 u8 reserved_at_a0[0x18]; 489 u8 log_max_flow[0x8]; 490 491 u8 reserved_at_c0[0x40]; 492 493 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 494 495 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 496 }; 497 498 struct mlx5_ifc_odp_per_transport_service_cap_bits { 499 u8 send[0x1]; 500 u8 receive[0x1]; 501 u8 write[0x1]; 502 u8 read[0x1]; 503 u8 atomic[0x1]; 504 u8 srq_receive[0x1]; 505 u8 reserved_0[0x1a]; 506 }; 507 508 struct mlx5_ifc_flow_counter_list_bits { 509 u8 reserved_0[0x10]; 510 u8 flow_counter_id[0x10]; 511 512 u8 reserved_1[0x20]; 513 }; 514 515 enum { 516 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 517 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 518 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 519 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 520 }; 521 522 struct mlx5_ifc_dest_format_struct_bits { 523 u8 destination_type[0x8]; 524 u8 destination_id[0x18]; 525 526 u8 reserved_0[0x20]; 527 }; 528 529 struct mlx5_ifc_ipv4_layout_bits { 530 u8 reserved_at_0[0x60]; 531 532 u8 ipv4[0x20]; 533 }; 534 535 struct mlx5_ifc_ipv6_layout_bits { 536 u8 ipv6[16][0x8]; 537 }; 538 539 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 540 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 541 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 542 u8 reserved_at_0[0x80]; 543 }; 544 545 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 546 u8 smac_47_16[0x20]; 547 548 u8 smac_15_0[0x10]; 549 u8 ethertype[0x10]; 550 551 u8 dmac_47_16[0x20]; 552 553 u8 dmac_15_0[0x10]; 554 u8 first_prio[0x3]; 555 u8 first_cfi[0x1]; 556 u8 first_vid[0xc]; 557 558 u8 ip_protocol[0x8]; 559 u8 ip_dscp[0x6]; 560 u8 ip_ecn[0x2]; 561 u8 cvlan_tag[0x1]; 562 u8 svlan_tag[0x1]; 563 u8 frag[0x1]; 564 u8 ip_version[0x4]; 565 u8 tcp_flags[0x9]; 566 567 u8 tcp_sport[0x10]; 568 u8 tcp_dport[0x10]; 569 570 u8 reserved_2[0x20]; 571 572 u8 udp_sport[0x10]; 573 u8 udp_dport[0x10]; 574 575 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 576 577 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 578 }; 579 580 struct mlx5_ifc_fte_match_set_misc_bits { 581 u8 reserved_0[0x8]; 582 u8 source_sqn[0x18]; 583 584 u8 reserved_1[0x10]; 585 u8 source_port[0x10]; 586 587 u8 outer_second_prio[0x3]; 588 u8 outer_second_cfi[0x1]; 589 u8 outer_second_vid[0xc]; 590 u8 inner_second_prio[0x3]; 591 u8 inner_second_cfi[0x1]; 592 u8 inner_second_vid[0xc]; 593 594 u8 outer_second_vlan_tag[0x1]; 595 u8 inner_second_vlan_tag[0x1]; 596 u8 reserved_2[0xe]; 597 u8 gre_protocol[0x10]; 598 599 u8 gre_key_h[0x18]; 600 u8 gre_key_l[0x8]; 601 602 u8 vxlan_vni[0x18]; 603 u8 reserved_3[0x8]; 604 605 u8 geneve_vni[0x18]; 606 u8 reserved4[0x7]; 607 u8 geneve_oam[0x1]; 608 609 u8 reserved_5[0xc]; 610 u8 outer_ipv6_flow_label[0x14]; 611 612 u8 reserved_6[0xc]; 613 u8 inner_ipv6_flow_label[0x14]; 614 615 u8 reserved_7[0xa]; 616 u8 geneve_opt_len[0x6]; 617 u8 geneve_protocol_type[0x10]; 618 619 u8 reserved_8[0x8]; 620 u8 bth_dst_qp[0x18]; 621 622 u8 reserved_9[0xa0]; 623 }; 624 625 struct mlx5_ifc_cmd_pas_bits { 626 u8 pa_h[0x20]; 627 628 u8 pa_l[0x14]; 629 u8 reserved_0[0xc]; 630 }; 631 632 struct mlx5_ifc_uint64_bits { 633 u8 hi[0x20]; 634 635 u8 lo[0x20]; 636 }; 637 638 struct mlx5_ifc_application_prio_entry_bits { 639 u8 reserved_0[0x8]; 640 u8 priority[0x3]; 641 u8 reserved_1[0x2]; 642 u8 sel[0x3]; 643 u8 protocol_id[0x10]; 644 }; 645 646 struct mlx5_ifc_nodnic_ring_doorbell_bits { 647 u8 reserved_0[0x8]; 648 u8 ring_pi[0x10]; 649 u8 reserved_1[0x8]; 650 }; 651 652 enum { 653 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 654 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 655 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 656 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 657 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 658 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 659 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 660 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 661 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 662 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 663 }; 664 665 struct mlx5_ifc_ads_bits { 666 u8 fl[0x1]; 667 u8 free_ar[0x1]; 668 u8 reserved_0[0xe]; 669 u8 pkey_index[0x10]; 670 671 u8 reserved_1[0x8]; 672 u8 grh[0x1]; 673 u8 mlid[0x7]; 674 u8 rlid[0x10]; 675 676 u8 ack_timeout[0x5]; 677 u8 reserved_2[0x3]; 678 u8 src_addr_index[0x8]; 679 u8 log_rtm[0x4]; 680 u8 stat_rate[0x4]; 681 u8 hop_limit[0x8]; 682 683 u8 reserved_3[0x4]; 684 u8 tclass[0x8]; 685 u8 flow_label[0x14]; 686 687 u8 rgid_rip[16][0x8]; 688 689 u8 reserved_4[0x4]; 690 u8 f_dscp[0x1]; 691 u8 f_ecn[0x1]; 692 u8 reserved_5[0x1]; 693 u8 f_eth_prio[0x1]; 694 u8 ecn[0x2]; 695 u8 dscp[0x6]; 696 u8 udp_sport[0x10]; 697 698 u8 dei_cfi[0x1]; 699 u8 eth_prio[0x3]; 700 u8 sl[0x4]; 701 u8 port[0x8]; 702 u8 rmac_47_32[0x10]; 703 704 u8 rmac_31_0[0x20]; 705 }; 706 707 struct mlx5_ifc_diagnostic_counter_cap_bits { 708 u8 sync[0x1]; 709 u8 reserved_0[0xf]; 710 u8 counter_id[0x10]; 711 }; 712 713 struct mlx5_ifc_debug_cap_bits { 714 u8 reserved_0[0x18]; 715 u8 log_max_samples[0x8]; 716 717 u8 single[0x1]; 718 u8 repetitive[0x1]; 719 u8 health_mon_rx_activity[0x1]; 720 u8 reserved_1[0x15]; 721 u8 log_min_sample_period[0x8]; 722 723 u8 reserved_2[0x1c0]; 724 725 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 726 }; 727 728 struct mlx5_ifc_qos_cap_bits { 729 u8 packet_pacing[0x1]; 730 u8 esw_scheduling[0x1]; 731 u8 esw_bw_share[0x1]; 732 u8 esw_rate_limit[0x1]; 733 u8 hll[0x1]; 734 u8 packet_pacing_burst_bound[0x1]; 735 u8 packet_pacing_typical_size[0x1]; 736 u8 reserved_at_7[0x19]; 737 738 u8 reserved_at_20[0xA]; 739 u8 qos_remap_pp[0x1]; 740 u8 reserved_at_2b[0x15]; 741 742 u8 packet_pacing_max_rate[0x20]; 743 744 u8 packet_pacing_min_rate[0x20]; 745 746 u8 reserved_at_80[0x10]; 747 u8 packet_pacing_rate_table_size[0x10]; 748 749 u8 esw_element_type[0x10]; 750 u8 esw_tsar_type[0x10]; 751 752 u8 reserved_at_c0[0x10]; 753 u8 max_qos_para_vport[0x10]; 754 755 u8 max_tsar_bw_share[0x20]; 756 757 u8 reserved_at_100[0x700]; 758 }; 759 760 struct mlx5_ifc_snapshot_cap_bits { 761 u8 reserved_0[0x1d]; 762 u8 suspend_qp_uc[0x1]; 763 u8 suspend_qp_ud[0x1]; 764 u8 suspend_qp_rc[0x1]; 765 766 u8 reserved_1[0x1c]; 767 u8 restore_pd[0x1]; 768 u8 restore_uar[0x1]; 769 u8 restore_mkey[0x1]; 770 u8 restore_qp[0x1]; 771 772 u8 reserved_2[0x1e]; 773 u8 named_mkey[0x1]; 774 u8 named_qp[0x1]; 775 776 u8 reserved_3[0x7a0]; 777 }; 778 779 struct mlx5_ifc_e_switch_cap_bits { 780 u8 vport_svlan_strip[0x1]; 781 u8 vport_cvlan_strip[0x1]; 782 u8 vport_svlan_insert[0x1]; 783 u8 vport_cvlan_insert_if_not_exist[0x1]; 784 u8 vport_cvlan_insert_overwrite[0x1]; 785 786 u8 reserved_0[0x19]; 787 788 u8 nic_vport_node_guid_modify[0x1]; 789 u8 nic_vport_port_guid_modify[0x1]; 790 791 u8 reserved_1[0x7e0]; 792 }; 793 794 struct mlx5_ifc_flow_table_eswitch_cap_bits { 795 u8 reserved_0[0x200]; 796 797 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 798 799 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 800 801 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 802 803 u8 reserved_1[0x7800]; 804 }; 805 806 struct mlx5_ifc_flow_table_nic_cap_bits { 807 u8 nic_rx_multi_path_tirs[0x1]; 808 u8 nic_rx_multi_path_tirs_fts[0x1]; 809 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 810 u8 reserved_at_3[0x1fd]; 811 812 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 813 814 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 815 816 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 817 818 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 819 820 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 821 822 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 823 824 u8 reserved_1[0x7200]; 825 }; 826 827 struct mlx5_ifc_pddr_module_info_bits { 828 u8 cable_technology[0x8]; 829 u8 cable_breakout[0x8]; 830 u8 ext_ethernet_compliance_code[0x8]; 831 u8 ethernet_compliance_code[0x8]; 832 833 u8 cable_type[0x4]; 834 u8 cable_vendor[0x4]; 835 u8 cable_length[0x8]; 836 u8 cable_identifier[0x8]; 837 u8 cable_power_class[0x8]; 838 839 u8 reserved_at_40[0x8]; 840 u8 cable_rx_amp[0x8]; 841 u8 cable_rx_emphasis[0x8]; 842 u8 cable_tx_equalization[0x8]; 843 844 u8 reserved_at_60[0x8]; 845 u8 cable_attenuation_12g[0x8]; 846 u8 cable_attenuation_7g[0x8]; 847 u8 cable_attenuation_5g[0x8]; 848 849 u8 reserved_at_80[0x8]; 850 u8 rx_cdr_cap[0x4]; 851 u8 tx_cdr_cap[0x4]; 852 u8 reserved_at_90[0x4]; 853 u8 rx_cdr_state[0x4]; 854 u8 reserved_at_98[0x4]; 855 u8 tx_cdr_state[0x4]; 856 857 u8 vendor_name[16][0x8]; 858 859 u8 vendor_pn[16][0x8]; 860 861 u8 vendor_rev[0x20]; 862 863 u8 fw_version[0x20]; 864 865 u8 vendor_sn[16][0x8]; 866 867 u8 temperature[0x10]; 868 u8 voltage[0x10]; 869 870 u8 rx_power_lane0[0x10]; 871 u8 rx_power_lane1[0x10]; 872 873 u8 rx_power_lane2[0x10]; 874 u8 rx_power_lane3[0x10]; 875 876 u8 reserved_at_2c0[0x40]; 877 878 u8 tx_power_lane0[0x10]; 879 u8 tx_power_lane1[0x10]; 880 881 u8 tx_power_lane2[0x10]; 882 u8 tx_power_lane3[0x10]; 883 884 u8 reserved_at_340[0x40]; 885 886 u8 tx_bias_lane0[0x10]; 887 u8 tx_bias_lane1[0x10]; 888 889 u8 tx_bias_lane2[0x10]; 890 u8 tx_bias_lane3[0x10]; 891 892 u8 reserved_at_3c0[0x40]; 893 894 u8 temperature_high_th[0x10]; 895 u8 temperature_low_th[0x10]; 896 897 u8 voltage_high_th[0x10]; 898 u8 voltage_low_th[0x10]; 899 900 u8 rx_power_high_th[0x10]; 901 u8 rx_power_low_th[0x10]; 902 903 u8 tx_power_high_th[0x10]; 904 u8 tx_power_low_th[0x10]; 905 906 u8 tx_bias_high_th[0x10]; 907 u8 tx_bias_low_th[0x10]; 908 909 u8 reserved_at_4a0[0x10]; 910 u8 wavelength[0x10]; 911 912 u8 reserved_at_4c0[0x300]; 913 }; 914 915 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 916 u8 csum_cap[0x1]; 917 u8 vlan_cap[0x1]; 918 u8 lro_cap[0x1]; 919 u8 lro_psh_flag[0x1]; 920 u8 lro_time_stamp[0x1]; 921 u8 lro_max_msg_sz_mode[0x2]; 922 u8 wqe_vlan_insert[0x1]; 923 u8 self_lb_en_modifiable[0x1]; 924 u8 self_lb_mc[0x1]; 925 u8 self_lb_uc[0x1]; 926 u8 max_lso_cap[0x5]; 927 u8 multi_pkt_send_wqe[0x2]; 928 u8 wqe_inline_mode[0x2]; 929 u8 rss_ind_tbl_cap[0x4]; 930 u8 reg_umr_sq[0x1]; 931 u8 scatter_fcs[0x1]; 932 u8 enhanced_multi_pkt_send_wqe[0x1]; 933 u8 tunnel_lso_const_out_ip_id[0x1]; 934 u8 tunnel_lro_gre[0x1]; 935 u8 tunnel_lro_vxlan[0x1]; 936 u8 tunnel_statless_gre[0x1]; 937 u8 tunnel_stateless_vxlan[0x1]; 938 939 u8 swp[0x1]; 940 u8 swp_csum[0x1]; 941 u8 swp_lso[0x1]; 942 u8 reserved_2[0x1b]; 943 u8 max_geneve_opt_len[0x1]; 944 u8 tunnel_stateless_geneve_rx[0x1]; 945 946 u8 reserved_3[0x10]; 947 u8 lro_min_mss_size[0x10]; 948 949 u8 reserved_4[0x120]; 950 951 u8 lro_timer_supported_periods[4][0x20]; 952 953 u8 reserved_5[0x600]; 954 }; 955 956 enum { 957 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 958 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 959 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 960 }; 961 962 enum { 963 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 964 MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 965 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 966 }; 967 968 struct mlx5_ifc_roce_cap_bits { 969 u8 roce_apm[0x1]; 970 u8 rts2rts_primary_eth_prio[0x1]; 971 u8 roce_rx_allow_untagged[0x1]; 972 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 973 u8 reserved_at_4[0x1a]; 974 u8 qp_ts_format[0x2]; 975 976 u8 reserved_1[0x60]; 977 978 u8 reserved_2[0xc]; 979 u8 l3_type[0x4]; 980 u8 reserved_3[0x8]; 981 u8 roce_version[0x8]; 982 983 u8 reserved_4[0x10]; 984 u8 r_roce_dest_udp_port[0x10]; 985 986 u8 r_roce_max_src_udp_port[0x10]; 987 u8 r_roce_min_src_udp_port[0x10]; 988 989 u8 reserved_5[0x10]; 990 u8 roce_address_table_size[0x10]; 991 992 u8 reserved_6[0x700]; 993 }; 994 995 struct mlx5_ifc_device_event_cap_bits { 996 u8 user_affiliated_events[4][0x40]; 997 998 u8 user_unaffiliated_events[4][0x40]; 999 }; 1000 1001 enum { 1002 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 1003 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1004 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1005 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1006 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1007 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1008 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1009 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1010 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1011 }; 1012 1013 enum { 1014 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1015 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1016 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1017 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1018 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1019 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1020 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1021 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1022 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1023 }; 1024 1025 struct mlx5_ifc_atomic_caps_bits { 1026 u8 reserved_0[0x40]; 1027 1028 u8 atomic_req_8B_endianess_mode[0x2]; 1029 u8 reserved_1[0x4]; 1030 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 1031 1032 u8 reserved_2[0x19]; 1033 1034 u8 reserved_3[0x20]; 1035 1036 u8 reserved_4[0x10]; 1037 u8 atomic_operations[0x10]; 1038 1039 u8 reserved_5[0x10]; 1040 u8 atomic_size_qp[0x10]; 1041 1042 u8 reserved_6[0x10]; 1043 u8 atomic_size_dc[0x10]; 1044 1045 u8 reserved_7[0x720]; 1046 }; 1047 1048 struct mlx5_ifc_odp_cap_bits { 1049 u8 reserved_0[0x40]; 1050 1051 u8 sig[0x1]; 1052 u8 reserved_1[0x1f]; 1053 1054 u8 reserved_2[0x20]; 1055 1056 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1057 1058 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1059 1060 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1061 1062 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1063 1064 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1065 1066 u8 reserved_3[0x6e0]; 1067 }; 1068 1069 enum { 1070 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1071 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1072 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1073 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1074 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1075 }; 1076 1077 enum { 1078 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1079 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1080 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1081 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1082 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1083 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1084 }; 1085 1086 enum { 1087 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1088 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1089 }; 1090 1091 enum { 1092 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1093 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1094 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1095 }; 1096 1097 enum { 1098 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1099 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1100 }; 1101 1102 enum { 1103 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1104 MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1105 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1106 }; 1107 1108 enum { 1109 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1110 MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1111 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1112 }; 1113 1114 struct mlx5_ifc_cmd_hca_cap_bits { 1115 u8 reserved_0[0x80]; 1116 1117 u8 log_max_srq_sz[0x8]; 1118 u8 log_max_qp_sz[0x8]; 1119 u8 event_cap[0x1]; 1120 u8 reserved_1[0xa]; 1121 u8 log_max_qp[0x5]; 1122 1123 u8 reserved_2[0xb]; 1124 u8 log_max_srq[0x5]; 1125 u8 reserved_3[0x10]; 1126 1127 u8 reserved_4[0x8]; 1128 u8 log_max_cq_sz[0x8]; 1129 u8 relaxed_ordering_write_umr[0x1]; 1130 u8 relaxed_ordering_read_umr[0x1]; 1131 u8 reserved_5[0x9]; 1132 u8 log_max_cq[0x5]; 1133 1134 u8 log_max_eq_sz[0x8]; 1135 u8 relaxed_ordering_write[0x1]; 1136 u8 relaxed_ordering_read[0x1]; 1137 u8 log_max_mkey[0x6]; 1138 u8 reserved_7[0xb]; 1139 u8 fast_teardown[0x1]; 1140 u8 log_max_eq[0x4]; 1141 1142 u8 max_indirection[0x8]; 1143 u8 reserved_8[0x1]; 1144 u8 log_max_mrw_sz[0x7]; 1145 u8 force_teardown[0x1]; 1146 u8 reserved_9[0x1]; 1147 u8 log_max_bsf_list_size[0x6]; 1148 u8 reserved_10[0x2]; 1149 u8 log_max_klm_list_size[0x6]; 1150 1151 u8 reserved_11[0xa]; 1152 u8 log_max_ra_req_dc[0x6]; 1153 u8 reserved_12[0xa]; 1154 u8 log_max_ra_res_dc[0x6]; 1155 1156 u8 reserved_13[0xa]; 1157 u8 log_max_ra_req_qp[0x6]; 1158 u8 reserved_14[0xa]; 1159 u8 log_max_ra_res_qp[0x6]; 1160 1161 u8 pad_cap[0x1]; 1162 u8 cc_query_allowed[0x1]; 1163 u8 cc_modify_allowed[0x1]; 1164 u8 start_pad[0x1]; 1165 u8 cache_line_128byte[0x1]; 1166 u8 reserved_at_165[0xa]; 1167 u8 qcam_reg[0x1]; 1168 u8 gid_table_size[0x10]; 1169 1170 u8 out_of_seq_cnt[0x1]; 1171 u8 vport_counters[0x1]; 1172 u8 retransmission_q_counters[0x1]; 1173 u8 debug[0x1]; 1174 u8 modify_rq_counters_set_id[0x1]; 1175 u8 rq_delay_drop[0x1]; 1176 u8 max_qp_cnt[0xa]; 1177 u8 pkey_table_size[0x10]; 1178 1179 u8 vport_group_manager[0x1]; 1180 u8 vhca_group_manager[0x1]; 1181 u8 ib_virt[0x1]; 1182 u8 eth_virt[0x1]; 1183 u8 reserved_17[0x1]; 1184 u8 ets[0x1]; 1185 u8 nic_flow_table[0x1]; 1186 u8 eswitch_flow_table[0x1]; 1187 u8 reserved_18[0x1]; 1188 u8 mcam_reg[0x1]; 1189 u8 pcam_reg[0x1]; 1190 u8 local_ca_ack_delay[0x5]; 1191 u8 port_module_event[0x1]; 1192 u8 reserved_19[0x5]; 1193 u8 port_type[0x2]; 1194 u8 num_ports[0x8]; 1195 1196 u8 snapshot[0x1]; 1197 u8 reserved_20[0x2]; 1198 u8 log_max_msg[0x5]; 1199 u8 reserved_21[0x4]; 1200 u8 max_tc[0x4]; 1201 u8 temp_warn_event[0x1]; 1202 u8 dcbx[0x1]; 1203 u8 general_notification_event[0x1]; 1204 u8 reserved_at_1d3[0x2]; 1205 u8 fpga[0x1]; 1206 u8 rol_s[0x1]; 1207 u8 rol_g[0x1]; 1208 u8 reserved_23[0x1]; 1209 u8 wol_s[0x1]; 1210 u8 wol_g[0x1]; 1211 u8 wol_a[0x1]; 1212 u8 wol_b[0x1]; 1213 u8 wol_m[0x1]; 1214 u8 wol_u[0x1]; 1215 u8 wol_p[0x1]; 1216 1217 u8 stat_rate_support[0x10]; 1218 u8 reserved_24[0xc]; 1219 u8 cqe_version[0x4]; 1220 1221 u8 compact_address_vector[0x1]; 1222 u8 striding_rq[0x1]; 1223 u8 reserved_25[0x1]; 1224 u8 ipoib_enhanced_offloads[0x1]; 1225 u8 ipoib_ipoib_offloads[0x1]; 1226 u8 reserved_26[0x8]; 1227 u8 dc_connect_qp[0x1]; 1228 u8 dc_cnak_trace[0x1]; 1229 u8 drain_sigerr[0x1]; 1230 u8 cmdif_checksum[0x2]; 1231 u8 sigerr_cqe[0x1]; 1232 u8 reserved_27[0x1]; 1233 u8 wq_signature[0x1]; 1234 u8 sctr_data_cqe[0x1]; 1235 u8 reserved_28[0x1]; 1236 u8 sho[0x1]; 1237 u8 tph[0x1]; 1238 u8 rf[0x1]; 1239 u8 dct[0x1]; 1240 u8 qos[0x1]; 1241 u8 eth_net_offloads[0x1]; 1242 u8 roce[0x1]; 1243 u8 atomic[0x1]; 1244 u8 reserved_30[0x1]; 1245 1246 u8 cq_oi[0x1]; 1247 u8 cq_resize[0x1]; 1248 u8 cq_moderation[0x1]; 1249 u8 cq_period_mode_modify[0x1]; 1250 u8 cq_invalidate[0x1]; 1251 u8 reserved_at_225[0x1]; 1252 u8 cq_eq_remap[0x1]; 1253 u8 pg[0x1]; 1254 u8 block_lb_mc[0x1]; 1255 u8 exponential_backoff[0x1]; 1256 u8 scqe_break_moderation[0x1]; 1257 u8 cq_period_start_from_cqe[0x1]; 1258 u8 cd[0x1]; 1259 u8 atm[0x1]; 1260 u8 apm[0x1]; 1261 u8 imaicl[0x1]; 1262 u8 reserved_32[0x6]; 1263 u8 qkv[0x1]; 1264 u8 pkv[0x1]; 1265 u8 set_deth_sqpn[0x1]; 1266 u8 reserved_33[0x3]; 1267 u8 xrc[0x1]; 1268 u8 ud[0x1]; 1269 u8 uc[0x1]; 1270 u8 rc[0x1]; 1271 1272 u8 uar_4k[0x1]; 1273 u8 reserved_at_241[0x9]; 1274 u8 uar_sz[0x6]; 1275 u8 reserved_35[0x8]; 1276 u8 log_pg_sz[0x8]; 1277 1278 u8 bf[0x1]; 1279 u8 driver_version[0x1]; 1280 u8 pad_tx_eth_packet[0x1]; 1281 u8 reserved_36[0x8]; 1282 u8 log_bf_reg_size[0x5]; 1283 u8 reserved_37[0x10]; 1284 1285 u8 num_of_diagnostic_counters[0x10]; 1286 u8 max_wqe_sz_sq[0x10]; 1287 1288 u8 reserved_38[0x10]; 1289 u8 max_wqe_sz_rq[0x10]; 1290 1291 u8 reserved_39[0x10]; 1292 u8 max_wqe_sz_sq_dc[0x10]; 1293 1294 u8 reserved_40[0x7]; 1295 u8 max_qp_mcg[0x19]; 1296 1297 u8 reserved_41[0x18]; 1298 u8 log_max_mcg[0x8]; 1299 1300 u8 reserved_42[0x3]; 1301 u8 log_max_transport_domain[0x5]; 1302 u8 reserved_43[0x3]; 1303 u8 log_max_pd[0x5]; 1304 u8 reserved_44[0xb]; 1305 u8 log_max_xrcd[0x5]; 1306 1307 u8 nic_receive_steering_discard[0x1]; 1308 u8 reserved_45[0x7]; 1309 u8 log_max_flow_counter_bulk[0x8]; 1310 u8 max_flow_counter[0x10]; 1311 1312 u8 reserved_46[0x3]; 1313 u8 log_max_rq[0x5]; 1314 u8 reserved_47[0x3]; 1315 u8 log_max_sq[0x5]; 1316 u8 reserved_48[0x3]; 1317 u8 log_max_tir[0x5]; 1318 u8 reserved_49[0x3]; 1319 u8 log_max_tis[0x5]; 1320 1321 u8 basic_cyclic_rcv_wqe[0x1]; 1322 u8 reserved_50[0x2]; 1323 u8 log_max_rmp[0x5]; 1324 u8 reserved_51[0x3]; 1325 u8 log_max_rqt[0x5]; 1326 u8 reserved_52[0x3]; 1327 u8 log_max_rqt_size[0x5]; 1328 u8 reserved_53[0x3]; 1329 u8 log_max_tis_per_sq[0x5]; 1330 1331 u8 reserved_54[0x3]; 1332 u8 log_max_stride_sz_rq[0x5]; 1333 u8 reserved_55[0x3]; 1334 u8 log_min_stride_sz_rq[0x5]; 1335 u8 reserved_56[0x3]; 1336 u8 log_max_stride_sz_sq[0x5]; 1337 u8 reserved_57[0x3]; 1338 u8 log_min_stride_sz_sq[0x5]; 1339 1340 u8 reserved_58[0x1b]; 1341 u8 log_max_wq_sz[0x5]; 1342 1343 u8 nic_vport_change_event[0x1]; 1344 u8 disable_local_lb_uc[0x1]; 1345 u8 disable_local_lb_mc[0x1]; 1346 u8 reserved_59[0x8]; 1347 u8 log_max_vlan_list[0x5]; 1348 u8 reserved_60[0x3]; 1349 u8 log_max_current_mc_list[0x5]; 1350 u8 reserved_61[0x3]; 1351 u8 log_max_current_uc_list[0x5]; 1352 1353 u8 general_obj_types[0x40]; 1354 1355 u8 sq_ts_format[0x2]; 1356 u8 rq_ts_format[0x2]; 1357 u8 reserved_at_444[0x4]; 1358 u8 create_qp_start_hint[0x18]; 1359 1360 u8 reserved_at_460[0x3]; 1361 u8 log_max_uctx[0x5]; 1362 u8 reserved_at_468[0x3]; 1363 u8 log_max_umem[0x5]; 1364 u8 max_num_eqs[0x10]; 1365 1366 u8 reserved_at_480[0x1]; 1367 u8 tls_tx[0x1]; 1368 u8 tls_rx[0x1]; 1369 u8 log_max_l2_table[0x5]; 1370 u8 reserved_64[0x8]; 1371 u8 log_uar_page_sz[0x10]; 1372 1373 u8 reserved_65[0x20]; 1374 1375 u8 device_frequency_mhz[0x20]; 1376 1377 u8 device_frequency_khz[0x20]; 1378 1379 u8 reserved_at_500[0x20]; 1380 u8 num_of_uars_per_page[0x20]; 1381 u8 reserved_at_540[0x40]; 1382 1383 u8 log_max_atomic_size_qp[0x8]; 1384 u8 reserved_67[0x10]; 1385 u8 log_max_atomic_size_dc[0x8]; 1386 1387 u8 reserved_at_5a0[0x13]; 1388 u8 log_max_dek[0x5]; 1389 u8 reserved_at_5b8[0x4]; 1390 u8 mini_cqe_resp_stride_index[0x1]; 1391 u8 cqe_128_always[0x1]; 1392 u8 cqe_compression_128b[0x1]; 1393 1394 u8 cqe_compression[0x1]; 1395 1396 u8 cqe_compression_timeout[0x10]; 1397 u8 cqe_compression_max_num[0x10]; 1398 1399 u8 reserved_5e0[0xc0]; 1400 1401 u8 uctx_cap[0x20]; 1402 1403 u8 reserved_6c0[0xc0]; 1404 1405 u8 vhca_tunnel_commands[0x40]; 1406 u8 reserved_at_7c0[0x40]; 1407 }; 1408 1409 enum mlx5_flow_destination_type { 1410 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1411 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1412 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1413 }; 1414 1415 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1416 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1417 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1418 u8 reserved_0[0x40]; 1419 }; 1420 1421 struct mlx5_ifc_fte_match_param_bits { 1422 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1423 1424 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1425 1426 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1427 1428 u8 reserved_0[0xa00]; 1429 }; 1430 1431 enum { 1432 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1433 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1434 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1435 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1436 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1437 }; 1438 1439 struct mlx5_ifc_rx_hash_field_select_bits { 1440 u8 l3_prot_type[0x1]; 1441 u8 l4_prot_type[0x1]; 1442 u8 selected_fields[0x1e]; 1443 }; 1444 1445 struct mlx5_ifc_tls_capabilities_bits { 1446 u8 tls_1_2_aes_gcm_128[0x1]; 1447 u8 tls_1_3_aes_gcm_128[0x1]; 1448 u8 tls_1_2_aes_gcm_256[0x1]; 1449 u8 tls_1_3_aes_gcm_256[0x1]; 1450 u8 reserved_at_4[0x1c]; 1451 1452 u8 reserved_at_20[0x7e0]; 1453 }; 1454 1455 enum { 1456 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1457 MLX5_WQ_TYPE_CYCLIC = 0x1, 1458 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1459 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1460 }; 1461 1462 enum rq_type { 1463 RQ_TYPE_NONE, 1464 RQ_TYPE_STRIDE, 1465 }; 1466 1467 enum { 1468 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1469 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1470 }; 1471 1472 struct mlx5_ifc_wq_bits { 1473 u8 wq_type[0x4]; 1474 u8 wq_signature[0x1]; 1475 u8 end_padding_mode[0x2]; 1476 u8 cd_slave[0x1]; 1477 u8 reserved_0[0x18]; 1478 1479 u8 hds_skip_first_sge[0x1]; 1480 u8 log2_hds_buf_size[0x3]; 1481 u8 reserved_1[0x7]; 1482 u8 page_offset[0x5]; 1483 u8 lwm[0x10]; 1484 1485 u8 reserved_2[0x8]; 1486 u8 pd[0x18]; 1487 1488 u8 reserved_3[0x8]; 1489 u8 uar_page[0x18]; 1490 1491 u8 dbr_addr[0x40]; 1492 1493 u8 hw_counter[0x20]; 1494 1495 u8 sw_counter[0x20]; 1496 1497 u8 reserved_4[0xc]; 1498 u8 log_wq_stride[0x4]; 1499 u8 reserved_5[0x3]; 1500 u8 log_wq_pg_sz[0x5]; 1501 u8 reserved_6[0x3]; 1502 u8 log_wq_sz[0x5]; 1503 1504 u8 dbr_umem_valid[0x1]; 1505 u8 wq_umem_valid[0x1]; 1506 u8 reserved_7[0x13]; 1507 u8 single_wqe_log_num_of_strides[0x3]; 1508 u8 two_byte_shift_en[0x1]; 1509 u8 reserved_8[0x4]; 1510 u8 single_stride_log_num_of_bytes[0x3]; 1511 1512 u8 reserved_9[0x4c0]; 1513 1514 struct mlx5_ifc_cmd_pas_bits pas[0]; 1515 }; 1516 1517 struct mlx5_ifc_rq_num_bits { 1518 u8 reserved_0[0x8]; 1519 u8 rq_num[0x18]; 1520 }; 1521 1522 struct mlx5_ifc_mac_address_layout_bits { 1523 u8 reserved_0[0x10]; 1524 u8 mac_addr_47_32[0x10]; 1525 1526 u8 mac_addr_31_0[0x20]; 1527 }; 1528 1529 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1530 u8 reserved_0[0xa0]; 1531 1532 u8 min_time_between_cnps[0x20]; 1533 1534 u8 reserved_1[0x12]; 1535 u8 cnp_dscp[0x6]; 1536 u8 reserved_2[0x4]; 1537 u8 cnp_prio_mode[0x1]; 1538 u8 cnp_802p_prio[0x3]; 1539 1540 u8 reserved_3[0x720]; 1541 }; 1542 1543 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1544 u8 reserved_0[0x60]; 1545 1546 u8 reserved_1[0x4]; 1547 u8 clamp_tgt_rate[0x1]; 1548 u8 reserved_2[0x3]; 1549 u8 clamp_tgt_rate_after_time_inc[0x1]; 1550 u8 reserved_3[0x17]; 1551 1552 u8 reserved_4[0x20]; 1553 1554 u8 rpg_time_reset[0x20]; 1555 1556 u8 rpg_byte_reset[0x20]; 1557 1558 u8 rpg_threshold[0x20]; 1559 1560 u8 rpg_max_rate[0x20]; 1561 1562 u8 rpg_ai_rate[0x20]; 1563 1564 u8 rpg_hai_rate[0x20]; 1565 1566 u8 rpg_gd[0x20]; 1567 1568 u8 rpg_min_dec_fac[0x20]; 1569 1570 u8 rpg_min_rate[0x20]; 1571 1572 u8 reserved_5[0xe0]; 1573 1574 u8 rate_to_set_on_first_cnp[0x20]; 1575 1576 u8 dce_tcp_g[0x20]; 1577 1578 u8 dce_tcp_rtt[0x20]; 1579 1580 u8 rate_reduce_monitor_period[0x20]; 1581 1582 u8 reserved_6[0x20]; 1583 1584 u8 initial_alpha_value[0x20]; 1585 1586 u8 reserved_7[0x4a0]; 1587 }; 1588 1589 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1590 u8 reserved_0[0x80]; 1591 1592 u8 rppp_max_rps[0x20]; 1593 1594 u8 rpg_time_reset[0x20]; 1595 1596 u8 rpg_byte_reset[0x20]; 1597 1598 u8 rpg_threshold[0x20]; 1599 1600 u8 rpg_max_rate[0x20]; 1601 1602 u8 rpg_ai_rate[0x20]; 1603 1604 u8 rpg_hai_rate[0x20]; 1605 1606 u8 rpg_gd[0x20]; 1607 1608 u8 rpg_min_dec_fac[0x20]; 1609 1610 u8 rpg_min_rate[0x20]; 1611 1612 u8 reserved_1[0x640]; 1613 }; 1614 1615 enum { 1616 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1617 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1618 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1619 }; 1620 1621 struct mlx5_ifc_resize_field_select_bits { 1622 u8 resize_field_select[0x20]; 1623 }; 1624 1625 enum { 1626 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1627 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1628 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1629 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1630 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1631 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1632 }; 1633 1634 struct mlx5_ifc_modify_field_select_bits { 1635 u8 modify_field_select[0x20]; 1636 }; 1637 1638 struct mlx5_ifc_field_select_r_roce_np_bits { 1639 u8 field_select_r_roce_np[0x20]; 1640 }; 1641 1642 enum { 1643 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1644 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1645 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1646 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1647 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1648 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1649 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1650 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1651 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1652 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1653 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1654 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1655 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1656 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1657 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1658 }; 1659 1660 struct mlx5_ifc_field_select_r_roce_rp_bits { 1661 u8 field_select_r_roce_rp[0x20]; 1662 }; 1663 1664 enum { 1665 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1666 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1667 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1668 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1669 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1670 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1671 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1672 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1673 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1674 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1675 }; 1676 1677 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1678 u8 field_select_8021qaurp[0x20]; 1679 }; 1680 1681 struct mlx5_ifc_pptb_reg_bits { 1682 u8 reserved_at_0[0x2]; 1683 u8 mm[0x2]; 1684 u8 reserved_at_4[0x4]; 1685 u8 local_port[0x8]; 1686 u8 reserved_at_10[0x6]; 1687 u8 cm[0x1]; 1688 u8 um[0x1]; 1689 u8 pm[0x8]; 1690 1691 u8 prio_x_buff[0x20]; 1692 1693 u8 pm_msb[0x8]; 1694 u8 reserved_at_48[0x10]; 1695 u8 ctrl_buff[0x4]; 1696 u8 untagged_buff[0x4]; 1697 }; 1698 1699 struct mlx5_ifc_dcbx_app_reg_bits { 1700 u8 reserved_0[0x8]; 1701 u8 port_number[0x8]; 1702 u8 reserved_1[0x10]; 1703 1704 u8 reserved_2[0x1a]; 1705 u8 num_app_prio[0x6]; 1706 1707 u8 reserved_3[0x40]; 1708 1709 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1710 }; 1711 1712 struct mlx5_ifc_dcbx_param_reg_bits { 1713 u8 dcbx_cee_cap[0x1]; 1714 u8 dcbx_ieee_cap[0x1]; 1715 u8 dcbx_standby_cap[0x1]; 1716 u8 reserved_0[0x5]; 1717 u8 port_number[0x8]; 1718 u8 reserved_1[0xa]; 1719 u8 max_application_table_size[0x6]; 1720 1721 u8 reserved_2[0x15]; 1722 u8 version_oper[0x3]; 1723 u8 reserved_3[0x5]; 1724 u8 version_admin[0x3]; 1725 1726 u8 willing_admin[0x1]; 1727 u8 reserved_4[0x3]; 1728 u8 pfc_cap_oper[0x4]; 1729 u8 reserved_5[0x4]; 1730 u8 pfc_cap_admin[0x4]; 1731 u8 reserved_6[0x4]; 1732 u8 num_of_tc_oper[0x4]; 1733 u8 reserved_7[0x4]; 1734 u8 num_of_tc_admin[0x4]; 1735 1736 u8 remote_willing[0x1]; 1737 u8 reserved_8[0x3]; 1738 u8 remote_pfc_cap[0x4]; 1739 u8 reserved_9[0x14]; 1740 u8 remote_num_of_tc[0x4]; 1741 1742 u8 reserved_10[0x18]; 1743 u8 error[0x8]; 1744 1745 u8 reserved_11[0x160]; 1746 }; 1747 1748 struct mlx5_ifc_qhll_bits { 1749 u8 reserved_at_0[0x8]; 1750 u8 local_port[0x8]; 1751 u8 reserved_at_10[0x10]; 1752 1753 u8 reserved_at_20[0x1b]; 1754 u8 hll_time[0x5]; 1755 1756 u8 stall_en[0x1]; 1757 u8 reserved_at_41[0x1c]; 1758 u8 stall_cnt[0x3]; 1759 }; 1760 1761 struct mlx5_ifc_qetcr_reg_bits { 1762 u8 operation_type[0x2]; 1763 u8 cap_local_admin[0x1]; 1764 u8 cap_remote_admin[0x1]; 1765 u8 reserved_0[0x4]; 1766 u8 port_number[0x8]; 1767 u8 reserved_1[0x10]; 1768 1769 u8 reserved_2[0x20]; 1770 1771 u8 tc[8][0x40]; 1772 1773 u8 global_configuration[0x40]; 1774 }; 1775 1776 struct mlx5_ifc_nodnic_ring_config_reg_bits { 1777 u8 queue_address_63_32[0x20]; 1778 1779 u8 queue_address_31_12[0x14]; 1780 u8 reserved_0[0x6]; 1781 u8 log_size[0x6]; 1782 1783 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1784 1785 u8 reserved_1[0x8]; 1786 u8 queue_number[0x18]; 1787 1788 u8 q_key[0x20]; 1789 1790 u8 reserved_2[0x10]; 1791 u8 pkey_index[0x10]; 1792 1793 u8 reserved_3[0x40]; 1794 }; 1795 1796 struct mlx5_ifc_nodnic_cq_arming_word_bits { 1797 u8 reserved_0[0x8]; 1798 u8 cq_ci[0x10]; 1799 u8 reserved_1[0x8]; 1800 }; 1801 1802 enum { 1803 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1804 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1805 }; 1806 1807 enum { 1808 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1809 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1810 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1811 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1812 }; 1813 1814 struct mlx5_ifc_nodnic_event_word_bits { 1815 u8 driver_reset_needed[0x1]; 1816 u8 port_management_change_event[0x1]; 1817 u8 reserved_0[0x19]; 1818 u8 link_type[0x1]; 1819 u8 port_state[0x4]; 1820 }; 1821 1822 struct mlx5_ifc_nic_vport_change_event_bits { 1823 u8 reserved_0[0x10]; 1824 u8 vport_num[0x10]; 1825 1826 u8 reserved_1[0xc0]; 1827 }; 1828 1829 struct mlx5_ifc_pages_req_event_bits { 1830 u8 reserved_0[0x10]; 1831 u8 function_id[0x10]; 1832 1833 u8 num_pages[0x20]; 1834 1835 u8 reserved_1[0xa0]; 1836 }; 1837 1838 struct mlx5_ifc_cmd_inter_comp_event_bits { 1839 u8 command_completion_vector[0x20]; 1840 1841 u8 reserved_0[0xc0]; 1842 }; 1843 1844 struct mlx5_ifc_stall_vl_event_bits { 1845 u8 reserved_0[0x18]; 1846 u8 port_num[0x1]; 1847 u8 reserved_1[0x3]; 1848 u8 vl[0x4]; 1849 1850 u8 reserved_2[0xa0]; 1851 }; 1852 1853 struct mlx5_ifc_db_bf_congestion_event_bits { 1854 u8 event_subtype[0x8]; 1855 u8 reserved_0[0x8]; 1856 u8 congestion_level[0x8]; 1857 u8 reserved_1[0x8]; 1858 1859 u8 reserved_2[0xa0]; 1860 }; 1861 1862 struct mlx5_ifc_gpio_event_bits { 1863 u8 reserved_0[0x60]; 1864 1865 u8 gpio_event_hi[0x20]; 1866 1867 u8 gpio_event_lo[0x20]; 1868 1869 u8 reserved_1[0x40]; 1870 }; 1871 1872 struct mlx5_ifc_port_state_change_event_bits { 1873 u8 reserved_0[0x40]; 1874 1875 u8 port_num[0x4]; 1876 u8 reserved_1[0x1c]; 1877 1878 u8 reserved_2[0x80]; 1879 }; 1880 1881 struct mlx5_ifc_dropped_packet_logged_bits { 1882 u8 reserved_0[0xe0]; 1883 }; 1884 1885 enum { 1886 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1887 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1888 }; 1889 1890 struct mlx5_ifc_cq_error_bits { 1891 u8 reserved_0[0x8]; 1892 u8 cqn[0x18]; 1893 1894 u8 reserved_1[0x20]; 1895 1896 u8 reserved_2[0x18]; 1897 u8 syndrome[0x8]; 1898 1899 u8 reserved_3[0x80]; 1900 }; 1901 1902 struct mlx5_ifc_rdma_page_fault_event_bits { 1903 u8 bytes_commited[0x20]; 1904 1905 u8 r_key[0x20]; 1906 1907 u8 reserved_0[0x10]; 1908 u8 packet_len[0x10]; 1909 1910 u8 rdma_op_len[0x20]; 1911 1912 u8 rdma_va[0x40]; 1913 1914 u8 reserved_1[0x5]; 1915 u8 rdma[0x1]; 1916 u8 write[0x1]; 1917 u8 requestor[0x1]; 1918 u8 qp_number[0x18]; 1919 }; 1920 1921 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1922 u8 bytes_committed[0x20]; 1923 1924 u8 reserved_0[0x10]; 1925 u8 wqe_index[0x10]; 1926 1927 u8 reserved_1[0x10]; 1928 u8 len[0x10]; 1929 1930 u8 reserved_2[0x60]; 1931 1932 u8 reserved_3[0x5]; 1933 u8 rdma[0x1]; 1934 u8 write_read[0x1]; 1935 u8 requestor[0x1]; 1936 u8 qpn[0x18]; 1937 }; 1938 1939 enum { 1940 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1941 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1942 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1943 }; 1944 1945 struct mlx5_ifc_qp_events_bits { 1946 u8 reserved_0[0xa0]; 1947 1948 u8 type[0x8]; 1949 u8 reserved_1[0x18]; 1950 1951 u8 reserved_2[0x8]; 1952 u8 qpn_rqn_sqn[0x18]; 1953 }; 1954 1955 struct mlx5_ifc_dct_events_bits { 1956 u8 reserved_0[0xc0]; 1957 1958 u8 reserved_1[0x8]; 1959 u8 dct_number[0x18]; 1960 }; 1961 1962 struct mlx5_ifc_comp_event_bits { 1963 u8 reserved_0[0xc0]; 1964 1965 u8 reserved_1[0x8]; 1966 u8 cq_number[0x18]; 1967 }; 1968 1969 struct mlx5_ifc_fw_version_bits { 1970 u8 major[0x10]; 1971 u8 reserved_0[0x10]; 1972 1973 u8 minor[0x10]; 1974 u8 subminor[0x10]; 1975 1976 u8 second[0x8]; 1977 u8 minute[0x8]; 1978 u8 hour[0x8]; 1979 u8 reserved_1[0x8]; 1980 1981 u8 year[0x10]; 1982 u8 month[0x8]; 1983 u8 day[0x8]; 1984 }; 1985 1986 enum { 1987 MLX5_QPC_STATE_RST = 0x0, 1988 MLX5_QPC_STATE_INIT = 0x1, 1989 MLX5_QPC_STATE_RTR = 0x2, 1990 MLX5_QPC_STATE_RTS = 0x3, 1991 MLX5_QPC_STATE_SQER = 0x4, 1992 MLX5_QPC_STATE_SQD = 0x5, 1993 MLX5_QPC_STATE_ERR = 0x6, 1994 MLX5_QPC_STATE_SUSPENDED = 0x9, 1995 }; 1996 1997 enum { 1998 MLX5_QPC_ST_RC = 0x0, 1999 MLX5_QPC_ST_UC = 0x1, 2000 MLX5_QPC_ST_UD = 0x2, 2001 MLX5_QPC_ST_XRC = 0x3, 2002 MLX5_QPC_ST_DCI = 0x5, 2003 MLX5_QPC_ST_QP0 = 0x7, 2004 MLX5_QPC_ST_QP1 = 0x8, 2005 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2006 MLX5_QPC_ST_REG_UMR = 0xc, 2007 }; 2008 2009 enum { 2010 MLX5_QP_PM_ARMED = 0x0, 2011 MLX5_QP_PM_REARM = 0x1, 2012 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2013 MLX5_QP_PM_MIGRATED = 0x3, 2014 }; 2015 2016 enum { 2017 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2018 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2019 }; 2020 2021 enum { 2022 MLX5_QPC_MTU_256_BYTES = 0x1, 2023 MLX5_QPC_MTU_512_BYTES = 0x2, 2024 MLX5_QPC_MTU_1K_BYTES = 0x3, 2025 MLX5_QPC_MTU_2K_BYTES = 0x4, 2026 MLX5_QPC_MTU_4K_BYTES = 0x5, 2027 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2028 }; 2029 2030 enum { 2031 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2032 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2033 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2034 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2035 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2036 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2037 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2038 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2039 }; 2040 2041 enum { 2042 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2043 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2044 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2045 }; 2046 2047 enum { 2048 MLX5_QPC_CS_RES_DISABLE = 0x0, 2049 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2050 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2051 }; 2052 2053 enum { 2054 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2055 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2056 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2057 }; 2058 2059 struct mlx5_ifc_qpc_bits { 2060 u8 state[0x4]; 2061 u8 lag_tx_port_affinity[0x4]; 2062 u8 st[0x8]; 2063 u8 reserved_1[0x3]; 2064 u8 pm_state[0x2]; 2065 u8 reserved_2[0x7]; 2066 u8 end_padding_mode[0x2]; 2067 u8 reserved_3[0x2]; 2068 2069 u8 wq_signature[0x1]; 2070 u8 block_lb_mc[0x1]; 2071 u8 atomic_like_write_en[0x1]; 2072 u8 latency_sensitive[0x1]; 2073 u8 reserved_4[0x1]; 2074 u8 drain_sigerr[0x1]; 2075 u8 reserved_5[0x2]; 2076 u8 pd[0x18]; 2077 2078 u8 mtu[0x3]; 2079 u8 log_msg_max[0x5]; 2080 u8 reserved_6[0x1]; 2081 u8 log_rq_size[0x4]; 2082 u8 log_rq_stride[0x3]; 2083 u8 no_sq[0x1]; 2084 u8 log_sq_size[0x4]; 2085 u8 reserved_at_55[0x3]; 2086 u8 ts_format[0x2]; 2087 u8 reserved_at_5a[0x1]; 2088 u8 rlky[0x1]; 2089 u8 ulp_stateless_offload_mode[0x4]; 2090 2091 u8 counter_set_id[0x8]; 2092 u8 uar_page[0x18]; 2093 2094 u8 reserved_8[0x8]; 2095 u8 user_index[0x18]; 2096 2097 u8 reserved_9[0x3]; 2098 u8 log_page_size[0x5]; 2099 u8 remote_qpn[0x18]; 2100 2101 struct mlx5_ifc_ads_bits primary_address_path; 2102 2103 struct mlx5_ifc_ads_bits secondary_address_path; 2104 2105 u8 log_ack_req_freq[0x4]; 2106 u8 reserved_10[0x4]; 2107 u8 log_sra_max[0x3]; 2108 u8 reserved_11[0x2]; 2109 u8 retry_count[0x3]; 2110 u8 rnr_retry[0x3]; 2111 u8 reserved_12[0x1]; 2112 u8 fre[0x1]; 2113 u8 cur_rnr_retry[0x3]; 2114 u8 cur_retry_count[0x3]; 2115 u8 reserved_13[0x5]; 2116 2117 u8 reserved_14[0x20]; 2118 2119 u8 reserved_15[0x8]; 2120 u8 next_send_psn[0x18]; 2121 2122 u8 reserved_16[0x8]; 2123 u8 cqn_snd[0x18]; 2124 2125 u8 reserved_at_400[0x8]; 2126 2127 u8 deth_sqpn[0x18]; 2128 u8 reserved_17[0x20]; 2129 2130 u8 reserved_18[0x8]; 2131 u8 last_acked_psn[0x18]; 2132 2133 u8 reserved_19[0x8]; 2134 u8 ssn[0x18]; 2135 2136 u8 reserved_20[0x8]; 2137 u8 log_rra_max[0x3]; 2138 u8 reserved_21[0x1]; 2139 u8 atomic_mode[0x4]; 2140 u8 rre[0x1]; 2141 u8 rwe[0x1]; 2142 u8 rae[0x1]; 2143 u8 reserved_22[0x1]; 2144 u8 page_offset[0x6]; 2145 u8 reserved_23[0x3]; 2146 u8 cd_slave_receive[0x1]; 2147 u8 cd_slave_send[0x1]; 2148 u8 cd_master[0x1]; 2149 2150 u8 reserved_24[0x3]; 2151 u8 min_rnr_nak[0x5]; 2152 u8 next_rcv_psn[0x18]; 2153 2154 u8 reserved_25[0x8]; 2155 u8 xrcd[0x18]; 2156 2157 u8 reserved_26[0x8]; 2158 u8 cqn_rcv[0x18]; 2159 2160 u8 dbr_addr[0x40]; 2161 2162 u8 q_key[0x20]; 2163 2164 u8 reserved_27[0x5]; 2165 u8 rq_type[0x3]; 2166 u8 srqn_rmpn[0x18]; 2167 2168 u8 reserved_28[0x8]; 2169 u8 rmsn[0x18]; 2170 2171 u8 hw_sq_wqebb_counter[0x10]; 2172 u8 sw_sq_wqebb_counter[0x10]; 2173 2174 u8 hw_rq_counter[0x20]; 2175 2176 u8 sw_rq_counter[0x20]; 2177 2178 u8 reserved_29[0x20]; 2179 2180 u8 reserved_30[0xf]; 2181 u8 cgs[0x1]; 2182 u8 cs_req[0x8]; 2183 u8 cs_res[0x8]; 2184 2185 u8 dc_access_key[0x40]; 2186 2187 u8 reserved_at_680[0x3]; 2188 u8 dbr_umem_valid[0x1]; 2189 2190 u8 reserved_at_684[0xbc]; 2191 }; 2192 2193 struct mlx5_ifc_roce_addr_layout_bits { 2194 u8 source_l3_address[16][0x8]; 2195 2196 u8 reserved_0[0x3]; 2197 u8 vlan_valid[0x1]; 2198 u8 vlan_id[0xc]; 2199 u8 source_mac_47_32[0x10]; 2200 2201 u8 source_mac_31_0[0x20]; 2202 2203 u8 reserved_1[0x14]; 2204 u8 roce_l3_type[0x4]; 2205 u8 roce_version[0x8]; 2206 2207 u8 reserved_2[0x20]; 2208 }; 2209 2210 struct mlx5_ifc_rdbc_bits { 2211 u8 reserved_0[0x1c]; 2212 u8 type[0x4]; 2213 2214 u8 reserved_1[0x20]; 2215 2216 u8 reserved_2[0x8]; 2217 u8 psn[0x18]; 2218 2219 u8 rkey[0x20]; 2220 2221 u8 address[0x40]; 2222 2223 u8 byte_count[0x20]; 2224 2225 u8 reserved_3[0x20]; 2226 2227 u8 atomic_resp[32][0x8]; 2228 }; 2229 2230 enum { 2231 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2232 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2233 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2234 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2235 }; 2236 2237 struct mlx5_ifc_flow_context_bits { 2238 u8 reserved_0[0x20]; 2239 2240 u8 group_id[0x20]; 2241 2242 u8 reserved_1[0x8]; 2243 u8 flow_tag[0x18]; 2244 2245 u8 reserved_2[0x10]; 2246 u8 action[0x10]; 2247 2248 u8 reserved_3[0x8]; 2249 u8 destination_list_size[0x18]; 2250 2251 u8 reserved_4[0x8]; 2252 u8 flow_counter_list_size[0x18]; 2253 2254 u8 reserved_5[0x140]; 2255 2256 struct mlx5_ifc_fte_match_param_bits match_value; 2257 2258 u8 reserved_6[0x600]; 2259 2260 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2261 }; 2262 2263 enum { 2264 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2265 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2266 }; 2267 2268 struct mlx5_ifc_xrc_srqc_bits { 2269 u8 state[0x4]; 2270 u8 log_xrc_srq_size[0x4]; 2271 u8 reserved_0[0x18]; 2272 2273 u8 wq_signature[0x1]; 2274 u8 cont_srq[0x1]; 2275 u8 reserved_1[0x1]; 2276 u8 rlky[0x1]; 2277 u8 basic_cyclic_rcv_wqe[0x1]; 2278 u8 log_rq_stride[0x3]; 2279 u8 xrcd[0x18]; 2280 2281 u8 page_offset[0x6]; 2282 u8 reserved_at_46[0x1]; 2283 u8 dbr_umem_valid[0x1]; 2284 u8 cqn[0x18]; 2285 2286 u8 reserved_3[0x20]; 2287 2288 u8 reserved_4[0x2]; 2289 u8 log_page_size[0x6]; 2290 u8 user_index[0x18]; 2291 2292 u8 reserved_5[0x20]; 2293 2294 u8 reserved_6[0x8]; 2295 u8 pd[0x18]; 2296 2297 u8 lwm[0x10]; 2298 u8 wqe_cnt[0x10]; 2299 2300 u8 reserved_7[0x40]; 2301 2302 u8 db_record_addr_h[0x20]; 2303 2304 u8 db_record_addr_l[0x1e]; 2305 u8 reserved_8[0x2]; 2306 2307 u8 reserved_9[0x80]; 2308 }; 2309 2310 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2311 u8 counter_error_queues[0x20]; 2312 2313 u8 total_error_queues[0x20]; 2314 2315 u8 send_queue_priority_update_flow[0x20]; 2316 2317 u8 reserved_at_60[0x20]; 2318 2319 u8 nic_receive_steering_discard[0x40]; 2320 2321 u8 receive_discard_vport_down[0x40]; 2322 2323 u8 transmit_discard_vport_down[0x40]; 2324 2325 u8 reserved_at_140[0xec0]; 2326 }; 2327 2328 struct mlx5_ifc_traffic_counter_bits { 2329 u8 packets[0x40]; 2330 2331 u8 octets[0x40]; 2332 }; 2333 2334 struct mlx5_ifc_tisc_bits { 2335 u8 strict_lag_tx_port_affinity[0x1]; 2336 u8 tls_en[0x1]; 2337 u8 reserved_at_2[0x2]; 2338 u8 lag_tx_port_affinity[0x04]; 2339 2340 u8 reserved_at_8[0x4]; 2341 u8 prio[0x4]; 2342 u8 reserved_1[0x10]; 2343 2344 u8 reserved_2[0x100]; 2345 2346 u8 reserved_3[0x8]; 2347 u8 transport_domain[0x18]; 2348 2349 u8 reserved_4[0x8]; 2350 u8 underlay_qpn[0x18]; 2351 2352 u8 reserved_5[0x8]; 2353 u8 pd[0x18]; 2354 2355 u8 reserved_6[0x380]; 2356 }; 2357 2358 enum { 2359 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2360 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2361 }; 2362 2363 enum { 2364 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2365 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2366 }; 2367 2368 enum { 2369 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2370 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2371 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2372 }; 2373 2374 enum { 2375 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2376 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2377 }; 2378 2379 struct mlx5_ifc_tirc_bits { 2380 u8 reserved_0[0x20]; 2381 2382 u8 disp_type[0x4]; 2383 u8 tls_en[0x1]; 2384 u8 reserved_at_25[0x1b]; 2385 2386 u8 reserved_2[0x40]; 2387 2388 u8 reserved_3[0x4]; 2389 u8 lro_timeout_period_usecs[0x10]; 2390 u8 lro_enable_mask[0x4]; 2391 u8 lro_max_msg_sz[0x8]; 2392 2393 u8 reserved_4[0x40]; 2394 2395 u8 reserved_5[0x8]; 2396 u8 inline_rqn[0x18]; 2397 2398 u8 rx_hash_symmetric[0x1]; 2399 u8 reserved_6[0x1]; 2400 u8 tunneled_offload_en[0x1]; 2401 u8 reserved_7[0x5]; 2402 u8 indirect_table[0x18]; 2403 2404 u8 rx_hash_fn[0x4]; 2405 u8 reserved_8[0x2]; 2406 u8 self_lb_en[0x2]; 2407 u8 transport_domain[0x18]; 2408 2409 u8 rx_hash_toeplitz_key[10][0x20]; 2410 2411 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2412 2413 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2414 2415 u8 reserved_9[0x4c0]; 2416 }; 2417 2418 enum { 2419 MLX5_SRQC_STATE_GOOD = 0x0, 2420 MLX5_SRQC_STATE_ERROR = 0x1, 2421 }; 2422 2423 struct mlx5_ifc_srqc_bits { 2424 u8 state[0x4]; 2425 u8 log_srq_size[0x4]; 2426 u8 reserved_0[0x18]; 2427 2428 u8 wq_signature[0x1]; 2429 u8 cont_srq[0x1]; 2430 u8 reserved_1[0x1]; 2431 u8 rlky[0x1]; 2432 u8 reserved_2[0x1]; 2433 u8 log_rq_stride[0x3]; 2434 u8 xrcd[0x18]; 2435 2436 u8 page_offset[0x6]; 2437 u8 reserved_3[0x2]; 2438 u8 cqn[0x18]; 2439 2440 u8 reserved_4[0x20]; 2441 2442 u8 reserved_5[0x2]; 2443 u8 log_page_size[0x6]; 2444 u8 reserved_6[0x18]; 2445 2446 u8 reserved_7[0x20]; 2447 2448 u8 reserved_8[0x8]; 2449 u8 pd[0x18]; 2450 2451 u8 lwm[0x10]; 2452 u8 wqe_cnt[0x10]; 2453 2454 u8 reserved_9[0x40]; 2455 2456 u8 dbr_addr[0x40]; 2457 2458 u8 reserved_10[0x80]; 2459 }; 2460 2461 enum { 2462 MLX5_SQC_STATE_RST = 0x0, 2463 MLX5_SQC_STATE_RDY = 0x1, 2464 MLX5_SQC_STATE_ERR = 0x3, 2465 }; 2466 2467 enum { 2468 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2469 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2470 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2471 }; 2472 2473 struct mlx5_ifc_sqc_bits { 2474 u8 rlkey[0x1]; 2475 u8 cd_master[0x1]; 2476 u8 fre[0x1]; 2477 u8 flush_in_error_en[0x1]; 2478 u8 allow_multi_pkt_send_wqe[0x1]; 2479 u8 min_wqe_inline_mode[0x3]; 2480 u8 state[0x4]; 2481 u8 reg_umr[0x1]; 2482 u8 allow_swp[0x1]; 2483 u8 reserved_at_e[0x4]; 2484 u8 qos_remap_en[0x1]; 2485 u8 reserved_at_d[0x7]; 2486 u8 ts_format[0x2]; 2487 u8 reserved_at_1c[0x4]; 2488 2489 u8 reserved_1[0x8]; 2490 u8 user_index[0x18]; 2491 2492 u8 reserved_2[0x8]; 2493 u8 cqn[0x18]; 2494 2495 u8 reserved_3[0x80]; 2496 2497 u8 qos_para_vport_number[0x10]; 2498 u8 packet_pacing_rate_limit_index[0x10]; 2499 2500 u8 tis_lst_sz[0x10]; 2501 u8 qos_queue_group_id[0x10]; 2502 2503 u8 reserved_4[0x8]; 2504 u8 queue_handle[0x18]; 2505 2506 u8 reserved_5[0x20]; 2507 2508 u8 reserved_6[0x8]; 2509 u8 tis_num_0[0x18]; 2510 2511 struct mlx5_ifc_wq_bits wq; 2512 }; 2513 2514 struct mlx5_ifc_query_pp_rate_limit_in_bits { 2515 u8 opcode[0x10]; 2516 u8 uid[0x10]; 2517 2518 u8 reserved1[0x10]; 2519 u8 op_mod[0x10]; 2520 2521 u8 reserved2[0x10]; 2522 u8 rate_limit_index[0x10]; 2523 2524 u8 reserved_3[0x20]; 2525 }; 2526 2527 struct mlx5_ifc_pp_context_bits { 2528 u8 rate_limit[0x20]; 2529 2530 u8 burst_upper_bound[0x20]; 2531 2532 u8 reserved_1[0xc]; 2533 u8 rate_mode[0x4]; 2534 u8 typical_packet_size[0x10]; 2535 2536 u8 reserved_2[0x8]; 2537 u8 qos_handle[0x18]; 2538 2539 u8 reserved_3[0x40]; 2540 }; 2541 2542 struct mlx5_ifc_query_pp_rate_limit_out_bits { 2543 u8 status[0x8]; 2544 u8 reserved_1[0x18]; 2545 2546 u8 syndrome[0x20]; 2547 2548 u8 reserved_2[0x40]; 2549 2550 struct mlx5_ifc_pp_context_bits pp_context; 2551 }; 2552 2553 enum { 2554 MLX5_TSAR_TYPE_DWRR = 0, 2555 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2556 MLX5_TSAR_TYPE_ETS = 2 2557 }; 2558 2559 struct mlx5_ifc_tsar_element_attributes_bits { 2560 u8 reserved_0[0x8]; 2561 u8 tsar_type[0x8]; 2562 u8 reserved_1[0x10]; 2563 }; 2564 2565 struct mlx5_ifc_vport_element_attributes_bits { 2566 u8 reserved_0[0x10]; 2567 u8 vport_number[0x10]; 2568 }; 2569 2570 struct mlx5_ifc_vport_tc_element_attributes_bits { 2571 u8 traffic_class[0x10]; 2572 u8 vport_number[0x10]; 2573 }; 2574 2575 struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2576 u8 reserved_0[0x0C]; 2577 u8 traffic_class[0x04]; 2578 u8 qos_para_vport_number[0x10]; 2579 }; 2580 2581 enum { 2582 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2583 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2584 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2585 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2586 }; 2587 2588 struct mlx5_ifc_scheduling_context_bits { 2589 u8 element_type[0x8]; 2590 u8 reserved_at_8[0x18]; 2591 2592 u8 element_attributes[0x20]; 2593 2594 u8 parent_element_id[0x20]; 2595 2596 u8 reserved_at_60[0x40]; 2597 2598 u8 bw_share[0x20]; 2599 2600 u8 max_average_bw[0x20]; 2601 2602 u8 reserved_at_e0[0x120]; 2603 }; 2604 2605 struct mlx5_ifc_rqtc_bits { 2606 u8 reserved_0[0xa0]; 2607 2608 u8 reserved_1[0x10]; 2609 u8 rqt_max_size[0x10]; 2610 2611 u8 reserved_2[0x10]; 2612 u8 rqt_actual_size[0x10]; 2613 2614 u8 reserved_3[0x6a0]; 2615 2616 struct mlx5_ifc_rq_num_bits rq_num[0]; 2617 }; 2618 2619 enum { 2620 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2621 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2622 }; 2623 2624 enum { 2625 MLX5_RQC_STATE_RST = 0x0, 2626 MLX5_RQC_STATE_RDY = 0x1, 2627 MLX5_RQC_STATE_ERR = 0x3, 2628 }; 2629 2630 enum { 2631 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2632 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2633 }; 2634 2635 enum { 2636 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2637 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2638 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2639 }; 2640 2641 struct mlx5_ifc_rqc_bits { 2642 u8 rlkey[0x1]; 2643 u8 delay_drop_en[0x1]; 2644 u8 scatter_fcs[0x1]; 2645 u8 vlan_strip_disable[0x1]; 2646 u8 mem_rq_type[0x4]; 2647 u8 state[0x4]; 2648 u8 reserved_1[0x1]; 2649 u8 flush_in_error_en[0x1]; 2650 u8 reserved_at_e[0xc]; 2651 u8 ts_format[0x2]; 2652 u8 reserved_at_1c[0x4]; 2653 2654 u8 reserved_3[0x8]; 2655 u8 user_index[0x18]; 2656 2657 u8 reserved_4[0x8]; 2658 u8 cqn[0x18]; 2659 2660 u8 counter_set_id[0x8]; 2661 u8 reserved_5[0x18]; 2662 2663 u8 reserved_6[0x8]; 2664 u8 rmpn[0x18]; 2665 2666 u8 reserved_7[0xe0]; 2667 2668 struct mlx5_ifc_wq_bits wq; 2669 }; 2670 2671 enum { 2672 MLX5_RMPC_STATE_RDY = 0x1, 2673 MLX5_RMPC_STATE_ERR = 0x3, 2674 }; 2675 2676 struct mlx5_ifc_rmpc_bits { 2677 u8 reserved_0[0x8]; 2678 u8 state[0x4]; 2679 u8 reserved_1[0x14]; 2680 2681 u8 basic_cyclic_rcv_wqe[0x1]; 2682 u8 reserved_2[0x1f]; 2683 2684 u8 reserved_3[0x140]; 2685 2686 struct mlx5_ifc_wq_bits wq; 2687 }; 2688 2689 enum { 2690 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2691 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2692 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2693 }; 2694 2695 struct mlx5_ifc_nic_vport_context_bits { 2696 u8 reserved_0[0x5]; 2697 u8 min_wqe_inline_mode[0x3]; 2698 u8 reserved_1[0x15]; 2699 u8 disable_mc_local_lb[0x1]; 2700 u8 disable_uc_local_lb[0x1]; 2701 u8 roce_en[0x1]; 2702 2703 u8 arm_change_event[0x1]; 2704 u8 reserved_2[0x1a]; 2705 u8 event_on_mtu[0x1]; 2706 u8 event_on_promisc_change[0x1]; 2707 u8 event_on_vlan_change[0x1]; 2708 u8 event_on_mc_address_change[0x1]; 2709 u8 event_on_uc_address_change[0x1]; 2710 2711 u8 reserved_3[0xe0]; 2712 2713 u8 reserved_4[0x10]; 2714 u8 mtu[0x10]; 2715 2716 u8 system_image_guid[0x40]; 2717 2718 u8 port_guid[0x40]; 2719 2720 u8 node_guid[0x40]; 2721 2722 u8 reserved_5[0x140]; 2723 2724 u8 qkey_violation_counter[0x10]; 2725 u8 reserved_6[0x10]; 2726 2727 u8 reserved_7[0x420]; 2728 2729 u8 promisc_uc[0x1]; 2730 u8 promisc_mc[0x1]; 2731 u8 promisc_all[0x1]; 2732 u8 reserved_8[0x2]; 2733 u8 allowed_list_type[0x3]; 2734 u8 reserved_9[0xc]; 2735 u8 allowed_list_size[0xc]; 2736 2737 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2738 2739 u8 reserved_10[0x20]; 2740 2741 u8 current_uc_mac_address[0][0x40]; 2742 }; 2743 2744 enum { 2745 MLX5_ACCESS_MODE_PA = 0x0, 2746 MLX5_ACCESS_MODE_MTT = 0x1, 2747 MLX5_ACCESS_MODE_KLM = 0x2, 2748 MLX5_ACCESS_MODE_KSM = 0x3, 2749 MLX5_ACCESS_MODE_SW_ICM = 0x4, 2750 MLX5_ACCESS_MODE_MEMIC = 0x5, 2751 }; 2752 2753 struct mlx5_ifc_mkc_bits { 2754 u8 reserved_at_0[0x1]; 2755 u8 free[0x1]; 2756 u8 reserved_at_2[0x1]; 2757 u8 access_mode_4_2[0x3]; 2758 u8 reserved_at_6[0x7]; 2759 u8 relaxed_ordering_write[0x1]; 2760 u8 reserved_at_e[0x1]; 2761 u8 small_fence_on_rdma_read_response[0x1]; 2762 u8 umr_en[0x1]; 2763 u8 a[0x1]; 2764 u8 rw[0x1]; 2765 u8 rr[0x1]; 2766 u8 lw[0x1]; 2767 u8 lr[0x1]; 2768 u8 access_mode[0x2]; 2769 u8 reserved_2[0x8]; 2770 2771 u8 qpn[0x18]; 2772 u8 mkey_7_0[0x8]; 2773 2774 u8 reserved_3[0x20]; 2775 2776 u8 length64[0x1]; 2777 u8 bsf_en[0x1]; 2778 u8 sync_umr[0x1]; 2779 u8 reserved_4[0x2]; 2780 u8 expected_sigerr_count[0x1]; 2781 u8 reserved_5[0x1]; 2782 u8 en_rinval[0x1]; 2783 u8 pd[0x18]; 2784 2785 u8 start_addr[0x40]; 2786 2787 u8 len[0x40]; 2788 2789 u8 bsf_octword_size[0x20]; 2790 2791 u8 reserved_6[0x80]; 2792 2793 u8 translations_octword_size[0x20]; 2794 2795 u8 reserved_at_1c0[0x19]; 2796 u8 relaxed_ordering_read[0x1]; 2797 u8 reserved_at_1d9[0x1]; 2798 u8 log_page_size[0x5]; 2799 2800 u8 reserved_8[0x20]; 2801 }; 2802 2803 struct mlx5_ifc_pkey_bits { 2804 u8 reserved_0[0x10]; 2805 u8 pkey[0x10]; 2806 }; 2807 2808 struct mlx5_ifc_array128_auto_bits { 2809 u8 array128_auto[16][0x8]; 2810 }; 2811 2812 enum { 2813 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2814 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2815 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2816 }; 2817 2818 enum { 2819 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2820 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2821 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2822 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2823 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2824 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2825 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2826 }; 2827 2828 enum { 2829 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2830 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2831 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2832 }; 2833 2834 enum { 2835 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2836 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2837 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2838 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2839 }; 2840 2841 enum { 2842 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2843 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2844 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2845 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2846 }; 2847 2848 struct mlx5_ifc_hca_vport_context_bits { 2849 u8 field_select[0x20]; 2850 2851 u8 reserved_0[0xe0]; 2852 2853 u8 sm_virt_aware[0x1]; 2854 u8 has_smi[0x1]; 2855 u8 has_raw[0x1]; 2856 u8 grh_required[0x1]; 2857 u8 reserved_1[0x1]; 2858 u8 min_wqe_inline_mode[0x3]; 2859 u8 reserved_2[0x8]; 2860 u8 port_physical_state[0x4]; 2861 u8 vport_state_policy[0x4]; 2862 u8 port_state[0x4]; 2863 u8 vport_state[0x4]; 2864 2865 u8 reserved_3[0x20]; 2866 2867 u8 system_image_guid[0x40]; 2868 2869 u8 port_guid[0x40]; 2870 2871 u8 node_guid[0x40]; 2872 2873 u8 cap_mask1[0x20]; 2874 2875 u8 cap_mask1_field_select[0x20]; 2876 2877 u8 cap_mask2[0x20]; 2878 2879 u8 cap_mask2_field_select[0x20]; 2880 2881 u8 reserved_4[0x80]; 2882 2883 u8 lid[0x10]; 2884 u8 reserved_5[0x4]; 2885 u8 init_type_reply[0x4]; 2886 u8 lmc[0x3]; 2887 u8 subnet_timeout[0x5]; 2888 2889 u8 sm_lid[0x10]; 2890 u8 sm_sl[0x4]; 2891 u8 reserved_6[0xc]; 2892 2893 u8 qkey_violation_counter[0x10]; 2894 u8 pkey_violation_counter[0x10]; 2895 2896 u8 reserved_7[0xca0]; 2897 }; 2898 2899 union mlx5_ifc_hca_cap_union_bits { 2900 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2901 struct mlx5_ifc_odp_cap_bits odp_cap; 2902 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2903 struct mlx5_ifc_roce_cap_bits roce_cap; 2904 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2905 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2906 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2907 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2908 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2909 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2910 struct mlx5_ifc_qos_cap_bits qos_cap; 2911 struct mlx5_ifc_tls_capabilities_bits tls_capabilities; 2912 u8 reserved_0[0x8000]; 2913 }; 2914 2915 enum { 2916 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 2917 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 2918 }; 2919 2920 struct mlx5_ifc_flow_table_context_bits { 2921 u8 encap_en[0x1]; 2922 u8 decap_en[0x1]; 2923 u8 reserved_at_2[0x2]; 2924 u8 table_miss_action[0x4]; 2925 u8 level[0x8]; 2926 u8 reserved_at_10[0x8]; 2927 u8 log_size[0x8]; 2928 2929 u8 reserved_at_20[0x8]; 2930 u8 table_miss_id[0x18]; 2931 2932 u8 reserved_at_40[0x8]; 2933 u8 lag_master_next_table_id[0x18]; 2934 2935 u8 reserved_at_60[0xe0]; 2936 }; 2937 2938 struct mlx5_ifc_esw_vport_context_bits { 2939 u8 reserved_0[0x3]; 2940 u8 vport_svlan_strip[0x1]; 2941 u8 vport_cvlan_strip[0x1]; 2942 u8 vport_svlan_insert[0x1]; 2943 u8 vport_cvlan_insert[0x2]; 2944 u8 reserved_1[0x18]; 2945 2946 u8 reserved_2[0x20]; 2947 2948 u8 svlan_cfi[0x1]; 2949 u8 svlan_pcp[0x3]; 2950 u8 svlan_id[0xc]; 2951 u8 cvlan_cfi[0x1]; 2952 u8 cvlan_pcp[0x3]; 2953 u8 cvlan_id[0xc]; 2954 2955 u8 reserved_3[0x7a0]; 2956 }; 2957 2958 enum { 2959 MLX5_EQC_STATUS_OK = 0x0, 2960 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2961 }; 2962 2963 enum { 2964 MLX5_EQ_STATE_ARMED = 0x9, 2965 MLX5_EQ_STATE_FIRED = 0xa, 2966 }; 2967 2968 struct mlx5_ifc_eqc_bits { 2969 u8 status[0x4]; 2970 u8 reserved_0[0x9]; 2971 u8 ec[0x1]; 2972 u8 oi[0x1]; 2973 u8 reserved_1[0x5]; 2974 u8 st[0x4]; 2975 u8 reserved_2[0x8]; 2976 2977 u8 reserved_3[0x20]; 2978 2979 u8 reserved_4[0x14]; 2980 u8 page_offset[0x6]; 2981 u8 reserved_5[0x6]; 2982 2983 u8 reserved_6[0x3]; 2984 u8 log_eq_size[0x5]; 2985 u8 uar_page[0x18]; 2986 2987 u8 reserved_7[0x20]; 2988 2989 u8 reserved_8[0x18]; 2990 u8 intr[0x8]; 2991 2992 u8 reserved_9[0x3]; 2993 u8 log_page_size[0x5]; 2994 u8 reserved_10[0x18]; 2995 2996 u8 reserved_11[0x60]; 2997 2998 u8 reserved_12[0x8]; 2999 u8 consumer_counter[0x18]; 3000 3001 u8 reserved_13[0x8]; 3002 u8 producer_counter[0x18]; 3003 3004 u8 reserved_14[0x80]; 3005 }; 3006 3007 enum { 3008 MLX5_DCTC_STATE_ACTIVE = 0x0, 3009 MLX5_DCTC_STATE_DRAINING = 0x1, 3010 MLX5_DCTC_STATE_DRAINED = 0x2, 3011 }; 3012 3013 enum { 3014 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3015 MLX5_DCTC_CS_RES_NA = 0x1, 3016 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3017 }; 3018 3019 enum { 3020 MLX5_DCTC_MTU_256_BYTES = 0x1, 3021 MLX5_DCTC_MTU_512_BYTES = 0x2, 3022 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3023 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3024 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3025 }; 3026 3027 struct mlx5_ifc_dctc_bits { 3028 u8 reserved_0[0x4]; 3029 u8 state[0x4]; 3030 u8 reserved_1[0x18]; 3031 3032 u8 reserved_2[0x8]; 3033 u8 user_index[0x18]; 3034 3035 u8 reserved_3[0x8]; 3036 u8 cqn[0x18]; 3037 3038 u8 counter_set_id[0x8]; 3039 u8 atomic_mode[0x4]; 3040 u8 rre[0x1]; 3041 u8 rwe[0x1]; 3042 u8 rae[0x1]; 3043 u8 atomic_like_write_en[0x1]; 3044 u8 latency_sensitive[0x1]; 3045 u8 rlky[0x1]; 3046 u8 reserved_4[0xe]; 3047 3048 u8 reserved_5[0x8]; 3049 u8 cs_res[0x8]; 3050 u8 reserved_6[0x3]; 3051 u8 min_rnr_nak[0x5]; 3052 u8 reserved_7[0x8]; 3053 3054 u8 reserved_8[0x8]; 3055 u8 srqn[0x18]; 3056 3057 u8 reserved_9[0x8]; 3058 u8 pd[0x18]; 3059 3060 u8 tclass[0x8]; 3061 u8 reserved_10[0x4]; 3062 u8 flow_label[0x14]; 3063 3064 u8 dc_access_key[0x40]; 3065 3066 u8 reserved_11[0x5]; 3067 u8 mtu[0x3]; 3068 u8 port[0x8]; 3069 u8 pkey_index[0x10]; 3070 3071 u8 reserved_12[0x8]; 3072 u8 my_addr_index[0x8]; 3073 u8 reserved_13[0x8]; 3074 u8 hop_limit[0x8]; 3075 3076 u8 dc_access_key_violation_count[0x20]; 3077 3078 u8 reserved_14[0x14]; 3079 u8 dei_cfi[0x1]; 3080 u8 eth_prio[0x3]; 3081 u8 ecn[0x2]; 3082 u8 dscp[0x6]; 3083 3084 u8 reserved_15[0x40]; 3085 }; 3086 3087 enum { 3088 MLX5_CQC_STATUS_OK = 0x0, 3089 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3090 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3091 }; 3092 3093 enum { 3094 CQE_SIZE_64 = 0x0, 3095 CQE_SIZE_128 = 0x1, 3096 }; 3097 3098 enum { 3099 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3100 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3101 }; 3102 3103 enum { 3104 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 3105 MLX5_CQ_STATE_ARMED = 0x9, 3106 MLX5_CQ_STATE_FIRED = 0xa, 3107 }; 3108 3109 struct mlx5_ifc_cqc_bits { 3110 u8 status[0x4]; 3111 u8 reserved_at_4[0x2]; 3112 u8 dbr_umem_valid[0x1]; 3113 u8 reserved_at_7[0x1]; 3114 u8 cqe_sz[0x3]; 3115 u8 cc[0x1]; 3116 u8 reserved_1[0x1]; 3117 u8 scqe_break_moderation_en[0x1]; 3118 u8 oi[0x1]; 3119 u8 cq_period_mode[0x2]; 3120 u8 cqe_compression_en[0x1]; 3121 u8 mini_cqe_res_format[0x2]; 3122 u8 st[0x4]; 3123 u8 reserved_2[0x8]; 3124 3125 u8 reserved_3[0x20]; 3126 3127 u8 reserved_4[0x14]; 3128 u8 page_offset[0x6]; 3129 u8 reserved_5[0x6]; 3130 3131 u8 reserved_6[0x3]; 3132 u8 log_cq_size[0x5]; 3133 u8 uar_page[0x18]; 3134 3135 u8 reserved_7[0x4]; 3136 u8 cq_period[0xc]; 3137 u8 cq_max_count[0x10]; 3138 3139 u8 reserved_8[0x18]; 3140 u8 c_eqn[0x8]; 3141 3142 u8 reserved_9[0x3]; 3143 u8 log_page_size[0x5]; 3144 u8 reserved_10[0x18]; 3145 3146 u8 reserved_11[0x20]; 3147 3148 u8 reserved_12[0x8]; 3149 u8 last_notified_index[0x18]; 3150 3151 u8 reserved_13[0x8]; 3152 u8 last_solicit_index[0x18]; 3153 3154 u8 reserved_14[0x8]; 3155 u8 consumer_counter[0x18]; 3156 3157 u8 reserved_15[0x8]; 3158 u8 producer_counter[0x18]; 3159 3160 u8 reserved_16[0x40]; 3161 3162 u8 dbr_addr[0x40]; 3163 }; 3164 3165 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3166 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3167 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3168 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3169 u8 reserved_0[0x800]; 3170 }; 3171 3172 struct mlx5_ifc_query_adapter_param_block_bits { 3173 u8 reserved_0[0xc0]; 3174 3175 u8 reserved_1[0x8]; 3176 u8 ieee_vendor_id[0x18]; 3177 3178 u8 reserved_2[0x10]; 3179 u8 vsd_vendor_id[0x10]; 3180 3181 u8 vsd[208][0x8]; 3182 3183 u8 vsd_contd_psid[16][0x8]; 3184 }; 3185 3186 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3187 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3188 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3189 u8 reserved_0[0x20]; 3190 }; 3191 3192 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3193 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3194 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3195 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3196 u8 reserved_0[0x20]; 3197 }; 3198 3199 struct mlx5_ifc_bufferx_reg_bits { 3200 u8 reserved_0[0x6]; 3201 u8 lossy[0x1]; 3202 u8 epsb[0x1]; 3203 u8 reserved_1[0xc]; 3204 u8 size[0xc]; 3205 3206 u8 xoff_threshold[0x10]; 3207 u8 xon_threshold[0x10]; 3208 }; 3209 3210 struct mlx5_ifc_config_item_bits { 3211 u8 valid[0x2]; 3212 u8 reserved_0[0x2]; 3213 u8 header_type[0x2]; 3214 u8 reserved_1[0x2]; 3215 u8 default_location[0x1]; 3216 u8 reserved_2[0x7]; 3217 u8 version[0x4]; 3218 u8 reserved_3[0x3]; 3219 u8 length[0x9]; 3220 3221 u8 type[0x20]; 3222 3223 u8 reserved_4[0x10]; 3224 u8 crc16[0x10]; 3225 }; 3226 3227 enum { 3228 MLX5_XRQC_STATE_GOOD = 0x0, 3229 MLX5_XRQC_STATE_ERROR = 0x1, 3230 }; 3231 3232 enum { 3233 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3234 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3235 }; 3236 3237 enum { 3238 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3239 }; 3240 3241 struct mlx5_ifc_tag_matching_topology_context_bits { 3242 u8 log_matching_list_sz[0x4]; 3243 u8 reserved_at_4[0xc]; 3244 u8 append_next_index[0x10]; 3245 3246 u8 sw_phase_cnt[0x10]; 3247 u8 hw_phase_cnt[0x10]; 3248 3249 u8 reserved_at_40[0x40]; 3250 }; 3251 3252 struct mlx5_ifc_xrqc_bits { 3253 u8 state[0x4]; 3254 u8 rlkey[0x1]; 3255 u8 reserved_at_5[0xf]; 3256 u8 topology[0x4]; 3257 u8 reserved_at_18[0x4]; 3258 u8 offload[0x4]; 3259 3260 u8 reserved_at_20[0x8]; 3261 u8 user_index[0x18]; 3262 3263 u8 reserved_at_40[0x8]; 3264 u8 cqn[0x18]; 3265 3266 u8 reserved_at_60[0xa0]; 3267 3268 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3269 3270 u8 reserved_at_180[0x280]; 3271 3272 struct mlx5_ifc_wq_bits wq; 3273 }; 3274 3275 struct mlx5_ifc_nodnic_port_config_reg_bits { 3276 struct mlx5_ifc_nodnic_event_word_bits event; 3277 3278 u8 network_en[0x1]; 3279 u8 dma_en[0x1]; 3280 u8 promisc_en[0x1]; 3281 u8 promisc_multicast_en[0x1]; 3282 u8 reserved_0[0x17]; 3283 u8 receive_filter_en[0x5]; 3284 3285 u8 reserved_1[0x10]; 3286 u8 mac_47_32[0x10]; 3287 3288 u8 mac_31_0[0x20]; 3289 3290 u8 receive_filters_mgid_mac[64][0x8]; 3291 3292 u8 gid[16][0x8]; 3293 3294 u8 reserved_2[0x10]; 3295 u8 lid[0x10]; 3296 3297 u8 reserved_3[0xc]; 3298 u8 sm_sl[0x4]; 3299 u8 sm_lid[0x10]; 3300 3301 u8 completion_address_63_32[0x20]; 3302 3303 u8 completion_address_31_12[0x14]; 3304 u8 reserved_4[0x6]; 3305 u8 log_cq_size[0x6]; 3306 3307 u8 working_buffer_address_63_32[0x20]; 3308 3309 u8 working_buffer_address_31_12[0x14]; 3310 u8 reserved_5[0xc]; 3311 3312 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 3313 3314 u8 pkey_index[0x10]; 3315 u8 pkey[0x10]; 3316 3317 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 3318 3319 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 3320 3321 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 3322 3323 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 3324 3325 u8 reserved_6[0x400]; 3326 }; 3327 3328 union mlx5_ifc_event_auto_bits { 3329 struct mlx5_ifc_comp_event_bits comp_event; 3330 struct mlx5_ifc_dct_events_bits dct_events; 3331 struct mlx5_ifc_qp_events_bits qp_events; 3332 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3333 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3334 struct mlx5_ifc_cq_error_bits cq_error; 3335 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3336 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3337 struct mlx5_ifc_gpio_event_bits gpio_event; 3338 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3339 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3340 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3341 struct mlx5_ifc_pages_req_event_bits pages_req_event; 3342 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 3343 u8 reserved_0[0xe0]; 3344 }; 3345 3346 struct mlx5_ifc_health_buffer_bits { 3347 u8 reserved_0[0x100]; 3348 3349 u8 assert_existptr[0x20]; 3350 3351 u8 assert_callra[0x20]; 3352 3353 u8 reserved_1[0x40]; 3354 3355 u8 fw_version[0x20]; 3356 3357 u8 hw_id[0x20]; 3358 3359 u8 reserved_2[0x20]; 3360 3361 u8 irisc_index[0x8]; 3362 u8 synd[0x8]; 3363 u8 ext_synd[0x10]; 3364 }; 3365 3366 struct mlx5_ifc_register_loopback_control_bits { 3367 u8 no_lb[0x1]; 3368 u8 reserved_0[0x7]; 3369 u8 port[0x8]; 3370 u8 reserved_1[0x10]; 3371 3372 u8 reserved_2[0x60]; 3373 }; 3374 3375 struct mlx5_ifc_lrh_bits { 3376 u8 vl[4]; 3377 u8 lver[4]; 3378 u8 sl[4]; 3379 u8 reserved2[2]; 3380 u8 lnh[2]; 3381 u8 dlid[16]; 3382 u8 reserved5[5]; 3383 u8 pkt_len[11]; 3384 u8 slid[16]; 3385 }; 3386 3387 struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3388 u8 reserved_0[0x40]; 3389 3390 u8 reserved_1[0x10]; 3391 u8 rol_mode[0x8]; 3392 u8 wol_mode[0x8]; 3393 }; 3394 3395 struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3396 u8 reserved_0[0x40]; 3397 3398 u8 rol_mode_valid[0x1]; 3399 u8 wol_mode_valid[0x1]; 3400 u8 reserved_1[0xe]; 3401 u8 rol_mode[0x8]; 3402 u8 wol_mode[0x8]; 3403 3404 u8 reserved_2[0x7a0]; 3405 }; 3406 3407 struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3408 u8 virtual_mac_en[0x1]; 3409 u8 mac_aux_v[0x1]; 3410 u8 reserved_0[0x1e]; 3411 3412 u8 reserved_1[0x40]; 3413 3414 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3415 3416 u8 reserved_2[0x760]; 3417 }; 3418 3419 struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3420 u8 virtual_mac_en[0x1]; 3421 u8 mac_aux_v[0x1]; 3422 u8 reserved_0[0x1e]; 3423 3424 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3425 3426 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3427 3428 u8 reserved_1[0x760]; 3429 }; 3430 3431 struct mlx5_ifc_icmd_query_fw_info_out_bits { 3432 struct mlx5_ifc_fw_version_bits fw_version; 3433 3434 u8 reserved_0[0x10]; 3435 u8 hash_signature[0x10]; 3436 3437 u8 psid[16][0x8]; 3438 3439 u8 reserved_1[0x6e0]; 3440 }; 3441 3442 struct mlx5_ifc_icmd_query_cap_in_bits { 3443 u8 reserved_0[0x10]; 3444 u8 capability_group[0x10]; 3445 }; 3446 3447 struct mlx5_ifc_icmd_query_cap_general_bits { 3448 u8 nv_access[0x1]; 3449 u8 fw_info_psid[0x1]; 3450 u8 reserved_0[0x1e]; 3451 3452 u8 reserved_1[0x16]; 3453 u8 rol_s[0x1]; 3454 u8 rol_g[0x1]; 3455 u8 reserved_2[0x1]; 3456 u8 wol_s[0x1]; 3457 u8 wol_g[0x1]; 3458 u8 wol_a[0x1]; 3459 u8 wol_b[0x1]; 3460 u8 wol_m[0x1]; 3461 u8 wol_u[0x1]; 3462 u8 wol_p[0x1]; 3463 }; 3464 3465 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3466 u8 status[0x8]; 3467 u8 reserved_0[0x18]; 3468 3469 u8 reserved_1[0x7e0]; 3470 }; 3471 3472 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3473 u8 status[0x8]; 3474 u8 reserved_0[0x18]; 3475 3476 u8 reserved_1[0x7e0]; 3477 }; 3478 3479 struct mlx5_ifc_icmd_ocbb_init_in_bits { 3480 u8 address_hi[0x20]; 3481 3482 u8 address_lo[0x20]; 3483 3484 u8 reserved_0[0x7c0]; 3485 }; 3486 3487 struct mlx5_ifc_icmd_init_ocsd_in_bits { 3488 u8 reserved_0[0x20]; 3489 3490 u8 address_hi[0x20]; 3491 3492 u8 address_lo[0x20]; 3493 3494 u8 reserved_1[0x7a0]; 3495 }; 3496 3497 struct mlx5_ifc_icmd_access_reg_out_bits { 3498 u8 reserved_0[0x11]; 3499 u8 status[0x7]; 3500 u8 reserved_1[0x8]; 3501 3502 u8 register_id[0x10]; 3503 u8 reserved_2[0x10]; 3504 3505 u8 reserved_3[0x40]; 3506 3507 u8 reserved_4[0x5]; 3508 u8 len[0xb]; 3509 u8 reserved_5[0x10]; 3510 3511 u8 register_data[0][0x20]; 3512 }; 3513 3514 enum { 3515 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3516 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3517 }; 3518 3519 struct mlx5_ifc_icmd_access_reg_in_bits { 3520 u8 constant_1[0x5]; 3521 u8 constant_2[0xb]; 3522 u8 reserved_0[0x10]; 3523 3524 u8 register_id[0x10]; 3525 u8 reserved_1[0x1]; 3526 u8 method[0x7]; 3527 u8 constant_3[0x8]; 3528 3529 u8 reserved_2[0x40]; 3530 3531 u8 constant_4[0x5]; 3532 u8 len[0xb]; 3533 u8 reserved_3[0x10]; 3534 3535 u8 register_data[0][0x20]; 3536 }; 3537 3538 enum { 3539 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3540 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3541 }; 3542 3543 struct mlx5_ifc_teardown_hca_out_bits { 3544 u8 status[0x8]; 3545 u8 reserved_0[0x18]; 3546 3547 u8 syndrome[0x20]; 3548 3549 u8 reserved_1[0x3f]; 3550 3551 u8 state[0x1]; 3552 }; 3553 3554 enum { 3555 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3556 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3557 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3558 }; 3559 3560 struct mlx5_ifc_teardown_hca_in_bits { 3561 u8 opcode[0x10]; 3562 u8 reserved_0[0x10]; 3563 3564 u8 reserved_1[0x10]; 3565 u8 op_mod[0x10]; 3566 3567 u8 reserved_2[0x10]; 3568 u8 profile[0x10]; 3569 3570 u8 reserved_3[0x20]; 3571 }; 3572 3573 struct mlx5_ifc_set_delay_drop_params_out_bits { 3574 u8 status[0x8]; 3575 u8 reserved_at_8[0x18]; 3576 3577 u8 syndrome[0x20]; 3578 3579 u8 reserved_at_40[0x40]; 3580 }; 3581 3582 struct mlx5_ifc_set_delay_drop_params_in_bits { 3583 u8 opcode[0x10]; 3584 u8 reserved_at_10[0x10]; 3585 3586 u8 reserved_at_20[0x10]; 3587 u8 op_mod[0x10]; 3588 3589 u8 reserved_at_40[0x20]; 3590 3591 u8 reserved_at_60[0x10]; 3592 u8 delay_drop_timeout[0x10]; 3593 }; 3594 3595 struct mlx5_ifc_query_delay_drop_params_out_bits { 3596 u8 status[0x8]; 3597 u8 reserved_at_8[0x18]; 3598 3599 u8 syndrome[0x20]; 3600 3601 u8 reserved_at_40[0x20]; 3602 3603 u8 reserved_at_60[0x10]; 3604 u8 delay_drop_timeout[0x10]; 3605 }; 3606 3607 struct mlx5_ifc_query_delay_drop_params_in_bits { 3608 u8 opcode[0x10]; 3609 u8 reserved_at_10[0x10]; 3610 3611 u8 reserved_at_20[0x10]; 3612 u8 op_mod[0x10]; 3613 3614 u8 reserved_at_40[0x40]; 3615 }; 3616 3617 struct mlx5_ifc_suspend_qp_out_bits { 3618 u8 status[0x8]; 3619 u8 reserved_0[0x18]; 3620 3621 u8 syndrome[0x20]; 3622 3623 u8 reserved_1[0x40]; 3624 }; 3625 3626 struct mlx5_ifc_suspend_qp_in_bits { 3627 u8 opcode[0x10]; 3628 u8 reserved_0[0x10]; 3629 3630 u8 reserved_1[0x10]; 3631 u8 op_mod[0x10]; 3632 3633 u8 reserved_2[0x8]; 3634 u8 qpn[0x18]; 3635 3636 u8 reserved_3[0x20]; 3637 }; 3638 3639 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3640 u8 status[0x8]; 3641 u8 reserved_0[0x18]; 3642 3643 u8 syndrome[0x20]; 3644 3645 u8 reserved_1[0x40]; 3646 }; 3647 3648 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3649 u8 opcode[0x10]; 3650 u8 uid[0x10]; 3651 3652 u8 reserved_1[0x10]; 3653 u8 op_mod[0x10]; 3654 3655 u8 reserved_2[0x8]; 3656 u8 qpn[0x18]; 3657 3658 u8 reserved_3[0x20]; 3659 3660 u8 opt_param_mask[0x20]; 3661 3662 u8 reserved_4[0x20]; 3663 3664 struct mlx5_ifc_qpc_bits qpc; 3665 3666 u8 reserved_5[0x80]; 3667 }; 3668 3669 struct mlx5_ifc_sqd2rts_qp_out_bits { 3670 u8 status[0x8]; 3671 u8 reserved_0[0x18]; 3672 3673 u8 syndrome[0x20]; 3674 3675 u8 reserved_1[0x40]; 3676 }; 3677 3678 struct mlx5_ifc_sqd2rts_qp_in_bits { 3679 u8 opcode[0x10]; 3680 u8 uid[0x10]; 3681 3682 u8 reserved_1[0x10]; 3683 u8 op_mod[0x10]; 3684 3685 u8 reserved_2[0x8]; 3686 u8 qpn[0x18]; 3687 3688 u8 reserved_3[0x20]; 3689 3690 u8 opt_param_mask[0x20]; 3691 3692 u8 reserved_4[0x20]; 3693 3694 struct mlx5_ifc_qpc_bits qpc; 3695 3696 u8 reserved_5[0x80]; 3697 }; 3698 3699 struct mlx5_ifc_set_wol_rol_out_bits { 3700 u8 status[0x8]; 3701 u8 reserved_0[0x18]; 3702 3703 u8 syndrome[0x20]; 3704 3705 u8 reserved_1[0x40]; 3706 }; 3707 3708 struct mlx5_ifc_set_wol_rol_in_bits { 3709 u8 opcode[0x10]; 3710 u8 reserved_0[0x10]; 3711 3712 u8 reserved_1[0x10]; 3713 u8 op_mod[0x10]; 3714 3715 u8 rol_mode_valid[0x1]; 3716 u8 wol_mode_valid[0x1]; 3717 u8 reserved_2[0xe]; 3718 u8 rol_mode[0x8]; 3719 u8 wol_mode[0x8]; 3720 3721 u8 reserved_3[0x20]; 3722 }; 3723 3724 struct mlx5_ifc_set_roce_address_out_bits { 3725 u8 status[0x8]; 3726 u8 reserved_0[0x18]; 3727 3728 u8 syndrome[0x20]; 3729 3730 u8 reserved_1[0x40]; 3731 }; 3732 3733 struct mlx5_ifc_set_roce_address_in_bits { 3734 u8 opcode[0x10]; 3735 u8 reserved_0[0x10]; 3736 3737 u8 reserved_1[0x10]; 3738 u8 op_mod[0x10]; 3739 3740 u8 roce_address_index[0x10]; 3741 u8 reserved_2[0x10]; 3742 3743 u8 reserved_3[0x20]; 3744 3745 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3746 }; 3747 3748 struct mlx5_ifc_set_rdb_out_bits { 3749 u8 status[0x8]; 3750 u8 reserved_0[0x18]; 3751 3752 u8 syndrome[0x20]; 3753 3754 u8 reserved_1[0x40]; 3755 }; 3756 3757 struct mlx5_ifc_set_rdb_in_bits { 3758 u8 opcode[0x10]; 3759 u8 reserved_0[0x10]; 3760 3761 u8 reserved_1[0x10]; 3762 u8 op_mod[0x10]; 3763 3764 u8 reserved_2[0x8]; 3765 u8 qpn[0x18]; 3766 3767 u8 reserved_3[0x18]; 3768 u8 rdb_list_size[0x8]; 3769 3770 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3771 }; 3772 3773 struct mlx5_ifc_set_mad_demux_out_bits { 3774 u8 status[0x8]; 3775 u8 reserved_0[0x18]; 3776 3777 u8 syndrome[0x20]; 3778 3779 u8 reserved_1[0x40]; 3780 }; 3781 3782 enum { 3783 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3784 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3785 }; 3786 3787 struct mlx5_ifc_set_mad_demux_in_bits { 3788 u8 opcode[0x10]; 3789 u8 reserved_0[0x10]; 3790 3791 u8 reserved_1[0x10]; 3792 u8 op_mod[0x10]; 3793 3794 u8 reserved_2[0x20]; 3795 3796 u8 reserved_3[0x6]; 3797 u8 demux_mode[0x2]; 3798 u8 reserved_4[0x18]; 3799 }; 3800 3801 struct mlx5_ifc_set_l2_table_entry_out_bits { 3802 u8 status[0x8]; 3803 u8 reserved_0[0x18]; 3804 3805 u8 syndrome[0x20]; 3806 3807 u8 reserved_1[0x40]; 3808 }; 3809 3810 struct mlx5_ifc_set_l2_table_entry_in_bits { 3811 u8 opcode[0x10]; 3812 u8 reserved_0[0x10]; 3813 3814 u8 reserved_1[0x10]; 3815 u8 op_mod[0x10]; 3816 3817 u8 reserved_2[0x60]; 3818 3819 u8 reserved_3[0x8]; 3820 u8 table_index[0x18]; 3821 3822 u8 reserved_4[0x20]; 3823 3824 u8 reserved_5[0x13]; 3825 u8 vlan_valid[0x1]; 3826 u8 vlan[0xc]; 3827 3828 struct mlx5_ifc_mac_address_layout_bits mac_address; 3829 3830 u8 reserved_6[0xc0]; 3831 }; 3832 3833 struct mlx5_ifc_set_issi_out_bits { 3834 u8 status[0x8]; 3835 u8 reserved_0[0x18]; 3836 3837 u8 syndrome[0x20]; 3838 3839 u8 reserved_1[0x40]; 3840 }; 3841 3842 struct mlx5_ifc_set_issi_in_bits { 3843 u8 opcode[0x10]; 3844 u8 reserved_0[0x10]; 3845 3846 u8 reserved_1[0x10]; 3847 u8 op_mod[0x10]; 3848 3849 u8 reserved_2[0x10]; 3850 u8 current_issi[0x10]; 3851 3852 u8 reserved_3[0x20]; 3853 }; 3854 3855 struct mlx5_ifc_set_hca_cap_out_bits { 3856 u8 status[0x8]; 3857 u8 reserved_0[0x18]; 3858 3859 u8 syndrome[0x20]; 3860 3861 u8 reserved_1[0x40]; 3862 }; 3863 3864 struct mlx5_ifc_set_hca_cap_in_bits { 3865 u8 opcode[0x10]; 3866 u8 reserved_0[0x10]; 3867 3868 u8 reserved_1[0x10]; 3869 u8 op_mod[0x10]; 3870 3871 u8 reserved_2[0x40]; 3872 3873 union mlx5_ifc_hca_cap_union_bits capability; 3874 }; 3875 3876 enum { 3877 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3878 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3879 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3880 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3881 }; 3882 3883 struct mlx5_ifc_set_flow_table_root_out_bits { 3884 u8 status[0x8]; 3885 u8 reserved_0[0x18]; 3886 3887 u8 syndrome[0x20]; 3888 3889 u8 reserved_1[0x40]; 3890 }; 3891 3892 struct mlx5_ifc_set_flow_table_root_in_bits { 3893 u8 opcode[0x10]; 3894 u8 reserved_0[0x10]; 3895 3896 u8 reserved_1[0x10]; 3897 u8 op_mod[0x10]; 3898 3899 u8 other_vport[0x1]; 3900 u8 reserved_2[0xf]; 3901 u8 vport_number[0x10]; 3902 3903 u8 reserved_3[0x20]; 3904 3905 u8 table_type[0x8]; 3906 u8 reserved_4[0x18]; 3907 3908 u8 reserved_5[0x8]; 3909 u8 table_id[0x18]; 3910 3911 u8 reserved_6[0x8]; 3912 u8 underlay_qpn[0x18]; 3913 3914 u8 reserved_7[0x120]; 3915 }; 3916 3917 struct mlx5_ifc_set_fte_out_bits { 3918 u8 status[0x8]; 3919 u8 reserved_0[0x18]; 3920 3921 u8 syndrome[0x20]; 3922 3923 u8 reserved_1[0x40]; 3924 }; 3925 3926 struct mlx5_ifc_set_fte_in_bits { 3927 u8 opcode[0x10]; 3928 u8 reserved_0[0x10]; 3929 3930 u8 reserved_1[0x10]; 3931 u8 op_mod[0x10]; 3932 3933 u8 other_vport[0x1]; 3934 u8 reserved_2[0xf]; 3935 u8 vport_number[0x10]; 3936 3937 u8 reserved_3[0x20]; 3938 3939 u8 table_type[0x8]; 3940 u8 reserved_4[0x18]; 3941 3942 u8 reserved_5[0x8]; 3943 u8 table_id[0x18]; 3944 3945 u8 reserved_6[0x18]; 3946 u8 modify_enable_mask[0x8]; 3947 3948 u8 reserved_7[0x20]; 3949 3950 u8 flow_index[0x20]; 3951 3952 u8 reserved_8[0xe0]; 3953 3954 struct mlx5_ifc_flow_context_bits flow_context; 3955 }; 3956 3957 struct mlx5_ifc_set_driver_version_out_bits { 3958 u8 status[0x8]; 3959 u8 reserved_0[0x18]; 3960 3961 u8 syndrome[0x20]; 3962 3963 u8 reserved_1[0x40]; 3964 }; 3965 3966 struct mlx5_ifc_set_driver_version_in_bits { 3967 u8 opcode[0x10]; 3968 u8 reserved_0[0x10]; 3969 3970 u8 reserved_1[0x10]; 3971 u8 op_mod[0x10]; 3972 3973 u8 reserved_2[0x40]; 3974 3975 u8 driver_version[64][0x8]; 3976 }; 3977 3978 struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3979 u8 status[0x8]; 3980 u8 reserved_0[0x18]; 3981 3982 u8 syndrome[0x20]; 3983 3984 u8 reserved_1[0x40]; 3985 }; 3986 3987 struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3988 u8 opcode[0x10]; 3989 u8 reserved_0[0x10]; 3990 3991 u8 reserved_1[0x10]; 3992 u8 op_mod[0x10]; 3993 3994 u8 enable[0x1]; 3995 u8 reserved_2[0x1f]; 3996 3997 u8 reserved_3[0x160]; 3998 3999 struct mlx5_ifc_cmd_pas_bits pas; 4000 }; 4001 4002 struct mlx5_ifc_set_burst_size_out_bits { 4003 u8 status[0x8]; 4004 u8 reserved_0[0x18]; 4005 4006 u8 syndrome[0x20]; 4007 4008 u8 reserved_1[0x40]; 4009 }; 4010 4011 struct mlx5_ifc_set_burst_size_in_bits { 4012 u8 opcode[0x10]; 4013 u8 reserved_0[0x10]; 4014 4015 u8 reserved_1[0x10]; 4016 u8 op_mod[0x10]; 4017 4018 u8 reserved_2[0x20]; 4019 4020 u8 reserved_3[0x9]; 4021 u8 device_burst_size[0x17]; 4022 }; 4023 4024 struct mlx5_ifc_rts2rts_qp_out_bits { 4025 u8 status[0x8]; 4026 u8 reserved_0[0x18]; 4027 4028 u8 syndrome[0x20]; 4029 4030 u8 reserved_1[0x40]; 4031 }; 4032 4033 struct mlx5_ifc_rts2rts_qp_in_bits { 4034 u8 opcode[0x10]; 4035 u8 uid[0x10]; 4036 4037 u8 reserved_1[0x10]; 4038 u8 op_mod[0x10]; 4039 4040 u8 reserved_2[0x8]; 4041 u8 qpn[0x18]; 4042 4043 u8 reserved_3[0x20]; 4044 4045 u8 opt_param_mask[0x20]; 4046 4047 u8 reserved_4[0x20]; 4048 4049 struct mlx5_ifc_qpc_bits qpc; 4050 4051 u8 reserved_5[0x80]; 4052 }; 4053 4054 struct mlx5_ifc_rtr2rts_qp_out_bits { 4055 u8 status[0x8]; 4056 u8 reserved_0[0x18]; 4057 4058 u8 syndrome[0x20]; 4059 4060 u8 reserved_1[0x40]; 4061 }; 4062 4063 struct mlx5_ifc_rtr2rts_qp_in_bits { 4064 u8 opcode[0x10]; 4065 u8 uid[0x10]; 4066 4067 u8 reserved_1[0x10]; 4068 u8 op_mod[0x10]; 4069 4070 u8 reserved_2[0x8]; 4071 u8 qpn[0x18]; 4072 4073 u8 reserved_3[0x20]; 4074 4075 u8 opt_param_mask[0x20]; 4076 4077 u8 reserved_4[0x20]; 4078 4079 struct mlx5_ifc_qpc_bits qpc; 4080 4081 u8 reserved_5[0x80]; 4082 }; 4083 4084 struct mlx5_ifc_rst2init_qp_out_bits { 4085 u8 status[0x8]; 4086 u8 reserved_0[0x18]; 4087 4088 u8 syndrome[0x20]; 4089 4090 u8 reserved_1[0x40]; 4091 }; 4092 4093 struct mlx5_ifc_rst2init_qp_in_bits { 4094 u8 opcode[0x10]; 4095 u8 uid[0x10]; 4096 4097 u8 reserved_1[0x10]; 4098 u8 op_mod[0x10]; 4099 4100 u8 reserved_2[0x8]; 4101 u8 qpn[0x18]; 4102 4103 u8 reserved_3[0x20]; 4104 4105 u8 opt_param_mask[0x20]; 4106 4107 u8 reserved_4[0x20]; 4108 4109 struct mlx5_ifc_qpc_bits qpc; 4110 4111 u8 reserved_5[0x80]; 4112 }; 4113 4114 struct mlx5_ifc_query_xrq_out_bits { 4115 u8 status[0x8]; 4116 u8 reserved_at_8[0x18]; 4117 4118 u8 syndrome[0x20]; 4119 4120 u8 reserved_at_40[0x40]; 4121 4122 struct mlx5_ifc_xrqc_bits xrq_context; 4123 }; 4124 4125 struct mlx5_ifc_query_xrq_in_bits { 4126 u8 opcode[0x10]; 4127 u8 reserved_at_10[0x10]; 4128 4129 u8 reserved_at_20[0x10]; 4130 u8 op_mod[0x10]; 4131 4132 u8 reserved_at_40[0x8]; 4133 u8 xrqn[0x18]; 4134 4135 u8 reserved_at_60[0x20]; 4136 }; 4137 4138 struct mlx5_ifc_resume_qp_out_bits { 4139 u8 status[0x8]; 4140 u8 reserved_0[0x18]; 4141 4142 u8 syndrome[0x20]; 4143 4144 u8 reserved_1[0x40]; 4145 }; 4146 4147 struct mlx5_ifc_resume_qp_in_bits { 4148 u8 opcode[0x10]; 4149 u8 reserved_0[0x10]; 4150 4151 u8 reserved_1[0x10]; 4152 u8 op_mod[0x10]; 4153 4154 u8 reserved_2[0x8]; 4155 u8 qpn[0x18]; 4156 4157 u8 reserved_3[0x20]; 4158 }; 4159 4160 struct mlx5_ifc_query_xrc_srq_out_bits { 4161 u8 status[0x8]; 4162 u8 reserved_0[0x18]; 4163 4164 u8 syndrome[0x20]; 4165 4166 u8 reserved_1[0x40]; 4167 4168 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4169 4170 u8 reserved_2[0x600]; 4171 4172 u8 pas[0][0x40]; 4173 }; 4174 4175 struct mlx5_ifc_query_xrc_srq_in_bits { 4176 u8 opcode[0x10]; 4177 u8 uid[0x10]; 4178 4179 u8 reserved_1[0x10]; 4180 u8 op_mod[0x10]; 4181 4182 u8 reserved_2[0x8]; 4183 u8 xrc_srqn[0x18]; 4184 4185 u8 reserved_3[0x20]; 4186 }; 4187 4188 struct mlx5_ifc_query_wol_rol_out_bits { 4189 u8 status[0x8]; 4190 u8 reserved_0[0x18]; 4191 4192 u8 syndrome[0x20]; 4193 4194 u8 reserved_1[0x10]; 4195 u8 rol_mode[0x8]; 4196 u8 wol_mode[0x8]; 4197 4198 u8 reserved_2[0x20]; 4199 }; 4200 4201 struct mlx5_ifc_query_wol_rol_in_bits { 4202 u8 opcode[0x10]; 4203 u8 reserved_0[0x10]; 4204 4205 u8 reserved_1[0x10]; 4206 u8 op_mod[0x10]; 4207 4208 u8 reserved_2[0x40]; 4209 }; 4210 4211 enum { 4212 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4213 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4214 }; 4215 4216 struct mlx5_ifc_query_vport_state_out_bits { 4217 u8 status[0x8]; 4218 u8 reserved_0[0x18]; 4219 4220 u8 syndrome[0x20]; 4221 4222 u8 reserved_1[0x20]; 4223 4224 u8 reserved_2[0x18]; 4225 u8 admin_state[0x4]; 4226 u8 state[0x4]; 4227 }; 4228 4229 enum { 4230 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 4231 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 4232 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 4233 }; 4234 4235 struct mlx5_ifc_query_vport_state_in_bits { 4236 u8 opcode[0x10]; 4237 u8 reserved_0[0x10]; 4238 4239 u8 reserved_1[0x10]; 4240 u8 op_mod[0x10]; 4241 4242 u8 other_vport[0x1]; 4243 u8 reserved_2[0xf]; 4244 u8 vport_number[0x10]; 4245 4246 u8 reserved_3[0x20]; 4247 }; 4248 4249 struct mlx5_ifc_query_vnic_env_out_bits { 4250 u8 status[0x8]; 4251 u8 reserved_at_8[0x18]; 4252 4253 u8 syndrome[0x20]; 4254 4255 u8 reserved_at_40[0x40]; 4256 4257 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4258 }; 4259 4260 enum { 4261 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4262 }; 4263 4264 struct mlx5_ifc_query_vnic_env_in_bits { 4265 u8 opcode[0x10]; 4266 u8 reserved_at_10[0x10]; 4267 4268 u8 reserved_at_20[0x10]; 4269 u8 op_mod[0x10]; 4270 4271 u8 other_vport[0x1]; 4272 u8 reserved_at_41[0xf]; 4273 u8 vport_number[0x10]; 4274 4275 u8 reserved_at_60[0x20]; 4276 }; 4277 4278 struct mlx5_ifc_query_vport_counter_out_bits { 4279 u8 status[0x8]; 4280 u8 reserved_0[0x18]; 4281 4282 u8 syndrome[0x20]; 4283 4284 u8 reserved_1[0x40]; 4285 4286 struct mlx5_ifc_traffic_counter_bits received_errors; 4287 4288 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4289 4290 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4291 4292 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4293 4294 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4295 4296 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4297 4298 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4299 4300 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4301 4302 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4303 4304 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4305 4306 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4307 4308 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4309 4310 u8 reserved_2[0xa00]; 4311 }; 4312 4313 enum { 4314 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4315 }; 4316 4317 struct mlx5_ifc_query_vport_counter_in_bits { 4318 u8 opcode[0x10]; 4319 u8 reserved_0[0x10]; 4320 4321 u8 reserved_1[0x10]; 4322 u8 op_mod[0x10]; 4323 4324 u8 other_vport[0x1]; 4325 u8 reserved_2[0xb]; 4326 u8 port_num[0x4]; 4327 u8 vport_number[0x10]; 4328 4329 u8 reserved_3[0x60]; 4330 4331 u8 clear[0x1]; 4332 u8 reserved_4[0x1f]; 4333 4334 u8 reserved_5[0x20]; 4335 }; 4336 4337 struct mlx5_ifc_query_tis_out_bits { 4338 u8 status[0x8]; 4339 u8 reserved_0[0x18]; 4340 4341 u8 syndrome[0x20]; 4342 4343 u8 reserved_1[0x40]; 4344 4345 struct mlx5_ifc_tisc_bits tis_context; 4346 }; 4347 4348 struct mlx5_ifc_query_tis_in_bits { 4349 u8 opcode[0x10]; 4350 u8 reserved_0[0x10]; 4351 4352 u8 reserved_1[0x10]; 4353 u8 op_mod[0x10]; 4354 4355 u8 reserved_2[0x8]; 4356 u8 tisn[0x18]; 4357 4358 u8 reserved_3[0x20]; 4359 }; 4360 4361 struct mlx5_ifc_query_tir_out_bits { 4362 u8 status[0x8]; 4363 u8 reserved_0[0x18]; 4364 4365 u8 syndrome[0x20]; 4366 4367 u8 reserved_1[0xc0]; 4368 4369 struct mlx5_ifc_tirc_bits tir_context; 4370 }; 4371 4372 struct mlx5_ifc_query_tir_in_bits { 4373 u8 opcode[0x10]; 4374 u8 reserved_0[0x10]; 4375 4376 u8 reserved_1[0x10]; 4377 u8 op_mod[0x10]; 4378 4379 u8 reserved_2[0x8]; 4380 u8 tirn[0x18]; 4381 4382 u8 reserved_3[0x20]; 4383 }; 4384 4385 struct mlx5_ifc_query_srq_out_bits { 4386 u8 status[0x8]; 4387 u8 reserved_0[0x18]; 4388 4389 u8 syndrome[0x20]; 4390 4391 u8 reserved_1[0x40]; 4392 4393 struct mlx5_ifc_srqc_bits srq_context_entry; 4394 4395 u8 reserved_2[0x600]; 4396 4397 u8 pas[0][0x40]; 4398 }; 4399 4400 struct mlx5_ifc_query_srq_in_bits { 4401 u8 opcode[0x10]; 4402 u8 reserved_0[0x10]; 4403 4404 u8 reserved_1[0x10]; 4405 u8 op_mod[0x10]; 4406 4407 u8 reserved_2[0x8]; 4408 u8 srqn[0x18]; 4409 4410 u8 reserved_3[0x20]; 4411 }; 4412 4413 struct mlx5_ifc_query_sq_out_bits { 4414 u8 status[0x8]; 4415 u8 reserved_0[0x18]; 4416 4417 u8 syndrome[0x20]; 4418 4419 u8 reserved_1[0xc0]; 4420 4421 struct mlx5_ifc_sqc_bits sq_context; 4422 }; 4423 4424 struct mlx5_ifc_query_sq_in_bits { 4425 u8 opcode[0x10]; 4426 u8 reserved_0[0x10]; 4427 4428 u8 reserved_1[0x10]; 4429 u8 op_mod[0x10]; 4430 4431 u8 reserved_2[0x8]; 4432 u8 sqn[0x18]; 4433 4434 u8 reserved_3[0x20]; 4435 }; 4436 4437 struct mlx5_ifc_query_special_contexts_out_bits { 4438 u8 status[0x8]; 4439 u8 reserved_0[0x18]; 4440 4441 u8 syndrome[0x20]; 4442 4443 u8 dump_fill_mkey[0x20]; 4444 4445 u8 resd_lkey[0x20]; 4446 }; 4447 4448 struct mlx5_ifc_query_special_contexts_in_bits { 4449 u8 opcode[0x10]; 4450 u8 reserved_0[0x10]; 4451 4452 u8 reserved_1[0x10]; 4453 u8 op_mod[0x10]; 4454 4455 u8 reserved_2[0x40]; 4456 }; 4457 4458 struct mlx5_ifc_query_scheduling_element_out_bits { 4459 u8 status[0x8]; 4460 u8 reserved_at_8[0x18]; 4461 4462 u8 syndrome[0x20]; 4463 4464 u8 reserved_at_40[0xc0]; 4465 4466 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4467 4468 u8 reserved_at_300[0x100]; 4469 }; 4470 4471 enum { 4472 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4473 }; 4474 4475 struct mlx5_ifc_query_scheduling_element_in_bits { 4476 u8 opcode[0x10]; 4477 u8 reserved_at_10[0x10]; 4478 4479 u8 reserved_at_20[0x10]; 4480 u8 op_mod[0x10]; 4481 4482 u8 scheduling_hierarchy[0x8]; 4483 u8 reserved_at_48[0x18]; 4484 4485 u8 scheduling_element_id[0x20]; 4486 4487 u8 reserved_at_80[0x180]; 4488 }; 4489 4490 struct mlx5_ifc_query_rqt_out_bits { 4491 u8 status[0x8]; 4492 u8 reserved_0[0x18]; 4493 4494 u8 syndrome[0x20]; 4495 4496 u8 reserved_1[0xc0]; 4497 4498 struct mlx5_ifc_rqtc_bits rqt_context; 4499 }; 4500 4501 struct mlx5_ifc_query_rqt_in_bits { 4502 u8 opcode[0x10]; 4503 u8 reserved_0[0x10]; 4504 4505 u8 reserved_1[0x10]; 4506 u8 op_mod[0x10]; 4507 4508 u8 reserved_2[0x8]; 4509 u8 rqtn[0x18]; 4510 4511 u8 reserved_3[0x20]; 4512 }; 4513 4514 struct mlx5_ifc_query_rq_out_bits { 4515 u8 status[0x8]; 4516 u8 reserved_0[0x18]; 4517 4518 u8 syndrome[0x20]; 4519 4520 u8 reserved_1[0xc0]; 4521 4522 struct mlx5_ifc_rqc_bits rq_context; 4523 }; 4524 4525 struct mlx5_ifc_query_rq_in_bits { 4526 u8 opcode[0x10]; 4527 u8 reserved_0[0x10]; 4528 4529 u8 reserved_1[0x10]; 4530 u8 op_mod[0x10]; 4531 4532 u8 reserved_2[0x8]; 4533 u8 rqn[0x18]; 4534 4535 u8 reserved_3[0x20]; 4536 }; 4537 4538 struct mlx5_ifc_query_roce_address_out_bits { 4539 u8 status[0x8]; 4540 u8 reserved_0[0x18]; 4541 4542 u8 syndrome[0x20]; 4543 4544 u8 reserved_1[0x40]; 4545 4546 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4547 }; 4548 4549 struct mlx5_ifc_query_roce_address_in_bits { 4550 u8 opcode[0x10]; 4551 u8 reserved_0[0x10]; 4552 4553 u8 reserved_1[0x10]; 4554 u8 op_mod[0x10]; 4555 4556 u8 roce_address_index[0x10]; 4557 u8 reserved_2[0x10]; 4558 4559 u8 reserved_3[0x20]; 4560 }; 4561 4562 struct mlx5_ifc_query_rmp_out_bits { 4563 u8 status[0x8]; 4564 u8 reserved_0[0x18]; 4565 4566 u8 syndrome[0x20]; 4567 4568 u8 reserved_1[0xc0]; 4569 4570 struct mlx5_ifc_rmpc_bits rmp_context; 4571 }; 4572 4573 struct mlx5_ifc_query_rmp_in_bits { 4574 u8 opcode[0x10]; 4575 u8 reserved_0[0x10]; 4576 4577 u8 reserved_1[0x10]; 4578 u8 op_mod[0x10]; 4579 4580 u8 reserved_2[0x8]; 4581 u8 rmpn[0x18]; 4582 4583 u8 reserved_3[0x20]; 4584 }; 4585 4586 struct mlx5_ifc_query_rdb_out_bits { 4587 u8 status[0x8]; 4588 u8 reserved_0[0x18]; 4589 4590 u8 syndrome[0x20]; 4591 4592 u8 reserved_1[0x20]; 4593 4594 u8 reserved_2[0x18]; 4595 u8 rdb_list_size[0x8]; 4596 4597 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4598 }; 4599 4600 struct mlx5_ifc_query_rdb_in_bits { 4601 u8 opcode[0x10]; 4602 u8 reserved_0[0x10]; 4603 4604 u8 reserved_1[0x10]; 4605 u8 op_mod[0x10]; 4606 4607 u8 reserved_2[0x8]; 4608 u8 qpn[0x18]; 4609 4610 u8 reserved_3[0x20]; 4611 }; 4612 4613 struct mlx5_ifc_query_qp_out_bits { 4614 u8 status[0x8]; 4615 u8 reserved_0[0x18]; 4616 4617 u8 syndrome[0x20]; 4618 4619 u8 reserved_1[0x40]; 4620 4621 u8 opt_param_mask[0x20]; 4622 4623 u8 reserved_2[0x20]; 4624 4625 struct mlx5_ifc_qpc_bits qpc; 4626 4627 u8 reserved_3[0x80]; 4628 4629 u8 pas[0][0x40]; 4630 }; 4631 4632 struct mlx5_ifc_query_qp_in_bits { 4633 u8 opcode[0x10]; 4634 u8 reserved_0[0x10]; 4635 4636 u8 reserved_1[0x10]; 4637 u8 op_mod[0x10]; 4638 4639 u8 reserved_2[0x8]; 4640 u8 qpn[0x18]; 4641 4642 u8 reserved_3[0x20]; 4643 }; 4644 4645 struct mlx5_ifc_query_q_counter_out_bits { 4646 u8 status[0x8]; 4647 u8 reserved_0[0x18]; 4648 4649 u8 syndrome[0x20]; 4650 4651 u8 reserved_1[0x40]; 4652 4653 u8 rx_write_requests[0x20]; 4654 4655 u8 reserved_2[0x20]; 4656 4657 u8 rx_read_requests[0x20]; 4658 4659 u8 reserved_3[0x20]; 4660 4661 u8 rx_atomic_requests[0x20]; 4662 4663 u8 reserved_4[0x20]; 4664 4665 u8 rx_dct_connect[0x20]; 4666 4667 u8 reserved_5[0x20]; 4668 4669 u8 out_of_buffer[0x20]; 4670 4671 u8 reserved_7[0x20]; 4672 4673 u8 out_of_sequence[0x20]; 4674 4675 u8 reserved_8[0x20]; 4676 4677 u8 duplicate_request[0x20]; 4678 4679 u8 reserved_9[0x20]; 4680 4681 u8 rnr_nak_retry_err[0x20]; 4682 4683 u8 reserved_10[0x20]; 4684 4685 u8 packet_seq_err[0x20]; 4686 4687 u8 reserved_11[0x20]; 4688 4689 u8 implied_nak_seq_err[0x20]; 4690 4691 u8 reserved_12[0x20]; 4692 4693 u8 local_ack_timeout_err[0x20]; 4694 4695 u8 reserved_13[0x20]; 4696 4697 u8 resp_rnr_nak[0x20]; 4698 4699 u8 reserved_14[0x20]; 4700 4701 u8 req_rnr_retries_exceeded[0x20]; 4702 4703 u8 reserved_15[0x460]; 4704 }; 4705 4706 struct mlx5_ifc_query_q_counter_in_bits { 4707 u8 opcode[0x10]; 4708 u8 reserved_0[0x10]; 4709 4710 u8 reserved_1[0x10]; 4711 u8 op_mod[0x10]; 4712 4713 u8 reserved_2[0x80]; 4714 4715 u8 clear[0x1]; 4716 u8 reserved_3[0x1f]; 4717 4718 u8 reserved_4[0x18]; 4719 u8 counter_set_id[0x8]; 4720 }; 4721 4722 struct mlx5_ifc_query_pages_out_bits { 4723 u8 status[0x8]; 4724 u8 reserved_0[0x18]; 4725 4726 u8 syndrome[0x20]; 4727 4728 u8 reserved_1[0x10]; 4729 u8 function_id[0x10]; 4730 4731 u8 num_pages[0x20]; 4732 }; 4733 4734 enum { 4735 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4736 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4737 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4738 }; 4739 4740 struct mlx5_ifc_query_pages_in_bits { 4741 u8 opcode[0x10]; 4742 u8 reserved_0[0x10]; 4743 4744 u8 reserved_1[0x10]; 4745 u8 op_mod[0x10]; 4746 4747 u8 reserved_2[0x10]; 4748 u8 function_id[0x10]; 4749 4750 u8 reserved_3[0x20]; 4751 }; 4752 4753 struct mlx5_ifc_query_nic_vport_context_out_bits { 4754 u8 status[0x8]; 4755 u8 reserved_0[0x18]; 4756 4757 u8 syndrome[0x20]; 4758 4759 u8 reserved_1[0x40]; 4760 4761 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4762 }; 4763 4764 struct mlx5_ifc_query_nic_vport_context_in_bits { 4765 u8 opcode[0x10]; 4766 u8 reserved_0[0x10]; 4767 4768 u8 reserved_1[0x10]; 4769 u8 op_mod[0x10]; 4770 4771 u8 other_vport[0x1]; 4772 u8 reserved_2[0xf]; 4773 u8 vport_number[0x10]; 4774 4775 u8 reserved_3[0x5]; 4776 u8 allowed_list_type[0x3]; 4777 u8 reserved_4[0x18]; 4778 }; 4779 4780 struct mlx5_ifc_query_mkey_out_bits { 4781 u8 status[0x8]; 4782 u8 reserved_0[0x18]; 4783 4784 u8 syndrome[0x20]; 4785 4786 u8 reserved_1[0x40]; 4787 4788 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4789 4790 u8 reserved_2[0x600]; 4791 4792 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4793 4794 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4795 }; 4796 4797 struct mlx5_ifc_query_mkey_in_bits { 4798 u8 opcode[0x10]; 4799 u8 reserved_0[0x10]; 4800 4801 u8 reserved_1[0x10]; 4802 u8 op_mod[0x10]; 4803 4804 u8 reserved_2[0x8]; 4805 u8 mkey_index[0x18]; 4806 4807 u8 pg_access[0x1]; 4808 u8 reserved_3[0x1f]; 4809 }; 4810 4811 struct mlx5_ifc_query_mad_demux_out_bits { 4812 u8 status[0x8]; 4813 u8 reserved_0[0x18]; 4814 4815 u8 syndrome[0x20]; 4816 4817 u8 reserved_1[0x40]; 4818 4819 u8 mad_dumux_parameters_block[0x20]; 4820 }; 4821 4822 struct mlx5_ifc_query_mad_demux_in_bits { 4823 u8 opcode[0x10]; 4824 u8 reserved_0[0x10]; 4825 4826 u8 reserved_1[0x10]; 4827 u8 op_mod[0x10]; 4828 4829 u8 reserved_2[0x40]; 4830 }; 4831 4832 struct mlx5_ifc_query_l2_table_entry_out_bits { 4833 u8 status[0x8]; 4834 u8 reserved_0[0x18]; 4835 4836 u8 syndrome[0x20]; 4837 4838 u8 reserved_1[0xa0]; 4839 4840 u8 reserved_2[0x13]; 4841 u8 vlan_valid[0x1]; 4842 u8 vlan[0xc]; 4843 4844 struct mlx5_ifc_mac_address_layout_bits mac_address; 4845 4846 u8 reserved_3[0xc0]; 4847 }; 4848 4849 struct mlx5_ifc_query_l2_table_entry_in_bits { 4850 u8 opcode[0x10]; 4851 u8 reserved_0[0x10]; 4852 4853 u8 reserved_1[0x10]; 4854 u8 op_mod[0x10]; 4855 4856 u8 reserved_2[0x60]; 4857 4858 u8 reserved_3[0x8]; 4859 u8 table_index[0x18]; 4860 4861 u8 reserved_4[0x140]; 4862 }; 4863 4864 struct mlx5_ifc_query_issi_out_bits { 4865 u8 status[0x8]; 4866 u8 reserved_0[0x18]; 4867 4868 u8 syndrome[0x20]; 4869 4870 u8 reserved_1[0x10]; 4871 u8 current_issi[0x10]; 4872 4873 u8 reserved_2[0xa0]; 4874 4875 u8 supported_issi_reserved[76][0x8]; 4876 u8 supported_issi_dw0[0x20]; 4877 }; 4878 4879 struct mlx5_ifc_query_issi_in_bits { 4880 u8 opcode[0x10]; 4881 u8 reserved_0[0x10]; 4882 4883 u8 reserved_1[0x10]; 4884 u8 op_mod[0x10]; 4885 4886 u8 reserved_2[0x40]; 4887 }; 4888 4889 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4890 u8 status[0x8]; 4891 u8 reserved_0[0x18]; 4892 4893 u8 syndrome[0x20]; 4894 4895 u8 reserved_1[0x40]; 4896 4897 struct mlx5_ifc_pkey_bits pkey[0]; 4898 }; 4899 4900 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4901 u8 opcode[0x10]; 4902 u8 reserved_0[0x10]; 4903 4904 u8 reserved_1[0x10]; 4905 u8 op_mod[0x10]; 4906 4907 u8 other_vport[0x1]; 4908 u8 reserved_2[0xb]; 4909 u8 port_num[0x4]; 4910 u8 vport_number[0x10]; 4911 4912 u8 reserved_3[0x10]; 4913 u8 pkey_index[0x10]; 4914 }; 4915 4916 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4917 u8 status[0x8]; 4918 u8 reserved_0[0x18]; 4919 4920 u8 syndrome[0x20]; 4921 4922 u8 reserved_1[0x20]; 4923 4924 u8 gids_num[0x10]; 4925 u8 reserved_2[0x10]; 4926 4927 struct mlx5_ifc_array128_auto_bits gid[0]; 4928 }; 4929 4930 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4931 u8 opcode[0x10]; 4932 u8 reserved_0[0x10]; 4933 4934 u8 reserved_1[0x10]; 4935 u8 op_mod[0x10]; 4936 4937 u8 other_vport[0x1]; 4938 u8 reserved_2[0xb]; 4939 u8 port_num[0x4]; 4940 u8 vport_number[0x10]; 4941 4942 u8 reserved_3[0x10]; 4943 u8 gid_index[0x10]; 4944 }; 4945 4946 struct mlx5_ifc_query_hca_vport_context_out_bits { 4947 u8 status[0x8]; 4948 u8 reserved_0[0x18]; 4949 4950 u8 syndrome[0x20]; 4951 4952 u8 reserved_1[0x40]; 4953 4954 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4955 }; 4956 4957 struct mlx5_ifc_query_hca_vport_context_in_bits { 4958 u8 opcode[0x10]; 4959 u8 reserved_0[0x10]; 4960 4961 u8 reserved_1[0x10]; 4962 u8 op_mod[0x10]; 4963 4964 u8 other_vport[0x1]; 4965 u8 reserved_2[0xb]; 4966 u8 port_num[0x4]; 4967 u8 vport_number[0x10]; 4968 4969 u8 reserved_3[0x20]; 4970 }; 4971 4972 struct mlx5_ifc_query_hca_cap_out_bits { 4973 u8 status[0x8]; 4974 u8 reserved_0[0x18]; 4975 4976 u8 syndrome[0x20]; 4977 4978 u8 reserved_1[0x40]; 4979 4980 union mlx5_ifc_hca_cap_union_bits capability; 4981 }; 4982 4983 struct mlx5_ifc_query_hca_cap_in_bits { 4984 u8 opcode[0x10]; 4985 u8 reserved_0[0x10]; 4986 4987 u8 reserved_1[0x10]; 4988 u8 op_mod[0x10]; 4989 4990 u8 reserved_2[0x40]; 4991 }; 4992 4993 struct mlx5_ifc_query_flow_table_out_bits { 4994 u8 status[0x8]; 4995 u8 reserved_at_8[0x18]; 4996 4997 u8 syndrome[0x20]; 4998 4999 u8 reserved_at_40[0x80]; 5000 5001 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5002 }; 5003 5004 struct mlx5_ifc_query_flow_table_in_bits { 5005 u8 opcode[0x10]; 5006 u8 reserved_0[0x10]; 5007 5008 u8 reserved_1[0x10]; 5009 u8 op_mod[0x10]; 5010 5011 u8 other_vport[0x1]; 5012 u8 reserved_2[0xf]; 5013 u8 vport_number[0x10]; 5014 5015 u8 reserved_3[0x20]; 5016 5017 u8 table_type[0x8]; 5018 u8 reserved_4[0x18]; 5019 5020 u8 reserved_5[0x8]; 5021 u8 table_id[0x18]; 5022 5023 u8 reserved_6[0x140]; 5024 }; 5025 5026 struct mlx5_ifc_query_fte_out_bits { 5027 u8 status[0x8]; 5028 u8 reserved_0[0x18]; 5029 5030 u8 syndrome[0x20]; 5031 5032 u8 reserved_1[0x1c0]; 5033 5034 struct mlx5_ifc_flow_context_bits flow_context; 5035 }; 5036 5037 struct mlx5_ifc_query_fte_in_bits { 5038 u8 opcode[0x10]; 5039 u8 reserved_0[0x10]; 5040 5041 u8 reserved_1[0x10]; 5042 u8 op_mod[0x10]; 5043 5044 u8 other_vport[0x1]; 5045 u8 reserved_2[0xf]; 5046 u8 vport_number[0x10]; 5047 5048 u8 reserved_3[0x20]; 5049 5050 u8 table_type[0x8]; 5051 u8 reserved_4[0x18]; 5052 5053 u8 reserved_5[0x8]; 5054 u8 table_id[0x18]; 5055 5056 u8 reserved_6[0x40]; 5057 5058 u8 flow_index[0x20]; 5059 5060 u8 reserved_7[0xe0]; 5061 }; 5062 5063 enum { 5064 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5065 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5066 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5067 }; 5068 5069 struct mlx5_ifc_query_flow_group_out_bits { 5070 u8 status[0x8]; 5071 u8 reserved_0[0x18]; 5072 5073 u8 syndrome[0x20]; 5074 5075 u8 reserved_1[0xa0]; 5076 5077 u8 start_flow_index[0x20]; 5078 5079 u8 reserved_2[0x20]; 5080 5081 u8 end_flow_index[0x20]; 5082 5083 u8 reserved_3[0xa0]; 5084 5085 u8 reserved_4[0x18]; 5086 u8 match_criteria_enable[0x8]; 5087 5088 struct mlx5_ifc_fte_match_param_bits match_criteria; 5089 5090 u8 reserved_5[0xe00]; 5091 }; 5092 5093 struct mlx5_ifc_query_flow_group_in_bits { 5094 u8 opcode[0x10]; 5095 u8 reserved_0[0x10]; 5096 5097 u8 reserved_1[0x10]; 5098 u8 op_mod[0x10]; 5099 5100 u8 other_vport[0x1]; 5101 u8 reserved_2[0xf]; 5102 u8 vport_number[0x10]; 5103 5104 u8 reserved_3[0x20]; 5105 5106 u8 table_type[0x8]; 5107 u8 reserved_4[0x18]; 5108 5109 u8 reserved_5[0x8]; 5110 u8 table_id[0x18]; 5111 5112 u8 group_id[0x20]; 5113 5114 u8 reserved_6[0x120]; 5115 }; 5116 5117 struct mlx5_ifc_query_flow_counter_out_bits { 5118 u8 status[0x8]; 5119 u8 reserved_at_8[0x18]; 5120 5121 u8 syndrome[0x20]; 5122 5123 u8 reserved_at_40[0x40]; 5124 5125 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 5126 }; 5127 5128 struct mlx5_ifc_query_flow_counter_in_bits { 5129 u8 opcode[0x10]; 5130 u8 reserved_at_10[0x10]; 5131 5132 u8 reserved_at_20[0x10]; 5133 u8 op_mod[0x10]; 5134 5135 u8 reserved_at_40[0x80]; 5136 5137 u8 clear[0x1]; 5138 u8 reserved_at_c1[0xf]; 5139 u8 num_of_counters[0x10]; 5140 5141 u8 reserved_at_e0[0x10]; 5142 u8 flow_counter_id[0x10]; 5143 }; 5144 5145 struct mlx5_ifc_query_esw_vport_context_out_bits { 5146 u8 status[0x8]; 5147 u8 reserved_0[0x18]; 5148 5149 u8 syndrome[0x20]; 5150 5151 u8 reserved_1[0x40]; 5152 5153 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5154 }; 5155 5156 struct mlx5_ifc_query_esw_vport_context_in_bits { 5157 u8 opcode[0x10]; 5158 u8 reserved_0[0x10]; 5159 5160 u8 reserved_1[0x10]; 5161 u8 op_mod[0x10]; 5162 5163 u8 other_vport[0x1]; 5164 u8 reserved_2[0xf]; 5165 u8 vport_number[0x10]; 5166 5167 u8 reserved_3[0x20]; 5168 }; 5169 5170 struct mlx5_ifc_query_eq_out_bits { 5171 u8 status[0x8]; 5172 u8 reserved_0[0x18]; 5173 5174 u8 syndrome[0x20]; 5175 5176 u8 reserved_1[0x40]; 5177 5178 struct mlx5_ifc_eqc_bits eq_context_entry; 5179 5180 u8 reserved_2[0x40]; 5181 5182 u8 event_bitmask[0x40]; 5183 5184 u8 reserved_3[0x580]; 5185 5186 u8 pas[0][0x40]; 5187 }; 5188 5189 struct mlx5_ifc_query_eq_in_bits { 5190 u8 opcode[0x10]; 5191 u8 reserved_0[0x10]; 5192 5193 u8 reserved_1[0x10]; 5194 u8 op_mod[0x10]; 5195 5196 u8 reserved_2[0x18]; 5197 u8 eq_number[0x8]; 5198 5199 u8 reserved_3[0x20]; 5200 }; 5201 5202 struct mlx5_ifc_query_dct_out_bits { 5203 u8 status[0x8]; 5204 u8 reserved_0[0x18]; 5205 5206 u8 syndrome[0x20]; 5207 5208 u8 reserved_1[0x40]; 5209 5210 struct mlx5_ifc_dctc_bits dct_context_entry; 5211 5212 u8 reserved_2[0x180]; 5213 }; 5214 5215 struct mlx5_ifc_query_dct_in_bits { 5216 u8 opcode[0x10]; 5217 u8 reserved_0[0x10]; 5218 5219 u8 reserved_1[0x10]; 5220 u8 op_mod[0x10]; 5221 5222 u8 reserved_2[0x8]; 5223 u8 dctn[0x18]; 5224 5225 u8 reserved_3[0x20]; 5226 }; 5227 5228 struct mlx5_ifc_query_dc_cnak_trace_out_bits { 5229 u8 status[0x8]; 5230 u8 reserved_0[0x18]; 5231 5232 u8 syndrome[0x20]; 5233 5234 u8 enable[0x1]; 5235 u8 reserved_1[0x1f]; 5236 5237 u8 reserved_2[0x160]; 5238 5239 struct mlx5_ifc_cmd_pas_bits pas; 5240 }; 5241 5242 struct mlx5_ifc_query_dc_cnak_trace_in_bits { 5243 u8 opcode[0x10]; 5244 u8 reserved_0[0x10]; 5245 5246 u8 reserved_1[0x10]; 5247 u8 op_mod[0x10]; 5248 5249 u8 reserved_2[0x40]; 5250 }; 5251 5252 struct mlx5_ifc_packet_reformat_context_in_bits { 5253 u8 reserved_at_0[0x5]; 5254 u8 reformat_type[0x3]; 5255 u8 reserved_at_8[0xe]; 5256 u8 reformat_data_size[0xa]; 5257 5258 u8 reserved_at_20[0x10]; 5259 u8 reformat_data[2][0x8]; 5260 5261 u8 more_reformat_data[0][0x8]; 5262 }; 5263 5264 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5265 u8 status[0x8]; 5266 u8 reserved_at_8[0x18]; 5267 5268 u8 syndrome[0x20]; 5269 5270 u8 reserved_at_40[0xa0]; 5271 5272 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 5273 }; 5274 5275 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5276 u8 opcode[0x10]; 5277 u8 reserved_at_10[0x10]; 5278 5279 u8 reserved_at_20[0x10]; 5280 u8 op_mod[0x10]; 5281 5282 u8 packet_reformat_id[0x20]; 5283 5284 u8 reserved_at_60[0xa0]; 5285 }; 5286 5287 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5288 u8 status[0x8]; 5289 u8 reserved_at_8[0x18]; 5290 5291 u8 syndrome[0x20]; 5292 5293 u8 packet_reformat_id[0x20]; 5294 5295 u8 reserved_at_60[0x20]; 5296 }; 5297 5298 enum mlx5_reformat_ctx_type { 5299 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5300 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5301 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5302 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5303 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5304 }; 5305 5306 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5307 u8 opcode[0x10]; 5308 u8 reserved_at_10[0x10]; 5309 5310 u8 reserved_at_20[0x10]; 5311 u8 op_mod[0x10]; 5312 5313 u8 reserved_at_40[0xa0]; 5314 5315 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5316 }; 5317 5318 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5319 u8 status[0x8]; 5320 u8 reserved_at_8[0x18]; 5321 5322 u8 syndrome[0x20]; 5323 5324 u8 reserved_at_40[0x40]; 5325 }; 5326 5327 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5328 u8 opcode[0x10]; 5329 u8 reserved_at_10[0x10]; 5330 5331 u8 reserved_20[0x10]; 5332 u8 op_mod[0x10]; 5333 5334 u8 packet_reformat_id[0x20]; 5335 5336 u8 reserved_60[0x20]; 5337 }; 5338 5339 struct mlx5_ifc_diagnostic_cntr_struct_bits { 5340 u8 counter_id[0x10]; 5341 u8 sample_id[0x10]; 5342 5343 u8 time_stamp_31_0[0x20]; 5344 5345 u8 counter_value_h[0x20]; 5346 5347 u8 counter_value_l[0x20]; 5348 }; 5349 5350 enum { 5351 MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_ENABLE = 0x1, 5352 MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_DISABLE = 0x0, 5353 }; 5354 5355 struct mlx5_ifc_query_cq_out_bits { 5356 u8 status[0x8]; 5357 u8 reserved_0[0x18]; 5358 5359 u8 syndrome[0x20]; 5360 5361 u8 reserved_1[0x40]; 5362 5363 struct mlx5_ifc_cqc_bits cq_context; 5364 5365 u8 reserved_2[0x600]; 5366 5367 u8 pas[0][0x40]; 5368 }; 5369 5370 struct mlx5_ifc_query_cq_in_bits { 5371 u8 opcode[0x10]; 5372 u8 reserved_0[0x10]; 5373 5374 u8 reserved_1[0x10]; 5375 u8 op_mod[0x10]; 5376 5377 u8 reserved_2[0x8]; 5378 u8 cqn[0x18]; 5379 5380 u8 reserved_3[0x20]; 5381 }; 5382 5383 struct mlx5_ifc_query_cong_status_out_bits { 5384 u8 status[0x8]; 5385 u8 reserved_0[0x18]; 5386 5387 u8 syndrome[0x20]; 5388 5389 u8 reserved_1[0x20]; 5390 5391 u8 enable[0x1]; 5392 u8 tag_enable[0x1]; 5393 u8 reserved_2[0x1e]; 5394 }; 5395 5396 struct mlx5_ifc_query_cong_status_in_bits { 5397 u8 opcode[0x10]; 5398 u8 reserved_0[0x10]; 5399 5400 u8 reserved_1[0x10]; 5401 u8 op_mod[0x10]; 5402 5403 u8 reserved_2[0x18]; 5404 u8 priority[0x4]; 5405 u8 cong_protocol[0x4]; 5406 5407 u8 reserved_3[0x20]; 5408 }; 5409 5410 struct mlx5_ifc_query_cong_statistics_out_bits { 5411 u8 status[0x8]; 5412 u8 reserved_0[0x18]; 5413 5414 u8 syndrome[0x20]; 5415 5416 u8 reserved_1[0x40]; 5417 5418 u8 rp_cur_flows[0x20]; 5419 5420 u8 sum_flows[0x20]; 5421 5422 u8 rp_cnp_ignored_high[0x20]; 5423 5424 u8 rp_cnp_ignored_low[0x20]; 5425 5426 u8 rp_cnp_handled_high[0x20]; 5427 5428 u8 rp_cnp_handled_low[0x20]; 5429 5430 u8 reserved_2[0x100]; 5431 5432 u8 time_stamp_high[0x20]; 5433 5434 u8 time_stamp_low[0x20]; 5435 5436 u8 accumulators_period[0x20]; 5437 5438 u8 np_ecn_marked_roce_packets_high[0x20]; 5439 5440 u8 np_ecn_marked_roce_packets_low[0x20]; 5441 5442 u8 np_cnp_sent_high[0x20]; 5443 5444 u8 np_cnp_sent_low[0x20]; 5445 5446 u8 reserved_3[0x560]; 5447 }; 5448 5449 struct mlx5_ifc_query_cong_statistics_in_bits { 5450 u8 opcode[0x10]; 5451 u8 reserved_0[0x10]; 5452 5453 u8 reserved_1[0x10]; 5454 u8 op_mod[0x10]; 5455 5456 u8 clear[0x1]; 5457 u8 reserved_2[0x1f]; 5458 5459 u8 reserved_3[0x20]; 5460 }; 5461 5462 struct mlx5_ifc_query_cong_params_out_bits { 5463 u8 status[0x8]; 5464 u8 reserved_0[0x18]; 5465 5466 u8 syndrome[0x20]; 5467 5468 u8 reserved_1[0x40]; 5469 5470 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5471 }; 5472 5473 struct mlx5_ifc_query_cong_params_in_bits { 5474 u8 opcode[0x10]; 5475 u8 reserved_0[0x10]; 5476 5477 u8 reserved_1[0x10]; 5478 u8 op_mod[0x10]; 5479 5480 u8 reserved_2[0x1c]; 5481 u8 cong_protocol[0x4]; 5482 5483 u8 reserved_3[0x20]; 5484 }; 5485 5486 struct mlx5_ifc_query_burst_size_out_bits { 5487 u8 status[0x8]; 5488 u8 reserved_0[0x18]; 5489 5490 u8 syndrome[0x20]; 5491 5492 u8 reserved_1[0x20]; 5493 5494 u8 reserved_2[0x9]; 5495 u8 device_burst_size[0x17]; 5496 }; 5497 5498 struct mlx5_ifc_query_burst_size_in_bits { 5499 u8 opcode[0x10]; 5500 u8 reserved_0[0x10]; 5501 5502 u8 reserved_1[0x10]; 5503 u8 op_mod[0x10]; 5504 5505 u8 reserved_2[0x40]; 5506 }; 5507 5508 struct mlx5_ifc_query_adapter_out_bits { 5509 u8 status[0x8]; 5510 u8 reserved_0[0x18]; 5511 5512 u8 syndrome[0x20]; 5513 5514 u8 reserved_1[0x40]; 5515 5516 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5517 }; 5518 5519 struct mlx5_ifc_query_adapter_in_bits { 5520 u8 opcode[0x10]; 5521 u8 reserved_0[0x10]; 5522 5523 u8 reserved_1[0x10]; 5524 u8 op_mod[0x10]; 5525 5526 u8 reserved_2[0x40]; 5527 }; 5528 5529 struct mlx5_ifc_qp_2rst_out_bits { 5530 u8 status[0x8]; 5531 u8 reserved_0[0x18]; 5532 5533 u8 syndrome[0x20]; 5534 5535 u8 reserved_1[0x40]; 5536 }; 5537 5538 struct mlx5_ifc_qp_2rst_in_bits { 5539 u8 opcode[0x10]; 5540 u8 uid[0x10]; 5541 5542 u8 reserved_1[0x10]; 5543 u8 op_mod[0x10]; 5544 5545 u8 reserved_2[0x8]; 5546 u8 qpn[0x18]; 5547 5548 u8 reserved_3[0x20]; 5549 }; 5550 5551 struct mlx5_ifc_qp_2err_out_bits { 5552 u8 status[0x8]; 5553 u8 reserved_0[0x18]; 5554 5555 u8 syndrome[0x20]; 5556 5557 u8 reserved_1[0x40]; 5558 }; 5559 5560 struct mlx5_ifc_qp_2err_in_bits { 5561 u8 opcode[0x10]; 5562 u8 uid[0x10]; 5563 5564 u8 reserved_1[0x10]; 5565 u8 op_mod[0x10]; 5566 5567 u8 reserved_2[0x8]; 5568 u8 qpn[0x18]; 5569 5570 u8 reserved_3[0x20]; 5571 }; 5572 5573 struct mlx5_ifc_para_vport_element_bits { 5574 u8 reserved_at_0[0xc]; 5575 u8 traffic_class[0x4]; 5576 u8 qos_para_vport_number[0x10]; 5577 }; 5578 5579 struct mlx5_ifc_page_fault_resume_out_bits { 5580 u8 status[0x8]; 5581 u8 reserved_0[0x18]; 5582 5583 u8 syndrome[0x20]; 5584 5585 u8 reserved_1[0x40]; 5586 }; 5587 5588 struct mlx5_ifc_page_fault_resume_in_bits { 5589 u8 opcode[0x10]; 5590 u8 reserved_0[0x10]; 5591 5592 u8 reserved_1[0x10]; 5593 u8 op_mod[0x10]; 5594 5595 u8 error[0x1]; 5596 u8 reserved_2[0x4]; 5597 u8 rdma[0x1]; 5598 u8 read_write[0x1]; 5599 u8 req_res[0x1]; 5600 u8 qpn[0x18]; 5601 5602 u8 reserved_3[0x20]; 5603 }; 5604 5605 struct mlx5_ifc_nop_out_bits { 5606 u8 status[0x8]; 5607 u8 reserved_0[0x18]; 5608 5609 u8 syndrome[0x20]; 5610 5611 u8 reserved_1[0x40]; 5612 }; 5613 5614 struct mlx5_ifc_nop_in_bits { 5615 u8 opcode[0x10]; 5616 u8 reserved_0[0x10]; 5617 5618 u8 reserved_1[0x10]; 5619 u8 op_mod[0x10]; 5620 5621 u8 reserved_2[0x40]; 5622 }; 5623 5624 struct mlx5_ifc_modify_vport_state_out_bits { 5625 u8 status[0x8]; 5626 u8 reserved_0[0x18]; 5627 5628 u8 syndrome[0x20]; 5629 5630 u8 reserved_1[0x40]; 5631 }; 5632 5633 enum { 5634 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5635 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5636 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5637 }; 5638 5639 enum { 5640 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5641 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5642 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5643 }; 5644 5645 struct mlx5_ifc_modify_vport_state_in_bits { 5646 u8 opcode[0x10]; 5647 u8 reserved_0[0x10]; 5648 5649 u8 reserved_1[0x10]; 5650 u8 op_mod[0x10]; 5651 5652 u8 other_vport[0x1]; 5653 u8 reserved_2[0xf]; 5654 u8 vport_number[0x10]; 5655 5656 u8 reserved_3[0x18]; 5657 u8 admin_state[0x4]; 5658 u8 reserved_4[0x4]; 5659 }; 5660 5661 struct mlx5_ifc_modify_tis_out_bits { 5662 u8 status[0x8]; 5663 u8 reserved_0[0x18]; 5664 5665 u8 syndrome[0x20]; 5666 5667 u8 reserved_1[0x40]; 5668 }; 5669 5670 struct mlx5_ifc_modify_tis_bitmask_bits { 5671 u8 reserved_at_0[0x20]; 5672 5673 u8 reserved_at_20[0x1d]; 5674 u8 lag_tx_port_affinity[0x1]; 5675 u8 strict_lag_tx_port_affinity[0x1]; 5676 u8 prio[0x1]; 5677 }; 5678 5679 struct mlx5_ifc_modify_tis_in_bits { 5680 u8 opcode[0x10]; 5681 u8 uid[0x10]; 5682 5683 u8 reserved_1[0x10]; 5684 u8 op_mod[0x10]; 5685 5686 u8 reserved_2[0x8]; 5687 u8 tisn[0x18]; 5688 5689 u8 reserved_3[0x20]; 5690 5691 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5692 5693 u8 reserved_4[0x40]; 5694 5695 struct mlx5_ifc_tisc_bits ctx; 5696 }; 5697 5698 struct mlx5_ifc_modify_tir_out_bits { 5699 u8 status[0x8]; 5700 u8 reserved_0[0x18]; 5701 5702 u8 syndrome[0x20]; 5703 5704 u8 reserved_1[0x40]; 5705 }; 5706 5707 enum 5708 { 5709 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5710 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5711 }; 5712 5713 struct mlx5_ifc_modify_tir_in_bits { 5714 u8 opcode[0x10]; 5715 u8 uid[0x10]; 5716 5717 u8 reserved_1[0x10]; 5718 u8 op_mod[0x10]; 5719 5720 u8 reserved_2[0x8]; 5721 u8 tirn[0x18]; 5722 5723 u8 reserved_3[0x20]; 5724 5725 u8 modify_bitmask[0x40]; 5726 5727 u8 reserved_4[0x40]; 5728 5729 struct mlx5_ifc_tirc_bits tir_context; 5730 }; 5731 5732 struct mlx5_ifc_modify_sq_out_bits { 5733 u8 status[0x8]; 5734 u8 reserved_0[0x18]; 5735 5736 u8 syndrome[0x20]; 5737 5738 u8 reserved_1[0x40]; 5739 }; 5740 5741 struct mlx5_ifc_modify_sq_in_bits { 5742 u8 opcode[0x10]; 5743 u8 uid[0x10]; 5744 5745 u8 reserved_1[0x10]; 5746 u8 op_mod[0x10]; 5747 5748 u8 sq_state[0x4]; 5749 u8 reserved_2[0x4]; 5750 u8 sqn[0x18]; 5751 5752 u8 reserved_3[0x20]; 5753 5754 u8 modify_bitmask[0x40]; 5755 5756 u8 reserved_4[0x40]; 5757 5758 struct mlx5_ifc_sqc_bits ctx; 5759 }; 5760 5761 struct mlx5_ifc_modify_scheduling_element_out_bits { 5762 u8 status[0x8]; 5763 u8 reserved_at_8[0x18]; 5764 5765 u8 syndrome[0x20]; 5766 5767 u8 reserved_at_40[0x1c0]; 5768 }; 5769 5770 enum { 5771 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5772 }; 5773 5774 enum { 5775 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5776 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5777 }; 5778 5779 struct mlx5_ifc_modify_scheduling_element_in_bits { 5780 u8 opcode[0x10]; 5781 u8 reserved_at_10[0x10]; 5782 5783 u8 reserved_at_20[0x10]; 5784 u8 op_mod[0x10]; 5785 5786 u8 scheduling_hierarchy[0x8]; 5787 u8 reserved_at_48[0x18]; 5788 5789 u8 scheduling_element_id[0x20]; 5790 5791 u8 reserved_at_80[0x20]; 5792 5793 u8 modify_bitmask[0x20]; 5794 5795 u8 reserved_at_c0[0x40]; 5796 5797 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5798 5799 u8 reserved_at_300[0x100]; 5800 }; 5801 5802 struct mlx5_ifc_modify_rqt_out_bits { 5803 u8 status[0x8]; 5804 u8 reserved_0[0x18]; 5805 5806 u8 syndrome[0x20]; 5807 5808 u8 reserved_1[0x40]; 5809 }; 5810 5811 struct mlx5_ifc_rqt_bitmask_bits { 5812 u8 reserved_at_0[0x20]; 5813 5814 u8 reserved_at_20[0x1f]; 5815 u8 rqn_list[0x1]; 5816 }; 5817 5818 5819 struct mlx5_ifc_modify_rqt_in_bits { 5820 u8 opcode[0x10]; 5821 u8 uid[0x10]; 5822 5823 u8 reserved_1[0x10]; 5824 u8 op_mod[0x10]; 5825 5826 u8 reserved_2[0x8]; 5827 u8 rqtn[0x18]; 5828 5829 u8 reserved_3[0x20]; 5830 5831 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5832 5833 u8 reserved_4[0x40]; 5834 5835 struct mlx5_ifc_rqtc_bits ctx; 5836 }; 5837 5838 struct mlx5_ifc_modify_rq_out_bits { 5839 u8 status[0x8]; 5840 u8 reserved_0[0x18]; 5841 5842 u8 syndrome[0x20]; 5843 5844 u8 reserved_1[0x40]; 5845 }; 5846 5847 enum { 5848 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5849 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5850 }; 5851 5852 struct mlx5_ifc_modify_rq_in_bits { 5853 u8 opcode[0x10]; 5854 u8 uid[0x10]; 5855 5856 u8 reserved_1[0x10]; 5857 u8 op_mod[0x10]; 5858 5859 u8 rq_state[0x4]; 5860 u8 reserved_2[0x4]; 5861 u8 rqn[0x18]; 5862 5863 u8 reserved_3[0x20]; 5864 5865 u8 modify_bitmask[0x40]; 5866 5867 u8 reserved_4[0x40]; 5868 5869 struct mlx5_ifc_rqc_bits ctx; 5870 }; 5871 5872 struct mlx5_ifc_modify_rmp_out_bits { 5873 u8 status[0x8]; 5874 u8 reserved_0[0x18]; 5875 5876 u8 syndrome[0x20]; 5877 5878 u8 reserved_1[0x40]; 5879 }; 5880 5881 struct mlx5_ifc_rmp_bitmask_bits { 5882 u8 reserved[0x20]; 5883 5884 u8 reserved1[0x1f]; 5885 u8 lwm[0x1]; 5886 }; 5887 5888 struct mlx5_ifc_modify_rmp_in_bits { 5889 u8 opcode[0x10]; 5890 u8 uid[0x10]; 5891 5892 u8 reserved_1[0x10]; 5893 u8 op_mod[0x10]; 5894 5895 u8 rmp_state[0x4]; 5896 u8 reserved_2[0x4]; 5897 u8 rmpn[0x18]; 5898 5899 u8 reserved_3[0x20]; 5900 5901 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5902 5903 u8 reserved_4[0x40]; 5904 5905 struct mlx5_ifc_rmpc_bits ctx; 5906 }; 5907 5908 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5909 u8 status[0x8]; 5910 u8 reserved_0[0x18]; 5911 5912 u8 syndrome[0x20]; 5913 5914 u8 reserved_1[0x40]; 5915 }; 5916 5917 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5918 u8 reserved_0[0x14]; 5919 u8 disable_uc_local_lb[0x1]; 5920 u8 disable_mc_local_lb[0x1]; 5921 u8 node_guid[0x1]; 5922 u8 port_guid[0x1]; 5923 u8 min_wqe_inline_mode[0x1]; 5924 u8 mtu[0x1]; 5925 u8 change_event[0x1]; 5926 u8 promisc[0x1]; 5927 u8 permanent_address[0x1]; 5928 u8 addresses_list[0x1]; 5929 u8 roce_en[0x1]; 5930 u8 reserved_1[0x1]; 5931 }; 5932 5933 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5934 u8 opcode[0x10]; 5935 u8 reserved_0[0x10]; 5936 5937 u8 reserved_1[0x10]; 5938 u8 op_mod[0x10]; 5939 5940 u8 other_vport[0x1]; 5941 u8 reserved_2[0xf]; 5942 u8 vport_number[0x10]; 5943 5944 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5945 5946 u8 reserved_3[0x780]; 5947 5948 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5949 }; 5950 5951 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5952 u8 status[0x8]; 5953 u8 reserved_0[0x18]; 5954 5955 u8 syndrome[0x20]; 5956 5957 u8 reserved_1[0x40]; 5958 }; 5959 5960 struct mlx5_ifc_grh_bits { 5961 u8 ip_version[4]; 5962 u8 traffic_class[8]; 5963 u8 flow_label[20]; 5964 u8 payload_length[16]; 5965 u8 next_header[8]; 5966 u8 hop_limit[8]; 5967 u8 sgid[128]; 5968 u8 dgid[128]; 5969 }; 5970 5971 struct mlx5_ifc_bth_bits { 5972 u8 opcode[8]; 5973 u8 se[1]; 5974 u8 migreq[1]; 5975 u8 pad_count[2]; 5976 u8 tver[4]; 5977 u8 p_key[16]; 5978 u8 reserved8[8]; 5979 u8 dest_qp[24]; 5980 u8 ack_req[1]; 5981 u8 reserved7[7]; 5982 u8 psn[24]; 5983 }; 5984 5985 struct mlx5_ifc_aeth_bits { 5986 u8 syndrome[8]; 5987 u8 msn[24]; 5988 }; 5989 5990 struct mlx5_ifc_dceth_bits { 5991 u8 reserved0[8]; 5992 u8 session_id[24]; 5993 u8 reserved1[8]; 5994 u8 dci_dct[24]; 5995 }; 5996 5997 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5998 u8 opcode[0x10]; 5999 u8 reserved_0[0x10]; 6000 6001 u8 reserved_1[0x10]; 6002 u8 op_mod[0x10]; 6003 6004 u8 other_vport[0x1]; 6005 u8 reserved_2[0xb]; 6006 u8 port_num[0x4]; 6007 u8 vport_number[0x10]; 6008 6009 u8 reserved_3[0x20]; 6010 6011 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6012 }; 6013 6014 struct mlx5_ifc_modify_flow_table_out_bits { 6015 u8 status[0x8]; 6016 u8 reserved_at_8[0x18]; 6017 6018 u8 syndrome[0x20]; 6019 6020 u8 reserved_at_40[0x40]; 6021 }; 6022 6023 enum { 6024 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 6025 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 6026 }; 6027 6028 struct mlx5_ifc_modify_flow_table_in_bits { 6029 u8 opcode[0x10]; 6030 u8 reserved_at_10[0x10]; 6031 6032 u8 reserved_at_20[0x10]; 6033 u8 op_mod[0x10]; 6034 6035 u8 other_vport[0x1]; 6036 u8 reserved_at_41[0xf]; 6037 u8 vport_number[0x10]; 6038 6039 u8 reserved_at_60[0x10]; 6040 u8 modify_field_select[0x10]; 6041 6042 u8 table_type[0x8]; 6043 u8 reserved_at_88[0x18]; 6044 6045 u8 reserved_at_a0[0x8]; 6046 u8 table_id[0x18]; 6047 6048 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6049 }; 6050 6051 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6052 u8 status[0x8]; 6053 u8 reserved_0[0x18]; 6054 6055 u8 syndrome[0x20]; 6056 6057 u8 reserved_1[0x40]; 6058 }; 6059 6060 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6061 u8 reserved[0x1c]; 6062 u8 vport_cvlan_insert[0x1]; 6063 u8 vport_svlan_insert[0x1]; 6064 u8 vport_cvlan_strip[0x1]; 6065 u8 vport_svlan_strip[0x1]; 6066 }; 6067 6068 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6069 u8 opcode[0x10]; 6070 u8 reserved_0[0x10]; 6071 6072 u8 reserved_1[0x10]; 6073 u8 op_mod[0x10]; 6074 6075 u8 other_vport[0x1]; 6076 u8 reserved_2[0xf]; 6077 u8 vport_number[0x10]; 6078 6079 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6080 6081 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6082 }; 6083 6084 struct mlx5_ifc_modify_cq_out_bits { 6085 u8 status[0x8]; 6086 u8 reserved_0[0x18]; 6087 6088 u8 syndrome[0x20]; 6089 6090 u8 reserved_1[0x40]; 6091 }; 6092 6093 enum { 6094 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6095 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6096 }; 6097 6098 struct mlx5_ifc_modify_cq_in_bits { 6099 u8 opcode[0x10]; 6100 u8 uid[0x10]; 6101 6102 u8 reserved_1[0x10]; 6103 u8 op_mod[0x10]; 6104 6105 u8 reserved_2[0x8]; 6106 u8 cqn[0x18]; 6107 6108 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6109 6110 struct mlx5_ifc_cqc_bits cq_context; 6111 6112 u8 reserved_at_280[0x60]; 6113 6114 u8 cq_umem_valid[0x1]; 6115 u8 reserved_at_2e1[0x1f]; 6116 6117 u8 reserved_at_300[0x580]; 6118 6119 u8 pas[0][0x40]; 6120 }; 6121 6122 struct mlx5_ifc_modify_cong_status_out_bits { 6123 u8 status[0x8]; 6124 u8 reserved_0[0x18]; 6125 6126 u8 syndrome[0x20]; 6127 6128 u8 reserved_1[0x40]; 6129 }; 6130 6131 struct mlx5_ifc_modify_cong_status_in_bits { 6132 u8 opcode[0x10]; 6133 u8 reserved_0[0x10]; 6134 6135 u8 reserved_1[0x10]; 6136 u8 op_mod[0x10]; 6137 6138 u8 reserved_2[0x18]; 6139 u8 priority[0x4]; 6140 u8 cong_protocol[0x4]; 6141 6142 u8 enable[0x1]; 6143 u8 tag_enable[0x1]; 6144 u8 reserved_3[0x1e]; 6145 }; 6146 6147 struct mlx5_ifc_modify_cong_params_out_bits { 6148 u8 status[0x8]; 6149 u8 reserved_0[0x18]; 6150 6151 u8 syndrome[0x20]; 6152 6153 u8 reserved_1[0x40]; 6154 }; 6155 6156 struct mlx5_ifc_modify_cong_params_in_bits { 6157 u8 opcode[0x10]; 6158 u8 reserved_0[0x10]; 6159 6160 u8 reserved_1[0x10]; 6161 u8 op_mod[0x10]; 6162 6163 u8 reserved_2[0x1c]; 6164 u8 cong_protocol[0x4]; 6165 6166 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6167 6168 u8 reserved_3[0x80]; 6169 6170 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6171 }; 6172 6173 struct mlx5_ifc_manage_pages_out_bits { 6174 u8 status[0x8]; 6175 u8 reserved_0[0x18]; 6176 6177 u8 syndrome[0x20]; 6178 6179 u8 output_num_entries[0x20]; 6180 6181 u8 reserved_1[0x20]; 6182 6183 u8 pas[0][0x40]; 6184 }; 6185 6186 enum { 6187 MLX5_PAGES_CANT_GIVE = 0x0, 6188 MLX5_PAGES_GIVE = 0x1, 6189 MLX5_PAGES_TAKE = 0x2, 6190 }; 6191 6192 struct mlx5_ifc_manage_pages_in_bits { 6193 u8 opcode[0x10]; 6194 u8 reserved_0[0x10]; 6195 6196 u8 reserved_1[0x10]; 6197 u8 op_mod[0x10]; 6198 6199 u8 reserved_2[0x10]; 6200 u8 function_id[0x10]; 6201 6202 u8 input_num_entries[0x20]; 6203 6204 u8 pas[0][0x40]; 6205 }; 6206 6207 struct mlx5_ifc_mad_ifc_out_bits { 6208 u8 status[0x8]; 6209 u8 reserved_0[0x18]; 6210 6211 u8 syndrome[0x20]; 6212 6213 u8 reserved_1[0x40]; 6214 6215 u8 response_mad_packet[256][0x8]; 6216 }; 6217 6218 struct mlx5_ifc_mad_ifc_in_bits { 6219 u8 opcode[0x10]; 6220 u8 reserved_0[0x10]; 6221 6222 u8 reserved_1[0x10]; 6223 u8 op_mod[0x10]; 6224 6225 u8 remote_lid[0x10]; 6226 u8 reserved_2[0x8]; 6227 u8 port[0x8]; 6228 6229 u8 reserved_3[0x20]; 6230 6231 u8 mad[256][0x8]; 6232 }; 6233 6234 struct mlx5_ifc_init_hca_out_bits { 6235 u8 status[0x8]; 6236 u8 reserved_0[0x18]; 6237 6238 u8 syndrome[0x20]; 6239 6240 u8 reserved_1[0x40]; 6241 }; 6242 6243 enum { 6244 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 6245 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 6246 }; 6247 6248 struct mlx5_ifc_init_hca_in_bits { 6249 u8 opcode[0x10]; 6250 u8 reserved_0[0x10]; 6251 6252 u8 reserved_1[0x10]; 6253 u8 op_mod[0x10]; 6254 6255 u8 reserved_2[0x40]; 6256 }; 6257 6258 struct mlx5_ifc_init2rtr_qp_out_bits { 6259 u8 status[0x8]; 6260 u8 reserved_0[0x18]; 6261 6262 u8 syndrome[0x20]; 6263 6264 u8 reserved_1[0x40]; 6265 }; 6266 6267 struct mlx5_ifc_init2rtr_qp_in_bits { 6268 u8 opcode[0x10]; 6269 u8 uid[0x10]; 6270 6271 u8 reserved_1[0x10]; 6272 u8 op_mod[0x10]; 6273 6274 u8 reserved_2[0x8]; 6275 u8 qpn[0x18]; 6276 6277 u8 reserved_3[0x20]; 6278 6279 u8 opt_param_mask[0x20]; 6280 6281 u8 reserved_4[0x20]; 6282 6283 struct mlx5_ifc_qpc_bits qpc; 6284 6285 u8 reserved_5[0x80]; 6286 }; 6287 6288 struct mlx5_ifc_init2init_qp_out_bits { 6289 u8 status[0x8]; 6290 u8 reserved_0[0x18]; 6291 6292 u8 syndrome[0x20]; 6293 6294 u8 reserved_1[0x40]; 6295 }; 6296 6297 struct mlx5_ifc_init2init_qp_in_bits { 6298 u8 opcode[0x10]; 6299 u8 uid[0x10]; 6300 6301 u8 reserved_1[0x10]; 6302 u8 op_mod[0x10]; 6303 6304 u8 reserved_2[0x8]; 6305 u8 qpn[0x18]; 6306 6307 u8 reserved_3[0x20]; 6308 6309 u8 opt_param_mask[0x20]; 6310 6311 u8 reserved_4[0x20]; 6312 6313 struct mlx5_ifc_qpc_bits qpc; 6314 6315 u8 reserved_5[0x80]; 6316 }; 6317 6318 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6319 u8 status[0x8]; 6320 u8 reserved_0[0x18]; 6321 6322 u8 syndrome[0x20]; 6323 6324 u8 reserved_1[0x40]; 6325 6326 u8 packet_headers_log[128][0x8]; 6327 6328 u8 packet_syndrome[64][0x8]; 6329 }; 6330 6331 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6332 u8 opcode[0x10]; 6333 u8 reserved_0[0x10]; 6334 6335 u8 reserved_1[0x10]; 6336 u8 op_mod[0x10]; 6337 6338 u8 reserved_2[0x40]; 6339 }; 6340 6341 struct mlx5_ifc_encryption_key_obj_bits { 6342 u8 modify_field_select[0x40]; 6343 6344 u8 reserved_at_40[0x14]; 6345 u8 key_size[0x4]; 6346 u8 reserved_at_58[0x4]; 6347 u8 key_type[0x4]; 6348 6349 u8 reserved_at_60[0x8]; 6350 u8 pd[0x18]; 6351 6352 u8 reserved_at_80[0x180]; 6353 6354 u8 key[8][0x20]; 6355 6356 u8 reserved_at_300[0x500]; 6357 }; 6358 6359 struct mlx5_ifc_gen_eqe_in_bits { 6360 u8 opcode[0x10]; 6361 u8 reserved_0[0x10]; 6362 6363 u8 reserved_1[0x10]; 6364 u8 op_mod[0x10]; 6365 6366 u8 reserved_2[0x18]; 6367 u8 eq_number[0x8]; 6368 6369 u8 reserved_3[0x20]; 6370 6371 u8 eqe[64][0x8]; 6372 }; 6373 6374 struct mlx5_ifc_gen_eq_out_bits { 6375 u8 status[0x8]; 6376 u8 reserved_0[0x18]; 6377 6378 u8 syndrome[0x20]; 6379 6380 u8 reserved_1[0x40]; 6381 }; 6382 6383 struct mlx5_ifc_enable_hca_out_bits { 6384 u8 status[0x8]; 6385 u8 reserved_0[0x18]; 6386 6387 u8 syndrome[0x20]; 6388 6389 u8 reserved_1[0x20]; 6390 }; 6391 6392 struct mlx5_ifc_enable_hca_in_bits { 6393 u8 opcode[0x10]; 6394 u8 reserved_0[0x10]; 6395 6396 u8 reserved_1[0x10]; 6397 u8 op_mod[0x10]; 6398 6399 u8 reserved_2[0x10]; 6400 u8 function_id[0x10]; 6401 6402 u8 reserved_3[0x20]; 6403 }; 6404 6405 struct mlx5_ifc_drain_dct_out_bits { 6406 u8 status[0x8]; 6407 u8 reserved_0[0x18]; 6408 6409 u8 syndrome[0x20]; 6410 6411 u8 reserved_1[0x40]; 6412 }; 6413 6414 struct mlx5_ifc_drain_dct_in_bits { 6415 u8 opcode[0x10]; 6416 u8 uid[0x10]; 6417 6418 u8 reserved_1[0x10]; 6419 u8 op_mod[0x10]; 6420 6421 u8 reserved_2[0x8]; 6422 u8 dctn[0x18]; 6423 6424 u8 reserved_3[0x20]; 6425 }; 6426 6427 struct mlx5_ifc_disable_hca_out_bits { 6428 u8 status[0x8]; 6429 u8 reserved_0[0x18]; 6430 6431 u8 syndrome[0x20]; 6432 6433 u8 reserved_1[0x20]; 6434 }; 6435 6436 struct mlx5_ifc_disable_hca_in_bits { 6437 u8 opcode[0x10]; 6438 u8 reserved_0[0x10]; 6439 6440 u8 reserved_1[0x10]; 6441 u8 op_mod[0x10]; 6442 6443 u8 reserved_2[0x10]; 6444 u8 function_id[0x10]; 6445 6446 u8 reserved_3[0x20]; 6447 }; 6448 6449 struct mlx5_ifc_detach_from_mcg_out_bits { 6450 u8 status[0x8]; 6451 u8 reserved_0[0x18]; 6452 6453 u8 syndrome[0x20]; 6454 6455 u8 reserved_1[0x40]; 6456 }; 6457 6458 struct mlx5_ifc_detach_from_mcg_in_bits { 6459 u8 opcode[0x10]; 6460 u8 uid[0x10]; 6461 6462 u8 reserved_1[0x10]; 6463 u8 op_mod[0x10]; 6464 6465 u8 reserved_2[0x8]; 6466 u8 qpn[0x18]; 6467 6468 u8 reserved_3[0x20]; 6469 6470 u8 multicast_gid[16][0x8]; 6471 }; 6472 6473 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6474 u8 status[0x8]; 6475 u8 reserved_0[0x18]; 6476 6477 u8 syndrome[0x20]; 6478 6479 u8 reserved_1[0x40]; 6480 }; 6481 6482 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6483 u8 opcode[0x10]; 6484 u8 uid[0x10]; 6485 6486 u8 reserved_1[0x10]; 6487 u8 op_mod[0x10]; 6488 6489 u8 reserved_2[0x8]; 6490 u8 xrc_srqn[0x18]; 6491 6492 u8 reserved_3[0x20]; 6493 }; 6494 6495 struct mlx5_ifc_destroy_tis_out_bits { 6496 u8 status[0x8]; 6497 u8 reserved_0[0x18]; 6498 6499 u8 syndrome[0x20]; 6500 6501 u8 reserved_1[0x40]; 6502 }; 6503 6504 struct mlx5_ifc_destroy_tis_in_bits { 6505 u8 opcode[0x10]; 6506 u8 uid[0x10]; 6507 6508 u8 reserved_1[0x10]; 6509 u8 op_mod[0x10]; 6510 6511 u8 reserved_2[0x8]; 6512 u8 tisn[0x18]; 6513 6514 u8 reserved_3[0x20]; 6515 }; 6516 6517 struct mlx5_ifc_destroy_tir_out_bits { 6518 u8 status[0x8]; 6519 u8 reserved_0[0x18]; 6520 6521 u8 syndrome[0x20]; 6522 6523 u8 reserved_1[0x40]; 6524 }; 6525 6526 struct mlx5_ifc_destroy_tir_in_bits { 6527 u8 opcode[0x10]; 6528 u8 uid[0x10]; 6529 6530 u8 reserved_1[0x10]; 6531 u8 op_mod[0x10]; 6532 6533 u8 reserved_2[0x8]; 6534 u8 tirn[0x18]; 6535 6536 u8 reserved_3[0x20]; 6537 }; 6538 6539 struct mlx5_ifc_destroy_srq_out_bits { 6540 u8 status[0x8]; 6541 u8 reserved_0[0x18]; 6542 6543 u8 syndrome[0x20]; 6544 6545 u8 reserved_1[0x40]; 6546 }; 6547 6548 struct mlx5_ifc_destroy_srq_in_bits { 6549 u8 opcode[0x10]; 6550 u8 uid[0x10]; 6551 6552 u8 reserved_1[0x10]; 6553 u8 op_mod[0x10]; 6554 6555 u8 reserved_2[0x8]; 6556 u8 srqn[0x18]; 6557 6558 u8 reserved_3[0x20]; 6559 }; 6560 6561 struct mlx5_ifc_destroy_sq_out_bits { 6562 u8 status[0x8]; 6563 u8 reserved_0[0x18]; 6564 6565 u8 syndrome[0x20]; 6566 6567 u8 reserved_1[0x40]; 6568 }; 6569 6570 struct mlx5_ifc_destroy_sq_in_bits { 6571 u8 opcode[0x10]; 6572 u8 uid[0x10]; 6573 6574 u8 reserved_1[0x10]; 6575 u8 op_mod[0x10]; 6576 6577 u8 reserved_2[0x8]; 6578 u8 sqn[0x18]; 6579 6580 u8 reserved_3[0x20]; 6581 }; 6582 6583 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6584 u8 status[0x8]; 6585 u8 reserved_at_8[0x18]; 6586 6587 u8 syndrome[0x20]; 6588 6589 u8 reserved_at_40[0x1c0]; 6590 }; 6591 6592 enum { 6593 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6594 }; 6595 6596 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6597 u8 opcode[0x10]; 6598 u8 reserved_at_10[0x10]; 6599 6600 u8 reserved_at_20[0x10]; 6601 u8 op_mod[0x10]; 6602 6603 u8 scheduling_hierarchy[0x8]; 6604 u8 reserved_at_48[0x18]; 6605 6606 u8 scheduling_element_id[0x20]; 6607 6608 u8 reserved_at_80[0x180]; 6609 }; 6610 6611 struct mlx5_ifc_destroy_rqt_out_bits { 6612 u8 status[0x8]; 6613 u8 reserved_0[0x18]; 6614 6615 u8 syndrome[0x20]; 6616 6617 u8 reserved_1[0x40]; 6618 }; 6619 6620 struct mlx5_ifc_destroy_rqt_in_bits { 6621 u8 opcode[0x10]; 6622 u8 uid[0x10]; 6623 6624 u8 reserved_1[0x10]; 6625 u8 op_mod[0x10]; 6626 6627 u8 reserved_2[0x8]; 6628 u8 rqtn[0x18]; 6629 6630 u8 reserved_3[0x20]; 6631 }; 6632 6633 struct mlx5_ifc_destroy_rq_out_bits { 6634 u8 status[0x8]; 6635 u8 reserved_0[0x18]; 6636 6637 u8 syndrome[0x20]; 6638 6639 u8 reserved_1[0x40]; 6640 }; 6641 6642 struct mlx5_ifc_destroy_rq_in_bits { 6643 u8 opcode[0x10]; 6644 u8 uid[0x10]; 6645 6646 u8 reserved_1[0x10]; 6647 u8 op_mod[0x10]; 6648 6649 u8 reserved_2[0x8]; 6650 u8 rqn[0x18]; 6651 6652 u8 reserved_3[0x20]; 6653 }; 6654 6655 struct mlx5_ifc_destroy_rmp_out_bits { 6656 u8 status[0x8]; 6657 u8 reserved_0[0x18]; 6658 6659 u8 syndrome[0x20]; 6660 6661 u8 reserved_1[0x40]; 6662 }; 6663 6664 struct mlx5_ifc_destroy_rmp_in_bits { 6665 u8 opcode[0x10]; 6666 u8 reserved_0[0x10]; 6667 6668 u8 reserved_1[0x10]; 6669 u8 op_mod[0x10]; 6670 6671 u8 reserved_2[0x8]; 6672 u8 rmpn[0x18]; 6673 6674 u8 reserved_3[0x20]; 6675 }; 6676 6677 struct mlx5_ifc_destroy_qp_out_bits { 6678 u8 status[0x8]; 6679 u8 reserved_0[0x18]; 6680 6681 u8 syndrome[0x20]; 6682 6683 u8 reserved_1[0x40]; 6684 }; 6685 6686 struct mlx5_ifc_destroy_qp_in_bits { 6687 u8 opcode[0x10]; 6688 u8 uid[0x10]; 6689 6690 u8 reserved_1[0x10]; 6691 u8 op_mod[0x10]; 6692 6693 u8 reserved_2[0x8]; 6694 u8 qpn[0x18]; 6695 6696 u8 reserved_3[0x20]; 6697 }; 6698 6699 struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6700 u8 status[0x8]; 6701 u8 reserved_at_8[0x18]; 6702 6703 u8 syndrome[0x20]; 6704 6705 u8 reserved_at_40[0x1c0]; 6706 }; 6707 6708 struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6709 u8 opcode[0x10]; 6710 u8 reserved_at_10[0x10]; 6711 6712 u8 reserved_at_20[0x10]; 6713 u8 op_mod[0x10]; 6714 6715 u8 reserved_at_40[0x20]; 6716 6717 u8 reserved_at_60[0x10]; 6718 u8 qos_para_vport_number[0x10]; 6719 6720 u8 reserved_at_80[0x180]; 6721 }; 6722 6723 struct mlx5_ifc_destroy_psv_out_bits { 6724 u8 status[0x8]; 6725 u8 reserved_0[0x18]; 6726 6727 u8 syndrome[0x20]; 6728 6729 u8 reserved_1[0x40]; 6730 }; 6731 6732 struct mlx5_ifc_destroy_psv_in_bits { 6733 u8 opcode[0x10]; 6734 u8 reserved_0[0x10]; 6735 6736 u8 reserved_1[0x10]; 6737 u8 op_mod[0x10]; 6738 6739 u8 reserved_2[0x8]; 6740 u8 psvn[0x18]; 6741 6742 u8 reserved_3[0x20]; 6743 }; 6744 6745 struct mlx5_ifc_destroy_mkey_out_bits { 6746 u8 status[0x8]; 6747 u8 reserved_0[0x18]; 6748 6749 u8 syndrome[0x20]; 6750 6751 u8 reserved_1[0x40]; 6752 }; 6753 6754 struct mlx5_ifc_destroy_mkey_in_bits { 6755 u8 opcode[0x10]; 6756 u8 reserved_0[0x10]; 6757 6758 u8 reserved_1[0x10]; 6759 u8 op_mod[0x10]; 6760 6761 u8 reserved_2[0x8]; 6762 u8 mkey_index[0x18]; 6763 6764 u8 reserved_3[0x20]; 6765 }; 6766 6767 struct mlx5_ifc_destroy_flow_table_out_bits { 6768 u8 status[0x8]; 6769 u8 reserved_0[0x18]; 6770 6771 u8 syndrome[0x20]; 6772 6773 u8 reserved_1[0x40]; 6774 }; 6775 6776 struct mlx5_ifc_destroy_flow_table_in_bits { 6777 u8 opcode[0x10]; 6778 u8 reserved_0[0x10]; 6779 6780 u8 reserved_1[0x10]; 6781 u8 op_mod[0x10]; 6782 6783 u8 other_vport[0x1]; 6784 u8 reserved_2[0xf]; 6785 u8 vport_number[0x10]; 6786 6787 u8 reserved_3[0x20]; 6788 6789 u8 table_type[0x8]; 6790 u8 reserved_4[0x18]; 6791 6792 u8 reserved_5[0x8]; 6793 u8 table_id[0x18]; 6794 6795 u8 reserved_6[0x140]; 6796 }; 6797 6798 struct mlx5_ifc_destroy_flow_group_out_bits { 6799 u8 status[0x8]; 6800 u8 reserved_0[0x18]; 6801 6802 u8 syndrome[0x20]; 6803 6804 u8 reserved_1[0x40]; 6805 }; 6806 6807 struct mlx5_ifc_destroy_flow_group_in_bits { 6808 u8 opcode[0x10]; 6809 u8 reserved_0[0x10]; 6810 6811 u8 reserved_1[0x10]; 6812 u8 op_mod[0x10]; 6813 6814 u8 other_vport[0x1]; 6815 u8 reserved_2[0xf]; 6816 u8 vport_number[0x10]; 6817 6818 u8 reserved_3[0x20]; 6819 6820 u8 table_type[0x8]; 6821 u8 reserved_4[0x18]; 6822 6823 u8 reserved_5[0x8]; 6824 u8 table_id[0x18]; 6825 6826 u8 group_id[0x20]; 6827 6828 u8 reserved_6[0x120]; 6829 }; 6830 6831 struct mlx5_ifc_destroy_encryption_key_out_bits { 6832 u8 status[0x8]; 6833 u8 reserved_at_8[0x18]; 6834 6835 u8 syndrome[0x20]; 6836 6837 u8 reserved_at_40[0x40]; 6838 }; 6839 6840 struct mlx5_ifc_destroy_encryption_key_in_bits { 6841 u8 opcode[0x10]; 6842 u8 reserved_at_10[0x10]; 6843 6844 u8 reserved_at_20[0x10]; 6845 u8 obj_type[0x10]; 6846 6847 u8 obj_id[0x20]; 6848 6849 u8 reserved_at_60[0x20]; 6850 }; 6851 6852 struct mlx5_ifc_destroy_eq_out_bits { 6853 u8 status[0x8]; 6854 u8 reserved_0[0x18]; 6855 6856 u8 syndrome[0x20]; 6857 6858 u8 reserved_1[0x40]; 6859 }; 6860 6861 struct mlx5_ifc_destroy_eq_in_bits { 6862 u8 opcode[0x10]; 6863 u8 reserved_0[0x10]; 6864 6865 u8 reserved_1[0x10]; 6866 u8 op_mod[0x10]; 6867 6868 u8 reserved_2[0x18]; 6869 u8 eq_number[0x8]; 6870 6871 u8 reserved_3[0x20]; 6872 }; 6873 6874 struct mlx5_ifc_destroy_dct_out_bits { 6875 u8 status[0x8]; 6876 u8 reserved_0[0x18]; 6877 6878 u8 syndrome[0x20]; 6879 6880 u8 reserved_1[0x40]; 6881 }; 6882 6883 struct mlx5_ifc_destroy_dct_in_bits { 6884 u8 opcode[0x10]; 6885 u8 uid[0x10]; 6886 6887 u8 reserved_1[0x10]; 6888 u8 op_mod[0x10]; 6889 6890 u8 reserved_2[0x8]; 6891 u8 dctn[0x18]; 6892 6893 u8 reserved_3[0x20]; 6894 }; 6895 6896 struct mlx5_ifc_destroy_cq_out_bits { 6897 u8 status[0x8]; 6898 u8 reserved_0[0x18]; 6899 6900 u8 syndrome[0x20]; 6901 6902 u8 reserved_1[0x40]; 6903 }; 6904 6905 struct mlx5_ifc_destroy_cq_in_bits { 6906 u8 opcode[0x10]; 6907 u8 uid[0x10]; 6908 6909 u8 reserved_1[0x10]; 6910 u8 op_mod[0x10]; 6911 6912 u8 reserved_2[0x8]; 6913 u8 cqn[0x18]; 6914 6915 u8 reserved_3[0x20]; 6916 }; 6917 6918 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6919 u8 status[0x8]; 6920 u8 reserved_0[0x18]; 6921 6922 u8 syndrome[0x20]; 6923 6924 u8 reserved_1[0x40]; 6925 }; 6926 6927 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6928 u8 opcode[0x10]; 6929 u8 reserved_0[0x10]; 6930 6931 u8 reserved_1[0x10]; 6932 u8 op_mod[0x10]; 6933 6934 u8 reserved_2[0x20]; 6935 6936 u8 reserved_3[0x10]; 6937 u8 vxlan_udp_port[0x10]; 6938 }; 6939 6940 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6941 u8 status[0x8]; 6942 u8 reserved_0[0x18]; 6943 6944 u8 syndrome[0x20]; 6945 6946 u8 reserved_1[0x40]; 6947 }; 6948 6949 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6950 u8 opcode[0x10]; 6951 u8 reserved_0[0x10]; 6952 6953 u8 reserved_1[0x10]; 6954 u8 op_mod[0x10]; 6955 6956 u8 reserved_2[0x60]; 6957 6958 u8 reserved_3[0x8]; 6959 u8 table_index[0x18]; 6960 6961 u8 reserved_4[0x140]; 6962 }; 6963 6964 struct mlx5_ifc_delete_fte_out_bits { 6965 u8 status[0x8]; 6966 u8 reserved_0[0x18]; 6967 6968 u8 syndrome[0x20]; 6969 6970 u8 reserved_1[0x40]; 6971 }; 6972 6973 struct mlx5_ifc_delete_fte_in_bits { 6974 u8 opcode[0x10]; 6975 u8 reserved_0[0x10]; 6976 6977 u8 reserved_1[0x10]; 6978 u8 op_mod[0x10]; 6979 6980 u8 other_vport[0x1]; 6981 u8 reserved_2[0xf]; 6982 u8 vport_number[0x10]; 6983 6984 u8 reserved_3[0x20]; 6985 6986 u8 table_type[0x8]; 6987 u8 reserved_4[0x18]; 6988 6989 u8 reserved_5[0x8]; 6990 u8 table_id[0x18]; 6991 6992 u8 reserved_6[0x40]; 6993 6994 u8 flow_index[0x20]; 6995 6996 u8 reserved_7[0xe0]; 6997 }; 6998 6999 struct mlx5_ifc_dealloc_xrcd_out_bits { 7000 u8 status[0x8]; 7001 u8 reserved_0[0x18]; 7002 7003 u8 syndrome[0x20]; 7004 7005 u8 reserved_1[0x40]; 7006 }; 7007 7008 struct mlx5_ifc_dealloc_xrcd_in_bits { 7009 u8 opcode[0x10]; 7010 u8 uid[0x10]; 7011 7012 u8 reserved_1[0x10]; 7013 u8 op_mod[0x10]; 7014 7015 u8 reserved_2[0x8]; 7016 u8 xrcd[0x18]; 7017 7018 u8 reserved_3[0x20]; 7019 }; 7020 7021 struct mlx5_ifc_dealloc_uar_out_bits { 7022 u8 status[0x8]; 7023 u8 reserved_0[0x18]; 7024 7025 u8 syndrome[0x20]; 7026 7027 u8 reserved_1[0x40]; 7028 }; 7029 7030 struct mlx5_ifc_dealloc_uar_in_bits { 7031 u8 opcode[0x10]; 7032 u8 reserved_0[0x10]; 7033 7034 u8 reserved_1[0x10]; 7035 u8 op_mod[0x10]; 7036 7037 u8 reserved_2[0x8]; 7038 u8 uar[0x18]; 7039 7040 u8 reserved_3[0x20]; 7041 }; 7042 7043 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7044 u8 status[0x8]; 7045 u8 reserved_0[0x18]; 7046 7047 u8 syndrome[0x20]; 7048 7049 u8 reserved_1[0x40]; 7050 }; 7051 7052 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7053 u8 opcode[0x10]; 7054 u8 uid[0x10]; 7055 7056 u8 reserved_1[0x10]; 7057 u8 op_mod[0x10]; 7058 7059 u8 reserved_2[0x8]; 7060 u8 transport_domain[0x18]; 7061 7062 u8 reserved_3[0x20]; 7063 }; 7064 7065 struct mlx5_ifc_dealloc_q_counter_out_bits { 7066 u8 status[0x8]; 7067 u8 reserved_0[0x18]; 7068 7069 u8 syndrome[0x20]; 7070 7071 u8 reserved_1[0x40]; 7072 }; 7073 7074 struct mlx5_ifc_counter_id_bits { 7075 u8 reserved[0x10]; 7076 u8 counter_id[0x10]; 7077 }; 7078 7079 struct mlx5_ifc_diagnostic_params_context_bits { 7080 u8 num_of_counters[0x10]; 7081 u8 reserved_2[0x8]; 7082 u8 log_num_of_samples[0x8]; 7083 7084 u8 single[0x1]; 7085 u8 repetitive[0x1]; 7086 u8 sync[0x1]; 7087 u8 clear[0x1]; 7088 u8 on_demand[0x1]; 7089 u8 enable[0x1]; 7090 u8 reserved_3[0x12]; 7091 u8 log_sample_period[0x8]; 7092 7093 u8 reserved_4[0x80]; 7094 7095 struct mlx5_ifc_counter_id_bits counter_id[0]; 7096 }; 7097 7098 struct mlx5_ifc_query_diagnostic_params_in_bits { 7099 u8 opcode[0x10]; 7100 u8 reserved_at_10[0x10]; 7101 7102 u8 reserved_at_20[0x10]; 7103 u8 op_mod[0x10]; 7104 7105 u8 reserved_at_40[0x40]; 7106 }; 7107 7108 struct mlx5_ifc_query_diagnostic_params_out_bits { 7109 u8 status[0x8]; 7110 u8 reserved_at_8[0x18]; 7111 7112 u8 syndrome[0x20]; 7113 7114 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 7115 }; 7116 7117 struct mlx5_ifc_set_diagnostic_params_in_bits { 7118 u8 opcode[0x10]; 7119 u8 reserved_0[0x10]; 7120 7121 u8 reserved_1[0x10]; 7122 u8 op_mod[0x10]; 7123 7124 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 7125 }; 7126 7127 struct mlx5_ifc_set_diagnostic_params_out_bits { 7128 u8 status[0x8]; 7129 u8 reserved_0[0x18]; 7130 7131 u8 syndrome[0x20]; 7132 7133 u8 reserved_1[0x40]; 7134 }; 7135 7136 struct mlx5_ifc_query_diagnostic_counters_in_bits { 7137 u8 opcode[0x10]; 7138 u8 reserved_0[0x10]; 7139 7140 u8 reserved_1[0x10]; 7141 u8 op_mod[0x10]; 7142 7143 u8 num_of_samples[0x10]; 7144 u8 sample_index[0x10]; 7145 7146 u8 reserved_2[0x20]; 7147 }; 7148 7149 struct mlx5_ifc_diagnostic_counter_bits { 7150 u8 counter_id[0x10]; 7151 u8 sample_id[0x10]; 7152 7153 u8 time_stamp_31_0[0x20]; 7154 7155 u8 counter_value_h[0x20]; 7156 7157 u8 counter_value_l[0x20]; 7158 }; 7159 7160 struct mlx5_ifc_query_diagnostic_counters_out_bits { 7161 u8 status[0x8]; 7162 u8 reserved_0[0x18]; 7163 7164 u8 syndrome[0x20]; 7165 7166 u8 reserved_1[0x40]; 7167 7168 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 7169 }; 7170 7171 struct mlx5_ifc_dealloc_q_counter_in_bits { 7172 u8 opcode[0x10]; 7173 u8 reserved_0[0x10]; 7174 7175 u8 reserved_1[0x10]; 7176 u8 op_mod[0x10]; 7177 7178 u8 reserved_2[0x18]; 7179 u8 counter_set_id[0x8]; 7180 7181 u8 reserved_3[0x20]; 7182 }; 7183 7184 struct mlx5_ifc_dealloc_pd_out_bits { 7185 u8 status[0x8]; 7186 u8 reserved_0[0x18]; 7187 7188 u8 syndrome[0x20]; 7189 7190 u8 reserved_1[0x40]; 7191 }; 7192 7193 struct mlx5_ifc_dealloc_pd_in_bits { 7194 u8 opcode[0x10]; 7195 u8 uid[0x10]; 7196 7197 u8 reserved_1[0x10]; 7198 u8 op_mod[0x10]; 7199 7200 u8 reserved_2[0x8]; 7201 u8 pd[0x18]; 7202 7203 u8 reserved_3[0x20]; 7204 }; 7205 7206 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7207 u8 status[0x8]; 7208 u8 reserved_0[0x18]; 7209 7210 u8 syndrome[0x20]; 7211 7212 u8 reserved_1[0x40]; 7213 }; 7214 7215 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7216 u8 opcode[0x10]; 7217 u8 reserved_0[0x10]; 7218 7219 u8 reserved_1[0x10]; 7220 u8 op_mod[0x10]; 7221 7222 u8 reserved_2[0x10]; 7223 u8 flow_counter_id[0x10]; 7224 7225 u8 reserved_3[0x20]; 7226 }; 7227 7228 struct mlx5_ifc_create_xrq_out_bits { 7229 u8 status[0x8]; 7230 u8 reserved_at_8[0x18]; 7231 7232 u8 syndrome[0x20]; 7233 7234 u8 reserved_at_40[0x8]; 7235 u8 xrqn[0x18]; 7236 7237 u8 reserved_at_60[0x20]; 7238 }; 7239 7240 struct mlx5_ifc_create_xrq_in_bits { 7241 u8 opcode[0x10]; 7242 u8 uid[0x10]; 7243 7244 u8 reserved_at_20[0x10]; 7245 u8 op_mod[0x10]; 7246 7247 u8 reserved_at_40[0x40]; 7248 7249 struct mlx5_ifc_xrqc_bits xrq_context; 7250 }; 7251 7252 struct mlx5_ifc_deactivate_tracer_out_bits { 7253 u8 status[0x8]; 7254 u8 reserved_0[0x18]; 7255 7256 u8 syndrome[0x20]; 7257 7258 u8 reserved_1[0x40]; 7259 }; 7260 7261 struct mlx5_ifc_deactivate_tracer_in_bits { 7262 u8 opcode[0x10]; 7263 u8 reserved_0[0x10]; 7264 7265 u8 reserved_1[0x10]; 7266 u8 op_mod[0x10]; 7267 7268 u8 mkey[0x20]; 7269 7270 u8 reserved_2[0x20]; 7271 }; 7272 7273 struct mlx5_ifc_create_xrc_srq_out_bits { 7274 u8 status[0x8]; 7275 u8 reserved_0[0x18]; 7276 7277 u8 syndrome[0x20]; 7278 7279 u8 reserved_1[0x8]; 7280 u8 xrc_srqn[0x18]; 7281 7282 u8 reserved_2[0x20]; 7283 }; 7284 7285 struct mlx5_ifc_create_xrc_srq_in_bits { 7286 u8 opcode[0x10]; 7287 u8 uid[0x10]; 7288 7289 u8 reserved_1[0x10]; 7290 u8 op_mod[0x10]; 7291 7292 u8 reserved_2[0x40]; 7293 7294 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7295 7296 u8 reserved_at_280[0x60]; 7297 7298 u8 xrc_srq_umem_valid[0x1]; 7299 u8 reserved_at_2e1[0x1f]; 7300 7301 u8 reserved_at_300[0x580]; 7302 7303 u8 pas[0][0x40]; 7304 }; 7305 7306 struct mlx5_ifc_create_tis_out_bits { 7307 u8 status[0x8]; 7308 u8 reserved_0[0x18]; 7309 7310 u8 syndrome[0x20]; 7311 7312 u8 reserved_1[0x8]; 7313 u8 tisn[0x18]; 7314 7315 u8 reserved_2[0x20]; 7316 }; 7317 7318 struct mlx5_ifc_create_tis_in_bits { 7319 u8 opcode[0x10]; 7320 u8 uid[0x10]; 7321 7322 u8 reserved_1[0x10]; 7323 u8 op_mod[0x10]; 7324 7325 u8 reserved_2[0xc0]; 7326 7327 struct mlx5_ifc_tisc_bits ctx; 7328 }; 7329 7330 struct mlx5_ifc_create_tir_out_bits { 7331 u8 status[0x8]; 7332 u8 reserved_0[0x18]; 7333 7334 u8 syndrome[0x20]; 7335 7336 u8 reserved_1[0x8]; 7337 u8 tirn[0x18]; 7338 7339 u8 reserved_2[0x20]; 7340 }; 7341 7342 struct mlx5_ifc_create_tir_in_bits { 7343 u8 opcode[0x10]; 7344 u8 uid[0x10]; 7345 7346 u8 reserved_1[0x10]; 7347 u8 op_mod[0x10]; 7348 7349 u8 reserved_2[0xc0]; 7350 7351 struct mlx5_ifc_tirc_bits tir_context; 7352 }; 7353 7354 struct mlx5_ifc_create_srq_out_bits { 7355 u8 status[0x8]; 7356 u8 reserved_0[0x18]; 7357 7358 u8 syndrome[0x20]; 7359 7360 u8 reserved_1[0x8]; 7361 u8 srqn[0x18]; 7362 7363 u8 reserved_2[0x20]; 7364 }; 7365 7366 struct mlx5_ifc_create_srq_in_bits { 7367 u8 opcode[0x10]; 7368 u8 uid[0x10]; 7369 7370 u8 reserved_1[0x10]; 7371 u8 op_mod[0x10]; 7372 7373 u8 reserved_2[0x40]; 7374 7375 struct mlx5_ifc_srqc_bits srq_context_entry; 7376 7377 u8 reserved_3[0x600]; 7378 7379 u8 pas[0][0x40]; 7380 }; 7381 7382 struct mlx5_ifc_create_sq_out_bits { 7383 u8 status[0x8]; 7384 u8 reserved_0[0x18]; 7385 7386 u8 syndrome[0x20]; 7387 7388 u8 reserved_1[0x8]; 7389 u8 sqn[0x18]; 7390 7391 u8 reserved_2[0x20]; 7392 }; 7393 7394 struct mlx5_ifc_create_sq_in_bits { 7395 u8 opcode[0x10]; 7396 u8 uid[0x10]; 7397 7398 u8 reserved_1[0x10]; 7399 u8 op_mod[0x10]; 7400 7401 u8 reserved_2[0xc0]; 7402 7403 struct mlx5_ifc_sqc_bits ctx; 7404 }; 7405 7406 struct mlx5_ifc_create_scheduling_element_out_bits { 7407 u8 status[0x8]; 7408 u8 reserved_at_8[0x18]; 7409 7410 u8 syndrome[0x20]; 7411 7412 u8 reserved_at_40[0x40]; 7413 7414 u8 scheduling_element_id[0x20]; 7415 7416 u8 reserved_at_a0[0x160]; 7417 }; 7418 7419 enum { 7420 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 7421 }; 7422 7423 struct mlx5_ifc_create_scheduling_element_in_bits { 7424 u8 opcode[0x10]; 7425 u8 reserved_at_10[0x10]; 7426 7427 u8 reserved_at_20[0x10]; 7428 u8 op_mod[0x10]; 7429 7430 u8 scheduling_hierarchy[0x8]; 7431 u8 reserved_at_48[0x18]; 7432 7433 u8 reserved_at_60[0xa0]; 7434 7435 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7436 7437 u8 reserved_at_300[0x100]; 7438 }; 7439 7440 struct mlx5_ifc_create_rqt_out_bits { 7441 u8 status[0x8]; 7442 u8 reserved_0[0x18]; 7443 7444 u8 syndrome[0x20]; 7445 7446 u8 reserved_1[0x8]; 7447 u8 rqtn[0x18]; 7448 7449 u8 reserved_2[0x20]; 7450 }; 7451 7452 struct mlx5_ifc_create_rqt_in_bits { 7453 u8 opcode[0x10]; 7454 u8 uid[0x10]; 7455 7456 u8 reserved_1[0x10]; 7457 u8 op_mod[0x10]; 7458 7459 u8 reserved_2[0xc0]; 7460 7461 struct mlx5_ifc_rqtc_bits rqt_context; 7462 }; 7463 7464 struct mlx5_ifc_create_rq_out_bits { 7465 u8 status[0x8]; 7466 u8 reserved_0[0x18]; 7467 7468 u8 syndrome[0x20]; 7469 7470 u8 reserved_1[0x8]; 7471 u8 rqn[0x18]; 7472 7473 u8 reserved_2[0x20]; 7474 }; 7475 7476 struct mlx5_ifc_create_rq_in_bits { 7477 u8 opcode[0x10]; 7478 u8 uid[0x10]; 7479 7480 u8 reserved_1[0x10]; 7481 u8 op_mod[0x10]; 7482 7483 u8 reserved_2[0xc0]; 7484 7485 struct mlx5_ifc_rqc_bits ctx; 7486 }; 7487 7488 struct mlx5_ifc_create_rmp_out_bits { 7489 u8 status[0x8]; 7490 u8 reserved_0[0x18]; 7491 7492 u8 syndrome[0x20]; 7493 7494 u8 reserved_1[0x8]; 7495 u8 rmpn[0x18]; 7496 7497 u8 reserved_2[0x20]; 7498 }; 7499 7500 struct mlx5_ifc_create_rmp_in_bits { 7501 u8 opcode[0x10]; 7502 u8 uid[0x10]; 7503 7504 u8 reserved_1[0x10]; 7505 u8 op_mod[0x10]; 7506 7507 u8 reserved_2[0xc0]; 7508 7509 struct mlx5_ifc_rmpc_bits ctx; 7510 }; 7511 7512 struct mlx5_ifc_create_qp_out_bits { 7513 u8 status[0x8]; 7514 u8 reserved_0[0x18]; 7515 7516 u8 syndrome[0x20]; 7517 7518 u8 reserved_1[0x8]; 7519 u8 qpn[0x18]; 7520 7521 u8 reserved_2[0x20]; 7522 }; 7523 7524 struct mlx5_ifc_create_qp_in_bits { 7525 u8 opcode[0x10]; 7526 u8 uid[0x10]; 7527 7528 u8 reserved_1[0x10]; 7529 u8 op_mod[0x10]; 7530 7531 u8 reserved_2[0x8]; 7532 u8 input_qpn[0x18]; 7533 7534 u8 reserved_3[0x20]; 7535 7536 u8 opt_param_mask[0x20]; 7537 7538 u8 reserved_4[0x20]; 7539 7540 struct mlx5_ifc_qpc_bits qpc; 7541 7542 u8 reserved_at_800[0x60]; 7543 7544 u8 wq_umem_valid[0x1]; 7545 u8 reserved_at_861[0x1f]; 7546 7547 u8 pas[0][0x40]; 7548 }; 7549 7550 struct mlx5_ifc_create_qos_para_vport_out_bits { 7551 u8 status[0x8]; 7552 u8 reserved_at_8[0x18]; 7553 7554 u8 syndrome[0x20]; 7555 7556 u8 reserved_at_40[0x20]; 7557 7558 u8 reserved_at_60[0x10]; 7559 u8 qos_para_vport_number[0x10]; 7560 7561 u8 reserved_at_80[0x180]; 7562 }; 7563 7564 struct mlx5_ifc_create_qos_para_vport_in_bits { 7565 u8 opcode[0x10]; 7566 u8 reserved_at_10[0x10]; 7567 7568 u8 reserved_at_20[0x10]; 7569 u8 op_mod[0x10]; 7570 7571 u8 reserved_at_40[0x1c0]; 7572 }; 7573 7574 struct mlx5_ifc_create_psv_out_bits { 7575 u8 status[0x8]; 7576 u8 reserved_0[0x18]; 7577 7578 u8 syndrome[0x20]; 7579 7580 u8 reserved_1[0x40]; 7581 7582 u8 reserved_2[0x8]; 7583 u8 psv0_index[0x18]; 7584 7585 u8 reserved_3[0x8]; 7586 u8 psv1_index[0x18]; 7587 7588 u8 reserved_4[0x8]; 7589 u8 psv2_index[0x18]; 7590 7591 u8 reserved_5[0x8]; 7592 u8 psv3_index[0x18]; 7593 }; 7594 7595 struct mlx5_ifc_create_psv_in_bits { 7596 u8 opcode[0x10]; 7597 u8 reserved_0[0x10]; 7598 7599 u8 reserved_1[0x10]; 7600 u8 op_mod[0x10]; 7601 7602 u8 num_psv[0x4]; 7603 u8 reserved_2[0x4]; 7604 u8 pd[0x18]; 7605 7606 u8 reserved_3[0x20]; 7607 }; 7608 7609 struct mlx5_ifc_create_mkey_out_bits { 7610 u8 status[0x8]; 7611 u8 reserved_0[0x18]; 7612 7613 u8 syndrome[0x20]; 7614 7615 u8 reserved_1[0x8]; 7616 u8 mkey_index[0x18]; 7617 7618 u8 reserved_2[0x20]; 7619 }; 7620 7621 struct mlx5_ifc_create_mkey_in_bits { 7622 u8 opcode[0x10]; 7623 u8 reserved_0[0x10]; 7624 7625 u8 reserved_1[0x10]; 7626 u8 op_mod[0x10]; 7627 7628 u8 reserved_2[0x20]; 7629 7630 u8 pg_access[0x1]; 7631 u8 mkey_umem_valid[0x1]; 7632 u8 reserved_at_62[0x1e]; 7633 7634 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7635 7636 u8 reserved_4[0x80]; 7637 7638 u8 translations_octword_actual_size[0x20]; 7639 7640 u8 reserved_5[0x560]; 7641 7642 u8 klm_pas_mtt[0][0x20]; 7643 }; 7644 7645 struct mlx5_ifc_create_flow_table_out_bits { 7646 u8 status[0x8]; 7647 u8 reserved_0[0x18]; 7648 7649 u8 syndrome[0x20]; 7650 7651 u8 reserved_1[0x8]; 7652 u8 table_id[0x18]; 7653 7654 u8 reserved_2[0x20]; 7655 }; 7656 7657 struct mlx5_ifc_create_flow_table_in_bits { 7658 u8 opcode[0x10]; 7659 u8 reserved_at_10[0x10]; 7660 7661 u8 reserved_at_20[0x10]; 7662 u8 op_mod[0x10]; 7663 7664 u8 other_vport[0x1]; 7665 u8 reserved_at_41[0xf]; 7666 u8 vport_number[0x10]; 7667 7668 u8 reserved_at_60[0x20]; 7669 7670 u8 table_type[0x8]; 7671 u8 reserved_at_88[0x18]; 7672 7673 u8 reserved_at_a0[0x20]; 7674 7675 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7676 }; 7677 7678 struct mlx5_ifc_create_flow_group_out_bits { 7679 u8 status[0x8]; 7680 u8 reserved_0[0x18]; 7681 7682 u8 syndrome[0x20]; 7683 7684 u8 reserved_1[0x8]; 7685 u8 group_id[0x18]; 7686 7687 u8 reserved_2[0x20]; 7688 }; 7689 7690 enum { 7691 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7692 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7693 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7694 }; 7695 7696 struct mlx5_ifc_create_flow_group_in_bits { 7697 u8 opcode[0x10]; 7698 u8 reserved_0[0x10]; 7699 7700 u8 reserved_1[0x10]; 7701 u8 op_mod[0x10]; 7702 7703 u8 other_vport[0x1]; 7704 u8 reserved_2[0xf]; 7705 u8 vport_number[0x10]; 7706 7707 u8 reserved_3[0x20]; 7708 7709 u8 table_type[0x8]; 7710 u8 reserved_4[0x18]; 7711 7712 u8 reserved_5[0x8]; 7713 u8 table_id[0x18]; 7714 7715 u8 reserved_6[0x20]; 7716 7717 u8 start_flow_index[0x20]; 7718 7719 u8 reserved_7[0x20]; 7720 7721 u8 end_flow_index[0x20]; 7722 7723 u8 reserved_8[0xa0]; 7724 7725 u8 reserved_9[0x18]; 7726 u8 match_criteria_enable[0x8]; 7727 7728 struct mlx5_ifc_fte_match_param_bits match_criteria; 7729 7730 u8 reserved_10[0xe00]; 7731 }; 7732 7733 struct mlx5_ifc_create_encryption_key_out_bits { 7734 u8 status[0x8]; 7735 u8 reserved_at_8[0x18]; 7736 7737 u8 syndrome[0x20]; 7738 7739 u8 obj_id[0x20]; 7740 7741 u8 reserved_at_60[0x20]; 7742 }; 7743 7744 struct mlx5_ifc_create_encryption_key_in_bits { 7745 u8 opcode[0x10]; 7746 u8 reserved_at_10[0x10]; 7747 7748 u8 reserved_at_20[0x10]; 7749 u8 obj_type[0x10]; 7750 7751 u8 reserved_at_40[0x40]; 7752 7753 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 7754 }; 7755 7756 struct mlx5_ifc_create_eq_out_bits { 7757 u8 status[0x8]; 7758 u8 reserved_0[0x18]; 7759 7760 u8 syndrome[0x20]; 7761 7762 u8 reserved_1[0x18]; 7763 u8 eq_number[0x8]; 7764 7765 u8 reserved_2[0x20]; 7766 }; 7767 7768 struct mlx5_ifc_create_eq_in_bits { 7769 u8 opcode[0x10]; 7770 u8 reserved_0[0x10]; 7771 7772 u8 reserved_1[0x10]; 7773 u8 op_mod[0x10]; 7774 7775 u8 reserved_2[0x40]; 7776 7777 struct mlx5_ifc_eqc_bits eq_context_entry; 7778 7779 u8 reserved_3[0x40]; 7780 7781 u8 event_bitmask[0x40]; 7782 7783 u8 reserved_4[0x580]; 7784 7785 u8 pas[0][0x40]; 7786 }; 7787 7788 struct mlx5_ifc_create_dct_out_bits { 7789 u8 status[0x8]; 7790 u8 reserved_0[0x18]; 7791 7792 u8 syndrome[0x20]; 7793 7794 u8 reserved_1[0x8]; 7795 u8 dctn[0x18]; 7796 7797 u8 reserved_2[0x20]; 7798 }; 7799 7800 struct mlx5_ifc_create_dct_in_bits { 7801 u8 opcode[0x10]; 7802 u8 uid[0x10]; 7803 7804 u8 reserved_1[0x10]; 7805 u8 op_mod[0x10]; 7806 7807 u8 reserved_2[0x40]; 7808 7809 struct mlx5_ifc_dctc_bits dct_context_entry; 7810 7811 u8 reserved_3[0x180]; 7812 }; 7813 7814 struct mlx5_ifc_create_cq_out_bits { 7815 u8 status[0x8]; 7816 u8 reserved_0[0x18]; 7817 7818 u8 syndrome[0x20]; 7819 7820 u8 reserved_1[0x8]; 7821 u8 cqn[0x18]; 7822 7823 u8 reserved_2[0x20]; 7824 }; 7825 7826 struct mlx5_ifc_create_cq_in_bits { 7827 u8 opcode[0x10]; 7828 u8 uid[0x10]; 7829 7830 u8 reserved_1[0x10]; 7831 u8 op_mod[0x10]; 7832 7833 u8 reserved_2[0x40]; 7834 7835 struct mlx5_ifc_cqc_bits cq_context; 7836 7837 u8 reserved_at_280[0x60]; 7838 7839 u8 cq_umem_valid[0x1]; 7840 u8 reserved_at_2e1[0x59f]; 7841 7842 u8 pas[0][0x40]; 7843 }; 7844 7845 struct mlx5_ifc_config_int_moderation_out_bits { 7846 u8 status[0x8]; 7847 u8 reserved_0[0x18]; 7848 7849 u8 syndrome[0x20]; 7850 7851 u8 reserved_1[0x4]; 7852 u8 min_delay[0xc]; 7853 u8 int_vector[0x10]; 7854 7855 u8 reserved_2[0x20]; 7856 }; 7857 7858 enum { 7859 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7860 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7861 }; 7862 7863 struct mlx5_ifc_config_int_moderation_in_bits { 7864 u8 opcode[0x10]; 7865 u8 reserved_0[0x10]; 7866 7867 u8 reserved_1[0x10]; 7868 u8 op_mod[0x10]; 7869 7870 u8 reserved_2[0x4]; 7871 u8 min_delay[0xc]; 7872 u8 int_vector[0x10]; 7873 7874 u8 reserved_3[0x20]; 7875 }; 7876 7877 struct mlx5_ifc_attach_to_mcg_out_bits { 7878 u8 status[0x8]; 7879 u8 reserved_0[0x18]; 7880 7881 u8 syndrome[0x20]; 7882 7883 u8 reserved_1[0x40]; 7884 }; 7885 7886 struct mlx5_ifc_attach_to_mcg_in_bits { 7887 u8 opcode[0x10]; 7888 u8 uid[0x10]; 7889 7890 u8 reserved_1[0x10]; 7891 u8 op_mod[0x10]; 7892 7893 u8 reserved_2[0x8]; 7894 u8 qpn[0x18]; 7895 7896 u8 reserved_3[0x20]; 7897 7898 u8 multicast_gid[16][0x8]; 7899 }; 7900 7901 struct mlx5_ifc_arm_xrq_out_bits { 7902 u8 status[0x8]; 7903 u8 reserved_at_8[0x18]; 7904 7905 u8 syndrome[0x20]; 7906 7907 u8 reserved_at_40[0x40]; 7908 }; 7909 7910 struct mlx5_ifc_arm_xrq_in_bits { 7911 u8 opcode[0x10]; 7912 u8 reserved_at_10[0x10]; 7913 7914 u8 reserved_at_20[0x10]; 7915 u8 op_mod[0x10]; 7916 7917 u8 reserved_at_40[0x8]; 7918 u8 xrqn[0x18]; 7919 7920 u8 reserved_at_60[0x10]; 7921 u8 lwm[0x10]; 7922 }; 7923 7924 struct mlx5_ifc_arm_xrc_srq_out_bits { 7925 u8 status[0x8]; 7926 u8 reserved_0[0x18]; 7927 7928 u8 syndrome[0x20]; 7929 7930 u8 reserved_1[0x40]; 7931 }; 7932 7933 enum { 7934 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7935 }; 7936 7937 struct mlx5_ifc_arm_xrc_srq_in_bits { 7938 u8 opcode[0x10]; 7939 u8 uid[0x10]; 7940 7941 u8 reserved_1[0x10]; 7942 u8 op_mod[0x10]; 7943 7944 u8 reserved_2[0x8]; 7945 u8 xrc_srqn[0x18]; 7946 7947 u8 reserved_3[0x10]; 7948 u8 lwm[0x10]; 7949 }; 7950 7951 struct mlx5_ifc_arm_rq_out_bits { 7952 u8 status[0x8]; 7953 u8 reserved_0[0x18]; 7954 7955 u8 syndrome[0x20]; 7956 7957 u8 reserved_1[0x40]; 7958 }; 7959 7960 enum { 7961 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7962 }; 7963 7964 struct mlx5_ifc_arm_rq_in_bits { 7965 u8 opcode[0x10]; 7966 u8 uid[0x10]; 7967 7968 u8 reserved_1[0x10]; 7969 u8 op_mod[0x10]; 7970 7971 u8 reserved_2[0x8]; 7972 u8 srq_number[0x18]; 7973 7974 u8 reserved_3[0x10]; 7975 u8 lwm[0x10]; 7976 }; 7977 7978 struct mlx5_ifc_arm_dct_out_bits { 7979 u8 status[0x8]; 7980 u8 reserved_0[0x18]; 7981 7982 u8 syndrome[0x20]; 7983 7984 u8 reserved_1[0x40]; 7985 }; 7986 7987 struct mlx5_ifc_arm_dct_in_bits { 7988 u8 opcode[0x10]; 7989 u8 reserved_0[0x10]; 7990 7991 u8 reserved_1[0x10]; 7992 u8 op_mod[0x10]; 7993 7994 u8 reserved_2[0x8]; 7995 u8 dctn[0x18]; 7996 7997 u8 reserved_3[0x20]; 7998 }; 7999 8000 struct mlx5_ifc_alloc_xrcd_out_bits { 8001 u8 status[0x8]; 8002 u8 reserved_0[0x18]; 8003 8004 u8 syndrome[0x20]; 8005 8006 u8 reserved_1[0x8]; 8007 u8 xrcd[0x18]; 8008 8009 u8 reserved_2[0x20]; 8010 }; 8011 8012 struct mlx5_ifc_alloc_xrcd_in_bits { 8013 u8 opcode[0x10]; 8014 u8 uid[0x10]; 8015 8016 u8 reserved_1[0x10]; 8017 u8 op_mod[0x10]; 8018 8019 u8 reserved_2[0x40]; 8020 }; 8021 8022 struct mlx5_ifc_alloc_uar_out_bits { 8023 u8 status[0x8]; 8024 u8 reserved_0[0x18]; 8025 8026 u8 syndrome[0x20]; 8027 8028 u8 reserved_1[0x8]; 8029 u8 uar[0x18]; 8030 8031 u8 reserved_2[0x20]; 8032 }; 8033 8034 struct mlx5_ifc_alloc_uar_in_bits { 8035 u8 opcode[0x10]; 8036 u8 reserved_0[0x10]; 8037 8038 u8 reserved_1[0x10]; 8039 u8 op_mod[0x10]; 8040 8041 u8 reserved_2[0x40]; 8042 }; 8043 8044 struct mlx5_ifc_alloc_transport_domain_out_bits { 8045 u8 status[0x8]; 8046 u8 reserved_0[0x18]; 8047 8048 u8 syndrome[0x20]; 8049 8050 u8 reserved_1[0x8]; 8051 u8 transport_domain[0x18]; 8052 8053 u8 reserved_2[0x20]; 8054 }; 8055 8056 struct mlx5_ifc_alloc_transport_domain_in_bits { 8057 u8 opcode[0x10]; 8058 u8 uid[0x10]; 8059 8060 u8 reserved_1[0x10]; 8061 u8 op_mod[0x10]; 8062 8063 u8 reserved_2[0x40]; 8064 }; 8065 8066 struct mlx5_ifc_alloc_q_counter_out_bits { 8067 u8 status[0x8]; 8068 u8 reserved_0[0x18]; 8069 8070 u8 syndrome[0x20]; 8071 8072 u8 reserved_1[0x18]; 8073 u8 counter_set_id[0x8]; 8074 8075 u8 reserved_2[0x20]; 8076 }; 8077 8078 struct mlx5_ifc_alloc_q_counter_in_bits { 8079 u8 opcode[0x10]; 8080 u8 uid[0x10]; 8081 8082 u8 reserved_1[0x10]; 8083 u8 op_mod[0x10]; 8084 8085 u8 reserved_2[0x40]; 8086 }; 8087 8088 struct mlx5_ifc_alloc_pd_out_bits { 8089 u8 status[0x8]; 8090 u8 reserved_0[0x18]; 8091 8092 u8 syndrome[0x20]; 8093 8094 u8 reserved_1[0x8]; 8095 u8 pd[0x18]; 8096 8097 u8 reserved_2[0x20]; 8098 }; 8099 8100 struct mlx5_ifc_alloc_pd_in_bits { 8101 u8 opcode[0x10]; 8102 u8 uid[0x10]; 8103 8104 u8 reserved_1[0x10]; 8105 u8 op_mod[0x10]; 8106 8107 u8 reserved_2[0x40]; 8108 }; 8109 8110 struct mlx5_ifc_alloc_flow_counter_out_bits { 8111 u8 status[0x8]; 8112 u8 reserved_at_8[0x18]; 8113 8114 u8 syndrome[0x20]; 8115 8116 u8 flow_counter_id[0x20]; 8117 8118 u8 reserved_at_60[0x20]; 8119 }; 8120 8121 struct mlx5_ifc_alloc_flow_counter_in_bits { 8122 u8 opcode[0x10]; 8123 u8 reserved_at_10[0x10]; 8124 8125 u8 reserved_at_20[0x10]; 8126 u8 op_mod[0x10]; 8127 8128 u8 reserved_at_40[0x38]; 8129 u8 flow_counter_bulk[0x8]; 8130 }; 8131 8132 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8133 u8 status[0x8]; 8134 u8 reserved_0[0x18]; 8135 8136 u8 syndrome[0x20]; 8137 8138 u8 reserved_1[0x40]; 8139 }; 8140 8141 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8142 u8 opcode[0x10]; 8143 u8 reserved_0[0x10]; 8144 8145 u8 reserved_1[0x10]; 8146 u8 op_mod[0x10]; 8147 8148 u8 reserved_2[0x20]; 8149 8150 u8 reserved_3[0x10]; 8151 u8 vxlan_udp_port[0x10]; 8152 }; 8153 8154 struct mlx5_ifc_activate_tracer_out_bits { 8155 u8 status[0x8]; 8156 u8 reserved_0[0x18]; 8157 8158 u8 syndrome[0x20]; 8159 8160 u8 reserved_1[0x40]; 8161 }; 8162 8163 struct mlx5_ifc_activate_tracer_in_bits { 8164 u8 opcode[0x10]; 8165 u8 reserved_0[0x10]; 8166 8167 u8 reserved_1[0x10]; 8168 u8 op_mod[0x10]; 8169 8170 u8 mkey[0x20]; 8171 8172 u8 reserved_2[0x20]; 8173 }; 8174 8175 struct mlx5_ifc_set_rate_limit_out_bits { 8176 u8 status[0x8]; 8177 u8 reserved_at_8[0x18]; 8178 8179 u8 syndrome[0x20]; 8180 8181 u8 reserved_at_40[0x40]; 8182 }; 8183 8184 struct mlx5_ifc_set_rate_limit_in_bits { 8185 u8 opcode[0x10]; 8186 u8 uid[0x10]; 8187 8188 u8 reserved_at_20[0x10]; 8189 u8 op_mod[0x10]; 8190 8191 u8 reserved_at_40[0x10]; 8192 u8 rate_limit_index[0x10]; 8193 8194 u8 reserved_at_60[0x20]; 8195 8196 u8 rate_limit[0x20]; 8197 8198 u8 burst_upper_bound[0x20]; 8199 8200 u8 reserved_at_c0[0x10]; 8201 u8 typical_packet_size[0x10]; 8202 8203 u8 reserved_at_e0[0x120]; 8204 }; 8205 8206 struct mlx5_ifc_access_register_out_bits { 8207 u8 status[0x8]; 8208 u8 reserved_0[0x18]; 8209 8210 u8 syndrome[0x20]; 8211 8212 u8 reserved_1[0x40]; 8213 8214 u8 register_data[0][0x20]; 8215 }; 8216 8217 enum { 8218 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8219 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8220 }; 8221 8222 struct mlx5_ifc_access_register_in_bits { 8223 u8 opcode[0x10]; 8224 u8 reserved_0[0x10]; 8225 8226 u8 reserved_1[0x10]; 8227 u8 op_mod[0x10]; 8228 8229 u8 reserved_2[0x10]; 8230 u8 register_id[0x10]; 8231 8232 u8 argument[0x20]; 8233 8234 u8 register_data[0][0x20]; 8235 }; 8236 8237 struct mlx5_ifc_sltp_reg_bits { 8238 u8 status[0x4]; 8239 u8 version[0x4]; 8240 u8 local_port[0x8]; 8241 u8 pnat[0x2]; 8242 u8 reserved_0[0x2]; 8243 u8 lane[0x4]; 8244 u8 reserved_1[0x8]; 8245 8246 u8 reserved_2[0x20]; 8247 8248 u8 reserved_3[0x7]; 8249 u8 polarity[0x1]; 8250 u8 ob_tap0[0x8]; 8251 u8 ob_tap1[0x8]; 8252 u8 ob_tap2[0x8]; 8253 8254 u8 reserved_4[0xc]; 8255 u8 ob_preemp_mode[0x4]; 8256 u8 ob_reg[0x8]; 8257 u8 ob_bias[0x8]; 8258 8259 u8 reserved_5[0x20]; 8260 }; 8261 8262 struct mlx5_ifc_slrp_reg_bits { 8263 u8 status[0x4]; 8264 u8 version[0x4]; 8265 u8 local_port[0x8]; 8266 u8 pnat[0x2]; 8267 u8 reserved_0[0x2]; 8268 u8 lane[0x4]; 8269 u8 reserved_1[0x8]; 8270 8271 u8 ib_sel[0x2]; 8272 u8 reserved_2[0x11]; 8273 u8 dp_sel[0x1]; 8274 u8 dp90sel[0x4]; 8275 u8 mix90phase[0x8]; 8276 8277 u8 ffe_tap0[0x8]; 8278 u8 ffe_tap1[0x8]; 8279 u8 ffe_tap2[0x8]; 8280 u8 ffe_tap3[0x8]; 8281 8282 u8 ffe_tap4[0x8]; 8283 u8 ffe_tap5[0x8]; 8284 u8 ffe_tap6[0x8]; 8285 u8 ffe_tap7[0x8]; 8286 8287 u8 ffe_tap8[0x8]; 8288 u8 mixerbias_tap_amp[0x8]; 8289 u8 reserved_3[0x7]; 8290 u8 ffe_tap_en[0x9]; 8291 8292 u8 ffe_tap_offset0[0x8]; 8293 u8 ffe_tap_offset1[0x8]; 8294 u8 slicer_offset0[0x10]; 8295 8296 u8 mixer_offset0[0x10]; 8297 u8 mixer_offset1[0x10]; 8298 8299 u8 mixerbgn_inp[0x8]; 8300 u8 mixerbgn_inn[0x8]; 8301 u8 mixerbgn_refp[0x8]; 8302 u8 mixerbgn_refn[0x8]; 8303 8304 u8 sel_slicer_lctrl_h[0x1]; 8305 u8 sel_slicer_lctrl_l[0x1]; 8306 u8 reserved_4[0x1]; 8307 u8 ref_mixer_vreg[0x5]; 8308 u8 slicer_gctrl[0x8]; 8309 u8 lctrl_input[0x8]; 8310 u8 mixer_offset_cm1[0x8]; 8311 8312 u8 common_mode[0x6]; 8313 u8 reserved_5[0x1]; 8314 u8 mixer_offset_cm0[0x9]; 8315 u8 reserved_6[0x7]; 8316 u8 slicer_offset_cm[0x9]; 8317 }; 8318 8319 struct mlx5_ifc_slrg_reg_bits { 8320 u8 status[0x4]; 8321 u8 version[0x4]; 8322 u8 local_port[0x8]; 8323 u8 pnat[0x2]; 8324 u8 reserved_0[0x2]; 8325 u8 lane[0x4]; 8326 u8 reserved_1[0x8]; 8327 8328 u8 time_to_link_up[0x10]; 8329 u8 reserved_2[0xc]; 8330 u8 grade_lane_speed[0x4]; 8331 8332 u8 grade_version[0x8]; 8333 u8 grade[0x18]; 8334 8335 u8 reserved_3[0x4]; 8336 u8 height_grade_type[0x4]; 8337 u8 height_grade[0x18]; 8338 8339 u8 height_dz[0x10]; 8340 u8 height_dv[0x10]; 8341 8342 u8 reserved_4[0x10]; 8343 u8 height_sigma[0x10]; 8344 8345 u8 reserved_5[0x20]; 8346 8347 u8 reserved_6[0x4]; 8348 u8 phase_grade_type[0x4]; 8349 u8 phase_grade[0x18]; 8350 8351 u8 reserved_7[0x8]; 8352 u8 phase_eo_pos[0x8]; 8353 u8 reserved_8[0x8]; 8354 u8 phase_eo_neg[0x8]; 8355 8356 u8 ffe_set_tested[0x10]; 8357 u8 test_errors_per_lane[0x10]; 8358 }; 8359 8360 struct mlx5_ifc_pvlc_reg_bits { 8361 u8 reserved_0[0x8]; 8362 u8 local_port[0x8]; 8363 u8 reserved_1[0x10]; 8364 8365 u8 reserved_2[0x1c]; 8366 u8 vl_hw_cap[0x4]; 8367 8368 u8 reserved_3[0x1c]; 8369 u8 vl_admin[0x4]; 8370 8371 u8 reserved_4[0x1c]; 8372 u8 vl_operational[0x4]; 8373 }; 8374 8375 struct mlx5_ifc_pude_reg_bits { 8376 u8 swid[0x8]; 8377 u8 local_port[0x8]; 8378 u8 reserved_0[0x4]; 8379 u8 admin_status[0x4]; 8380 u8 reserved_1[0x4]; 8381 u8 oper_status[0x4]; 8382 8383 u8 reserved_2[0x60]; 8384 }; 8385 8386 enum { 8387 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 8388 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 8389 }; 8390 8391 struct mlx5_ifc_ptys_reg_bits { 8392 u8 reserved_0[0x1]; 8393 u8 an_disable_admin[0x1]; 8394 u8 an_disable_cap[0x1]; 8395 u8 reserved_1[0x4]; 8396 u8 force_tx_aba_param[0x1]; 8397 u8 local_port[0x8]; 8398 u8 reserved_2[0xd]; 8399 u8 proto_mask[0x3]; 8400 8401 u8 an_status[0x4]; 8402 u8 reserved_3[0xc]; 8403 u8 data_rate_oper[0x10]; 8404 8405 u8 ext_eth_proto_capability[0x20]; 8406 8407 u8 eth_proto_capability[0x20]; 8408 8409 u8 ib_link_width_capability[0x10]; 8410 u8 ib_proto_capability[0x10]; 8411 8412 u8 ext_eth_proto_admin[0x20]; 8413 8414 u8 eth_proto_admin[0x20]; 8415 8416 u8 ib_link_width_admin[0x10]; 8417 u8 ib_proto_admin[0x10]; 8418 8419 u8 ext_eth_proto_oper[0x20]; 8420 8421 u8 eth_proto_oper[0x20]; 8422 8423 u8 ib_link_width_oper[0x10]; 8424 u8 ib_proto_oper[0x10]; 8425 8426 u8 reserved_4[0x1c]; 8427 u8 connector_type[0x4]; 8428 8429 u8 eth_proto_lp_advertise[0x20]; 8430 8431 u8 reserved_5[0x60]; 8432 }; 8433 8434 struct mlx5_ifc_ptas_reg_bits { 8435 u8 reserved_0[0x20]; 8436 8437 u8 algorithm_options[0x10]; 8438 u8 reserved_1[0x4]; 8439 u8 repetitions_mode[0x4]; 8440 u8 num_of_repetitions[0x8]; 8441 8442 u8 grade_version[0x8]; 8443 u8 height_grade_type[0x4]; 8444 u8 phase_grade_type[0x4]; 8445 u8 height_grade_weight[0x8]; 8446 u8 phase_grade_weight[0x8]; 8447 8448 u8 gisim_measure_bits[0x10]; 8449 u8 adaptive_tap_measure_bits[0x10]; 8450 8451 u8 ber_bath_high_error_threshold[0x10]; 8452 u8 ber_bath_mid_error_threshold[0x10]; 8453 8454 u8 ber_bath_low_error_threshold[0x10]; 8455 u8 one_ratio_high_threshold[0x10]; 8456 8457 u8 one_ratio_high_mid_threshold[0x10]; 8458 u8 one_ratio_low_mid_threshold[0x10]; 8459 8460 u8 one_ratio_low_threshold[0x10]; 8461 u8 ndeo_error_threshold[0x10]; 8462 8463 u8 mixer_offset_step_size[0x10]; 8464 u8 reserved_2[0x8]; 8465 u8 mix90_phase_for_voltage_bath[0x8]; 8466 8467 u8 mixer_offset_start[0x10]; 8468 u8 mixer_offset_end[0x10]; 8469 8470 u8 reserved_3[0x15]; 8471 u8 ber_test_time[0xb]; 8472 }; 8473 8474 struct mlx5_ifc_pspa_reg_bits { 8475 u8 swid[0x8]; 8476 u8 local_port[0x8]; 8477 u8 sub_port[0x8]; 8478 u8 reserved_0[0x8]; 8479 8480 u8 reserved_1[0x20]; 8481 }; 8482 8483 struct mlx5_ifc_ppsc_reg_bits { 8484 u8 reserved_0[0x8]; 8485 u8 local_port[0x8]; 8486 u8 reserved_1[0x10]; 8487 8488 u8 reserved_2[0x60]; 8489 8490 u8 reserved_3[0x1c]; 8491 u8 wrps_admin[0x4]; 8492 8493 u8 reserved_4[0x1c]; 8494 u8 wrps_status[0x4]; 8495 8496 u8 up_th_vld[0x1]; 8497 u8 down_th_vld[0x1]; 8498 u8 reserved_5[0x6]; 8499 u8 up_threshold[0x8]; 8500 u8 reserved_6[0x8]; 8501 u8 down_threshold[0x8]; 8502 8503 u8 reserved_7[0x20]; 8504 8505 u8 reserved_8[0x1c]; 8506 u8 srps_admin[0x4]; 8507 8508 u8 reserved_9[0x60]; 8509 }; 8510 8511 struct mlx5_ifc_pplr_reg_bits { 8512 u8 reserved_0[0x8]; 8513 u8 local_port[0x8]; 8514 u8 reserved_1[0x10]; 8515 8516 u8 reserved_2[0x8]; 8517 u8 lb_cap[0x8]; 8518 u8 reserved_3[0x8]; 8519 u8 lb_en[0x8]; 8520 }; 8521 8522 struct mlx5_ifc_pplm_reg_bits { 8523 u8 reserved_at_0[0x8]; 8524 u8 local_port[0x8]; 8525 u8 reserved_at_10[0x10]; 8526 8527 u8 reserved_at_20[0x20]; 8528 8529 u8 port_profile_mode[0x8]; 8530 u8 static_port_profile[0x8]; 8531 u8 active_port_profile[0x8]; 8532 u8 reserved_at_58[0x8]; 8533 8534 u8 retransmission_active[0x8]; 8535 u8 fec_mode_active[0x18]; 8536 8537 u8 rs_fec_correction_bypass_cap[0x4]; 8538 u8 reserved_at_84[0x8]; 8539 u8 fec_override_cap_56g[0x4]; 8540 u8 fec_override_cap_100g[0x4]; 8541 u8 fec_override_cap_50g[0x4]; 8542 u8 fec_override_cap_25g[0x4]; 8543 u8 fec_override_cap_10g_40g[0x4]; 8544 8545 u8 rs_fec_correction_bypass_admin[0x4]; 8546 u8 reserved_at_a4[0x8]; 8547 u8 fec_override_admin_56g[0x4]; 8548 u8 fec_override_admin_100g[0x4]; 8549 u8 fec_override_admin_50g[0x4]; 8550 u8 fec_override_admin_25g[0x4]; 8551 u8 fec_override_admin_10g_40g[0x4]; 8552 8553 u8 fec_override_cap_400g_8x[0x10]; 8554 u8 fec_override_cap_200g_4x[0x10]; 8555 u8 fec_override_cap_100g_2x[0x10]; 8556 u8 fec_override_cap_50g_1x[0x10]; 8557 8558 u8 fec_override_admin_400g_8x[0x10]; 8559 u8 fec_override_admin_200g_4x[0x10]; 8560 u8 fec_override_admin_100g_2x[0x10]; 8561 u8 fec_override_admin_50g_1x[0x10]; 8562 8563 u8 reserved_at_140[0x140]; 8564 }; 8565 8566 struct mlx5_ifc_ppll_reg_bits { 8567 u8 num_pll_groups[0x8]; 8568 u8 pll_group[0x8]; 8569 u8 reserved_0[0x4]; 8570 u8 num_plls[0x4]; 8571 u8 reserved_1[0x8]; 8572 8573 u8 reserved_2[0x1f]; 8574 u8 ae[0x1]; 8575 8576 u8 pll_status[4][0x40]; 8577 }; 8578 8579 struct mlx5_ifc_ppad_reg_bits { 8580 u8 reserved_0[0x3]; 8581 u8 single_mac[0x1]; 8582 u8 reserved_1[0x4]; 8583 u8 local_port[0x8]; 8584 u8 mac_47_32[0x10]; 8585 8586 u8 mac_31_0[0x20]; 8587 8588 u8 reserved_2[0x40]; 8589 }; 8590 8591 struct mlx5_ifc_pmtu_reg_bits { 8592 u8 reserved_0[0x8]; 8593 u8 local_port[0x8]; 8594 u8 reserved_1[0x10]; 8595 8596 u8 max_mtu[0x10]; 8597 u8 reserved_2[0x10]; 8598 8599 u8 admin_mtu[0x10]; 8600 u8 reserved_3[0x10]; 8601 8602 u8 oper_mtu[0x10]; 8603 u8 reserved_4[0x10]; 8604 }; 8605 8606 struct mlx5_ifc_pmpr_reg_bits { 8607 u8 reserved_0[0x8]; 8608 u8 module[0x8]; 8609 u8 reserved_1[0x10]; 8610 8611 u8 reserved_2[0x18]; 8612 u8 attenuation_5g[0x8]; 8613 8614 u8 reserved_3[0x18]; 8615 u8 attenuation_7g[0x8]; 8616 8617 u8 reserved_4[0x18]; 8618 u8 attenuation_12g[0x8]; 8619 }; 8620 8621 struct mlx5_ifc_pmpe_reg_bits { 8622 u8 reserved_0[0x8]; 8623 u8 module[0x8]; 8624 u8 reserved_1[0xc]; 8625 u8 module_status[0x4]; 8626 8627 u8 reserved_2[0x14]; 8628 u8 error_type[0x4]; 8629 u8 reserved_3[0x8]; 8630 8631 u8 reserved_4[0x40]; 8632 }; 8633 8634 struct mlx5_ifc_pmpc_reg_bits { 8635 u8 module_state_updated[32][0x8]; 8636 }; 8637 8638 struct mlx5_ifc_pmlpn_reg_bits { 8639 u8 reserved_0[0x4]; 8640 u8 mlpn_status[0x4]; 8641 u8 local_port[0x8]; 8642 u8 reserved_1[0x10]; 8643 8644 u8 e[0x1]; 8645 u8 reserved_2[0x1f]; 8646 }; 8647 8648 struct mlx5_ifc_pmlp_reg_bits { 8649 u8 rxtx[0x1]; 8650 u8 reserved_0[0x7]; 8651 u8 local_port[0x8]; 8652 u8 reserved_1[0x8]; 8653 u8 width[0x8]; 8654 8655 u8 lane0_module_mapping[0x20]; 8656 8657 u8 lane1_module_mapping[0x20]; 8658 8659 u8 lane2_module_mapping[0x20]; 8660 8661 u8 lane3_module_mapping[0x20]; 8662 8663 u8 reserved_2[0x160]; 8664 }; 8665 8666 struct mlx5_ifc_pmaos_reg_bits { 8667 u8 reserved_0[0x8]; 8668 u8 module[0x8]; 8669 u8 reserved_1[0x4]; 8670 u8 admin_status[0x4]; 8671 u8 reserved_2[0x4]; 8672 u8 oper_status[0x4]; 8673 8674 u8 ase[0x1]; 8675 u8 ee[0x1]; 8676 u8 reserved_3[0x12]; 8677 u8 error_type[0x4]; 8678 u8 reserved_4[0x6]; 8679 u8 e[0x2]; 8680 8681 u8 reserved_5[0x40]; 8682 }; 8683 8684 struct mlx5_ifc_plpc_reg_bits { 8685 u8 reserved_0[0x4]; 8686 u8 profile_id[0xc]; 8687 u8 reserved_1[0x4]; 8688 u8 proto_mask[0x4]; 8689 u8 reserved_2[0x8]; 8690 8691 u8 reserved_3[0x10]; 8692 u8 lane_speed[0x10]; 8693 8694 u8 reserved_4[0x17]; 8695 u8 lpbf[0x1]; 8696 u8 fec_mode_policy[0x8]; 8697 8698 u8 retransmission_capability[0x8]; 8699 u8 fec_mode_capability[0x18]; 8700 8701 u8 retransmission_support_admin[0x8]; 8702 u8 fec_mode_support_admin[0x18]; 8703 8704 u8 retransmission_request_admin[0x8]; 8705 u8 fec_mode_request_admin[0x18]; 8706 8707 u8 reserved_5[0x80]; 8708 }; 8709 8710 struct mlx5_ifc_pll_status_data_bits { 8711 u8 reserved_0[0x1]; 8712 u8 lock_cal[0x1]; 8713 u8 lock_status[0x2]; 8714 u8 reserved_1[0x2]; 8715 u8 algo_f_ctrl[0xa]; 8716 u8 analog_algo_num_var[0x6]; 8717 u8 f_ctrl_measure[0xa]; 8718 8719 u8 reserved_2[0x2]; 8720 u8 analog_var[0x6]; 8721 u8 reserved_3[0x2]; 8722 u8 high_var[0x6]; 8723 u8 reserved_4[0x2]; 8724 u8 low_var[0x6]; 8725 u8 reserved_5[0x2]; 8726 u8 mid_val[0x6]; 8727 }; 8728 8729 struct mlx5_ifc_plib_reg_bits { 8730 u8 reserved_0[0x8]; 8731 u8 local_port[0x8]; 8732 u8 reserved_1[0x8]; 8733 u8 ib_port[0x8]; 8734 8735 u8 reserved_2[0x60]; 8736 }; 8737 8738 struct mlx5_ifc_plbf_reg_bits { 8739 u8 reserved_0[0x8]; 8740 u8 local_port[0x8]; 8741 u8 reserved_1[0xd]; 8742 u8 lbf_mode[0x3]; 8743 8744 u8 reserved_2[0x20]; 8745 }; 8746 8747 struct mlx5_ifc_pipg_reg_bits { 8748 u8 reserved_0[0x8]; 8749 u8 local_port[0x8]; 8750 u8 reserved_1[0x10]; 8751 8752 u8 dic[0x1]; 8753 u8 reserved_2[0x19]; 8754 u8 ipg[0x4]; 8755 u8 reserved_3[0x2]; 8756 }; 8757 8758 struct mlx5_ifc_pifr_reg_bits { 8759 u8 reserved_0[0x8]; 8760 u8 local_port[0x8]; 8761 u8 reserved_1[0x10]; 8762 8763 u8 reserved_2[0xe0]; 8764 8765 u8 port_filter[8][0x20]; 8766 8767 u8 port_filter_update_en[8][0x20]; 8768 }; 8769 8770 struct mlx5_ifc_phys_layer_cntrs_bits { 8771 u8 time_since_last_clear_high[0x20]; 8772 8773 u8 time_since_last_clear_low[0x20]; 8774 8775 u8 symbol_errors_high[0x20]; 8776 8777 u8 symbol_errors_low[0x20]; 8778 8779 u8 sync_headers_errors_high[0x20]; 8780 8781 u8 sync_headers_errors_low[0x20]; 8782 8783 u8 edpl_bip_errors_lane0_high[0x20]; 8784 8785 u8 edpl_bip_errors_lane0_low[0x20]; 8786 8787 u8 edpl_bip_errors_lane1_high[0x20]; 8788 8789 u8 edpl_bip_errors_lane1_low[0x20]; 8790 8791 u8 edpl_bip_errors_lane2_high[0x20]; 8792 8793 u8 edpl_bip_errors_lane2_low[0x20]; 8794 8795 u8 edpl_bip_errors_lane3_high[0x20]; 8796 8797 u8 edpl_bip_errors_lane3_low[0x20]; 8798 8799 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 8800 8801 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 8802 8803 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 8804 8805 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 8806 8807 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 8808 8809 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 8810 8811 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 8812 8813 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 8814 8815 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 8816 8817 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 8818 8819 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 8820 8821 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 8822 8823 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 8824 8825 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 8826 8827 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 8828 8829 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 8830 8831 u8 rs_fec_corrected_blocks_high[0x20]; 8832 8833 u8 rs_fec_corrected_blocks_low[0x20]; 8834 8835 u8 rs_fec_uncorrectable_blocks_high[0x20]; 8836 8837 u8 rs_fec_uncorrectable_blocks_low[0x20]; 8838 8839 u8 rs_fec_no_errors_blocks_high[0x20]; 8840 8841 u8 rs_fec_no_errors_blocks_low[0x20]; 8842 8843 u8 rs_fec_single_error_blocks_high[0x20]; 8844 8845 u8 rs_fec_single_error_blocks_low[0x20]; 8846 8847 u8 rs_fec_corrected_symbols_total_high[0x20]; 8848 8849 u8 rs_fec_corrected_symbols_total_low[0x20]; 8850 8851 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 8852 8853 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 8854 8855 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 8856 8857 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 8858 8859 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 8860 8861 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 8862 8863 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 8864 8865 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 8866 8867 u8 link_down_events[0x20]; 8868 8869 u8 successful_recovery_events[0x20]; 8870 8871 u8 reserved_0[0x180]; 8872 }; 8873 8874 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 8875 u8 symbol_error_counter[0x10]; 8876 8877 u8 link_error_recovery_counter[0x8]; 8878 8879 u8 link_downed_counter[0x8]; 8880 8881 u8 port_rcv_errors[0x10]; 8882 8883 u8 port_rcv_remote_physical_errors[0x10]; 8884 8885 u8 port_rcv_switch_relay_errors[0x10]; 8886 8887 u8 port_xmit_discards[0x10]; 8888 8889 u8 port_xmit_constraint_errors[0x8]; 8890 8891 u8 port_rcv_constraint_errors[0x8]; 8892 8893 u8 reserved_at_70[0x8]; 8894 8895 u8 link_overrun_errors[0x8]; 8896 8897 u8 reserved_at_80[0x10]; 8898 8899 u8 vl_15_dropped[0x10]; 8900 8901 u8 reserved_at_a0[0xa0]; 8902 }; 8903 8904 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 8905 u8 time_since_last_clear_high[0x20]; 8906 8907 u8 time_since_last_clear_low[0x20]; 8908 8909 u8 phy_received_bits_high[0x20]; 8910 8911 u8 phy_received_bits_low[0x20]; 8912 8913 u8 phy_symbol_errors_high[0x20]; 8914 8915 u8 phy_symbol_errors_low[0x20]; 8916 8917 u8 phy_corrected_bits_high[0x20]; 8918 8919 u8 phy_corrected_bits_low[0x20]; 8920 8921 u8 phy_corrected_bits_lane0_high[0x20]; 8922 8923 u8 phy_corrected_bits_lane0_low[0x20]; 8924 8925 u8 phy_corrected_bits_lane1_high[0x20]; 8926 8927 u8 phy_corrected_bits_lane1_low[0x20]; 8928 8929 u8 phy_corrected_bits_lane2_high[0x20]; 8930 8931 u8 phy_corrected_bits_lane2_low[0x20]; 8932 8933 u8 phy_corrected_bits_lane3_high[0x20]; 8934 8935 u8 phy_corrected_bits_lane3_low[0x20]; 8936 8937 u8 reserved_at_200[0x5c0]; 8938 }; 8939 8940 struct mlx5_ifc_infiniband_port_cntrs_bits { 8941 u8 symbol_error_counter[0x10]; 8942 u8 link_error_recovery_counter[0x8]; 8943 u8 link_downed_counter[0x8]; 8944 8945 u8 port_rcv_errors[0x10]; 8946 u8 port_rcv_remote_physical_errors[0x10]; 8947 8948 u8 port_rcv_switch_relay_errors[0x10]; 8949 u8 port_xmit_discards[0x10]; 8950 8951 u8 port_xmit_constraint_errors[0x8]; 8952 u8 port_rcv_constraint_errors[0x8]; 8953 u8 reserved_0[0x8]; 8954 u8 local_link_integrity_errors[0x4]; 8955 u8 excessive_buffer_overrun_errors[0x4]; 8956 8957 u8 reserved_1[0x10]; 8958 u8 vl_15_dropped[0x10]; 8959 8960 u8 port_xmit_data[0x20]; 8961 8962 u8 port_rcv_data[0x20]; 8963 8964 u8 port_xmit_pkts[0x20]; 8965 8966 u8 port_rcv_pkts[0x20]; 8967 8968 u8 port_xmit_wait[0x20]; 8969 8970 u8 reserved_2[0x680]; 8971 }; 8972 8973 struct mlx5_ifc_phrr_reg_bits { 8974 u8 clr[0x1]; 8975 u8 reserved_0[0x7]; 8976 u8 local_port[0x8]; 8977 u8 reserved_1[0x10]; 8978 8979 u8 hist_group[0x8]; 8980 u8 reserved_2[0x10]; 8981 u8 hist_id[0x8]; 8982 8983 u8 reserved_3[0x40]; 8984 8985 u8 time_since_last_clear_high[0x20]; 8986 8987 u8 time_since_last_clear_low[0x20]; 8988 8989 u8 bin[10][0x20]; 8990 }; 8991 8992 struct mlx5_ifc_phbr_for_prio_reg_bits { 8993 u8 reserved_0[0x18]; 8994 u8 prio[0x8]; 8995 }; 8996 8997 struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8998 u8 reserved_0[0x18]; 8999 u8 tclass[0x8]; 9000 }; 9001 9002 struct mlx5_ifc_phbr_binding_reg_bits { 9003 u8 opcode[0x4]; 9004 u8 reserved_0[0x4]; 9005 u8 local_port[0x8]; 9006 u8 pnat[0x2]; 9007 u8 reserved_1[0xe]; 9008 9009 u8 hist_group[0x8]; 9010 u8 reserved_2[0x10]; 9011 u8 hist_id[0x8]; 9012 9013 u8 reserved_3[0x10]; 9014 u8 hist_type[0x10]; 9015 9016 u8 hist_parameters[0x20]; 9017 9018 u8 hist_min_value[0x20]; 9019 9020 u8 hist_max_value[0x20]; 9021 9022 u8 sample_time[0x20]; 9023 }; 9024 9025 enum { 9026 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 9027 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 9028 }; 9029 9030 struct mlx5_ifc_pfcc_reg_bits { 9031 u8 dcbx_operation_type[0x2]; 9032 u8 cap_local_admin[0x1]; 9033 u8 cap_remote_admin[0x1]; 9034 u8 reserved_0[0x4]; 9035 u8 local_port[0x8]; 9036 u8 pnat[0x2]; 9037 u8 reserved_1[0xc]; 9038 u8 shl_cap[0x1]; 9039 u8 shl_opr[0x1]; 9040 9041 u8 ppan[0x4]; 9042 u8 reserved_2[0x4]; 9043 u8 prio_mask_tx[0x8]; 9044 u8 reserved_3[0x8]; 9045 u8 prio_mask_rx[0x8]; 9046 9047 u8 pptx[0x1]; 9048 u8 aptx[0x1]; 9049 u8 reserved_4[0x6]; 9050 u8 pfctx[0x8]; 9051 u8 reserved_5[0x8]; 9052 u8 cbftx[0x8]; 9053 9054 u8 pprx[0x1]; 9055 u8 aprx[0x1]; 9056 u8 reserved_6[0x6]; 9057 u8 pfcrx[0x8]; 9058 u8 reserved_7[0x8]; 9059 u8 cbfrx[0x8]; 9060 9061 u8 device_stall_minor_watermark[0x10]; 9062 u8 device_stall_critical_watermark[0x10]; 9063 9064 u8 reserved_8[0x60]; 9065 }; 9066 9067 struct mlx5_ifc_pelc_reg_bits { 9068 u8 op[0x4]; 9069 u8 reserved_0[0x4]; 9070 u8 local_port[0x8]; 9071 u8 reserved_1[0x10]; 9072 9073 u8 op_admin[0x8]; 9074 u8 op_capability[0x8]; 9075 u8 op_request[0x8]; 9076 u8 op_active[0x8]; 9077 9078 u8 admin[0x40]; 9079 9080 u8 capability[0x40]; 9081 9082 u8 request[0x40]; 9083 9084 u8 active[0x40]; 9085 9086 u8 reserved_2[0x80]; 9087 }; 9088 9089 struct mlx5_ifc_peir_reg_bits { 9090 u8 reserved_0[0x8]; 9091 u8 local_port[0x8]; 9092 u8 reserved_1[0x10]; 9093 9094 u8 reserved_2[0xc]; 9095 u8 error_count[0x4]; 9096 u8 reserved_3[0x10]; 9097 9098 u8 reserved_4[0xc]; 9099 u8 lane[0x4]; 9100 u8 reserved_5[0x8]; 9101 u8 error_type[0x8]; 9102 }; 9103 9104 struct mlx5_ifc_qcam_access_reg_cap_mask { 9105 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9106 u8 qpdpm[0x1]; 9107 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9108 u8 qdpm[0x1]; 9109 u8 qpts[0x1]; 9110 u8 qcap[0x1]; 9111 u8 qcam_access_reg_cap_mask_0[0x1]; 9112 }; 9113 9114 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9115 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9116 u8 qpts_trust_both[0x1]; 9117 }; 9118 9119 struct mlx5_ifc_qcam_reg_bits { 9120 u8 reserved_at_0[0x8]; 9121 u8 feature_group[0x8]; 9122 u8 reserved_at_10[0x8]; 9123 u8 access_reg_group[0x8]; 9124 u8 reserved_at_20[0x20]; 9125 9126 union { 9127 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9128 u8 reserved_at_0[0x80]; 9129 } qos_access_reg_cap_mask; 9130 9131 u8 reserved_at_c0[0x80]; 9132 9133 union { 9134 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9135 u8 reserved_at_0[0x80]; 9136 } qos_feature_cap_mask; 9137 9138 u8 reserved_at_1c0[0x80]; 9139 }; 9140 9141 struct mlx5_ifc_pcam_enhanced_features_bits { 9142 u8 reserved_at_0[0x6d]; 9143 u8 rx_icrc_encapsulated_counter[0x1]; 9144 u8 reserved_at_6e[0x4]; 9145 u8 ptys_extended_ethernet[0x1]; 9146 u8 reserved_at_73[0x3]; 9147 u8 pfcc_mask[0x1]; 9148 u8 reserved_at_77[0x3]; 9149 u8 per_lane_error_counters[0x1]; 9150 u8 rx_buffer_fullness_counters[0x1]; 9151 u8 ptys_connector_type[0x1]; 9152 u8 reserved_at_7d[0x1]; 9153 u8 ppcnt_discard_group[0x1]; 9154 u8 ppcnt_statistical_group[0x1]; 9155 }; 9156 9157 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9158 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9159 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9160 9161 u8 reserved_at_40[0xe]; 9162 u8 pddr[0x1]; 9163 u8 reserved_at_4f[0xd]; 9164 9165 u8 pplm[0x1]; 9166 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9167 9168 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9169 u8 pbmc[0x1]; 9170 u8 pptb[0x1]; 9171 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9172 u8 ppcnt[0x1]; 9173 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9174 }; 9175 9176 struct mlx5_ifc_pcam_reg_bits { 9177 u8 reserved_at_0[0x8]; 9178 u8 feature_group[0x8]; 9179 u8 reserved_at_10[0x8]; 9180 u8 access_reg_group[0x8]; 9181 9182 u8 reserved_at_20[0x20]; 9183 9184 union { 9185 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9186 u8 reserved_at_0[0x80]; 9187 } port_access_reg_cap_mask; 9188 9189 u8 reserved_at_c0[0x80]; 9190 9191 union { 9192 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9193 u8 reserved_at_0[0x80]; 9194 } feature_cap_mask; 9195 9196 u8 reserved_at_1c0[0xc0]; 9197 }; 9198 9199 struct mlx5_ifc_mcam_enhanced_features_bits { 9200 u8 reserved_at_0[0x6e]; 9201 u8 pcie_status_and_power[0x1]; 9202 u8 reserved_at_111[0x10]; 9203 u8 pcie_performance_group[0x1]; 9204 }; 9205 9206 struct mlx5_ifc_mcam_access_reg_bits { 9207 u8 reserved_at_0[0x1c]; 9208 u8 mcda[0x1]; 9209 u8 mcc[0x1]; 9210 u8 mcqi[0x1]; 9211 u8 reserved_at_1f[0x1]; 9212 9213 u8 regs_95_to_64[0x20]; 9214 u8 regs_63_to_32[0x20]; 9215 u8 regs_31_to_0[0x20]; 9216 }; 9217 9218 struct mlx5_ifc_mcam_reg_bits { 9219 u8 reserved_at_0[0x8]; 9220 u8 feature_group[0x8]; 9221 u8 reserved_at_10[0x8]; 9222 u8 access_reg_group[0x8]; 9223 9224 u8 reserved_at_20[0x20]; 9225 9226 union { 9227 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9228 u8 reserved_at_0[0x80]; 9229 } mng_access_reg_cap_mask; 9230 9231 u8 reserved_at_c0[0x80]; 9232 9233 union { 9234 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9235 u8 reserved_at_0[0x80]; 9236 } mng_feature_cap_mask; 9237 9238 u8 reserved_at_1c0[0x80]; 9239 }; 9240 9241 struct mlx5_ifc_pcap_reg_bits { 9242 u8 reserved_0[0x8]; 9243 u8 local_port[0x8]; 9244 u8 reserved_1[0x10]; 9245 9246 u8 port_capability_mask[4][0x20]; 9247 }; 9248 9249 struct mlx5_ifc_pbmc_reg_bits { 9250 u8 reserved_at_0[0x8]; 9251 u8 local_port[0x8]; 9252 u8 reserved_at_10[0x10]; 9253 9254 u8 xoff_timer_value[0x10]; 9255 u8 xoff_refresh[0x10]; 9256 9257 u8 reserved_at_40[0x9]; 9258 u8 fullness_threshold[0x7]; 9259 u8 port_buffer_size[0x10]; 9260 9261 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9262 9263 u8 reserved_at_2e0[0x80]; 9264 }; 9265 9266 struct mlx5_ifc_paos_reg_bits { 9267 u8 swid[0x8]; 9268 u8 local_port[0x8]; 9269 u8 reserved_0[0x4]; 9270 u8 admin_status[0x4]; 9271 u8 reserved_1[0x4]; 9272 u8 oper_status[0x4]; 9273 9274 u8 ase[0x1]; 9275 u8 ee[0x1]; 9276 u8 reserved_2[0x1c]; 9277 u8 e[0x2]; 9278 9279 u8 reserved_3[0x40]; 9280 }; 9281 9282 struct mlx5_ifc_pamp_reg_bits { 9283 u8 reserved_0[0x8]; 9284 u8 opamp_group[0x8]; 9285 u8 reserved_1[0xc]; 9286 u8 opamp_group_type[0x4]; 9287 9288 u8 start_index[0x10]; 9289 u8 reserved_2[0x4]; 9290 u8 num_of_indices[0xc]; 9291 9292 u8 index_data[18][0x10]; 9293 }; 9294 9295 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 9296 u8 llr_rx_cells_high[0x20]; 9297 9298 u8 llr_rx_cells_low[0x20]; 9299 9300 u8 llr_rx_error_high[0x20]; 9301 9302 u8 llr_rx_error_low[0x20]; 9303 9304 u8 llr_rx_crc_error_high[0x20]; 9305 9306 u8 llr_rx_crc_error_low[0x20]; 9307 9308 u8 llr_tx_cells_high[0x20]; 9309 9310 u8 llr_tx_cells_low[0x20]; 9311 9312 u8 llr_tx_ret_cells_high[0x20]; 9313 9314 u8 llr_tx_ret_cells_low[0x20]; 9315 9316 u8 llr_tx_ret_events_high[0x20]; 9317 9318 u8 llr_tx_ret_events_low[0x20]; 9319 9320 u8 reserved_0[0x640]; 9321 }; 9322 9323 struct mlx5_ifc_mtmp_reg_bits { 9324 u8 i[0x1]; 9325 u8 reserved_at_1[0x18]; 9326 u8 sensor_index[0x7]; 9327 9328 u8 reserved_at_20[0x10]; 9329 u8 temperature[0x10]; 9330 9331 u8 mte[0x1]; 9332 u8 mtr[0x1]; 9333 u8 reserved_at_42[0x0e]; 9334 u8 max_temperature[0x10]; 9335 9336 u8 tee[0x2]; 9337 u8 reserved_at_62[0x0e]; 9338 u8 temperature_threshold_hi[0x10]; 9339 9340 u8 reserved_at_80[0x10]; 9341 u8 temperature_threshold_lo[0x10]; 9342 9343 u8 reserved_at_100[0x20]; 9344 9345 u8 sensor_name[0x40]; 9346 }; 9347 9348 struct mlx5_ifc_lane_2_module_mapping_bits { 9349 u8 reserved_0[0x6]; 9350 u8 rx_lane[0x2]; 9351 u8 reserved_1[0x6]; 9352 u8 tx_lane[0x2]; 9353 u8 reserved_2[0x8]; 9354 u8 module[0x8]; 9355 }; 9356 9357 struct mlx5_ifc_eth_per_traffic_class_layout_bits { 9358 u8 transmit_queue_high[0x20]; 9359 9360 u8 transmit_queue_low[0x20]; 9361 9362 u8 reserved_0[0x780]; 9363 }; 9364 9365 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 9366 u8 no_buffer_discard_uc_high[0x20]; 9367 9368 u8 no_buffer_discard_uc_low[0x20]; 9369 9370 u8 wred_discard_high[0x20]; 9371 9372 u8 wred_discard_low[0x20]; 9373 9374 u8 reserved_0[0x740]; 9375 }; 9376 9377 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 9378 u8 rx_octets_high[0x20]; 9379 9380 u8 rx_octets_low[0x20]; 9381 9382 u8 reserved_0[0xc0]; 9383 9384 u8 rx_frames_high[0x20]; 9385 9386 u8 rx_frames_low[0x20]; 9387 9388 u8 tx_octets_high[0x20]; 9389 9390 u8 tx_octets_low[0x20]; 9391 9392 u8 reserved_1[0xc0]; 9393 9394 u8 tx_frames_high[0x20]; 9395 9396 u8 tx_frames_low[0x20]; 9397 9398 u8 rx_pause_high[0x20]; 9399 9400 u8 rx_pause_low[0x20]; 9401 9402 u8 rx_pause_duration_high[0x20]; 9403 9404 u8 rx_pause_duration_low[0x20]; 9405 9406 u8 tx_pause_high[0x20]; 9407 9408 u8 tx_pause_low[0x20]; 9409 9410 u8 tx_pause_duration_high[0x20]; 9411 9412 u8 tx_pause_duration_low[0x20]; 9413 9414 u8 rx_pause_transition_high[0x20]; 9415 9416 u8 rx_pause_transition_low[0x20]; 9417 9418 u8 rx_discards_high[0x20]; 9419 9420 u8 rx_discards_low[0x20]; 9421 9422 u8 device_stall_minor_watermark_cnt_high[0x20]; 9423 9424 u8 device_stall_minor_watermark_cnt_low[0x20]; 9425 9426 u8 device_stall_critical_watermark_cnt_high[0x20]; 9427 9428 u8 device_stall_critical_watermark_cnt_low[0x20]; 9429 9430 u8 reserved_2[0x340]; 9431 }; 9432 9433 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 9434 u8 port_transmit_wait_high[0x20]; 9435 9436 u8 port_transmit_wait_low[0x20]; 9437 9438 u8 ecn_marked_high[0x20]; 9439 9440 u8 ecn_marked_low[0x20]; 9441 9442 u8 no_buffer_discard_mc_high[0x20]; 9443 9444 u8 no_buffer_discard_mc_low[0x20]; 9445 9446 u8 rx_ebp_high[0x20]; 9447 9448 u8 rx_ebp_low[0x20]; 9449 9450 u8 tx_ebp_high[0x20]; 9451 9452 u8 tx_ebp_low[0x20]; 9453 9454 u8 rx_buffer_almost_full_high[0x20]; 9455 9456 u8 rx_buffer_almost_full_low[0x20]; 9457 9458 u8 rx_buffer_full_high[0x20]; 9459 9460 u8 rx_buffer_full_low[0x20]; 9461 9462 u8 rx_icrc_encapsulated_high[0x20]; 9463 9464 u8 rx_icrc_encapsulated_low[0x20]; 9465 9466 u8 reserved_0[0x80]; 9467 9468 u8 tx_stats_pkts64octets_high[0x20]; 9469 9470 u8 tx_stats_pkts64octets_low[0x20]; 9471 9472 u8 tx_stats_pkts65to127octets_high[0x20]; 9473 9474 u8 tx_stats_pkts65to127octets_low[0x20]; 9475 9476 u8 tx_stats_pkts128to255octets_high[0x20]; 9477 9478 u8 tx_stats_pkts128to255octets_low[0x20]; 9479 9480 u8 tx_stats_pkts256to511octets_high[0x20]; 9481 9482 u8 tx_stats_pkts256to511octets_low[0x20]; 9483 9484 u8 tx_stats_pkts512to1023octets_high[0x20]; 9485 9486 u8 tx_stats_pkts512to1023octets_low[0x20]; 9487 9488 u8 tx_stats_pkts1024to1518octets_high[0x20]; 9489 9490 u8 tx_stats_pkts1024to1518octets_low[0x20]; 9491 9492 u8 tx_stats_pkts1519to2047octets_high[0x20]; 9493 9494 u8 tx_stats_pkts1519to2047octets_low[0x20]; 9495 9496 u8 tx_stats_pkts2048to4095octets_high[0x20]; 9497 9498 u8 tx_stats_pkts2048to4095octets_low[0x20]; 9499 9500 u8 tx_stats_pkts4096to8191octets_high[0x20]; 9501 9502 u8 tx_stats_pkts4096to8191octets_low[0x20]; 9503 9504 u8 tx_stats_pkts8192to10239octets_high[0x20]; 9505 9506 u8 tx_stats_pkts8192to10239octets_low[0x20]; 9507 9508 u8 reserved_1[0x2C0]; 9509 }; 9510 9511 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 9512 u8 a_frames_transmitted_ok_high[0x20]; 9513 9514 u8 a_frames_transmitted_ok_low[0x20]; 9515 9516 u8 a_frames_received_ok_high[0x20]; 9517 9518 u8 a_frames_received_ok_low[0x20]; 9519 9520 u8 a_frame_check_sequence_errors_high[0x20]; 9521 9522 u8 a_frame_check_sequence_errors_low[0x20]; 9523 9524 u8 a_alignment_errors_high[0x20]; 9525 9526 u8 a_alignment_errors_low[0x20]; 9527 9528 u8 a_octets_transmitted_ok_high[0x20]; 9529 9530 u8 a_octets_transmitted_ok_low[0x20]; 9531 9532 u8 a_octets_received_ok_high[0x20]; 9533 9534 u8 a_octets_received_ok_low[0x20]; 9535 9536 u8 a_multicast_frames_xmitted_ok_high[0x20]; 9537 9538 u8 a_multicast_frames_xmitted_ok_low[0x20]; 9539 9540 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 9541 9542 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 9543 9544 u8 a_multicast_frames_received_ok_high[0x20]; 9545 9546 u8 a_multicast_frames_received_ok_low[0x20]; 9547 9548 u8 a_broadcast_frames_recieved_ok_high[0x20]; 9549 9550 u8 a_broadcast_frames_recieved_ok_low[0x20]; 9551 9552 u8 a_in_range_length_errors_high[0x20]; 9553 9554 u8 a_in_range_length_errors_low[0x20]; 9555 9556 u8 a_out_of_range_length_field_high[0x20]; 9557 9558 u8 a_out_of_range_length_field_low[0x20]; 9559 9560 u8 a_frame_too_long_errors_high[0x20]; 9561 9562 u8 a_frame_too_long_errors_low[0x20]; 9563 9564 u8 a_symbol_error_during_carrier_high[0x20]; 9565 9566 u8 a_symbol_error_during_carrier_low[0x20]; 9567 9568 u8 a_mac_control_frames_transmitted_high[0x20]; 9569 9570 u8 a_mac_control_frames_transmitted_low[0x20]; 9571 9572 u8 a_mac_control_frames_received_high[0x20]; 9573 9574 u8 a_mac_control_frames_received_low[0x20]; 9575 9576 u8 a_unsupported_opcodes_received_high[0x20]; 9577 9578 u8 a_unsupported_opcodes_received_low[0x20]; 9579 9580 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 9581 9582 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 9583 9584 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 9585 9586 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 9587 9588 u8 reserved_0[0x300]; 9589 }; 9590 9591 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 9592 u8 dot3stats_alignment_errors_high[0x20]; 9593 9594 u8 dot3stats_alignment_errors_low[0x20]; 9595 9596 u8 dot3stats_fcs_errors_high[0x20]; 9597 9598 u8 dot3stats_fcs_errors_low[0x20]; 9599 9600 u8 dot3stats_single_collision_frames_high[0x20]; 9601 9602 u8 dot3stats_single_collision_frames_low[0x20]; 9603 9604 u8 dot3stats_multiple_collision_frames_high[0x20]; 9605 9606 u8 dot3stats_multiple_collision_frames_low[0x20]; 9607 9608 u8 dot3stats_sqe_test_errors_high[0x20]; 9609 9610 u8 dot3stats_sqe_test_errors_low[0x20]; 9611 9612 u8 dot3stats_deferred_transmissions_high[0x20]; 9613 9614 u8 dot3stats_deferred_transmissions_low[0x20]; 9615 9616 u8 dot3stats_late_collisions_high[0x20]; 9617 9618 u8 dot3stats_late_collisions_low[0x20]; 9619 9620 u8 dot3stats_excessive_collisions_high[0x20]; 9621 9622 u8 dot3stats_excessive_collisions_low[0x20]; 9623 9624 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 9625 9626 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 9627 9628 u8 dot3stats_carrier_sense_errors_high[0x20]; 9629 9630 u8 dot3stats_carrier_sense_errors_low[0x20]; 9631 9632 u8 dot3stats_frame_too_longs_high[0x20]; 9633 9634 u8 dot3stats_frame_too_longs_low[0x20]; 9635 9636 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 9637 9638 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 9639 9640 u8 dot3stats_symbol_errors_high[0x20]; 9641 9642 u8 dot3stats_symbol_errors_low[0x20]; 9643 9644 u8 dot3control_in_unknown_opcodes_high[0x20]; 9645 9646 u8 dot3control_in_unknown_opcodes_low[0x20]; 9647 9648 u8 dot3in_pause_frames_high[0x20]; 9649 9650 u8 dot3in_pause_frames_low[0x20]; 9651 9652 u8 dot3out_pause_frames_high[0x20]; 9653 9654 u8 dot3out_pause_frames_low[0x20]; 9655 9656 u8 reserved_0[0x3c0]; 9657 }; 9658 9659 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 9660 u8 if_in_octets_high[0x20]; 9661 9662 u8 if_in_octets_low[0x20]; 9663 9664 u8 if_in_ucast_pkts_high[0x20]; 9665 9666 u8 if_in_ucast_pkts_low[0x20]; 9667 9668 u8 if_in_discards_high[0x20]; 9669 9670 u8 if_in_discards_low[0x20]; 9671 9672 u8 if_in_errors_high[0x20]; 9673 9674 u8 if_in_errors_low[0x20]; 9675 9676 u8 if_in_unknown_protos_high[0x20]; 9677 9678 u8 if_in_unknown_protos_low[0x20]; 9679 9680 u8 if_out_octets_high[0x20]; 9681 9682 u8 if_out_octets_low[0x20]; 9683 9684 u8 if_out_ucast_pkts_high[0x20]; 9685 9686 u8 if_out_ucast_pkts_low[0x20]; 9687 9688 u8 if_out_discards_high[0x20]; 9689 9690 u8 if_out_discards_low[0x20]; 9691 9692 u8 if_out_errors_high[0x20]; 9693 9694 u8 if_out_errors_low[0x20]; 9695 9696 u8 if_in_multicast_pkts_high[0x20]; 9697 9698 u8 if_in_multicast_pkts_low[0x20]; 9699 9700 u8 if_in_broadcast_pkts_high[0x20]; 9701 9702 u8 if_in_broadcast_pkts_low[0x20]; 9703 9704 u8 if_out_multicast_pkts_high[0x20]; 9705 9706 u8 if_out_multicast_pkts_low[0x20]; 9707 9708 u8 if_out_broadcast_pkts_high[0x20]; 9709 9710 u8 if_out_broadcast_pkts_low[0x20]; 9711 9712 u8 reserved_0[0x480]; 9713 }; 9714 9715 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 9716 u8 ether_stats_drop_events_high[0x20]; 9717 9718 u8 ether_stats_drop_events_low[0x20]; 9719 9720 u8 ether_stats_octets_high[0x20]; 9721 9722 u8 ether_stats_octets_low[0x20]; 9723 9724 u8 ether_stats_pkts_high[0x20]; 9725 9726 u8 ether_stats_pkts_low[0x20]; 9727 9728 u8 ether_stats_broadcast_pkts_high[0x20]; 9729 9730 u8 ether_stats_broadcast_pkts_low[0x20]; 9731 9732 u8 ether_stats_multicast_pkts_high[0x20]; 9733 9734 u8 ether_stats_multicast_pkts_low[0x20]; 9735 9736 u8 ether_stats_crc_align_errors_high[0x20]; 9737 9738 u8 ether_stats_crc_align_errors_low[0x20]; 9739 9740 u8 ether_stats_undersize_pkts_high[0x20]; 9741 9742 u8 ether_stats_undersize_pkts_low[0x20]; 9743 9744 u8 ether_stats_oversize_pkts_high[0x20]; 9745 9746 u8 ether_stats_oversize_pkts_low[0x20]; 9747 9748 u8 ether_stats_fragments_high[0x20]; 9749 9750 u8 ether_stats_fragments_low[0x20]; 9751 9752 u8 ether_stats_jabbers_high[0x20]; 9753 9754 u8 ether_stats_jabbers_low[0x20]; 9755 9756 u8 ether_stats_collisions_high[0x20]; 9757 9758 u8 ether_stats_collisions_low[0x20]; 9759 9760 u8 ether_stats_pkts64octets_high[0x20]; 9761 9762 u8 ether_stats_pkts64octets_low[0x20]; 9763 9764 u8 ether_stats_pkts65to127octets_high[0x20]; 9765 9766 u8 ether_stats_pkts65to127octets_low[0x20]; 9767 9768 u8 ether_stats_pkts128to255octets_high[0x20]; 9769 9770 u8 ether_stats_pkts128to255octets_low[0x20]; 9771 9772 u8 ether_stats_pkts256to511octets_high[0x20]; 9773 9774 u8 ether_stats_pkts256to511octets_low[0x20]; 9775 9776 u8 ether_stats_pkts512to1023octets_high[0x20]; 9777 9778 u8 ether_stats_pkts512to1023octets_low[0x20]; 9779 9780 u8 ether_stats_pkts1024to1518octets_high[0x20]; 9781 9782 u8 ether_stats_pkts1024to1518octets_low[0x20]; 9783 9784 u8 ether_stats_pkts1519to2047octets_high[0x20]; 9785 9786 u8 ether_stats_pkts1519to2047octets_low[0x20]; 9787 9788 u8 ether_stats_pkts2048to4095octets_high[0x20]; 9789 9790 u8 ether_stats_pkts2048to4095octets_low[0x20]; 9791 9792 u8 ether_stats_pkts4096to8191octets_high[0x20]; 9793 9794 u8 ether_stats_pkts4096to8191octets_low[0x20]; 9795 9796 u8 ether_stats_pkts8192to10239octets_high[0x20]; 9797 9798 u8 ether_stats_pkts8192to10239octets_low[0x20]; 9799 9800 u8 reserved_0[0x280]; 9801 }; 9802 9803 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 9804 u8 symbol_error_counter[0x10]; 9805 u8 link_error_recovery_counter[0x8]; 9806 u8 link_downed_counter[0x8]; 9807 9808 u8 port_rcv_errors[0x10]; 9809 u8 port_rcv_remote_physical_errors[0x10]; 9810 9811 u8 port_rcv_switch_relay_errors[0x10]; 9812 u8 port_xmit_discards[0x10]; 9813 9814 u8 port_xmit_constraint_errors[0x8]; 9815 u8 port_rcv_constraint_errors[0x8]; 9816 u8 reserved_0[0x8]; 9817 u8 local_link_integrity_errors[0x4]; 9818 u8 excessive_buffer_overrun_errors[0x4]; 9819 9820 u8 reserved_1[0x10]; 9821 u8 vl_15_dropped[0x10]; 9822 9823 u8 port_xmit_data[0x20]; 9824 9825 u8 port_rcv_data[0x20]; 9826 9827 u8 port_xmit_pkts[0x20]; 9828 9829 u8 port_rcv_pkts[0x20]; 9830 9831 u8 port_xmit_wait[0x20]; 9832 9833 u8 reserved_2[0x680]; 9834 }; 9835 9836 struct mlx5_ifc_trc_tlb_reg_bits { 9837 u8 reserved_0[0x80]; 9838 9839 u8 tlb_addr[0][0x40]; 9840 }; 9841 9842 struct mlx5_ifc_trc_read_fifo_reg_bits { 9843 u8 reserved_0[0x10]; 9844 u8 requested_event_num[0x10]; 9845 9846 u8 reserved_1[0x20]; 9847 9848 u8 reserved_2[0x10]; 9849 u8 acual_event_num[0x10]; 9850 9851 u8 reserved_3[0x20]; 9852 9853 u8 event[0][0x40]; 9854 }; 9855 9856 struct mlx5_ifc_trc_lock_reg_bits { 9857 u8 reserved_0[0x1f]; 9858 u8 lock[0x1]; 9859 9860 u8 reserved_1[0x60]; 9861 }; 9862 9863 struct mlx5_ifc_trc_filter_reg_bits { 9864 u8 status[0x1]; 9865 u8 reserved_0[0xf]; 9866 u8 filter_index[0x10]; 9867 9868 u8 reserved_1[0x20]; 9869 9870 u8 filter_val[0x20]; 9871 9872 u8 reserved_2[0x1a0]; 9873 }; 9874 9875 struct mlx5_ifc_trc_event_reg_bits { 9876 u8 status[0x1]; 9877 u8 reserved_0[0xf]; 9878 u8 event_index[0x10]; 9879 9880 u8 reserved_1[0x20]; 9881 9882 u8 event_id[0x20]; 9883 9884 u8 event_selector_val[0x10]; 9885 u8 event_selector_size[0x10]; 9886 9887 u8 reserved_2[0x180]; 9888 }; 9889 9890 struct mlx5_ifc_trc_conf_reg_bits { 9891 u8 limit_en[0x1]; 9892 u8 reserved_0[0x3]; 9893 u8 dump_mode[0x4]; 9894 u8 reserved_1[0x15]; 9895 u8 state[0x3]; 9896 9897 u8 reserved_2[0x20]; 9898 9899 u8 limit_event_index[0x20]; 9900 9901 u8 mkey[0x20]; 9902 9903 u8 fifo_ready_ev_num[0x20]; 9904 9905 u8 reserved_3[0x160]; 9906 }; 9907 9908 struct mlx5_ifc_trc_cap_reg_bits { 9909 u8 reserved_0[0x18]; 9910 u8 dump_mode[0x8]; 9911 9912 u8 reserved_1[0x20]; 9913 9914 u8 num_of_events[0x10]; 9915 u8 num_of_filters[0x10]; 9916 9917 u8 fifo_size[0x20]; 9918 9919 u8 tlb_size[0x10]; 9920 u8 event_size[0x10]; 9921 9922 u8 reserved_2[0x160]; 9923 }; 9924 9925 struct mlx5_ifc_set_node_in_bits { 9926 u8 node_description[64][0x8]; 9927 }; 9928 9929 struct mlx5_ifc_register_power_settings_bits { 9930 u8 reserved_0[0x18]; 9931 u8 power_settings_level[0x8]; 9932 9933 u8 reserved_1[0x60]; 9934 }; 9935 9936 struct mlx5_ifc_register_host_endianess_bits { 9937 u8 he[0x1]; 9938 u8 reserved_0[0x1f]; 9939 9940 u8 reserved_1[0x60]; 9941 }; 9942 9943 struct mlx5_ifc_register_diag_buffer_ctrl_bits { 9944 u8 physical_address[0x40]; 9945 }; 9946 9947 struct mlx5_ifc_qtct_reg_bits { 9948 u8 operation_type[0x2]; 9949 u8 cap_local_admin[0x1]; 9950 u8 cap_remote_admin[0x1]; 9951 u8 reserved_0[0x4]; 9952 u8 port_number[0x8]; 9953 u8 reserved_1[0xd]; 9954 u8 prio[0x3]; 9955 9956 u8 reserved_2[0x1d]; 9957 u8 tclass[0x3]; 9958 }; 9959 9960 struct mlx5_ifc_qpdp_reg_bits { 9961 u8 reserved_0[0x8]; 9962 u8 port_number[0x8]; 9963 u8 reserved_1[0x10]; 9964 9965 u8 reserved_2[0x1d]; 9966 u8 pprio[0x3]; 9967 }; 9968 9969 struct mlx5_ifc_port_info_ro_fields_param_bits { 9970 u8 reserved_0[0x8]; 9971 u8 port[0x8]; 9972 u8 max_gid[0x10]; 9973 9974 u8 reserved_1[0x20]; 9975 9976 u8 port_guid[0x40]; 9977 }; 9978 9979 struct mlx5_ifc_nvqc_reg_bits { 9980 u8 type[0x20]; 9981 9982 u8 reserved_0[0x18]; 9983 u8 version[0x4]; 9984 u8 reserved_1[0x2]; 9985 u8 support_wr[0x1]; 9986 u8 support_rd[0x1]; 9987 }; 9988 9989 struct mlx5_ifc_nvia_reg_bits { 9990 u8 reserved_0[0x1d]; 9991 u8 target[0x3]; 9992 9993 u8 reserved_1[0x20]; 9994 }; 9995 9996 struct mlx5_ifc_nvdi_reg_bits { 9997 struct mlx5_ifc_config_item_bits configuration_item_header; 9998 }; 9999 10000 struct mlx5_ifc_nvda_reg_bits { 10001 struct mlx5_ifc_config_item_bits configuration_item_header; 10002 10003 u8 configuration_item_data[0x20]; 10004 }; 10005 10006 struct mlx5_ifc_node_info_ro_fields_param_bits { 10007 u8 system_image_guid[0x40]; 10008 10009 u8 reserved_0[0x40]; 10010 10011 u8 node_guid[0x40]; 10012 10013 u8 reserved_1[0x10]; 10014 u8 max_pkey[0x10]; 10015 10016 u8 reserved_2[0x20]; 10017 }; 10018 10019 struct mlx5_ifc_ets_tcn_config_reg_bits { 10020 u8 g[0x1]; 10021 u8 b[0x1]; 10022 u8 r[0x1]; 10023 u8 reserved_0[0x9]; 10024 u8 group[0x4]; 10025 u8 reserved_1[0x9]; 10026 u8 bw_allocation[0x7]; 10027 10028 u8 reserved_2[0xc]; 10029 u8 max_bw_units[0x4]; 10030 u8 reserved_3[0x8]; 10031 u8 max_bw_value[0x8]; 10032 }; 10033 10034 struct mlx5_ifc_ets_global_config_reg_bits { 10035 u8 reserved_0[0x2]; 10036 u8 r[0x1]; 10037 u8 reserved_1[0x1d]; 10038 10039 u8 reserved_2[0xc]; 10040 u8 max_bw_units[0x4]; 10041 u8 reserved_3[0x8]; 10042 u8 max_bw_value[0x8]; 10043 }; 10044 10045 struct mlx5_ifc_qetc_reg_bits { 10046 u8 reserved_at_0[0x8]; 10047 u8 port_number[0x8]; 10048 u8 reserved_at_10[0x30]; 10049 10050 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10051 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10052 }; 10053 10054 struct mlx5_ifc_nodnic_mac_filters_bits { 10055 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 10056 10057 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 10058 10059 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 10060 10061 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 10062 10063 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 10064 10065 u8 reserved_0[0xc0]; 10066 }; 10067 10068 struct mlx5_ifc_nodnic_gid_filters_bits { 10069 u8 mgid_filter0[16][0x8]; 10070 10071 u8 mgid_filter1[16][0x8]; 10072 10073 u8 mgid_filter2[16][0x8]; 10074 10075 u8 mgid_filter3[16][0x8]; 10076 }; 10077 10078 enum { 10079 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 10080 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 10081 }; 10082 10083 enum { 10084 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 10085 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 10086 }; 10087 10088 struct mlx5_ifc_nodnic_config_reg_bits { 10089 u8 no_dram_nic_revision[0x8]; 10090 u8 hardware_format[0x8]; 10091 u8 support_receive_filter[0x1]; 10092 u8 support_promisc_filter[0x1]; 10093 u8 support_promisc_multicast_filter[0x1]; 10094 u8 reserved_0[0x2]; 10095 u8 log_working_buffer_size[0x3]; 10096 u8 log_pkey_table_size[0x4]; 10097 u8 reserved_1[0x3]; 10098 u8 num_ports[0x1]; 10099 10100 u8 reserved_2[0x2]; 10101 u8 log_max_ring_size[0x6]; 10102 u8 reserved_3[0x18]; 10103 10104 u8 lkey[0x20]; 10105 10106 u8 cqe_format[0x4]; 10107 u8 reserved_4[0x1c]; 10108 10109 u8 node_guid[0x40]; 10110 10111 u8 reserved_5[0x740]; 10112 10113 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 10114 10115 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 10116 }; 10117 10118 struct mlx5_ifc_vlan_layout_bits { 10119 u8 reserved_0[0x14]; 10120 u8 vlan[0xc]; 10121 10122 u8 reserved_1[0x20]; 10123 }; 10124 10125 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10126 u8 reserved_0[0x20]; 10127 10128 u8 mkey[0x20]; 10129 10130 u8 addressh_63_32[0x20]; 10131 10132 u8 addressl_31_0[0x20]; 10133 }; 10134 10135 struct mlx5_ifc_ud_adrs_vector_bits { 10136 u8 dc_key[0x40]; 10137 10138 u8 ext[0x1]; 10139 u8 reserved_0[0x7]; 10140 u8 destination_qp_dct[0x18]; 10141 10142 u8 static_rate[0x4]; 10143 u8 sl_eth_prio[0x4]; 10144 u8 fl[0x1]; 10145 u8 mlid[0x7]; 10146 u8 rlid_udp_sport[0x10]; 10147 10148 u8 reserved_1[0x20]; 10149 10150 u8 rmac_47_16[0x20]; 10151 10152 u8 rmac_15_0[0x10]; 10153 u8 tclass[0x8]; 10154 u8 hop_limit[0x8]; 10155 10156 u8 reserved_2[0x1]; 10157 u8 grh[0x1]; 10158 u8 reserved_3[0x2]; 10159 u8 src_addr_index[0x8]; 10160 u8 flow_label[0x14]; 10161 10162 u8 rgid_rip[16][0x8]; 10163 }; 10164 10165 struct mlx5_ifc_port_module_event_bits { 10166 u8 reserved_0[0x8]; 10167 u8 module[0x8]; 10168 u8 reserved_1[0xc]; 10169 u8 module_status[0x4]; 10170 10171 u8 reserved_2[0x14]; 10172 u8 error_type[0x4]; 10173 u8 reserved_3[0x8]; 10174 10175 u8 reserved_4[0xa0]; 10176 }; 10177 10178 struct mlx5_ifc_icmd_control_bits { 10179 u8 opcode[0x10]; 10180 u8 status[0x8]; 10181 u8 reserved_0[0x7]; 10182 u8 busy[0x1]; 10183 }; 10184 10185 struct mlx5_ifc_eqe_bits { 10186 u8 reserved_0[0x8]; 10187 u8 event_type[0x8]; 10188 u8 reserved_1[0x8]; 10189 u8 event_sub_type[0x8]; 10190 10191 u8 reserved_2[0xe0]; 10192 10193 union mlx5_ifc_event_auto_bits event_data; 10194 10195 u8 reserved_3[0x10]; 10196 u8 signature[0x8]; 10197 u8 reserved_4[0x7]; 10198 u8 owner[0x1]; 10199 }; 10200 10201 enum { 10202 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10203 }; 10204 10205 struct mlx5_ifc_cmd_queue_entry_bits { 10206 u8 type[0x8]; 10207 u8 reserved_0[0x18]; 10208 10209 u8 input_length[0x20]; 10210 10211 u8 input_mailbox_pointer_63_32[0x20]; 10212 10213 u8 input_mailbox_pointer_31_9[0x17]; 10214 u8 reserved_1[0x9]; 10215 10216 u8 command_input_inline_data[16][0x8]; 10217 10218 u8 command_output_inline_data[16][0x8]; 10219 10220 u8 output_mailbox_pointer_63_32[0x20]; 10221 10222 u8 output_mailbox_pointer_31_9[0x17]; 10223 u8 reserved_2[0x9]; 10224 10225 u8 output_length[0x20]; 10226 10227 u8 token[0x8]; 10228 u8 signature[0x8]; 10229 u8 reserved_3[0x8]; 10230 u8 status[0x7]; 10231 u8 ownership[0x1]; 10232 }; 10233 10234 struct mlx5_ifc_cmd_out_bits { 10235 u8 status[0x8]; 10236 u8 reserved_0[0x18]; 10237 10238 u8 syndrome[0x20]; 10239 10240 u8 command_output[0x20]; 10241 }; 10242 10243 struct mlx5_ifc_cmd_in_bits { 10244 u8 opcode[0x10]; 10245 u8 reserved_0[0x10]; 10246 10247 u8 reserved_1[0x10]; 10248 u8 op_mod[0x10]; 10249 10250 u8 command[0][0x20]; 10251 }; 10252 10253 struct mlx5_ifc_cmd_if_box_bits { 10254 u8 mailbox_data[512][0x8]; 10255 10256 u8 reserved_0[0x180]; 10257 10258 u8 next_pointer_63_32[0x20]; 10259 10260 u8 next_pointer_31_10[0x16]; 10261 u8 reserved_1[0xa]; 10262 10263 u8 block_number[0x20]; 10264 10265 u8 reserved_2[0x8]; 10266 u8 token[0x8]; 10267 u8 ctrl_signature[0x8]; 10268 u8 signature[0x8]; 10269 }; 10270 10271 struct mlx5_ifc_mtt_bits { 10272 u8 ptag_63_32[0x20]; 10273 10274 u8 ptag_31_8[0x18]; 10275 u8 reserved_0[0x6]; 10276 u8 wr_en[0x1]; 10277 u8 rd_en[0x1]; 10278 }; 10279 10280 struct mlx5_ifc_tls_progress_params_bits { 10281 u8 valid[0x1]; 10282 u8 reserved_at_1[0x7]; 10283 u8 pd[0x18]; 10284 10285 u8 next_record_tcp_sn[0x20]; 10286 10287 u8 hw_resync_tcp_sn[0x20]; 10288 10289 u8 record_tracker_state[0x2]; 10290 u8 auth_state[0x2]; 10291 u8 reserved_at_64[0x4]; 10292 u8 hw_offset_record_number[0x18]; 10293 }; 10294 10295 struct mlx5_ifc_tls_static_params_bits { 10296 u8 const_2[0x2]; 10297 u8 tls_version[0x4]; 10298 u8 const_1[0x2]; 10299 u8 reserved_at_8[0x14]; 10300 u8 encryption_standard[0x4]; 10301 10302 u8 reserved_at_20[0x20]; 10303 10304 u8 initial_record_number[0x40]; 10305 10306 u8 resync_tcp_sn[0x20]; 10307 10308 u8 gcm_iv[0x20]; 10309 10310 u8 implicit_iv[0x40]; 10311 10312 u8 reserved_at_100[0x8]; 10313 u8 dek_index[0x18]; 10314 10315 u8 reserved_at_120[0xe0]; 10316 }; 10317 10318 /* Vendor Specific Capabilities, VSC */ 10319 enum { 10320 MLX5_VSC_DOMAIN_ICMD = 0x1, 10321 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 10322 MLX5_VSC_DOMAIN_SCAN_CRSPACE = 0x7, 10323 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 10324 }; 10325 10326 struct mlx5_ifc_vendor_specific_cap_bits { 10327 u8 type[0x8]; 10328 u8 length[0x8]; 10329 u8 next_pointer[0x8]; 10330 u8 capability_id[0x8]; 10331 10332 u8 status[0x3]; 10333 u8 reserved_0[0xd]; 10334 u8 space[0x10]; 10335 10336 u8 counter[0x20]; 10337 10338 u8 semaphore[0x20]; 10339 10340 u8 flag[0x1]; 10341 u8 reserved_1[0x1]; 10342 u8 address[0x1e]; 10343 10344 u8 data[0x20]; 10345 }; 10346 10347 struct mlx5_ifc_vsc_space_bits { 10348 u8 status[0x3]; 10349 u8 reserved0[0xd]; 10350 u8 space[0x10]; 10351 }; 10352 10353 struct mlx5_ifc_vsc_addr_bits { 10354 u8 flag[0x1]; 10355 u8 reserved0[0x1]; 10356 u8 address[0x1e]; 10357 }; 10358 10359 enum { 10360 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10361 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10362 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10363 }; 10364 10365 enum { 10366 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10367 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10368 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10369 }; 10370 10371 enum { 10372 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 10373 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 10374 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 10375 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 10376 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 10377 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 10378 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 10379 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 10380 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 10381 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 10382 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 10383 }; 10384 10385 struct mlx5_ifc_initial_seg_bits { 10386 u8 fw_rev_minor[0x10]; 10387 u8 fw_rev_major[0x10]; 10388 10389 u8 cmd_interface_rev[0x10]; 10390 u8 fw_rev_subminor[0x10]; 10391 10392 u8 reserved_0[0x40]; 10393 10394 u8 cmdq_phy_addr_63_32[0x20]; 10395 10396 u8 cmdq_phy_addr_31_12[0x14]; 10397 u8 reserved_1[0x2]; 10398 u8 nic_interface[0x2]; 10399 u8 log_cmdq_size[0x4]; 10400 u8 log_cmdq_stride[0x4]; 10401 10402 u8 command_doorbell_vector[0x20]; 10403 10404 u8 reserved_2[0xf00]; 10405 10406 u8 initializing[0x1]; 10407 u8 reserved_3[0x4]; 10408 u8 nic_interface_supported[0x3]; 10409 u8 reserved_4[0x18]; 10410 10411 struct mlx5_ifc_health_buffer_bits health_buffer; 10412 10413 u8 no_dram_nic_offset[0x20]; 10414 10415 u8 reserved_5[0x6de0]; 10416 10417 u8 internal_timer_h[0x20]; 10418 10419 u8 internal_timer_l[0x20]; 10420 10421 u8 reserved_6[0x20]; 10422 10423 u8 reserved_7[0x1f]; 10424 u8 clear_int[0x1]; 10425 10426 u8 health_syndrome[0x8]; 10427 u8 health_counter[0x18]; 10428 10429 u8 reserved_8[0x17fc0]; 10430 }; 10431 10432 union mlx5_ifc_icmd_interface_document_bits { 10433 struct mlx5_ifc_fw_version_bits fw_version; 10434 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 10435 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 10436 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 10437 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 10438 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 10439 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 10440 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 10441 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 10442 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 10443 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 10444 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 10445 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 10446 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 10447 u8 reserved_0[0x42c0]; 10448 }; 10449 10450 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 10451 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10452 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10453 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10454 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10455 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10456 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10457 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10458 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10459 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 10460 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 10461 u8 reserved_0[0x7c0]; 10462 }; 10463 10464 struct mlx5_ifc_ppcnt_reg_bits { 10465 u8 swid[0x8]; 10466 u8 local_port[0x8]; 10467 u8 pnat[0x2]; 10468 u8 reserved_0[0x8]; 10469 u8 grp[0x6]; 10470 10471 u8 clr[0x1]; 10472 u8 reserved_1[0x1c]; 10473 u8 prio_tc[0x3]; 10474 10475 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10476 }; 10477 10478 struct mlx5_ifc_pcie_lanes_counters_bits { 10479 u8 life_time_counter_high[0x20]; 10480 10481 u8 life_time_counter_low[0x20]; 10482 10483 u8 error_counter_lane0[0x20]; 10484 10485 u8 error_counter_lane1[0x20]; 10486 10487 u8 error_counter_lane2[0x20]; 10488 10489 u8 error_counter_lane3[0x20]; 10490 10491 u8 error_counter_lane4[0x20]; 10492 10493 u8 error_counter_lane5[0x20]; 10494 10495 u8 error_counter_lane6[0x20]; 10496 10497 u8 error_counter_lane7[0x20]; 10498 10499 u8 error_counter_lane8[0x20]; 10500 10501 u8 error_counter_lane9[0x20]; 10502 10503 u8 error_counter_lane10[0x20]; 10504 10505 u8 error_counter_lane11[0x20]; 10506 10507 u8 error_counter_lane12[0x20]; 10508 10509 u8 error_counter_lane13[0x20]; 10510 10511 u8 error_counter_lane14[0x20]; 10512 10513 u8 error_counter_lane15[0x20]; 10514 10515 u8 reserved_at_240[0x580]; 10516 }; 10517 10518 struct mlx5_ifc_pcie_lanes_counters_ext_bits { 10519 u8 reserved_at_0[0x40]; 10520 10521 u8 error_counter_lane0[0x20]; 10522 10523 u8 error_counter_lane1[0x20]; 10524 10525 u8 error_counter_lane2[0x20]; 10526 10527 u8 error_counter_lane3[0x20]; 10528 10529 u8 error_counter_lane4[0x20]; 10530 10531 u8 error_counter_lane5[0x20]; 10532 10533 u8 error_counter_lane6[0x20]; 10534 10535 u8 error_counter_lane7[0x20]; 10536 10537 u8 error_counter_lane8[0x20]; 10538 10539 u8 error_counter_lane9[0x20]; 10540 10541 u8 error_counter_lane10[0x20]; 10542 10543 u8 error_counter_lane11[0x20]; 10544 10545 u8 error_counter_lane12[0x20]; 10546 10547 u8 error_counter_lane13[0x20]; 10548 10549 u8 error_counter_lane14[0x20]; 10550 10551 u8 error_counter_lane15[0x20]; 10552 10553 u8 reserved_at_240[0x580]; 10554 }; 10555 10556 struct mlx5_ifc_pcie_perf_counters_bits { 10557 u8 life_time_counter_high[0x20]; 10558 10559 u8 life_time_counter_low[0x20]; 10560 10561 u8 rx_errors[0x20]; 10562 10563 u8 tx_errors[0x20]; 10564 10565 u8 l0_to_recovery_eieos[0x20]; 10566 10567 u8 l0_to_recovery_ts[0x20]; 10568 10569 u8 l0_to_recovery_framing[0x20]; 10570 10571 u8 l0_to_recovery_retrain[0x20]; 10572 10573 u8 crc_error_dllp[0x20]; 10574 10575 u8 crc_error_tlp[0x20]; 10576 10577 u8 tx_overflow_buffer_pkt[0x40]; 10578 10579 u8 outbound_stalled_reads[0x20]; 10580 10581 u8 outbound_stalled_writes[0x20]; 10582 10583 u8 outbound_stalled_reads_events[0x20]; 10584 10585 u8 outbound_stalled_writes_events[0x20]; 10586 10587 u8 tx_overflow_buffer_marked_pkt[0x40]; 10588 10589 u8 reserved_at_240[0x580]; 10590 }; 10591 10592 struct mlx5_ifc_pcie_perf_counters_ext_bits { 10593 u8 reserved_at_0[0x40]; 10594 10595 u8 rx_errors[0x20]; 10596 10597 u8 tx_errors[0x20]; 10598 10599 u8 reserved_at_80[0xc0]; 10600 10601 u8 tx_overflow_buffer_pkt[0x40]; 10602 10603 u8 outbound_stalled_reads[0x20]; 10604 10605 u8 outbound_stalled_writes[0x20]; 10606 10607 u8 outbound_stalled_reads_events[0x20]; 10608 10609 u8 outbound_stalled_writes_events[0x20]; 10610 10611 u8 tx_overflow_buffer_marked_pkt[0x40]; 10612 10613 u8 reserved_at_240[0x580]; 10614 }; 10615 10616 struct mlx5_ifc_pcie_timers_states_bits { 10617 u8 life_time_counter_high[0x20]; 10618 10619 u8 life_time_counter_low[0x20]; 10620 10621 u8 time_to_boot_image_start[0x20]; 10622 10623 u8 time_to_link_image[0x20]; 10624 10625 u8 calibration_time[0x20]; 10626 10627 u8 time_to_first_perst[0x20]; 10628 10629 u8 time_to_detect_state[0x20]; 10630 10631 u8 time_to_l0[0x20]; 10632 10633 u8 time_to_crs_en[0x20]; 10634 10635 u8 time_to_plastic_image_start[0x20]; 10636 10637 u8 time_to_iron_image_start[0x20]; 10638 10639 u8 perst_handler[0x20]; 10640 10641 u8 times_in_l1[0x20]; 10642 10643 u8 times_in_l23[0x20]; 10644 10645 u8 dl_down[0x20]; 10646 10647 u8 config_cycle1usec[0x20]; 10648 10649 u8 config_cycle2to7usec[0x20]; 10650 10651 u8 config_cycle8to15usec[0x20]; 10652 10653 u8 config_cycle16to63usec[0x20]; 10654 10655 u8 config_cycle64usec[0x20]; 10656 10657 u8 correctable_err_msg_sent[0x20]; 10658 10659 u8 non_fatal_err_msg_sent[0x20]; 10660 10661 u8 fatal_err_msg_sent[0x20]; 10662 10663 u8 reserved_at_2e0[0x4e0]; 10664 }; 10665 10666 struct mlx5_ifc_pcie_timers_states_ext_bits { 10667 u8 reserved_at_0[0x40]; 10668 10669 u8 time_to_boot_image_start[0x20]; 10670 10671 u8 time_to_link_image[0x20]; 10672 10673 u8 calibration_time[0x20]; 10674 10675 u8 time_to_first_perst[0x20]; 10676 10677 u8 time_to_detect_state[0x20]; 10678 10679 u8 time_to_l0[0x20]; 10680 10681 u8 time_to_crs_en[0x20]; 10682 10683 u8 time_to_plastic_image_start[0x20]; 10684 10685 u8 time_to_iron_image_start[0x20]; 10686 10687 u8 perst_handler[0x20]; 10688 10689 u8 times_in_l1[0x20]; 10690 10691 u8 times_in_l23[0x20]; 10692 10693 u8 dl_down[0x20]; 10694 10695 u8 config_cycle1usec[0x20]; 10696 10697 u8 config_cycle2to7usec[0x20]; 10698 10699 u8 config_cycle8to15usec[0x20]; 10700 10701 u8 config_cycle16to63usec[0x20]; 10702 10703 u8 config_cycle64usec[0x20]; 10704 10705 u8 correctable_err_msg_sent[0x20]; 10706 10707 u8 non_fatal_err_msg_sent[0x20]; 10708 10709 u8 fatal_err_msg_sent[0x20]; 10710 10711 u8 reserved_at_2e0[0x4e0]; 10712 }; 10713 10714 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits { 10715 struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters; 10716 struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters; 10717 struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states; 10718 u8 reserved_at_0[0x7c0]; 10719 }; 10720 10721 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits { 10722 struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext; 10723 struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext; 10724 struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext; 10725 u8 reserved_at_0[0x7c0]; 10726 }; 10727 10728 struct mlx5_ifc_mpcnt_reg_bits { 10729 u8 reserved_at_0[0x2]; 10730 u8 depth[0x6]; 10731 u8 pcie_index[0x8]; 10732 u8 node[0x8]; 10733 u8 reserved_at_18[0x2]; 10734 u8 grp[0x6]; 10735 10736 u8 clr[0x1]; 10737 u8 reserved_at_21[0x1f]; 10738 10739 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set; 10740 }; 10741 10742 struct mlx5_ifc_mpcnt_reg_ext_bits { 10743 u8 reserved_at_0[0x2]; 10744 u8 depth[0x6]; 10745 u8 pcie_index[0x8]; 10746 u8 node[0x8]; 10747 u8 reserved_at_18[0x2]; 10748 u8 grp[0x6]; 10749 10750 u8 clr[0x1]; 10751 u8 reserved_at_21[0x1f]; 10752 10753 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set; 10754 }; 10755 10756 struct mlx5_ifc_monitor_opcodes_layout_bits { 10757 u8 reserved_at_0[0x10]; 10758 u8 monitor_opcode[0x10]; 10759 }; 10760 10761 union mlx5_ifc_pddr_status_opcode_bits { 10762 struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes; 10763 u8 reserved_at_0[0x20]; 10764 }; 10765 10766 struct mlx5_ifc_troubleshooting_info_page_layout_bits { 10767 u8 reserved_at_0[0x10]; 10768 u8 group_opcode[0x10]; 10769 10770 union mlx5_ifc_pddr_status_opcode_bits status_opcode; 10771 10772 u8 user_feedback_data[0x10]; 10773 u8 user_feedback_index[0x10]; 10774 10775 u8 status_message[0x760]; 10776 }; 10777 10778 union mlx5_ifc_pddr_page_data_bits { 10779 struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page; 10780 struct mlx5_ifc_pddr_module_info_bits pddr_module_info; 10781 u8 reserved_at_0[0x7c0]; 10782 }; 10783 10784 struct mlx5_ifc_pddr_reg_bits { 10785 u8 reserved_at_0[0x8]; 10786 u8 local_port[0x8]; 10787 u8 pnat[0x2]; 10788 u8 reserved_at_12[0xe]; 10789 10790 u8 reserved_at_20[0x18]; 10791 u8 page_select[0x8]; 10792 10793 union mlx5_ifc_pddr_page_data_bits page_data; 10794 }; 10795 10796 enum { 10797 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050, 10798 MLX5_MPEIN_PWR_STATUS_INVALID = 0, 10799 MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1, 10800 MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2, 10801 }; 10802 10803 struct mlx5_ifc_mpein_reg_bits { 10804 u8 reserved_at_0[0x2]; 10805 u8 depth[0x6]; 10806 u8 pcie_index[0x8]; 10807 u8 node[0x8]; 10808 u8 reserved_at_18[0x8]; 10809 10810 u8 capability_mask[0x20]; 10811 10812 u8 reserved_at_40[0x8]; 10813 u8 link_width_enabled[0x8]; 10814 u8 link_speed_enabled[0x10]; 10815 10816 u8 lane0_physical_position[0x8]; 10817 u8 link_width_active[0x8]; 10818 u8 link_speed_active[0x10]; 10819 10820 u8 num_of_pfs[0x10]; 10821 u8 num_of_vfs[0x10]; 10822 10823 u8 bdf0[0x10]; 10824 u8 reserved_at_b0[0x10]; 10825 10826 u8 max_read_request_size[0x4]; 10827 u8 max_payload_size[0x4]; 10828 u8 reserved_at_c8[0x5]; 10829 u8 pwr_status[0x3]; 10830 u8 port_type[0x4]; 10831 u8 reserved_at_d4[0xb]; 10832 u8 lane_reversal[0x1]; 10833 10834 u8 reserved_at_e0[0x14]; 10835 u8 pci_power[0xc]; 10836 10837 u8 reserved_at_100[0x20]; 10838 10839 u8 device_status[0x10]; 10840 u8 port_state[0x8]; 10841 u8 reserved_at_138[0x8]; 10842 10843 u8 reserved_at_140[0x10]; 10844 u8 receiver_detect_result[0x10]; 10845 10846 u8 reserved_at_160[0x20]; 10847 }; 10848 10849 struct mlx5_ifc_mpein_reg_ext_bits { 10850 u8 reserved_at_0[0x2]; 10851 u8 depth[0x6]; 10852 u8 pcie_index[0x8]; 10853 u8 node[0x8]; 10854 u8 reserved_at_18[0x8]; 10855 10856 u8 reserved_at_20[0x20]; 10857 10858 u8 reserved_at_40[0x8]; 10859 u8 link_width_enabled[0x8]; 10860 u8 link_speed_enabled[0x10]; 10861 10862 u8 lane0_physical_position[0x8]; 10863 u8 link_width_active[0x8]; 10864 u8 link_speed_active[0x10]; 10865 10866 u8 num_of_pfs[0x10]; 10867 u8 num_of_vfs[0x10]; 10868 10869 u8 bdf0[0x10]; 10870 u8 reserved_at_b0[0x10]; 10871 10872 u8 max_read_request_size[0x4]; 10873 u8 max_payload_size[0x4]; 10874 u8 reserved_at_c8[0x5]; 10875 u8 pwr_status[0x3]; 10876 u8 port_type[0x4]; 10877 u8 reserved_at_d4[0xb]; 10878 u8 lane_reversal[0x1]; 10879 }; 10880 10881 struct mlx5_ifc_mcqi_cap_bits { 10882 u8 supported_info_bitmask[0x20]; 10883 10884 u8 component_size[0x20]; 10885 10886 u8 max_component_size[0x20]; 10887 10888 u8 log_mcda_word_size[0x4]; 10889 u8 reserved_at_64[0xc]; 10890 u8 mcda_max_write_size[0x10]; 10891 10892 u8 rd_en[0x1]; 10893 u8 reserved_at_81[0x1]; 10894 u8 match_chip_id[0x1]; 10895 u8 match_psid[0x1]; 10896 u8 check_user_timestamp[0x1]; 10897 u8 match_base_guid_mac[0x1]; 10898 u8 reserved_at_86[0x1a]; 10899 }; 10900 10901 struct mlx5_ifc_mcqi_reg_bits { 10902 u8 read_pending_component[0x1]; 10903 u8 reserved_at_1[0xf]; 10904 u8 component_index[0x10]; 10905 10906 u8 reserved_at_20[0x20]; 10907 10908 u8 reserved_at_40[0x1b]; 10909 u8 info_type[0x5]; 10910 10911 u8 info_size[0x20]; 10912 10913 u8 offset[0x20]; 10914 10915 u8 reserved_at_a0[0x10]; 10916 u8 data_size[0x10]; 10917 10918 u8 data[0][0x20]; 10919 }; 10920 10921 struct mlx5_ifc_mcc_reg_bits { 10922 u8 reserved_at_0[0x4]; 10923 u8 time_elapsed_since_last_cmd[0xc]; 10924 u8 reserved_at_10[0x8]; 10925 u8 instruction[0x8]; 10926 10927 u8 reserved_at_20[0x10]; 10928 u8 component_index[0x10]; 10929 10930 u8 reserved_at_40[0x8]; 10931 u8 update_handle[0x18]; 10932 10933 u8 handle_owner_type[0x4]; 10934 u8 handle_owner_host_id[0x4]; 10935 u8 reserved_at_68[0x1]; 10936 u8 control_progress[0x7]; 10937 u8 error_code[0x8]; 10938 u8 reserved_at_78[0x4]; 10939 u8 control_state[0x4]; 10940 10941 u8 component_size[0x20]; 10942 10943 u8 reserved_at_a0[0x60]; 10944 }; 10945 10946 struct mlx5_ifc_mcda_reg_bits { 10947 u8 reserved_at_0[0x8]; 10948 u8 update_handle[0x18]; 10949 10950 u8 offset[0x20]; 10951 10952 u8 reserved_at_40[0x10]; 10953 u8 size[0x10]; 10954 10955 u8 reserved_at_60[0x20]; 10956 10957 u8 data[0][0x20]; 10958 }; 10959 10960 union mlx5_ifc_ports_control_registers_document_bits { 10961 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 10962 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10963 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10964 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10965 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10966 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10967 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10968 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10969 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10970 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 10971 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 10972 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10973 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 10974 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10975 struct mlx5_ifc_paos_reg_bits paos_reg; 10976 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 10977 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10978 struct mlx5_ifc_peir_reg_bits peir_reg; 10979 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10980 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10981 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 10982 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 10983 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 10984 struct mlx5_ifc_phrr_reg_bits phrr_reg; 10985 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10986 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10987 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10988 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10989 struct mlx5_ifc_plib_reg_bits plib_reg; 10990 struct mlx5_ifc_pll_status_data_bits pll_status_data; 10991 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10992 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10993 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10994 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10995 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10996 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10997 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10998 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10999 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11000 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11001 struct mlx5_ifc_ppll_reg_bits ppll_reg; 11002 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11003 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11004 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11005 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11006 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11007 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11008 struct mlx5_ifc_pude_reg_bits pude_reg; 11009 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11010 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11011 struct mlx5_ifc_slrp_reg_bits slrp_reg; 11012 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11013 u8 reserved_0[0x7880]; 11014 }; 11015 11016 union mlx5_ifc_debug_enhancements_document_bits { 11017 struct mlx5_ifc_health_buffer_bits health_buffer; 11018 u8 reserved_0[0x200]; 11019 }; 11020 11021 union mlx5_ifc_no_dram_nic_document_bits { 11022 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 11023 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 11024 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 11025 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 11026 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 11027 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 11028 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 11029 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 11030 u8 reserved_0[0x3160]; 11031 }; 11032 11033 union mlx5_ifc_uplink_pci_interface_document_bits { 11034 struct mlx5_ifc_initial_seg_bits initial_seg; 11035 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 11036 u8 reserved_0[0x20120]; 11037 }; 11038 11039 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11040 u8 e[0x1]; 11041 u8 reserved_at_01[0x0b]; 11042 u8 prio[0x04]; 11043 }; 11044 11045 struct mlx5_ifc_qpdpm_reg_bits { 11046 u8 reserved_at_0[0x8]; 11047 u8 local_port[0x8]; 11048 u8 reserved_at_10[0x10]; 11049 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11050 }; 11051 11052 struct mlx5_ifc_qpts_reg_bits { 11053 u8 reserved_at_0[0x8]; 11054 u8 local_port[0x8]; 11055 u8 reserved_at_10[0x2d]; 11056 u8 trust_state[0x3]; 11057 }; 11058 11059 struct mlx5_ifc_mfrl_reg_bits { 11060 u8 reserved_at_0[0x38]; 11061 u8 reset_level[0x8]; 11062 }; 11063 11064 enum { 11065 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP = 0x9009, 11066 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR = 0x9109, 11067 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP = 0x900a, 11068 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE = 0x900b, 11069 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR = 0x900f, 11070 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE = 0x910b, 11071 MLX5_MAX_TEMPERATURE = 16, 11072 }; 11073 11074 struct mlx5_ifc_mtbr_temp_record_bits { 11075 u8 max_temperature[0x10]; 11076 u8 temperature[0x10]; 11077 }; 11078 11079 struct mlx5_ifc_mtbr_reg_bits { 11080 u8 reserved_at_0[0x14]; 11081 u8 base_sensor_index[0xc]; 11082 11083 u8 reserved_at_20[0x18]; 11084 u8 num_rec[0x8]; 11085 11086 u8 reserved_at_40[0x40]; 11087 11088 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 11089 }; 11090 11091 struct mlx5_ifc_mtbr_reg_ext_bits { 11092 u8 reserved_at_0[0x14]; 11093 u8 base_sensor_index[0xc]; 11094 11095 u8 reserved_at_20[0x18]; 11096 u8 num_rec[0x8]; 11097 11098 u8 reserved_at_40[0x40]; 11099 11100 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 11101 }; 11102 11103 struct mlx5_ifc_mtcap_bits { 11104 u8 reserved_at_0[0x19]; 11105 u8 sensor_count[0x7]; 11106 11107 u8 reserved_at_20[0x19]; 11108 u8 internal_sensor_count[0x7]; 11109 11110 u8 sensor_map[0x40]; 11111 }; 11112 11113 struct mlx5_ifc_mtcap_ext_bits { 11114 u8 reserved_at_0[0x19]; 11115 u8 sensor_count[0x7]; 11116 11117 u8 reserved_at_20[0x20]; 11118 11119 u8 sensor_map[0x40]; 11120 }; 11121 11122 struct mlx5_ifc_mtecr_bits { 11123 u8 reserved_at_0[0x4]; 11124 u8 last_sensor[0xc]; 11125 u8 reserved_at_10[0x4]; 11126 u8 sensor_count[0xc]; 11127 11128 u8 reserved_at_20[0x19]; 11129 u8 internal_sensor_count[0x7]; 11130 11131 u8 sensor_map_0[0x20]; 11132 11133 u8 reserved_at_60[0x2a0]; 11134 }; 11135 11136 struct mlx5_ifc_mtecr_ext_bits { 11137 u8 reserved_at_0[0x4]; 11138 u8 last_sensor[0xc]; 11139 u8 reserved_at_10[0x4]; 11140 u8 sensor_count[0xc]; 11141 11142 u8 reserved_at_20[0x20]; 11143 11144 u8 sensor_map_0[0x20]; 11145 11146 u8 reserved_at_60[0x2a0]; 11147 }; 11148 11149 struct mlx5_ifc_mtewe_bits { 11150 u8 reserved_at_0[0x4]; 11151 u8 last_sensor[0xc]; 11152 u8 reserved_at_10[0x4]; 11153 u8 sensor_count[0xc]; 11154 11155 u8 sensor_warning_0[0x20]; 11156 11157 u8 reserved_at_40[0x2a0]; 11158 }; 11159 11160 struct mlx5_ifc_mtewe_ext_bits { 11161 u8 reserved_at_0[0x4]; 11162 u8 last_sensor[0xc]; 11163 u8 reserved_at_10[0x4]; 11164 u8 sensor_count[0xc]; 11165 11166 u8 sensor_warning_0[0x20]; 11167 11168 u8 reserved_at_40[0x2a0]; 11169 }; 11170 11171 struct mlx5_ifc_mtmp_bits { 11172 u8 reserved_at_0[0x14]; 11173 u8 sensor_index[0xc]; 11174 11175 u8 reserved_at_20[0x10]; 11176 u8 temperature[0x10]; 11177 11178 u8 mte[0x1]; 11179 u8 mtr[0x1]; 11180 u8 reserved_at_42[0xe]; 11181 u8 max_temperature[0x10]; 11182 11183 u8 tee[0x2]; 11184 u8 reserved_at_62[0xe]; 11185 u8 temperature_threshold_hi[0x10]; 11186 11187 u8 reserved_at_80[0x10]; 11188 u8 temperature_threshold_lo[0x10]; 11189 11190 u8 reserved_at_a0[0x20]; 11191 11192 u8 sensor_name_hi[0x20]; 11193 11194 u8 sensor_name_lo[0x20]; 11195 }; 11196 11197 struct mlx5_ifc_mtmp_ext_bits { 11198 u8 reserved_at_0[0x14]; 11199 u8 sensor_index[0xc]; 11200 11201 u8 reserved_at_20[0x10]; 11202 u8 temperature[0x10]; 11203 11204 u8 mte[0x1]; 11205 u8 mtr[0x1]; 11206 u8 reserved_at_42[0xe]; 11207 u8 max_temperature[0x10]; 11208 11209 u8 tee[0x2]; 11210 u8 reserved_at_62[0xe]; 11211 u8 temperature_threshold_hi[0x10]; 11212 11213 u8 reserved_at_80[0x10]; 11214 u8 temperature_threshold_lo[0x10]; 11215 11216 u8 reserved_at_a0[0x20]; 11217 11218 u8 sensor_name_hi[0x20]; 11219 11220 u8 sensor_name_lo[0x20]; 11221 }; 11222 11223 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 11224 u8 opcode[0x10]; 11225 u8 uid[0x10]; 11226 11227 u8 vhca_tunnel_id[0x10]; 11228 u8 obj_type[0x10]; 11229 11230 u8 obj_id[0x20]; 11231 11232 u8 reserved_at_60[0x20]; 11233 }; 11234 11235 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 11236 u8 status[0x8]; 11237 u8 reserved_at_8[0x18]; 11238 11239 u8 syndrome[0x20]; 11240 11241 u8 obj_id[0x20]; 11242 11243 u8 reserved_at_60[0x20]; 11244 }; 11245 11246 struct mlx5_ifc_umem_bits { 11247 u8 reserved_at_0[0x80]; 11248 11249 u8 reserved_at_80[0x1b]; 11250 u8 log_page_size[0x5]; 11251 11252 u8 page_offset[0x20]; 11253 11254 u8 num_of_mtt[0x40]; 11255 11256 struct mlx5_ifc_mtt_bits mtt[0]; 11257 }; 11258 11259 struct mlx5_ifc_uctx_bits { 11260 u8 cap[0x20]; 11261 11262 u8 reserved_at_20[0x160]; 11263 }; 11264 11265 struct mlx5_ifc_create_umem_in_bits { 11266 u8 opcode[0x10]; 11267 u8 uid[0x10]; 11268 11269 u8 reserved_at_20[0x10]; 11270 u8 op_mod[0x10]; 11271 11272 u8 reserved_at_40[0x40]; 11273 11274 struct mlx5_ifc_umem_bits umem; 11275 }; 11276 11277 struct mlx5_ifc_create_uctx_in_bits { 11278 u8 opcode[0x10]; 11279 u8 reserved_at_10[0x10]; 11280 11281 u8 reserved_at_20[0x10]; 11282 u8 op_mod[0x10]; 11283 11284 u8 reserved_at_40[0x40]; 11285 11286 struct mlx5_ifc_uctx_bits uctx; 11287 }; 11288 11289 struct mlx5_ifc_destroy_uctx_in_bits { 11290 u8 opcode[0x10]; 11291 u8 reserved_at_10[0x10]; 11292 11293 u8 reserved_at_20[0x10]; 11294 u8 op_mod[0x10]; 11295 11296 u8 reserved_at_40[0x10]; 11297 u8 uid[0x10]; 11298 11299 u8 reserved_at_60[0x20]; 11300 }; 11301 11302 struct mlx5_ifc_mtrc_string_db_param_bits { 11303 u8 string_db_base_address[0x20]; 11304 11305 u8 reserved_at_20[0x8]; 11306 u8 string_db_size[0x18]; 11307 }; 11308 11309 struct mlx5_ifc_mtrc_cap_bits { 11310 u8 trace_owner[0x1]; 11311 u8 trace_to_memory[0x1]; 11312 u8 reserved_at_2[0x4]; 11313 u8 trc_ver[0x2]; 11314 u8 reserved_at_8[0x14]; 11315 u8 num_string_db[0x4]; 11316 11317 u8 first_string_trace[0x8]; 11318 u8 num_string_trace[0x8]; 11319 u8 reserved_at_30[0x28]; 11320 11321 u8 log_max_trace_buffer_size[0x8]; 11322 11323 u8 reserved_at_60[0x20]; 11324 11325 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11326 11327 u8 reserved_at_280[0x180]; 11328 }; 11329 11330 struct mlx5_ifc_mtrc_conf_bits { 11331 u8 reserved_at_0[0x1c]; 11332 u8 trace_mode[0x4]; 11333 u8 reserved_at_20[0x18]; 11334 u8 log_trace_buffer_size[0x8]; 11335 u8 trace_mkey[0x20]; 11336 u8 reserved_at_60[0x3a0]; 11337 }; 11338 11339 struct mlx5_ifc_mtrc_stdb_bits { 11340 u8 string_db_index[0x4]; 11341 u8 reserved_at_4[0x4]; 11342 u8 read_size[0x18]; 11343 u8 start_offset[0x20]; 11344 u8 string_db_data[0]; 11345 }; 11346 11347 struct mlx5_ifc_mtrc_ctrl_bits { 11348 u8 trace_status[0x2]; 11349 u8 reserved_at_2[0x2]; 11350 u8 arm_event[0x1]; 11351 u8 reserved_at_5[0xb]; 11352 u8 modify_field_select[0x10]; 11353 u8 reserved_at_20[0x2b]; 11354 u8 current_timestamp52_32[0x15]; 11355 u8 current_timestamp31_0[0x20]; 11356 u8 reserved_at_80[0x180]; 11357 }; 11358 11359 struct mlx5_ifc_affiliated_event_header_bits { 11360 u8 reserved_at_0[0x10]; 11361 u8 obj_type[0x10]; 11362 11363 u8 obj_id[0x20]; 11364 }; 11365 11366 #endif /* MLX5_IFC_H */ 11367