1 /*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_IFC_H 29 #define MLX5_IFC_H 30 31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> 32 33 enum { 34 MLX5_EVENT_TYPE_COMP = 0x0, 35 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 36 MLX5_EVENT_TYPE_COMM_EST = 0x2, 37 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 38 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 39 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 40 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 41 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 42 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 43 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 44 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 45 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 46 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 47 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 48 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 49 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 50 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 51 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 52 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 53 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 54 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 55 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 56 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 57 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 58 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 59 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 60 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 61 MLX5_EVENT_TYPE_CMD = 0xa, 62 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 63 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 64 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 65 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 66 MLX5_EVENT_TYPE_CODING_GENERAL_OBJ_EVENT = 0x27, 67 }; 68 69 enum { 70 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 71 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 72 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 73 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 74 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 75 }; 76 77 enum { 78 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 79 }; 80 81 enum { 82 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 83 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 84 }; 85 86 enum { 87 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 88 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 89 MLX5_CMD_OP_INIT_HCA = 0x102, 90 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 91 MLX5_CMD_OP_ENABLE_HCA = 0x104, 92 MLX5_CMD_OP_DISABLE_HCA = 0x105, 93 MLX5_CMD_OP_QUERY_PAGES = 0x107, 94 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 95 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 96 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 97 MLX5_CMD_OP_SET_ISSI = 0x10b, 98 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 99 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 100 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 101 MLX5_CMD_OP_CREATE_MKEY = 0x200, 102 MLX5_CMD_OP_QUERY_MKEY = 0x201, 103 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 104 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 105 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 106 MLX5_CMD_OP_CREATE_EQ = 0x301, 107 MLX5_CMD_OP_DESTROY_EQ = 0x302, 108 MLX5_CMD_OP_QUERY_EQ = 0x303, 109 MLX5_CMD_OP_GEN_EQE = 0x304, 110 MLX5_CMD_OP_CREATE_CQ = 0x400, 111 MLX5_CMD_OP_DESTROY_CQ = 0x401, 112 MLX5_CMD_OP_QUERY_CQ = 0x402, 113 MLX5_CMD_OP_MODIFY_CQ = 0x403, 114 MLX5_CMD_OP_CREATE_QP = 0x500, 115 MLX5_CMD_OP_DESTROY_QP = 0x501, 116 MLX5_CMD_OP_RST2INIT_QP = 0x502, 117 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 118 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 119 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 120 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 121 MLX5_CMD_OP_2ERR_QP = 0x507, 122 MLX5_CMD_OP_2RST_QP = 0x50a, 123 MLX5_CMD_OP_QUERY_QP = 0x50b, 124 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 125 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 126 MLX5_CMD_OP_CREATE_PSV = 0x600, 127 MLX5_CMD_OP_DESTROY_PSV = 0x601, 128 MLX5_CMD_OP_CREATE_SRQ = 0x700, 129 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 130 MLX5_CMD_OP_QUERY_SRQ = 0x702, 131 MLX5_CMD_OP_ARM_RQ = 0x703, 132 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 133 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 134 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 135 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 136 MLX5_CMD_OP_CREATE_DCT = 0x710, 137 MLX5_CMD_OP_DESTROY_DCT = 0x711, 138 MLX5_CMD_OP_DRAIN_DCT = 0x712, 139 MLX5_CMD_OP_QUERY_DCT = 0x713, 140 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 141 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 142 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 143 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 144 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 145 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 146 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 147 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 148 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 149 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 150 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 151 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 152 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 153 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 154 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 155 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 156 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 157 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 158 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 159 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 160 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 161 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 162 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 163 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 164 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 165 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 166 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 167 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 168 MLX5_CMD_OP_ALLOC_PD = 0x800, 169 MLX5_CMD_OP_DEALLOC_PD = 0x801, 170 MLX5_CMD_OP_ALLOC_UAR = 0x802, 171 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 172 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 173 MLX5_CMD_OP_ACCESS_REG = 0x805, 174 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 175 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 176 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 177 MLX5_CMD_OP_MAD_IFC = 0x50d, 178 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 179 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 180 MLX5_CMD_OP_NOP = 0x80d, 181 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 182 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 183 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 184 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 185 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 186 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 187 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 188 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 189 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 190 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 191 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 192 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 193 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 194 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 195 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 196 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 197 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 198 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 199 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 200 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 201 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 202 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 203 MLX5_CMD_OP_CREATE_LAG = 0x840, 204 MLX5_CMD_OP_MODIFY_LAG = 0x841, 205 MLX5_CMD_OP_QUERY_LAG = 0x842, 206 MLX5_CMD_OP_DESTROY_LAG = 0x843, 207 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 208 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 209 MLX5_CMD_OP_CREATE_TIR = 0x900, 210 MLX5_CMD_OP_MODIFY_TIR = 0x901, 211 MLX5_CMD_OP_DESTROY_TIR = 0x902, 212 MLX5_CMD_OP_QUERY_TIR = 0x903, 213 MLX5_CMD_OP_CREATE_SQ = 0x904, 214 MLX5_CMD_OP_MODIFY_SQ = 0x905, 215 MLX5_CMD_OP_DESTROY_SQ = 0x906, 216 MLX5_CMD_OP_QUERY_SQ = 0x907, 217 MLX5_CMD_OP_CREATE_RQ = 0x908, 218 MLX5_CMD_OP_MODIFY_RQ = 0x909, 219 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 220 MLX5_CMD_OP_QUERY_RQ = 0x90b, 221 MLX5_CMD_OP_CREATE_RMP = 0x90c, 222 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 223 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 224 MLX5_CMD_OP_QUERY_RMP = 0x90f, 225 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 226 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 227 MLX5_CMD_OP_CREATE_TIS = 0x912, 228 MLX5_CMD_OP_MODIFY_TIS = 0x913, 229 MLX5_CMD_OP_DESTROY_TIS = 0x914, 230 MLX5_CMD_OP_QUERY_TIS = 0x915, 231 MLX5_CMD_OP_CREATE_RQT = 0x916, 232 MLX5_CMD_OP_MODIFY_RQT = 0x917, 233 MLX5_CMD_OP_DESTROY_RQT = 0x918, 234 MLX5_CMD_OP_QUERY_RQT = 0x919, 235 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 236 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 237 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 238 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 239 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 240 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 241 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 242 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 243 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 244 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 245 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 246 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 247 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 248 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 249 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 250 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 251 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 252 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 253 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 254 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 255 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 256 MLX5_CMD_OP_CREATE_GENERAL_OBJ = 0xa00, 257 MLX5_CMD_OP_MODIFY_GENERAL_OBJ = 0xa01, 258 MLX5_CMD_OP_QUERY_GENERAL_OBJ = 0xa02, 259 MLX5_CMD_OP_DESTROY_GENERAL_OBJ = 0xa03, 260 261 }; 262 263 enum { 264 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 265 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 266 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 267 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 268 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 269 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 270 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 271 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 272 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 273 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 274 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 275 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 276 }; 277 278 enum { 279 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 280 }; 281 282 enum { 283 MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc, 284 }; 285 286 enum { 287 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 288 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 289 }; 290 291 enum { 292 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1, 293 }; 294 295 struct mlx5_ifc_flow_table_fields_supported_bits { 296 u8 outer_dmac[0x1]; 297 u8 outer_smac[0x1]; 298 u8 outer_ether_type[0x1]; 299 u8 reserved_0[0x1]; 300 u8 outer_first_prio[0x1]; 301 u8 outer_first_cfi[0x1]; 302 u8 outer_first_vid[0x1]; 303 u8 reserved_1[0x1]; 304 u8 outer_second_prio[0x1]; 305 u8 outer_second_cfi[0x1]; 306 u8 outer_second_vid[0x1]; 307 u8 outer_ipv6_flow_label[0x1]; 308 u8 outer_sip[0x1]; 309 u8 outer_dip[0x1]; 310 u8 outer_frag[0x1]; 311 u8 outer_ip_protocol[0x1]; 312 u8 outer_ip_ecn[0x1]; 313 u8 outer_ip_dscp[0x1]; 314 u8 outer_udp_sport[0x1]; 315 u8 outer_udp_dport[0x1]; 316 u8 outer_tcp_sport[0x1]; 317 u8 outer_tcp_dport[0x1]; 318 u8 outer_tcp_flags[0x1]; 319 u8 outer_gre_protocol[0x1]; 320 u8 outer_gre_key[0x1]; 321 u8 outer_vxlan_vni[0x1]; 322 u8 outer_geneve_vni[0x1]; 323 u8 outer_geneve_oam[0x1]; 324 u8 outer_geneve_protocol_type[0x1]; 325 u8 outer_geneve_opt_len[0x1]; 326 u8 reserved_2[0x1]; 327 u8 source_eswitch_port[0x1]; 328 329 u8 inner_dmac[0x1]; 330 u8 inner_smac[0x1]; 331 u8 inner_ether_type[0x1]; 332 u8 reserved_3[0x1]; 333 u8 inner_first_prio[0x1]; 334 u8 inner_first_cfi[0x1]; 335 u8 inner_first_vid[0x1]; 336 u8 reserved_4[0x1]; 337 u8 inner_second_prio[0x1]; 338 u8 inner_second_cfi[0x1]; 339 u8 inner_second_vid[0x1]; 340 u8 inner_ipv6_flow_label[0x1]; 341 u8 inner_sip[0x1]; 342 u8 inner_dip[0x1]; 343 u8 inner_frag[0x1]; 344 u8 inner_ip_protocol[0x1]; 345 u8 inner_ip_ecn[0x1]; 346 u8 inner_ip_dscp[0x1]; 347 u8 inner_udp_sport[0x1]; 348 u8 inner_udp_dport[0x1]; 349 u8 inner_tcp_sport[0x1]; 350 u8 inner_tcp_dport[0x1]; 351 u8 inner_tcp_flags[0x1]; 352 u8 reserved_5[0x9]; 353 354 u8 reserved_6[0x1a]; 355 u8 bth_dst_qp[0x1]; 356 u8 reserved_7[0x4]; 357 u8 source_sqn[0x1]; 358 359 u8 reserved_8[0x20]; 360 }; 361 362 struct mlx5_ifc_eth_discard_cntrs_grp_bits { 363 u8 ingress_general_high[0x20]; 364 365 u8 ingress_general_low[0x20]; 366 367 u8 ingress_policy_engine_high[0x20]; 368 369 u8 ingress_policy_engine_low[0x20]; 370 371 u8 ingress_vlan_membership_high[0x20]; 372 373 u8 ingress_vlan_membership_low[0x20]; 374 375 u8 ingress_tag_frame_type_high[0x20]; 376 377 u8 ingress_tag_frame_type_low[0x20]; 378 379 u8 egress_vlan_membership_high[0x20]; 380 381 u8 egress_vlan_membership_low[0x20]; 382 383 u8 loopback_filter_high[0x20]; 384 385 u8 loopback_filter_low[0x20]; 386 387 u8 egress_general_high[0x20]; 388 389 u8 egress_general_low[0x20]; 390 391 u8 reserved_at_1c0[0x40]; 392 393 u8 egress_hoq_high[0x20]; 394 395 u8 egress_hoq_low[0x20]; 396 397 u8 port_isolation_high[0x20]; 398 399 u8 port_isolation_low[0x20]; 400 401 u8 egress_policy_engine_high[0x20]; 402 403 u8 egress_policy_engine_low[0x20]; 404 405 u8 ingress_tx_link_down_high[0x20]; 406 407 u8 ingress_tx_link_down_low[0x20]; 408 409 u8 egress_stp_filter_high[0x20]; 410 411 u8 egress_stp_filter_low[0x20]; 412 413 u8 egress_hoq_stall_high[0x20]; 414 415 u8 egress_hoq_stall_low[0x20]; 416 417 u8 reserved_at_340[0x440]; 418 }; 419 struct mlx5_ifc_flow_table_prop_layout_bits { 420 u8 ft_support[0x1]; 421 u8 flow_tag[0x1]; 422 u8 flow_counter[0x1]; 423 u8 flow_modify_en[0x1]; 424 u8 modify_root[0x1]; 425 u8 identified_miss_table[0x1]; 426 u8 flow_table_modify[0x1]; 427 u8 encap[0x1]; 428 u8 decap[0x1]; 429 u8 reset_root_to_default[0x1]; 430 u8 reserved_at_a[0x16]; 431 432 u8 reserved_at_20[0x2]; 433 u8 log_max_ft_size[0x6]; 434 u8 reserved_at_28[0x10]; 435 u8 max_ft_level[0x8]; 436 437 u8 reserved_at_40[0x20]; 438 439 u8 reserved_at_60[0x18]; 440 u8 log_max_ft_num[0x8]; 441 442 u8 reserved_at_80[0x10]; 443 u8 log_max_flow_counter[0x8]; 444 u8 log_max_destination[0x8]; 445 446 u8 reserved_at_a0[0x18]; 447 u8 log_max_flow[0x8]; 448 449 u8 reserved_at_c0[0x40]; 450 451 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 452 453 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 454 }; 455 456 struct mlx5_ifc_odp_per_transport_service_cap_bits { 457 u8 send[0x1]; 458 u8 receive[0x1]; 459 u8 write[0x1]; 460 u8 read[0x1]; 461 u8 atomic[0x1]; 462 u8 srq_receive[0x1]; 463 u8 reserved_0[0x1a]; 464 }; 465 466 struct mlx5_ifc_flow_counter_list_bits { 467 u8 reserved_0[0x10]; 468 u8 flow_counter_id[0x10]; 469 470 u8 reserved_1[0x20]; 471 }; 472 473 enum { 474 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 475 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 476 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 477 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 478 }; 479 480 struct mlx5_ifc_dest_format_struct_bits { 481 u8 destination_type[0x8]; 482 u8 destination_id[0x18]; 483 484 u8 reserved_0[0x20]; 485 }; 486 487 struct mlx5_ifc_ipv4_layout_bits { 488 u8 reserved_at_0[0x60]; 489 490 u8 ipv4[0x20]; 491 }; 492 493 struct mlx5_ifc_ipv6_layout_bits { 494 u8 ipv6[16][0x8]; 495 }; 496 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 498 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 499 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 500 u8 reserved_at_0[0x80]; 501 }; 502 503 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 504 u8 smac_47_16[0x20]; 505 506 u8 smac_15_0[0x10]; 507 u8 ethertype[0x10]; 508 509 u8 dmac_47_16[0x20]; 510 511 u8 dmac_15_0[0x10]; 512 u8 first_prio[0x3]; 513 u8 first_cfi[0x1]; 514 u8 first_vid[0xc]; 515 516 u8 ip_protocol[0x8]; 517 u8 ip_dscp[0x6]; 518 u8 ip_ecn[0x2]; 519 u8 cvlan_tag[0x1]; 520 u8 svlan_tag[0x1]; 521 u8 frag[0x1]; 522 u8 reserved_1[0x4]; 523 u8 tcp_flags[0x9]; 524 525 u8 tcp_sport[0x10]; 526 u8 tcp_dport[0x10]; 527 528 u8 reserved_2[0x20]; 529 530 u8 udp_sport[0x10]; 531 u8 udp_dport[0x10]; 532 533 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 534 535 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 536 }; 537 538 struct mlx5_ifc_fte_match_set_misc_bits { 539 u8 reserved_0[0x8]; 540 u8 source_sqn[0x18]; 541 542 u8 reserved_1[0x10]; 543 u8 source_port[0x10]; 544 545 u8 outer_second_prio[0x3]; 546 u8 outer_second_cfi[0x1]; 547 u8 outer_second_vid[0xc]; 548 u8 inner_second_prio[0x3]; 549 u8 inner_second_cfi[0x1]; 550 u8 inner_second_vid[0xc]; 551 552 u8 outer_second_vlan_tag[0x1]; 553 u8 inner_second_vlan_tag[0x1]; 554 u8 reserved_2[0xe]; 555 u8 gre_protocol[0x10]; 556 557 u8 gre_key_h[0x18]; 558 u8 gre_key_l[0x8]; 559 560 u8 vxlan_vni[0x18]; 561 u8 reserved_3[0x8]; 562 563 u8 geneve_vni[0x18]; 564 u8 reserved4[0x7]; 565 u8 geneve_oam[0x1]; 566 567 u8 reserved_5[0xc]; 568 u8 outer_ipv6_flow_label[0x14]; 569 570 u8 reserved_6[0xc]; 571 u8 inner_ipv6_flow_label[0x14]; 572 573 u8 reserved_7[0xa]; 574 u8 geneve_opt_len[0x6]; 575 u8 geneve_protocol_type[0x10]; 576 577 u8 reserved_8[0x8]; 578 u8 bth_dst_qp[0x18]; 579 580 u8 reserved_9[0xa0]; 581 }; 582 583 struct mlx5_ifc_cmd_pas_bits { 584 u8 pa_h[0x20]; 585 586 u8 pa_l[0x14]; 587 u8 reserved_0[0xc]; 588 }; 589 590 struct mlx5_ifc_uint64_bits { 591 u8 hi[0x20]; 592 593 u8 lo[0x20]; 594 }; 595 596 struct mlx5_ifc_application_prio_entry_bits { 597 u8 reserved_0[0x8]; 598 u8 priority[0x3]; 599 u8 reserved_1[0x2]; 600 u8 sel[0x3]; 601 u8 protocol_id[0x10]; 602 }; 603 604 struct mlx5_ifc_nodnic_ring_doorbell_bits { 605 u8 reserved_0[0x8]; 606 u8 ring_pi[0x10]; 607 u8 reserved_1[0x8]; 608 }; 609 610 enum { 611 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 612 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 613 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 614 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 615 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 616 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 617 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 618 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 619 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 620 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 621 }; 622 623 struct mlx5_ifc_ads_bits { 624 u8 fl[0x1]; 625 u8 free_ar[0x1]; 626 u8 reserved_0[0xe]; 627 u8 pkey_index[0x10]; 628 629 u8 reserved_1[0x8]; 630 u8 grh[0x1]; 631 u8 mlid[0x7]; 632 u8 rlid[0x10]; 633 634 u8 ack_timeout[0x5]; 635 u8 reserved_2[0x3]; 636 u8 src_addr_index[0x8]; 637 u8 log_rtm[0x4]; 638 u8 stat_rate[0x4]; 639 u8 hop_limit[0x8]; 640 641 u8 reserved_3[0x4]; 642 u8 tclass[0x8]; 643 u8 flow_label[0x14]; 644 645 u8 rgid_rip[16][0x8]; 646 647 u8 reserved_4[0x4]; 648 u8 f_dscp[0x1]; 649 u8 f_ecn[0x1]; 650 u8 reserved_5[0x1]; 651 u8 f_eth_prio[0x1]; 652 u8 ecn[0x2]; 653 u8 dscp[0x6]; 654 u8 udp_sport[0x10]; 655 656 u8 dei_cfi[0x1]; 657 u8 eth_prio[0x3]; 658 u8 sl[0x4]; 659 u8 port[0x8]; 660 u8 rmac_47_32[0x10]; 661 662 u8 rmac_31_0[0x20]; 663 }; 664 665 struct mlx5_ifc_diagnostic_counter_cap_bits { 666 u8 sync[0x1]; 667 u8 reserved_0[0xf]; 668 u8 counter_id[0x10]; 669 }; 670 671 struct mlx5_ifc_debug_cap_bits { 672 u8 reserved_0[0x18]; 673 u8 log_max_samples[0x8]; 674 675 u8 single[0x1]; 676 u8 repetitive[0x1]; 677 u8 health_mon_rx_activity[0x1]; 678 u8 reserved_1[0x15]; 679 u8 log_min_sample_period[0x8]; 680 681 u8 reserved_2[0x1c0]; 682 683 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 684 }; 685 686 struct mlx5_ifc_qos_cap_bits { 687 u8 packet_pacing[0x1]; 688 u8 esw_scheduling[0x1]; 689 u8 esw_bw_share[0x1]; 690 u8 esw_rate_limit[0x1]; 691 u8 hll[0x1]; 692 u8 packet_pacing_burst_bound[0x1]; 693 u8 packet_pacing_typical_size[0x1]; 694 u8 reserved_at_7[0x19]; 695 696 u8 reserved_at_20[0x20]; 697 698 u8 packet_pacing_max_rate[0x20]; 699 700 u8 packet_pacing_min_rate[0x20]; 701 702 u8 reserved_at_80[0x10]; 703 u8 packet_pacing_rate_table_size[0x10]; 704 705 u8 esw_element_type[0x10]; 706 u8 esw_tsar_type[0x10]; 707 708 u8 reserved_at_c0[0x10]; 709 u8 max_qos_para_vport[0x10]; 710 711 u8 max_tsar_bw_share[0x20]; 712 713 u8 reserved_at_100[0x700]; 714 }; 715 716 struct mlx5_ifc_snapshot_cap_bits { 717 u8 reserved_0[0x1d]; 718 u8 suspend_qp_uc[0x1]; 719 u8 suspend_qp_ud[0x1]; 720 u8 suspend_qp_rc[0x1]; 721 722 u8 reserved_1[0x1c]; 723 u8 restore_pd[0x1]; 724 u8 restore_uar[0x1]; 725 u8 restore_mkey[0x1]; 726 u8 restore_qp[0x1]; 727 728 u8 reserved_2[0x1e]; 729 u8 named_mkey[0x1]; 730 u8 named_qp[0x1]; 731 732 u8 reserved_3[0x7a0]; 733 }; 734 735 struct mlx5_ifc_e_switch_cap_bits { 736 u8 vport_svlan_strip[0x1]; 737 u8 vport_cvlan_strip[0x1]; 738 u8 vport_svlan_insert[0x1]; 739 u8 vport_cvlan_insert_if_not_exist[0x1]; 740 u8 vport_cvlan_insert_overwrite[0x1]; 741 742 u8 reserved_0[0x19]; 743 744 u8 nic_vport_node_guid_modify[0x1]; 745 u8 nic_vport_port_guid_modify[0x1]; 746 747 u8 reserved_1[0x7e0]; 748 }; 749 750 struct mlx5_ifc_flow_table_eswitch_cap_bits { 751 u8 reserved_0[0x200]; 752 753 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 754 755 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 756 757 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 758 759 u8 reserved_1[0x7800]; 760 }; 761 762 struct mlx5_ifc_flow_table_nic_cap_bits { 763 u8 nic_rx_multi_path_tirs[0x1]; 764 u8 nic_rx_multi_path_tirs_fts[0x1]; 765 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 766 u8 reserved_at_3[0x1fd]; 767 768 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 769 770 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 771 772 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 773 774 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 775 776 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 777 778 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 779 780 u8 reserved_1[0x7200]; 781 }; 782 783 enum { 784 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_PDDR = 0x5031, 785 }; 786 787 struct mlx5_ifc_pddr_module_info_bits { 788 u8 cable_technology[0x8]; 789 u8 cable_breakout[0x8]; 790 u8 ext_ethernet_compliance_code[0x8]; 791 u8 ethernet_compliance_code[0x8]; 792 793 u8 cable_type[0x4]; 794 u8 cable_vendor[0x4]; 795 u8 cable_length[0x8]; 796 u8 cable_identifier[0x8]; 797 u8 cable_power_class[0x8]; 798 799 u8 reserved_at_40[0x8]; 800 u8 cable_rx_amp[0x8]; 801 u8 cable_rx_emphasis[0x8]; 802 u8 cable_tx_equalization[0x8]; 803 804 u8 reserved_at_60[0x8]; 805 u8 cable_attenuation_12g[0x8]; 806 u8 cable_attenuation_7g[0x8]; 807 u8 cable_attenuation_5g[0x8]; 808 809 u8 reserved_at_80[0x8]; 810 u8 rx_cdr_cap[0x4]; 811 u8 tx_cdr_cap[0x4]; 812 u8 reserved_at_90[0x4]; 813 u8 rx_cdr_state[0x4]; 814 u8 reserved_at_98[0x4]; 815 u8 tx_cdr_state[0x4]; 816 817 u8 vendor_name[16][0x8]; 818 819 u8 vendor_pn[16][0x8]; 820 821 u8 vendor_rev[0x20]; 822 823 u8 fw_version[0x20]; 824 825 u8 vendor_sn[16][0x8]; 826 827 u8 temperature[0x10]; 828 u8 voltage[0x10]; 829 830 u8 rx_power_lane0[0x10]; 831 u8 rx_power_lane1[0x10]; 832 833 u8 rx_power_lane2[0x10]; 834 u8 rx_power_lane3[0x10]; 835 836 u8 reserved_at_2c0[0x40]; 837 838 u8 tx_power_lane0[0x10]; 839 u8 tx_power_lane1[0x10]; 840 841 u8 tx_power_lane2[0x10]; 842 u8 tx_power_lane3[0x10]; 843 844 u8 reserved_at_340[0x40]; 845 846 u8 tx_bias_lane0[0x10]; 847 u8 tx_bias_lane1[0x10]; 848 849 u8 tx_bias_lane2[0x10]; 850 u8 tx_bias_lane3[0x10]; 851 852 u8 reserved_at_3c0[0x40]; 853 854 u8 temperature_high_th[0x10]; 855 u8 temperature_low_th[0x10]; 856 857 u8 voltage_high_th[0x10]; 858 u8 voltage_low_th[0x10]; 859 860 u8 rx_power_high_th[0x10]; 861 u8 rx_power_low_th[0x10]; 862 863 u8 tx_power_high_th[0x10]; 864 u8 tx_power_low_th[0x10]; 865 866 u8 tx_bias_high_th[0x10]; 867 u8 tx_bias_low_th[0x10]; 868 869 u8 reserved_at_4a0[0x10]; 870 u8 wavelength[0x10]; 871 872 u8 reserved_at_4c0[0x300]; 873 }; 874 875 union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits { 876 struct mlx5_ifc_pddr_module_info_bits pddr_module_info; 877 u8 reserved_at_0[0x7c0]; 878 }; 879 880 struct mlx5_ifc_pddr_reg_bits { 881 u8 reserved_at_0[0x8]; 882 u8 local_port[0x8]; 883 u8 pnat[0x2]; 884 u8 reserved_at_12[0xe]; 885 886 u8 reserved_at_20[0x18]; 887 u8 page_select[0x8]; 888 889 union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits page_data; 890 }; 891 892 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 893 u8 csum_cap[0x1]; 894 u8 vlan_cap[0x1]; 895 u8 lro_cap[0x1]; 896 u8 lro_psh_flag[0x1]; 897 u8 lro_time_stamp[0x1]; 898 u8 lro_max_msg_sz_mode[0x2]; 899 u8 wqe_vlan_insert[0x1]; 900 u8 self_lb_en_modifiable[0x1]; 901 u8 self_lb_mc[0x1]; 902 u8 self_lb_uc[0x1]; 903 u8 max_lso_cap[0x5]; 904 u8 multi_pkt_send_wqe[0x2]; 905 u8 wqe_inline_mode[0x2]; 906 u8 rss_ind_tbl_cap[0x4]; 907 u8 scatter_fcs[0x1]; 908 u8 reserved_1[0x2]; 909 u8 tunnel_lso_const_out_ip_id[0x1]; 910 u8 tunnel_lro_gre[0x1]; 911 u8 tunnel_lro_vxlan[0x1]; 912 u8 tunnel_statless_gre[0x1]; 913 u8 tunnel_stateless_vxlan[0x1]; 914 915 u8 swp[0x1]; 916 u8 swp_csum[0x1]; 917 u8 swp_lso[0x1]; 918 u8 reserved_2[0x1b]; 919 u8 max_geneve_opt_len[0x1]; 920 u8 tunnel_stateless_geneve_rx[0x1]; 921 922 u8 reserved_3[0x10]; 923 u8 lro_min_mss_size[0x10]; 924 925 u8 reserved_4[0x120]; 926 927 u8 lro_timer_supported_periods[4][0x20]; 928 929 u8 reserved_5[0x600]; 930 }; 931 932 enum { 933 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 934 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 935 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 936 }; 937 938 struct mlx5_ifc_roce_cap_bits { 939 u8 roce_apm[0x1]; 940 u8 rts2rts_primary_eth_prio[0x1]; 941 u8 roce_rx_allow_untagged[0x1]; 942 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 943 944 u8 reserved_0[0x1c]; 945 946 u8 reserved_1[0x60]; 947 948 u8 reserved_2[0xc]; 949 u8 l3_type[0x4]; 950 u8 reserved_3[0x8]; 951 u8 roce_version[0x8]; 952 953 u8 reserved_4[0x10]; 954 u8 r_roce_dest_udp_port[0x10]; 955 956 u8 r_roce_max_src_udp_port[0x10]; 957 u8 r_roce_min_src_udp_port[0x10]; 958 959 u8 reserved_5[0x10]; 960 u8 roce_address_table_size[0x10]; 961 962 u8 reserved_6[0x700]; 963 }; 964 965 enum { 966 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 967 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 968 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 969 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 970 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 971 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 972 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 973 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 974 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 975 }; 976 977 enum { 978 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 979 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 980 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 981 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 982 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 983 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 984 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 985 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 986 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 987 }; 988 989 struct mlx5_ifc_atomic_caps_bits { 990 u8 reserved_0[0x40]; 991 992 u8 atomic_req_8B_endianess_mode[0x2]; 993 u8 reserved_1[0x4]; 994 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 995 996 u8 reserved_2[0x19]; 997 998 u8 reserved_3[0x20]; 999 1000 u8 reserved_4[0x10]; 1001 u8 atomic_operations[0x10]; 1002 1003 u8 reserved_5[0x10]; 1004 u8 atomic_size_qp[0x10]; 1005 1006 u8 reserved_6[0x10]; 1007 u8 atomic_size_dc[0x10]; 1008 1009 u8 reserved_7[0x720]; 1010 }; 1011 1012 struct mlx5_ifc_odp_cap_bits { 1013 u8 reserved_0[0x40]; 1014 1015 u8 sig[0x1]; 1016 u8 reserved_1[0x1f]; 1017 1018 u8 reserved_2[0x20]; 1019 1020 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1021 1022 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1023 1024 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1025 1026 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1027 1028 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1029 1030 u8 reserved_3[0x6e0]; 1031 }; 1032 1033 enum { 1034 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1035 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1036 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1037 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1038 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1039 }; 1040 1041 enum { 1042 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1043 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1044 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1045 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1046 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1047 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1048 }; 1049 1050 enum { 1051 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1052 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1053 }; 1054 1055 enum { 1056 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1057 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1058 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1059 }; 1060 1061 struct mlx5_ifc_cmd_hca_cap_bits { 1062 u8 reserved_0[0x80]; 1063 1064 u8 log_max_srq_sz[0x8]; 1065 u8 log_max_qp_sz[0x8]; 1066 u8 reserved_1[0xb]; 1067 u8 log_max_qp[0x5]; 1068 1069 u8 reserved_2[0xb]; 1070 u8 log_max_srq[0x5]; 1071 u8 reserved_3[0x10]; 1072 1073 u8 reserved_4[0x8]; 1074 u8 log_max_cq_sz[0x8]; 1075 u8 reserved_5[0xb]; 1076 u8 log_max_cq[0x5]; 1077 1078 u8 log_max_eq_sz[0x8]; 1079 u8 relaxed_ordering_write[1]; 1080 u8 reserved_6[0x1]; 1081 u8 log_max_mkey[0x6]; 1082 u8 reserved_7[0xb]; 1083 u8 fast_teardown[0x1]; 1084 u8 log_max_eq[0x4]; 1085 1086 u8 max_indirection[0x8]; 1087 u8 reserved_8[0x1]; 1088 u8 log_max_mrw_sz[0x7]; 1089 u8 force_teardown[0x1]; 1090 u8 reserved_9[0x1]; 1091 u8 log_max_bsf_list_size[0x6]; 1092 u8 reserved_10[0x2]; 1093 u8 log_max_klm_list_size[0x6]; 1094 1095 u8 reserved_11[0xa]; 1096 u8 log_max_ra_req_dc[0x6]; 1097 u8 reserved_12[0xa]; 1098 u8 log_max_ra_res_dc[0x6]; 1099 1100 u8 reserved_13[0xa]; 1101 u8 log_max_ra_req_qp[0x6]; 1102 u8 reserved_14[0xa]; 1103 u8 log_max_ra_res_qp[0x6]; 1104 1105 u8 pad_cap[0x1]; 1106 u8 cc_query_allowed[0x1]; 1107 u8 cc_modify_allowed[0x1]; 1108 u8 start_pad[0x1]; 1109 u8 cache_line_128byte[0x1]; 1110 u8 reserved_at_165[0xa]; 1111 u8 qcam_reg[0x1]; 1112 u8 gid_table_size[0x10]; 1113 1114 u8 out_of_seq_cnt[0x1]; 1115 u8 vport_counters[0x1]; 1116 u8 retransmission_q_counters[0x1]; 1117 u8 debug[0x1]; 1118 u8 modify_rq_counters_set_id[0x1]; 1119 u8 rq_delay_drop[0x1]; 1120 u8 max_qp_cnt[0xa]; 1121 u8 pkey_table_size[0x10]; 1122 1123 u8 vport_group_manager[0x1]; 1124 u8 vhca_group_manager[0x1]; 1125 u8 ib_virt[0x1]; 1126 u8 eth_virt[0x1]; 1127 u8 reserved_17[0x1]; 1128 u8 ets[0x1]; 1129 u8 nic_flow_table[0x1]; 1130 u8 eswitch_flow_table[0x1]; 1131 u8 reserved_18[0x1]; 1132 u8 mcam_reg[0x1]; 1133 u8 pcam_reg[0x1]; 1134 u8 local_ca_ack_delay[0x5]; 1135 u8 port_module_event[0x1]; 1136 u8 reserved_19[0x5]; 1137 u8 port_type[0x2]; 1138 u8 num_ports[0x8]; 1139 1140 u8 snapshot[0x1]; 1141 u8 reserved_20[0x2]; 1142 u8 log_max_msg[0x5]; 1143 u8 reserved_21[0x4]; 1144 u8 max_tc[0x4]; 1145 u8 temp_warn_event[0x1]; 1146 u8 dcbx[0x1]; 1147 u8 general_notification_event[0x1]; 1148 u8 reserved_at_1d3[0x2]; 1149 u8 fpga[0x1]; 1150 u8 rol_s[0x1]; 1151 u8 rol_g[0x1]; 1152 u8 reserved_23[0x1]; 1153 u8 wol_s[0x1]; 1154 u8 wol_g[0x1]; 1155 u8 wol_a[0x1]; 1156 u8 wol_b[0x1]; 1157 u8 wol_m[0x1]; 1158 u8 wol_u[0x1]; 1159 u8 wol_p[0x1]; 1160 1161 u8 stat_rate_support[0x10]; 1162 u8 reserved_24[0xc]; 1163 u8 cqe_version[0x4]; 1164 1165 u8 compact_address_vector[0x1]; 1166 u8 striding_rq[0x1]; 1167 u8 reserved_25[0x1]; 1168 u8 ipoib_enhanced_offloads[0x1]; 1169 u8 ipoib_ipoib_offloads[0x1]; 1170 u8 reserved_26[0x8]; 1171 u8 dc_connect_qp[0x1]; 1172 u8 dc_cnak_trace[0x1]; 1173 u8 drain_sigerr[0x1]; 1174 u8 cmdif_checksum[0x2]; 1175 u8 sigerr_cqe[0x1]; 1176 u8 reserved_27[0x1]; 1177 u8 wq_signature[0x1]; 1178 u8 sctr_data_cqe[0x1]; 1179 u8 reserved_28[0x1]; 1180 u8 sho[0x1]; 1181 u8 tph[0x1]; 1182 u8 rf[0x1]; 1183 u8 dct[0x1]; 1184 u8 qos[0x1]; 1185 u8 eth_net_offloads[0x1]; 1186 u8 roce[0x1]; 1187 u8 atomic[0x1]; 1188 u8 reserved_30[0x1]; 1189 1190 u8 cq_oi[0x1]; 1191 u8 cq_resize[0x1]; 1192 u8 cq_moderation[0x1]; 1193 u8 cq_period_mode_modify[0x1]; 1194 u8 cq_invalidate[0x1]; 1195 u8 reserved_at_225[0x1]; 1196 u8 cq_eq_remap[0x1]; 1197 u8 pg[0x1]; 1198 u8 block_lb_mc[0x1]; 1199 u8 exponential_backoff[0x1]; 1200 u8 scqe_break_moderation[0x1]; 1201 u8 cq_period_start_from_cqe[0x1]; 1202 u8 cd[0x1]; 1203 u8 atm[0x1]; 1204 u8 apm[0x1]; 1205 u8 imaicl[0x1]; 1206 u8 reserved_32[0x6]; 1207 u8 qkv[0x1]; 1208 u8 pkv[0x1]; 1209 u8 set_deth_sqpn[0x1]; 1210 u8 reserved_33[0x3]; 1211 u8 xrc[0x1]; 1212 u8 ud[0x1]; 1213 u8 uc[0x1]; 1214 u8 rc[0x1]; 1215 1216 u8 reserved_34[0xa]; 1217 u8 uar_sz[0x6]; 1218 u8 reserved_35[0x8]; 1219 u8 log_pg_sz[0x8]; 1220 1221 u8 bf[0x1]; 1222 u8 driver_version[0x1]; 1223 u8 pad_tx_eth_packet[0x1]; 1224 u8 reserved_36[0x8]; 1225 u8 log_bf_reg_size[0x5]; 1226 u8 reserved_37[0x10]; 1227 1228 u8 num_of_diagnostic_counters[0x10]; 1229 u8 max_wqe_sz_sq[0x10]; 1230 1231 u8 reserved_38[0x10]; 1232 u8 max_wqe_sz_rq[0x10]; 1233 1234 u8 reserved_39[0x10]; 1235 u8 max_wqe_sz_sq_dc[0x10]; 1236 1237 u8 reserved_40[0x7]; 1238 u8 max_qp_mcg[0x19]; 1239 1240 u8 reserved_41[0x18]; 1241 u8 log_max_mcg[0x8]; 1242 1243 u8 reserved_42[0x3]; 1244 u8 log_max_transport_domain[0x5]; 1245 u8 reserved_43[0x3]; 1246 u8 log_max_pd[0x5]; 1247 u8 reserved_44[0xb]; 1248 u8 log_max_xrcd[0x5]; 1249 1250 u8 nic_receive_steering_discard[0x1]; 1251 u8 reserved_45[0x7]; 1252 u8 log_max_flow_counter_bulk[0x8]; 1253 u8 max_flow_counter[0x10]; 1254 1255 u8 reserved_46[0x3]; 1256 u8 log_max_rq[0x5]; 1257 u8 reserved_47[0x3]; 1258 u8 log_max_sq[0x5]; 1259 u8 reserved_48[0x3]; 1260 u8 log_max_tir[0x5]; 1261 u8 reserved_49[0x3]; 1262 u8 log_max_tis[0x5]; 1263 1264 u8 basic_cyclic_rcv_wqe[0x1]; 1265 u8 reserved_50[0x2]; 1266 u8 log_max_rmp[0x5]; 1267 u8 reserved_51[0x3]; 1268 u8 log_max_rqt[0x5]; 1269 u8 reserved_52[0x3]; 1270 u8 log_max_rqt_size[0x5]; 1271 u8 reserved_53[0x3]; 1272 u8 log_max_tis_per_sq[0x5]; 1273 1274 u8 reserved_54[0x3]; 1275 u8 log_max_stride_sz_rq[0x5]; 1276 u8 reserved_55[0x3]; 1277 u8 log_min_stride_sz_rq[0x5]; 1278 u8 reserved_56[0x3]; 1279 u8 log_max_stride_sz_sq[0x5]; 1280 u8 reserved_57[0x3]; 1281 u8 log_min_stride_sz_sq[0x5]; 1282 1283 u8 reserved_58[0x1b]; 1284 u8 log_max_wq_sz[0x5]; 1285 1286 u8 nic_vport_change_event[0x1]; 1287 u8 disable_local_lb[0x1]; 1288 u8 reserved_59[0x9]; 1289 u8 log_max_vlan_list[0x5]; 1290 u8 reserved_60[0x3]; 1291 u8 log_max_current_mc_list[0x5]; 1292 u8 reserved_61[0x3]; 1293 u8 log_max_current_uc_list[0x5]; 1294 1295 u8 general_obj_types[0x40]; 1296 1297 u8 reserved_at_440[0x8]; 1298 u8 create_qp_start_hint[0x18]; 1299 1300 u8 reserved_at_460[0x3]; 1301 u8 log_max_uctx[0x5]; 1302 u8 reserved_at_468[0x3]; 1303 u8 log_max_umem[0x5]; 1304 u8 max_num_eqs[0x10]; 1305 1306 u8 reserved_at_480[0x1]; 1307 u8 tls_tx[0x1]; 1308 u8 reserved_at_482[0x1]; 1309 u8 log_max_l2_table[0x5]; 1310 u8 reserved_64[0x8]; 1311 u8 log_uar_page_sz[0x10]; 1312 1313 u8 reserved_65[0x20]; 1314 1315 u8 device_frequency_mhz[0x20]; 1316 1317 u8 device_frequency_khz[0x20]; 1318 1319 u8 reserved_66[0x80]; 1320 1321 u8 log_max_atomic_size_qp[0x8]; 1322 u8 reserved_67[0x10]; 1323 u8 log_max_atomic_size_dc[0x8]; 1324 1325 u8 reserved_at_5a0[0x13]; 1326 u8 log_max_dek[0x5]; 1327 u8 reserved_at_5b8[0x4]; 1328 u8 mini_cqe_resp_stride_index[0x1]; 1329 u8 cqe_128_always[0x1]; 1330 u8 cqe_compression_128b[0x1]; 1331 1332 u8 cqe_compression[0x1]; 1333 1334 u8 cqe_compression_timeout[0x10]; 1335 u8 cqe_compression_max_num[0x10]; 1336 1337 u8 reserved_69[0x220]; 1338 }; 1339 1340 enum mlx5_flow_destination_type { 1341 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1342 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1343 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1344 }; 1345 1346 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1347 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1348 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1349 u8 reserved_0[0x40]; 1350 }; 1351 1352 struct mlx5_ifc_fte_match_param_bits { 1353 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1354 1355 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1356 1357 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1358 1359 u8 reserved_0[0xa00]; 1360 }; 1361 1362 enum { 1363 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1364 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1365 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1366 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1367 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1368 }; 1369 1370 struct mlx5_ifc_rx_hash_field_select_bits { 1371 u8 l3_prot_type[0x1]; 1372 u8 l4_prot_type[0x1]; 1373 u8 selected_fields[0x1e]; 1374 }; 1375 1376 struct mlx5_ifc_tls_capabilities_bits { 1377 u8 tls_1_2_aes_gcm_128[0x1]; 1378 u8 tls_1_3_aes_gcm_128[0x1]; 1379 u8 tls_1_2_aes_gcm_256[0x1]; 1380 u8 tls_1_3_aes_gcm_256[0x1]; 1381 u8 reserved_at_4[0x1c]; 1382 1383 u8 reserved_at_20[0x7e0]; 1384 }; 1385 1386 enum { 1387 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1388 MLX5_WQ_TYPE_CYCLIC = 0x1, 1389 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1390 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1391 }; 1392 1393 enum rq_type { 1394 RQ_TYPE_NONE, 1395 RQ_TYPE_STRIDE, 1396 }; 1397 1398 enum { 1399 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1400 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1401 }; 1402 1403 struct mlx5_ifc_wq_bits { 1404 u8 wq_type[0x4]; 1405 u8 wq_signature[0x1]; 1406 u8 end_padding_mode[0x2]; 1407 u8 cd_slave[0x1]; 1408 u8 reserved_0[0x18]; 1409 1410 u8 hds_skip_first_sge[0x1]; 1411 u8 log2_hds_buf_size[0x3]; 1412 u8 reserved_1[0x7]; 1413 u8 page_offset[0x5]; 1414 u8 lwm[0x10]; 1415 1416 u8 reserved_2[0x8]; 1417 u8 pd[0x18]; 1418 1419 u8 reserved_3[0x8]; 1420 u8 uar_page[0x18]; 1421 1422 u8 dbr_addr[0x40]; 1423 1424 u8 hw_counter[0x20]; 1425 1426 u8 sw_counter[0x20]; 1427 1428 u8 reserved_4[0xc]; 1429 u8 log_wq_stride[0x4]; 1430 u8 reserved_5[0x3]; 1431 u8 log_wq_pg_sz[0x5]; 1432 u8 reserved_6[0x3]; 1433 u8 log_wq_sz[0x5]; 1434 1435 u8 reserved_7[0x15]; 1436 u8 single_wqe_log_num_of_strides[0x3]; 1437 u8 two_byte_shift_en[0x1]; 1438 u8 reserved_8[0x4]; 1439 u8 single_stride_log_num_of_bytes[0x3]; 1440 1441 u8 reserved_9[0x4c0]; 1442 1443 struct mlx5_ifc_cmd_pas_bits pas[0]; 1444 }; 1445 1446 struct mlx5_ifc_rq_num_bits { 1447 u8 reserved_0[0x8]; 1448 u8 rq_num[0x18]; 1449 }; 1450 1451 struct mlx5_ifc_mac_address_layout_bits { 1452 u8 reserved_0[0x10]; 1453 u8 mac_addr_47_32[0x10]; 1454 1455 u8 mac_addr_31_0[0x20]; 1456 }; 1457 1458 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1459 u8 reserved_0[0xa0]; 1460 1461 u8 min_time_between_cnps[0x20]; 1462 1463 u8 reserved_1[0x12]; 1464 u8 cnp_dscp[0x6]; 1465 u8 reserved_2[0x4]; 1466 u8 cnp_prio_mode[0x1]; 1467 u8 cnp_802p_prio[0x3]; 1468 1469 u8 reserved_3[0x720]; 1470 }; 1471 1472 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1473 u8 reserved_0[0x60]; 1474 1475 u8 reserved_1[0x4]; 1476 u8 clamp_tgt_rate[0x1]; 1477 u8 reserved_2[0x3]; 1478 u8 clamp_tgt_rate_after_time_inc[0x1]; 1479 u8 reserved_3[0x17]; 1480 1481 u8 reserved_4[0x20]; 1482 1483 u8 rpg_time_reset[0x20]; 1484 1485 u8 rpg_byte_reset[0x20]; 1486 1487 u8 rpg_threshold[0x20]; 1488 1489 u8 rpg_max_rate[0x20]; 1490 1491 u8 rpg_ai_rate[0x20]; 1492 1493 u8 rpg_hai_rate[0x20]; 1494 1495 u8 rpg_gd[0x20]; 1496 1497 u8 rpg_min_dec_fac[0x20]; 1498 1499 u8 rpg_min_rate[0x20]; 1500 1501 u8 reserved_5[0xe0]; 1502 1503 u8 rate_to_set_on_first_cnp[0x20]; 1504 1505 u8 dce_tcp_g[0x20]; 1506 1507 u8 dce_tcp_rtt[0x20]; 1508 1509 u8 rate_reduce_monitor_period[0x20]; 1510 1511 u8 reserved_6[0x20]; 1512 1513 u8 initial_alpha_value[0x20]; 1514 1515 u8 reserved_7[0x4a0]; 1516 }; 1517 1518 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1519 u8 reserved_0[0x80]; 1520 1521 u8 rppp_max_rps[0x20]; 1522 1523 u8 rpg_time_reset[0x20]; 1524 1525 u8 rpg_byte_reset[0x20]; 1526 1527 u8 rpg_threshold[0x20]; 1528 1529 u8 rpg_max_rate[0x20]; 1530 1531 u8 rpg_ai_rate[0x20]; 1532 1533 u8 rpg_hai_rate[0x20]; 1534 1535 u8 rpg_gd[0x20]; 1536 1537 u8 rpg_min_dec_fac[0x20]; 1538 1539 u8 rpg_min_rate[0x20]; 1540 1541 u8 reserved_1[0x640]; 1542 }; 1543 1544 enum { 1545 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1546 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1547 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1548 }; 1549 1550 struct mlx5_ifc_resize_field_select_bits { 1551 u8 resize_field_select[0x20]; 1552 }; 1553 1554 enum { 1555 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1556 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1557 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1558 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1559 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1560 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1561 }; 1562 1563 struct mlx5_ifc_modify_field_select_bits { 1564 u8 modify_field_select[0x20]; 1565 }; 1566 1567 struct mlx5_ifc_field_select_r_roce_np_bits { 1568 u8 field_select_r_roce_np[0x20]; 1569 }; 1570 1571 enum { 1572 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1573 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1574 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1575 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1576 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1577 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1578 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1579 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1580 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1581 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1582 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1583 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1584 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1585 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1586 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1587 }; 1588 1589 struct mlx5_ifc_field_select_r_roce_rp_bits { 1590 u8 field_select_r_roce_rp[0x20]; 1591 }; 1592 1593 enum { 1594 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1595 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1596 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1597 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1598 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1599 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1600 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1601 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1602 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1603 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1604 }; 1605 1606 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1607 u8 field_select_8021qaurp[0x20]; 1608 }; 1609 1610 struct mlx5_ifc_pptb_reg_bits { 1611 u8 reserved_at_0[0x2]; 1612 u8 mm[0x2]; 1613 u8 reserved_at_4[0x4]; 1614 u8 local_port[0x8]; 1615 u8 reserved_at_10[0x6]; 1616 u8 cm[0x1]; 1617 u8 um[0x1]; 1618 u8 pm[0x8]; 1619 1620 u8 prio_x_buff[0x20]; 1621 1622 u8 pm_msb[0x8]; 1623 u8 reserved_at_48[0x10]; 1624 u8 ctrl_buff[0x4]; 1625 u8 untagged_buff[0x4]; 1626 }; 1627 1628 struct mlx5_ifc_dcbx_app_reg_bits { 1629 u8 reserved_0[0x8]; 1630 u8 port_number[0x8]; 1631 u8 reserved_1[0x10]; 1632 1633 u8 reserved_2[0x1a]; 1634 u8 num_app_prio[0x6]; 1635 1636 u8 reserved_3[0x40]; 1637 1638 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1639 }; 1640 1641 struct mlx5_ifc_dcbx_param_reg_bits { 1642 u8 dcbx_cee_cap[0x1]; 1643 u8 dcbx_ieee_cap[0x1]; 1644 u8 dcbx_standby_cap[0x1]; 1645 u8 reserved_0[0x5]; 1646 u8 port_number[0x8]; 1647 u8 reserved_1[0xa]; 1648 u8 max_application_table_size[0x6]; 1649 1650 u8 reserved_2[0x15]; 1651 u8 version_oper[0x3]; 1652 u8 reserved_3[0x5]; 1653 u8 version_admin[0x3]; 1654 1655 u8 willing_admin[0x1]; 1656 u8 reserved_4[0x3]; 1657 u8 pfc_cap_oper[0x4]; 1658 u8 reserved_5[0x4]; 1659 u8 pfc_cap_admin[0x4]; 1660 u8 reserved_6[0x4]; 1661 u8 num_of_tc_oper[0x4]; 1662 u8 reserved_7[0x4]; 1663 u8 num_of_tc_admin[0x4]; 1664 1665 u8 remote_willing[0x1]; 1666 u8 reserved_8[0x3]; 1667 u8 remote_pfc_cap[0x4]; 1668 u8 reserved_9[0x14]; 1669 u8 remote_num_of_tc[0x4]; 1670 1671 u8 reserved_10[0x18]; 1672 u8 error[0x8]; 1673 1674 u8 reserved_11[0x160]; 1675 }; 1676 1677 struct mlx5_ifc_qhll_bits { 1678 u8 reserved_at_0[0x8]; 1679 u8 local_port[0x8]; 1680 u8 reserved_at_10[0x10]; 1681 1682 u8 reserved_at_20[0x1b]; 1683 u8 hll_time[0x5]; 1684 1685 u8 stall_en[0x1]; 1686 u8 reserved_at_41[0x1c]; 1687 u8 stall_cnt[0x3]; 1688 }; 1689 1690 struct mlx5_ifc_qetcr_reg_bits { 1691 u8 operation_type[0x2]; 1692 u8 cap_local_admin[0x1]; 1693 u8 cap_remote_admin[0x1]; 1694 u8 reserved_0[0x4]; 1695 u8 port_number[0x8]; 1696 u8 reserved_1[0x10]; 1697 1698 u8 reserved_2[0x20]; 1699 1700 u8 tc[8][0x40]; 1701 1702 u8 global_configuration[0x40]; 1703 }; 1704 1705 struct mlx5_ifc_nodnic_ring_config_reg_bits { 1706 u8 queue_address_63_32[0x20]; 1707 1708 u8 queue_address_31_12[0x14]; 1709 u8 reserved_0[0x6]; 1710 u8 log_size[0x6]; 1711 1712 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1713 1714 u8 reserved_1[0x8]; 1715 u8 queue_number[0x18]; 1716 1717 u8 q_key[0x20]; 1718 1719 u8 reserved_2[0x10]; 1720 u8 pkey_index[0x10]; 1721 1722 u8 reserved_3[0x40]; 1723 }; 1724 1725 struct mlx5_ifc_nodnic_cq_arming_word_bits { 1726 u8 reserved_0[0x8]; 1727 u8 cq_ci[0x10]; 1728 u8 reserved_1[0x8]; 1729 }; 1730 1731 enum { 1732 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1733 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1734 }; 1735 1736 enum { 1737 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1738 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1739 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1740 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1741 }; 1742 1743 struct mlx5_ifc_nodnic_event_word_bits { 1744 u8 driver_reset_needed[0x1]; 1745 u8 port_management_change_event[0x1]; 1746 u8 reserved_0[0x19]; 1747 u8 link_type[0x1]; 1748 u8 port_state[0x4]; 1749 }; 1750 1751 struct mlx5_ifc_nic_vport_change_event_bits { 1752 u8 reserved_0[0x10]; 1753 u8 vport_num[0x10]; 1754 1755 u8 reserved_1[0xc0]; 1756 }; 1757 1758 struct mlx5_ifc_pages_req_event_bits { 1759 u8 reserved_0[0x10]; 1760 u8 function_id[0x10]; 1761 1762 u8 num_pages[0x20]; 1763 1764 u8 reserved_1[0xa0]; 1765 }; 1766 1767 struct mlx5_ifc_cmd_inter_comp_event_bits { 1768 u8 command_completion_vector[0x20]; 1769 1770 u8 reserved_0[0xc0]; 1771 }; 1772 1773 struct mlx5_ifc_stall_vl_event_bits { 1774 u8 reserved_0[0x18]; 1775 u8 port_num[0x1]; 1776 u8 reserved_1[0x3]; 1777 u8 vl[0x4]; 1778 1779 u8 reserved_2[0xa0]; 1780 }; 1781 1782 struct mlx5_ifc_db_bf_congestion_event_bits { 1783 u8 event_subtype[0x8]; 1784 u8 reserved_0[0x8]; 1785 u8 congestion_level[0x8]; 1786 u8 reserved_1[0x8]; 1787 1788 u8 reserved_2[0xa0]; 1789 }; 1790 1791 struct mlx5_ifc_gpio_event_bits { 1792 u8 reserved_0[0x60]; 1793 1794 u8 gpio_event_hi[0x20]; 1795 1796 u8 gpio_event_lo[0x20]; 1797 1798 u8 reserved_1[0x40]; 1799 }; 1800 1801 struct mlx5_ifc_port_state_change_event_bits { 1802 u8 reserved_0[0x40]; 1803 1804 u8 port_num[0x4]; 1805 u8 reserved_1[0x1c]; 1806 1807 u8 reserved_2[0x80]; 1808 }; 1809 1810 struct mlx5_ifc_dropped_packet_logged_bits { 1811 u8 reserved_0[0xe0]; 1812 }; 1813 1814 enum { 1815 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1816 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1817 }; 1818 1819 struct mlx5_ifc_cq_error_bits { 1820 u8 reserved_0[0x8]; 1821 u8 cqn[0x18]; 1822 1823 u8 reserved_1[0x20]; 1824 1825 u8 reserved_2[0x18]; 1826 u8 syndrome[0x8]; 1827 1828 u8 reserved_3[0x80]; 1829 }; 1830 1831 struct mlx5_ifc_rdma_page_fault_event_bits { 1832 u8 bytes_commited[0x20]; 1833 1834 u8 r_key[0x20]; 1835 1836 u8 reserved_0[0x10]; 1837 u8 packet_len[0x10]; 1838 1839 u8 rdma_op_len[0x20]; 1840 1841 u8 rdma_va[0x40]; 1842 1843 u8 reserved_1[0x5]; 1844 u8 rdma[0x1]; 1845 u8 write[0x1]; 1846 u8 requestor[0x1]; 1847 u8 qp_number[0x18]; 1848 }; 1849 1850 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1851 u8 bytes_committed[0x20]; 1852 1853 u8 reserved_0[0x10]; 1854 u8 wqe_index[0x10]; 1855 1856 u8 reserved_1[0x10]; 1857 u8 len[0x10]; 1858 1859 u8 reserved_2[0x60]; 1860 1861 u8 reserved_3[0x5]; 1862 u8 rdma[0x1]; 1863 u8 write_read[0x1]; 1864 u8 requestor[0x1]; 1865 u8 qpn[0x18]; 1866 }; 1867 1868 enum { 1869 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1870 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1871 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1872 }; 1873 1874 struct mlx5_ifc_qp_events_bits { 1875 u8 reserved_0[0xa0]; 1876 1877 u8 type[0x8]; 1878 u8 reserved_1[0x18]; 1879 1880 u8 reserved_2[0x8]; 1881 u8 qpn_rqn_sqn[0x18]; 1882 }; 1883 1884 struct mlx5_ifc_dct_events_bits { 1885 u8 reserved_0[0xc0]; 1886 1887 u8 reserved_1[0x8]; 1888 u8 dct_number[0x18]; 1889 }; 1890 1891 struct mlx5_ifc_comp_event_bits { 1892 u8 reserved_0[0xc0]; 1893 1894 u8 reserved_1[0x8]; 1895 u8 cq_number[0x18]; 1896 }; 1897 1898 struct mlx5_ifc_fw_version_bits { 1899 u8 major[0x10]; 1900 u8 reserved_0[0x10]; 1901 1902 u8 minor[0x10]; 1903 u8 subminor[0x10]; 1904 1905 u8 second[0x8]; 1906 u8 minute[0x8]; 1907 u8 hour[0x8]; 1908 u8 reserved_1[0x8]; 1909 1910 u8 year[0x10]; 1911 u8 month[0x8]; 1912 u8 day[0x8]; 1913 }; 1914 1915 enum { 1916 MLX5_QPC_STATE_RST = 0x0, 1917 MLX5_QPC_STATE_INIT = 0x1, 1918 MLX5_QPC_STATE_RTR = 0x2, 1919 MLX5_QPC_STATE_RTS = 0x3, 1920 MLX5_QPC_STATE_SQER = 0x4, 1921 MLX5_QPC_STATE_SQD = 0x5, 1922 MLX5_QPC_STATE_ERR = 0x6, 1923 MLX5_QPC_STATE_SUSPENDED = 0x9, 1924 }; 1925 1926 enum { 1927 MLX5_QPC_ST_RC = 0x0, 1928 MLX5_QPC_ST_UC = 0x1, 1929 MLX5_QPC_ST_UD = 0x2, 1930 MLX5_QPC_ST_XRC = 0x3, 1931 MLX5_QPC_ST_DCI = 0x5, 1932 MLX5_QPC_ST_QP0 = 0x7, 1933 MLX5_QPC_ST_QP1 = 0x8, 1934 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1935 MLX5_QPC_ST_REG_UMR = 0xc, 1936 }; 1937 1938 enum { 1939 MLX5_QP_PM_ARMED = 0x0, 1940 MLX5_QP_PM_REARM = 0x1, 1941 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1942 MLX5_QP_PM_MIGRATED = 0x3, 1943 }; 1944 1945 enum { 1946 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1947 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1948 }; 1949 1950 enum { 1951 MLX5_QPC_MTU_256_BYTES = 0x1, 1952 MLX5_QPC_MTU_512_BYTES = 0x2, 1953 MLX5_QPC_MTU_1K_BYTES = 0x3, 1954 MLX5_QPC_MTU_2K_BYTES = 0x4, 1955 MLX5_QPC_MTU_4K_BYTES = 0x5, 1956 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1957 }; 1958 1959 enum { 1960 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1961 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1962 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1963 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1964 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1965 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1966 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1967 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1968 }; 1969 1970 enum { 1971 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1972 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1973 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1974 }; 1975 1976 enum { 1977 MLX5_QPC_CS_RES_DISABLE = 0x0, 1978 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1979 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1980 }; 1981 1982 struct mlx5_ifc_qpc_bits { 1983 u8 state[0x4]; 1984 u8 lag_tx_port_affinity[0x4]; 1985 u8 st[0x8]; 1986 u8 reserved_1[0x3]; 1987 u8 pm_state[0x2]; 1988 u8 reserved_2[0x7]; 1989 u8 end_padding_mode[0x2]; 1990 u8 reserved_3[0x2]; 1991 1992 u8 wq_signature[0x1]; 1993 u8 block_lb_mc[0x1]; 1994 u8 atomic_like_write_en[0x1]; 1995 u8 latency_sensitive[0x1]; 1996 u8 reserved_4[0x1]; 1997 u8 drain_sigerr[0x1]; 1998 u8 reserved_5[0x2]; 1999 u8 pd[0x18]; 2000 2001 u8 mtu[0x3]; 2002 u8 log_msg_max[0x5]; 2003 u8 reserved_6[0x1]; 2004 u8 log_rq_size[0x4]; 2005 u8 log_rq_stride[0x3]; 2006 u8 no_sq[0x1]; 2007 u8 log_sq_size[0x4]; 2008 u8 reserved_7[0x6]; 2009 u8 rlky[0x1]; 2010 u8 ulp_stateless_offload_mode[0x4]; 2011 2012 u8 counter_set_id[0x8]; 2013 u8 uar_page[0x18]; 2014 2015 u8 reserved_8[0x8]; 2016 u8 user_index[0x18]; 2017 2018 u8 reserved_9[0x3]; 2019 u8 log_page_size[0x5]; 2020 u8 remote_qpn[0x18]; 2021 2022 struct mlx5_ifc_ads_bits primary_address_path; 2023 2024 struct mlx5_ifc_ads_bits secondary_address_path; 2025 2026 u8 log_ack_req_freq[0x4]; 2027 u8 reserved_10[0x4]; 2028 u8 log_sra_max[0x3]; 2029 u8 reserved_11[0x2]; 2030 u8 retry_count[0x3]; 2031 u8 rnr_retry[0x3]; 2032 u8 reserved_12[0x1]; 2033 u8 fre[0x1]; 2034 u8 cur_rnr_retry[0x3]; 2035 u8 cur_retry_count[0x3]; 2036 u8 reserved_13[0x5]; 2037 2038 u8 reserved_14[0x20]; 2039 2040 u8 reserved_15[0x8]; 2041 u8 next_send_psn[0x18]; 2042 2043 u8 reserved_16[0x8]; 2044 u8 cqn_snd[0x18]; 2045 2046 u8 reserved_at_400[0x8]; 2047 2048 u8 deth_sqpn[0x18]; 2049 u8 reserved_17[0x20]; 2050 2051 u8 reserved_18[0x8]; 2052 u8 last_acked_psn[0x18]; 2053 2054 u8 reserved_19[0x8]; 2055 u8 ssn[0x18]; 2056 2057 u8 reserved_20[0x8]; 2058 u8 log_rra_max[0x3]; 2059 u8 reserved_21[0x1]; 2060 u8 atomic_mode[0x4]; 2061 u8 rre[0x1]; 2062 u8 rwe[0x1]; 2063 u8 rae[0x1]; 2064 u8 reserved_22[0x1]; 2065 u8 page_offset[0x6]; 2066 u8 reserved_23[0x3]; 2067 u8 cd_slave_receive[0x1]; 2068 u8 cd_slave_send[0x1]; 2069 u8 cd_master[0x1]; 2070 2071 u8 reserved_24[0x3]; 2072 u8 min_rnr_nak[0x5]; 2073 u8 next_rcv_psn[0x18]; 2074 2075 u8 reserved_25[0x8]; 2076 u8 xrcd[0x18]; 2077 2078 u8 reserved_26[0x8]; 2079 u8 cqn_rcv[0x18]; 2080 2081 u8 dbr_addr[0x40]; 2082 2083 u8 q_key[0x20]; 2084 2085 u8 reserved_27[0x5]; 2086 u8 rq_type[0x3]; 2087 u8 srqn_rmpn[0x18]; 2088 2089 u8 reserved_28[0x8]; 2090 u8 rmsn[0x18]; 2091 2092 u8 hw_sq_wqebb_counter[0x10]; 2093 u8 sw_sq_wqebb_counter[0x10]; 2094 2095 u8 hw_rq_counter[0x20]; 2096 2097 u8 sw_rq_counter[0x20]; 2098 2099 u8 reserved_29[0x20]; 2100 2101 u8 reserved_30[0xf]; 2102 u8 cgs[0x1]; 2103 u8 cs_req[0x8]; 2104 u8 cs_res[0x8]; 2105 2106 u8 dc_access_key[0x40]; 2107 2108 u8 rdma_active[0x1]; 2109 u8 comm_est[0x1]; 2110 u8 suspended[0x1]; 2111 u8 reserved_31[0x5]; 2112 u8 send_msg_psn[0x18]; 2113 2114 u8 reserved_32[0x8]; 2115 u8 rcv_msg_psn[0x18]; 2116 2117 u8 rdma_va[0x40]; 2118 2119 u8 rdma_key[0x20]; 2120 2121 u8 reserved_33[0x20]; 2122 }; 2123 2124 struct mlx5_ifc_roce_addr_layout_bits { 2125 u8 source_l3_address[16][0x8]; 2126 2127 u8 reserved_0[0x3]; 2128 u8 vlan_valid[0x1]; 2129 u8 vlan_id[0xc]; 2130 u8 source_mac_47_32[0x10]; 2131 2132 u8 source_mac_31_0[0x20]; 2133 2134 u8 reserved_1[0x14]; 2135 u8 roce_l3_type[0x4]; 2136 u8 roce_version[0x8]; 2137 2138 u8 reserved_2[0x20]; 2139 }; 2140 2141 struct mlx5_ifc_rdbc_bits { 2142 u8 reserved_0[0x1c]; 2143 u8 type[0x4]; 2144 2145 u8 reserved_1[0x20]; 2146 2147 u8 reserved_2[0x8]; 2148 u8 psn[0x18]; 2149 2150 u8 rkey[0x20]; 2151 2152 u8 address[0x40]; 2153 2154 u8 byte_count[0x20]; 2155 2156 u8 reserved_3[0x20]; 2157 2158 u8 atomic_resp[32][0x8]; 2159 }; 2160 2161 enum { 2162 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2163 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2164 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2165 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2166 }; 2167 2168 struct mlx5_ifc_flow_context_bits { 2169 u8 reserved_0[0x20]; 2170 2171 u8 group_id[0x20]; 2172 2173 u8 reserved_1[0x8]; 2174 u8 flow_tag[0x18]; 2175 2176 u8 reserved_2[0x10]; 2177 u8 action[0x10]; 2178 2179 u8 reserved_3[0x8]; 2180 u8 destination_list_size[0x18]; 2181 2182 u8 reserved_4[0x8]; 2183 u8 flow_counter_list_size[0x18]; 2184 2185 u8 reserved_5[0x140]; 2186 2187 struct mlx5_ifc_fte_match_param_bits match_value; 2188 2189 u8 reserved_6[0x600]; 2190 2191 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2192 }; 2193 2194 enum { 2195 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2196 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2197 }; 2198 2199 struct mlx5_ifc_xrc_srqc_bits { 2200 u8 state[0x4]; 2201 u8 log_xrc_srq_size[0x4]; 2202 u8 reserved_0[0x18]; 2203 2204 u8 wq_signature[0x1]; 2205 u8 cont_srq[0x1]; 2206 u8 reserved_1[0x1]; 2207 u8 rlky[0x1]; 2208 u8 basic_cyclic_rcv_wqe[0x1]; 2209 u8 log_rq_stride[0x3]; 2210 u8 xrcd[0x18]; 2211 2212 u8 page_offset[0x6]; 2213 u8 reserved_2[0x2]; 2214 u8 cqn[0x18]; 2215 2216 u8 reserved_3[0x20]; 2217 2218 u8 reserved_4[0x2]; 2219 u8 log_page_size[0x6]; 2220 u8 user_index[0x18]; 2221 2222 u8 reserved_5[0x20]; 2223 2224 u8 reserved_6[0x8]; 2225 u8 pd[0x18]; 2226 2227 u8 lwm[0x10]; 2228 u8 wqe_cnt[0x10]; 2229 2230 u8 reserved_7[0x40]; 2231 2232 u8 db_record_addr_h[0x20]; 2233 2234 u8 db_record_addr_l[0x1e]; 2235 u8 reserved_8[0x2]; 2236 2237 u8 reserved_9[0x80]; 2238 }; 2239 2240 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2241 u8 counter_error_queues[0x20]; 2242 2243 u8 total_error_queues[0x20]; 2244 2245 u8 send_queue_priority_update_flow[0x20]; 2246 2247 u8 reserved_at_60[0x20]; 2248 2249 u8 nic_receive_steering_discard[0x40]; 2250 2251 u8 receive_discard_vport_down[0x40]; 2252 2253 u8 transmit_discard_vport_down[0x40]; 2254 2255 u8 reserved_at_140[0xec0]; 2256 }; 2257 2258 struct mlx5_ifc_traffic_counter_bits { 2259 u8 packets[0x40]; 2260 2261 u8 octets[0x40]; 2262 }; 2263 2264 struct mlx5_ifc_tisc_bits { 2265 u8 strict_lag_tx_port_affinity[0x1]; 2266 u8 tls_en[0x1]; 2267 u8 reserved_at_2[0x2]; 2268 u8 lag_tx_port_affinity[0x04]; 2269 2270 u8 reserved_at_8[0x4]; 2271 u8 prio[0x4]; 2272 u8 reserved_1[0x10]; 2273 2274 u8 reserved_2[0x100]; 2275 2276 u8 reserved_3[0x8]; 2277 u8 transport_domain[0x18]; 2278 2279 u8 reserved_4[0x8]; 2280 u8 underlay_qpn[0x18]; 2281 2282 u8 reserved_5[0x8]; 2283 u8 pd[0x18]; 2284 2285 u8 reserved_6[0x380]; 2286 }; 2287 2288 enum { 2289 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2290 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2291 }; 2292 2293 enum { 2294 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2295 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2296 }; 2297 2298 enum { 2299 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2300 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2301 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2302 }; 2303 2304 enum { 2305 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2306 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2307 }; 2308 2309 struct mlx5_ifc_tirc_bits { 2310 u8 reserved_0[0x20]; 2311 2312 u8 disp_type[0x4]; 2313 u8 tls_en[0x1]; 2314 u8 reserved_at_25[0x1b]; 2315 2316 u8 reserved_2[0x40]; 2317 2318 u8 reserved_3[0x4]; 2319 u8 lro_timeout_period_usecs[0x10]; 2320 u8 lro_enable_mask[0x4]; 2321 u8 lro_max_msg_sz[0x8]; 2322 2323 u8 reserved_4[0x40]; 2324 2325 u8 reserved_5[0x8]; 2326 u8 inline_rqn[0x18]; 2327 2328 u8 rx_hash_symmetric[0x1]; 2329 u8 reserved_6[0x1]; 2330 u8 tunneled_offload_en[0x1]; 2331 u8 reserved_7[0x5]; 2332 u8 indirect_table[0x18]; 2333 2334 u8 rx_hash_fn[0x4]; 2335 u8 reserved_8[0x2]; 2336 u8 self_lb_en[0x2]; 2337 u8 transport_domain[0x18]; 2338 2339 u8 rx_hash_toeplitz_key[10][0x20]; 2340 2341 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2342 2343 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2344 2345 u8 reserved_9[0x4c0]; 2346 }; 2347 2348 enum { 2349 MLX5_SRQC_STATE_GOOD = 0x0, 2350 MLX5_SRQC_STATE_ERROR = 0x1, 2351 }; 2352 2353 struct mlx5_ifc_srqc_bits { 2354 u8 state[0x4]; 2355 u8 log_srq_size[0x4]; 2356 u8 reserved_0[0x18]; 2357 2358 u8 wq_signature[0x1]; 2359 u8 cont_srq[0x1]; 2360 u8 reserved_1[0x1]; 2361 u8 rlky[0x1]; 2362 u8 reserved_2[0x1]; 2363 u8 log_rq_stride[0x3]; 2364 u8 xrcd[0x18]; 2365 2366 u8 page_offset[0x6]; 2367 u8 reserved_3[0x2]; 2368 u8 cqn[0x18]; 2369 2370 u8 reserved_4[0x20]; 2371 2372 u8 reserved_5[0x2]; 2373 u8 log_page_size[0x6]; 2374 u8 reserved_6[0x18]; 2375 2376 u8 reserved_7[0x20]; 2377 2378 u8 reserved_8[0x8]; 2379 u8 pd[0x18]; 2380 2381 u8 lwm[0x10]; 2382 u8 wqe_cnt[0x10]; 2383 2384 u8 reserved_9[0x40]; 2385 2386 u8 dbr_addr[0x40]; 2387 2388 u8 reserved_10[0x80]; 2389 }; 2390 2391 enum { 2392 MLX5_SQC_STATE_RST = 0x0, 2393 MLX5_SQC_STATE_RDY = 0x1, 2394 MLX5_SQC_STATE_ERR = 0x3, 2395 }; 2396 2397 struct mlx5_ifc_sqc_bits { 2398 u8 rlkey[0x1]; 2399 u8 cd_master[0x1]; 2400 u8 fre[0x1]; 2401 u8 flush_in_error_en[0x1]; 2402 u8 allow_multi_pkt_send_wqe[0x1]; 2403 u8 min_wqe_inline_mode[0x3]; 2404 u8 state[0x4]; 2405 u8 reg_umr[0x1]; 2406 u8 allow_swp[0x1]; 2407 u8 reserved_0[0x12]; 2408 2409 u8 reserved_1[0x8]; 2410 u8 user_index[0x18]; 2411 2412 u8 reserved_2[0x8]; 2413 u8 cqn[0x18]; 2414 2415 u8 reserved_3[0x80]; 2416 2417 u8 qos_para_vport_number[0x10]; 2418 u8 packet_pacing_rate_limit_index[0x10]; 2419 2420 u8 tis_lst_sz[0x10]; 2421 u8 reserved_4[0x10]; 2422 2423 u8 reserved_5[0x40]; 2424 2425 u8 reserved_6[0x8]; 2426 u8 tis_num_0[0x18]; 2427 2428 struct mlx5_ifc_wq_bits wq; 2429 }; 2430 2431 enum { 2432 MLX5_TSAR_TYPE_DWRR = 0, 2433 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2434 MLX5_TSAR_TYPE_ETS = 2 2435 }; 2436 2437 struct mlx5_ifc_tsar_element_attributes_bits { 2438 u8 reserved_0[0x8]; 2439 u8 tsar_type[0x8]; 2440 u8 reserved_1[0x10]; 2441 }; 2442 2443 struct mlx5_ifc_vport_element_attributes_bits { 2444 u8 reserved_0[0x10]; 2445 u8 vport_number[0x10]; 2446 }; 2447 2448 struct mlx5_ifc_vport_tc_element_attributes_bits { 2449 u8 traffic_class[0x10]; 2450 u8 vport_number[0x10]; 2451 }; 2452 2453 struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2454 u8 reserved_0[0x0C]; 2455 u8 traffic_class[0x04]; 2456 u8 qos_para_vport_number[0x10]; 2457 }; 2458 2459 enum { 2460 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2461 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2462 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2463 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2464 }; 2465 2466 struct mlx5_ifc_scheduling_context_bits { 2467 u8 element_type[0x8]; 2468 u8 reserved_at_8[0x18]; 2469 2470 u8 element_attributes[0x20]; 2471 2472 u8 parent_element_id[0x20]; 2473 2474 u8 reserved_at_60[0x40]; 2475 2476 u8 bw_share[0x20]; 2477 2478 u8 max_average_bw[0x20]; 2479 2480 u8 reserved_at_e0[0x120]; 2481 }; 2482 2483 struct mlx5_ifc_rqtc_bits { 2484 u8 reserved_0[0xa0]; 2485 2486 u8 reserved_1[0x10]; 2487 u8 rqt_max_size[0x10]; 2488 2489 u8 reserved_2[0x10]; 2490 u8 rqt_actual_size[0x10]; 2491 2492 u8 reserved_3[0x6a0]; 2493 2494 struct mlx5_ifc_rq_num_bits rq_num[0]; 2495 }; 2496 2497 enum { 2498 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2499 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2500 }; 2501 2502 enum { 2503 MLX5_RQC_STATE_RST = 0x0, 2504 MLX5_RQC_STATE_RDY = 0x1, 2505 MLX5_RQC_STATE_ERR = 0x3, 2506 }; 2507 2508 enum { 2509 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2510 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2511 }; 2512 2513 struct mlx5_ifc_rqc_bits { 2514 u8 rlkey[0x1]; 2515 u8 delay_drop_en[0x1]; 2516 u8 scatter_fcs[0x1]; 2517 u8 vlan_strip_disable[0x1]; 2518 u8 mem_rq_type[0x4]; 2519 u8 state[0x4]; 2520 u8 reserved_1[0x1]; 2521 u8 flush_in_error_en[0x1]; 2522 u8 reserved_2[0x12]; 2523 2524 u8 reserved_3[0x8]; 2525 u8 user_index[0x18]; 2526 2527 u8 reserved_4[0x8]; 2528 u8 cqn[0x18]; 2529 2530 u8 counter_set_id[0x8]; 2531 u8 reserved_5[0x18]; 2532 2533 u8 reserved_6[0x8]; 2534 u8 rmpn[0x18]; 2535 2536 u8 reserved_7[0xe0]; 2537 2538 struct mlx5_ifc_wq_bits wq; 2539 }; 2540 2541 enum { 2542 MLX5_RMPC_STATE_RDY = 0x1, 2543 MLX5_RMPC_STATE_ERR = 0x3, 2544 }; 2545 2546 struct mlx5_ifc_rmpc_bits { 2547 u8 reserved_0[0x8]; 2548 u8 state[0x4]; 2549 u8 reserved_1[0x14]; 2550 2551 u8 basic_cyclic_rcv_wqe[0x1]; 2552 u8 reserved_2[0x1f]; 2553 2554 u8 reserved_3[0x140]; 2555 2556 struct mlx5_ifc_wq_bits wq; 2557 }; 2558 2559 enum { 2560 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2561 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2562 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2563 }; 2564 2565 struct mlx5_ifc_nic_vport_context_bits { 2566 u8 reserved_0[0x5]; 2567 u8 min_wqe_inline_mode[0x3]; 2568 u8 reserved_1[0x15]; 2569 u8 disable_mc_local_lb[0x1]; 2570 u8 disable_uc_local_lb[0x1]; 2571 u8 roce_en[0x1]; 2572 2573 u8 arm_change_event[0x1]; 2574 u8 reserved_2[0x1a]; 2575 u8 event_on_mtu[0x1]; 2576 u8 event_on_promisc_change[0x1]; 2577 u8 event_on_vlan_change[0x1]; 2578 u8 event_on_mc_address_change[0x1]; 2579 u8 event_on_uc_address_change[0x1]; 2580 2581 u8 reserved_3[0xe0]; 2582 2583 u8 reserved_4[0x10]; 2584 u8 mtu[0x10]; 2585 2586 u8 system_image_guid[0x40]; 2587 2588 u8 port_guid[0x40]; 2589 2590 u8 node_guid[0x40]; 2591 2592 u8 reserved_5[0x140]; 2593 2594 u8 qkey_violation_counter[0x10]; 2595 u8 reserved_6[0x10]; 2596 2597 u8 reserved_7[0x420]; 2598 2599 u8 promisc_uc[0x1]; 2600 u8 promisc_mc[0x1]; 2601 u8 promisc_all[0x1]; 2602 u8 reserved_8[0x2]; 2603 u8 allowed_list_type[0x3]; 2604 u8 reserved_9[0xc]; 2605 u8 allowed_list_size[0xc]; 2606 2607 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2608 2609 u8 reserved_10[0x20]; 2610 2611 u8 current_uc_mac_address[0][0x40]; 2612 }; 2613 2614 enum { 2615 MLX5_ACCESS_MODE_PA = 0x0, 2616 MLX5_ACCESS_MODE_MTT = 0x1, 2617 MLX5_ACCESS_MODE_KLM = 0x2, 2618 }; 2619 2620 struct mlx5_ifc_mkc_bits { 2621 u8 reserved_at_0[0x1]; 2622 u8 free[0x1]; 2623 u8 reserved_at_2[0x1]; 2624 u8 access_mode_4_2[0x3]; 2625 u8 reserved_at_6[0x7]; 2626 u8 relaxed_ordering_write[0x1]; 2627 u8 reserved_at_e[0x1]; 2628 u8 small_fence_on_rdma_read_response[0x1]; 2629 u8 umr_en[0x1]; 2630 u8 a[0x1]; 2631 u8 rw[0x1]; 2632 u8 rr[0x1]; 2633 u8 lw[0x1]; 2634 u8 lr[0x1]; 2635 u8 access_mode[0x2]; 2636 u8 reserved_2[0x8]; 2637 2638 u8 qpn[0x18]; 2639 u8 mkey_7_0[0x8]; 2640 2641 u8 reserved_3[0x20]; 2642 2643 u8 length64[0x1]; 2644 u8 bsf_en[0x1]; 2645 u8 sync_umr[0x1]; 2646 u8 reserved_4[0x2]; 2647 u8 expected_sigerr_count[0x1]; 2648 u8 reserved_5[0x1]; 2649 u8 en_rinval[0x1]; 2650 u8 pd[0x18]; 2651 2652 u8 start_addr[0x40]; 2653 2654 u8 len[0x40]; 2655 2656 u8 bsf_octword_size[0x20]; 2657 2658 u8 reserved_6[0x80]; 2659 2660 u8 translations_octword_size[0x20]; 2661 2662 u8 reserved_7[0x1b]; 2663 u8 log_page_size[0x5]; 2664 2665 u8 reserved_8[0x20]; 2666 }; 2667 2668 struct mlx5_ifc_pkey_bits { 2669 u8 reserved_0[0x10]; 2670 u8 pkey[0x10]; 2671 }; 2672 2673 struct mlx5_ifc_array128_auto_bits { 2674 u8 array128_auto[16][0x8]; 2675 }; 2676 2677 enum { 2678 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2679 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2680 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2681 }; 2682 2683 enum { 2684 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2685 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2686 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2687 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2688 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2689 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2690 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2691 }; 2692 2693 enum { 2694 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2695 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2696 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2697 }; 2698 2699 enum { 2700 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2701 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2702 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2703 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2704 }; 2705 2706 enum { 2707 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2708 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2709 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2710 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2711 }; 2712 2713 struct mlx5_ifc_hca_vport_context_bits { 2714 u8 field_select[0x20]; 2715 2716 u8 reserved_0[0xe0]; 2717 2718 u8 sm_virt_aware[0x1]; 2719 u8 has_smi[0x1]; 2720 u8 has_raw[0x1]; 2721 u8 grh_required[0x1]; 2722 u8 reserved_1[0x1]; 2723 u8 min_wqe_inline_mode[0x3]; 2724 u8 reserved_2[0x8]; 2725 u8 port_physical_state[0x4]; 2726 u8 vport_state_policy[0x4]; 2727 u8 port_state[0x4]; 2728 u8 vport_state[0x4]; 2729 2730 u8 reserved_3[0x20]; 2731 2732 u8 system_image_guid[0x40]; 2733 2734 u8 port_guid[0x40]; 2735 2736 u8 node_guid[0x40]; 2737 2738 u8 cap_mask1[0x20]; 2739 2740 u8 cap_mask1_field_select[0x20]; 2741 2742 u8 cap_mask2[0x20]; 2743 2744 u8 cap_mask2_field_select[0x20]; 2745 2746 u8 reserved_4[0x80]; 2747 2748 u8 lid[0x10]; 2749 u8 reserved_5[0x4]; 2750 u8 init_type_reply[0x4]; 2751 u8 lmc[0x3]; 2752 u8 subnet_timeout[0x5]; 2753 2754 u8 sm_lid[0x10]; 2755 u8 sm_sl[0x4]; 2756 u8 reserved_6[0xc]; 2757 2758 u8 qkey_violation_counter[0x10]; 2759 u8 pkey_violation_counter[0x10]; 2760 2761 u8 reserved_7[0xca0]; 2762 }; 2763 2764 union mlx5_ifc_hca_cap_union_bits { 2765 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2766 struct mlx5_ifc_odp_cap_bits odp_cap; 2767 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2768 struct mlx5_ifc_roce_cap_bits roce_cap; 2769 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2770 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2771 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2772 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2773 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2774 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2775 struct mlx5_ifc_qos_cap_bits qos_cap; 2776 struct mlx5_ifc_tls_capabilities_bits tls_capabilities; 2777 u8 reserved_0[0x8000]; 2778 }; 2779 2780 enum { 2781 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 2782 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 2783 }; 2784 2785 struct mlx5_ifc_flow_table_context_bits { 2786 u8 encap_en[0x1]; 2787 u8 decap_en[0x1]; 2788 u8 reserved_at_2[0x2]; 2789 u8 table_miss_action[0x4]; 2790 u8 level[0x8]; 2791 u8 reserved_at_10[0x8]; 2792 u8 log_size[0x8]; 2793 2794 u8 reserved_at_20[0x8]; 2795 u8 table_miss_id[0x18]; 2796 2797 u8 reserved_at_40[0x8]; 2798 u8 lag_master_next_table_id[0x18]; 2799 2800 u8 reserved_at_60[0xe0]; 2801 }; 2802 2803 struct mlx5_ifc_esw_vport_context_bits { 2804 u8 reserved_0[0x3]; 2805 u8 vport_svlan_strip[0x1]; 2806 u8 vport_cvlan_strip[0x1]; 2807 u8 vport_svlan_insert[0x1]; 2808 u8 vport_cvlan_insert[0x2]; 2809 u8 reserved_1[0x18]; 2810 2811 u8 reserved_2[0x20]; 2812 2813 u8 svlan_cfi[0x1]; 2814 u8 svlan_pcp[0x3]; 2815 u8 svlan_id[0xc]; 2816 u8 cvlan_cfi[0x1]; 2817 u8 cvlan_pcp[0x3]; 2818 u8 cvlan_id[0xc]; 2819 2820 u8 reserved_3[0x7a0]; 2821 }; 2822 2823 enum { 2824 MLX5_EQC_STATUS_OK = 0x0, 2825 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2826 }; 2827 2828 enum { 2829 MLX5_EQ_STATE_ARMED = 0x9, 2830 MLX5_EQ_STATE_FIRED = 0xa, 2831 }; 2832 2833 struct mlx5_ifc_eqc_bits { 2834 u8 status[0x4]; 2835 u8 reserved_0[0x9]; 2836 u8 ec[0x1]; 2837 u8 oi[0x1]; 2838 u8 reserved_1[0x5]; 2839 u8 st[0x4]; 2840 u8 reserved_2[0x8]; 2841 2842 u8 reserved_3[0x20]; 2843 2844 u8 reserved_4[0x14]; 2845 u8 page_offset[0x6]; 2846 u8 reserved_5[0x6]; 2847 2848 u8 reserved_6[0x3]; 2849 u8 log_eq_size[0x5]; 2850 u8 uar_page[0x18]; 2851 2852 u8 reserved_7[0x20]; 2853 2854 u8 reserved_8[0x18]; 2855 u8 intr[0x8]; 2856 2857 u8 reserved_9[0x3]; 2858 u8 log_page_size[0x5]; 2859 u8 reserved_10[0x18]; 2860 2861 u8 reserved_11[0x60]; 2862 2863 u8 reserved_12[0x8]; 2864 u8 consumer_counter[0x18]; 2865 2866 u8 reserved_13[0x8]; 2867 u8 producer_counter[0x18]; 2868 2869 u8 reserved_14[0x80]; 2870 }; 2871 2872 enum { 2873 MLX5_DCTC_STATE_ACTIVE = 0x0, 2874 MLX5_DCTC_STATE_DRAINING = 0x1, 2875 MLX5_DCTC_STATE_DRAINED = 0x2, 2876 }; 2877 2878 enum { 2879 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2880 MLX5_DCTC_CS_RES_NA = 0x1, 2881 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2882 }; 2883 2884 enum { 2885 MLX5_DCTC_MTU_256_BYTES = 0x1, 2886 MLX5_DCTC_MTU_512_BYTES = 0x2, 2887 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2888 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2889 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2890 }; 2891 2892 struct mlx5_ifc_dctc_bits { 2893 u8 reserved_0[0x4]; 2894 u8 state[0x4]; 2895 u8 reserved_1[0x18]; 2896 2897 u8 reserved_2[0x8]; 2898 u8 user_index[0x18]; 2899 2900 u8 reserved_3[0x8]; 2901 u8 cqn[0x18]; 2902 2903 u8 counter_set_id[0x8]; 2904 u8 atomic_mode[0x4]; 2905 u8 rre[0x1]; 2906 u8 rwe[0x1]; 2907 u8 rae[0x1]; 2908 u8 atomic_like_write_en[0x1]; 2909 u8 latency_sensitive[0x1]; 2910 u8 rlky[0x1]; 2911 u8 reserved_4[0xe]; 2912 2913 u8 reserved_5[0x8]; 2914 u8 cs_res[0x8]; 2915 u8 reserved_6[0x3]; 2916 u8 min_rnr_nak[0x5]; 2917 u8 reserved_7[0x8]; 2918 2919 u8 reserved_8[0x8]; 2920 u8 srqn[0x18]; 2921 2922 u8 reserved_9[0x8]; 2923 u8 pd[0x18]; 2924 2925 u8 tclass[0x8]; 2926 u8 reserved_10[0x4]; 2927 u8 flow_label[0x14]; 2928 2929 u8 dc_access_key[0x40]; 2930 2931 u8 reserved_11[0x5]; 2932 u8 mtu[0x3]; 2933 u8 port[0x8]; 2934 u8 pkey_index[0x10]; 2935 2936 u8 reserved_12[0x8]; 2937 u8 my_addr_index[0x8]; 2938 u8 reserved_13[0x8]; 2939 u8 hop_limit[0x8]; 2940 2941 u8 dc_access_key_violation_count[0x20]; 2942 2943 u8 reserved_14[0x14]; 2944 u8 dei_cfi[0x1]; 2945 u8 eth_prio[0x3]; 2946 u8 ecn[0x2]; 2947 u8 dscp[0x6]; 2948 2949 u8 reserved_15[0x40]; 2950 }; 2951 2952 enum { 2953 MLX5_CQC_STATUS_OK = 0x0, 2954 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2955 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2956 }; 2957 2958 enum { 2959 CQE_SIZE_64 = 0x0, 2960 CQE_SIZE_128 = 0x1, 2961 }; 2962 2963 enum { 2964 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2965 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2966 }; 2967 2968 enum { 2969 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 2970 MLX5_CQ_STATE_ARMED = 0x9, 2971 MLX5_CQ_STATE_FIRED = 0xa, 2972 }; 2973 2974 struct mlx5_ifc_cqc_bits { 2975 u8 status[0x4]; 2976 u8 reserved_0[0x4]; 2977 u8 cqe_sz[0x3]; 2978 u8 cc[0x1]; 2979 u8 reserved_1[0x1]; 2980 u8 scqe_break_moderation_en[0x1]; 2981 u8 oi[0x1]; 2982 u8 cq_period_mode[0x2]; 2983 u8 cqe_compression_en[0x1]; 2984 u8 mini_cqe_res_format[0x2]; 2985 u8 st[0x4]; 2986 u8 reserved_2[0x8]; 2987 2988 u8 reserved_3[0x20]; 2989 2990 u8 reserved_4[0x14]; 2991 u8 page_offset[0x6]; 2992 u8 reserved_5[0x6]; 2993 2994 u8 reserved_6[0x3]; 2995 u8 log_cq_size[0x5]; 2996 u8 uar_page[0x18]; 2997 2998 u8 reserved_7[0x4]; 2999 u8 cq_period[0xc]; 3000 u8 cq_max_count[0x10]; 3001 3002 u8 reserved_8[0x18]; 3003 u8 c_eqn[0x8]; 3004 3005 u8 reserved_9[0x3]; 3006 u8 log_page_size[0x5]; 3007 u8 reserved_10[0x18]; 3008 3009 u8 reserved_11[0x20]; 3010 3011 u8 reserved_12[0x8]; 3012 u8 last_notified_index[0x18]; 3013 3014 u8 reserved_13[0x8]; 3015 u8 last_solicit_index[0x18]; 3016 3017 u8 reserved_14[0x8]; 3018 u8 consumer_counter[0x18]; 3019 3020 u8 reserved_15[0x8]; 3021 u8 producer_counter[0x18]; 3022 3023 u8 reserved_16[0x40]; 3024 3025 u8 dbr_addr[0x40]; 3026 }; 3027 3028 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3029 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3030 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3031 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3032 u8 reserved_0[0x800]; 3033 }; 3034 3035 struct mlx5_ifc_query_adapter_param_block_bits { 3036 u8 reserved_0[0xc0]; 3037 3038 u8 reserved_1[0x8]; 3039 u8 ieee_vendor_id[0x18]; 3040 3041 u8 reserved_2[0x10]; 3042 u8 vsd_vendor_id[0x10]; 3043 3044 u8 vsd[208][0x8]; 3045 3046 u8 vsd_contd_psid[16][0x8]; 3047 }; 3048 3049 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3050 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3051 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3052 u8 reserved_0[0x20]; 3053 }; 3054 3055 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3056 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3057 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3058 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3059 u8 reserved_0[0x20]; 3060 }; 3061 3062 struct mlx5_ifc_bufferx_reg_bits { 3063 u8 reserved_0[0x6]; 3064 u8 lossy[0x1]; 3065 u8 epsb[0x1]; 3066 u8 reserved_1[0xc]; 3067 u8 size[0xc]; 3068 3069 u8 xoff_threshold[0x10]; 3070 u8 xon_threshold[0x10]; 3071 }; 3072 3073 struct mlx5_ifc_config_item_bits { 3074 u8 valid[0x2]; 3075 u8 reserved_0[0x2]; 3076 u8 header_type[0x2]; 3077 u8 reserved_1[0x2]; 3078 u8 default_location[0x1]; 3079 u8 reserved_2[0x7]; 3080 u8 version[0x4]; 3081 u8 reserved_3[0x3]; 3082 u8 length[0x9]; 3083 3084 u8 type[0x20]; 3085 3086 u8 reserved_4[0x10]; 3087 u8 crc16[0x10]; 3088 }; 3089 3090 struct mlx5_ifc_nodnic_port_config_reg_bits { 3091 struct mlx5_ifc_nodnic_event_word_bits event; 3092 3093 u8 network_en[0x1]; 3094 u8 dma_en[0x1]; 3095 u8 promisc_en[0x1]; 3096 u8 promisc_multicast_en[0x1]; 3097 u8 reserved_0[0x17]; 3098 u8 receive_filter_en[0x5]; 3099 3100 u8 reserved_1[0x10]; 3101 u8 mac_47_32[0x10]; 3102 3103 u8 mac_31_0[0x20]; 3104 3105 u8 receive_filters_mgid_mac[64][0x8]; 3106 3107 u8 gid[16][0x8]; 3108 3109 u8 reserved_2[0x10]; 3110 u8 lid[0x10]; 3111 3112 u8 reserved_3[0xc]; 3113 u8 sm_sl[0x4]; 3114 u8 sm_lid[0x10]; 3115 3116 u8 completion_address_63_32[0x20]; 3117 3118 u8 completion_address_31_12[0x14]; 3119 u8 reserved_4[0x6]; 3120 u8 log_cq_size[0x6]; 3121 3122 u8 working_buffer_address_63_32[0x20]; 3123 3124 u8 working_buffer_address_31_12[0x14]; 3125 u8 reserved_5[0xc]; 3126 3127 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 3128 3129 u8 pkey_index[0x10]; 3130 u8 pkey[0x10]; 3131 3132 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 3133 3134 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 3135 3136 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 3137 3138 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 3139 3140 u8 reserved_6[0x400]; 3141 }; 3142 3143 union mlx5_ifc_event_auto_bits { 3144 struct mlx5_ifc_comp_event_bits comp_event; 3145 struct mlx5_ifc_dct_events_bits dct_events; 3146 struct mlx5_ifc_qp_events_bits qp_events; 3147 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3148 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3149 struct mlx5_ifc_cq_error_bits cq_error; 3150 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3151 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3152 struct mlx5_ifc_gpio_event_bits gpio_event; 3153 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3154 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3155 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3156 struct mlx5_ifc_pages_req_event_bits pages_req_event; 3157 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 3158 u8 reserved_0[0xe0]; 3159 }; 3160 3161 struct mlx5_ifc_health_buffer_bits { 3162 u8 reserved_0[0x100]; 3163 3164 u8 assert_existptr[0x20]; 3165 3166 u8 assert_callra[0x20]; 3167 3168 u8 reserved_1[0x40]; 3169 3170 u8 fw_version[0x20]; 3171 3172 u8 hw_id[0x20]; 3173 3174 u8 reserved_2[0x20]; 3175 3176 u8 irisc_index[0x8]; 3177 u8 synd[0x8]; 3178 u8 ext_synd[0x10]; 3179 }; 3180 3181 struct mlx5_ifc_register_loopback_control_bits { 3182 u8 no_lb[0x1]; 3183 u8 reserved_0[0x7]; 3184 u8 port[0x8]; 3185 u8 reserved_1[0x10]; 3186 3187 u8 reserved_2[0x60]; 3188 }; 3189 3190 struct mlx5_ifc_lrh_bits { 3191 u8 vl[4]; 3192 u8 lver[4]; 3193 u8 sl[4]; 3194 u8 reserved2[2]; 3195 u8 lnh[2]; 3196 u8 dlid[16]; 3197 u8 reserved5[5]; 3198 u8 pkt_len[11]; 3199 u8 slid[16]; 3200 }; 3201 3202 struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3203 u8 reserved_0[0x40]; 3204 3205 u8 reserved_1[0x10]; 3206 u8 rol_mode[0x8]; 3207 u8 wol_mode[0x8]; 3208 }; 3209 3210 struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3211 u8 reserved_0[0x40]; 3212 3213 u8 rol_mode_valid[0x1]; 3214 u8 wol_mode_valid[0x1]; 3215 u8 reserved_1[0xe]; 3216 u8 rol_mode[0x8]; 3217 u8 wol_mode[0x8]; 3218 3219 u8 reserved_2[0x7a0]; 3220 }; 3221 3222 struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3223 u8 virtual_mac_en[0x1]; 3224 u8 mac_aux_v[0x1]; 3225 u8 reserved_0[0x1e]; 3226 3227 u8 reserved_1[0x40]; 3228 3229 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3230 3231 u8 reserved_2[0x760]; 3232 }; 3233 3234 struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3235 u8 virtual_mac_en[0x1]; 3236 u8 mac_aux_v[0x1]; 3237 u8 reserved_0[0x1e]; 3238 3239 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3240 3241 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3242 3243 u8 reserved_1[0x760]; 3244 }; 3245 3246 struct mlx5_ifc_icmd_query_fw_info_out_bits { 3247 struct mlx5_ifc_fw_version_bits fw_version; 3248 3249 u8 reserved_0[0x10]; 3250 u8 hash_signature[0x10]; 3251 3252 u8 psid[16][0x8]; 3253 3254 u8 reserved_1[0x6e0]; 3255 }; 3256 3257 struct mlx5_ifc_icmd_query_cap_in_bits { 3258 u8 reserved_0[0x10]; 3259 u8 capability_group[0x10]; 3260 }; 3261 3262 struct mlx5_ifc_icmd_query_cap_general_bits { 3263 u8 nv_access[0x1]; 3264 u8 fw_info_psid[0x1]; 3265 u8 reserved_0[0x1e]; 3266 3267 u8 reserved_1[0x16]; 3268 u8 rol_s[0x1]; 3269 u8 rol_g[0x1]; 3270 u8 reserved_2[0x1]; 3271 u8 wol_s[0x1]; 3272 u8 wol_g[0x1]; 3273 u8 wol_a[0x1]; 3274 u8 wol_b[0x1]; 3275 u8 wol_m[0x1]; 3276 u8 wol_u[0x1]; 3277 u8 wol_p[0x1]; 3278 }; 3279 3280 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3281 u8 status[0x8]; 3282 u8 reserved_0[0x18]; 3283 3284 u8 reserved_1[0x7e0]; 3285 }; 3286 3287 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3288 u8 status[0x8]; 3289 u8 reserved_0[0x18]; 3290 3291 u8 reserved_1[0x7e0]; 3292 }; 3293 3294 struct mlx5_ifc_icmd_ocbb_init_in_bits { 3295 u8 address_hi[0x20]; 3296 3297 u8 address_lo[0x20]; 3298 3299 u8 reserved_0[0x7c0]; 3300 }; 3301 3302 struct mlx5_ifc_icmd_init_ocsd_in_bits { 3303 u8 reserved_0[0x20]; 3304 3305 u8 address_hi[0x20]; 3306 3307 u8 address_lo[0x20]; 3308 3309 u8 reserved_1[0x7a0]; 3310 }; 3311 3312 struct mlx5_ifc_icmd_access_reg_out_bits { 3313 u8 reserved_0[0x11]; 3314 u8 status[0x7]; 3315 u8 reserved_1[0x8]; 3316 3317 u8 register_id[0x10]; 3318 u8 reserved_2[0x10]; 3319 3320 u8 reserved_3[0x40]; 3321 3322 u8 reserved_4[0x5]; 3323 u8 len[0xb]; 3324 u8 reserved_5[0x10]; 3325 3326 u8 register_data[0][0x20]; 3327 }; 3328 3329 enum { 3330 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3331 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3332 }; 3333 3334 struct mlx5_ifc_icmd_access_reg_in_bits { 3335 u8 constant_1[0x5]; 3336 u8 constant_2[0xb]; 3337 u8 reserved_0[0x10]; 3338 3339 u8 register_id[0x10]; 3340 u8 reserved_1[0x1]; 3341 u8 method[0x7]; 3342 u8 constant_3[0x8]; 3343 3344 u8 reserved_2[0x40]; 3345 3346 u8 constant_4[0x5]; 3347 u8 len[0xb]; 3348 u8 reserved_3[0x10]; 3349 3350 u8 register_data[0][0x20]; 3351 }; 3352 3353 enum { 3354 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3355 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3356 }; 3357 3358 struct mlx5_ifc_teardown_hca_out_bits { 3359 u8 status[0x8]; 3360 u8 reserved_0[0x18]; 3361 3362 u8 syndrome[0x20]; 3363 3364 u8 reserved_1[0x3f]; 3365 3366 u8 state[0x1]; 3367 }; 3368 3369 enum { 3370 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3371 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3372 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3373 }; 3374 3375 struct mlx5_ifc_teardown_hca_in_bits { 3376 u8 opcode[0x10]; 3377 u8 reserved_0[0x10]; 3378 3379 u8 reserved_1[0x10]; 3380 u8 op_mod[0x10]; 3381 3382 u8 reserved_2[0x10]; 3383 u8 profile[0x10]; 3384 3385 u8 reserved_3[0x20]; 3386 }; 3387 3388 struct mlx5_ifc_set_delay_drop_params_out_bits { 3389 u8 status[0x8]; 3390 u8 reserved_at_8[0x18]; 3391 3392 u8 syndrome[0x20]; 3393 3394 u8 reserved_at_40[0x40]; 3395 }; 3396 3397 struct mlx5_ifc_set_delay_drop_params_in_bits { 3398 u8 opcode[0x10]; 3399 u8 reserved_at_10[0x10]; 3400 3401 u8 reserved_at_20[0x10]; 3402 u8 op_mod[0x10]; 3403 3404 u8 reserved_at_40[0x20]; 3405 3406 u8 reserved_at_60[0x10]; 3407 u8 delay_drop_timeout[0x10]; 3408 }; 3409 3410 struct mlx5_ifc_query_delay_drop_params_out_bits { 3411 u8 status[0x8]; 3412 u8 reserved_at_8[0x18]; 3413 3414 u8 syndrome[0x20]; 3415 3416 u8 reserved_at_40[0x20]; 3417 3418 u8 reserved_at_60[0x10]; 3419 u8 delay_drop_timeout[0x10]; 3420 }; 3421 3422 struct mlx5_ifc_query_delay_drop_params_in_bits { 3423 u8 opcode[0x10]; 3424 u8 reserved_at_10[0x10]; 3425 3426 u8 reserved_at_20[0x10]; 3427 u8 op_mod[0x10]; 3428 3429 u8 reserved_at_40[0x40]; 3430 }; 3431 3432 struct mlx5_ifc_suspend_qp_out_bits { 3433 u8 status[0x8]; 3434 u8 reserved_0[0x18]; 3435 3436 u8 syndrome[0x20]; 3437 3438 u8 reserved_1[0x40]; 3439 }; 3440 3441 struct mlx5_ifc_suspend_qp_in_bits { 3442 u8 opcode[0x10]; 3443 u8 reserved_0[0x10]; 3444 3445 u8 reserved_1[0x10]; 3446 u8 op_mod[0x10]; 3447 3448 u8 reserved_2[0x8]; 3449 u8 qpn[0x18]; 3450 3451 u8 reserved_3[0x20]; 3452 }; 3453 3454 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3455 u8 status[0x8]; 3456 u8 reserved_0[0x18]; 3457 3458 u8 syndrome[0x20]; 3459 3460 u8 reserved_1[0x40]; 3461 }; 3462 3463 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3464 u8 opcode[0x10]; 3465 u8 reserved_0[0x10]; 3466 3467 u8 reserved_1[0x10]; 3468 u8 op_mod[0x10]; 3469 3470 u8 reserved_2[0x8]; 3471 u8 qpn[0x18]; 3472 3473 u8 reserved_3[0x20]; 3474 3475 u8 opt_param_mask[0x20]; 3476 3477 u8 reserved_4[0x20]; 3478 3479 struct mlx5_ifc_qpc_bits qpc; 3480 3481 u8 reserved_5[0x80]; 3482 }; 3483 3484 struct mlx5_ifc_sqd2rts_qp_out_bits { 3485 u8 status[0x8]; 3486 u8 reserved_0[0x18]; 3487 3488 u8 syndrome[0x20]; 3489 3490 u8 reserved_1[0x40]; 3491 }; 3492 3493 struct mlx5_ifc_sqd2rts_qp_in_bits { 3494 u8 opcode[0x10]; 3495 u8 reserved_0[0x10]; 3496 3497 u8 reserved_1[0x10]; 3498 u8 op_mod[0x10]; 3499 3500 u8 reserved_2[0x8]; 3501 u8 qpn[0x18]; 3502 3503 u8 reserved_3[0x20]; 3504 3505 u8 opt_param_mask[0x20]; 3506 3507 u8 reserved_4[0x20]; 3508 3509 struct mlx5_ifc_qpc_bits qpc; 3510 3511 u8 reserved_5[0x80]; 3512 }; 3513 3514 struct mlx5_ifc_set_wol_rol_out_bits { 3515 u8 status[0x8]; 3516 u8 reserved_0[0x18]; 3517 3518 u8 syndrome[0x20]; 3519 3520 u8 reserved_1[0x40]; 3521 }; 3522 3523 struct mlx5_ifc_set_wol_rol_in_bits { 3524 u8 opcode[0x10]; 3525 u8 reserved_0[0x10]; 3526 3527 u8 reserved_1[0x10]; 3528 u8 op_mod[0x10]; 3529 3530 u8 rol_mode_valid[0x1]; 3531 u8 wol_mode_valid[0x1]; 3532 u8 reserved_2[0xe]; 3533 u8 rol_mode[0x8]; 3534 u8 wol_mode[0x8]; 3535 3536 u8 reserved_3[0x20]; 3537 }; 3538 3539 struct mlx5_ifc_set_roce_address_out_bits { 3540 u8 status[0x8]; 3541 u8 reserved_0[0x18]; 3542 3543 u8 syndrome[0x20]; 3544 3545 u8 reserved_1[0x40]; 3546 }; 3547 3548 struct mlx5_ifc_set_roce_address_in_bits { 3549 u8 opcode[0x10]; 3550 u8 reserved_0[0x10]; 3551 3552 u8 reserved_1[0x10]; 3553 u8 op_mod[0x10]; 3554 3555 u8 roce_address_index[0x10]; 3556 u8 reserved_2[0x10]; 3557 3558 u8 reserved_3[0x20]; 3559 3560 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3561 }; 3562 3563 struct mlx5_ifc_set_rdb_out_bits { 3564 u8 status[0x8]; 3565 u8 reserved_0[0x18]; 3566 3567 u8 syndrome[0x20]; 3568 3569 u8 reserved_1[0x40]; 3570 }; 3571 3572 struct mlx5_ifc_set_rdb_in_bits { 3573 u8 opcode[0x10]; 3574 u8 reserved_0[0x10]; 3575 3576 u8 reserved_1[0x10]; 3577 u8 op_mod[0x10]; 3578 3579 u8 reserved_2[0x8]; 3580 u8 qpn[0x18]; 3581 3582 u8 reserved_3[0x18]; 3583 u8 rdb_list_size[0x8]; 3584 3585 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3586 }; 3587 3588 struct mlx5_ifc_set_mad_demux_out_bits { 3589 u8 status[0x8]; 3590 u8 reserved_0[0x18]; 3591 3592 u8 syndrome[0x20]; 3593 3594 u8 reserved_1[0x40]; 3595 }; 3596 3597 enum { 3598 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3599 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3600 }; 3601 3602 struct mlx5_ifc_set_mad_demux_in_bits { 3603 u8 opcode[0x10]; 3604 u8 reserved_0[0x10]; 3605 3606 u8 reserved_1[0x10]; 3607 u8 op_mod[0x10]; 3608 3609 u8 reserved_2[0x20]; 3610 3611 u8 reserved_3[0x6]; 3612 u8 demux_mode[0x2]; 3613 u8 reserved_4[0x18]; 3614 }; 3615 3616 struct mlx5_ifc_set_l2_table_entry_out_bits { 3617 u8 status[0x8]; 3618 u8 reserved_0[0x18]; 3619 3620 u8 syndrome[0x20]; 3621 3622 u8 reserved_1[0x40]; 3623 }; 3624 3625 struct mlx5_ifc_set_l2_table_entry_in_bits { 3626 u8 opcode[0x10]; 3627 u8 reserved_0[0x10]; 3628 3629 u8 reserved_1[0x10]; 3630 u8 op_mod[0x10]; 3631 3632 u8 reserved_2[0x60]; 3633 3634 u8 reserved_3[0x8]; 3635 u8 table_index[0x18]; 3636 3637 u8 reserved_4[0x20]; 3638 3639 u8 reserved_5[0x13]; 3640 u8 vlan_valid[0x1]; 3641 u8 vlan[0xc]; 3642 3643 struct mlx5_ifc_mac_address_layout_bits mac_address; 3644 3645 u8 reserved_6[0xc0]; 3646 }; 3647 3648 struct mlx5_ifc_set_issi_out_bits { 3649 u8 status[0x8]; 3650 u8 reserved_0[0x18]; 3651 3652 u8 syndrome[0x20]; 3653 3654 u8 reserved_1[0x40]; 3655 }; 3656 3657 struct mlx5_ifc_set_issi_in_bits { 3658 u8 opcode[0x10]; 3659 u8 reserved_0[0x10]; 3660 3661 u8 reserved_1[0x10]; 3662 u8 op_mod[0x10]; 3663 3664 u8 reserved_2[0x10]; 3665 u8 current_issi[0x10]; 3666 3667 u8 reserved_3[0x20]; 3668 }; 3669 3670 struct mlx5_ifc_set_hca_cap_out_bits { 3671 u8 status[0x8]; 3672 u8 reserved_0[0x18]; 3673 3674 u8 syndrome[0x20]; 3675 3676 u8 reserved_1[0x40]; 3677 }; 3678 3679 struct mlx5_ifc_set_hca_cap_in_bits { 3680 u8 opcode[0x10]; 3681 u8 reserved_0[0x10]; 3682 3683 u8 reserved_1[0x10]; 3684 u8 op_mod[0x10]; 3685 3686 u8 reserved_2[0x40]; 3687 3688 union mlx5_ifc_hca_cap_union_bits capability; 3689 }; 3690 3691 enum { 3692 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3693 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3694 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3695 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3696 }; 3697 3698 struct mlx5_ifc_set_flow_table_root_out_bits { 3699 u8 status[0x8]; 3700 u8 reserved_0[0x18]; 3701 3702 u8 syndrome[0x20]; 3703 3704 u8 reserved_1[0x40]; 3705 }; 3706 3707 struct mlx5_ifc_set_flow_table_root_in_bits { 3708 u8 opcode[0x10]; 3709 u8 reserved_0[0x10]; 3710 3711 u8 reserved_1[0x10]; 3712 u8 op_mod[0x10]; 3713 3714 u8 other_vport[0x1]; 3715 u8 reserved_2[0xf]; 3716 u8 vport_number[0x10]; 3717 3718 u8 reserved_3[0x20]; 3719 3720 u8 table_type[0x8]; 3721 u8 reserved_4[0x18]; 3722 3723 u8 reserved_5[0x8]; 3724 u8 table_id[0x18]; 3725 3726 u8 reserved_6[0x8]; 3727 u8 underlay_qpn[0x18]; 3728 3729 u8 reserved_7[0x120]; 3730 }; 3731 3732 struct mlx5_ifc_set_fte_out_bits { 3733 u8 status[0x8]; 3734 u8 reserved_0[0x18]; 3735 3736 u8 syndrome[0x20]; 3737 3738 u8 reserved_1[0x40]; 3739 }; 3740 3741 struct mlx5_ifc_set_fte_in_bits { 3742 u8 opcode[0x10]; 3743 u8 reserved_0[0x10]; 3744 3745 u8 reserved_1[0x10]; 3746 u8 op_mod[0x10]; 3747 3748 u8 other_vport[0x1]; 3749 u8 reserved_2[0xf]; 3750 u8 vport_number[0x10]; 3751 3752 u8 reserved_3[0x20]; 3753 3754 u8 table_type[0x8]; 3755 u8 reserved_4[0x18]; 3756 3757 u8 reserved_5[0x8]; 3758 u8 table_id[0x18]; 3759 3760 u8 reserved_6[0x18]; 3761 u8 modify_enable_mask[0x8]; 3762 3763 u8 reserved_7[0x20]; 3764 3765 u8 flow_index[0x20]; 3766 3767 u8 reserved_8[0xe0]; 3768 3769 struct mlx5_ifc_flow_context_bits flow_context; 3770 }; 3771 3772 struct mlx5_ifc_set_driver_version_out_bits { 3773 u8 status[0x8]; 3774 u8 reserved_0[0x18]; 3775 3776 u8 syndrome[0x20]; 3777 3778 u8 reserved_1[0x40]; 3779 }; 3780 3781 struct mlx5_ifc_set_driver_version_in_bits { 3782 u8 opcode[0x10]; 3783 u8 reserved_0[0x10]; 3784 3785 u8 reserved_1[0x10]; 3786 u8 op_mod[0x10]; 3787 3788 u8 reserved_2[0x40]; 3789 3790 u8 driver_version[64][0x8]; 3791 }; 3792 3793 struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3794 u8 status[0x8]; 3795 u8 reserved_0[0x18]; 3796 3797 u8 syndrome[0x20]; 3798 3799 u8 reserved_1[0x40]; 3800 }; 3801 3802 struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3803 u8 opcode[0x10]; 3804 u8 reserved_0[0x10]; 3805 3806 u8 reserved_1[0x10]; 3807 u8 op_mod[0x10]; 3808 3809 u8 enable[0x1]; 3810 u8 reserved_2[0x1f]; 3811 3812 u8 reserved_3[0x160]; 3813 3814 struct mlx5_ifc_cmd_pas_bits pas; 3815 }; 3816 3817 struct mlx5_ifc_set_burst_size_out_bits { 3818 u8 status[0x8]; 3819 u8 reserved_0[0x18]; 3820 3821 u8 syndrome[0x20]; 3822 3823 u8 reserved_1[0x40]; 3824 }; 3825 3826 struct mlx5_ifc_set_burst_size_in_bits { 3827 u8 opcode[0x10]; 3828 u8 reserved_0[0x10]; 3829 3830 u8 reserved_1[0x10]; 3831 u8 op_mod[0x10]; 3832 3833 u8 reserved_2[0x20]; 3834 3835 u8 reserved_3[0x9]; 3836 u8 device_burst_size[0x17]; 3837 }; 3838 3839 struct mlx5_ifc_rts2rts_qp_out_bits { 3840 u8 status[0x8]; 3841 u8 reserved_0[0x18]; 3842 3843 u8 syndrome[0x20]; 3844 3845 u8 reserved_1[0x40]; 3846 }; 3847 3848 struct mlx5_ifc_rts2rts_qp_in_bits { 3849 u8 opcode[0x10]; 3850 u8 reserved_0[0x10]; 3851 3852 u8 reserved_1[0x10]; 3853 u8 op_mod[0x10]; 3854 3855 u8 reserved_2[0x8]; 3856 u8 qpn[0x18]; 3857 3858 u8 reserved_3[0x20]; 3859 3860 u8 opt_param_mask[0x20]; 3861 3862 u8 reserved_4[0x20]; 3863 3864 struct mlx5_ifc_qpc_bits qpc; 3865 3866 u8 reserved_5[0x80]; 3867 }; 3868 3869 struct mlx5_ifc_rtr2rts_qp_out_bits { 3870 u8 status[0x8]; 3871 u8 reserved_0[0x18]; 3872 3873 u8 syndrome[0x20]; 3874 3875 u8 reserved_1[0x40]; 3876 }; 3877 3878 struct mlx5_ifc_rtr2rts_qp_in_bits { 3879 u8 opcode[0x10]; 3880 u8 reserved_0[0x10]; 3881 3882 u8 reserved_1[0x10]; 3883 u8 op_mod[0x10]; 3884 3885 u8 reserved_2[0x8]; 3886 u8 qpn[0x18]; 3887 3888 u8 reserved_3[0x20]; 3889 3890 u8 opt_param_mask[0x20]; 3891 3892 u8 reserved_4[0x20]; 3893 3894 struct mlx5_ifc_qpc_bits qpc; 3895 3896 u8 reserved_5[0x80]; 3897 }; 3898 3899 struct mlx5_ifc_rst2init_qp_out_bits { 3900 u8 status[0x8]; 3901 u8 reserved_0[0x18]; 3902 3903 u8 syndrome[0x20]; 3904 3905 u8 reserved_1[0x40]; 3906 }; 3907 3908 struct mlx5_ifc_rst2init_qp_in_bits { 3909 u8 opcode[0x10]; 3910 u8 reserved_0[0x10]; 3911 3912 u8 reserved_1[0x10]; 3913 u8 op_mod[0x10]; 3914 3915 u8 reserved_2[0x8]; 3916 u8 qpn[0x18]; 3917 3918 u8 reserved_3[0x20]; 3919 3920 u8 opt_param_mask[0x20]; 3921 3922 u8 reserved_4[0x20]; 3923 3924 struct mlx5_ifc_qpc_bits qpc; 3925 3926 u8 reserved_5[0x80]; 3927 }; 3928 3929 struct mlx5_ifc_resume_qp_out_bits { 3930 u8 status[0x8]; 3931 u8 reserved_0[0x18]; 3932 3933 u8 syndrome[0x20]; 3934 3935 u8 reserved_1[0x40]; 3936 }; 3937 3938 struct mlx5_ifc_resume_qp_in_bits { 3939 u8 opcode[0x10]; 3940 u8 reserved_0[0x10]; 3941 3942 u8 reserved_1[0x10]; 3943 u8 op_mod[0x10]; 3944 3945 u8 reserved_2[0x8]; 3946 u8 qpn[0x18]; 3947 3948 u8 reserved_3[0x20]; 3949 }; 3950 3951 struct mlx5_ifc_query_xrc_srq_out_bits { 3952 u8 status[0x8]; 3953 u8 reserved_0[0x18]; 3954 3955 u8 syndrome[0x20]; 3956 3957 u8 reserved_1[0x40]; 3958 3959 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3960 3961 u8 reserved_2[0x600]; 3962 3963 u8 pas[0][0x40]; 3964 }; 3965 3966 struct mlx5_ifc_query_xrc_srq_in_bits { 3967 u8 opcode[0x10]; 3968 u8 reserved_0[0x10]; 3969 3970 u8 reserved_1[0x10]; 3971 u8 op_mod[0x10]; 3972 3973 u8 reserved_2[0x8]; 3974 u8 xrc_srqn[0x18]; 3975 3976 u8 reserved_3[0x20]; 3977 }; 3978 3979 struct mlx5_ifc_query_wol_rol_out_bits { 3980 u8 status[0x8]; 3981 u8 reserved_0[0x18]; 3982 3983 u8 syndrome[0x20]; 3984 3985 u8 reserved_1[0x10]; 3986 u8 rol_mode[0x8]; 3987 u8 wol_mode[0x8]; 3988 3989 u8 reserved_2[0x20]; 3990 }; 3991 3992 struct mlx5_ifc_query_wol_rol_in_bits { 3993 u8 opcode[0x10]; 3994 u8 reserved_0[0x10]; 3995 3996 u8 reserved_1[0x10]; 3997 u8 op_mod[0x10]; 3998 3999 u8 reserved_2[0x40]; 4000 }; 4001 4002 enum { 4003 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4004 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4005 }; 4006 4007 struct mlx5_ifc_query_vport_state_out_bits { 4008 u8 status[0x8]; 4009 u8 reserved_0[0x18]; 4010 4011 u8 syndrome[0x20]; 4012 4013 u8 reserved_1[0x20]; 4014 4015 u8 reserved_2[0x18]; 4016 u8 admin_state[0x4]; 4017 u8 state[0x4]; 4018 }; 4019 4020 enum { 4021 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 4022 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 4023 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 4024 }; 4025 4026 struct mlx5_ifc_query_vport_state_in_bits { 4027 u8 opcode[0x10]; 4028 u8 reserved_0[0x10]; 4029 4030 u8 reserved_1[0x10]; 4031 u8 op_mod[0x10]; 4032 4033 u8 other_vport[0x1]; 4034 u8 reserved_2[0xf]; 4035 u8 vport_number[0x10]; 4036 4037 u8 reserved_3[0x20]; 4038 }; 4039 4040 struct mlx5_ifc_query_vnic_env_out_bits { 4041 u8 status[0x8]; 4042 u8 reserved_at_8[0x18]; 4043 4044 u8 syndrome[0x20]; 4045 4046 u8 reserved_at_40[0x40]; 4047 4048 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4049 }; 4050 4051 enum { 4052 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4053 }; 4054 4055 struct mlx5_ifc_query_vnic_env_in_bits { 4056 u8 opcode[0x10]; 4057 u8 reserved_at_10[0x10]; 4058 4059 u8 reserved_at_20[0x10]; 4060 u8 op_mod[0x10]; 4061 4062 u8 other_vport[0x1]; 4063 u8 reserved_at_41[0xf]; 4064 u8 vport_number[0x10]; 4065 4066 u8 reserved_at_60[0x20]; 4067 }; 4068 4069 struct mlx5_ifc_query_vport_counter_out_bits { 4070 u8 status[0x8]; 4071 u8 reserved_0[0x18]; 4072 4073 u8 syndrome[0x20]; 4074 4075 u8 reserved_1[0x40]; 4076 4077 struct mlx5_ifc_traffic_counter_bits received_errors; 4078 4079 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4080 4081 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4082 4083 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4084 4085 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4086 4087 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4088 4089 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4090 4091 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4092 4093 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4094 4095 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4096 4097 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4098 4099 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4100 4101 u8 reserved_2[0xa00]; 4102 }; 4103 4104 enum { 4105 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4106 }; 4107 4108 struct mlx5_ifc_query_vport_counter_in_bits { 4109 u8 opcode[0x10]; 4110 u8 reserved_0[0x10]; 4111 4112 u8 reserved_1[0x10]; 4113 u8 op_mod[0x10]; 4114 4115 u8 other_vport[0x1]; 4116 u8 reserved_2[0xb]; 4117 u8 port_num[0x4]; 4118 u8 vport_number[0x10]; 4119 4120 u8 reserved_3[0x60]; 4121 4122 u8 clear[0x1]; 4123 u8 reserved_4[0x1f]; 4124 4125 u8 reserved_5[0x20]; 4126 }; 4127 4128 struct mlx5_ifc_query_tis_out_bits { 4129 u8 status[0x8]; 4130 u8 reserved_0[0x18]; 4131 4132 u8 syndrome[0x20]; 4133 4134 u8 reserved_1[0x40]; 4135 4136 struct mlx5_ifc_tisc_bits tis_context; 4137 }; 4138 4139 struct mlx5_ifc_query_tis_in_bits { 4140 u8 opcode[0x10]; 4141 u8 reserved_0[0x10]; 4142 4143 u8 reserved_1[0x10]; 4144 u8 op_mod[0x10]; 4145 4146 u8 reserved_2[0x8]; 4147 u8 tisn[0x18]; 4148 4149 u8 reserved_3[0x20]; 4150 }; 4151 4152 struct mlx5_ifc_query_tir_out_bits { 4153 u8 status[0x8]; 4154 u8 reserved_0[0x18]; 4155 4156 u8 syndrome[0x20]; 4157 4158 u8 reserved_1[0xc0]; 4159 4160 struct mlx5_ifc_tirc_bits tir_context; 4161 }; 4162 4163 struct mlx5_ifc_query_tir_in_bits { 4164 u8 opcode[0x10]; 4165 u8 reserved_0[0x10]; 4166 4167 u8 reserved_1[0x10]; 4168 u8 op_mod[0x10]; 4169 4170 u8 reserved_2[0x8]; 4171 u8 tirn[0x18]; 4172 4173 u8 reserved_3[0x20]; 4174 }; 4175 4176 struct mlx5_ifc_query_srq_out_bits { 4177 u8 status[0x8]; 4178 u8 reserved_0[0x18]; 4179 4180 u8 syndrome[0x20]; 4181 4182 u8 reserved_1[0x40]; 4183 4184 struct mlx5_ifc_srqc_bits srq_context_entry; 4185 4186 u8 reserved_2[0x600]; 4187 4188 u8 pas[0][0x40]; 4189 }; 4190 4191 struct mlx5_ifc_query_srq_in_bits { 4192 u8 opcode[0x10]; 4193 u8 reserved_0[0x10]; 4194 4195 u8 reserved_1[0x10]; 4196 u8 op_mod[0x10]; 4197 4198 u8 reserved_2[0x8]; 4199 u8 srqn[0x18]; 4200 4201 u8 reserved_3[0x20]; 4202 }; 4203 4204 struct mlx5_ifc_query_sq_out_bits { 4205 u8 status[0x8]; 4206 u8 reserved_0[0x18]; 4207 4208 u8 syndrome[0x20]; 4209 4210 u8 reserved_1[0xc0]; 4211 4212 struct mlx5_ifc_sqc_bits sq_context; 4213 }; 4214 4215 struct mlx5_ifc_query_sq_in_bits { 4216 u8 opcode[0x10]; 4217 u8 reserved_0[0x10]; 4218 4219 u8 reserved_1[0x10]; 4220 u8 op_mod[0x10]; 4221 4222 u8 reserved_2[0x8]; 4223 u8 sqn[0x18]; 4224 4225 u8 reserved_3[0x20]; 4226 }; 4227 4228 struct mlx5_ifc_query_special_contexts_out_bits { 4229 u8 status[0x8]; 4230 u8 reserved_0[0x18]; 4231 4232 u8 syndrome[0x20]; 4233 4234 u8 dump_fill_mkey[0x20]; 4235 4236 u8 resd_lkey[0x20]; 4237 }; 4238 4239 struct mlx5_ifc_query_special_contexts_in_bits { 4240 u8 opcode[0x10]; 4241 u8 reserved_0[0x10]; 4242 4243 u8 reserved_1[0x10]; 4244 u8 op_mod[0x10]; 4245 4246 u8 reserved_2[0x40]; 4247 }; 4248 4249 struct mlx5_ifc_query_scheduling_element_out_bits { 4250 u8 status[0x8]; 4251 u8 reserved_at_8[0x18]; 4252 4253 u8 syndrome[0x20]; 4254 4255 u8 reserved_at_40[0xc0]; 4256 4257 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4258 4259 u8 reserved_at_300[0x100]; 4260 }; 4261 4262 enum { 4263 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4264 }; 4265 4266 struct mlx5_ifc_query_scheduling_element_in_bits { 4267 u8 opcode[0x10]; 4268 u8 reserved_at_10[0x10]; 4269 4270 u8 reserved_at_20[0x10]; 4271 u8 op_mod[0x10]; 4272 4273 u8 scheduling_hierarchy[0x8]; 4274 u8 reserved_at_48[0x18]; 4275 4276 u8 scheduling_element_id[0x20]; 4277 4278 u8 reserved_at_80[0x180]; 4279 }; 4280 4281 struct mlx5_ifc_query_rqt_out_bits { 4282 u8 status[0x8]; 4283 u8 reserved_0[0x18]; 4284 4285 u8 syndrome[0x20]; 4286 4287 u8 reserved_1[0xc0]; 4288 4289 struct mlx5_ifc_rqtc_bits rqt_context; 4290 }; 4291 4292 struct mlx5_ifc_query_rqt_in_bits { 4293 u8 opcode[0x10]; 4294 u8 reserved_0[0x10]; 4295 4296 u8 reserved_1[0x10]; 4297 u8 op_mod[0x10]; 4298 4299 u8 reserved_2[0x8]; 4300 u8 rqtn[0x18]; 4301 4302 u8 reserved_3[0x20]; 4303 }; 4304 4305 struct mlx5_ifc_query_rq_out_bits { 4306 u8 status[0x8]; 4307 u8 reserved_0[0x18]; 4308 4309 u8 syndrome[0x20]; 4310 4311 u8 reserved_1[0xc0]; 4312 4313 struct mlx5_ifc_rqc_bits rq_context; 4314 }; 4315 4316 struct mlx5_ifc_query_rq_in_bits { 4317 u8 opcode[0x10]; 4318 u8 reserved_0[0x10]; 4319 4320 u8 reserved_1[0x10]; 4321 u8 op_mod[0x10]; 4322 4323 u8 reserved_2[0x8]; 4324 u8 rqn[0x18]; 4325 4326 u8 reserved_3[0x20]; 4327 }; 4328 4329 struct mlx5_ifc_query_roce_address_out_bits { 4330 u8 status[0x8]; 4331 u8 reserved_0[0x18]; 4332 4333 u8 syndrome[0x20]; 4334 4335 u8 reserved_1[0x40]; 4336 4337 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4338 }; 4339 4340 struct mlx5_ifc_query_roce_address_in_bits { 4341 u8 opcode[0x10]; 4342 u8 reserved_0[0x10]; 4343 4344 u8 reserved_1[0x10]; 4345 u8 op_mod[0x10]; 4346 4347 u8 roce_address_index[0x10]; 4348 u8 reserved_2[0x10]; 4349 4350 u8 reserved_3[0x20]; 4351 }; 4352 4353 struct mlx5_ifc_query_rmp_out_bits { 4354 u8 status[0x8]; 4355 u8 reserved_0[0x18]; 4356 4357 u8 syndrome[0x20]; 4358 4359 u8 reserved_1[0xc0]; 4360 4361 struct mlx5_ifc_rmpc_bits rmp_context; 4362 }; 4363 4364 struct mlx5_ifc_query_rmp_in_bits { 4365 u8 opcode[0x10]; 4366 u8 reserved_0[0x10]; 4367 4368 u8 reserved_1[0x10]; 4369 u8 op_mod[0x10]; 4370 4371 u8 reserved_2[0x8]; 4372 u8 rmpn[0x18]; 4373 4374 u8 reserved_3[0x20]; 4375 }; 4376 4377 struct mlx5_ifc_query_rdb_out_bits { 4378 u8 status[0x8]; 4379 u8 reserved_0[0x18]; 4380 4381 u8 syndrome[0x20]; 4382 4383 u8 reserved_1[0x20]; 4384 4385 u8 reserved_2[0x18]; 4386 u8 rdb_list_size[0x8]; 4387 4388 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4389 }; 4390 4391 struct mlx5_ifc_query_rdb_in_bits { 4392 u8 opcode[0x10]; 4393 u8 reserved_0[0x10]; 4394 4395 u8 reserved_1[0x10]; 4396 u8 op_mod[0x10]; 4397 4398 u8 reserved_2[0x8]; 4399 u8 qpn[0x18]; 4400 4401 u8 reserved_3[0x20]; 4402 }; 4403 4404 struct mlx5_ifc_query_qp_out_bits { 4405 u8 status[0x8]; 4406 u8 reserved_0[0x18]; 4407 4408 u8 syndrome[0x20]; 4409 4410 u8 reserved_1[0x40]; 4411 4412 u8 opt_param_mask[0x20]; 4413 4414 u8 reserved_2[0x20]; 4415 4416 struct mlx5_ifc_qpc_bits qpc; 4417 4418 u8 reserved_3[0x80]; 4419 4420 u8 pas[0][0x40]; 4421 }; 4422 4423 struct mlx5_ifc_query_qp_in_bits { 4424 u8 opcode[0x10]; 4425 u8 reserved_0[0x10]; 4426 4427 u8 reserved_1[0x10]; 4428 u8 op_mod[0x10]; 4429 4430 u8 reserved_2[0x8]; 4431 u8 qpn[0x18]; 4432 4433 u8 reserved_3[0x20]; 4434 }; 4435 4436 struct mlx5_ifc_query_q_counter_out_bits { 4437 u8 status[0x8]; 4438 u8 reserved_0[0x18]; 4439 4440 u8 syndrome[0x20]; 4441 4442 u8 reserved_1[0x40]; 4443 4444 u8 rx_write_requests[0x20]; 4445 4446 u8 reserved_2[0x20]; 4447 4448 u8 rx_read_requests[0x20]; 4449 4450 u8 reserved_3[0x20]; 4451 4452 u8 rx_atomic_requests[0x20]; 4453 4454 u8 reserved_4[0x20]; 4455 4456 u8 rx_dct_connect[0x20]; 4457 4458 u8 reserved_5[0x20]; 4459 4460 u8 out_of_buffer[0x20]; 4461 4462 u8 reserved_7[0x20]; 4463 4464 u8 out_of_sequence[0x20]; 4465 4466 u8 reserved_8[0x20]; 4467 4468 u8 duplicate_request[0x20]; 4469 4470 u8 reserved_9[0x20]; 4471 4472 u8 rnr_nak_retry_err[0x20]; 4473 4474 u8 reserved_10[0x20]; 4475 4476 u8 packet_seq_err[0x20]; 4477 4478 u8 reserved_11[0x20]; 4479 4480 u8 implied_nak_seq_err[0x20]; 4481 4482 u8 reserved_12[0x20]; 4483 4484 u8 local_ack_timeout_err[0x20]; 4485 4486 u8 reserved_13[0x20]; 4487 4488 u8 resp_rnr_nak[0x20]; 4489 4490 u8 reserved_14[0x20]; 4491 4492 u8 req_rnr_retries_exceeded[0x20]; 4493 4494 u8 reserved_15[0x460]; 4495 }; 4496 4497 struct mlx5_ifc_query_q_counter_in_bits { 4498 u8 opcode[0x10]; 4499 u8 reserved_0[0x10]; 4500 4501 u8 reserved_1[0x10]; 4502 u8 op_mod[0x10]; 4503 4504 u8 reserved_2[0x80]; 4505 4506 u8 clear[0x1]; 4507 u8 reserved_3[0x1f]; 4508 4509 u8 reserved_4[0x18]; 4510 u8 counter_set_id[0x8]; 4511 }; 4512 4513 struct mlx5_ifc_query_pages_out_bits { 4514 u8 status[0x8]; 4515 u8 reserved_0[0x18]; 4516 4517 u8 syndrome[0x20]; 4518 4519 u8 reserved_1[0x10]; 4520 u8 function_id[0x10]; 4521 4522 u8 num_pages[0x20]; 4523 }; 4524 4525 enum { 4526 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4527 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4528 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4529 }; 4530 4531 struct mlx5_ifc_query_pages_in_bits { 4532 u8 opcode[0x10]; 4533 u8 reserved_0[0x10]; 4534 4535 u8 reserved_1[0x10]; 4536 u8 op_mod[0x10]; 4537 4538 u8 reserved_2[0x10]; 4539 u8 function_id[0x10]; 4540 4541 u8 reserved_3[0x20]; 4542 }; 4543 4544 struct mlx5_ifc_query_nic_vport_context_out_bits { 4545 u8 status[0x8]; 4546 u8 reserved_0[0x18]; 4547 4548 u8 syndrome[0x20]; 4549 4550 u8 reserved_1[0x40]; 4551 4552 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4553 }; 4554 4555 struct mlx5_ifc_query_nic_vport_context_in_bits { 4556 u8 opcode[0x10]; 4557 u8 reserved_0[0x10]; 4558 4559 u8 reserved_1[0x10]; 4560 u8 op_mod[0x10]; 4561 4562 u8 other_vport[0x1]; 4563 u8 reserved_2[0xf]; 4564 u8 vport_number[0x10]; 4565 4566 u8 reserved_3[0x5]; 4567 u8 allowed_list_type[0x3]; 4568 u8 reserved_4[0x18]; 4569 }; 4570 4571 struct mlx5_ifc_query_mkey_out_bits { 4572 u8 status[0x8]; 4573 u8 reserved_0[0x18]; 4574 4575 u8 syndrome[0x20]; 4576 4577 u8 reserved_1[0x40]; 4578 4579 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4580 4581 u8 reserved_2[0x600]; 4582 4583 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4584 4585 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4586 }; 4587 4588 struct mlx5_ifc_query_mkey_in_bits { 4589 u8 opcode[0x10]; 4590 u8 reserved_0[0x10]; 4591 4592 u8 reserved_1[0x10]; 4593 u8 op_mod[0x10]; 4594 4595 u8 reserved_2[0x8]; 4596 u8 mkey_index[0x18]; 4597 4598 u8 pg_access[0x1]; 4599 u8 reserved_3[0x1f]; 4600 }; 4601 4602 struct mlx5_ifc_query_mad_demux_out_bits { 4603 u8 status[0x8]; 4604 u8 reserved_0[0x18]; 4605 4606 u8 syndrome[0x20]; 4607 4608 u8 reserved_1[0x40]; 4609 4610 u8 mad_dumux_parameters_block[0x20]; 4611 }; 4612 4613 struct mlx5_ifc_query_mad_demux_in_bits { 4614 u8 opcode[0x10]; 4615 u8 reserved_0[0x10]; 4616 4617 u8 reserved_1[0x10]; 4618 u8 op_mod[0x10]; 4619 4620 u8 reserved_2[0x40]; 4621 }; 4622 4623 struct mlx5_ifc_query_l2_table_entry_out_bits { 4624 u8 status[0x8]; 4625 u8 reserved_0[0x18]; 4626 4627 u8 syndrome[0x20]; 4628 4629 u8 reserved_1[0xa0]; 4630 4631 u8 reserved_2[0x13]; 4632 u8 vlan_valid[0x1]; 4633 u8 vlan[0xc]; 4634 4635 struct mlx5_ifc_mac_address_layout_bits mac_address; 4636 4637 u8 reserved_3[0xc0]; 4638 }; 4639 4640 struct mlx5_ifc_query_l2_table_entry_in_bits { 4641 u8 opcode[0x10]; 4642 u8 reserved_0[0x10]; 4643 4644 u8 reserved_1[0x10]; 4645 u8 op_mod[0x10]; 4646 4647 u8 reserved_2[0x60]; 4648 4649 u8 reserved_3[0x8]; 4650 u8 table_index[0x18]; 4651 4652 u8 reserved_4[0x140]; 4653 }; 4654 4655 struct mlx5_ifc_query_issi_out_bits { 4656 u8 status[0x8]; 4657 u8 reserved_0[0x18]; 4658 4659 u8 syndrome[0x20]; 4660 4661 u8 reserved_1[0x10]; 4662 u8 current_issi[0x10]; 4663 4664 u8 reserved_2[0xa0]; 4665 4666 u8 supported_issi_reserved[76][0x8]; 4667 u8 supported_issi_dw0[0x20]; 4668 }; 4669 4670 struct mlx5_ifc_query_issi_in_bits { 4671 u8 opcode[0x10]; 4672 u8 reserved_0[0x10]; 4673 4674 u8 reserved_1[0x10]; 4675 u8 op_mod[0x10]; 4676 4677 u8 reserved_2[0x40]; 4678 }; 4679 4680 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4681 u8 status[0x8]; 4682 u8 reserved_0[0x18]; 4683 4684 u8 syndrome[0x20]; 4685 4686 u8 reserved_1[0x40]; 4687 4688 struct mlx5_ifc_pkey_bits pkey[0]; 4689 }; 4690 4691 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4692 u8 opcode[0x10]; 4693 u8 reserved_0[0x10]; 4694 4695 u8 reserved_1[0x10]; 4696 u8 op_mod[0x10]; 4697 4698 u8 other_vport[0x1]; 4699 u8 reserved_2[0xb]; 4700 u8 port_num[0x4]; 4701 u8 vport_number[0x10]; 4702 4703 u8 reserved_3[0x10]; 4704 u8 pkey_index[0x10]; 4705 }; 4706 4707 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4708 u8 status[0x8]; 4709 u8 reserved_0[0x18]; 4710 4711 u8 syndrome[0x20]; 4712 4713 u8 reserved_1[0x20]; 4714 4715 u8 gids_num[0x10]; 4716 u8 reserved_2[0x10]; 4717 4718 struct mlx5_ifc_array128_auto_bits gid[0]; 4719 }; 4720 4721 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4722 u8 opcode[0x10]; 4723 u8 reserved_0[0x10]; 4724 4725 u8 reserved_1[0x10]; 4726 u8 op_mod[0x10]; 4727 4728 u8 other_vport[0x1]; 4729 u8 reserved_2[0xb]; 4730 u8 port_num[0x4]; 4731 u8 vport_number[0x10]; 4732 4733 u8 reserved_3[0x10]; 4734 u8 gid_index[0x10]; 4735 }; 4736 4737 struct mlx5_ifc_query_hca_vport_context_out_bits { 4738 u8 status[0x8]; 4739 u8 reserved_0[0x18]; 4740 4741 u8 syndrome[0x20]; 4742 4743 u8 reserved_1[0x40]; 4744 4745 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4746 }; 4747 4748 struct mlx5_ifc_query_hca_vport_context_in_bits { 4749 u8 opcode[0x10]; 4750 u8 reserved_0[0x10]; 4751 4752 u8 reserved_1[0x10]; 4753 u8 op_mod[0x10]; 4754 4755 u8 other_vport[0x1]; 4756 u8 reserved_2[0xb]; 4757 u8 port_num[0x4]; 4758 u8 vport_number[0x10]; 4759 4760 u8 reserved_3[0x20]; 4761 }; 4762 4763 struct mlx5_ifc_query_hca_cap_out_bits { 4764 u8 status[0x8]; 4765 u8 reserved_0[0x18]; 4766 4767 u8 syndrome[0x20]; 4768 4769 u8 reserved_1[0x40]; 4770 4771 union mlx5_ifc_hca_cap_union_bits capability; 4772 }; 4773 4774 struct mlx5_ifc_query_hca_cap_in_bits { 4775 u8 opcode[0x10]; 4776 u8 reserved_0[0x10]; 4777 4778 u8 reserved_1[0x10]; 4779 u8 op_mod[0x10]; 4780 4781 u8 reserved_2[0x40]; 4782 }; 4783 4784 struct mlx5_ifc_query_flow_table_out_bits { 4785 u8 status[0x8]; 4786 u8 reserved_at_8[0x18]; 4787 4788 u8 syndrome[0x20]; 4789 4790 u8 reserved_at_40[0x80]; 4791 4792 struct mlx5_ifc_flow_table_context_bits flow_table_context; 4793 }; 4794 4795 struct mlx5_ifc_query_flow_table_in_bits { 4796 u8 opcode[0x10]; 4797 u8 reserved_0[0x10]; 4798 4799 u8 reserved_1[0x10]; 4800 u8 op_mod[0x10]; 4801 4802 u8 other_vport[0x1]; 4803 u8 reserved_2[0xf]; 4804 u8 vport_number[0x10]; 4805 4806 u8 reserved_3[0x20]; 4807 4808 u8 table_type[0x8]; 4809 u8 reserved_4[0x18]; 4810 4811 u8 reserved_5[0x8]; 4812 u8 table_id[0x18]; 4813 4814 u8 reserved_6[0x140]; 4815 }; 4816 4817 struct mlx5_ifc_query_fte_out_bits { 4818 u8 status[0x8]; 4819 u8 reserved_0[0x18]; 4820 4821 u8 syndrome[0x20]; 4822 4823 u8 reserved_1[0x1c0]; 4824 4825 struct mlx5_ifc_flow_context_bits flow_context; 4826 }; 4827 4828 struct mlx5_ifc_query_fte_in_bits { 4829 u8 opcode[0x10]; 4830 u8 reserved_0[0x10]; 4831 4832 u8 reserved_1[0x10]; 4833 u8 op_mod[0x10]; 4834 4835 u8 other_vport[0x1]; 4836 u8 reserved_2[0xf]; 4837 u8 vport_number[0x10]; 4838 4839 u8 reserved_3[0x20]; 4840 4841 u8 table_type[0x8]; 4842 u8 reserved_4[0x18]; 4843 4844 u8 reserved_5[0x8]; 4845 u8 table_id[0x18]; 4846 4847 u8 reserved_6[0x40]; 4848 4849 u8 flow_index[0x20]; 4850 4851 u8 reserved_7[0xe0]; 4852 }; 4853 4854 enum { 4855 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4856 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4857 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4858 }; 4859 4860 struct mlx5_ifc_query_flow_group_out_bits { 4861 u8 status[0x8]; 4862 u8 reserved_0[0x18]; 4863 4864 u8 syndrome[0x20]; 4865 4866 u8 reserved_1[0xa0]; 4867 4868 u8 start_flow_index[0x20]; 4869 4870 u8 reserved_2[0x20]; 4871 4872 u8 end_flow_index[0x20]; 4873 4874 u8 reserved_3[0xa0]; 4875 4876 u8 reserved_4[0x18]; 4877 u8 match_criteria_enable[0x8]; 4878 4879 struct mlx5_ifc_fte_match_param_bits match_criteria; 4880 4881 u8 reserved_5[0xe00]; 4882 }; 4883 4884 struct mlx5_ifc_query_flow_group_in_bits { 4885 u8 opcode[0x10]; 4886 u8 reserved_0[0x10]; 4887 4888 u8 reserved_1[0x10]; 4889 u8 op_mod[0x10]; 4890 4891 u8 other_vport[0x1]; 4892 u8 reserved_2[0xf]; 4893 u8 vport_number[0x10]; 4894 4895 u8 reserved_3[0x20]; 4896 4897 u8 table_type[0x8]; 4898 u8 reserved_4[0x18]; 4899 4900 u8 reserved_5[0x8]; 4901 u8 table_id[0x18]; 4902 4903 u8 group_id[0x20]; 4904 4905 u8 reserved_6[0x120]; 4906 }; 4907 4908 struct mlx5_ifc_query_flow_counter_out_bits { 4909 u8 status[0x8]; 4910 u8 reserved_at_8[0x18]; 4911 4912 u8 syndrome[0x20]; 4913 4914 u8 reserved_at_40[0x40]; 4915 4916 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4917 }; 4918 4919 struct mlx5_ifc_query_flow_counter_in_bits { 4920 u8 opcode[0x10]; 4921 u8 reserved_at_10[0x10]; 4922 4923 u8 reserved_at_20[0x10]; 4924 u8 op_mod[0x10]; 4925 4926 u8 reserved_at_40[0x80]; 4927 4928 u8 clear[0x1]; 4929 u8 reserved_at_c1[0xf]; 4930 u8 num_of_counters[0x10]; 4931 4932 u8 reserved_at_e0[0x10]; 4933 u8 flow_counter_id[0x10]; 4934 }; 4935 4936 struct mlx5_ifc_query_esw_vport_context_out_bits { 4937 u8 status[0x8]; 4938 u8 reserved_0[0x18]; 4939 4940 u8 syndrome[0x20]; 4941 4942 u8 reserved_1[0x40]; 4943 4944 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4945 }; 4946 4947 struct mlx5_ifc_query_esw_vport_context_in_bits { 4948 u8 opcode[0x10]; 4949 u8 reserved_0[0x10]; 4950 4951 u8 reserved_1[0x10]; 4952 u8 op_mod[0x10]; 4953 4954 u8 other_vport[0x1]; 4955 u8 reserved_2[0xf]; 4956 u8 vport_number[0x10]; 4957 4958 u8 reserved_3[0x20]; 4959 }; 4960 4961 struct mlx5_ifc_query_eq_out_bits { 4962 u8 status[0x8]; 4963 u8 reserved_0[0x18]; 4964 4965 u8 syndrome[0x20]; 4966 4967 u8 reserved_1[0x40]; 4968 4969 struct mlx5_ifc_eqc_bits eq_context_entry; 4970 4971 u8 reserved_2[0x40]; 4972 4973 u8 event_bitmask[0x40]; 4974 4975 u8 reserved_3[0x580]; 4976 4977 u8 pas[0][0x40]; 4978 }; 4979 4980 struct mlx5_ifc_query_eq_in_bits { 4981 u8 opcode[0x10]; 4982 u8 reserved_0[0x10]; 4983 4984 u8 reserved_1[0x10]; 4985 u8 op_mod[0x10]; 4986 4987 u8 reserved_2[0x18]; 4988 u8 eq_number[0x8]; 4989 4990 u8 reserved_3[0x20]; 4991 }; 4992 4993 struct mlx5_ifc_query_dct_out_bits { 4994 u8 status[0x8]; 4995 u8 reserved_0[0x18]; 4996 4997 u8 syndrome[0x20]; 4998 4999 u8 reserved_1[0x40]; 5000 5001 struct mlx5_ifc_dctc_bits dct_context_entry; 5002 5003 u8 reserved_2[0x180]; 5004 }; 5005 5006 struct mlx5_ifc_query_dct_in_bits { 5007 u8 opcode[0x10]; 5008 u8 reserved_0[0x10]; 5009 5010 u8 reserved_1[0x10]; 5011 u8 op_mod[0x10]; 5012 5013 u8 reserved_2[0x8]; 5014 u8 dctn[0x18]; 5015 5016 u8 reserved_3[0x20]; 5017 }; 5018 5019 struct mlx5_ifc_query_dc_cnak_trace_out_bits { 5020 u8 status[0x8]; 5021 u8 reserved_0[0x18]; 5022 5023 u8 syndrome[0x20]; 5024 5025 u8 enable[0x1]; 5026 u8 reserved_1[0x1f]; 5027 5028 u8 reserved_2[0x160]; 5029 5030 struct mlx5_ifc_cmd_pas_bits pas; 5031 }; 5032 5033 struct mlx5_ifc_query_dc_cnak_trace_in_bits { 5034 u8 opcode[0x10]; 5035 u8 reserved_0[0x10]; 5036 5037 u8 reserved_1[0x10]; 5038 u8 op_mod[0x10]; 5039 5040 u8 reserved_2[0x40]; 5041 }; 5042 5043 struct mlx5_ifc_query_cq_out_bits { 5044 u8 status[0x8]; 5045 u8 reserved_0[0x18]; 5046 5047 u8 syndrome[0x20]; 5048 5049 u8 reserved_1[0x40]; 5050 5051 struct mlx5_ifc_cqc_bits cq_context; 5052 5053 u8 reserved_2[0x600]; 5054 5055 u8 pas[0][0x40]; 5056 }; 5057 5058 struct mlx5_ifc_query_cq_in_bits { 5059 u8 opcode[0x10]; 5060 u8 reserved_0[0x10]; 5061 5062 u8 reserved_1[0x10]; 5063 u8 op_mod[0x10]; 5064 5065 u8 reserved_2[0x8]; 5066 u8 cqn[0x18]; 5067 5068 u8 reserved_3[0x20]; 5069 }; 5070 5071 struct mlx5_ifc_query_cong_status_out_bits { 5072 u8 status[0x8]; 5073 u8 reserved_0[0x18]; 5074 5075 u8 syndrome[0x20]; 5076 5077 u8 reserved_1[0x20]; 5078 5079 u8 enable[0x1]; 5080 u8 tag_enable[0x1]; 5081 u8 reserved_2[0x1e]; 5082 }; 5083 5084 struct mlx5_ifc_query_cong_status_in_bits { 5085 u8 opcode[0x10]; 5086 u8 reserved_0[0x10]; 5087 5088 u8 reserved_1[0x10]; 5089 u8 op_mod[0x10]; 5090 5091 u8 reserved_2[0x18]; 5092 u8 priority[0x4]; 5093 u8 cong_protocol[0x4]; 5094 5095 u8 reserved_3[0x20]; 5096 }; 5097 5098 struct mlx5_ifc_query_cong_statistics_out_bits { 5099 u8 status[0x8]; 5100 u8 reserved_0[0x18]; 5101 5102 u8 syndrome[0x20]; 5103 5104 u8 reserved_1[0x40]; 5105 5106 u8 rp_cur_flows[0x20]; 5107 5108 u8 sum_flows[0x20]; 5109 5110 u8 rp_cnp_ignored_high[0x20]; 5111 5112 u8 rp_cnp_ignored_low[0x20]; 5113 5114 u8 rp_cnp_handled_high[0x20]; 5115 5116 u8 rp_cnp_handled_low[0x20]; 5117 5118 u8 reserved_2[0x100]; 5119 5120 u8 time_stamp_high[0x20]; 5121 5122 u8 time_stamp_low[0x20]; 5123 5124 u8 accumulators_period[0x20]; 5125 5126 u8 np_ecn_marked_roce_packets_high[0x20]; 5127 5128 u8 np_ecn_marked_roce_packets_low[0x20]; 5129 5130 u8 np_cnp_sent_high[0x20]; 5131 5132 u8 np_cnp_sent_low[0x20]; 5133 5134 u8 reserved_3[0x560]; 5135 }; 5136 5137 struct mlx5_ifc_query_cong_statistics_in_bits { 5138 u8 opcode[0x10]; 5139 u8 reserved_0[0x10]; 5140 5141 u8 reserved_1[0x10]; 5142 u8 op_mod[0x10]; 5143 5144 u8 clear[0x1]; 5145 u8 reserved_2[0x1f]; 5146 5147 u8 reserved_3[0x20]; 5148 }; 5149 5150 struct mlx5_ifc_query_cong_params_out_bits { 5151 u8 status[0x8]; 5152 u8 reserved_0[0x18]; 5153 5154 u8 syndrome[0x20]; 5155 5156 u8 reserved_1[0x40]; 5157 5158 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5159 }; 5160 5161 struct mlx5_ifc_query_cong_params_in_bits { 5162 u8 opcode[0x10]; 5163 u8 reserved_0[0x10]; 5164 5165 u8 reserved_1[0x10]; 5166 u8 op_mod[0x10]; 5167 5168 u8 reserved_2[0x1c]; 5169 u8 cong_protocol[0x4]; 5170 5171 u8 reserved_3[0x20]; 5172 }; 5173 5174 struct mlx5_ifc_query_burst_size_out_bits { 5175 u8 status[0x8]; 5176 u8 reserved_0[0x18]; 5177 5178 u8 syndrome[0x20]; 5179 5180 u8 reserved_1[0x20]; 5181 5182 u8 reserved_2[0x9]; 5183 u8 device_burst_size[0x17]; 5184 }; 5185 5186 struct mlx5_ifc_query_burst_size_in_bits { 5187 u8 opcode[0x10]; 5188 u8 reserved_0[0x10]; 5189 5190 u8 reserved_1[0x10]; 5191 u8 op_mod[0x10]; 5192 5193 u8 reserved_2[0x40]; 5194 }; 5195 5196 struct mlx5_ifc_query_adapter_out_bits { 5197 u8 status[0x8]; 5198 u8 reserved_0[0x18]; 5199 5200 u8 syndrome[0x20]; 5201 5202 u8 reserved_1[0x40]; 5203 5204 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5205 }; 5206 5207 struct mlx5_ifc_query_adapter_in_bits { 5208 u8 opcode[0x10]; 5209 u8 reserved_0[0x10]; 5210 5211 u8 reserved_1[0x10]; 5212 u8 op_mod[0x10]; 5213 5214 u8 reserved_2[0x40]; 5215 }; 5216 5217 struct mlx5_ifc_qp_2rst_out_bits { 5218 u8 status[0x8]; 5219 u8 reserved_0[0x18]; 5220 5221 u8 syndrome[0x20]; 5222 5223 u8 reserved_1[0x40]; 5224 }; 5225 5226 struct mlx5_ifc_qp_2rst_in_bits { 5227 u8 opcode[0x10]; 5228 u8 reserved_0[0x10]; 5229 5230 u8 reserved_1[0x10]; 5231 u8 op_mod[0x10]; 5232 5233 u8 reserved_2[0x8]; 5234 u8 qpn[0x18]; 5235 5236 u8 reserved_3[0x20]; 5237 }; 5238 5239 struct mlx5_ifc_qp_2err_out_bits { 5240 u8 status[0x8]; 5241 u8 reserved_0[0x18]; 5242 5243 u8 syndrome[0x20]; 5244 5245 u8 reserved_1[0x40]; 5246 }; 5247 5248 struct mlx5_ifc_qp_2err_in_bits { 5249 u8 opcode[0x10]; 5250 u8 reserved_0[0x10]; 5251 5252 u8 reserved_1[0x10]; 5253 u8 op_mod[0x10]; 5254 5255 u8 reserved_2[0x8]; 5256 u8 qpn[0x18]; 5257 5258 u8 reserved_3[0x20]; 5259 }; 5260 5261 struct mlx5_ifc_para_vport_element_bits { 5262 u8 reserved_at_0[0xc]; 5263 u8 traffic_class[0x4]; 5264 u8 qos_para_vport_number[0x10]; 5265 }; 5266 5267 struct mlx5_ifc_page_fault_resume_out_bits { 5268 u8 status[0x8]; 5269 u8 reserved_0[0x18]; 5270 5271 u8 syndrome[0x20]; 5272 5273 u8 reserved_1[0x40]; 5274 }; 5275 5276 struct mlx5_ifc_page_fault_resume_in_bits { 5277 u8 opcode[0x10]; 5278 u8 reserved_0[0x10]; 5279 5280 u8 reserved_1[0x10]; 5281 u8 op_mod[0x10]; 5282 5283 u8 error[0x1]; 5284 u8 reserved_2[0x4]; 5285 u8 rdma[0x1]; 5286 u8 read_write[0x1]; 5287 u8 req_res[0x1]; 5288 u8 qpn[0x18]; 5289 5290 u8 reserved_3[0x20]; 5291 }; 5292 5293 struct mlx5_ifc_nop_out_bits { 5294 u8 status[0x8]; 5295 u8 reserved_0[0x18]; 5296 5297 u8 syndrome[0x20]; 5298 5299 u8 reserved_1[0x40]; 5300 }; 5301 5302 struct mlx5_ifc_nop_in_bits { 5303 u8 opcode[0x10]; 5304 u8 reserved_0[0x10]; 5305 5306 u8 reserved_1[0x10]; 5307 u8 op_mod[0x10]; 5308 5309 u8 reserved_2[0x40]; 5310 }; 5311 5312 struct mlx5_ifc_modify_vport_state_out_bits { 5313 u8 status[0x8]; 5314 u8 reserved_0[0x18]; 5315 5316 u8 syndrome[0x20]; 5317 5318 u8 reserved_1[0x40]; 5319 }; 5320 5321 enum { 5322 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5323 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5324 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5325 }; 5326 5327 enum { 5328 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5329 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5330 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5331 }; 5332 5333 struct mlx5_ifc_modify_vport_state_in_bits { 5334 u8 opcode[0x10]; 5335 u8 reserved_0[0x10]; 5336 5337 u8 reserved_1[0x10]; 5338 u8 op_mod[0x10]; 5339 5340 u8 other_vport[0x1]; 5341 u8 reserved_2[0xf]; 5342 u8 vport_number[0x10]; 5343 5344 u8 reserved_3[0x18]; 5345 u8 admin_state[0x4]; 5346 u8 reserved_4[0x4]; 5347 }; 5348 5349 struct mlx5_ifc_modify_tis_out_bits { 5350 u8 status[0x8]; 5351 u8 reserved_0[0x18]; 5352 5353 u8 syndrome[0x20]; 5354 5355 u8 reserved_1[0x40]; 5356 }; 5357 5358 struct mlx5_ifc_modify_tis_bitmask_bits { 5359 u8 reserved_at_0[0x20]; 5360 5361 u8 reserved_at_20[0x1d]; 5362 u8 lag_tx_port_affinity[0x1]; 5363 u8 strict_lag_tx_port_affinity[0x1]; 5364 u8 prio[0x1]; 5365 }; 5366 5367 struct mlx5_ifc_modify_tis_in_bits { 5368 u8 opcode[0x10]; 5369 u8 reserved_0[0x10]; 5370 5371 u8 reserved_1[0x10]; 5372 u8 op_mod[0x10]; 5373 5374 u8 reserved_2[0x8]; 5375 u8 tisn[0x18]; 5376 5377 u8 reserved_3[0x20]; 5378 5379 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5380 5381 u8 reserved_4[0x40]; 5382 5383 struct mlx5_ifc_tisc_bits ctx; 5384 }; 5385 5386 struct mlx5_ifc_modify_tir_out_bits { 5387 u8 status[0x8]; 5388 u8 reserved_0[0x18]; 5389 5390 u8 syndrome[0x20]; 5391 5392 u8 reserved_1[0x40]; 5393 }; 5394 5395 enum 5396 { 5397 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5398 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5399 }; 5400 5401 struct mlx5_ifc_modify_tir_in_bits { 5402 u8 opcode[0x10]; 5403 u8 reserved_0[0x10]; 5404 5405 u8 reserved_1[0x10]; 5406 u8 op_mod[0x10]; 5407 5408 u8 reserved_2[0x8]; 5409 u8 tirn[0x18]; 5410 5411 u8 reserved_3[0x20]; 5412 5413 u8 modify_bitmask[0x40]; 5414 5415 u8 reserved_4[0x40]; 5416 5417 struct mlx5_ifc_tirc_bits tir_context; 5418 }; 5419 5420 struct mlx5_ifc_modify_sq_out_bits { 5421 u8 status[0x8]; 5422 u8 reserved_0[0x18]; 5423 5424 u8 syndrome[0x20]; 5425 5426 u8 reserved_1[0x40]; 5427 }; 5428 5429 struct mlx5_ifc_modify_sq_in_bits { 5430 u8 opcode[0x10]; 5431 u8 reserved_0[0x10]; 5432 5433 u8 reserved_1[0x10]; 5434 u8 op_mod[0x10]; 5435 5436 u8 sq_state[0x4]; 5437 u8 reserved_2[0x4]; 5438 u8 sqn[0x18]; 5439 5440 u8 reserved_3[0x20]; 5441 5442 u8 modify_bitmask[0x40]; 5443 5444 u8 reserved_4[0x40]; 5445 5446 struct mlx5_ifc_sqc_bits ctx; 5447 }; 5448 5449 struct mlx5_ifc_modify_scheduling_element_out_bits { 5450 u8 status[0x8]; 5451 u8 reserved_at_8[0x18]; 5452 5453 u8 syndrome[0x20]; 5454 5455 u8 reserved_at_40[0x1c0]; 5456 }; 5457 5458 enum { 5459 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5460 }; 5461 5462 enum { 5463 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5464 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5465 }; 5466 5467 struct mlx5_ifc_modify_scheduling_element_in_bits { 5468 u8 opcode[0x10]; 5469 u8 reserved_at_10[0x10]; 5470 5471 u8 reserved_at_20[0x10]; 5472 u8 op_mod[0x10]; 5473 5474 u8 scheduling_hierarchy[0x8]; 5475 u8 reserved_at_48[0x18]; 5476 5477 u8 scheduling_element_id[0x20]; 5478 5479 u8 reserved_at_80[0x20]; 5480 5481 u8 modify_bitmask[0x20]; 5482 5483 u8 reserved_at_c0[0x40]; 5484 5485 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5486 5487 u8 reserved_at_300[0x100]; 5488 }; 5489 5490 struct mlx5_ifc_modify_rqt_out_bits { 5491 u8 status[0x8]; 5492 u8 reserved_0[0x18]; 5493 5494 u8 syndrome[0x20]; 5495 5496 u8 reserved_1[0x40]; 5497 }; 5498 5499 struct mlx5_ifc_modify_rqt_in_bits { 5500 u8 opcode[0x10]; 5501 u8 reserved_0[0x10]; 5502 5503 u8 reserved_1[0x10]; 5504 u8 op_mod[0x10]; 5505 5506 u8 reserved_2[0x8]; 5507 u8 rqtn[0x18]; 5508 5509 u8 reserved_3[0x20]; 5510 5511 u8 modify_bitmask[0x40]; 5512 5513 u8 reserved_4[0x40]; 5514 5515 struct mlx5_ifc_rqtc_bits ctx; 5516 }; 5517 5518 struct mlx5_ifc_modify_rq_out_bits { 5519 u8 status[0x8]; 5520 u8 reserved_0[0x18]; 5521 5522 u8 syndrome[0x20]; 5523 5524 u8 reserved_1[0x40]; 5525 }; 5526 5527 enum { 5528 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5529 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5530 }; 5531 5532 struct mlx5_ifc_modify_rq_in_bits { 5533 u8 opcode[0x10]; 5534 u8 reserved_0[0x10]; 5535 5536 u8 reserved_1[0x10]; 5537 u8 op_mod[0x10]; 5538 5539 u8 rq_state[0x4]; 5540 u8 reserved_2[0x4]; 5541 u8 rqn[0x18]; 5542 5543 u8 reserved_3[0x20]; 5544 5545 u8 modify_bitmask[0x40]; 5546 5547 u8 reserved_4[0x40]; 5548 5549 struct mlx5_ifc_rqc_bits ctx; 5550 }; 5551 5552 struct mlx5_ifc_modify_rmp_out_bits { 5553 u8 status[0x8]; 5554 u8 reserved_0[0x18]; 5555 5556 u8 syndrome[0x20]; 5557 5558 u8 reserved_1[0x40]; 5559 }; 5560 5561 struct mlx5_ifc_rmp_bitmask_bits { 5562 u8 reserved[0x20]; 5563 5564 u8 reserved1[0x1f]; 5565 u8 lwm[0x1]; 5566 }; 5567 5568 struct mlx5_ifc_modify_rmp_in_bits { 5569 u8 opcode[0x10]; 5570 u8 reserved_0[0x10]; 5571 5572 u8 reserved_1[0x10]; 5573 u8 op_mod[0x10]; 5574 5575 u8 rmp_state[0x4]; 5576 u8 reserved_2[0x4]; 5577 u8 rmpn[0x18]; 5578 5579 u8 reserved_3[0x20]; 5580 5581 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5582 5583 u8 reserved_4[0x40]; 5584 5585 struct mlx5_ifc_rmpc_bits ctx; 5586 }; 5587 5588 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5589 u8 status[0x8]; 5590 u8 reserved_0[0x18]; 5591 5592 u8 syndrome[0x20]; 5593 5594 u8 reserved_1[0x40]; 5595 }; 5596 5597 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5598 u8 reserved_0[0x14]; 5599 u8 disable_uc_local_lb[0x1]; 5600 u8 disable_mc_local_lb[0x1]; 5601 u8 node_guid[0x1]; 5602 u8 port_guid[0x1]; 5603 u8 min_wqe_inline_mode[0x1]; 5604 u8 mtu[0x1]; 5605 u8 change_event[0x1]; 5606 u8 promisc[0x1]; 5607 u8 permanent_address[0x1]; 5608 u8 addresses_list[0x1]; 5609 u8 roce_en[0x1]; 5610 u8 reserved_1[0x1]; 5611 }; 5612 5613 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5614 u8 opcode[0x10]; 5615 u8 reserved_0[0x10]; 5616 5617 u8 reserved_1[0x10]; 5618 u8 op_mod[0x10]; 5619 5620 u8 other_vport[0x1]; 5621 u8 reserved_2[0xf]; 5622 u8 vport_number[0x10]; 5623 5624 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5625 5626 u8 reserved_3[0x780]; 5627 5628 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5629 }; 5630 5631 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5632 u8 status[0x8]; 5633 u8 reserved_0[0x18]; 5634 5635 u8 syndrome[0x20]; 5636 5637 u8 reserved_1[0x40]; 5638 }; 5639 5640 struct mlx5_ifc_grh_bits { 5641 u8 ip_version[4]; 5642 u8 traffic_class[8]; 5643 u8 flow_label[20]; 5644 u8 payload_length[16]; 5645 u8 next_header[8]; 5646 u8 hop_limit[8]; 5647 u8 sgid[128]; 5648 u8 dgid[128]; 5649 }; 5650 5651 struct mlx5_ifc_bth_bits { 5652 u8 opcode[8]; 5653 u8 se[1]; 5654 u8 migreq[1]; 5655 u8 pad_count[2]; 5656 u8 tver[4]; 5657 u8 p_key[16]; 5658 u8 reserved8[8]; 5659 u8 dest_qp[24]; 5660 u8 ack_req[1]; 5661 u8 reserved7[7]; 5662 u8 psn[24]; 5663 }; 5664 5665 struct mlx5_ifc_aeth_bits { 5666 u8 syndrome[8]; 5667 u8 msn[24]; 5668 }; 5669 5670 struct mlx5_ifc_dceth_bits { 5671 u8 reserved0[8]; 5672 u8 session_id[24]; 5673 u8 reserved1[8]; 5674 u8 dci_dct[24]; 5675 }; 5676 5677 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5678 u8 opcode[0x10]; 5679 u8 reserved_0[0x10]; 5680 5681 u8 reserved_1[0x10]; 5682 u8 op_mod[0x10]; 5683 5684 u8 other_vport[0x1]; 5685 u8 reserved_2[0xb]; 5686 u8 port_num[0x4]; 5687 u8 vport_number[0x10]; 5688 5689 u8 reserved_3[0x20]; 5690 5691 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5692 }; 5693 5694 struct mlx5_ifc_modify_flow_table_out_bits { 5695 u8 status[0x8]; 5696 u8 reserved_at_8[0x18]; 5697 5698 u8 syndrome[0x20]; 5699 5700 u8 reserved_at_40[0x40]; 5701 }; 5702 5703 enum { 5704 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 5705 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 5706 }; 5707 5708 struct mlx5_ifc_modify_flow_table_in_bits { 5709 u8 opcode[0x10]; 5710 u8 reserved_at_10[0x10]; 5711 5712 u8 reserved_at_20[0x10]; 5713 u8 op_mod[0x10]; 5714 5715 u8 other_vport[0x1]; 5716 u8 reserved_at_41[0xf]; 5717 u8 vport_number[0x10]; 5718 5719 u8 reserved_at_60[0x10]; 5720 u8 modify_field_select[0x10]; 5721 5722 u8 table_type[0x8]; 5723 u8 reserved_at_88[0x18]; 5724 5725 u8 reserved_at_a0[0x8]; 5726 u8 table_id[0x18]; 5727 5728 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5729 }; 5730 5731 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5732 u8 status[0x8]; 5733 u8 reserved_0[0x18]; 5734 5735 u8 syndrome[0x20]; 5736 5737 u8 reserved_1[0x40]; 5738 }; 5739 5740 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5741 u8 reserved[0x1c]; 5742 u8 vport_cvlan_insert[0x1]; 5743 u8 vport_svlan_insert[0x1]; 5744 u8 vport_cvlan_strip[0x1]; 5745 u8 vport_svlan_strip[0x1]; 5746 }; 5747 5748 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5749 u8 opcode[0x10]; 5750 u8 reserved_0[0x10]; 5751 5752 u8 reserved_1[0x10]; 5753 u8 op_mod[0x10]; 5754 5755 u8 other_vport[0x1]; 5756 u8 reserved_2[0xf]; 5757 u8 vport_number[0x10]; 5758 5759 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5760 5761 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5762 }; 5763 5764 struct mlx5_ifc_modify_cq_out_bits { 5765 u8 status[0x8]; 5766 u8 reserved_0[0x18]; 5767 5768 u8 syndrome[0x20]; 5769 5770 u8 reserved_1[0x40]; 5771 }; 5772 5773 enum { 5774 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5775 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5776 }; 5777 5778 struct mlx5_ifc_modify_cq_in_bits { 5779 u8 opcode[0x10]; 5780 u8 reserved_0[0x10]; 5781 5782 u8 reserved_1[0x10]; 5783 u8 op_mod[0x10]; 5784 5785 u8 reserved_2[0x8]; 5786 u8 cqn[0x18]; 5787 5788 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5789 5790 struct mlx5_ifc_cqc_bits cq_context; 5791 5792 u8 reserved_3[0x600]; 5793 5794 u8 pas[0][0x40]; 5795 }; 5796 5797 struct mlx5_ifc_modify_cong_status_out_bits { 5798 u8 status[0x8]; 5799 u8 reserved_0[0x18]; 5800 5801 u8 syndrome[0x20]; 5802 5803 u8 reserved_1[0x40]; 5804 }; 5805 5806 struct mlx5_ifc_modify_cong_status_in_bits { 5807 u8 opcode[0x10]; 5808 u8 reserved_0[0x10]; 5809 5810 u8 reserved_1[0x10]; 5811 u8 op_mod[0x10]; 5812 5813 u8 reserved_2[0x18]; 5814 u8 priority[0x4]; 5815 u8 cong_protocol[0x4]; 5816 5817 u8 enable[0x1]; 5818 u8 tag_enable[0x1]; 5819 u8 reserved_3[0x1e]; 5820 }; 5821 5822 struct mlx5_ifc_modify_cong_params_out_bits { 5823 u8 status[0x8]; 5824 u8 reserved_0[0x18]; 5825 5826 u8 syndrome[0x20]; 5827 5828 u8 reserved_1[0x40]; 5829 }; 5830 5831 struct mlx5_ifc_modify_cong_params_in_bits { 5832 u8 opcode[0x10]; 5833 u8 reserved_0[0x10]; 5834 5835 u8 reserved_1[0x10]; 5836 u8 op_mod[0x10]; 5837 5838 u8 reserved_2[0x1c]; 5839 u8 cong_protocol[0x4]; 5840 5841 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5842 5843 u8 reserved_3[0x80]; 5844 5845 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5846 }; 5847 5848 struct mlx5_ifc_manage_pages_out_bits { 5849 u8 status[0x8]; 5850 u8 reserved_0[0x18]; 5851 5852 u8 syndrome[0x20]; 5853 5854 u8 output_num_entries[0x20]; 5855 5856 u8 reserved_1[0x20]; 5857 5858 u8 pas[0][0x40]; 5859 }; 5860 5861 enum { 5862 MLX5_PAGES_CANT_GIVE = 0x0, 5863 MLX5_PAGES_GIVE = 0x1, 5864 MLX5_PAGES_TAKE = 0x2, 5865 }; 5866 5867 struct mlx5_ifc_manage_pages_in_bits { 5868 u8 opcode[0x10]; 5869 u8 reserved_0[0x10]; 5870 5871 u8 reserved_1[0x10]; 5872 u8 op_mod[0x10]; 5873 5874 u8 reserved_2[0x10]; 5875 u8 function_id[0x10]; 5876 5877 u8 input_num_entries[0x20]; 5878 5879 u8 pas[0][0x40]; 5880 }; 5881 5882 struct mlx5_ifc_mad_ifc_out_bits { 5883 u8 status[0x8]; 5884 u8 reserved_0[0x18]; 5885 5886 u8 syndrome[0x20]; 5887 5888 u8 reserved_1[0x40]; 5889 5890 u8 response_mad_packet[256][0x8]; 5891 }; 5892 5893 struct mlx5_ifc_mad_ifc_in_bits { 5894 u8 opcode[0x10]; 5895 u8 reserved_0[0x10]; 5896 5897 u8 reserved_1[0x10]; 5898 u8 op_mod[0x10]; 5899 5900 u8 remote_lid[0x10]; 5901 u8 reserved_2[0x8]; 5902 u8 port[0x8]; 5903 5904 u8 reserved_3[0x20]; 5905 5906 u8 mad[256][0x8]; 5907 }; 5908 5909 struct mlx5_ifc_init_hca_out_bits { 5910 u8 status[0x8]; 5911 u8 reserved_0[0x18]; 5912 5913 u8 syndrome[0x20]; 5914 5915 u8 reserved_1[0x40]; 5916 }; 5917 5918 enum { 5919 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 5920 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 5921 }; 5922 5923 struct mlx5_ifc_init_hca_in_bits { 5924 u8 opcode[0x10]; 5925 u8 reserved_0[0x10]; 5926 5927 u8 reserved_1[0x10]; 5928 u8 op_mod[0x10]; 5929 5930 u8 reserved_2[0x40]; 5931 }; 5932 5933 struct mlx5_ifc_init2rtr_qp_out_bits { 5934 u8 status[0x8]; 5935 u8 reserved_0[0x18]; 5936 5937 u8 syndrome[0x20]; 5938 5939 u8 reserved_1[0x40]; 5940 }; 5941 5942 struct mlx5_ifc_init2rtr_qp_in_bits { 5943 u8 opcode[0x10]; 5944 u8 reserved_0[0x10]; 5945 5946 u8 reserved_1[0x10]; 5947 u8 op_mod[0x10]; 5948 5949 u8 reserved_2[0x8]; 5950 u8 qpn[0x18]; 5951 5952 u8 reserved_3[0x20]; 5953 5954 u8 opt_param_mask[0x20]; 5955 5956 u8 reserved_4[0x20]; 5957 5958 struct mlx5_ifc_qpc_bits qpc; 5959 5960 u8 reserved_5[0x80]; 5961 }; 5962 5963 struct mlx5_ifc_init2init_qp_out_bits { 5964 u8 status[0x8]; 5965 u8 reserved_0[0x18]; 5966 5967 u8 syndrome[0x20]; 5968 5969 u8 reserved_1[0x40]; 5970 }; 5971 5972 struct mlx5_ifc_init2init_qp_in_bits { 5973 u8 opcode[0x10]; 5974 u8 reserved_0[0x10]; 5975 5976 u8 reserved_1[0x10]; 5977 u8 op_mod[0x10]; 5978 5979 u8 reserved_2[0x8]; 5980 u8 qpn[0x18]; 5981 5982 u8 reserved_3[0x20]; 5983 5984 u8 opt_param_mask[0x20]; 5985 5986 u8 reserved_4[0x20]; 5987 5988 struct mlx5_ifc_qpc_bits qpc; 5989 5990 u8 reserved_5[0x80]; 5991 }; 5992 5993 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5994 u8 status[0x8]; 5995 u8 reserved_0[0x18]; 5996 5997 u8 syndrome[0x20]; 5998 5999 u8 reserved_1[0x40]; 6000 6001 u8 packet_headers_log[128][0x8]; 6002 6003 u8 packet_syndrome[64][0x8]; 6004 }; 6005 6006 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6007 u8 opcode[0x10]; 6008 u8 reserved_0[0x10]; 6009 6010 u8 reserved_1[0x10]; 6011 u8 op_mod[0x10]; 6012 6013 u8 reserved_2[0x40]; 6014 }; 6015 6016 struct mlx5_ifc_encryption_key_obj_bits { 6017 u8 modify_field_select[0x40]; 6018 6019 u8 reserved_at_40[0x14]; 6020 u8 key_size[0x4]; 6021 u8 reserved_at_58[0x4]; 6022 u8 key_type[0x4]; 6023 6024 u8 reserved_at_60[0x8]; 6025 u8 pd[0x18]; 6026 6027 u8 reserved_at_80[0x180]; 6028 6029 u8 key[8][0x20]; 6030 6031 u8 reserved_at_300[0x500]; 6032 }; 6033 6034 struct mlx5_ifc_gen_eqe_in_bits { 6035 u8 opcode[0x10]; 6036 u8 reserved_0[0x10]; 6037 6038 u8 reserved_1[0x10]; 6039 u8 op_mod[0x10]; 6040 6041 u8 reserved_2[0x18]; 6042 u8 eq_number[0x8]; 6043 6044 u8 reserved_3[0x20]; 6045 6046 u8 eqe[64][0x8]; 6047 }; 6048 6049 struct mlx5_ifc_gen_eq_out_bits { 6050 u8 status[0x8]; 6051 u8 reserved_0[0x18]; 6052 6053 u8 syndrome[0x20]; 6054 6055 u8 reserved_1[0x40]; 6056 }; 6057 6058 struct mlx5_ifc_enable_hca_out_bits { 6059 u8 status[0x8]; 6060 u8 reserved_0[0x18]; 6061 6062 u8 syndrome[0x20]; 6063 6064 u8 reserved_1[0x20]; 6065 }; 6066 6067 struct mlx5_ifc_enable_hca_in_bits { 6068 u8 opcode[0x10]; 6069 u8 reserved_0[0x10]; 6070 6071 u8 reserved_1[0x10]; 6072 u8 op_mod[0x10]; 6073 6074 u8 reserved_2[0x10]; 6075 u8 function_id[0x10]; 6076 6077 u8 reserved_3[0x20]; 6078 }; 6079 6080 struct mlx5_ifc_drain_dct_out_bits { 6081 u8 status[0x8]; 6082 u8 reserved_0[0x18]; 6083 6084 u8 syndrome[0x20]; 6085 6086 u8 reserved_1[0x40]; 6087 }; 6088 6089 struct mlx5_ifc_drain_dct_in_bits { 6090 u8 opcode[0x10]; 6091 u8 reserved_0[0x10]; 6092 6093 u8 reserved_1[0x10]; 6094 u8 op_mod[0x10]; 6095 6096 u8 reserved_2[0x8]; 6097 u8 dctn[0x18]; 6098 6099 u8 reserved_3[0x20]; 6100 }; 6101 6102 struct mlx5_ifc_disable_hca_out_bits { 6103 u8 status[0x8]; 6104 u8 reserved_0[0x18]; 6105 6106 u8 syndrome[0x20]; 6107 6108 u8 reserved_1[0x20]; 6109 }; 6110 6111 struct mlx5_ifc_disable_hca_in_bits { 6112 u8 opcode[0x10]; 6113 u8 reserved_0[0x10]; 6114 6115 u8 reserved_1[0x10]; 6116 u8 op_mod[0x10]; 6117 6118 u8 reserved_2[0x10]; 6119 u8 function_id[0x10]; 6120 6121 u8 reserved_3[0x20]; 6122 }; 6123 6124 struct mlx5_ifc_detach_from_mcg_out_bits { 6125 u8 status[0x8]; 6126 u8 reserved_0[0x18]; 6127 6128 u8 syndrome[0x20]; 6129 6130 u8 reserved_1[0x40]; 6131 }; 6132 6133 struct mlx5_ifc_detach_from_mcg_in_bits { 6134 u8 opcode[0x10]; 6135 u8 reserved_0[0x10]; 6136 6137 u8 reserved_1[0x10]; 6138 u8 op_mod[0x10]; 6139 6140 u8 reserved_2[0x8]; 6141 u8 qpn[0x18]; 6142 6143 u8 reserved_3[0x20]; 6144 6145 u8 multicast_gid[16][0x8]; 6146 }; 6147 6148 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6149 u8 status[0x8]; 6150 u8 reserved_0[0x18]; 6151 6152 u8 syndrome[0x20]; 6153 6154 u8 reserved_1[0x40]; 6155 }; 6156 6157 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6158 u8 opcode[0x10]; 6159 u8 reserved_0[0x10]; 6160 6161 u8 reserved_1[0x10]; 6162 u8 op_mod[0x10]; 6163 6164 u8 reserved_2[0x8]; 6165 u8 xrc_srqn[0x18]; 6166 6167 u8 reserved_3[0x20]; 6168 }; 6169 6170 struct mlx5_ifc_destroy_tis_out_bits { 6171 u8 status[0x8]; 6172 u8 reserved_0[0x18]; 6173 6174 u8 syndrome[0x20]; 6175 6176 u8 reserved_1[0x40]; 6177 }; 6178 6179 struct mlx5_ifc_destroy_tis_in_bits { 6180 u8 opcode[0x10]; 6181 u8 reserved_0[0x10]; 6182 6183 u8 reserved_1[0x10]; 6184 u8 op_mod[0x10]; 6185 6186 u8 reserved_2[0x8]; 6187 u8 tisn[0x18]; 6188 6189 u8 reserved_3[0x20]; 6190 }; 6191 6192 struct mlx5_ifc_destroy_tir_out_bits { 6193 u8 status[0x8]; 6194 u8 reserved_0[0x18]; 6195 6196 u8 syndrome[0x20]; 6197 6198 u8 reserved_1[0x40]; 6199 }; 6200 6201 struct mlx5_ifc_destroy_tir_in_bits { 6202 u8 opcode[0x10]; 6203 u8 reserved_0[0x10]; 6204 6205 u8 reserved_1[0x10]; 6206 u8 op_mod[0x10]; 6207 6208 u8 reserved_2[0x8]; 6209 u8 tirn[0x18]; 6210 6211 u8 reserved_3[0x20]; 6212 }; 6213 6214 struct mlx5_ifc_destroy_srq_out_bits { 6215 u8 status[0x8]; 6216 u8 reserved_0[0x18]; 6217 6218 u8 syndrome[0x20]; 6219 6220 u8 reserved_1[0x40]; 6221 }; 6222 6223 struct mlx5_ifc_destroy_srq_in_bits { 6224 u8 opcode[0x10]; 6225 u8 reserved_0[0x10]; 6226 6227 u8 reserved_1[0x10]; 6228 u8 op_mod[0x10]; 6229 6230 u8 reserved_2[0x8]; 6231 u8 srqn[0x18]; 6232 6233 u8 reserved_3[0x20]; 6234 }; 6235 6236 struct mlx5_ifc_destroy_sq_out_bits { 6237 u8 status[0x8]; 6238 u8 reserved_0[0x18]; 6239 6240 u8 syndrome[0x20]; 6241 6242 u8 reserved_1[0x40]; 6243 }; 6244 6245 struct mlx5_ifc_destroy_sq_in_bits { 6246 u8 opcode[0x10]; 6247 u8 reserved_0[0x10]; 6248 6249 u8 reserved_1[0x10]; 6250 u8 op_mod[0x10]; 6251 6252 u8 reserved_2[0x8]; 6253 u8 sqn[0x18]; 6254 6255 u8 reserved_3[0x20]; 6256 }; 6257 6258 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6259 u8 status[0x8]; 6260 u8 reserved_at_8[0x18]; 6261 6262 u8 syndrome[0x20]; 6263 6264 u8 reserved_at_40[0x1c0]; 6265 }; 6266 6267 enum { 6268 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6269 }; 6270 6271 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6272 u8 opcode[0x10]; 6273 u8 reserved_at_10[0x10]; 6274 6275 u8 reserved_at_20[0x10]; 6276 u8 op_mod[0x10]; 6277 6278 u8 scheduling_hierarchy[0x8]; 6279 u8 reserved_at_48[0x18]; 6280 6281 u8 scheduling_element_id[0x20]; 6282 6283 u8 reserved_at_80[0x180]; 6284 }; 6285 6286 struct mlx5_ifc_destroy_rqt_out_bits { 6287 u8 status[0x8]; 6288 u8 reserved_0[0x18]; 6289 6290 u8 syndrome[0x20]; 6291 6292 u8 reserved_1[0x40]; 6293 }; 6294 6295 struct mlx5_ifc_destroy_rqt_in_bits { 6296 u8 opcode[0x10]; 6297 u8 reserved_0[0x10]; 6298 6299 u8 reserved_1[0x10]; 6300 u8 op_mod[0x10]; 6301 6302 u8 reserved_2[0x8]; 6303 u8 rqtn[0x18]; 6304 6305 u8 reserved_3[0x20]; 6306 }; 6307 6308 struct mlx5_ifc_destroy_rq_out_bits { 6309 u8 status[0x8]; 6310 u8 reserved_0[0x18]; 6311 6312 u8 syndrome[0x20]; 6313 6314 u8 reserved_1[0x40]; 6315 }; 6316 6317 struct mlx5_ifc_destroy_rq_in_bits { 6318 u8 opcode[0x10]; 6319 u8 reserved_0[0x10]; 6320 6321 u8 reserved_1[0x10]; 6322 u8 op_mod[0x10]; 6323 6324 u8 reserved_2[0x8]; 6325 u8 rqn[0x18]; 6326 6327 u8 reserved_3[0x20]; 6328 }; 6329 6330 struct mlx5_ifc_destroy_rmp_out_bits { 6331 u8 status[0x8]; 6332 u8 reserved_0[0x18]; 6333 6334 u8 syndrome[0x20]; 6335 6336 u8 reserved_1[0x40]; 6337 }; 6338 6339 struct mlx5_ifc_destroy_rmp_in_bits { 6340 u8 opcode[0x10]; 6341 u8 reserved_0[0x10]; 6342 6343 u8 reserved_1[0x10]; 6344 u8 op_mod[0x10]; 6345 6346 u8 reserved_2[0x8]; 6347 u8 rmpn[0x18]; 6348 6349 u8 reserved_3[0x20]; 6350 }; 6351 6352 struct mlx5_ifc_destroy_qp_out_bits { 6353 u8 status[0x8]; 6354 u8 reserved_0[0x18]; 6355 6356 u8 syndrome[0x20]; 6357 6358 u8 reserved_1[0x40]; 6359 }; 6360 6361 struct mlx5_ifc_destroy_qp_in_bits { 6362 u8 opcode[0x10]; 6363 u8 reserved_0[0x10]; 6364 6365 u8 reserved_1[0x10]; 6366 u8 op_mod[0x10]; 6367 6368 u8 reserved_2[0x8]; 6369 u8 qpn[0x18]; 6370 6371 u8 reserved_3[0x20]; 6372 }; 6373 6374 struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6375 u8 status[0x8]; 6376 u8 reserved_at_8[0x18]; 6377 6378 u8 syndrome[0x20]; 6379 6380 u8 reserved_at_40[0x1c0]; 6381 }; 6382 6383 struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6384 u8 opcode[0x10]; 6385 u8 reserved_at_10[0x10]; 6386 6387 u8 reserved_at_20[0x10]; 6388 u8 op_mod[0x10]; 6389 6390 u8 reserved_at_40[0x20]; 6391 6392 u8 reserved_at_60[0x10]; 6393 u8 qos_para_vport_number[0x10]; 6394 6395 u8 reserved_at_80[0x180]; 6396 }; 6397 6398 struct mlx5_ifc_destroy_psv_out_bits { 6399 u8 status[0x8]; 6400 u8 reserved_0[0x18]; 6401 6402 u8 syndrome[0x20]; 6403 6404 u8 reserved_1[0x40]; 6405 }; 6406 6407 struct mlx5_ifc_destroy_psv_in_bits { 6408 u8 opcode[0x10]; 6409 u8 reserved_0[0x10]; 6410 6411 u8 reserved_1[0x10]; 6412 u8 op_mod[0x10]; 6413 6414 u8 reserved_2[0x8]; 6415 u8 psvn[0x18]; 6416 6417 u8 reserved_3[0x20]; 6418 }; 6419 6420 struct mlx5_ifc_destroy_mkey_out_bits { 6421 u8 status[0x8]; 6422 u8 reserved_0[0x18]; 6423 6424 u8 syndrome[0x20]; 6425 6426 u8 reserved_1[0x40]; 6427 }; 6428 6429 struct mlx5_ifc_destroy_mkey_in_bits { 6430 u8 opcode[0x10]; 6431 u8 reserved_0[0x10]; 6432 6433 u8 reserved_1[0x10]; 6434 u8 op_mod[0x10]; 6435 6436 u8 reserved_2[0x8]; 6437 u8 mkey_index[0x18]; 6438 6439 u8 reserved_3[0x20]; 6440 }; 6441 6442 struct mlx5_ifc_destroy_flow_table_out_bits { 6443 u8 status[0x8]; 6444 u8 reserved_0[0x18]; 6445 6446 u8 syndrome[0x20]; 6447 6448 u8 reserved_1[0x40]; 6449 }; 6450 6451 struct mlx5_ifc_destroy_flow_table_in_bits { 6452 u8 opcode[0x10]; 6453 u8 reserved_0[0x10]; 6454 6455 u8 reserved_1[0x10]; 6456 u8 op_mod[0x10]; 6457 6458 u8 other_vport[0x1]; 6459 u8 reserved_2[0xf]; 6460 u8 vport_number[0x10]; 6461 6462 u8 reserved_3[0x20]; 6463 6464 u8 table_type[0x8]; 6465 u8 reserved_4[0x18]; 6466 6467 u8 reserved_5[0x8]; 6468 u8 table_id[0x18]; 6469 6470 u8 reserved_6[0x140]; 6471 }; 6472 6473 struct mlx5_ifc_destroy_flow_group_out_bits { 6474 u8 status[0x8]; 6475 u8 reserved_0[0x18]; 6476 6477 u8 syndrome[0x20]; 6478 6479 u8 reserved_1[0x40]; 6480 }; 6481 6482 struct mlx5_ifc_destroy_flow_group_in_bits { 6483 u8 opcode[0x10]; 6484 u8 reserved_0[0x10]; 6485 6486 u8 reserved_1[0x10]; 6487 u8 op_mod[0x10]; 6488 6489 u8 other_vport[0x1]; 6490 u8 reserved_2[0xf]; 6491 u8 vport_number[0x10]; 6492 6493 u8 reserved_3[0x20]; 6494 6495 u8 table_type[0x8]; 6496 u8 reserved_4[0x18]; 6497 6498 u8 reserved_5[0x8]; 6499 u8 table_id[0x18]; 6500 6501 u8 group_id[0x20]; 6502 6503 u8 reserved_6[0x120]; 6504 }; 6505 6506 struct mlx5_ifc_destroy_encryption_key_out_bits { 6507 u8 status[0x8]; 6508 u8 reserved_at_8[0x18]; 6509 6510 u8 syndrome[0x20]; 6511 6512 u8 reserved_at_40[0x40]; 6513 }; 6514 6515 struct mlx5_ifc_destroy_encryption_key_in_bits { 6516 u8 opcode[0x10]; 6517 u8 reserved_at_10[0x10]; 6518 6519 u8 reserved_at_20[0x10]; 6520 u8 obj_type[0x10]; 6521 6522 u8 obj_id[0x20]; 6523 6524 u8 reserved_at_60[0x20]; 6525 }; 6526 6527 struct mlx5_ifc_destroy_eq_out_bits { 6528 u8 status[0x8]; 6529 u8 reserved_0[0x18]; 6530 6531 u8 syndrome[0x20]; 6532 6533 u8 reserved_1[0x40]; 6534 }; 6535 6536 struct mlx5_ifc_destroy_eq_in_bits { 6537 u8 opcode[0x10]; 6538 u8 reserved_0[0x10]; 6539 6540 u8 reserved_1[0x10]; 6541 u8 op_mod[0x10]; 6542 6543 u8 reserved_2[0x18]; 6544 u8 eq_number[0x8]; 6545 6546 u8 reserved_3[0x20]; 6547 }; 6548 6549 struct mlx5_ifc_destroy_dct_out_bits { 6550 u8 status[0x8]; 6551 u8 reserved_0[0x18]; 6552 6553 u8 syndrome[0x20]; 6554 6555 u8 reserved_1[0x40]; 6556 }; 6557 6558 struct mlx5_ifc_destroy_dct_in_bits { 6559 u8 opcode[0x10]; 6560 u8 reserved_0[0x10]; 6561 6562 u8 reserved_1[0x10]; 6563 u8 op_mod[0x10]; 6564 6565 u8 reserved_2[0x8]; 6566 u8 dctn[0x18]; 6567 6568 u8 reserved_3[0x20]; 6569 }; 6570 6571 struct mlx5_ifc_destroy_cq_out_bits { 6572 u8 status[0x8]; 6573 u8 reserved_0[0x18]; 6574 6575 u8 syndrome[0x20]; 6576 6577 u8 reserved_1[0x40]; 6578 }; 6579 6580 struct mlx5_ifc_destroy_cq_in_bits { 6581 u8 opcode[0x10]; 6582 u8 reserved_0[0x10]; 6583 6584 u8 reserved_1[0x10]; 6585 u8 op_mod[0x10]; 6586 6587 u8 reserved_2[0x8]; 6588 u8 cqn[0x18]; 6589 6590 u8 reserved_3[0x20]; 6591 }; 6592 6593 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6594 u8 status[0x8]; 6595 u8 reserved_0[0x18]; 6596 6597 u8 syndrome[0x20]; 6598 6599 u8 reserved_1[0x40]; 6600 }; 6601 6602 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6603 u8 opcode[0x10]; 6604 u8 reserved_0[0x10]; 6605 6606 u8 reserved_1[0x10]; 6607 u8 op_mod[0x10]; 6608 6609 u8 reserved_2[0x20]; 6610 6611 u8 reserved_3[0x10]; 6612 u8 vxlan_udp_port[0x10]; 6613 }; 6614 6615 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6616 u8 status[0x8]; 6617 u8 reserved_0[0x18]; 6618 6619 u8 syndrome[0x20]; 6620 6621 u8 reserved_1[0x40]; 6622 }; 6623 6624 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6625 u8 opcode[0x10]; 6626 u8 reserved_0[0x10]; 6627 6628 u8 reserved_1[0x10]; 6629 u8 op_mod[0x10]; 6630 6631 u8 reserved_2[0x60]; 6632 6633 u8 reserved_3[0x8]; 6634 u8 table_index[0x18]; 6635 6636 u8 reserved_4[0x140]; 6637 }; 6638 6639 struct mlx5_ifc_delete_fte_out_bits { 6640 u8 status[0x8]; 6641 u8 reserved_0[0x18]; 6642 6643 u8 syndrome[0x20]; 6644 6645 u8 reserved_1[0x40]; 6646 }; 6647 6648 struct mlx5_ifc_delete_fte_in_bits { 6649 u8 opcode[0x10]; 6650 u8 reserved_0[0x10]; 6651 6652 u8 reserved_1[0x10]; 6653 u8 op_mod[0x10]; 6654 6655 u8 other_vport[0x1]; 6656 u8 reserved_2[0xf]; 6657 u8 vport_number[0x10]; 6658 6659 u8 reserved_3[0x20]; 6660 6661 u8 table_type[0x8]; 6662 u8 reserved_4[0x18]; 6663 6664 u8 reserved_5[0x8]; 6665 u8 table_id[0x18]; 6666 6667 u8 reserved_6[0x40]; 6668 6669 u8 flow_index[0x20]; 6670 6671 u8 reserved_7[0xe0]; 6672 }; 6673 6674 struct mlx5_ifc_dealloc_xrcd_out_bits { 6675 u8 status[0x8]; 6676 u8 reserved_0[0x18]; 6677 6678 u8 syndrome[0x20]; 6679 6680 u8 reserved_1[0x40]; 6681 }; 6682 6683 struct mlx5_ifc_dealloc_xrcd_in_bits { 6684 u8 opcode[0x10]; 6685 u8 reserved_0[0x10]; 6686 6687 u8 reserved_1[0x10]; 6688 u8 op_mod[0x10]; 6689 6690 u8 reserved_2[0x8]; 6691 u8 xrcd[0x18]; 6692 6693 u8 reserved_3[0x20]; 6694 }; 6695 6696 struct mlx5_ifc_dealloc_uar_out_bits { 6697 u8 status[0x8]; 6698 u8 reserved_0[0x18]; 6699 6700 u8 syndrome[0x20]; 6701 6702 u8 reserved_1[0x40]; 6703 }; 6704 6705 struct mlx5_ifc_dealloc_uar_in_bits { 6706 u8 opcode[0x10]; 6707 u8 reserved_0[0x10]; 6708 6709 u8 reserved_1[0x10]; 6710 u8 op_mod[0x10]; 6711 6712 u8 reserved_2[0x8]; 6713 u8 uar[0x18]; 6714 6715 u8 reserved_3[0x20]; 6716 }; 6717 6718 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6719 u8 status[0x8]; 6720 u8 reserved_0[0x18]; 6721 6722 u8 syndrome[0x20]; 6723 6724 u8 reserved_1[0x40]; 6725 }; 6726 6727 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6728 u8 opcode[0x10]; 6729 u8 reserved_0[0x10]; 6730 6731 u8 reserved_1[0x10]; 6732 u8 op_mod[0x10]; 6733 6734 u8 reserved_2[0x8]; 6735 u8 transport_domain[0x18]; 6736 6737 u8 reserved_3[0x20]; 6738 }; 6739 6740 struct mlx5_ifc_dealloc_q_counter_out_bits { 6741 u8 status[0x8]; 6742 u8 reserved_0[0x18]; 6743 6744 u8 syndrome[0x20]; 6745 6746 u8 reserved_1[0x40]; 6747 }; 6748 6749 struct mlx5_ifc_counter_id_bits { 6750 u8 reserved[0x10]; 6751 u8 counter_id[0x10]; 6752 }; 6753 6754 struct mlx5_ifc_diagnostic_params_context_bits { 6755 u8 num_of_counters[0x10]; 6756 u8 reserved_2[0x8]; 6757 u8 log_num_of_samples[0x8]; 6758 6759 u8 single[0x1]; 6760 u8 repetitive[0x1]; 6761 u8 sync[0x1]; 6762 u8 clear[0x1]; 6763 u8 on_demand[0x1]; 6764 u8 enable[0x1]; 6765 u8 reserved_3[0x12]; 6766 u8 log_sample_period[0x8]; 6767 6768 u8 reserved_4[0x80]; 6769 6770 struct mlx5_ifc_counter_id_bits counter_id[0]; 6771 }; 6772 6773 struct mlx5_ifc_set_diagnostic_params_in_bits { 6774 u8 opcode[0x10]; 6775 u8 reserved_0[0x10]; 6776 6777 u8 reserved_1[0x10]; 6778 u8 op_mod[0x10]; 6779 6780 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 6781 }; 6782 6783 struct mlx5_ifc_set_diagnostic_params_out_bits { 6784 u8 status[0x8]; 6785 u8 reserved_0[0x18]; 6786 6787 u8 syndrome[0x20]; 6788 6789 u8 reserved_1[0x40]; 6790 }; 6791 6792 struct mlx5_ifc_query_diagnostic_counters_in_bits { 6793 u8 opcode[0x10]; 6794 u8 reserved_0[0x10]; 6795 6796 u8 reserved_1[0x10]; 6797 u8 op_mod[0x10]; 6798 6799 u8 num_of_samples[0x10]; 6800 u8 sample_index[0x10]; 6801 6802 u8 reserved_2[0x20]; 6803 }; 6804 6805 struct mlx5_ifc_diagnostic_counter_bits { 6806 u8 counter_id[0x10]; 6807 u8 sample_id[0x10]; 6808 6809 u8 time_stamp_31_0[0x20]; 6810 6811 u8 counter_value_h[0x20]; 6812 6813 u8 counter_value_l[0x20]; 6814 }; 6815 6816 struct mlx5_ifc_query_diagnostic_counters_out_bits { 6817 u8 status[0x8]; 6818 u8 reserved_0[0x18]; 6819 6820 u8 syndrome[0x20]; 6821 6822 u8 reserved_1[0x40]; 6823 6824 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 6825 }; 6826 6827 struct mlx5_ifc_dealloc_q_counter_in_bits { 6828 u8 opcode[0x10]; 6829 u8 reserved_0[0x10]; 6830 6831 u8 reserved_1[0x10]; 6832 u8 op_mod[0x10]; 6833 6834 u8 reserved_2[0x18]; 6835 u8 counter_set_id[0x8]; 6836 6837 u8 reserved_3[0x20]; 6838 }; 6839 6840 struct mlx5_ifc_dealloc_pd_out_bits { 6841 u8 status[0x8]; 6842 u8 reserved_0[0x18]; 6843 6844 u8 syndrome[0x20]; 6845 6846 u8 reserved_1[0x40]; 6847 }; 6848 6849 struct mlx5_ifc_dealloc_pd_in_bits { 6850 u8 opcode[0x10]; 6851 u8 reserved_0[0x10]; 6852 6853 u8 reserved_1[0x10]; 6854 u8 op_mod[0x10]; 6855 6856 u8 reserved_2[0x8]; 6857 u8 pd[0x18]; 6858 6859 u8 reserved_3[0x20]; 6860 }; 6861 6862 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6863 u8 status[0x8]; 6864 u8 reserved_0[0x18]; 6865 6866 u8 syndrome[0x20]; 6867 6868 u8 reserved_1[0x40]; 6869 }; 6870 6871 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6872 u8 opcode[0x10]; 6873 u8 reserved_0[0x10]; 6874 6875 u8 reserved_1[0x10]; 6876 u8 op_mod[0x10]; 6877 6878 u8 reserved_2[0x10]; 6879 u8 flow_counter_id[0x10]; 6880 6881 u8 reserved_3[0x20]; 6882 }; 6883 6884 struct mlx5_ifc_deactivate_tracer_out_bits { 6885 u8 status[0x8]; 6886 u8 reserved_0[0x18]; 6887 6888 u8 syndrome[0x20]; 6889 6890 u8 reserved_1[0x40]; 6891 }; 6892 6893 struct mlx5_ifc_deactivate_tracer_in_bits { 6894 u8 opcode[0x10]; 6895 u8 reserved_0[0x10]; 6896 6897 u8 reserved_1[0x10]; 6898 u8 op_mod[0x10]; 6899 6900 u8 mkey[0x20]; 6901 6902 u8 reserved_2[0x20]; 6903 }; 6904 6905 struct mlx5_ifc_create_xrc_srq_out_bits { 6906 u8 status[0x8]; 6907 u8 reserved_0[0x18]; 6908 6909 u8 syndrome[0x20]; 6910 6911 u8 reserved_1[0x8]; 6912 u8 xrc_srqn[0x18]; 6913 6914 u8 reserved_2[0x20]; 6915 }; 6916 6917 struct mlx5_ifc_create_xrc_srq_in_bits { 6918 u8 opcode[0x10]; 6919 u8 reserved_0[0x10]; 6920 6921 u8 reserved_1[0x10]; 6922 u8 op_mod[0x10]; 6923 6924 u8 reserved_2[0x40]; 6925 6926 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6927 6928 u8 reserved_3[0x600]; 6929 6930 u8 pas[0][0x40]; 6931 }; 6932 6933 struct mlx5_ifc_create_tis_out_bits { 6934 u8 status[0x8]; 6935 u8 reserved_0[0x18]; 6936 6937 u8 syndrome[0x20]; 6938 6939 u8 reserved_1[0x8]; 6940 u8 tisn[0x18]; 6941 6942 u8 reserved_2[0x20]; 6943 }; 6944 6945 struct mlx5_ifc_create_tis_in_bits { 6946 u8 opcode[0x10]; 6947 u8 reserved_0[0x10]; 6948 6949 u8 reserved_1[0x10]; 6950 u8 op_mod[0x10]; 6951 6952 u8 reserved_2[0xc0]; 6953 6954 struct mlx5_ifc_tisc_bits ctx; 6955 }; 6956 6957 struct mlx5_ifc_create_tir_out_bits { 6958 u8 status[0x8]; 6959 u8 reserved_0[0x18]; 6960 6961 u8 syndrome[0x20]; 6962 6963 u8 reserved_1[0x8]; 6964 u8 tirn[0x18]; 6965 6966 u8 reserved_2[0x20]; 6967 }; 6968 6969 struct mlx5_ifc_create_tir_in_bits { 6970 u8 opcode[0x10]; 6971 u8 reserved_0[0x10]; 6972 6973 u8 reserved_1[0x10]; 6974 u8 op_mod[0x10]; 6975 6976 u8 reserved_2[0xc0]; 6977 6978 struct mlx5_ifc_tirc_bits tir_context; 6979 }; 6980 6981 struct mlx5_ifc_create_srq_out_bits { 6982 u8 status[0x8]; 6983 u8 reserved_0[0x18]; 6984 6985 u8 syndrome[0x20]; 6986 6987 u8 reserved_1[0x8]; 6988 u8 srqn[0x18]; 6989 6990 u8 reserved_2[0x20]; 6991 }; 6992 6993 struct mlx5_ifc_create_srq_in_bits { 6994 u8 opcode[0x10]; 6995 u8 reserved_0[0x10]; 6996 6997 u8 reserved_1[0x10]; 6998 u8 op_mod[0x10]; 6999 7000 u8 reserved_2[0x40]; 7001 7002 struct mlx5_ifc_srqc_bits srq_context_entry; 7003 7004 u8 reserved_3[0x600]; 7005 7006 u8 pas[0][0x40]; 7007 }; 7008 7009 struct mlx5_ifc_create_sq_out_bits { 7010 u8 status[0x8]; 7011 u8 reserved_0[0x18]; 7012 7013 u8 syndrome[0x20]; 7014 7015 u8 reserved_1[0x8]; 7016 u8 sqn[0x18]; 7017 7018 u8 reserved_2[0x20]; 7019 }; 7020 7021 struct mlx5_ifc_create_sq_in_bits { 7022 u8 opcode[0x10]; 7023 u8 reserved_0[0x10]; 7024 7025 u8 reserved_1[0x10]; 7026 u8 op_mod[0x10]; 7027 7028 u8 reserved_2[0xc0]; 7029 7030 struct mlx5_ifc_sqc_bits ctx; 7031 }; 7032 7033 struct mlx5_ifc_create_scheduling_element_out_bits { 7034 u8 status[0x8]; 7035 u8 reserved_at_8[0x18]; 7036 7037 u8 syndrome[0x20]; 7038 7039 u8 reserved_at_40[0x40]; 7040 7041 u8 scheduling_element_id[0x20]; 7042 7043 u8 reserved_at_a0[0x160]; 7044 }; 7045 7046 enum { 7047 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 7048 }; 7049 7050 struct mlx5_ifc_create_scheduling_element_in_bits { 7051 u8 opcode[0x10]; 7052 u8 reserved_at_10[0x10]; 7053 7054 u8 reserved_at_20[0x10]; 7055 u8 op_mod[0x10]; 7056 7057 u8 scheduling_hierarchy[0x8]; 7058 u8 reserved_at_48[0x18]; 7059 7060 u8 reserved_at_60[0xa0]; 7061 7062 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7063 7064 u8 reserved_at_300[0x100]; 7065 }; 7066 7067 struct mlx5_ifc_create_rqt_out_bits { 7068 u8 status[0x8]; 7069 u8 reserved_0[0x18]; 7070 7071 u8 syndrome[0x20]; 7072 7073 u8 reserved_1[0x8]; 7074 u8 rqtn[0x18]; 7075 7076 u8 reserved_2[0x20]; 7077 }; 7078 7079 struct mlx5_ifc_create_rqt_in_bits { 7080 u8 opcode[0x10]; 7081 u8 reserved_0[0x10]; 7082 7083 u8 reserved_1[0x10]; 7084 u8 op_mod[0x10]; 7085 7086 u8 reserved_2[0xc0]; 7087 7088 struct mlx5_ifc_rqtc_bits rqt_context; 7089 }; 7090 7091 struct mlx5_ifc_create_rq_out_bits { 7092 u8 status[0x8]; 7093 u8 reserved_0[0x18]; 7094 7095 u8 syndrome[0x20]; 7096 7097 u8 reserved_1[0x8]; 7098 u8 rqn[0x18]; 7099 7100 u8 reserved_2[0x20]; 7101 }; 7102 7103 struct mlx5_ifc_create_rq_in_bits { 7104 u8 opcode[0x10]; 7105 u8 reserved_0[0x10]; 7106 7107 u8 reserved_1[0x10]; 7108 u8 op_mod[0x10]; 7109 7110 u8 reserved_2[0xc0]; 7111 7112 struct mlx5_ifc_rqc_bits ctx; 7113 }; 7114 7115 struct mlx5_ifc_create_rmp_out_bits { 7116 u8 status[0x8]; 7117 u8 reserved_0[0x18]; 7118 7119 u8 syndrome[0x20]; 7120 7121 u8 reserved_1[0x8]; 7122 u8 rmpn[0x18]; 7123 7124 u8 reserved_2[0x20]; 7125 }; 7126 7127 struct mlx5_ifc_create_rmp_in_bits { 7128 u8 opcode[0x10]; 7129 u8 reserved_0[0x10]; 7130 7131 u8 reserved_1[0x10]; 7132 u8 op_mod[0x10]; 7133 7134 u8 reserved_2[0xc0]; 7135 7136 struct mlx5_ifc_rmpc_bits ctx; 7137 }; 7138 7139 struct mlx5_ifc_create_qp_out_bits { 7140 u8 status[0x8]; 7141 u8 reserved_0[0x18]; 7142 7143 u8 syndrome[0x20]; 7144 7145 u8 reserved_1[0x8]; 7146 u8 qpn[0x18]; 7147 7148 u8 reserved_2[0x20]; 7149 }; 7150 7151 struct mlx5_ifc_create_qp_in_bits { 7152 u8 opcode[0x10]; 7153 u8 reserved_0[0x10]; 7154 7155 u8 reserved_1[0x10]; 7156 u8 op_mod[0x10]; 7157 7158 u8 reserved_2[0x8]; 7159 u8 input_qpn[0x18]; 7160 7161 u8 reserved_3[0x20]; 7162 7163 u8 opt_param_mask[0x20]; 7164 7165 u8 reserved_4[0x20]; 7166 7167 struct mlx5_ifc_qpc_bits qpc; 7168 7169 u8 reserved_5[0x80]; 7170 7171 u8 pas[0][0x40]; 7172 }; 7173 7174 struct mlx5_ifc_create_qos_para_vport_out_bits { 7175 u8 status[0x8]; 7176 u8 reserved_at_8[0x18]; 7177 7178 u8 syndrome[0x20]; 7179 7180 u8 reserved_at_40[0x20]; 7181 7182 u8 reserved_at_60[0x10]; 7183 u8 qos_para_vport_number[0x10]; 7184 7185 u8 reserved_at_80[0x180]; 7186 }; 7187 7188 struct mlx5_ifc_create_qos_para_vport_in_bits { 7189 u8 opcode[0x10]; 7190 u8 reserved_at_10[0x10]; 7191 7192 u8 reserved_at_20[0x10]; 7193 u8 op_mod[0x10]; 7194 7195 u8 reserved_at_40[0x1c0]; 7196 }; 7197 7198 struct mlx5_ifc_create_psv_out_bits { 7199 u8 status[0x8]; 7200 u8 reserved_0[0x18]; 7201 7202 u8 syndrome[0x20]; 7203 7204 u8 reserved_1[0x40]; 7205 7206 u8 reserved_2[0x8]; 7207 u8 psv0_index[0x18]; 7208 7209 u8 reserved_3[0x8]; 7210 u8 psv1_index[0x18]; 7211 7212 u8 reserved_4[0x8]; 7213 u8 psv2_index[0x18]; 7214 7215 u8 reserved_5[0x8]; 7216 u8 psv3_index[0x18]; 7217 }; 7218 7219 struct mlx5_ifc_create_psv_in_bits { 7220 u8 opcode[0x10]; 7221 u8 reserved_0[0x10]; 7222 7223 u8 reserved_1[0x10]; 7224 u8 op_mod[0x10]; 7225 7226 u8 num_psv[0x4]; 7227 u8 reserved_2[0x4]; 7228 u8 pd[0x18]; 7229 7230 u8 reserved_3[0x20]; 7231 }; 7232 7233 struct mlx5_ifc_create_mkey_out_bits { 7234 u8 status[0x8]; 7235 u8 reserved_0[0x18]; 7236 7237 u8 syndrome[0x20]; 7238 7239 u8 reserved_1[0x8]; 7240 u8 mkey_index[0x18]; 7241 7242 u8 reserved_2[0x20]; 7243 }; 7244 7245 struct mlx5_ifc_create_mkey_in_bits { 7246 u8 opcode[0x10]; 7247 u8 reserved_0[0x10]; 7248 7249 u8 reserved_1[0x10]; 7250 u8 op_mod[0x10]; 7251 7252 u8 reserved_2[0x20]; 7253 7254 u8 pg_access[0x1]; 7255 u8 reserved_3[0x1f]; 7256 7257 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7258 7259 u8 reserved_4[0x80]; 7260 7261 u8 translations_octword_actual_size[0x20]; 7262 7263 u8 reserved_5[0x560]; 7264 7265 u8 klm_pas_mtt[0][0x20]; 7266 }; 7267 7268 struct mlx5_ifc_create_flow_table_out_bits { 7269 u8 status[0x8]; 7270 u8 reserved_0[0x18]; 7271 7272 u8 syndrome[0x20]; 7273 7274 u8 reserved_1[0x8]; 7275 u8 table_id[0x18]; 7276 7277 u8 reserved_2[0x20]; 7278 }; 7279 7280 struct mlx5_ifc_create_flow_table_in_bits { 7281 u8 opcode[0x10]; 7282 u8 reserved_at_10[0x10]; 7283 7284 u8 reserved_at_20[0x10]; 7285 u8 op_mod[0x10]; 7286 7287 u8 other_vport[0x1]; 7288 u8 reserved_at_41[0xf]; 7289 u8 vport_number[0x10]; 7290 7291 u8 reserved_at_60[0x20]; 7292 7293 u8 table_type[0x8]; 7294 u8 reserved_at_88[0x18]; 7295 7296 u8 reserved_at_a0[0x20]; 7297 7298 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7299 }; 7300 7301 struct mlx5_ifc_create_flow_group_out_bits { 7302 u8 status[0x8]; 7303 u8 reserved_0[0x18]; 7304 7305 u8 syndrome[0x20]; 7306 7307 u8 reserved_1[0x8]; 7308 u8 group_id[0x18]; 7309 7310 u8 reserved_2[0x20]; 7311 }; 7312 7313 enum { 7314 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7315 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7316 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7317 }; 7318 7319 struct mlx5_ifc_create_flow_group_in_bits { 7320 u8 opcode[0x10]; 7321 u8 reserved_0[0x10]; 7322 7323 u8 reserved_1[0x10]; 7324 u8 op_mod[0x10]; 7325 7326 u8 other_vport[0x1]; 7327 u8 reserved_2[0xf]; 7328 u8 vport_number[0x10]; 7329 7330 u8 reserved_3[0x20]; 7331 7332 u8 table_type[0x8]; 7333 u8 reserved_4[0x18]; 7334 7335 u8 reserved_5[0x8]; 7336 u8 table_id[0x18]; 7337 7338 u8 reserved_6[0x20]; 7339 7340 u8 start_flow_index[0x20]; 7341 7342 u8 reserved_7[0x20]; 7343 7344 u8 end_flow_index[0x20]; 7345 7346 u8 reserved_8[0xa0]; 7347 7348 u8 reserved_9[0x18]; 7349 u8 match_criteria_enable[0x8]; 7350 7351 struct mlx5_ifc_fte_match_param_bits match_criteria; 7352 7353 u8 reserved_10[0xe00]; 7354 }; 7355 7356 struct mlx5_ifc_create_encryption_key_out_bits { 7357 u8 status[0x8]; 7358 u8 reserved_at_8[0x18]; 7359 7360 u8 syndrome[0x20]; 7361 7362 u8 obj_id[0x20]; 7363 7364 u8 reserved_at_60[0x20]; 7365 }; 7366 7367 struct mlx5_ifc_create_encryption_key_in_bits { 7368 u8 opcode[0x10]; 7369 u8 reserved_at_10[0x10]; 7370 7371 u8 reserved_at_20[0x10]; 7372 u8 obj_type[0x10]; 7373 7374 u8 reserved_at_40[0x40]; 7375 7376 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 7377 }; 7378 7379 struct mlx5_ifc_create_eq_out_bits { 7380 u8 status[0x8]; 7381 u8 reserved_0[0x18]; 7382 7383 u8 syndrome[0x20]; 7384 7385 u8 reserved_1[0x18]; 7386 u8 eq_number[0x8]; 7387 7388 u8 reserved_2[0x20]; 7389 }; 7390 7391 struct mlx5_ifc_create_eq_in_bits { 7392 u8 opcode[0x10]; 7393 u8 reserved_0[0x10]; 7394 7395 u8 reserved_1[0x10]; 7396 u8 op_mod[0x10]; 7397 7398 u8 reserved_2[0x40]; 7399 7400 struct mlx5_ifc_eqc_bits eq_context_entry; 7401 7402 u8 reserved_3[0x40]; 7403 7404 u8 event_bitmask[0x40]; 7405 7406 u8 reserved_4[0x580]; 7407 7408 u8 pas[0][0x40]; 7409 }; 7410 7411 struct mlx5_ifc_create_dct_out_bits { 7412 u8 status[0x8]; 7413 u8 reserved_0[0x18]; 7414 7415 u8 syndrome[0x20]; 7416 7417 u8 reserved_1[0x8]; 7418 u8 dctn[0x18]; 7419 7420 u8 reserved_2[0x20]; 7421 }; 7422 7423 struct mlx5_ifc_create_dct_in_bits { 7424 u8 opcode[0x10]; 7425 u8 reserved_0[0x10]; 7426 7427 u8 reserved_1[0x10]; 7428 u8 op_mod[0x10]; 7429 7430 u8 reserved_2[0x40]; 7431 7432 struct mlx5_ifc_dctc_bits dct_context_entry; 7433 7434 u8 reserved_3[0x180]; 7435 }; 7436 7437 struct mlx5_ifc_create_cq_out_bits { 7438 u8 status[0x8]; 7439 u8 reserved_0[0x18]; 7440 7441 u8 syndrome[0x20]; 7442 7443 u8 reserved_1[0x8]; 7444 u8 cqn[0x18]; 7445 7446 u8 reserved_2[0x20]; 7447 }; 7448 7449 struct mlx5_ifc_create_cq_in_bits { 7450 u8 opcode[0x10]; 7451 u8 reserved_0[0x10]; 7452 7453 u8 reserved_1[0x10]; 7454 u8 op_mod[0x10]; 7455 7456 u8 reserved_2[0x40]; 7457 7458 struct mlx5_ifc_cqc_bits cq_context; 7459 7460 u8 reserved_3[0x600]; 7461 7462 u8 pas[0][0x40]; 7463 }; 7464 7465 struct mlx5_ifc_config_int_moderation_out_bits { 7466 u8 status[0x8]; 7467 u8 reserved_0[0x18]; 7468 7469 u8 syndrome[0x20]; 7470 7471 u8 reserved_1[0x4]; 7472 u8 min_delay[0xc]; 7473 u8 int_vector[0x10]; 7474 7475 u8 reserved_2[0x20]; 7476 }; 7477 7478 enum { 7479 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7480 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7481 }; 7482 7483 struct mlx5_ifc_config_int_moderation_in_bits { 7484 u8 opcode[0x10]; 7485 u8 reserved_0[0x10]; 7486 7487 u8 reserved_1[0x10]; 7488 u8 op_mod[0x10]; 7489 7490 u8 reserved_2[0x4]; 7491 u8 min_delay[0xc]; 7492 u8 int_vector[0x10]; 7493 7494 u8 reserved_3[0x20]; 7495 }; 7496 7497 struct mlx5_ifc_attach_to_mcg_out_bits { 7498 u8 status[0x8]; 7499 u8 reserved_0[0x18]; 7500 7501 u8 syndrome[0x20]; 7502 7503 u8 reserved_1[0x40]; 7504 }; 7505 7506 struct mlx5_ifc_attach_to_mcg_in_bits { 7507 u8 opcode[0x10]; 7508 u8 reserved_0[0x10]; 7509 7510 u8 reserved_1[0x10]; 7511 u8 op_mod[0x10]; 7512 7513 u8 reserved_2[0x8]; 7514 u8 qpn[0x18]; 7515 7516 u8 reserved_3[0x20]; 7517 7518 u8 multicast_gid[16][0x8]; 7519 }; 7520 7521 struct mlx5_ifc_arm_xrc_srq_out_bits { 7522 u8 status[0x8]; 7523 u8 reserved_0[0x18]; 7524 7525 u8 syndrome[0x20]; 7526 7527 u8 reserved_1[0x40]; 7528 }; 7529 7530 enum { 7531 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7532 }; 7533 7534 struct mlx5_ifc_arm_xrc_srq_in_bits { 7535 u8 opcode[0x10]; 7536 u8 reserved_0[0x10]; 7537 7538 u8 reserved_1[0x10]; 7539 u8 op_mod[0x10]; 7540 7541 u8 reserved_2[0x8]; 7542 u8 xrc_srqn[0x18]; 7543 7544 u8 reserved_3[0x10]; 7545 u8 lwm[0x10]; 7546 }; 7547 7548 struct mlx5_ifc_arm_rq_out_bits { 7549 u8 status[0x8]; 7550 u8 reserved_0[0x18]; 7551 7552 u8 syndrome[0x20]; 7553 7554 u8 reserved_1[0x40]; 7555 }; 7556 7557 enum { 7558 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7559 }; 7560 7561 struct mlx5_ifc_arm_rq_in_bits { 7562 u8 opcode[0x10]; 7563 u8 reserved_0[0x10]; 7564 7565 u8 reserved_1[0x10]; 7566 u8 op_mod[0x10]; 7567 7568 u8 reserved_2[0x8]; 7569 u8 srq_number[0x18]; 7570 7571 u8 reserved_3[0x10]; 7572 u8 lwm[0x10]; 7573 }; 7574 7575 struct mlx5_ifc_arm_dct_out_bits { 7576 u8 status[0x8]; 7577 u8 reserved_0[0x18]; 7578 7579 u8 syndrome[0x20]; 7580 7581 u8 reserved_1[0x40]; 7582 }; 7583 7584 struct mlx5_ifc_arm_dct_in_bits { 7585 u8 opcode[0x10]; 7586 u8 reserved_0[0x10]; 7587 7588 u8 reserved_1[0x10]; 7589 u8 op_mod[0x10]; 7590 7591 u8 reserved_2[0x8]; 7592 u8 dctn[0x18]; 7593 7594 u8 reserved_3[0x20]; 7595 }; 7596 7597 struct mlx5_ifc_alloc_xrcd_out_bits { 7598 u8 status[0x8]; 7599 u8 reserved_0[0x18]; 7600 7601 u8 syndrome[0x20]; 7602 7603 u8 reserved_1[0x8]; 7604 u8 xrcd[0x18]; 7605 7606 u8 reserved_2[0x20]; 7607 }; 7608 7609 struct mlx5_ifc_alloc_xrcd_in_bits { 7610 u8 opcode[0x10]; 7611 u8 reserved_0[0x10]; 7612 7613 u8 reserved_1[0x10]; 7614 u8 op_mod[0x10]; 7615 7616 u8 reserved_2[0x40]; 7617 }; 7618 7619 struct mlx5_ifc_alloc_uar_out_bits { 7620 u8 status[0x8]; 7621 u8 reserved_0[0x18]; 7622 7623 u8 syndrome[0x20]; 7624 7625 u8 reserved_1[0x8]; 7626 u8 uar[0x18]; 7627 7628 u8 reserved_2[0x20]; 7629 }; 7630 7631 struct mlx5_ifc_alloc_uar_in_bits { 7632 u8 opcode[0x10]; 7633 u8 reserved_0[0x10]; 7634 7635 u8 reserved_1[0x10]; 7636 u8 op_mod[0x10]; 7637 7638 u8 reserved_2[0x40]; 7639 }; 7640 7641 struct mlx5_ifc_alloc_transport_domain_out_bits { 7642 u8 status[0x8]; 7643 u8 reserved_0[0x18]; 7644 7645 u8 syndrome[0x20]; 7646 7647 u8 reserved_1[0x8]; 7648 u8 transport_domain[0x18]; 7649 7650 u8 reserved_2[0x20]; 7651 }; 7652 7653 struct mlx5_ifc_alloc_transport_domain_in_bits { 7654 u8 opcode[0x10]; 7655 u8 reserved_0[0x10]; 7656 7657 u8 reserved_1[0x10]; 7658 u8 op_mod[0x10]; 7659 7660 u8 reserved_2[0x40]; 7661 }; 7662 7663 struct mlx5_ifc_alloc_q_counter_out_bits { 7664 u8 status[0x8]; 7665 u8 reserved_0[0x18]; 7666 7667 u8 syndrome[0x20]; 7668 7669 u8 reserved_1[0x18]; 7670 u8 counter_set_id[0x8]; 7671 7672 u8 reserved_2[0x20]; 7673 }; 7674 7675 struct mlx5_ifc_alloc_q_counter_in_bits { 7676 u8 opcode[0x10]; 7677 u8 reserved_0[0x10]; 7678 7679 u8 reserved_1[0x10]; 7680 u8 op_mod[0x10]; 7681 7682 u8 reserved_2[0x40]; 7683 }; 7684 7685 struct mlx5_ifc_alloc_pd_out_bits { 7686 u8 status[0x8]; 7687 u8 reserved_0[0x18]; 7688 7689 u8 syndrome[0x20]; 7690 7691 u8 reserved_1[0x8]; 7692 u8 pd[0x18]; 7693 7694 u8 reserved_2[0x20]; 7695 }; 7696 7697 struct mlx5_ifc_alloc_pd_in_bits { 7698 u8 opcode[0x10]; 7699 u8 reserved_0[0x10]; 7700 7701 u8 reserved_1[0x10]; 7702 u8 op_mod[0x10]; 7703 7704 u8 reserved_2[0x40]; 7705 }; 7706 7707 struct mlx5_ifc_alloc_flow_counter_out_bits { 7708 u8 status[0x8]; 7709 u8 reserved_0[0x18]; 7710 7711 u8 syndrome[0x20]; 7712 7713 u8 reserved_1[0x10]; 7714 u8 flow_counter_id[0x10]; 7715 7716 u8 reserved_2[0x20]; 7717 }; 7718 7719 struct mlx5_ifc_alloc_flow_counter_in_bits { 7720 u8 opcode[0x10]; 7721 u8 reserved_0[0x10]; 7722 7723 u8 reserved_1[0x10]; 7724 u8 op_mod[0x10]; 7725 7726 u8 reserved_2[0x40]; 7727 }; 7728 7729 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7730 u8 status[0x8]; 7731 u8 reserved_0[0x18]; 7732 7733 u8 syndrome[0x20]; 7734 7735 u8 reserved_1[0x40]; 7736 }; 7737 7738 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7739 u8 opcode[0x10]; 7740 u8 reserved_0[0x10]; 7741 7742 u8 reserved_1[0x10]; 7743 u8 op_mod[0x10]; 7744 7745 u8 reserved_2[0x20]; 7746 7747 u8 reserved_3[0x10]; 7748 u8 vxlan_udp_port[0x10]; 7749 }; 7750 7751 struct mlx5_ifc_activate_tracer_out_bits { 7752 u8 status[0x8]; 7753 u8 reserved_0[0x18]; 7754 7755 u8 syndrome[0x20]; 7756 7757 u8 reserved_1[0x40]; 7758 }; 7759 7760 struct mlx5_ifc_activate_tracer_in_bits { 7761 u8 opcode[0x10]; 7762 u8 reserved_0[0x10]; 7763 7764 u8 reserved_1[0x10]; 7765 u8 op_mod[0x10]; 7766 7767 u8 mkey[0x20]; 7768 7769 u8 reserved_2[0x20]; 7770 }; 7771 7772 struct mlx5_ifc_set_rate_limit_out_bits { 7773 u8 status[0x8]; 7774 u8 reserved_at_8[0x18]; 7775 7776 u8 syndrome[0x20]; 7777 7778 u8 reserved_at_40[0x40]; 7779 }; 7780 7781 struct mlx5_ifc_set_rate_limit_in_bits { 7782 u8 opcode[0x10]; 7783 u8 reserved_at_10[0x10]; 7784 7785 u8 reserved_at_20[0x10]; 7786 u8 op_mod[0x10]; 7787 7788 u8 reserved_at_40[0x10]; 7789 u8 rate_limit_index[0x10]; 7790 7791 u8 reserved_at_60[0x20]; 7792 7793 u8 rate_limit[0x20]; 7794 7795 u8 burst_upper_bound[0x20]; 7796 7797 u8 reserved_at_c0[0x10]; 7798 u8 typical_packet_size[0x10]; 7799 7800 u8 reserved_at_e0[0x120]; 7801 }; 7802 7803 struct mlx5_ifc_access_register_out_bits { 7804 u8 status[0x8]; 7805 u8 reserved_0[0x18]; 7806 7807 u8 syndrome[0x20]; 7808 7809 u8 reserved_1[0x40]; 7810 7811 u8 register_data[0][0x20]; 7812 }; 7813 7814 enum { 7815 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7816 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7817 }; 7818 7819 struct mlx5_ifc_access_register_in_bits { 7820 u8 opcode[0x10]; 7821 u8 reserved_0[0x10]; 7822 7823 u8 reserved_1[0x10]; 7824 u8 op_mod[0x10]; 7825 7826 u8 reserved_2[0x10]; 7827 u8 register_id[0x10]; 7828 7829 u8 argument[0x20]; 7830 7831 u8 register_data[0][0x20]; 7832 }; 7833 7834 struct mlx5_ifc_sltp_reg_bits { 7835 u8 status[0x4]; 7836 u8 version[0x4]; 7837 u8 local_port[0x8]; 7838 u8 pnat[0x2]; 7839 u8 reserved_0[0x2]; 7840 u8 lane[0x4]; 7841 u8 reserved_1[0x8]; 7842 7843 u8 reserved_2[0x20]; 7844 7845 u8 reserved_3[0x7]; 7846 u8 polarity[0x1]; 7847 u8 ob_tap0[0x8]; 7848 u8 ob_tap1[0x8]; 7849 u8 ob_tap2[0x8]; 7850 7851 u8 reserved_4[0xc]; 7852 u8 ob_preemp_mode[0x4]; 7853 u8 ob_reg[0x8]; 7854 u8 ob_bias[0x8]; 7855 7856 u8 reserved_5[0x20]; 7857 }; 7858 7859 struct mlx5_ifc_slrp_reg_bits { 7860 u8 status[0x4]; 7861 u8 version[0x4]; 7862 u8 local_port[0x8]; 7863 u8 pnat[0x2]; 7864 u8 reserved_0[0x2]; 7865 u8 lane[0x4]; 7866 u8 reserved_1[0x8]; 7867 7868 u8 ib_sel[0x2]; 7869 u8 reserved_2[0x11]; 7870 u8 dp_sel[0x1]; 7871 u8 dp90sel[0x4]; 7872 u8 mix90phase[0x8]; 7873 7874 u8 ffe_tap0[0x8]; 7875 u8 ffe_tap1[0x8]; 7876 u8 ffe_tap2[0x8]; 7877 u8 ffe_tap3[0x8]; 7878 7879 u8 ffe_tap4[0x8]; 7880 u8 ffe_tap5[0x8]; 7881 u8 ffe_tap6[0x8]; 7882 u8 ffe_tap7[0x8]; 7883 7884 u8 ffe_tap8[0x8]; 7885 u8 mixerbias_tap_amp[0x8]; 7886 u8 reserved_3[0x7]; 7887 u8 ffe_tap_en[0x9]; 7888 7889 u8 ffe_tap_offset0[0x8]; 7890 u8 ffe_tap_offset1[0x8]; 7891 u8 slicer_offset0[0x10]; 7892 7893 u8 mixer_offset0[0x10]; 7894 u8 mixer_offset1[0x10]; 7895 7896 u8 mixerbgn_inp[0x8]; 7897 u8 mixerbgn_inn[0x8]; 7898 u8 mixerbgn_refp[0x8]; 7899 u8 mixerbgn_refn[0x8]; 7900 7901 u8 sel_slicer_lctrl_h[0x1]; 7902 u8 sel_slicer_lctrl_l[0x1]; 7903 u8 reserved_4[0x1]; 7904 u8 ref_mixer_vreg[0x5]; 7905 u8 slicer_gctrl[0x8]; 7906 u8 lctrl_input[0x8]; 7907 u8 mixer_offset_cm1[0x8]; 7908 7909 u8 common_mode[0x6]; 7910 u8 reserved_5[0x1]; 7911 u8 mixer_offset_cm0[0x9]; 7912 u8 reserved_6[0x7]; 7913 u8 slicer_offset_cm[0x9]; 7914 }; 7915 7916 struct mlx5_ifc_slrg_reg_bits { 7917 u8 status[0x4]; 7918 u8 version[0x4]; 7919 u8 local_port[0x8]; 7920 u8 pnat[0x2]; 7921 u8 reserved_0[0x2]; 7922 u8 lane[0x4]; 7923 u8 reserved_1[0x8]; 7924 7925 u8 time_to_link_up[0x10]; 7926 u8 reserved_2[0xc]; 7927 u8 grade_lane_speed[0x4]; 7928 7929 u8 grade_version[0x8]; 7930 u8 grade[0x18]; 7931 7932 u8 reserved_3[0x4]; 7933 u8 height_grade_type[0x4]; 7934 u8 height_grade[0x18]; 7935 7936 u8 height_dz[0x10]; 7937 u8 height_dv[0x10]; 7938 7939 u8 reserved_4[0x10]; 7940 u8 height_sigma[0x10]; 7941 7942 u8 reserved_5[0x20]; 7943 7944 u8 reserved_6[0x4]; 7945 u8 phase_grade_type[0x4]; 7946 u8 phase_grade[0x18]; 7947 7948 u8 reserved_7[0x8]; 7949 u8 phase_eo_pos[0x8]; 7950 u8 reserved_8[0x8]; 7951 u8 phase_eo_neg[0x8]; 7952 7953 u8 ffe_set_tested[0x10]; 7954 u8 test_errors_per_lane[0x10]; 7955 }; 7956 7957 struct mlx5_ifc_pvlc_reg_bits { 7958 u8 reserved_0[0x8]; 7959 u8 local_port[0x8]; 7960 u8 reserved_1[0x10]; 7961 7962 u8 reserved_2[0x1c]; 7963 u8 vl_hw_cap[0x4]; 7964 7965 u8 reserved_3[0x1c]; 7966 u8 vl_admin[0x4]; 7967 7968 u8 reserved_4[0x1c]; 7969 u8 vl_operational[0x4]; 7970 }; 7971 7972 struct mlx5_ifc_pude_reg_bits { 7973 u8 swid[0x8]; 7974 u8 local_port[0x8]; 7975 u8 reserved_0[0x4]; 7976 u8 admin_status[0x4]; 7977 u8 reserved_1[0x4]; 7978 u8 oper_status[0x4]; 7979 7980 u8 reserved_2[0x60]; 7981 }; 7982 7983 enum { 7984 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 7985 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 7986 }; 7987 7988 struct mlx5_ifc_ptys_reg_bits { 7989 u8 reserved_0[0x1]; 7990 u8 an_disable_admin[0x1]; 7991 u8 an_disable_cap[0x1]; 7992 u8 reserved_1[0x4]; 7993 u8 force_tx_aba_param[0x1]; 7994 u8 local_port[0x8]; 7995 u8 reserved_2[0xd]; 7996 u8 proto_mask[0x3]; 7997 7998 u8 an_status[0x4]; 7999 u8 reserved_3[0xc]; 8000 u8 data_rate_oper[0x10]; 8001 8002 u8 ext_eth_proto_capability[0x20]; 8003 8004 u8 eth_proto_capability[0x20]; 8005 8006 u8 ib_link_width_capability[0x10]; 8007 u8 ib_proto_capability[0x10]; 8008 8009 u8 ext_eth_proto_admin[0x20]; 8010 8011 u8 eth_proto_admin[0x20]; 8012 8013 u8 ib_link_width_admin[0x10]; 8014 u8 ib_proto_admin[0x10]; 8015 8016 u8 ext_eth_proto_oper[0x20]; 8017 8018 u8 eth_proto_oper[0x20]; 8019 8020 u8 ib_link_width_oper[0x10]; 8021 u8 ib_proto_oper[0x10]; 8022 8023 u8 reserved_4[0x1c]; 8024 u8 connector_type[0x4]; 8025 8026 u8 eth_proto_lp_advertise[0x20]; 8027 8028 u8 reserved_5[0x60]; 8029 }; 8030 8031 struct mlx5_ifc_ptas_reg_bits { 8032 u8 reserved_0[0x20]; 8033 8034 u8 algorithm_options[0x10]; 8035 u8 reserved_1[0x4]; 8036 u8 repetitions_mode[0x4]; 8037 u8 num_of_repetitions[0x8]; 8038 8039 u8 grade_version[0x8]; 8040 u8 height_grade_type[0x4]; 8041 u8 phase_grade_type[0x4]; 8042 u8 height_grade_weight[0x8]; 8043 u8 phase_grade_weight[0x8]; 8044 8045 u8 gisim_measure_bits[0x10]; 8046 u8 adaptive_tap_measure_bits[0x10]; 8047 8048 u8 ber_bath_high_error_threshold[0x10]; 8049 u8 ber_bath_mid_error_threshold[0x10]; 8050 8051 u8 ber_bath_low_error_threshold[0x10]; 8052 u8 one_ratio_high_threshold[0x10]; 8053 8054 u8 one_ratio_high_mid_threshold[0x10]; 8055 u8 one_ratio_low_mid_threshold[0x10]; 8056 8057 u8 one_ratio_low_threshold[0x10]; 8058 u8 ndeo_error_threshold[0x10]; 8059 8060 u8 mixer_offset_step_size[0x10]; 8061 u8 reserved_2[0x8]; 8062 u8 mix90_phase_for_voltage_bath[0x8]; 8063 8064 u8 mixer_offset_start[0x10]; 8065 u8 mixer_offset_end[0x10]; 8066 8067 u8 reserved_3[0x15]; 8068 u8 ber_test_time[0xb]; 8069 }; 8070 8071 struct mlx5_ifc_pspa_reg_bits { 8072 u8 swid[0x8]; 8073 u8 local_port[0x8]; 8074 u8 sub_port[0x8]; 8075 u8 reserved_0[0x8]; 8076 8077 u8 reserved_1[0x20]; 8078 }; 8079 8080 struct mlx5_ifc_ppsc_reg_bits { 8081 u8 reserved_0[0x8]; 8082 u8 local_port[0x8]; 8083 u8 reserved_1[0x10]; 8084 8085 u8 reserved_2[0x60]; 8086 8087 u8 reserved_3[0x1c]; 8088 u8 wrps_admin[0x4]; 8089 8090 u8 reserved_4[0x1c]; 8091 u8 wrps_status[0x4]; 8092 8093 u8 up_th_vld[0x1]; 8094 u8 down_th_vld[0x1]; 8095 u8 reserved_5[0x6]; 8096 u8 up_threshold[0x8]; 8097 u8 reserved_6[0x8]; 8098 u8 down_threshold[0x8]; 8099 8100 u8 reserved_7[0x20]; 8101 8102 u8 reserved_8[0x1c]; 8103 u8 srps_admin[0x4]; 8104 8105 u8 reserved_9[0x60]; 8106 }; 8107 8108 struct mlx5_ifc_pplr_reg_bits { 8109 u8 reserved_0[0x8]; 8110 u8 local_port[0x8]; 8111 u8 reserved_1[0x10]; 8112 8113 u8 reserved_2[0x8]; 8114 u8 lb_cap[0x8]; 8115 u8 reserved_3[0x8]; 8116 u8 lb_en[0x8]; 8117 }; 8118 8119 struct mlx5_ifc_pplm_reg_bits { 8120 u8 reserved_at_0[0x8]; 8121 u8 local_port[0x8]; 8122 u8 reserved_at_10[0x10]; 8123 8124 u8 reserved_at_20[0x20]; 8125 8126 u8 port_profile_mode[0x8]; 8127 u8 static_port_profile[0x8]; 8128 u8 active_port_profile[0x8]; 8129 u8 reserved_at_58[0x8]; 8130 8131 u8 retransmission_active[0x8]; 8132 u8 fec_mode_active[0x18]; 8133 8134 u8 rs_fec_correction_bypass_cap[0x4]; 8135 u8 reserved_at_84[0x8]; 8136 u8 fec_override_cap_56g[0x4]; 8137 u8 fec_override_cap_100g[0x4]; 8138 u8 fec_override_cap_50g[0x4]; 8139 u8 fec_override_cap_25g[0x4]; 8140 u8 fec_override_cap_10g_40g[0x4]; 8141 8142 u8 rs_fec_correction_bypass_admin[0x4]; 8143 u8 reserved_at_a4[0x8]; 8144 u8 fec_override_admin_56g[0x4]; 8145 u8 fec_override_admin_100g[0x4]; 8146 u8 fec_override_admin_50g[0x4]; 8147 u8 fec_override_admin_25g[0x4]; 8148 u8 fec_override_admin_10g_40g[0x4]; 8149 8150 u8 fec_override_cap_400g_8x[0x10]; 8151 u8 fec_override_cap_200g_4x[0x10]; 8152 u8 fec_override_cap_100g_2x[0x10]; 8153 u8 fec_override_cap_50g_1x[0x10]; 8154 8155 u8 fec_override_admin_400g_8x[0x10]; 8156 u8 fec_override_admin_200g_4x[0x10]; 8157 u8 fec_override_admin_100g_2x[0x10]; 8158 u8 fec_override_admin_50g_1x[0x10]; 8159 8160 u8 reserved_at_140[0xC0]; 8161 }; 8162 8163 struct mlx5_ifc_ppll_reg_bits { 8164 u8 num_pll_groups[0x8]; 8165 u8 pll_group[0x8]; 8166 u8 reserved_0[0x4]; 8167 u8 num_plls[0x4]; 8168 u8 reserved_1[0x8]; 8169 8170 u8 reserved_2[0x1f]; 8171 u8 ae[0x1]; 8172 8173 u8 pll_status[4][0x40]; 8174 }; 8175 8176 struct mlx5_ifc_ppad_reg_bits { 8177 u8 reserved_0[0x3]; 8178 u8 single_mac[0x1]; 8179 u8 reserved_1[0x4]; 8180 u8 local_port[0x8]; 8181 u8 mac_47_32[0x10]; 8182 8183 u8 mac_31_0[0x20]; 8184 8185 u8 reserved_2[0x40]; 8186 }; 8187 8188 struct mlx5_ifc_pmtu_reg_bits { 8189 u8 reserved_0[0x8]; 8190 u8 local_port[0x8]; 8191 u8 reserved_1[0x10]; 8192 8193 u8 max_mtu[0x10]; 8194 u8 reserved_2[0x10]; 8195 8196 u8 admin_mtu[0x10]; 8197 u8 reserved_3[0x10]; 8198 8199 u8 oper_mtu[0x10]; 8200 u8 reserved_4[0x10]; 8201 }; 8202 8203 struct mlx5_ifc_pmpr_reg_bits { 8204 u8 reserved_0[0x8]; 8205 u8 module[0x8]; 8206 u8 reserved_1[0x10]; 8207 8208 u8 reserved_2[0x18]; 8209 u8 attenuation_5g[0x8]; 8210 8211 u8 reserved_3[0x18]; 8212 u8 attenuation_7g[0x8]; 8213 8214 u8 reserved_4[0x18]; 8215 u8 attenuation_12g[0x8]; 8216 }; 8217 8218 struct mlx5_ifc_pmpe_reg_bits { 8219 u8 reserved_0[0x8]; 8220 u8 module[0x8]; 8221 u8 reserved_1[0xc]; 8222 u8 module_status[0x4]; 8223 8224 u8 reserved_2[0x14]; 8225 u8 error_type[0x4]; 8226 u8 reserved_3[0x8]; 8227 8228 u8 reserved_4[0x40]; 8229 }; 8230 8231 struct mlx5_ifc_pmpc_reg_bits { 8232 u8 module_state_updated[32][0x8]; 8233 }; 8234 8235 struct mlx5_ifc_pmlpn_reg_bits { 8236 u8 reserved_0[0x4]; 8237 u8 mlpn_status[0x4]; 8238 u8 local_port[0x8]; 8239 u8 reserved_1[0x10]; 8240 8241 u8 e[0x1]; 8242 u8 reserved_2[0x1f]; 8243 }; 8244 8245 struct mlx5_ifc_pmlp_reg_bits { 8246 u8 rxtx[0x1]; 8247 u8 reserved_0[0x7]; 8248 u8 local_port[0x8]; 8249 u8 reserved_1[0x8]; 8250 u8 width[0x8]; 8251 8252 u8 lane0_module_mapping[0x20]; 8253 8254 u8 lane1_module_mapping[0x20]; 8255 8256 u8 lane2_module_mapping[0x20]; 8257 8258 u8 lane3_module_mapping[0x20]; 8259 8260 u8 reserved_2[0x160]; 8261 }; 8262 8263 struct mlx5_ifc_pmaos_reg_bits { 8264 u8 reserved_0[0x8]; 8265 u8 module[0x8]; 8266 u8 reserved_1[0x4]; 8267 u8 admin_status[0x4]; 8268 u8 reserved_2[0x4]; 8269 u8 oper_status[0x4]; 8270 8271 u8 ase[0x1]; 8272 u8 ee[0x1]; 8273 u8 reserved_3[0x12]; 8274 u8 error_type[0x4]; 8275 u8 reserved_4[0x6]; 8276 u8 e[0x2]; 8277 8278 u8 reserved_5[0x40]; 8279 }; 8280 8281 struct mlx5_ifc_plpc_reg_bits { 8282 u8 reserved_0[0x4]; 8283 u8 profile_id[0xc]; 8284 u8 reserved_1[0x4]; 8285 u8 proto_mask[0x4]; 8286 u8 reserved_2[0x8]; 8287 8288 u8 reserved_3[0x10]; 8289 u8 lane_speed[0x10]; 8290 8291 u8 reserved_4[0x17]; 8292 u8 lpbf[0x1]; 8293 u8 fec_mode_policy[0x8]; 8294 8295 u8 retransmission_capability[0x8]; 8296 u8 fec_mode_capability[0x18]; 8297 8298 u8 retransmission_support_admin[0x8]; 8299 u8 fec_mode_support_admin[0x18]; 8300 8301 u8 retransmission_request_admin[0x8]; 8302 u8 fec_mode_request_admin[0x18]; 8303 8304 u8 reserved_5[0x80]; 8305 }; 8306 8307 struct mlx5_ifc_pll_status_data_bits { 8308 u8 reserved_0[0x1]; 8309 u8 lock_cal[0x1]; 8310 u8 lock_status[0x2]; 8311 u8 reserved_1[0x2]; 8312 u8 algo_f_ctrl[0xa]; 8313 u8 analog_algo_num_var[0x6]; 8314 u8 f_ctrl_measure[0xa]; 8315 8316 u8 reserved_2[0x2]; 8317 u8 analog_var[0x6]; 8318 u8 reserved_3[0x2]; 8319 u8 high_var[0x6]; 8320 u8 reserved_4[0x2]; 8321 u8 low_var[0x6]; 8322 u8 reserved_5[0x2]; 8323 u8 mid_val[0x6]; 8324 }; 8325 8326 struct mlx5_ifc_plib_reg_bits { 8327 u8 reserved_0[0x8]; 8328 u8 local_port[0x8]; 8329 u8 reserved_1[0x8]; 8330 u8 ib_port[0x8]; 8331 8332 u8 reserved_2[0x60]; 8333 }; 8334 8335 struct mlx5_ifc_plbf_reg_bits { 8336 u8 reserved_0[0x8]; 8337 u8 local_port[0x8]; 8338 u8 reserved_1[0xd]; 8339 u8 lbf_mode[0x3]; 8340 8341 u8 reserved_2[0x20]; 8342 }; 8343 8344 struct mlx5_ifc_pipg_reg_bits { 8345 u8 reserved_0[0x8]; 8346 u8 local_port[0x8]; 8347 u8 reserved_1[0x10]; 8348 8349 u8 dic[0x1]; 8350 u8 reserved_2[0x19]; 8351 u8 ipg[0x4]; 8352 u8 reserved_3[0x2]; 8353 }; 8354 8355 struct mlx5_ifc_pifr_reg_bits { 8356 u8 reserved_0[0x8]; 8357 u8 local_port[0x8]; 8358 u8 reserved_1[0x10]; 8359 8360 u8 reserved_2[0xe0]; 8361 8362 u8 port_filter[8][0x20]; 8363 8364 u8 port_filter_update_en[8][0x20]; 8365 }; 8366 8367 struct mlx5_ifc_phys_layer_cntrs_bits { 8368 u8 time_since_last_clear_high[0x20]; 8369 8370 u8 time_since_last_clear_low[0x20]; 8371 8372 u8 symbol_errors_high[0x20]; 8373 8374 u8 symbol_errors_low[0x20]; 8375 8376 u8 sync_headers_errors_high[0x20]; 8377 8378 u8 sync_headers_errors_low[0x20]; 8379 8380 u8 edpl_bip_errors_lane0_high[0x20]; 8381 8382 u8 edpl_bip_errors_lane0_low[0x20]; 8383 8384 u8 edpl_bip_errors_lane1_high[0x20]; 8385 8386 u8 edpl_bip_errors_lane1_low[0x20]; 8387 8388 u8 edpl_bip_errors_lane2_high[0x20]; 8389 8390 u8 edpl_bip_errors_lane2_low[0x20]; 8391 8392 u8 edpl_bip_errors_lane3_high[0x20]; 8393 8394 u8 edpl_bip_errors_lane3_low[0x20]; 8395 8396 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 8397 8398 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 8399 8400 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 8401 8402 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 8403 8404 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 8405 8406 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 8407 8408 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 8409 8410 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 8411 8412 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 8413 8414 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 8415 8416 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 8417 8418 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 8419 8420 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 8421 8422 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 8423 8424 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 8425 8426 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 8427 8428 u8 rs_fec_corrected_blocks_high[0x20]; 8429 8430 u8 rs_fec_corrected_blocks_low[0x20]; 8431 8432 u8 rs_fec_uncorrectable_blocks_high[0x20]; 8433 8434 u8 rs_fec_uncorrectable_blocks_low[0x20]; 8435 8436 u8 rs_fec_no_errors_blocks_high[0x20]; 8437 8438 u8 rs_fec_no_errors_blocks_low[0x20]; 8439 8440 u8 rs_fec_single_error_blocks_high[0x20]; 8441 8442 u8 rs_fec_single_error_blocks_low[0x20]; 8443 8444 u8 rs_fec_corrected_symbols_total_high[0x20]; 8445 8446 u8 rs_fec_corrected_symbols_total_low[0x20]; 8447 8448 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 8449 8450 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 8451 8452 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 8453 8454 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 8455 8456 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 8457 8458 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 8459 8460 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 8461 8462 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 8463 8464 u8 link_down_events[0x20]; 8465 8466 u8 successful_recovery_events[0x20]; 8467 8468 u8 reserved_0[0x180]; 8469 }; 8470 8471 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 8472 u8 symbol_error_counter[0x10]; 8473 8474 u8 link_error_recovery_counter[0x8]; 8475 8476 u8 link_downed_counter[0x8]; 8477 8478 u8 port_rcv_errors[0x10]; 8479 8480 u8 port_rcv_remote_physical_errors[0x10]; 8481 8482 u8 port_rcv_switch_relay_errors[0x10]; 8483 8484 u8 port_xmit_discards[0x10]; 8485 8486 u8 port_xmit_constraint_errors[0x8]; 8487 8488 u8 port_rcv_constraint_errors[0x8]; 8489 8490 u8 reserved_at_70[0x8]; 8491 8492 u8 link_overrun_errors[0x8]; 8493 8494 u8 reserved_at_80[0x10]; 8495 8496 u8 vl_15_dropped[0x10]; 8497 8498 u8 reserved_at_a0[0xa0]; 8499 }; 8500 8501 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 8502 u8 time_since_last_clear_high[0x20]; 8503 8504 u8 time_since_last_clear_low[0x20]; 8505 8506 u8 phy_received_bits_high[0x20]; 8507 8508 u8 phy_received_bits_low[0x20]; 8509 8510 u8 phy_symbol_errors_high[0x20]; 8511 8512 u8 phy_symbol_errors_low[0x20]; 8513 8514 u8 phy_corrected_bits_high[0x20]; 8515 8516 u8 phy_corrected_bits_low[0x20]; 8517 8518 u8 phy_corrected_bits_lane0_high[0x20]; 8519 8520 u8 phy_corrected_bits_lane0_low[0x20]; 8521 8522 u8 phy_corrected_bits_lane1_high[0x20]; 8523 8524 u8 phy_corrected_bits_lane1_low[0x20]; 8525 8526 u8 phy_corrected_bits_lane2_high[0x20]; 8527 8528 u8 phy_corrected_bits_lane2_low[0x20]; 8529 8530 u8 phy_corrected_bits_lane3_high[0x20]; 8531 8532 u8 phy_corrected_bits_lane3_low[0x20]; 8533 8534 u8 reserved_at_200[0x5c0]; 8535 }; 8536 8537 struct mlx5_ifc_infiniband_port_cntrs_bits { 8538 u8 symbol_error_counter[0x10]; 8539 u8 link_error_recovery_counter[0x8]; 8540 u8 link_downed_counter[0x8]; 8541 8542 u8 port_rcv_errors[0x10]; 8543 u8 port_rcv_remote_physical_errors[0x10]; 8544 8545 u8 port_rcv_switch_relay_errors[0x10]; 8546 u8 port_xmit_discards[0x10]; 8547 8548 u8 port_xmit_constraint_errors[0x8]; 8549 u8 port_rcv_constraint_errors[0x8]; 8550 u8 reserved_0[0x8]; 8551 u8 local_link_integrity_errors[0x4]; 8552 u8 excessive_buffer_overrun_errors[0x4]; 8553 8554 u8 reserved_1[0x10]; 8555 u8 vl_15_dropped[0x10]; 8556 8557 u8 port_xmit_data[0x20]; 8558 8559 u8 port_rcv_data[0x20]; 8560 8561 u8 port_xmit_pkts[0x20]; 8562 8563 u8 port_rcv_pkts[0x20]; 8564 8565 u8 port_xmit_wait[0x20]; 8566 8567 u8 reserved_2[0x680]; 8568 }; 8569 8570 struct mlx5_ifc_phrr_reg_bits { 8571 u8 clr[0x1]; 8572 u8 reserved_0[0x7]; 8573 u8 local_port[0x8]; 8574 u8 reserved_1[0x10]; 8575 8576 u8 hist_group[0x8]; 8577 u8 reserved_2[0x10]; 8578 u8 hist_id[0x8]; 8579 8580 u8 reserved_3[0x40]; 8581 8582 u8 time_since_last_clear_high[0x20]; 8583 8584 u8 time_since_last_clear_low[0x20]; 8585 8586 u8 bin[10][0x20]; 8587 }; 8588 8589 struct mlx5_ifc_phbr_for_prio_reg_bits { 8590 u8 reserved_0[0x18]; 8591 u8 prio[0x8]; 8592 }; 8593 8594 struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8595 u8 reserved_0[0x18]; 8596 u8 tclass[0x8]; 8597 }; 8598 8599 struct mlx5_ifc_phbr_binding_reg_bits { 8600 u8 opcode[0x4]; 8601 u8 reserved_0[0x4]; 8602 u8 local_port[0x8]; 8603 u8 pnat[0x2]; 8604 u8 reserved_1[0xe]; 8605 8606 u8 hist_group[0x8]; 8607 u8 reserved_2[0x10]; 8608 u8 hist_id[0x8]; 8609 8610 u8 reserved_3[0x10]; 8611 u8 hist_type[0x10]; 8612 8613 u8 hist_parameters[0x20]; 8614 8615 u8 hist_min_value[0x20]; 8616 8617 u8 hist_max_value[0x20]; 8618 8619 u8 sample_time[0x20]; 8620 }; 8621 8622 enum { 8623 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 8624 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 8625 }; 8626 8627 struct mlx5_ifc_pfcc_reg_bits { 8628 u8 dcbx_operation_type[0x2]; 8629 u8 cap_local_admin[0x1]; 8630 u8 cap_remote_admin[0x1]; 8631 u8 reserved_0[0x4]; 8632 u8 local_port[0x8]; 8633 u8 pnat[0x2]; 8634 u8 reserved_1[0xc]; 8635 u8 shl_cap[0x1]; 8636 u8 shl_opr[0x1]; 8637 8638 u8 ppan[0x4]; 8639 u8 reserved_2[0x4]; 8640 u8 prio_mask_tx[0x8]; 8641 u8 reserved_3[0x8]; 8642 u8 prio_mask_rx[0x8]; 8643 8644 u8 pptx[0x1]; 8645 u8 aptx[0x1]; 8646 u8 reserved_4[0x6]; 8647 u8 pfctx[0x8]; 8648 u8 reserved_5[0x8]; 8649 u8 cbftx[0x8]; 8650 8651 u8 pprx[0x1]; 8652 u8 aprx[0x1]; 8653 u8 reserved_6[0x6]; 8654 u8 pfcrx[0x8]; 8655 u8 reserved_7[0x8]; 8656 u8 cbfrx[0x8]; 8657 8658 u8 device_stall_minor_watermark[0x10]; 8659 u8 device_stall_critical_watermark[0x10]; 8660 8661 u8 reserved_8[0x60]; 8662 }; 8663 8664 struct mlx5_ifc_pelc_reg_bits { 8665 u8 op[0x4]; 8666 u8 reserved_0[0x4]; 8667 u8 local_port[0x8]; 8668 u8 reserved_1[0x10]; 8669 8670 u8 op_admin[0x8]; 8671 u8 op_capability[0x8]; 8672 u8 op_request[0x8]; 8673 u8 op_active[0x8]; 8674 8675 u8 admin[0x40]; 8676 8677 u8 capability[0x40]; 8678 8679 u8 request[0x40]; 8680 8681 u8 active[0x40]; 8682 8683 u8 reserved_2[0x80]; 8684 }; 8685 8686 struct mlx5_ifc_peir_reg_bits { 8687 u8 reserved_0[0x8]; 8688 u8 local_port[0x8]; 8689 u8 reserved_1[0x10]; 8690 8691 u8 reserved_2[0xc]; 8692 u8 error_count[0x4]; 8693 u8 reserved_3[0x10]; 8694 8695 u8 reserved_4[0xc]; 8696 u8 lane[0x4]; 8697 u8 reserved_5[0x8]; 8698 u8 error_type[0x8]; 8699 }; 8700 8701 struct mlx5_ifc_qcam_access_reg_cap_mask { 8702 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8703 u8 qpdpm[0x1]; 8704 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8705 u8 qdpm[0x1]; 8706 u8 qpts[0x1]; 8707 u8 qcap[0x1]; 8708 u8 qcam_access_reg_cap_mask_0[0x1]; 8709 }; 8710 8711 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8712 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8713 u8 qpts_trust_both[0x1]; 8714 }; 8715 8716 struct mlx5_ifc_qcam_reg_bits { 8717 u8 reserved_at_0[0x8]; 8718 u8 feature_group[0x8]; 8719 u8 reserved_at_10[0x8]; 8720 u8 access_reg_group[0x8]; 8721 u8 reserved_at_20[0x20]; 8722 8723 union { 8724 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8725 u8 reserved_at_0[0x80]; 8726 } qos_access_reg_cap_mask; 8727 8728 u8 reserved_at_c0[0x80]; 8729 8730 union { 8731 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8732 u8 reserved_at_0[0x80]; 8733 } qos_feature_cap_mask; 8734 8735 u8 reserved_at_1c0[0x80]; 8736 }; 8737 8738 struct mlx5_ifc_pcam_enhanced_features_bits { 8739 u8 reserved_at_0[0x6d]; 8740 u8 rx_icrc_encapsulated_counter[0x1]; 8741 u8 reserved_at_6e[0x4]; 8742 u8 ptys_extended_ethernet[0x1]; 8743 u8 reserved_at_73[0x3]; 8744 u8 pfcc_mask[0x1]; 8745 u8 reserved_at_77[0x3]; 8746 u8 per_lane_error_counters[0x1]; 8747 u8 rx_buffer_fullness_counters[0x1]; 8748 u8 ptys_connector_type[0x1]; 8749 u8 reserved_at_7d[0x1]; 8750 u8 ppcnt_discard_group[0x1]; 8751 u8 ppcnt_statistical_group[0x1]; 8752 }; 8753 8754 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8755 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8756 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8757 8758 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 8759 u8 pplm[0x1]; 8760 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8761 8762 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8763 u8 pbmc[0x1]; 8764 u8 pptb[0x1]; 8765 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8766 u8 ppcnt[0x1]; 8767 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8768 }; 8769 8770 struct mlx5_ifc_pcam_reg_bits { 8771 u8 reserved_at_0[0x8]; 8772 u8 feature_group[0x8]; 8773 u8 reserved_at_10[0x8]; 8774 u8 access_reg_group[0x8]; 8775 8776 u8 reserved_at_20[0x20]; 8777 8778 union { 8779 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8780 u8 reserved_at_0[0x80]; 8781 } port_access_reg_cap_mask; 8782 8783 u8 reserved_at_c0[0x80]; 8784 8785 union { 8786 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8787 u8 reserved_at_0[0x80]; 8788 } feature_cap_mask; 8789 8790 u8 reserved_at_1c0[0xc0]; 8791 }; 8792 8793 struct mlx5_ifc_mcam_enhanced_features_bits { 8794 u8 reserved_at_0[0x6e]; 8795 u8 pcie_status_and_power[0x1]; 8796 u8 reserved_at_111[0x10]; 8797 u8 pcie_performance_group[0x1]; 8798 }; 8799 8800 struct mlx5_ifc_mcam_access_reg_bits { 8801 u8 reserved_at_0[0x1c]; 8802 u8 mcda[0x1]; 8803 u8 mcc[0x1]; 8804 u8 mcqi[0x1]; 8805 u8 reserved_at_1f[0x1]; 8806 8807 u8 regs_95_to_64[0x20]; 8808 u8 regs_63_to_32[0x20]; 8809 u8 regs_31_to_0[0x20]; 8810 }; 8811 8812 struct mlx5_ifc_mcam_reg_bits { 8813 u8 reserved_at_0[0x8]; 8814 u8 feature_group[0x8]; 8815 u8 reserved_at_10[0x8]; 8816 u8 access_reg_group[0x8]; 8817 8818 u8 reserved_at_20[0x20]; 8819 8820 union { 8821 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8822 u8 reserved_at_0[0x80]; 8823 } mng_access_reg_cap_mask; 8824 8825 u8 reserved_at_c0[0x80]; 8826 8827 union { 8828 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8829 u8 reserved_at_0[0x80]; 8830 } mng_feature_cap_mask; 8831 8832 u8 reserved_at_1c0[0x80]; 8833 }; 8834 8835 struct mlx5_ifc_pcap_reg_bits { 8836 u8 reserved_0[0x8]; 8837 u8 local_port[0x8]; 8838 u8 reserved_1[0x10]; 8839 8840 u8 port_capability_mask[4][0x20]; 8841 }; 8842 8843 struct mlx5_ifc_pbmc_reg_bits { 8844 u8 reserved_at_0[0x8]; 8845 u8 local_port[0x8]; 8846 u8 reserved_at_10[0x10]; 8847 8848 u8 xoff_timer_value[0x10]; 8849 u8 xoff_refresh[0x10]; 8850 8851 u8 reserved_at_40[0x9]; 8852 u8 fullness_threshold[0x7]; 8853 u8 port_buffer_size[0x10]; 8854 8855 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8856 8857 u8 reserved_at_2e0[0x40]; 8858 }; 8859 8860 struct mlx5_ifc_paos_reg_bits { 8861 u8 swid[0x8]; 8862 u8 local_port[0x8]; 8863 u8 reserved_0[0x4]; 8864 u8 admin_status[0x4]; 8865 u8 reserved_1[0x4]; 8866 u8 oper_status[0x4]; 8867 8868 u8 ase[0x1]; 8869 u8 ee[0x1]; 8870 u8 reserved_2[0x1c]; 8871 u8 e[0x2]; 8872 8873 u8 reserved_3[0x40]; 8874 }; 8875 8876 struct mlx5_ifc_pamp_reg_bits { 8877 u8 reserved_0[0x8]; 8878 u8 opamp_group[0x8]; 8879 u8 reserved_1[0xc]; 8880 u8 opamp_group_type[0x4]; 8881 8882 u8 start_index[0x10]; 8883 u8 reserved_2[0x4]; 8884 u8 num_of_indices[0xc]; 8885 8886 u8 index_data[18][0x10]; 8887 }; 8888 8889 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 8890 u8 llr_rx_cells_high[0x20]; 8891 8892 u8 llr_rx_cells_low[0x20]; 8893 8894 u8 llr_rx_error_high[0x20]; 8895 8896 u8 llr_rx_error_low[0x20]; 8897 8898 u8 llr_rx_crc_error_high[0x20]; 8899 8900 u8 llr_rx_crc_error_low[0x20]; 8901 8902 u8 llr_tx_cells_high[0x20]; 8903 8904 u8 llr_tx_cells_low[0x20]; 8905 8906 u8 llr_tx_ret_cells_high[0x20]; 8907 8908 u8 llr_tx_ret_cells_low[0x20]; 8909 8910 u8 llr_tx_ret_events_high[0x20]; 8911 8912 u8 llr_tx_ret_events_low[0x20]; 8913 8914 u8 reserved_0[0x640]; 8915 }; 8916 8917 struct mlx5_ifc_mtmp_reg_bits { 8918 u8 i[0x1]; 8919 u8 reserved_at_1[0x18]; 8920 u8 sensor_index[0x7]; 8921 8922 u8 reserved_at_20[0x10]; 8923 u8 temperature[0x10]; 8924 8925 u8 mte[0x1]; 8926 u8 mtr[0x1]; 8927 u8 reserved_at_42[0x0e]; 8928 u8 max_temperature[0x10]; 8929 8930 u8 tee[0x2]; 8931 u8 reserved_at_62[0x0e]; 8932 u8 temperature_threshold_hi[0x10]; 8933 8934 u8 reserved_at_80[0x10]; 8935 u8 temperature_threshold_lo[0x10]; 8936 8937 u8 reserved_at_100[0x20]; 8938 8939 u8 sensor_name[0x40]; 8940 }; 8941 8942 struct mlx5_ifc_lane_2_module_mapping_bits { 8943 u8 reserved_0[0x6]; 8944 u8 rx_lane[0x2]; 8945 u8 reserved_1[0x6]; 8946 u8 tx_lane[0x2]; 8947 u8 reserved_2[0x8]; 8948 u8 module[0x8]; 8949 }; 8950 8951 struct mlx5_ifc_eth_per_traffic_class_layout_bits { 8952 u8 transmit_queue_high[0x20]; 8953 8954 u8 transmit_queue_low[0x20]; 8955 8956 u8 reserved_0[0x780]; 8957 }; 8958 8959 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 8960 u8 no_buffer_discard_uc_high[0x20]; 8961 8962 u8 no_buffer_discard_uc_low[0x20]; 8963 8964 u8 wred_discard_high[0x20]; 8965 8966 u8 wred_discard_low[0x20]; 8967 8968 u8 reserved_0[0x740]; 8969 }; 8970 8971 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 8972 u8 rx_octets_high[0x20]; 8973 8974 u8 rx_octets_low[0x20]; 8975 8976 u8 reserved_0[0xc0]; 8977 8978 u8 rx_frames_high[0x20]; 8979 8980 u8 rx_frames_low[0x20]; 8981 8982 u8 tx_octets_high[0x20]; 8983 8984 u8 tx_octets_low[0x20]; 8985 8986 u8 reserved_1[0xc0]; 8987 8988 u8 tx_frames_high[0x20]; 8989 8990 u8 tx_frames_low[0x20]; 8991 8992 u8 rx_pause_high[0x20]; 8993 8994 u8 rx_pause_low[0x20]; 8995 8996 u8 rx_pause_duration_high[0x20]; 8997 8998 u8 rx_pause_duration_low[0x20]; 8999 9000 u8 tx_pause_high[0x20]; 9001 9002 u8 tx_pause_low[0x20]; 9003 9004 u8 tx_pause_duration_high[0x20]; 9005 9006 u8 tx_pause_duration_low[0x20]; 9007 9008 u8 rx_pause_transition_high[0x20]; 9009 9010 u8 rx_pause_transition_low[0x20]; 9011 9012 u8 rx_discards_high[0x20]; 9013 9014 u8 rx_discards_low[0x20]; 9015 9016 u8 device_stall_minor_watermark_cnt_high[0x20]; 9017 9018 u8 device_stall_minor_watermark_cnt_low[0x20]; 9019 9020 u8 device_stall_critical_watermark_cnt_high[0x20]; 9021 9022 u8 device_stall_critical_watermark_cnt_low[0x20]; 9023 9024 u8 reserved_2[0x340]; 9025 }; 9026 9027 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 9028 u8 port_transmit_wait_high[0x20]; 9029 9030 u8 port_transmit_wait_low[0x20]; 9031 9032 u8 ecn_marked_high[0x20]; 9033 9034 u8 ecn_marked_low[0x20]; 9035 9036 u8 no_buffer_discard_mc_high[0x20]; 9037 9038 u8 no_buffer_discard_mc_low[0x20]; 9039 9040 u8 rx_ebp_high[0x20]; 9041 9042 u8 rx_ebp_low[0x20]; 9043 9044 u8 tx_ebp_high[0x20]; 9045 9046 u8 tx_ebp_low[0x20]; 9047 9048 u8 rx_buffer_almost_full_high[0x20]; 9049 9050 u8 rx_buffer_almost_full_low[0x20]; 9051 9052 u8 rx_buffer_full_high[0x20]; 9053 9054 u8 rx_buffer_full_low[0x20]; 9055 9056 u8 rx_icrc_encapsulated_high[0x20]; 9057 9058 u8 rx_icrc_encapsulated_low[0x20]; 9059 9060 u8 reserved_0[0x80]; 9061 9062 u8 tx_stats_pkts64octets_high[0x20]; 9063 9064 u8 tx_stats_pkts64octets_low[0x20]; 9065 9066 u8 tx_stats_pkts65to127octets_high[0x20]; 9067 9068 u8 tx_stats_pkts65to127octets_low[0x20]; 9069 9070 u8 tx_stats_pkts128to255octets_high[0x20]; 9071 9072 u8 tx_stats_pkts128to255octets_low[0x20]; 9073 9074 u8 tx_stats_pkts256to511octets_high[0x20]; 9075 9076 u8 tx_stats_pkts256to511octets_low[0x20]; 9077 9078 u8 tx_stats_pkts512to1023octets_high[0x20]; 9079 9080 u8 tx_stats_pkts512to1023octets_low[0x20]; 9081 9082 u8 tx_stats_pkts1024to1518octets_high[0x20]; 9083 9084 u8 tx_stats_pkts1024to1518octets_low[0x20]; 9085 9086 u8 tx_stats_pkts1519to2047octets_high[0x20]; 9087 9088 u8 tx_stats_pkts1519to2047octets_low[0x20]; 9089 9090 u8 tx_stats_pkts2048to4095octets_high[0x20]; 9091 9092 u8 tx_stats_pkts2048to4095octets_low[0x20]; 9093 9094 u8 tx_stats_pkts4096to8191octets_high[0x20]; 9095 9096 u8 tx_stats_pkts4096to8191octets_low[0x20]; 9097 9098 u8 tx_stats_pkts8192to10239octets_high[0x20]; 9099 9100 u8 tx_stats_pkts8192to10239octets_low[0x20]; 9101 9102 u8 reserved_1[0x2C0]; 9103 }; 9104 9105 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 9106 u8 a_frames_transmitted_ok_high[0x20]; 9107 9108 u8 a_frames_transmitted_ok_low[0x20]; 9109 9110 u8 a_frames_received_ok_high[0x20]; 9111 9112 u8 a_frames_received_ok_low[0x20]; 9113 9114 u8 a_frame_check_sequence_errors_high[0x20]; 9115 9116 u8 a_frame_check_sequence_errors_low[0x20]; 9117 9118 u8 a_alignment_errors_high[0x20]; 9119 9120 u8 a_alignment_errors_low[0x20]; 9121 9122 u8 a_octets_transmitted_ok_high[0x20]; 9123 9124 u8 a_octets_transmitted_ok_low[0x20]; 9125 9126 u8 a_octets_received_ok_high[0x20]; 9127 9128 u8 a_octets_received_ok_low[0x20]; 9129 9130 u8 a_multicast_frames_xmitted_ok_high[0x20]; 9131 9132 u8 a_multicast_frames_xmitted_ok_low[0x20]; 9133 9134 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 9135 9136 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 9137 9138 u8 a_multicast_frames_received_ok_high[0x20]; 9139 9140 u8 a_multicast_frames_received_ok_low[0x20]; 9141 9142 u8 a_broadcast_frames_recieved_ok_high[0x20]; 9143 9144 u8 a_broadcast_frames_recieved_ok_low[0x20]; 9145 9146 u8 a_in_range_length_errors_high[0x20]; 9147 9148 u8 a_in_range_length_errors_low[0x20]; 9149 9150 u8 a_out_of_range_length_field_high[0x20]; 9151 9152 u8 a_out_of_range_length_field_low[0x20]; 9153 9154 u8 a_frame_too_long_errors_high[0x20]; 9155 9156 u8 a_frame_too_long_errors_low[0x20]; 9157 9158 u8 a_symbol_error_during_carrier_high[0x20]; 9159 9160 u8 a_symbol_error_during_carrier_low[0x20]; 9161 9162 u8 a_mac_control_frames_transmitted_high[0x20]; 9163 9164 u8 a_mac_control_frames_transmitted_low[0x20]; 9165 9166 u8 a_mac_control_frames_received_high[0x20]; 9167 9168 u8 a_mac_control_frames_received_low[0x20]; 9169 9170 u8 a_unsupported_opcodes_received_high[0x20]; 9171 9172 u8 a_unsupported_opcodes_received_low[0x20]; 9173 9174 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 9175 9176 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 9177 9178 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 9179 9180 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 9181 9182 u8 reserved_0[0x300]; 9183 }; 9184 9185 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 9186 u8 dot3stats_alignment_errors_high[0x20]; 9187 9188 u8 dot3stats_alignment_errors_low[0x20]; 9189 9190 u8 dot3stats_fcs_errors_high[0x20]; 9191 9192 u8 dot3stats_fcs_errors_low[0x20]; 9193 9194 u8 dot3stats_single_collision_frames_high[0x20]; 9195 9196 u8 dot3stats_single_collision_frames_low[0x20]; 9197 9198 u8 dot3stats_multiple_collision_frames_high[0x20]; 9199 9200 u8 dot3stats_multiple_collision_frames_low[0x20]; 9201 9202 u8 dot3stats_sqe_test_errors_high[0x20]; 9203 9204 u8 dot3stats_sqe_test_errors_low[0x20]; 9205 9206 u8 dot3stats_deferred_transmissions_high[0x20]; 9207 9208 u8 dot3stats_deferred_transmissions_low[0x20]; 9209 9210 u8 dot3stats_late_collisions_high[0x20]; 9211 9212 u8 dot3stats_late_collisions_low[0x20]; 9213 9214 u8 dot3stats_excessive_collisions_high[0x20]; 9215 9216 u8 dot3stats_excessive_collisions_low[0x20]; 9217 9218 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 9219 9220 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 9221 9222 u8 dot3stats_carrier_sense_errors_high[0x20]; 9223 9224 u8 dot3stats_carrier_sense_errors_low[0x20]; 9225 9226 u8 dot3stats_frame_too_longs_high[0x20]; 9227 9228 u8 dot3stats_frame_too_longs_low[0x20]; 9229 9230 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 9231 9232 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 9233 9234 u8 dot3stats_symbol_errors_high[0x20]; 9235 9236 u8 dot3stats_symbol_errors_low[0x20]; 9237 9238 u8 dot3control_in_unknown_opcodes_high[0x20]; 9239 9240 u8 dot3control_in_unknown_opcodes_low[0x20]; 9241 9242 u8 dot3in_pause_frames_high[0x20]; 9243 9244 u8 dot3in_pause_frames_low[0x20]; 9245 9246 u8 dot3out_pause_frames_high[0x20]; 9247 9248 u8 dot3out_pause_frames_low[0x20]; 9249 9250 u8 reserved_0[0x3c0]; 9251 }; 9252 9253 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 9254 u8 if_in_octets_high[0x20]; 9255 9256 u8 if_in_octets_low[0x20]; 9257 9258 u8 if_in_ucast_pkts_high[0x20]; 9259 9260 u8 if_in_ucast_pkts_low[0x20]; 9261 9262 u8 if_in_discards_high[0x20]; 9263 9264 u8 if_in_discards_low[0x20]; 9265 9266 u8 if_in_errors_high[0x20]; 9267 9268 u8 if_in_errors_low[0x20]; 9269 9270 u8 if_in_unknown_protos_high[0x20]; 9271 9272 u8 if_in_unknown_protos_low[0x20]; 9273 9274 u8 if_out_octets_high[0x20]; 9275 9276 u8 if_out_octets_low[0x20]; 9277 9278 u8 if_out_ucast_pkts_high[0x20]; 9279 9280 u8 if_out_ucast_pkts_low[0x20]; 9281 9282 u8 if_out_discards_high[0x20]; 9283 9284 u8 if_out_discards_low[0x20]; 9285 9286 u8 if_out_errors_high[0x20]; 9287 9288 u8 if_out_errors_low[0x20]; 9289 9290 u8 if_in_multicast_pkts_high[0x20]; 9291 9292 u8 if_in_multicast_pkts_low[0x20]; 9293 9294 u8 if_in_broadcast_pkts_high[0x20]; 9295 9296 u8 if_in_broadcast_pkts_low[0x20]; 9297 9298 u8 if_out_multicast_pkts_high[0x20]; 9299 9300 u8 if_out_multicast_pkts_low[0x20]; 9301 9302 u8 if_out_broadcast_pkts_high[0x20]; 9303 9304 u8 if_out_broadcast_pkts_low[0x20]; 9305 9306 u8 reserved_0[0x480]; 9307 }; 9308 9309 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 9310 u8 ether_stats_drop_events_high[0x20]; 9311 9312 u8 ether_stats_drop_events_low[0x20]; 9313 9314 u8 ether_stats_octets_high[0x20]; 9315 9316 u8 ether_stats_octets_low[0x20]; 9317 9318 u8 ether_stats_pkts_high[0x20]; 9319 9320 u8 ether_stats_pkts_low[0x20]; 9321 9322 u8 ether_stats_broadcast_pkts_high[0x20]; 9323 9324 u8 ether_stats_broadcast_pkts_low[0x20]; 9325 9326 u8 ether_stats_multicast_pkts_high[0x20]; 9327 9328 u8 ether_stats_multicast_pkts_low[0x20]; 9329 9330 u8 ether_stats_crc_align_errors_high[0x20]; 9331 9332 u8 ether_stats_crc_align_errors_low[0x20]; 9333 9334 u8 ether_stats_undersize_pkts_high[0x20]; 9335 9336 u8 ether_stats_undersize_pkts_low[0x20]; 9337 9338 u8 ether_stats_oversize_pkts_high[0x20]; 9339 9340 u8 ether_stats_oversize_pkts_low[0x20]; 9341 9342 u8 ether_stats_fragments_high[0x20]; 9343 9344 u8 ether_stats_fragments_low[0x20]; 9345 9346 u8 ether_stats_jabbers_high[0x20]; 9347 9348 u8 ether_stats_jabbers_low[0x20]; 9349 9350 u8 ether_stats_collisions_high[0x20]; 9351 9352 u8 ether_stats_collisions_low[0x20]; 9353 9354 u8 ether_stats_pkts64octets_high[0x20]; 9355 9356 u8 ether_stats_pkts64octets_low[0x20]; 9357 9358 u8 ether_stats_pkts65to127octets_high[0x20]; 9359 9360 u8 ether_stats_pkts65to127octets_low[0x20]; 9361 9362 u8 ether_stats_pkts128to255octets_high[0x20]; 9363 9364 u8 ether_stats_pkts128to255octets_low[0x20]; 9365 9366 u8 ether_stats_pkts256to511octets_high[0x20]; 9367 9368 u8 ether_stats_pkts256to511octets_low[0x20]; 9369 9370 u8 ether_stats_pkts512to1023octets_high[0x20]; 9371 9372 u8 ether_stats_pkts512to1023octets_low[0x20]; 9373 9374 u8 ether_stats_pkts1024to1518octets_high[0x20]; 9375 9376 u8 ether_stats_pkts1024to1518octets_low[0x20]; 9377 9378 u8 ether_stats_pkts1519to2047octets_high[0x20]; 9379 9380 u8 ether_stats_pkts1519to2047octets_low[0x20]; 9381 9382 u8 ether_stats_pkts2048to4095octets_high[0x20]; 9383 9384 u8 ether_stats_pkts2048to4095octets_low[0x20]; 9385 9386 u8 ether_stats_pkts4096to8191octets_high[0x20]; 9387 9388 u8 ether_stats_pkts4096to8191octets_low[0x20]; 9389 9390 u8 ether_stats_pkts8192to10239octets_high[0x20]; 9391 9392 u8 ether_stats_pkts8192to10239octets_low[0x20]; 9393 9394 u8 reserved_0[0x280]; 9395 }; 9396 9397 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 9398 u8 symbol_error_counter[0x10]; 9399 u8 link_error_recovery_counter[0x8]; 9400 u8 link_downed_counter[0x8]; 9401 9402 u8 port_rcv_errors[0x10]; 9403 u8 port_rcv_remote_physical_errors[0x10]; 9404 9405 u8 port_rcv_switch_relay_errors[0x10]; 9406 u8 port_xmit_discards[0x10]; 9407 9408 u8 port_xmit_constraint_errors[0x8]; 9409 u8 port_rcv_constraint_errors[0x8]; 9410 u8 reserved_0[0x8]; 9411 u8 local_link_integrity_errors[0x4]; 9412 u8 excessive_buffer_overrun_errors[0x4]; 9413 9414 u8 reserved_1[0x10]; 9415 u8 vl_15_dropped[0x10]; 9416 9417 u8 port_xmit_data[0x20]; 9418 9419 u8 port_rcv_data[0x20]; 9420 9421 u8 port_xmit_pkts[0x20]; 9422 9423 u8 port_rcv_pkts[0x20]; 9424 9425 u8 port_xmit_wait[0x20]; 9426 9427 u8 reserved_2[0x680]; 9428 }; 9429 9430 struct mlx5_ifc_trc_tlb_reg_bits { 9431 u8 reserved_0[0x80]; 9432 9433 u8 tlb_addr[0][0x40]; 9434 }; 9435 9436 struct mlx5_ifc_trc_read_fifo_reg_bits { 9437 u8 reserved_0[0x10]; 9438 u8 requested_event_num[0x10]; 9439 9440 u8 reserved_1[0x20]; 9441 9442 u8 reserved_2[0x10]; 9443 u8 acual_event_num[0x10]; 9444 9445 u8 reserved_3[0x20]; 9446 9447 u8 event[0][0x40]; 9448 }; 9449 9450 struct mlx5_ifc_trc_lock_reg_bits { 9451 u8 reserved_0[0x1f]; 9452 u8 lock[0x1]; 9453 9454 u8 reserved_1[0x60]; 9455 }; 9456 9457 struct mlx5_ifc_trc_filter_reg_bits { 9458 u8 status[0x1]; 9459 u8 reserved_0[0xf]; 9460 u8 filter_index[0x10]; 9461 9462 u8 reserved_1[0x20]; 9463 9464 u8 filter_val[0x20]; 9465 9466 u8 reserved_2[0x1a0]; 9467 }; 9468 9469 struct mlx5_ifc_trc_event_reg_bits { 9470 u8 status[0x1]; 9471 u8 reserved_0[0xf]; 9472 u8 event_index[0x10]; 9473 9474 u8 reserved_1[0x20]; 9475 9476 u8 event_id[0x20]; 9477 9478 u8 event_selector_val[0x10]; 9479 u8 event_selector_size[0x10]; 9480 9481 u8 reserved_2[0x180]; 9482 }; 9483 9484 struct mlx5_ifc_trc_conf_reg_bits { 9485 u8 limit_en[0x1]; 9486 u8 reserved_0[0x3]; 9487 u8 dump_mode[0x4]; 9488 u8 reserved_1[0x15]; 9489 u8 state[0x3]; 9490 9491 u8 reserved_2[0x20]; 9492 9493 u8 limit_event_index[0x20]; 9494 9495 u8 mkey[0x20]; 9496 9497 u8 fifo_ready_ev_num[0x20]; 9498 9499 u8 reserved_3[0x160]; 9500 }; 9501 9502 struct mlx5_ifc_trc_cap_reg_bits { 9503 u8 reserved_0[0x18]; 9504 u8 dump_mode[0x8]; 9505 9506 u8 reserved_1[0x20]; 9507 9508 u8 num_of_events[0x10]; 9509 u8 num_of_filters[0x10]; 9510 9511 u8 fifo_size[0x20]; 9512 9513 u8 tlb_size[0x10]; 9514 u8 event_size[0x10]; 9515 9516 u8 reserved_2[0x160]; 9517 }; 9518 9519 struct mlx5_ifc_set_node_in_bits { 9520 u8 node_description[64][0x8]; 9521 }; 9522 9523 struct mlx5_ifc_register_power_settings_bits { 9524 u8 reserved_0[0x18]; 9525 u8 power_settings_level[0x8]; 9526 9527 u8 reserved_1[0x60]; 9528 }; 9529 9530 struct mlx5_ifc_register_host_endianess_bits { 9531 u8 he[0x1]; 9532 u8 reserved_0[0x1f]; 9533 9534 u8 reserved_1[0x60]; 9535 }; 9536 9537 struct mlx5_ifc_register_diag_buffer_ctrl_bits { 9538 u8 physical_address[0x40]; 9539 }; 9540 9541 struct mlx5_ifc_qtct_reg_bits { 9542 u8 operation_type[0x2]; 9543 u8 cap_local_admin[0x1]; 9544 u8 cap_remote_admin[0x1]; 9545 u8 reserved_0[0x4]; 9546 u8 port_number[0x8]; 9547 u8 reserved_1[0xd]; 9548 u8 prio[0x3]; 9549 9550 u8 reserved_2[0x1d]; 9551 u8 tclass[0x3]; 9552 }; 9553 9554 struct mlx5_ifc_qpdp_reg_bits { 9555 u8 reserved_0[0x8]; 9556 u8 port_number[0x8]; 9557 u8 reserved_1[0x10]; 9558 9559 u8 reserved_2[0x1d]; 9560 u8 pprio[0x3]; 9561 }; 9562 9563 struct mlx5_ifc_port_info_ro_fields_param_bits { 9564 u8 reserved_0[0x8]; 9565 u8 port[0x8]; 9566 u8 max_gid[0x10]; 9567 9568 u8 reserved_1[0x20]; 9569 9570 u8 port_guid[0x40]; 9571 }; 9572 9573 struct mlx5_ifc_nvqc_reg_bits { 9574 u8 type[0x20]; 9575 9576 u8 reserved_0[0x18]; 9577 u8 version[0x4]; 9578 u8 reserved_1[0x2]; 9579 u8 support_wr[0x1]; 9580 u8 support_rd[0x1]; 9581 }; 9582 9583 struct mlx5_ifc_nvia_reg_bits { 9584 u8 reserved_0[0x1d]; 9585 u8 target[0x3]; 9586 9587 u8 reserved_1[0x20]; 9588 }; 9589 9590 struct mlx5_ifc_nvdi_reg_bits { 9591 struct mlx5_ifc_config_item_bits configuration_item_header; 9592 }; 9593 9594 struct mlx5_ifc_nvda_reg_bits { 9595 struct mlx5_ifc_config_item_bits configuration_item_header; 9596 9597 u8 configuration_item_data[0x20]; 9598 }; 9599 9600 struct mlx5_ifc_node_info_ro_fields_param_bits { 9601 u8 system_image_guid[0x40]; 9602 9603 u8 reserved_0[0x40]; 9604 9605 u8 node_guid[0x40]; 9606 9607 u8 reserved_1[0x10]; 9608 u8 max_pkey[0x10]; 9609 9610 u8 reserved_2[0x20]; 9611 }; 9612 9613 struct mlx5_ifc_ets_tcn_config_reg_bits { 9614 u8 g[0x1]; 9615 u8 b[0x1]; 9616 u8 r[0x1]; 9617 u8 reserved_0[0x9]; 9618 u8 group[0x4]; 9619 u8 reserved_1[0x9]; 9620 u8 bw_allocation[0x7]; 9621 9622 u8 reserved_2[0xc]; 9623 u8 max_bw_units[0x4]; 9624 u8 reserved_3[0x8]; 9625 u8 max_bw_value[0x8]; 9626 }; 9627 9628 struct mlx5_ifc_ets_global_config_reg_bits { 9629 u8 reserved_0[0x2]; 9630 u8 r[0x1]; 9631 u8 reserved_1[0x1d]; 9632 9633 u8 reserved_2[0xc]; 9634 u8 max_bw_units[0x4]; 9635 u8 reserved_3[0x8]; 9636 u8 max_bw_value[0x8]; 9637 }; 9638 9639 struct mlx5_ifc_qetc_reg_bits { 9640 u8 reserved_at_0[0x8]; 9641 u8 port_number[0x8]; 9642 u8 reserved_at_10[0x30]; 9643 9644 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9645 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9646 }; 9647 9648 struct mlx5_ifc_nodnic_mac_filters_bits { 9649 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 9650 9651 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 9652 9653 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 9654 9655 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 9656 9657 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 9658 9659 u8 reserved_0[0xc0]; 9660 }; 9661 9662 struct mlx5_ifc_nodnic_gid_filters_bits { 9663 u8 mgid_filter0[16][0x8]; 9664 9665 u8 mgid_filter1[16][0x8]; 9666 9667 u8 mgid_filter2[16][0x8]; 9668 9669 u8 mgid_filter3[16][0x8]; 9670 }; 9671 9672 enum { 9673 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 9674 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 9675 }; 9676 9677 enum { 9678 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 9679 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 9680 }; 9681 9682 struct mlx5_ifc_nodnic_config_reg_bits { 9683 u8 no_dram_nic_revision[0x8]; 9684 u8 hardware_format[0x8]; 9685 u8 support_receive_filter[0x1]; 9686 u8 support_promisc_filter[0x1]; 9687 u8 support_promisc_multicast_filter[0x1]; 9688 u8 reserved_0[0x2]; 9689 u8 log_working_buffer_size[0x3]; 9690 u8 log_pkey_table_size[0x4]; 9691 u8 reserved_1[0x3]; 9692 u8 num_ports[0x1]; 9693 9694 u8 reserved_2[0x2]; 9695 u8 log_max_ring_size[0x6]; 9696 u8 reserved_3[0x18]; 9697 9698 u8 lkey[0x20]; 9699 9700 u8 cqe_format[0x4]; 9701 u8 reserved_4[0x1c]; 9702 9703 u8 node_guid[0x40]; 9704 9705 u8 reserved_5[0x740]; 9706 9707 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 9708 9709 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 9710 }; 9711 9712 struct mlx5_ifc_vlan_layout_bits { 9713 u8 reserved_0[0x14]; 9714 u8 vlan[0xc]; 9715 9716 u8 reserved_1[0x20]; 9717 }; 9718 9719 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9720 u8 reserved_0[0x20]; 9721 9722 u8 mkey[0x20]; 9723 9724 u8 addressh_63_32[0x20]; 9725 9726 u8 addressl_31_0[0x20]; 9727 }; 9728 9729 struct mlx5_ifc_ud_adrs_vector_bits { 9730 u8 dc_key[0x40]; 9731 9732 u8 ext[0x1]; 9733 u8 reserved_0[0x7]; 9734 u8 destination_qp_dct[0x18]; 9735 9736 u8 static_rate[0x4]; 9737 u8 sl_eth_prio[0x4]; 9738 u8 fl[0x1]; 9739 u8 mlid[0x7]; 9740 u8 rlid_udp_sport[0x10]; 9741 9742 u8 reserved_1[0x20]; 9743 9744 u8 rmac_47_16[0x20]; 9745 9746 u8 rmac_15_0[0x10]; 9747 u8 tclass[0x8]; 9748 u8 hop_limit[0x8]; 9749 9750 u8 reserved_2[0x1]; 9751 u8 grh[0x1]; 9752 u8 reserved_3[0x2]; 9753 u8 src_addr_index[0x8]; 9754 u8 flow_label[0x14]; 9755 9756 u8 rgid_rip[16][0x8]; 9757 }; 9758 9759 struct mlx5_ifc_port_module_event_bits { 9760 u8 reserved_0[0x8]; 9761 u8 module[0x8]; 9762 u8 reserved_1[0xc]; 9763 u8 module_status[0x4]; 9764 9765 u8 reserved_2[0x14]; 9766 u8 error_type[0x4]; 9767 u8 reserved_3[0x8]; 9768 9769 u8 reserved_4[0xa0]; 9770 }; 9771 9772 struct mlx5_ifc_icmd_control_bits { 9773 u8 opcode[0x10]; 9774 u8 status[0x8]; 9775 u8 reserved_0[0x7]; 9776 u8 busy[0x1]; 9777 }; 9778 9779 struct mlx5_ifc_eqe_bits { 9780 u8 reserved_0[0x8]; 9781 u8 event_type[0x8]; 9782 u8 reserved_1[0x8]; 9783 u8 event_sub_type[0x8]; 9784 9785 u8 reserved_2[0xe0]; 9786 9787 union mlx5_ifc_event_auto_bits event_data; 9788 9789 u8 reserved_3[0x10]; 9790 u8 signature[0x8]; 9791 u8 reserved_4[0x7]; 9792 u8 owner[0x1]; 9793 }; 9794 9795 enum { 9796 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9797 }; 9798 9799 struct mlx5_ifc_cmd_queue_entry_bits { 9800 u8 type[0x8]; 9801 u8 reserved_0[0x18]; 9802 9803 u8 input_length[0x20]; 9804 9805 u8 input_mailbox_pointer_63_32[0x20]; 9806 9807 u8 input_mailbox_pointer_31_9[0x17]; 9808 u8 reserved_1[0x9]; 9809 9810 u8 command_input_inline_data[16][0x8]; 9811 9812 u8 command_output_inline_data[16][0x8]; 9813 9814 u8 output_mailbox_pointer_63_32[0x20]; 9815 9816 u8 output_mailbox_pointer_31_9[0x17]; 9817 u8 reserved_2[0x9]; 9818 9819 u8 output_length[0x20]; 9820 9821 u8 token[0x8]; 9822 u8 signature[0x8]; 9823 u8 reserved_3[0x8]; 9824 u8 status[0x7]; 9825 u8 ownership[0x1]; 9826 }; 9827 9828 struct mlx5_ifc_cmd_out_bits { 9829 u8 status[0x8]; 9830 u8 reserved_0[0x18]; 9831 9832 u8 syndrome[0x20]; 9833 9834 u8 command_output[0x20]; 9835 }; 9836 9837 struct mlx5_ifc_cmd_in_bits { 9838 u8 opcode[0x10]; 9839 u8 reserved_0[0x10]; 9840 9841 u8 reserved_1[0x10]; 9842 u8 op_mod[0x10]; 9843 9844 u8 command[0][0x20]; 9845 }; 9846 9847 struct mlx5_ifc_cmd_if_box_bits { 9848 u8 mailbox_data[512][0x8]; 9849 9850 u8 reserved_0[0x180]; 9851 9852 u8 next_pointer_63_32[0x20]; 9853 9854 u8 next_pointer_31_10[0x16]; 9855 u8 reserved_1[0xa]; 9856 9857 u8 block_number[0x20]; 9858 9859 u8 reserved_2[0x8]; 9860 u8 token[0x8]; 9861 u8 ctrl_signature[0x8]; 9862 u8 signature[0x8]; 9863 }; 9864 9865 struct mlx5_ifc_mtt_bits { 9866 u8 ptag_63_32[0x20]; 9867 9868 u8 ptag_31_8[0x18]; 9869 u8 reserved_0[0x6]; 9870 u8 wr_en[0x1]; 9871 u8 rd_en[0x1]; 9872 }; 9873 9874 struct mlx5_ifc_tls_progress_params_bits { 9875 u8 valid[0x1]; 9876 u8 reserved_at_1[0x7]; 9877 u8 pd[0x18]; 9878 9879 u8 next_record_tcp_sn[0x20]; 9880 9881 u8 hw_resync_tcp_sn[0x20]; 9882 9883 u8 record_tracker_state[0x2]; 9884 u8 auth_state[0x2]; 9885 u8 reserved_at_64[0x4]; 9886 u8 hw_offset_record_number[0x18]; 9887 }; 9888 9889 struct mlx5_ifc_tls_static_params_bits { 9890 u8 const_2[0x2]; 9891 u8 tls_version[0x4]; 9892 u8 const_1[0x2]; 9893 u8 reserved_at_8[0x14]; 9894 u8 encryption_standard[0x4]; 9895 9896 u8 reserved_at_20[0x20]; 9897 9898 u8 initial_record_number[0x40]; 9899 9900 u8 resync_tcp_sn[0x20]; 9901 9902 u8 gcm_iv[0x20]; 9903 9904 u8 implicit_iv[0x40]; 9905 9906 u8 reserved_at_100[0x8]; 9907 u8 dek_index[0x18]; 9908 9909 u8 reserved_at_120[0xe0]; 9910 }; 9911 9912 /* Vendor Specific Capabilities, VSC */ 9913 enum { 9914 MLX5_VSC_DOMAIN_ICMD = 0x1, 9915 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 9916 MLX5_VSC_DOMAIN_SCAN_CRSPACE = 0x7, 9917 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 9918 }; 9919 9920 struct mlx5_ifc_vendor_specific_cap_bits { 9921 u8 type[0x8]; 9922 u8 length[0x8]; 9923 u8 next_pointer[0x8]; 9924 u8 capability_id[0x8]; 9925 9926 u8 status[0x3]; 9927 u8 reserved_0[0xd]; 9928 u8 space[0x10]; 9929 9930 u8 counter[0x20]; 9931 9932 u8 semaphore[0x20]; 9933 9934 u8 flag[0x1]; 9935 u8 reserved_1[0x1]; 9936 u8 address[0x1e]; 9937 9938 u8 data[0x20]; 9939 }; 9940 9941 struct mlx5_ifc_vsc_space_bits { 9942 u8 status[0x3]; 9943 u8 reserved0[0xd]; 9944 u8 space[0x10]; 9945 }; 9946 9947 struct mlx5_ifc_vsc_addr_bits { 9948 u8 flag[0x1]; 9949 u8 reserved0[0x1]; 9950 u8 address[0x1e]; 9951 }; 9952 9953 enum { 9954 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9955 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9956 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9957 }; 9958 9959 enum { 9960 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9961 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9962 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9963 }; 9964 9965 enum { 9966 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 9967 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 9968 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 9969 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 9970 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 9971 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 9972 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 9973 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 9974 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 9975 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 9976 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 9977 }; 9978 9979 struct mlx5_ifc_initial_seg_bits { 9980 u8 fw_rev_minor[0x10]; 9981 u8 fw_rev_major[0x10]; 9982 9983 u8 cmd_interface_rev[0x10]; 9984 u8 fw_rev_subminor[0x10]; 9985 9986 u8 reserved_0[0x40]; 9987 9988 u8 cmdq_phy_addr_63_32[0x20]; 9989 9990 u8 cmdq_phy_addr_31_12[0x14]; 9991 u8 reserved_1[0x2]; 9992 u8 nic_interface[0x2]; 9993 u8 log_cmdq_size[0x4]; 9994 u8 log_cmdq_stride[0x4]; 9995 9996 u8 command_doorbell_vector[0x20]; 9997 9998 u8 reserved_2[0xf00]; 9999 10000 u8 initializing[0x1]; 10001 u8 reserved_3[0x4]; 10002 u8 nic_interface_supported[0x3]; 10003 u8 reserved_4[0x18]; 10004 10005 struct mlx5_ifc_health_buffer_bits health_buffer; 10006 10007 u8 no_dram_nic_offset[0x20]; 10008 10009 u8 reserved_5[0x6de0]; 10010 10011 u8 internal_timer_h[0x20]; 10012 10013 u8 internal_timer_l[0x20]; 10014 10015 u8 reserved_6[0x20]; 10016 10017 u8 reserved_7[0x1f]; 10018 u8 clear_int[0x1]; 10019 10020 u8 health_syndrome[0x8]; 10021 u8 health_counter[0x18]; 10022 10023 u8 reserved_8[0x17fc0]; 10024 }; 10025 10026 union mlx5_ifc_icmd_interface_document_bits { 10027 struct mlx5_ifc_fw_version_bits fw_version; 10028 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 10029 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 10030 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 10031 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 10032 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 10033 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 10034 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 10035 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 10036 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 10037 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 10038 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 10039 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 10040 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 10041 u8 reserved_0[0x42c0]; 10042 }; 10043 10044 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 10045 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10046 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10047 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10048 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10049 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10050 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10051 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10052 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10053 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 10054 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 10055 u8 reserved_0[0x7c0]; 10056 }; 10057 10058 struct mlx5_ifc_ppcnt_reg_bits { 10059 u8 swid[0x8]; 10060 u8 local_port[0x8]; 10061 u8 pnat[0x2]; 10062 u8 reserved_0[0x8]; 10063 u8 grp[0x6]; 10064 10065 u8 clr[0x1]; 10066 u8 reserved_1[0x1c]; 10067 u8 prio_tc[0x3]; 10068 10069 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10070 }; 10071 10072 struct mlx5_ifc_pcie_lanes_counters_bits { 10073 u8 life_time_counter_high[0x20]; 10074 10075 u8 life_time_counter_low[0x20]; 10076 10077 u8 error_counter_lane0[0x20]; 10078 10079 u8 error_counter_lane1[0x20]; 10080 10081 u8 error_counter_lane2[0x20]; 10082 10083 u8 error_counter_lane3[0x20]; 10084 10085 u8 error_counter_lane4[0x20]; 10086 10087 u8 error_counter_lane5[0x20]; 10088 10089 u8 error_counter_lane6[0x20]; 10090 10091 u8 error_counter_lane7[0x20]; 10092 10093 u8 error_counter_lane8[0x20]; 10094 10095 u8 error_counter_lane9[0x20]; 10096 10097 u8 error_counter_lane10[0x20]; 10098 10099 u8 error_counter_lane11[0x20]; 10100 10101 u8 error_counter_lane12[0x20]; 10102 10103 u8 error_counter_lane13[0x20]; 10104 10105 u8 error_counter_lane14[0x20]; 10106 10107 u8 error_counter_lane15[0x20]; 10108 10109 u8 reserved_at_240[0x580]; 10110 }; 10111 10112 struct mlx5_ifc_pcie_lanes_counters_ext_bits { 10113 u8 reserved_at_0[0x40]; 10114 10115 u8 error_counter_lane0[0x20]; 10116 10117 u8 error_counter_lane1[0x20]; 10118 10119 u8 error_counter_lane2[0x20]; 10120 10121 u8 error_counter_lane3[0x20]; 10122 10123 u8 error_counter_lane4[0x20]; 10124 10125 u8 error_counter_lane5[0x20]; 10126 10127 u8 error_counter_lane6[0x20]; 10128 10129 u8 error_counter_lane7[0x20]; 10130 10131 u8 error_counter_lane8[0x20]; 10132 10133 u8 error_counter_lane9[0x20]; 10134 10135 u8 error_counter_lane10[0x20]; 10136 10137 u8 error_counter_lane11[0x20]; 10138 10139 u8 error_counter_lane12[0x20]; 10140 10141 u8 error_counter_lane13[0x20]; 10142 10143 u8 error_counter_lane14[0x20]; 10144 10145 u8 error_counter_lane15[0x20]; 10146 10147 u8 reserved_at_240[0x580]; 10148 }; 10149 10150 struct mlx5_ifc_pcie_perf_counters_bits { 10151 u8 life_time_counter_high[0x20]; 10152 10153 u8 life_time_counter_low[0x20]; 10154 10155 u8 rx_errors[0x20]; 10156 10157 u8 tx_errors[0x20]; 10158 10159 u8 l0_to_recovery_eieos[0x20]; 10160 10161 u8 l0_to_recovery_ts[0x20]; 10162 10163 u8 l0_to_recovery_framing[0x20]; 10164 10165 u8 l0_to_recovery_retrain[0x20]; 10166 10167 u8 crc_error_dllp[0x20]; 10168 10169 u8 crc_error_tlp[0x20]; 10170 10171 u8 tx_overflow_buffer_pkt[0x40]; 10172 10173 u8 outbound_stalled_reads[0x20]; 10174 10175 u8 outbound_stalled_writes[0x20]; 10176 10177 u8 outbound_stalled_reads_events[0x20]; 10178 10179 u8 outbound_stalled_writes_events[0x20]; 10180 10181 u8 tx_overflow_buffer_marked_pkt[0x40]; 10182 10183 u8 reserved_at_240[0x580]; 10184 }; 10185 10186 struct mlx5_ifc_pcie_perf_counters_ext_bits { 10187 u8 reserved_at_0[0x40]; 10188 10189 u8 rx_errors[0x20]; 10190 10191 u8 tx_errors[0x20]; 10192 10193 u8 reserved_at_80[0xc0]; 10194 10195 u8 tx_overflow_buffer_pkt[0x40]; 10196 10197 u8 outbound_stalled_reads[0x20]; 10198 10199 u8 outbound_stalled_writes[0x20]; 10200 10201 u8 outbound_stalled_reads_events[0x20]; 10202 10203 u8 outbound_stalled_writes_events[0x20]; 10204 10205 u8 tx_overflow_buffer_marked_pkt[0x40]; 10206 10207 u8 reserved_at_240[0x580]; 10208 }; 10209 10210 struct mlx5_ifc_pcie_timers_states_bits { 10211 u8 life_time_counter_high[0x20]; 10212 10213 u8 life_time_counter_low[0x20]; 10214 10215 u8 time_to_boot_image_start[0x20]; 10216 10217 u8 time_to_link_image[0x20]; 10218 10219 u8 calibration_time[0x20]; 10220 10221 u8 time_to_first_perst[0x20]; 10222 10223 u8 time_to_detect_state[0x20]; 10224 10225 u8 time_to_l0[0x20]; 10226 10227 u8 time_to_crs_en[0x20]; 10228 10229 u8 time_to_plastic_image_start[0x20]; 10230 10231 u8 time_to_iron_image_start[0x20]; 10232 10233 u8 perst_handler[0x20]; 10234 10235 u8 times_in_l1[0x20]; 10236 10237 u8 times_in_l23[0x20]; 10238 10239 u8 dl_down[0x20]; 10240 10241 u8 config_cycle1usec[0x20]; 10242 10243 u8 config_cycle2to7usec[0x20]; 10244 10245 u8 config_cycle8to15usec[0x20]; 10246 10247 u8 config_cycle16to63usec[0x20]; 10248 10249 u8 config_cycle64usec[0x20]; 10250 10251 u8 correctable_err_msg_sent[0x20]; 10252 10253 u8 non_fatal_err_msg_sent[0x20]; 10254 10255 u8 fatal_err_msg_sent[0x20]; 10256 10257 u8 reserved_at_2e0[0x4e0]; 10258 }; 10259 10260 struct mlx5_ifc_pcie_timers_states_ext_bits { 10261 u8 reserved_at_0[0x40]; 10262 10263 u8 time_to_boot_image_start[0x20]; 10264 10265 u8 time_to_link_image[0x20]; 10266 10267 u8 calibration_time[0x20]; 10268 10269 u8 time_to_first_perst[0x20]; 10270 10271 u8 time_to_detect_state[0x20]; 10272 10273 u8 time_to_l0[0x20]; 10274 10275 u8 time_to_crs_en[0x20]; 10276 10277 u8 time_to_plastic_image_start[0x20]; 10278 10279 u8 time_to_iron_image_start[0x20]; 10280 10281 u8 perst_handler[0x20]; 10282 10283 u8 times_in_l1[0x20]; 10284 10285 u8 times_in_l23[0x20]; 10286 10287 u8 dl_down[0x20]; 10288 10289 u8 config_cycle1usec[0x20]; 10290 10291 u8 config_cycle2to7usec[0x20]; 10292 10293 u8 config_cycle8to15usec[0x20]; 10294 10295 u8 config_cycle16to63usec[0x20]; 10296 10297 u8 config_cycle64usec[0x20]; 10298 10299 u8 correctable_err_msg_sent[0x20]; 10300 10301 u8 non_fatal_err_msg_sent[0x20]; 10302 10303 u8 fatal_err_msg_sent[0x20]; 10304 10305 u8 reserved_at_2e0[0x4e0]; 10306 }; 10307 10308 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits { 10309 struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters; 10310 struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters; 10311 struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states; 10312 u8 reserved_at_0[0x7c0]; 10313 }; 10314 10315 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits { 10316 struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext; 10317 struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext; 10318 struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext; 10319 u8 reserved_at_0[0x7c0]; 10320 }; 10321 10322 struct mlx5_ifc_mpcnt_reg_bits { 10323 u8 reserved_at_0[0x2]; 10324 u8 depth[0x6]; 10325 u8 pcie_index[0x8]; 10326 u8 node[0x8]; 10327 u8 reserved_at_18[0x2]; 10328 u8 grp[0x6]; 10329 10330 u8 clr[0x1]; 10331 u8 reserved_at_21[0x1f]; 10332 10333 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set; 10334 }; 10335 10336 struct mlx5_ifc_mpcnt_reg_ext_bits { 10337 u8 reserved_at_0[0x2]; 10338 u8 depth[0x6]; 10339 u8 pcie_index[0x8]; 10340 u8 node[0x8]; 10341 u8 reserved_at_18[0x2]; 10342 u8 grp[0x6]; 10343 10344 u8 clr[0x1]; 10345 u8 reserved_at_21[0x1f]; 10346 10347 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set; 10348 }; 10349 10350 enum { 10351 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050, 10352 MLX5_MPEIN_PWR_STATUS_INVALID = 0, 10353 MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1, 10354 MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2, 10355 }; 10356 10357 struct mlx5_ifc_mpein_reg_bits { 10358 u8 reserved_at_0[0x2]; 10359 u8 depth[0x6]; 10360 u8 pcie_index[0x8]; 10361 u8 node[0x8]; 10362 u8 reserved_at_18[0x8]; 10363 10364 u8 capability_mask[0x20]; 10365 10366 u8 reserved_at_40[0x8]; 10367 u8 link_width_enabled[0x8]; 10368 u8 link_speed_enabled[0x10]; 10369 10370 u8 lane0_physical_position[0x8]; 10371 u8 link_width_active[0x8]; 10372 u8 link_speed_active[0x10]; 10373 10374 u8 num_of_pfs[0x10]; 10375 u8 num_of_vfs[0x10]; 10376 10377 u8 bdf0[0x10]; 10378 u8 reserved_at_b0[0x10]; 10379 10380 u8 max_read_request_size[0x4]; 10381 u8 max_payload_size[0x4]; 10382 u8 reserved_at_c8[0x5]; 10383 u8 pwr_status[0x3]; 10384 u8 port_type[0x4]; 10385 u8 reserved_at_d4[0xb]; 10386 u8 lane_reversal[0x1]; 10387 10388 u8 reserved_at_e0[0x14]; 10389 u8 pci_power[0xc]; 10390 10391 u8 reserved_at_100[0x20]; 10392 10393 u8 device_status[0x10]; 10394 u8 port_state[0x8]; 10395 u8 reserved_at_138[0x8]; 10396 10397 u8 reserved_at_140[0x10]; 10398 u8 receiver_detect_result[0x10]; 10399 10400 u8 reserved_at_160[0x20]; 10401 }; 10402 10403 struct mlx5_ifc_mpein_reg_ext_bits { 10404 u8 reserved_at_0[0x2]; 10405 u8 depth[0x6]; 10406 u8 pcie_index[0x8]; 10407 u8 node[0x8]; 10408 u8 reserved_at_18[0x8]; 10409 10410 u8 reserved_at_20[0x20]; 10411 10412 u8 reserved_at_40[0x8]; 10413 u8 link_width_enabled[0x8]; 10414 u8 link_speed_enabled[0x10]; 10415 10416 u8 lane0_physical_position[0x8]; 10417 u8 link_width_active[0x8]; 10418 u8 link_speed_active[0x10]; 10419 10420 u8 num_of_pfs[0x10]; 10421 u8 num_of_vfs[0x10]; 10422 10423 u8 bdf0[0x10]; 10424 u8 reserved_at_b0[0x10]; 10425 10426 u8 max_read_request_size[0x4]; 10427 u8 max_payload_size[0x4]; 10428 u8 reserved_at_c8[0x5]; 10429 u8 pwr_status[0x3]; 10430 u8 port_type[0x4]; 10431 u8 reserved_at_d4[0xb]; 10432 u8 lane_reversal[0x1]; 10433 }; 10434 10435 struct mlx5_ifc_mcqi_cap_bits { 10436 u8 supported_info_bitmask[0x20]; 10437 10438 u8 component_size[0x20]; 10439 10440 u8 max_component_size[0x20]; 10441 10442 u8 log_mcda_word_size[0x4]; 10443 u8 reserved_at_64[0xc]; 10444 u8 mcda_max_write_size[0x10]; 10445 10446 u8 rd_en[0x1]; 10447 u8 reserved_at_81[0x1]; 10448 u8 match_chip_id[0x1]; 10449 u8 match_psid[0x1]; 10450 u8 check_user_timestamp[0x1]; 10451 u8 match_base_guid_mac[0x1]; 10452 u8 reserved_at_86[0x1a]; 10453 }; 10454 10455 struct mlx5_ifc_mcqi_reg_bits { 10456 u8 read_pending_component[0x1]; 10457 u8 reserved_at_1[0xf]; 10458 u8 component_index[0x10]; 10459 10460 u8 reserved_at_20[0x20]; 10461 10462 u8 reserved_at_40[0x1b]; 10463 u8 info_type[0x5]; 10464 10465 u8 info_size[0x20]; 10466 10467 u8 offset[0x20]; 10468 10469 u8 reserved_at_a0[0x10]; 10470 u8 data_size[0x10]; 10471 10472 u8 data[0][0x20]; 10473 }; 10474 10475 struct mlx5_ifc_mcc_reg_bits { 10476 u8 reserved_at_0[0x4]; 10477 u8 time_elapsed_since_last_cmd[0xc]; 10478 u8 reserved_at_10[0x8]; 10479 u8 instruction[0x8]; 10480 10481 u8 reserved_at_20[0x10]; 10482 u8 component_index[0x10]; 10483 10484 u8 reserved_at_40[0x8]; 10485 u8 update_handle[0x18]; 10486 10487 u8 handle_owner_type[0x4]; 10488 u8 handle_owner_host_id[0x4]; 10489 u8 reserved_at_68[0x1]; 10490 u8 control_progress[0x7]; 10491 u8 error_code[0x8]; 10492 u8 reserved_at_78[0x4]; 10493 u8 control_state[0x4]; 10494 10495 u8 component_size[0x20]; 10496 10497 u8 reserved_at_a0[0x60]; 10498 }; 10499 10500 struct mlx5_ifc_mcda_reg_bits { 10501 u8 reserved_at_0[0x8]; 10502 u8 update_handle[0x18]; 10503 10504 u8 offset[0x20]; 10505 10506 u8 reserved_at_40[0x10]; 10507 u8 size[0x10]; 10508 10509 u8 reserved_at_60[0x20]; 10510 10511 u8 data[0][0x20]; 10512 }; 10513 10514 union mlx5_ifc_ports_control_registers_document_bits { 10515 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 10516 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10517 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10518 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10519 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10520 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10521 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10522 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10523 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10524 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 10525 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 10526 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10527 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 10528 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10529 struct mlx5_ifc_paos_reg_bits paos_reg; 10530 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 10531 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10532 struct mlx5_ifc_peir_reg_bits peir_reg; 10533 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10534 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10535 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 10536 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 10537 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 10538 struct mlx5_ifc_phrr_reg_bits phrr_reg; 10539 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10540 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10541 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10542 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10543 struct mlx5_ifc_plib_reg_bits plib_reg; 10544 struct mlx5_ifc_pll_status_data_bits pll_status_data; 10545 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10546 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10547 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10548 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10549 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10550 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10551 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10552 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10553 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10554 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10555 struct mlx5_ifc_ppll_reg_bits ppll_reg; 10556 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10557 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10558 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10559 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10560 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10561 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10562 struct mlx5_ifc_pude_reg_bits pude_reg; 10563 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10564 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10565 struct mlx5_ifc_slrp_reg_bits slrp_reg; 10566 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10567 u8 reserved_0[0x7880]; 10568 }; 10569 10570 union mlx5_ifc_debug_enhancements_document_bits { 10571 struct mlx5_ifc_health_buffer_bits health_buffer; 10572 u8 reserved_0[0x200]; 10573 }; 10574 10575 union mlx5_ifc_no_dram_nic_document_bits { 10576 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 10577 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 10578 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 10579 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 10580 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 10581 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 10582 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 10583 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 10584 u8 reserved_0[0x3160]; 10585 }; 10586 10587 union mlx5_ifc_uplink_pci_interface_document_bits { 10588 struct mlx5_ifc_initial_seg_bits initial_seg; 10589 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 10590 u8 reserved_0[0x20120]; 10591 }; 10592 10593 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10594 u8 e[0x1]; 10595 u8 reserved_at_01[0x0b]; 10596 u8 prio[0x04]; 10597 }; 10598 10599 struct mlx5_ifc_qpdpm_reg_bits { 10600 u8 reserved_at_0[0x8]; 10601 u8 local_port[0x8]; 10602 u8 reserved_at_10[0x10]; 10603 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10604 }; 10605 10606 struct mlx5_ifc_qpts_reg_bits { 10607 u8 reserved_at_0[0x8]; 10608 u8 local_port[0x8]; 10609 u8 reserved_at_10[0x2d]; 10610 u8 trust_state[0x3]; 10611 }; 10612 10613 struct mlx5_ifc_mfrl_reg_bits { 10614 u8 reserved_at_0[0x38]; 10615 u8 reset_level[0x8]; 10616 }; 10617 10618 enum { 10619 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP = 0x9009, 10620 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR = 0x9109, 10621 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP = 0x900a, 10622 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE = 0x900b, 10623 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR = 0x900f, 10624 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE = 0x910b, 10625 MLX5_MAX_TEMPERATURE = 16, 10626 }; 10627 10628 struct mlx5_ifc_mtbr_temp_record_bits { 10629 u8 max_temperature[0x10]; 10630 u8 temperature[0x10]; 10631 }; 10632 10633 struct mlx5_ifc_mtbr_reg_bits { 10634 u8 reserved_at_0[0x14]; 10635 u8 base_sensor_index[0xc]; 10636 10637 u8 reserved_at_20[0x18]; 10638 u8 num_rec[0x8]; 10639 10640 u8 reserved_at_40[0x40]; 10641 10642 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 10643 }; 10644 10645 struct mlx5_ifc_mtbr_reg_ext_bits { 10646 u8 reserved_at_0[0x14]; 10647 u8 base_sensor_index[0xc]; 10648 10649 u8 reserved_at_20[0x18]; 10650 u8 num_rec[0x8]; 10651 10652 u8 reserved_at_40[0x40]; 10653 10654 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 10655 }; 10656 10657 struct mlx5_ifc_mtcap_bits { 10658 u8 reserved_at_0[0x19]; 10659 u8 sensor_count[0x7]; 10660 10661 u8 reserved_at_20[0x19]; 10662 u8 internal_sensor_count[0x7]; 10663 10664 u8 sensor_map[0x40]; 10665 }; 10666 10667 struct mlx5_ifc_mtcap_ext_bits { 10668 u8 reserved_at_0[0x19]; 10669 u8 sensor_count[0x7]; 10670 10671 u8 reserved_at_20[0x20]; 10672 10673 u8 sensor_map[0x40]; 10674 }; 10675 10676 struct mlx5_ifc_mtecr_bits { 10677 u8 reserved_at_0[0x4]; 10678 u8 last_sensor[0xc]; 10679 u8 reserved_at_10[0x4]; 10680 u8 sensor_count[0xc]; 10681 10682 u8 reserved_at_20[0x19]; 10683 u8 internal_sensor_count[0x7]; 10684 10685 u8 sensor_map_0[0x20]; 10686 10687 u8 reserved_at_60[0x2a0]; 10688 }; 10689 10690 struct mlx5_ifc_mtecr_ext_bits { 10691 u8 reserved_at_0[0x4]; 10692 u8 last_sensor[0xc]; 10693 u8 reserved_at_10[0x4]; 10694 u8 sensor_count[0xc]; 10695 10696 u8 reserved_at_20[0x20]; 10697 10698 u8 sensor_map_0[0x20]; 10699 10700 u8 reserved_at_60[0x2a0]; 10701 }; 10702 10703 struct mlx5_ifc_mtewe_bits { 10704 u8 reserved_at_0[0x4]; 10705 u8 last_sensor[0xc]; 10706 u8 reserved_at_10[0x4]; 10707 u8 sensor_count[0xc]; 10708 10709 u8 sensor_warning_0[0x20]; 10710 10711 u8 reserved_at_40[0x2a0]; 10712 }; 10713 10714 struct mlx5_ifc_mtewe_ext_bits { 10715 u8 reserved_at_0[0x4]; 10716 u8 last_sensor[0xc]; 10717 u8 reserved_at_10[0x4]; 10718 u8 sensor_count[0xc]; 10719 10720 u8 sensor_warning_0[0x20]; 10721 10722 u8 reserved_at_40[0x2a0]; 10723 }; 10724 10725 struct mlx5_ifc_mtmp_bits { 10726 u8 reserved_at_0[0x14]; 10727 u8 sensor_index[0xc]; 10728 10729 u8 reserved_at_20[0x10]; 10730 u8 temperature[0x10]; 10731 10732 u8 mte[0x1]; 10733 u8 mtr[0x1]; 10734 u8 reserved_at_42[0xe]; 10735 u8 max_temperature[0x10]; 10736 10737 u8 tee[0x2]; 10738 u8 reserved_at_62[0xe]; 10739 u8 temperature_threshold_hi[0x10]; 10740 10741 u8 reserved_at_80[0x10]; 10742 u8 temperature_threshold_lo[0x10]; 10743 10744 u8 reserved_at_a0[0x20]; 10745 10746 u8 sensor_name_hi[0x20]; 10747 10748 u8 sensor_name_lo[0x20]; 10749 }; 10750 10751 struct mlx5_ifc_mtmp_ext_bits { 10752 u8 reserved_at_0[0x14]; 10753 u8 sensor_index[0xc]; 10754 10755 u8 reserved_at_20[0x10]; 10756 u8 temperature[0x10]; 10757 10758 u8 mte[0x1]; 10759 u8 mtr[0x1]; 10760 u8 reserved_at_42[0xe]; 10761 u8 max_temperature[0x10]; 10762 10763 u8 tee[0x2]; 10764 u8 reserved_at_62[0xe]; 10765 u8 temperature_threshold_hi[0x10]; 10766 10767 u8 reserved_at_80[0x10]; 10768 u8 temperature_threshold_lo[0x10]; 10769 10770 u8 reserved_at_a0[0x20]; 10771 10772 u8 sensor_name_hi[0x20]; 10773 10774 u8 sensor_name_lo[0x20]; 10775 }; 10776 10777 #endif /* MLX5_IFC_H */ 10778