1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_IFC_H 29 #define MLX5_IFC_H 30 31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> 32 33 enum { 34 MLX5_EVENT_TYPE_COMP = 0x0, 35 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 36 MLX5_EVENT_TYPE_COMM_EST = 0x2, 37 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 38 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 39 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 40 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 41 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 42 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 43 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 44 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 45 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 46 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 47 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 48 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 49 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 50 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 51 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 52 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 53 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 54 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 55 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 56 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 57 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 58 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 59 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 60 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 61 MLX5_EVENT_TYPE_CMD = 0xa, 62 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 63 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 64 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 65 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 66 }; 67 68 enum { 69 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 70 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 71 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 72 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 73 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 74 }; 75 76 enum { 77 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 78 }; 79 80 enum { 81 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 82 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 83 }; 84 85 enum { 86 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 87 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 88 MLX5_CMD_OP_INIT_HCA = 0x102, 89 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 90 MLX5_CMD_OP_ENABLE_HCA = 0x104, 91 MLX5_CMD_OP_DISABLE_HCA = 0x105, 92 MLX5_CMD_OP_QUERY_PAGES = 0x107, 93 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 94 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 95 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 96 MLX5_CMD_OP_SET_ISSI = 0x10b, 97 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 98 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 99 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 100 MLX5_CMD_OP_CREATE_MKEY = 0x200, 101 MLX5_CMD_OP_QUERY_MKEY = 0x201, 102 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 103 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 104 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 105 MLX5_CMD_OP_CREATE_EQ = 0x301, 106 MLX5_CMD_OP_DESTROY_EQ = 0x302, 107 MLX5_CMD_OP_QUERY_EQ = 0x303, 108 MLX5_CMD_OP_GEN_EQE = 0x304, 109 MLX5_CMD_OP_CREATE_CQ = 0x400, 110 MLX5_CMD_OP_DESTROY_CQ = 0x401, 111 MLX5_CMD_OP_QUERY_CQ = 0x402, 112 MLX5_CMD_OP_MODIFY_CQ = 0x403, 113 MLX5_CMD_OP_CREATE_QP = 0x500, 114 MLX5_CMD_OP_DESTROY_QP = 0x501, 115 MLX5_CMD_OP_RST2INIT_QP = 0x502, 116 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 117 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 118 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 119 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 120 MLX5_CMD_OP_2ERR_QP = 0x507, 121 MLX5_CMD_OP_2RST_QP = 0x50a, 122 MLX5_CMD_OP_QUERY_QP = 0x50b, 123 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 124 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 125 MLX5_CMD_OP_CREATE_PSV = 0x600, 126 MLX5_CMD_OP_DESTROY_PSV = 0x601, 127 MLX5_CMD_OP_CREATE_SRQ = 0x700, 128 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 129 MLX5_CMD_OP_QUERY_SRQ = 0x702, 130 MLX5_CMD_OP_ARM_RQ = 0x703, 131 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 132 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 133 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 134 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 135 MLX5_CMD_OP_CREATE_DCT = 0x710, 136 MLX5_CMD_OP_DESTROY_DCT = 0x711, 137 MLX5_CMD_OP_DRAIN_DCT = 0x712, 138 MLX5_CMD_OP_QUERY_DCT = 0x713, 139 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 140 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 141 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 142 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 143 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 144 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 145 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 146 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 147 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 148 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 149 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 150 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 151 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 152 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 153 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 154 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 155 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 156 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 157 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 158 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 159 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 160 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 161 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 162 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 163 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 164 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 165 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 166 MLX5_CMD_OP_ALLOC_PD = 0x800, 167 MLX5_CMD_OP_DEALLOC_PD = 0x801, 168 MLX5_CMD_OP_ALLOC_UAR = 0x802, 169 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 170 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 171 MLX5_CMD_OP_ACCESS_REG = 0x805, 172 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 173 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 174 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 175 MLX5_CMD_OP_MAD_IFC = 0x50d, 176 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 177 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 178 MLX5_CMD_OP_NOP = 0x80d, 179 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 180 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 181 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 182 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 183 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 184 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 185 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 186 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 187 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 188 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 189 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 190 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 191 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 192 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 193 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 194 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 195 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 196 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 197 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 198 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 199 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 200 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 201 MLX5_CMD_OP_CREATE_LAG = 0x840, 202 MLX5_CMD_OP_MODIFY_LAG = 0x841, 203 MLX5_CMD_OP_QUERY_LAG = 0x842, 204 MLX5_CMD_OP_DESTROY_LAG = 0x843, 205 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 206 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 207 MLX5_CMD_OP_CREATE_TIR = 0x900, 208 MLX5_CMD_OP_MODIFY_TIR = 0x901, 209 MLX5_CMD_OP_DESTROY_TIR = 0x902, 210 MLX5_CMD_OP_QUERY_TIR = 0x903, 211 MLX5_CMD_OP_CREATE_SQ = 0x904, 212 MLX5_CMD_OP_MODIFY_SQ = 0x905, 213 MLX5_CMD_OP_DESTROY_SQ = 0x906, 214 MLX5_CMD_OP_QUERY_SQ = 0x907, 215 MLX5_CMD_OP_CREATE_RQ = 0x908, 216 MLX5_CMD_OP_MODIFY_RQ = 0x909, 217 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 218 MLX5_CMD_OP_QUERY_RQ = 0x90b, 219 MLX5_CMD_OP_CREATE_RMP = 0x90c, 220 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 221 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 222 MLX5_CMD_OP_QUERY_RMP = 0x90f, 223 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 224 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 225 MLX5_CMD_OP_CREATE_TIS = 0x912, 226 MLX5_CMD_OP_MODIFY_TIS = 0x913, 227 MLX5_CMD_OP_DESTROY_TIS = 0x914, 228 MLX5_CMD_OP_QUERY_TIS = 0x915, 229 MLX5_CMD_OP_CREATE_RQT = 0x916, 230 MLX5_CMD_OP_MODIFY_RQT = 0x917, 231 MLX5_CMD_OP_DESTROY_RQT = 0x918, 232 MLX5_CMD_OP_QUERY_RQT = 0x919, 233 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 234 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 235 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 236 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 237 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 238 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 239 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 240 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 241 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 242 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 243 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 244 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 245 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 246 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 247 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 248 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 249 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 250 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 251 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 252 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 253 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 254 }; 255 256 enum { 257 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 258 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 259 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 260 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 261 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 262 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 263 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 264 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 265 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 266 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 267 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 268 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 269 }; 270 271 struct mlx5_ifc_flow_table_fields_supported_bits { 272 u8 outer_dmac[0x1]; 273 u8 outer_smac[0x1]; 274 u8 outer_ether_type[0x1]; 275 u8 reserved_0[0x1]; 276 u8 outer_first_prio[0x1]; 277 u8 outer_first_cfi[0x1]; 278 u8 outer_first_vid[0x1]; 279 u8 reserved_1[0x1]; 280 u8 outer_second_prio[0x1]; 281 u8 outer_second_cfi[0x1]; 282 u8 outer_second_vid[0x1]; 283 u8 outer_ipv6_flow_label[0x1]; 284 u8 outer_sip[0x1]; 285 u8 outer_dip[0x1]; 286 u8 outer_frag[0x1]; 287 u8 outer_ip_protocol[0x1]; 288 u8 outer_ip_ecn[0x1]; 289 u8 outer_ip_dscp[0x1]; 290 u8 outer_udp_sport[0x1]; 291 u8 outer_udp_dport[0x1]; 292 u8 outer_tcp_sport[0x1]; 293 u8 outer_tcp_dport[0x1]; 294 u8 outer_tcp_flags[0x1]; 295 u8 outer_gre_protocol[0x1]; 296 u8 outer_gre_key[0x1]; 297 u8 outer_vxlan_vni[0x1]; 298 u8 outer_geneve_vni[0x1]; 299 u8 outer_geneve_oam[0x1]; 300 u8 outer_geneve_protocol_type[0x1]; 301 u8 outer_geneve_opt_len[0x1]; 302 u8 reserved_2[0x1]; 303 u8 source_eswitch_port[0x1]; 304 305 u8 inner_dmac[0x1]; 306 u8 inner_smac[0x1]; 307 u8 inner_ether_type[0x1]; 308 u8 reserved_3[0x1]; 309 u8 inner_first_prio[0x1]; 310 u8 inner_first_cfi[0x1]; 311 u8 inner_first_vid[0x1]; 312 u8 reserved_4[0x1]; 313 u8 inner_second_prio[0x1]; 314 u8 inner_second_cfi[0x1]; 315 u8 inner_second_vid[0x1]; 316 u8 inner_ipv6_flow_label[0x1]; 317 u8 inner_sip[0x1]; 318 u8 inner_dip[0x1]; 319 u8 inner_frag[0x1]; 320 u8 inner_ip_protocol[0x1]; 321 u8 inner_ip_ecn[0x1]; 322 u8 inner_ip_dscp[0x1]; 323 u8 inner_udp_sport[0x1]; 324 u8 inner_udp_dport[0x1]; 325 u8 inner_tcp_sport[0x1]; 326 u8 inner_tcp_dport[0x1]; 327 u8 inner_tcp_flags[0x1]; 328 u8 reserved_5[0x9]; 329 330 u8 reserved_6[0x1a]; 331 u8 bth_dst_qp[0x1]; 332 u8 reserved_7[0x4]; 333 u8 source_sqn[0x1]; 334 335 u8 reserved_8[0x20]; 336 }; 337 338 struct mlx5_ifc_eth_discard_cntrs_grp_bits { 339 u8 ingress_general_high[0x20]; 340 341 u8 ingress_general_low[0x20]; 342 343 u8 ingress_policy_engine_high[0x20]; 344 345 u8 ingress_policy_engine_low[0x20]; 346 347 u8 ingress_vlan_membership_high[0x20]; 348 349 u8 ingress_vlan_membership_low[0x20]; 350 351 u8 ingress_tag_frame_type_high[0x20]; 352 353 u8 ingress_tag_frame_type_low[0x20]; 354 355 u8 egress_vlan_membership_high[0x20]; 356 357 u8 egress_vlan_membership_low[0x20]; 358 359 u8 loopback_filter_high[0x20]; 360 361 u8 loopback_filter_low[0x20]; 362 363 u8 egress_general_high[0x20]; 364 365 u8 egress_general_low[0x20]; 366 367 u8 reserved_at_1c0[0x40]; 368 369 u8 egress_hoq_high[0x20]; 370 371 u8 egress_hoq_low[0x20]; 372 373 u8 port_isolation_high[0x20]; 374 375 u8 port_isolation_low[0x20]; 376 377 u8 egress_policy_engine_high[0x20]; 378 379 u8 egress_policy_engine_low[0x20]; 380 381 u8 ingress_tx_link_down_high[0x20]; 382 383 u8 ingress_tx_link_down_low[0x20]; 384 385 u8 egress_stp_filter_high[0x20]; 386 387 u8 egress_stp_filter_low[0x20]; 388 389 u8 egress_hoq_stall_high[0x20]; 390 391 u8 egress_hoq_stall_low[0x20]; 392 393 u8 reserved_at_340[0x440]; 394 }; 395 struct mlx5_ifc_flow_table_prop_layout_bits { 396 u8 ft_support[0x1]; 397 u8 flow_tag[0x1]; 398 u8 flow_counter[0x1]; 399 u8 flow_modify_en[0x1]; 400 u8 modify_root[0x1]; 401 u8 identified_miss_table[0x1]; 402 u8 flow_table_modify[0x1]; 403 u8 encap[0x1]; 404 u8 decap[0x1]; 405 u8 reset_root_to_default[0x1]; 406 u8 reserved_at_a[0x16]; 407 408 u8 reserved_at_20[0x2]; 409 u8 log_max_ft_size[0x6]; 410 u8 reserved_at_28[0x10]; 411 u8 max_ft_level[0x8]; 412 413 u8 reserved_at_40[0x20]; 414 415 u8 reserved_at_60[0x18]; 416 u8 log_max_ft_num[0x8]; 417 418 u8 reserved_at_80[0x10]; 419 u8 log_max_flow_counter[0x8]; 420 u8 log_max_destination[0x8]; 421 422 u8 reserved_at_a0[0x18]; 423 u8 log_max_flow[0x8]; 424 425 u8 reserved_at_c0[0x40]; 426 427 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 428 429 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 430 }; 431 432 struct mlx5_ifc_odp_per_transport_service_cap_bits { 433 u8 send[0x1]; 434 u8 receive[0x1]; 435 u8 write[0x1]; 436 u8 read[0x1]; 437 u8 atomic[0x1]; 438 u8 srq_receive[0x1]; 439 u8 reserved_0[0x1a]; 440 }; 441 442 struct mlx5_ifc_flow_counter_list_bits { 443 u8 reserved_0[0x10]; 444 u8 flow_counter_id[0x10]; 445 446 u8 reserved_1[0x20]; 447 }; 448 449 enum { 450 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 451 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 452 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 453 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 454 }; 455 456 struct mlx5_ifc_dest_format_struct_bits { 457 u8 destination_type[0x8]; 458 u8 destination_id[0x18]; 459 460 u8 reserved_0[0x20]; 461 }; 462 463 struct mlx5_ifc_ipv4_layout_bits { 464 u8 reserved_at_0[0x60]; 465 466 u8 ipv4[0x20]; 467 }; 468 469 struct mlx5_ifc_ipv6_layout_bits { 470 u8 ipv6[16][0x8]; 471 }; 472 473 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 474 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 475 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 476 u8 reserved_at_0[0x80]; 477 }; 478 479 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 480 u8 smac_47_16[0x20]; 481 482 u8 smac_15_0[0x10]; 483 u8 ethertype[0x10]; 484 485 u8 dmac_47_16[0x20]; 486 487 u8 dmac_15_0[0x10]; 488 u8 first_prio[0x3]; 489 u8 first_cfi[0x1]; 490 u8 first_vid[0xc]; 491 492 u8 ip_protocol[0x8]; 493 u8 ip_dscp[0x6]; 494 u8 ip_ecn[0x2]; 495 u8 cvlan_tag[0x1]; 496 u8 svlan_tag[0x1]; 497 u8 frag[0x1]; 498 u8 reserved_1[0x4]; 499 u8 tcp_flags[0x9]; 500 501 u8 tcp_sport[0x10]; 502 u8 tcp_dport[0x10]; 503 504 u8 reserved_2[0x20]; 505 506 u8 udp_sport[0x10]; 507 u8 udp_dport[0x10]; 508 509 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 510 511 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 512 }; 513 514 struct mlx5_ifc_fte_match_set_misc_bits { 515 u8 reserved_0[0x8]; 516 u8 source_sqn[0x18]; 517 518 u8 reserved_1[0x10]; 519 u8 source_port[0x10]; 520 521 u8 outer_second_prio[0x3]; 522 u8 outer_second_cfi[0x1]; 523 u8 outer_second_vid[0xc]; 524 u8 inner_second_prio[0x3]; 525 u8 inner_second_cfi[0x1]; 526 u8 inner_second_vid[0xc]; 527 528 u8 outer_second_vlan_tag[0x1]; 529 u8 inner_second_vlan_tag[0x1]; 530 u8 reserved_2[0xe]; 531 u8 gre_protocol[0x10]; 532 533 u8 gre_key_h[0x18]; 534 u8 gre_key_l[0x8]; 535 536 u8 vxlan_vni[0x18]; 537 u8 reserved_3[0x8]; 538 539 u8 geneve_vni[0x18]; 540 u8 reserved4[0x7]; 541 u8 geneve_oam[0x1]; 542 543 u8 reserved_5[0xc]; 544 u8 outer_ipv6_flow_label[0x14]; 545 546 u8 reserved_6[0xc]; 547 u8 inner_ipv6_flow_label[0x14]; 548 549 u8 reserved_7[0xa]; 550 u8 geneve_opt_len[0x6]; 551 u8 geneve_protocol_type[0x10]; 552 553 u8 reserved_8[0x8]; 554 u8 bth_dst_qp[0x18]; 555 556 u8 reserved_9[0xa0]; 557 }; 558 559 struct mlx5_ifc_cmd_pas_bits { 560 u8 pa_h[0x20]; 561 562 u8 pa_l[0x14]; 563 u8 reserved_0[0xc]; 564 }; 565 566 struct mlx5_ifc_uint64_bits { 567 u8 hi[0x20]; 568 569 u8 lo[0x20]; 570 }; 571 572 struct mlx5_ifc_application_prio_entry_bits { 573 u8 reserved_0[0x8]; 574 u8 priority[0x3]; 575 u8 reserved_1[0x2]; 576 u8 sel[0x3]; 577 u8 protocol_id[0x10]; 578 }; 579 580 struct mlx5_ifc_nodnic_ring_doorbell_bits { 581 u8 reserved_0[0x8]; 582 u8 ring_pi[0x10]; 583 u8 reserved_1[0x8]; 584 }; 585 586 enum { 587 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 588 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 589 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 590 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 591 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 592 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 593 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 594 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 595 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 596 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 597 }; 598 599 struct mlx5_ifc_ads_bits { 600 u8 fl[0x1]; 601 u8 free_ar[0x1]; 602 u8 reserved_0[0xe]; 603 u8 pkey_index[0x10]; 604 605 u8 reserved_1[0x8]; 606 u8 grh[0x1]; 607 u8 mlid[0x7]; 608 u8 rlid[0x10]; 609 610 u8 ack_timeout[0x5]; 611 u8 reserved_2[0x3]; 612 u8 src_addr_index[0x8]; 613 u8 log_rtm[0x4]; 614 u8 stat_rate[0x4]; 615 u8 hop_limit[0x8]; 616 617 u8 reserved_3[0x4]; 618 u8 tclass[0x8]; 619 u8 flow_label[0x14]; 620 621 u8 rgid_rip[16][0x8]; 622 623 u8 reserved_4[0x4]; 624 u8 f_dscp[0x1]; 625 u8 f_ecn[0x1]; 626 u8 reserved_5[0x1]; 627 u8 f_eth_prio[0x1]; 628 u8 ecn[0x2]; 629 u8 dscp[0x6]; 630 u8 udp_sport[0x10]; 631 632 u8 dei_cfi[0x1]; 633 u8 eth_prio[0x3]; 634 u8 sl[0x4]; 635 u8 port[0x8]; 636 u8 rmac_47_32[0x10]; 637 638 u8 rmac_31_0[0x20]; 639 }; 640 641 struct mlx5_ifc_diagnostic_counter_cap_bits { 642 u8 sync[0x1]; 643 u8 reserved_0[0xf]; 644 u8 counter_id[0x10]; 645 }; 646 647 struct mlx5_ifc_debug_cap_bits { 648 u8 reserved_0[0x18]; 649 u8 log_max_samples[0x8]; 650 651 u8 single[0x1]; 652 u8 repetitive[0x1]; 653 u8 health_mon_rx_activity[0x1]; 654 u8 reserved_1[0x15]; 655 u8 log_min_sample_period[0x8]; 656 657 u8 reserved_2[0x1c0]; 658 659 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 660 }; 661 662 struct mlx5_ifc_qos_cap_bits { 663 u8 packet_pacing[0x1]; 664 u8 esw_scheduling[0x1]; 665 u8 esw_bw_share[0x1]; 666 u8 esw_rate_limit[0x1]; 667 u8 hll[0x1]; 668 u8 packet_pacing_burst_bound[0x1]; 669 u8 reserved_at_6[0x1a]; 670 671 u8 reserved_at_20[0x20]; 672 673 u8 packet_pacing_max_rate[0x20]; 674 675 u8 packet_pacing_min_rate[0x20]; 676 677 u8 reserved_at_80[0x10]; 678 u8 packet_pacing_rate_table_size[0x10]; 679 680 u8 esw_element_type[0x10]; 681 u8 esw_tsar_type[0x10]; 682 683 u8 reserved_at_c0[0x10]; 684 u8 max_qos_para_vport[0x10]; 685 686 u8 max_tsar_bw_share[0x20]; 687 688 u8 reserved_at_100[0x700]; 689 }; 690 691 struct mlx5_ifc_snapshot_cap_bits { 692 u8 reserved_0[0x1d]; 693 u8 suspend_qp_uc[0x1]; 694 u8 suspend_qp_ud[0x1]; 695 u8 suspend_qp_rc[0x1]; 696 697 u8 reserved_1[0x1c]; 698 u8 restore_pd[0x1]; 699 u8 restore_uar[0x1]; 700 u8 restore_mkey[0x1]; 701 u8 restore_qp[0x1]; 702 703 u8 reserved_2[0x1e]; 704 u8 named_mkey[0x1]; 705 u8 named_qp[0x1]; 706 707 u8 reserved_3[0x7a0]; 708 }; 709 710 struct mlx5_ifc_e_switch_cap_bits { 711 u8 vport_svlan_strip[0x1]; 712 u8 vport_cvlan_strip[0x1]; 713 u8 vport_svlan_insert[0x1]; 714 u8 vport_cvlan_insert_if_not_exist[0x1]; 715 u8 vport_cvlan_insert_overwrite[0x1]; 716 717 u8 reserved_0[0x19]; 718 719 u8 nic_vport_node_guid_modify[0x1]; 720 u8 nic_vport_port_guid_modify[0x1]; 721 722 u8 reserved_1[0x7e0]; 723 }; 724 725 struct mlx5_ifc_flow_table_eswitch_cap_bits { 726 u8 reserved_0[0x200]; 727 728 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 729 730 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 731 732 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 733 734 u8 reserved_1[0x7800]; 735 }; 736 737 struct mlx5_ifc_flow_table_nic_cap_bits { 738 u8 nic_rx_multi_path_tirs[0x1]; 739 u8 nic_rx_multi_path_tirs_fts[0x1]; 740 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 741 u8 reserved_at_3[0x1fd]; 742 743 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 744 745 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 746 747 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 748 749 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 750 751 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 752 753 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 754 755 u8 reserved_1[0x7200]; 756 }; 757 758 enum { 759 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_PDDR = 0x5031, 760 }; 761 762 struct mlx5_ifc_pddr_module_info_bits { 763 u8 cable_technology[0x8]; 764 u8 cable_breakout[0x8]; 765 u8 ext_ethernet_compliance_code[0x8]; 766 u8 ethernet_compliance_code[0x8]; 767 768 u8 cable_type[0x4]; 769 u8 cable_vendor[0x4]; 770 u8 cable_length[0x8]; 771 u8 cable_identifier[0x8]; 772 u8 cable_power_class[0x8]; 773 774 u8 reserved_at_40[0x8]; 775 u8 cable_rx_amp[0x8]; 776 u8 cable_rx_emphasis[0x8]; 777 u8 cable_tx_equalization[0x8]; 778 779 u8 reserved_at_60[0x8]; 780 u8 cable_attenuation_12g[0x8]; 781 u8 cable_attenuation_7g[0x8]; 782 u8 cable_attenuation_5g[0x8]; 783 784 u8 reserved_at_80[0x8]; 785 u8 rx_cdr_cap[0x4]; 786 u8 tx_cdr_cap[0x4]; 787 u8 reserved_at_90[0x4]; 788 u8 rx_cdr_state[0x4]; 789 u8 reserved_at_98[0x4]; 790 u8 tx_cdr_state[0x4]; 791 792 u8 vendor_name[16][0x8]; 793 794 u8 vendor_pn[16][0x8]; 795 796 u8 vendor_rev[0x20]; 797 798 u8 fw_version[0x20]; 799 800 u8 vendor_sn[16][0x8]; 801 802 u8 temperature[0x10]; 803 u8 voltage[0x10]; 804 805 u8 rx_power_lane0[0x10]; 806 u8 rx_power_lane1[0x10]; 807 808 u8 rx_power_lane2[0x10]; 809 u8 rx_power_lane3[0x10]; 810 811 u8 reserved_at_2c0[0x40]; 812 813 u8 tx_power_lane0[0x10]; 814 u8 tx_power_lane1[0x10]; 815 816 u8 tx_power_lane2[0x10]; 817 u8 tx_power_lane3[0x10]; 818 819 u8 reserved_at_340[0x40]; 820 821 u8 tx_bias_lane0[0x10]; 822 u8 tx_bias_lane1[0x10]; 823 824 u8 tx_bias_lane2[0x10]; 825 u8 tx_bias_lane3[0x10]; 826 827 u8 reserved_at_3c0[0x40]; 828 829 u8 temperature_high_th[0x10]; 830 u8 temperature_low_th[0x10]; 831 832 u8 voltage_high_th[0x10]; 833 u8 voltage_low_th[0x10]; 834 835 u8 rx_power_high_th[0x10]; 836 u8 rx_power_low_th[0x10]; 837 838 u8 tx_power_high_th[0x10]; 839 u8 tx_power_low_th[0x10]; 840 841 u8 tx_bias_high_th[0x10]; 842 u8 tx_bias_low_th[0x10]; 843 844 u8 reserved_at_4a0[0x10]; 845 u8 wavelength[0x10]; 846 847 u8 reserved_at_4c0[0x300]; 848 }; 849 850 union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits { 851 struct mlx5_ifc_pddr_module_info_bits pddr_module_info; 852 u8 reserved_at_0[0x7c0]; 853 }; 854 855 struct mlx5_ifc_pddr_reg_bits { 856 u8 reserved_at_0[0x8]; 857 u8 local_port[0x8]; 858 u8 pnat[0x2]; 859 u8 reserved_at_12[0xe]; 860 861 u8 reserved_at_20[0x18]; 862 u8 page_select[0x8]; 863 864 union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits page_data; 865 }; 866 867 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 868 u8 csum_cap[0x1]; 869 u8 vlan_cap[0x1]; 870 u8 lro_cap[0x1]; 871 u8 lro_psh_flag[0x1]; 872 u8 lro_time_stamp[0x1]; 873 u8 lro_max_msg_sz_mode[0x2]; 874 u8 wqe_vlan_insert[0x1]; 875 u8 self_lb_en_modifiable[0x1]; 876 u8 self_lb_mc[0x1]; 877 u8 self_lb_uc[0x1]; 878 u8 max_lso_cap[0x5]; 879 u8 multi_pkt_send_wqe[0x2]; 880 u8 wqe_inline_mode[0x2]; 881 u8 rss_ind_tbl_cap[0x4]; 882 u8 scatter_fcs[0x1]; 883 u8 reserved_1[0x2]; 884 u8 tunnel_lso_const_out_ip_id[0x1]; 885 u8 tunnel_lro_gre[0x1]; 886 u8 tunnel_lro_vxlan[0x1]; 887 u8 tunnel_statless_gre[0x1]; 888 u8 tunnel_stateless_vxlan[0x1]; 889 890 u8 swp[0x1]; 891 u8 swp_csum[0x1]; 892 u8 swp_lso[0x1]; 893 u8 reserved_2[0x1b]; 894 u8 max_geneve_opt_len[0x1]; 895 u8 tunnel_stateless_geneve_rx[0x1]; 896 897 u8 reserved_3[0x10]; 898 u8 lro_min_mss_size[0x10]; 899 900 u8 reserved_4[0x120]; 901 902 u8 lro_timer_supported_periods[4][0x20]; 903 904 u8 reserved_5[0x600]; 905 }; 906 907 enum { 908 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 909 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 910 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 911 }; 912 913 struct mlx5_ifc_roce_cap_bits { 914 u8 roce_apm[0x1]; 915 u8 rts2rts_primary_eth_prio[0x1]; 916 u8 roce_rx_allow_untagged[0x1]; 917 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 918 919 u8 reserved_0[0x1c]; 920 921 u8 reserved_1[0x60]; 922 923 u8 reserved_2[0xc]; 924 u8 l3_type[0x4]; 925 u8 reserved_3[0x8]; 926 u8 roce_version[0x8]; 927 928 u8 reserved_4[0x10]; 929 u8 r_roce_dest_udp_port[0x10]; 930 931 u8 r_roce_max_src_udp_port[0x10]; 932 u8 r_roce_min_src_udp_port[0x10]; 933 934 u8 reserved_5[0x10]; 935 u8 roce_address_table_size[0x10]; 936 937 u8 reserved_6[0x700]; 938 }; 939 940 enum { 941 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 942 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 943 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 944 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 945 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 946 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 947 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 948 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 949 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 950 }; 951 952 enum { 953 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 954 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 955 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 956 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 957 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 958 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 959 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 960 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 961 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 962 }; 963 964 struct mlx5_ifc_atomic_caps_bits { 965 u8 reserved_0[0x40]; 966 967 u8 atomic_req_8B_endianess_mode[0x2]; 968 u8 reserved_1[0x4]; 969 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 970 971 u8 reserved_2[0x19]; 972 973 u8 reserved_3[0x20]; 974 975 u8 reserved_4[0x10]; 976 u8 atomic_operations[0x10]; 977 978 u8 reserved_5[0x10]; 979 u8 atomic_size_qp[0x10]; 980 981 u8 reserved_6[0x10]; 982 u8 atomic_size_dc[0x10]; 983 984 u8 reserved_7[0x720]; 985 }; 986 987 struct mlx5_ifc_odp_cap_bits { 988 u8 reserved_0[0x40]; 989 990 u8 sig[0x1]; 991 u8 reserved_1[0x1f]; 992 993 u8 reserved_2[0x20]; 994 995 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 996 997 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 998 999 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1000 1001 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1002 1003 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1004 1005 u8 reserved_3[0x6e0]; 1006 }; 1007 1008 enum { 1009 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1010 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1011 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1012 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1013 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1014 }; 1015 1016 enum { 1017 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1018 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1019 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1020 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1021 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1022 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1023 }; 1024 1025 enum { 1026 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1027 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1028 }; 1029 1030 enum { 1031 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1032 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1033 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1034 }; 1035 1036 struct mlx5_ifc_cmd_hca_cap_bits { 1037 u8 reserved_0[0x80]; 1038 1039 u8 log_max_srq_sz[0x8]; 1040 u8 log_max_qp_sz[0x8]; 1041 u8 reserved_1[0xb]; 1042 u8 log_max_qp[0x5]; 1043 1044 u8 reserved_2[0xb]; 1045 u8 log_max_srq[0x5]; 1046 u8 reserved_3[0x10]; 1047 1048 u8 reserved_4[0x8]; 1049 u8 log_max_cq_sz[0x8]; 1050 u8 reserved_5[0xb]; 1051 u8 log_max_cq[0x5]; 1052 1053 u8 log_max_eq_sz[0x8]; 1054 u8 relaxed_ordering_write[1]; 1055 u8 reserved_6[0x1]; 1056 u8 log_max_mkey[0x6]; 1057 u8 reserved_7[0xb]; 1058 u8 fast_teardown[0x1]; 1059 u8 log_max_eq[0x4]; 1060 1061 u8 max_indirection[0x8]; 1062 u8 reserved_8[0x1]; 1063 u8 log_max_mrw_sz[0x7]; 1064 u8 force_teardown[0x1]; 1065 u8 reserved_9[0x1]; 1066 u8 log_max_bsf_list_size[0x6]; 1067 u8 reserved_10[0x2]; 1068 u8 log_max_klm_list_size[0x6]; 1069 1070 u8 reserved_11[0xa]; 1071 u8 log_max_ra_req_dc[0x6]; 1072 u8 reserved_12[0xa]; 1073 u8 log_max_ra_res_dc[0x6]; 1074 1075 u8 reserved_13[0xa]; 1076 u8 log_max_ra_req_qp[0x6]; 1077 u8 reserved_14[0xa]; 1078 u8 log_max_ra_res_qp[0x6]; 1079 1080 u8 pad_cap[0x1]; 1081 u8 cc_query_allowed[0x1]; 1082 u8 cc_modify_allowed[0x1]; 1083 u8 start_pad[0x1]; 1084 u8 cache_line_128byte[0x1]; 1085 u8 reserved_at_165[0xa]; 1086 u8 qcam_reg[0x1]; 1087 u8 gid_table_size[0x10]; 1088 1089 u8 out_of_seq_cnt[0x1]; 1090 u8 vport_counters[0x1]; 1091 u8 retransmission_q_counters[0x1]; 1092 u8 debug[0x1]; 1093 u8 modify_rq_counters_set_id[0x1]; 1094 u8 rq_delay_drop[0x1]; 1095 u8 max_qp_cnt[0xa]; 1096 u8 pkey_table_size[0x10]; 1097 1098 u8 vport_group_manager[0x1]; 1099 u8 vhca_group_manager[0x1]; 1100 u8 ib_virt[0x1]; 1101 u8 eth_virt[0x1]; 1102 u8 reserved_17[0x1]; 1103 u8 ets[0x1]; 1104 u8 nic_flow_table[0x1]; 1105 u8 eswitch_flow_table[0x1]; 1106 u8 reserved_18[0x1]; 1107 u8 mcam_reg[0x1]; 1108 u8 pcam_reg[0x1]; 1109 u8 local_ca_ack_delay[0x5]; 1110 u8 port_module_event[0x1]; 1111 u8 reserved_19[0x5]; 1112 u8 port_type[0x2]; 1113 u8 num_ports[0x8]; 1114 1115 u8 snapshot[0x1]; 1116 u8 reserved_20[0x2]; 1117 u8 log_max_msg[0x5]; 1118 u8 reserved_21[0x4]; 1119 u8 max_tc[0x4]; 1120 u8 temp_warn_event[0x1]; 1121 u8 dcbx[0x1]; 1122 u8 general_notification_event[0x1]; 1123 u8 reserved_at_1d3[0x2]; 1124 u8 fpga[0x1]; 1125 u8 rol_s[0x1]; 1126 u8 rol_g[0x1]; 1127 u8 reserved_23[0x1]; 1128 u8 wol_s[0x1]; 1129 u8 wol_g[0x1]; 1130 u8 wol_a[0x1]; 1131 u8 wol_b[0x1]; 1132 u8 wol_m[0x1]; 1133 u8 wol_u[0x1]; 1134 u8 wol_p[0x1]; 1135 1136 u8 stat_rate_support[0x10]; 1137 u8 reserved_24[0xc]; 1138 u8 cqe_version[0x4]; 1139 1140 u8 compact_address_vector[0x1]; 1141 u8 striding_rq[0x1]; 1142 u8 reserved_25[0x1]; 1143 u8 ipoib_enhanced_offloads[0x1]; 1144 u8 ipoib_ipoib_offloads[0x1]; 1145 u8 reserved_26[0x8]; 1146 u8 dc_connect_qp[0x1]; 1147 u8 dc_cnak_trace[0x1]; 1148 u8 drain_sigerr[0x1]; 1149 u8 cmdif_checksum[0x2]; 1150 u8 sigerr_cqe[0x1]; 1151 u8 reserved_27[0x1]; 1152 u8 wq_signature[0x1]; 1153 u8 sctr_data_cqe[0x1]; 1154 u8 reserved_28[0x1]; 1155 u8 sho[0x1]; 1156 u8 tph[0x1]; 1157 u8 rf[0x1]; 1158 u8 dct[0x1]; 1159 u8 qos[0x1]; 1160 u8 eth_net_offloads[0x1]; 1161 u8 roce[0x1]; 1162 u8 atomic[0x1]; 1163 u8 reserved_30[0x1]; 1164 1165 u8 cq_oi[0x1]; 1166 u8 cq_resize[0x1]; 1167 u8 cq_moderation[0x1]; 1168 u8 cq_period_mode_modify[0x1]; 1169 u8 cq_invalidate[0x1]; 1170 u8 reserved_at_225[0x1]; 1171 u8 cq_eq_remap[0x1]; 1172 u8 pg[0x1]; 1173 u8 block_lb_mc[0x1]; 1174 u8 exponential_backoff[0x1]; 1175 u8 scqe_break_moderation[0x1]; 1176 u8 cq_period_start_from_cqe[0x1]; 1177 u8 cd[0x1]; 1178 u8 atm[0x1]; 1179 u8 apm[0x1]; 1180 u8 imaicl[0x1]; 1181 u8 reserved_32[0x6]; 1182 u8 qkv[0x1]; 1183 u8 pkv[0x1]; 1184 u8 set_deth_sqpn[0x1]; 1185 u8 reserved_33[0x3]; 1186 u8 xrc[0x1]; 1187 u8 ud[0x1]; 1188 u8 uc[0x1]; 1189 u8 rc[0x1]; 1190 1191 u8 reserved_34[0xa]; 1192 u8 uar_sz[0x6]; 1193 u8 reserved_35[0x8]; 1194 u8 log_pg_sz[0x8]; 1195 1196 u8 bf[0x1]; 1197 u8 driver_version[0x1]; 1198 u8 pad_tx_eth_packet[0x1]; 1199 u8 reserved_36[0x8]; 1200 u8 log_bf_reg_size[0x5]; 1201 u8 reserved_37[0x10]; 1202 1203 u8 num_of_diagnostic_counters[0x10]; 1204 u8 max_wqe_sz_sq[0x10]; 1205 1206 u8 reserved_38[0x10]; 1207 u8 max_wqe_sz_rq[0x10]; 1208 1209 u8 reserved_39[0x10]; 1210 u8 max_wqe_sz_sq_dc[0x10]; 1211 1212 u8 reserved_40[0x7]; 1213 u8 max_qp_mcg[0x19]; 1214 1215 u8 reserved_41[0x18]; 1216 u8 log_max_mcg[0x8]; 1217 1218 u8 reserved_42[0x3]; 1219 u8 log_max_transport_domain[0x5]; 1220 u8 reserved_43[0x3]; 1221 u8 log_max_pd[0x5]; 1222 u8 reserved_44[0xb]; 1223 u8 log_max_xrcd[0x5]; 1224 1225 u8 reserved_45[0x10]; 1226 u8 max_flow_counter[0x10]; 1227 1228 u8 reserved_46[0x3]; 1229 u8 log_max_rq[0x5]; 1230 u8 reserved_47[0x3]; 1231 u8 log_max_sq[0x5]; 1232 u8 reserved_48[0x3]; 1233 u8 log_max_tir[0x5]; 1234 u8 reserved_49[0x3]; 1235 u8 log_max_tis[0x5]; 1236 1237 u8 basic_cyclic_rcv_wqe[0x1]; 1238 u8 reserved_50[0x2]; 1239 u8 log_max_rmp[0x5]; 1240 u8 reserved_51[0x3]; 1241 u8 log_max_rqt[0x5]; 1242 u8 reserved_52[0x3]; 1243 u8 log_max_rqt_size[0x5]; 1244 u8 reserved_53[0x3]; 1245 u8 log_max_tis_per_sq[0x5]; 1246 1247 u8 reserved_54[0x3]; 1248 u8 log_max_stride_sz_rq[0x5]; 1249 u8 reserved_55[0x3]; 1250 u8 log_min_stride_sz_rq[0x5]; 1251 u8 reserved_56[0x3]; 1252 u8 log_max_stride_sz_sq[0x5]; 1253 u8 reserved_57[0x3]; 1254 u8 log_min_stride_sz_sq[0x5]; 1255 1256 u8 reserved_58[0x1b]; 1257 u8 log_max_wq_sz[0x5]; 1258 1259 u8 nic_vport_change_event[0x1]; 1260 u8 disable_local_lb[0x1]; 1261 u8 reserved_59[0x9]; 1262 u8 log_max_vlan_list[0x5]; 1263 u8 reserved_60[0x3]; 1264 u8 log_max_current_mc_list[0x5]; 1265 u8 reserved_61[0x3]; 1266 u8 log_max_current_uc_list[0x5]; 1267 1268 u8 reserved_62[0x80]; 1269 1270 u8 reserved_63[0x3]; 1271 u8 log_max_l2_table[0x5]; 1272 u8 reserved_64[0x8]; 1273 u8 log_uar_page_sz[0x10]; 1274 1275 u8 reserved_65[0x20]; 1276 1277 u8 device_frequency_mhz[0x20]; 1278 1279 u8 device_frequency_khz[0x20]; 1280 1281 u8 reserved_66[0x80]; 1282 1283 u8 log_max_atomic_size_qp[0x8]; 1284 u8 reserved_67[0x10]; 1285 u8 log_max_atomic_size_dc[0x8]; 1286 1287 u8 reserved_68[0x1f]; 1288 u8 cqe_compression[0x1]; 1289 1290 u8 cqe_compression_timeout[0x10]; 1291 u8 cqe_compression_max_num[0x10]; 1292 1293 u8 reserved_69[0x220]; 1294 }; 1295 1296 enum mlx5_flow_destination_type { 1297 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1298 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1299 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1300 }; 1301 1302 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1303 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1304 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1305 u8 reserved_0[0x40]; 1306 }; 1307 1308 struct mlx5_ifc_fte_match_param_bits { 1309 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1310 1311 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1312 1313 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1314 1315 u8 reserved_0[0xa00]; 1316 }; 1317 1318 enum { 1319 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1320 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1321 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1322 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1323 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1324 }; 1325 1326 struct mlx5_ifc_rx_hash_field_select_bits { 1327 u8 l3_prot_type[0x1]; 1328 u8 l4_prot_type[0x1]; 1329 u8 selected_fields[0x1e]; 1330 }; 1331 1332 enum { 1333 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1334 MLX5_WQ_TYPE_CYCLIC = 0x1, 1335 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1336 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1337 }; 1338 1339 enum rq_type { 1340 RQ_TYPE_NONE, 1341 RQ_TYPE_STRIDE, 1342 }; 1343 1344 enum { 1345 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1346 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1347 }; 1348 1349 struct mlx5_ifc_wq_bits { 1350 u8 wq_type[0x4]; 1351 u8 wq_signature[0x1]; 1352 u8 end_padding_mode[0x2]; 1353 u8 cd_slave[0x1]; 1354 u8 reserved_0[0x18]; 1355 1356 u8 hds_skip_first_sge[0x1]; 1357 u8 log2_hds_buf_size[0x3]; 1358 u8 reserved_1[0x7]; 1359 u8 page_offset[0x5]; 1360 u8 lwm[0x10]; 1361 1362 u8 reserved_2[0x8]; 1363 u8 pd[0x18]; 1364 1365 u8 reserved_3[0x8]; 1366 u8 uar_page[0x18]; 1367 1368 u8 dbr_addr[0x40]; 1369 1370 u8 hw_counter[0x20]; 1371 1372 u8 sw_counter[0x20]; 1373 1374 u8 reserved_4[0xc]; 1375 u8 log_wq_stride[0x4]; 1376 u8 reserved_5[0x3]; 1377 u8 log_wq_pg_sz[0x5]; 1378 u8 reserved_6[0x3]; 1379 u8 log_wq_sz[0x5]; 1380 1381 u8 reserved_7[0x15]; 1382 u8 single_wqe_log_num_of_strides[0x3]; 1383 u8 two_byte_shift_en[0x1]; 1384 u8 reserved_8[0x4]; 1385 u8 single_stride_log_num_of_bytes[0x3]; 1386 1387 u8 reserved_9[0x4c0]; 1388 1389 struct mlx5_ifc_cmd_pas_bits pas[0]; 1390 }; 1391 1392 struct mlx5_ifc_rq_num_bits { 1393 u8 reserved_0[0x8]; 1394 u8 rq_num[0x18]; 1395 }; 1396 1397 struct mlx5_ifc_mac_address_layout_bits { 1398 u8 reserved_0[0x10]; 1399 u8 mac_addr_47_32[0x10]; 1400 1401 u8 mac_addr_31_0[0x20]; 1402 }; 1403 1404 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1405 u8 reserved_0[0xa0]; 1406 1407 u8 min_time_between_cnps[0x20]; 1408 1409 u8 reserved_1[0x12]; 1410 u8 cnp_dscp[0x6]; 1411 u8 reserved_2[0x4]; 1412 u8 cnp_prio_mode[0x1]; 1413 u8 cnp_802p_prio[0x3]; 1414 1415 u8 reserved_3[0x720]; 1416 }; 1417 1418 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1419 u8 reserved_0[0x60]; 1420 1421 u8 reserved_1[0x4]; 1422 u8 clamp_tgt_rate[0x1]; 1423 u8 reserved_2[0x3]; 1424 u8 clamp_tgt_rate_after_time_inc[0x1]; 1425 u8 reserved_3[0x17]; 1426 1427 u8 reserved_4[0x20]; 1428 1429 u8 rpg_time_reset[0x20]; 1430 1431 u8 rpg_byte_reset[0x20]; 1432 1433 u8 rpg_threshold[0x20]; 1434 1435 u8 rpg_max_rate[0x20]; 1436 1437 u8 rpg_ai_rate[0x20]; 1438 1439 u8 rpg_hai_rate[0x20]; 1440 1441 u8 rpg_gd[0x20]; 1442 1443 u8 rpg_min_dec_fac[0x20]; 1444 1445 u8 rpg_min_rate[0x20]; 1446 1447 u8 reserved_5[0xe0]; 1448 1449 u8 rate_to_set_on_first_cnp[0x20]; 1450 1451 u8 dce_tcp_g[0x20]; 1452 1453 u8 dce_tcp_rtt[0x20]; 1454 1455 u8 rate_reduce_monitor_period[0x20]; 1456 1457 u8 reserved_6[0x20]; 1458 1459 u8 initial_alpha_value[0x20]; 1460 1461 u8 reserved_7[0x4a0]; 1462 }; 1463 1464 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1465 u8 reserved_0[0x80]; 1466 1467 u8 rppp_max_rps[0x20]; 1468 1469 u8 rpg_time_reset[0x20]; 1470 1471 u8 rpg_byte_reset[0x20]; 1472 1473 u8 rpg_threshold[0x20]; 1474 1475 u8 rpg_max_rate[0x20]; 1476 1477 u8 rpg_ai_rate[0x20]; 1478 1479 u8 rpg_hai_rate[0x20]; 1480 1481 u8 rpg_gd[0x20]; 1482 1483 u8 rpg_min_dec_fac[0x20]; 1484 1485 u8 rpg_min_rate[0x20]; 1486 1487 u8 reserved_1[0x640]; 1488 }; 1489 1490 enum { 1491 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1492 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1493 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1494 }; 1495 1496 struct mlx5_ifc_resize_field_select_bits { 1497 u8 resize_field_select[0x20]; 1498 }; 1499 1500 enum { 1501 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1502 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1503 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1504 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1505 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1506 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1507 }; 1508 1509 struct mlx5_ifc_modify_field_select_bits { 1510 u8 modify_field_select[0x20]; 1511 }; 1512 1513 struct mlx5_ifc_field_select_r_roce_np_bits { 1514 u8 field_select_r_roce_np[0x20]; 1515 }; 1516 1517 enum { 1518 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1519 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1520 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1521 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1522 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1523 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1524 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1525 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1526 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1527 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1528 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1529 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1530 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1531 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1532 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1533 }; 1534 1535 struct mlx5_ifc_field_select_r_roce_rp_bits { 1536 u8 field_select_r_roce_rp[0x20]; 1537 }; 1538 1539 enum { 1540 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1541 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1542 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1543 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1544 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1545 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1546 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1547 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1548 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1549 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1550 }; 1551 1552 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1553 u8 field_select_8021qaurp[0x20]; 1554 }; 1555 1556 struct mlx5_ifc_pptb_reg_bits { 1557 u8 reserved_0[0x2]; 1558 u8 mm[0x2]; 1559 u8 reserved_1[0x4]; 1560 u8 local_port[0x8]; 1561 u8 reserved_2[0x6]; 1562 u8 cm[0x1]; 1563 u8 um[0x1]; 1564 u8 pm[0x8]; 1565 1566 u8 prio7buff[0x4]; 1567 u8 prio6buff[0x4]; 1568 u8 prio5buff[0x4]; 1569 u8 prio4buff[0x4]; 1570 u8 prio3buff[0x4]; 1571 u8 prio2buff[0x4]; 1572 u8 prio1buff[0x4]; 1573 u8 prio0buff[0x4]; 1574 1575 u8 pm_msb[0x8]; 1576 u8 reserved_3[0x10]; 1577 u8 ctrl_buff[0x4]; 1578 u8 untagged_buff[0x4]; 1579 }; 1580 1581 struct mlx5_ifc_dcbx_app_reg_bits { 1582 u8 reserved_0[0x8]; 1583 u8 port_number[0x8]; 1584 u8 reserved_1[0x10]; 1585 1586 u8 reserved_2[0x1a]; 1587 u8 num_app_prio[0x6]; 1588 1589 u8 reserved_3[0x40]; 1590 1591 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1592 }; 1593 1594 struct mlx5_ifc_dcbx_param_reg_bits { 1595 u8 dcbx_cee_cap[0x1]; 1596 u8 dcbx_ieee_cap[0x1]; 1597 u8 dcbx_standby_cap[0x1]; 1598 u8 reserved_0[0x5]; 1599 u8 port_number[0x8]; 1600 u8 reserved_1[0xa]; 1601 u8 max_application_table_size[0x6]; 1602 1603 u8 reserved_2[0x15]; 1604 u8 version_oper[0x3]; 1605 u8 reserved_3[0x5]; 1606 u8 version_admin[0x3]; 1607 1608 u8 willing_admin[0x1]; 1609 u8 reserved_4[0x3]; 1610 u8 pfc_cap_oper[0x4]; 1611 u8 reserved_5[0x4]; 1612 u8 pfc_cap_admin[0x4]; 1613 u8 reserved_6[0x4]; 1614 u8 num_of_tc_oper[0x4]; 1615 u8 reserved_7[0x4]; 1616 u8 num_of_tc_admin[0x4]; 1617 1618 u8 remote_willing[0x1]; 1619 u8 reserved_8[0x3]; 1620 u8 remote_pfc_cap[0x4]; 1621 u8 reserved_9[0x14]; 1622 u8 remote_num_of_tc[0x4]; 1623 1624 u8 reserved_10[0x18]; 1625 u8 error[0x8]; 1626 1627 u8 reserved_11[0x160]; 1628 }; 1629 1630 struct mlx5_ifc_qhll_bits { 1631 u8 reserved_at_0[0x8]; 1632 u8 local_port[0x8]; 1633 u8 reserved_at_10[0x10]; 1634 1635 u8 reserved_at_20[0x1b]; 1636 u8 hll_time[0x5]; 1637 1638 u8 stall_en[0x1]; 1639 u8 reserved_at_41[0x1c]; 1640 u8 stall_cnt[0x3]; 1641 }; 1642 1643 struct mlx5_ifc_qetcr_reg_bits { 1644 u8 operation_type[0x2]; 1645 u8 cap_local_admin[0x1]; 1646 u8 cap_remote_admin[0x1]; 1647 u8 reserved_0[0x4]; 1648 u8 port_number[0x8]; 1649 u8 reserved_1[0x10]; 1650 1651 u8 reserved_2[0x20]; 1652 1653 u8 tc[8][0x40]; 1654 1655 u8 global_configuration[0x40]; 1656 }; 1657 1658 struct mlx5_ifc_nodnic_ring_config_reg_bits { 1659 u8 queue_address_63_32[0x20]; 1660 1661 u8 queue_address_31_12[0x14]; 1662 u8 reserved_0[0x6]; 1663 u8 log_size[0x6]; 1664 1665 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1666 1667 u8 reserved_1[0x8]; 1668 u8 queue_number[0x18]; 1669 1670 u8 q_key[0x20]; 1671 1672 u8 reserved_2[0x10]; 1673 u8 pkey_index[0x10]; 1674 1675 u8 reserved_3[0x40]; 1676 }; 1677 1678 struct mlx5_ifc_nodnic_cq_arming_word_bits { 1679 u8 reserved_0[0x8]; 1680 u8 cq_ci[0x10]; 1681 u8 reserved_1[0x8]; 1682 }; 1683 1684 enum { 1685 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1686 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1687 }; 1688 1689 enum { 1690 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1691 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1692 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1693 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1694 }; 1695 1696 struct mlx5_ifc_nodnic_event_word_bits { 1697 u8 driver_reset_needed[0x1]; 1698 u8 port_management_change_event[0x1]; 1699 u8 reserved_0[0x19]; 1700 u8 link_type[0x1]; 1701 u8 port_state[0x4]; 1702 }; 1703 1704 struct mlx5_ifc_nic_vport_change_event_bits { 1705 u8 reserved_0[0x10]; 1706 u8 vport_num[0x10]; 1707 1708 u8 reserved_1[0xc0]; 1709 }; 1710 1711 struct mlx5_ifc_pages_req_event_bits { 1712 u8 reserved_0[0x10]; 1713 u8 function_id[0x10]; 1714 1715 u8 num_pages[0x20]; 1716 1717 u8 reserved_1[0xa0]; 1718 }; 1719 1720 struct mlx5_ifc_cmd_inter_comp_event_bits { 1721 u8 command_completion_vector[0x20]; 1722 1723 u8 reserved_0[0xc0]; 1724 }; 1725 1726 struct mlx5_ifc_stall_vl_event_bits { 1727 u8 reserved_0[0x18]; 1728 u8 port_num[0x1]; 1729 u8 reserved_1[0x3]; 1730 u8 vl[0x4]; 1731 1732 u8 reserved_2[0xa0]; 1733 }; 1734 1735 struct mlx5_ifc_db_bf_congestion_event_bits { 1736 u8 event_subtype[0x8]; 1737 u8 reserved_0[0x8]; 1738 u8 congestion_level[0x8]; 1739 u8 reserved_1[0x8]; 1740 1741 u8 reserved_2[0xa0]; 1742 }; 1743 1744 struct mlx5_ifc_gpio_event_bits { 1745 u8 reserved_0[0x60]; 1746 1747 u8 gpio_event_hi[0x20]; 1748 1749 u8 gpio_event_lo[0x20]; 1750 1751 u8 reserved_1[0x40]; 1752 }; 1753 1754 struct mlx5_ifc_port_state_change_event_bits { 1755 u8 reserved_0[0x40]; 1756 1757 u8 port_num[0x4]; 1758 u8 reserved_1[0x1c]; 1759 1760 u8 reserved_2[0x80]; 1761 }; 1762 1763 struct mlx5_ifc_dropped_packet_logged_bits { 1764 u8 reserved_0[0xe0]; 1765 }; 1766 1767 enum { 1768 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1769 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1770 }; 1771 1772 struct mlx5_ifc_cq_error_bits { 1773 u8 reserved_0[0x8]; 1774 u8 cqn[0x18]; 1775 1776 u8 reserved_1[0x20]; 1777 1778 u8 reserved_2[0x18]; 1779 u8 syndrome[0x8]; 1780 1781 u8 reserved_3[0x80]; 1782 }; 1783 1784 struct mlx5_ifc_rdma_page_fault_event_bits { 1785 u8 bytes_commited[0x20]; 1786 1787 u8 r_key[0x20]; 1788 1789 u8 reserved_0[0x10]; 1790 u8 packet_len[0x10]; 1791 1792 u8 rdma_op_len[0x20]; 1793 1794 u8 rdma_va[0x40]; 1795 1796 u8 reserved_1[0x5]; 1797 u8 rdma[0x1]; 1798 u8 write[0x1]; 1799 u8 requestor[0x1]; 1800 u8 qp_number[0x18]; 1801 }; 1802 1803 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1804 u8 bytes_committed[0x20]; 1805 1806 u8 reserved_0[0x10]; 1807 u8 wqe_index[0x10]; 1808 1809 u8 reserved_1[0x10]; 1810 u8 len[0x10]; 1811 1812 u8 reserved_2[0x60]; 1813 1814 u8 reserved_3[0x5]; 1815 u8 rdma[0x1]; 1816 u8 write_read[0x1]; 1817 u8 requestor[0x1]; 1818 u8 qpn[0x18]; 1819 }; 1820 1821 enum { 1822 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1823 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1824 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1825 }; 1826 1827 struct mlx5_ifc_qp_events_bits { 1828 u8 reserved_0[0xa0]; 1829 1830 u8 type[0x8]; 1831 u8 reserved_1[0x18]; 1832 1833 u8 reserved_2[0x8]; 1834 u8 qpn_rqn_sqn[0x18]; 1835 }; 1836 1837 struct mlx5_ifc_dct_events_bits { 1838 u8 reserved_0[0xc0]; 1839 1840 u8 reserved_1[0x8]; 1841 u8 dct_number[0x18]; 1842 }; 1843 1844 struct mlx5_ifc_comp_event_bits { 1845 u8 reserved_0[0xc0]; 1846 1847 u8 reserved_1[0x8]; 1848 u8 cq_number[0x18]; 1849 }; 1850 1851 struct mlx5_ifc_fw_version_bits { 1852 u8 major[0x10]; 1853 u8 reserved_0[0x10]; 1854 1855 u8 minor[0x10]; 1856 u8 subminor[0x10]; 1857 1858 u8 second[0x8]; 1859 u8 minute[0x8]; 1860 u8 hour[0x8]; 1861 u8 reserved_1[0x8]; 1862 1863 u8 year[0x10]; 1864 u8 month[0x8]; 1865 u8 day[0x8]; 1866 }; 1867 1868 enum { 1869 MLX5_QPC_STATE_RST = 0x0, 1870 MLX5_QPC_STATE_INIT = 0x1, 1871 MLX5_QPC_STATE_RTR = 0x2, 1872 MLX5_QPC_STATE_RTS = 0x3, 1873 MLX5_QPC_STATE_SQER = 0x4, 1874 MLX5_QPC_STATE_SQD = 0x5, 1875 MLX5_QPC_STATE_ERR = 0x6, 1876 MLX5_QPC_STATE_SUSPENDED = 0x9, 1877 }; 1878 1879 enum { 1880 MLX5_QPC_ST_RC = 0x0, 1881 MLX5_QPC_ST_UC = 0x1, 1882 MLX5_QPC_ST_UD = 0x2, 1883 MLX5_QPC_ST_XRC = 0x3, 1884 MLX5_QPC_ST_DCI = 0x5, 1885 MLX5_QPC_ST_QP0 = 0x7, 1886 MLX5_QPC_ST_QP1 = 0x8, 1887 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1888 MLX5_QPC_ST_REG_UMR = 0xc, 1889 }; 1890 1891 enum { 1892 MLX5_QP_PM_ARMED = 0x0, 1893 MLX5_QP_PM_REARM = 0x1, 1894 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1895 MLX5_QP_PM_MIGRATED = 0x3, 1896 }; 1897 1898 enum { 1899 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1900 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1901 }; 1902 1903 enum { 1904 MLX5_QPC_MTU_256_BYTES = 0x1, 1905 MLX5_QPC_MTU_512_BYTES = 0x2, 1906 MLX5_QPC_MTU_1K_BYTES = 0x3, 1907 MLX5_QPC_MTU_2K_BYTES = 0x4, 1908 MLX5_QPC_MTU_4K_BYTES = 0x5, 1909 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1910 }; 1911 1912 enum { 1913 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1914 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1915 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1916 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1917 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1918 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1919 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1920 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1921 }; 1922 1923 enum { 1924 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1925 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1926 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1927 }; 1928 1929 enum { 1930 MLX5_QPC_CS_RES_DISABLE = 0x0, 1931 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1932 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1933 }; 1934 1935 struct mlx5_ifc_qpc_bits { 1936 u8 state[0x4]; 1937 u8 lag_tx_port_affinity[0x4]; 1938 u8 st[0x8]; 1939 u8 reserved_1[0x3]; 1940 u8 pm_state[0x2]; 1941 u8 reserved_2[0x7]; 1942 u8 end_padding_mode[0x2]; 1943 u8 reserved_3[0x2]; 1944 1945 u8 wq_signature[0x1]; 1946 u8 block_lb_mc[0x1]; 1947 u8 atomic_like_write_en[0x1]; 1948 u8 latency_sensitive[0x1]; 1949 u8 reserved_4[0x1]; 1950 u8 drain_sigerr[0x1]; 1951 u8 reserved_5[0x2]; 1952 u8 pd[0x18]; 1953 1954 u8 mtu[0x3]; 1955 u8 log_msg_max[0x5]; 1956 u8 reserved_6[0x1]; 1957 u8 log_rq_size[0x4]; 1958 u8 log_rq_stride[0x3]; 1959 u8 no_sq[0x1]; 1960 u8 log_sq_size[0x4]; 1961 u8 reserved_7[0x6]; 1962 u8 rlky[0x1]; 1963 u8 ulp_stateless_offload_mode[0x4]; 1964 1965 u8 counter_set_id[0x8]; 1966 u8 uar_page[0x18]; 1967 1968 u8 reserved_8[0x8]; 1969 u8 user_index[0x18]; 1970 1971 u8 reserved_9[0x3]; 1972 u8 log_page_size[0x5]; 1973 u8 remote_qpn[0x18]; 1974 1975 struct mlx5_ifc_ads_bits primary_address_path; 1976 1977 struct mlx5_ifc_ads_bits secondary_address_path; 1978 1979 u8 log_ack_req_freq[0x4]; 1980 u8 reserved_10[0x4]; 1981 u8 log_sra_max[0x3]; 1982 u8 reserved_11[0x2]; 1983 u8 retry_count[0x3]; 1984 u8 rnr_retry[0x3]; 1985 u8 reserved_12[0x1]; 1986 u8 fre[0x1]; 1987 u8 cur_rnr_retry[0x3]; 1988 u8 cur_retry_count[0x3]; 1989 u8 reserved_13[0x5]; 1990 1991 u8 reserved_14[0x20]; 1992 1993 u8 reserved_15[0x8]; 1994 u8 next_send_psn[0x18]; 1995 1996 u8 reserved_16[0x8]; 1997 u8 cqn_snd[0x18]; 1998 1999 u8 reserved_at_400[0x8]; 2000 2001 u8 deth_sqpn[0x18]; 2002 u8 reserved_17[0x20]; 2003 2004 u8 reserved_18[0x8]; 2005 u8 last_acked_psn[0x18]; 2006 2007 u8 reserved_19[0x8]; 2008 u8 ssn[0x18]; 2009 2010 u8 reserved_20[0x8]; 2011 u8 log_rra_max[0x3]; 2012 u8 reserved_21[0x1]; 2013 u8 atomic_mode[0x4]; 2014 u8 rre[0x1]; 2015 u8 rwe[0x1]; 2016 u8 rae[0x1]; 2017 u8 reserved_22[0x1]; 2018 u8 page_offset[0x6]; 2019 u8 reserved_23[0x3]; 2020 u8 cd_slave_receive[0x1]; 2021 u8 cd_slave_send[0x1]; 2022 u8 cd_master[0x1]; 2023 2024 u8 reserved_24[0x3]; 2025 u8 min_rnr_nak[0x5]; 2026 u8 next_rcv_psn[0x18]; 2027 2028 u8 reserved_25[0x8]; 2029 u8 xrcd[0x18]; 2030 2031 u8 reserved_26[0x8]; 2032 u8 cqn_rcv[0x18]; 2033 2034 u8 dbr_addr[0x40]; 2035 2036 u8 q_key[0x20]; 2037 2038 u8 reserved_27[0x5]; 2039 u8 rq_type[0x3]; 2040 u8 srqn_rmpn[0x18]; 2041 2042 u8 reserved_28[0x8]; 2043 u8 rmsn[0x18]; 2044 2045 u8 hw_sq_wqebb_counter[0x10]; 2046 u8 sw_sq_wqebb_counter[0x10]; 2047 2048 u8 hw_rq_counter[0x20]; 2049 2050 u8 sw_rq_counter[0x20]; 2051 2052 u8 reserved_29[0x20]; 2053 2054 u8 reserved_30[0xf]; 2055 u8 cgs[0x1]; 2056 u8 cs_req[0x8]; 2057 u8 cs_res[0x8]; 2058 2059 u8 dc_access_key[0x40]; 2060 2061 u8 rdma_active[0x1]; 2062 u8 comm_est[0x1]; 2063 u8 suspended[0x1]; 2064 u8 reserved_31[0x5]; 2065 u8 send_msg_psn[0x18]; 2066 2067 u8 reserved_32[0x8]; 2068 u8 rcv_msg_psn[0x18]; 2069 2070 u8 rdma_va[0x40]; 2071 2072 u8 rdma_key[0x20]; 2073 2074 u8 reserved_33[0x20]; 2075 }; 2076 2077 struct mlx5_ifc_roce_addr_layout_bits { 2078 u8 source_l3_address[16][0x8]; 2079 2080 u8 reserved_0[0x3]; 2081 u8 vlan_valid[0x1]; 2082 u8 vlan_id[0xc]; 2083 u8 source_mac_47_32[0x10]; 2084 2085 u8 source_mac_31_0[0x20]; 2086 2087 u8 reserved_1[0x14]; 2088 u8 roce_l3_type[0x4]; 2089 u8 roce_version[0x8]; 2090 2091 u8 reserved_2[0x20]; 2092 }; 2093 2094 struct mlx5_ifc_rdbc_bits { 2095 u8 reserved_0[0x1c]; 2096 u8 type[0x4]; 2097 2098 u8 reserved_1[0x20]; 2099 2100 u8 reserved_2[0x8]; 2101 u8 psn[0x18]; 2102 2103 u8 rkey[0x20]; 2104 2105 u8 address[0x40]; 2106 2107 u8 byte_count[0x20]; 2108 2109 u8 reserved_3[0x20]; 2110 2111 u8 atomic_resp[32][0x8]; 2112 }; 2113 2114 enum { 2115 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2116 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2117 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2118 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2119 }; 2120 2121 struct mlx5_ifc_flow_context_bits { 2122 u8 reserved_0[0x20]; 2123 2124 u8 group_id[0x20]; 2125 2126 u8 reserved_1[0x8]; 2127 u8 flow_tag[0x18]; 2128 2129 u8 reserved_2[0x10]; 2130 u8 action[0x10]; 2131 2132 u8 reserved_3[0x8]; 2133 u8 destination_list_size[0x18]; 2134 2135 u8 reserved_4[0x8]; 2136 u8 flow_counter_list_size[0x18]; 2137 2138 u8 reserved_5[0x140]; 2139 2140 struct mlx5_ifc_fte_match_param_bits match_value; 2141 2142 u8 reserved_6[0x600]; 2143 2144 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2145 }; 2146 2147 enum { 2148 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2149 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2150 }; 2151 2152 struct mlx5_ifc_xrc_srqc_bits { 2153 u8 state[0x4]; 2154 u8 log_xrc_srq_size[0x4]; 2155 u8 reserved_0[0x18]; 2156 2157 u8 wq_signature[0x1]; 2158 u8 cont_srq[0x1]; 2159 u8 reserved_1[0x1]; 2160 u8 rlky[0x1]; 2161 u8 basic_cyclic_rcv_wqe[0x1]; 2162 u8 log_rq_stride[0x3]; 2163 u8 xrcd[0x18]; 2164 2165 u8 page_offset[0x6]; 2166 u8 reserved_2[0x2]; 2167 u8 cqn[0x18]; 2168 2169 u8 reserved_3[0x20]; 2170 2171 u8 reserved_4[0x2]; 2172 u8 log_page_size[0x6]; 2173 u8 user_index[0x18]; 2174 2175 u8 reserved_5[0x20]; 2176 2177 u8 reserved_6[0x8]; 2178 u8 pd[0x18]; 2179 2180 u8 lwm[0x10]; 2181 u8 wqe_cnt[0x10]; 2182 2183 u8 reserved_7[0x40]; 2184 2185 u8 db_record_addr_h[0x20]; 2186 2187 u8 db_record_addr_l[0x1e]; 2188 u8 reserved_8[0x2]; 2189 2190 u8 reserved_9[0x80]; 2191 }; 2192 2193 struct mlx5_ifc_traffic_counter_bits { 2194 u8 packets[0x40]; 2195 2196 u8 octets[0x40]; 2197 }; 2198 2199 struct mlx5_ifc_tisc_bits { 2200 u8 strict_lag_tx_port_affinity[0x1]; 2201 u8 reserved_at_1[0x3]; 2202 u8 lag_tx_port_affinity[0x04]; 2203 2204 u8 reserved_at_8[0x4]; 2205 u8 prio[0x4]; 2206 u8 reserved_1[0x10]; 2207 2208 u8 reserved_2[0x100]; 2209 2210 u8 reserved_3[0x8]; 2211 u8 transport_domain[0x18]; 2212 2213 u8 reserved_4[0x8]; 2214 u8 underlay_qpn[0x18]; 2215 2216 u8 reserved_5[0x3a0]; 2217 }; 2218 2219 enum { 2220 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2221 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2222 }; 2223 2224 enum { 2225 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2226 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2227 }; 2228 2229 enum { 2230 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2231 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2232 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2233 }; 2234 2235 enum { 2236 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2237 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2238 }; 2239 2240 struct mlx5_ifc_tirc_bits { 2241 u8 reserved_0[0x20]; 2242 2243 u8 disp_type[0x4]; 2244 u8 reserved_1[0x1c]; 2245 2246 u8 reserved_2[0x40]; 2247 2248 u8 reserved_3[0x4]; 2249 u8 lro_timeout_period_usecs[0x10]; 2250 u8 lro_enable_mask[0x4]; 2251 u8 lro_max_msg_sz[0x8]; 2252 2253 u8 reserved_4[0x40]; 2254 2255 u8 reserved_5[0x8]; 2256 u8 inline_rqn[0x18]; 2257 2258 u8 rx_hash_symmetric[0x1]; 2259 u8 reserved_6[0x1]; 2260 u8 tunneled_offload_en[0x1]; 2261 u8 reserved_7[0x5]; 2262 u8 indirect_table[0x18]; 2263 2264 u8 rx_hash_fn[0x4]; 2265 u8 reserved_8[0x2]; 2266 u8 self_lb_en[0x2]; 2267 u8 transport_domain[0x18]; 2268 2269 u8 rx_hash_toeplitz_key[10][0x20]; 2270 2271 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2272 2273 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2274 2275 u8 reserved_9[0x4c0]; 2276 }; 2277 2278 enum { 2279 MLX5_SRQC_STATE_GOOD = 0x0, 2280 MLX5_SRQC_STATE_ERROR = 0x1, 2281 }; 2282 2283 struct mlx5_ifc_srqc_bits { 2284 u8 state[0x4]; 2285 u8 log_srq_size[0x4]; 2286 u8 reserved_0[0x18]; 2287 2288 u8 wq_signature[0x1]; 2289 u8 cont_srq[0x1]; 2290 u8 reserved_1[0x1]; 2291 u8 rlky[0x1]; 2292 u8 reserved_2[0x1]; 2293 u8 log_rq_stride[0x3]; 2294 u8 xrcd[0x18]; 2295 2296 u8 page_offset[0x6]; 2297 u8 reserved_3[0x2]; 2298 u8 cqn[0x18]; 2299 2300 u8 reserved_4[0x20]; 2301 2302 u8 reserved_5[0x2]; 2303 u8 log_page_size[0x6]; 2304 u8 reserved_6[0x18]; 2305 2306 u8 reserved_7[0x20]; 2307 2308 u8 reserved_8[0x8]; 2309 u8 pd[0x18]; 2310 2311 u8 lwm[0x10]; 2312 u8 wqe_cnt[0x10]; 2313 2314 u8 reserved_9[0x40]; 2315 2316 u8 dbr_addr[0x40]; 2317 2318 u8 reserved_10[0x80]; 2319 }; 2320 2321 enum { 2322 MLX5_SQC_STATE_RST = 0x0, 2323 MLX5_SQC_STATE_RDY = 0x1, 2324 MLX5_SQC_STATE_ERR = 0x3, 2325 }; 2326 2327 struct mlx5_ifc_sqc_bits { 2328 u8 rlkey[0x1]; 2329 u8 cd_master[0x1]; 2330 u8 fre[0x1]; 2331 u8 flush_in_error_en[0x1]; 2332 u8 allow_multi_pkt_send_wqe[0x1]; 2333 u8 min_wqe_inline_mode[0x3]; 2334 u8 state[0x4]; 2335 u8 reg_umr[0x1]; 2336 u8 allow_swp[0x1]; 2337 u8 reserved_0[0x12]; 2338 2339 u8 reserved_1[0x8]; 2340 u8 user_index[0x18]; 2341 2342 u8 reserved_2[0x8]; 2343 u8 cqn[0x18]; 2344 2345 u8 reserved_3[0x80]; 2346 2347 u8 qos_para_vport_number[0x10]; 2348 u8 packet_pacing_rate_limit_index[0x10]; 2349 2350 u8 tis_lst_sz[0x10]; 2351 u8 reserved_4[0x10]; 2352 2353 u8 reserved_5[0x40]; 2354 2355 u8 reserved_6[0x8]; 2356 u8 tis_num_0[0x18]; 2357 2358 struct mlx5_ifc_wq_bits wq; 2359 }; 2360 2361 enum { 2362 MLX5_TSAR_TYPE_DWRR = 0, 2363 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2364 MLX5_TSAR_TYPE_ETS = 2 2365 }; 2366 2367 struct mlx5_ifc_tsar_element_attributes_bits { 2368 u8 reserved_0[0x8]; 2369 u8 tsar_type[0x8]; 2370 u8 reserved_1[0x10]; 2371 }; 2372 2373 struct mlx5_ifc_vport_element_attributes_bits { 2374 u8 reserved_0[0x10]; 2375 u8 vport_number[0x10]; 2376 }; 2377 2378 struct mlx5_ifc_vport_tc_element_attributes_bits { 2379 u8 traffic_class[0x10]; 2380 u8 vport_number[0x10]; 2381 }; 2382 2383 struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2384 u8 reserved_0[0x0C]; 2385 u8 traffic_class[0x04]; 2386 u8 qos_para_vport_number[0x10]; 2387 }; 2388 2389 enum { 2390 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2391 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2392 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2393 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2394 }; 2395 2396 struct mlx5_ifc_scheduling_context_bits { 2397 u8 element_type[0x8]; 2398 u8 reserved_at_8[0x18]; 2399 2400 u8 element_attributes[0x20]; 2401 2402 u8 parent_element_id[0x20]; 2403 2404 u8 reserved_at_60[0x40]; 2405 2406 u8 bw_share[0x20]; 2407 2408 u8 max_average_bw[0x20]; 2409 2410 u8 reserved_at_e0[0x120]; 2411 }; 2412 2413 struct mlx5_ifc_rqtc_bits { 2414 u8 reserved_0[0xa0]; 2415 2416 u8 reserved_1[0x10]; 2417 u8 rqt_max_size[0x10]; 2418 2419 u8 reserved_2[0x10]; 2420 u8 rqt_actual_size[0x10]; 2421 2422 u8 reserved_3[0x6a0]; 2423 2424 struct mlx5_ifc_rq_num_bits rq_num[0]; 2425 }; 2426 2427 enum { 2428 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2429 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2430 }; 2431 2432 enum { 2433 MLX5_RQC_STATE_RST = 0x0, 2434 MLX5_RQC_STATE_RDY = 0x1, 2435 MLX5_RQC_STATE_ERR = 0x3, 2436 }; 2437 2438 enum { 2439 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2440 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2441 }; 2442 2443 struct mlx5_ifc_rqc_bits { 2444 u8 rlkey[0x1]; 2445 u8 delay_drop_en[0x1]; 2446 u8 scatter_fcs[0x1]; 2447 u8 vlan_strip_disable[0x1]; 2448 u8 mem_rq_type[0x4]; 2449 u8 state[0x4]; 2450 u8 reserved_1[0x1]; 2451 u8 flush_in_error_en[0x1]; 2452 u8 reserved_2[0x12]; 2453 2454 u8 reserved_3[0x8]; 2455 u8 user_index[0x18]; 2456 2457 u8 reserved_4[0x8]; 2458 u8 cqn[0x18]; 2459 2460 u8 counter_set_id[0x8]; 2461 u8 reserved_5[0x18]; 2462 2463 u8 reserved_6[0x8]; 2464 u8 rmpn[0x18]; 2465 2466 u8 reserved_7[0xe0]; 2467 2468 struct mlx5_ifc_wq_bits wq; 2469 }; 2470 2471 enum { 2472 MLX5_RMPC_STATE_RDY = 0x1, 2473 MLX5_RMPC_STATE_ERR = 0x3, 2474 }; 2475 2476 struct mlx5_ifc_rmpc_bits { 2477 u8 reserved_0[0x8]; 2478 u8 state[0x4]; 2479 u8 reserved_1[0x14]; 2480 2481 u8 basic_cyclic_rcv_wqe[0x1]; 2482 u8 reserved_2[0x1f]; 2483 2484 u8 reserved_3[0x140]; 2485 2486 struct mlx5_ifc_wq_bits wq; 2487 }; 2488 2489 enum { 2490 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2491 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2492 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2493 }; 2494 2495 struct mlx5_ifc_nic_vport_context_bits { 2496 u8 reserved_0[0x5]; 2497 u8 min_wqe_inline_mode[0x3]; 2498 u8 reserved_1[0x15]; 2499 u8 disable_mc_local_lb[0x1]; 2500 u8 disable_uc_local_lb[0x1]; 2501 u8 roce_en[0x1]; 2502 2503 u8 arm_change_event[0x1]; 2504 u8 reserved_2[0x1a]; 2505 u8 event_on_mtu[0x1]; 2506 u8 event_on_promisc_change[0x1]; 2507 u8 event_on_vlan_change[0x1]; 2508 u8 event_on_mc_address_change[0x1]; 2509 u8 event_on_uc_address_change[0x1]; 2510 2511 u8 reserved_3[0xe0]; 2512 2513 u8 reserved_4[0x10]; 2514 u8 mtu[0x10]; 2515 2516 u8 system_image_guid[0x40]; 2517 2518 u8 port_guid[0x40]; 2519 2520 u8 node_guid[0x40]; 2521 2522 u8 reserved_5[0x140]; 2523 2524 u8 qkey_violation_counter[0x10]; 2525 u8 reserved_6[0x10]; 2526 2527 u8 reserved_7[0x420]; 2528 2529 u8 promisc_uc[0x1]; 2530 u8 promisc_mc[0x1]; 2531 u8 promisc_all[0x1]; 2532 u8 reserved_8[0x2]; 2533 u8 allowed_list_type[0x3]; 2534 u8 reserved_9[0xc]; 2535 u8 allowed_list_size[0xc]; 2536 2537 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2538 2539 u8 reserved_10[0x20]; 2540 2541 u8 current_uc_mac_address[0][0x40]; 2542 }; 2543 2544 enum { 2545 MLX5_ACCESS_MODE_PA = 0x0, 2546 MLX5_ACCESS_MODE_MTT = 0x1, 2547 MLX5_ACCESS_MODE_KLM = 0x2, 2548 }; 2549 2550 struct mlx5_ifc_mkc_bits { 2551 u8 reserved_at_0[0x1]; 2552 u8 free[0x1]; 2553 u8 reserved_at_2[0x1]; 2554 u8 access_mode_4_2[0x3]; 2555 u8 reserved_at_6[0x7]; 2556 u8 relaxed_ordering_write[0x1]; 2557 u8 reserved_at_e[0x1]; 2558 u8 small_fence_on_rdma_read_response[0x1]; 2559 u8 umr_en[0x1]; 2560 u8 a[0x1]; 2561 u8 rw[0x1]; 2562 u8 rr[0x1]; 2563 u8 lw[0x1]; 2564 u8 lr[0x1]; 2565 u8 access_mode[0x2]; 2566 u8 reserved_2[0x8]; 2567 2568 u8 qpn[0x18]; 2569 u8 mkey_7_0[0x8]; 2570 2571 u8 reserved_3[0x20]; 2572 2573 u8 length64[0x1]; 2574 u8 bsf_en[0x1]; 2575 u8 sync_umr[0x1]; 2576 u8 reserved_4[0x2]; 2577 u8 expected_sigerr_count[0x1]; 2578 u8 reserved_5[0x1]; 2579 u8 en_rinval[0x1]; 2580 u8 pd[0x18]; 2581 2582 u8 start_addr[0x40]; 2583 2584 u8 len[0x40]; 2585 2586 u8 bsf_octword_size[0x20]; 2587 2588 u8 reserved_6[0x80]; 2589 2590 u8 translations_octword_size[0x20]; 2591 2592 u8 reserved_7[0x1b]; 2593 u8 log_page_size[0x5]; 2594 2595 u8 reserved_8[0x20]; 2596 }; 2597 2598 struct mlx5_ifc_pkey_bits { 2599 u8 reserved_0[0x10]; 2600 u8 pkey[0x10]; 2601 }; 2602 2603 struct mlx5_ifc_array128_auto_bits { 2604 u8 array128_auto[16][0x8]; 2605 }; 2606 2607 enum { 2608 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2609 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2610 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2611 }; 2612 2613 enum { 2614 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2615 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2616 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2617 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2618 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2619 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2620 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2621 }; 2622 2623 enum { 2624 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2625 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2626 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2627 }; 2628 2629 enum { 2630 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2631 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2632 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2633 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2634 }; 2635 2636 enum { 2637 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2638 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2639 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2640 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2641 }; 2642 2643 struct mlx5_ifc_hca_vport_context_bits { 2644 u8 field_select[0x20]; 2645 2646 u8 reserved_0[0xe0]; 2647 2648 u8 sm_virt_aware[0x1]; 2649 u8 has_smi[0x1]; 2650 u8 has_raw[0x1]; 2651 u8 grh_required[0x1]; 2652 u8 reserved_1[0x1]; 2653 u8 min_wqe_inline_mode[0x3]; 2654 u8 reserved_2[0x8]; 2655 u8 port_physical_state[0x4]; 2656 u8 vport_state_policy[0x4]; 2657 u8 port_state[0x4]; 2658 u8 vport_state[0x4]; 2659 2660 u8 reserved_3[0x20]; 2661 2662 u8 system_image_guid[0x40]; 2663 2664 u8 port_guid[0x40]; 2665 2666 u8 node_guid[0x40]; 2667 2668 u8 cap_mask1[0x20]; 2669 2670 u8 cap_mask1_field_select[0x20]; 2671 2672 u8 cap_mask2[0x20]; 2673 2674 u8 cap_mask2_field_select[0x20]; 2675 2676 u8 reserved_4[0x80]; 2677 2678 u8 lid[0x10]; 2679 u8 reserved_5[0x4]; 2680 u8 init_type_reply[0x4]; 2681 u8 lmc[0x3]; 2682 u8 subnet_timeout[0x5]; 2683 2684 u8 sm_lid[0x10]; 2685 u8 sm_sl[0x4]; 2686 u8 reserved_6[0xc]; 2687 2688 u8 qkey_violation_counter[0x10]; 2689 u8 pkey_violation_counter[0x10]; 2690 2691 u8 reserved_7[0xca0]; 2692 }; 2693 2694 union mlx5_ifc_hca_cap_union_bits { 2695 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2696 struct mlx5_ifc_odp_cap_bits odp_cap; 2697 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2698 struct mlx5_ifc_roce_cap_bits roce_cap; 2699 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2700 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2701 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2702 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2703 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2704 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2705 struct mlx5_ifc_qos_cap_bits qos_cap; 2706 u8 reserved_0[0x8000]; 2707 }; 2708 2709 enum { 2710 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 2711 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 2712 }; 2713 2714 struct mlx5_ifc_flow_table_context_bits { 2715 u8 encap_en[0x1]; 2716 u8 decap_en[0x1]; 2717 u8 reserved_at_2[0x2]; 2718 u8 table_miss_action[0x4]; 2719 u8 level[0x8]; 2720 u8 reserved_at_10[0x8]; 2721 u8 log_size[0x8]; 2722 2723 u8 reserved_at_20[0x8]; 2724 u8 table_miss_id[0x18]; 2725 2726 u8 reserved_at_40[0x8]; 2727 u8 lag_master_next_table_id[0x18]; 2728 2729 u8 reserved_at_60[0xe0]; 2730 }; 2731 2732 struct mlx5_ifc_esw_vport_context_bits { 2733 u8 reserved_0[0x3]; 2734 u8 vport_svlan_strip[0x1]; 2735 u8 vport_cvlan_strip[0x1]; 2736 u8 vport_svlan_insert[0x1]; 2737 u8 vport_cvlan_insert[0x2]; 2738 u8 reserved_1[0x18]; 2739 2740 u8 reserved_2[0x20]; 2741 2742 u8 svlan_cfi[0x1]; 2743 u8 svlan_pcp[0x3]; 2744 u8 svlan_id[0xc]; 2745 u8 cvlan_cfi[0x1]; 2746 u8 cvlan_pcp[0x3]; 2747 u8 cvlan_id[0xc]; 2748 2749 u8 reserved_3[0x7a0]; 2750 }; 2751 2752 enum { 2753 MLX5_EQC_STATUS_OK = 0x0, 2754 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2755 }; 2756 2757 enum { 2758 MLX5_EQ_STATE_ARMED = 0x9, 2759 MLX5_EQ_STATE_FIRED = 0xa, 2760 }; 2761 2762 struct mlx5_ifc_eqc_bits { 2763 u8 status[0x4]; 2764 u8 reserved_0[0x9]; 2765 u8 ec[0x1]; 2766 u8 oi[0x1]; 2767 u8 reserved_1[0x5]; 2768 u8 st[0x4]; 2769 u8 reserved_2[0x8]; 2770 2771 u8 reserved_3[0x20]; 2772 2773 u8 reserved_4[0x14]; 2774 u8 page_offset[0x6]; 2775 u8 reserved_5[0x6]; 2776 2777 u8 reserved_6[0x3]; 2778 u8 log_eq_size[0x5]; 2779 u8 uar_page[0x18]; 2780 2781 u8 reserved_7[0x20]; 2782 2783 u8 reserved_8[0x18]; 2784 u8 intr[0x8]; 2785 2786 u8 reserved_9[0x3]; 2787 u8 log_page_size[0x5]; 2788 u8 reserved_10[0x18]; 2789 2790 u8 reserved_11[0x60]; 2791 2792 u8 reserved_12[0x8]; 2793 u8 consumer_counter[0x18]; 2794 2795 u8 reserved_13[0x8]; 2796 u8 producer_counter[0x18]; 2797 2798 u8 reserved_14[0x80]; 2799 }; 2800 2801 enum { 2802 MLX5_DCTC_STATE_ACTIVE = 0x0, 2803 MLX5_DCTC_STATE_DRAINING = 0x1, 2804 MLX5_DCTC_STATE_DRAINED = 0x2, 2805 }; 2806 2807 enum { 2808 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2809 MLX5_DCTC_CS_RES_NA = 0x1, 2810 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2811 }; 2812 2813 enum { 2814 MLX5_DCTC_MTU_256_BYTES = 0x1, 2815 MLX5_DCTC_MTU_512_BYTES = 0x2, 2816 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2817 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2818 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2819 }; 2820 2821 struct mlx5_ifc_dctc_bits { 2822 u8 reserved_0[0x4]; 2823 u8 state[0x4]; 2824 u8 reserved_1[0x18]; 2825 2826 u8 reserved_2[0x8]; 2827 u8 user_index[0x18]; 2828 2829 u8 reserved_3[0x8]; 2830 u8 cqn[0x18]; 2831 2832 u8 counter_set_id[0x8]; 2833 u8 atomic_mode[0x4]; 2834 u8 rre[0x1]; 2835 u8 rwe[0x1]; 2836 u8 rae[0x1]; 2837 u8 atomic_like_write_en[0x1]; 2838 u8 latency_sensitive[0x1]; 2839 u8 rlky[0x1]; 2840 u8 reserved_4[0xe]; 2841 2842 u8 reserved_5[0x8]; 2843 u8 cs_res[0x8]; 2844 u8 reserved_6[0x3]; 2845 u8 min_rnr_nak[0x5]; 2846 u8 reserved_7[0x8]; 2847 2848 u8 reserved_8[0x8]; 2849 u8 srqn[0x18]; 2850 2851 u8 reserved_9[0x8]; 2852 u8 pd[0x18]; 2853 2854 u8 tclass[0x8]; 2855 u8 reserved_10[0x4]; 2856 u8 flow_label[0x14]; 2857 2858 u8 dc_access_key[0x40]; 2859 2860 u8 reserved_11[0x5]; 2861 u8 mtu[0x3]; 2862 u8 port[0x8]; 2863 u8 pkey_index[0x10]; 2864 2865 u8 reserved_12[0x8]; 2866 u8 my_addr_index[0x8]; 2867 u8 reserved_13[0x8]; 2868 u8 hop_limit[0x8]; 2869 2870 u8 dc_access_key_violation_count[0x20]; 2871 2872 u8 reserved_14[0x14]; 2873 u8 dei_cfi[0x1]; 2874 u8 eth_prio[0x3]; 2875 u8 ecn[0x2]; 2876 u8 dscp[0x6]; 2877 2878 u8 reserved_15[0x40]; 2879 }; 2880 2881 enum { 2882 MLX5_CQC_STATUS_OK = 0x0, 2883 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2884 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2885 }; 2886 2887 enum { 2888 CQE_SIZE_64 = 0x0, 2889 CQE_SIZE_128 = 0x1, 2890 }; 2891 2892 enum { 2893 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2894 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2895 }; 2896 2897 enum { 2898 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 2899 MLX5_CQ_STATE_ARMED = 0x9, 2900 MLX5_CQ_STATE_FIRED = 0xa, 2901 }; 2902 2903 struct mlx5_ifc_cqc_bits { 2904 u8 status[0x4]; 2905 u8 reserved_0[0x4]; 2906 u8 cqe_sz[0x3]; 2907 u8 cc[0x1]; 2908 u8 reserved_1[0x1]; 2909 u8 scqe_break_moderation_en[0x1]; 2910 u8 oi[0x1]; 2911 u8 cq_period_mode[0x2]; 2912 u8 cqe_compression_en[0x1]; 2913 u8 mini_cqe_res_format[0x2]; 2914 u8 st[0x4]; 2915 u8 reserved_2[0x8]; 2916 2917 u8 reserved_3[0x20]; 2918 2919 u8 reserved_4[0x14]; 2920 u8 page_offset[0x6]; 2921 u8 reserved_5[0x6]; 2922 2923 u8 reserved_6[0x3]; 2924 u8 log_cq_size[0x5]; 2925 u8 uar_page[0x18]; 2926 2927 u8 reserved_7[0x4]; 2928 u8 cq_period[0xc]; 2929 u8 cq_max_count[0x10]; 2930 2931 u8 reserved_8[0x18]; 2932 u8 c_eqn[0x8]; 2933 2934 u8 reserved_9[0x3]; 2935 u8 log_page_size[0x5]; 2936 u8 reserved_10[0x18]; 2937 2938 u8 reserved_11[0x20]; 2939 2940 u8 reserved_12[0x8]; 2941 u8 last_notified_index[0x18]; 2942 2943 u8 reserved_13[0x8]; 2944 u8 last_solicit_index[0x18]; 2945 2946 u8 reserved_14[0x8]; 2947 u8 consumer_counter[0x18]; 2948 2949 u8 reserved_15[0x8]; 2950 u8 producer_counter[0x18]; 2951 2952 u8 reserved_16[0x40]; 2953 2954 u8 dbr_addr[0x40]; 2955 }; 2956 2957 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2958 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2959 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2960 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2961 u8 reserved_0[0x800]; 2962 }; 2963 2964 struct mlx5_ifc_query_adapter_param_block_bits { 2965 u8 reserved_0[0xc0]; 2966 2967 u8 reserved_1[0x8]; 2968 u8 ieee_vendor_id[0x18]; 2969 2970 u8 reserved_2[0x10]; 2971 u8 vsd_vendor_id[0x10]; 2972 2973 u8 vsd[208][0x8]; 2974 2975 u8 vsd_contd_psid[16][0x8]; 2976 }; 2977 2978 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2979 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2980 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2981 u8 reserved_0[0x20]; 2982 }; 2983 2984 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2985 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2986 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2987 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2988 u8 reserved_0[0x20]; 2989 }; 2990 2991 struct mlx5_ifc_bufferx_reg_bits { 2992 u8 reserved_0[0x6]; 2993 u8 lossy[0x1]; 2994 u8 epsb[0x1]; 2995 u8 reserved_1[0xc]; 2996 u8 size[0xc]; 2997 2998 u8 xoff_threshold[0x10]; 2999 u8 xon_threshold[0x10]; 3000 }; 3001 3002 struct mlx5_ifc_config_item_bits { 3003 u8 valid[0x2]; 3004 u8 reserved_0[0x2]; 3005 u8 header_type[0x2]; 3006 u8 reserved_1[0x2]; 3007 u8 default_location[0x1]; 3008 u8 reserved_2[0x7]; 3009 u8 version[0x4]; 3010 u8 reserved_3[0x3]; 3011 u8 length[0x9]; 3012 3013 u8 type[0x20]; 3014 3015 u8 reserved_4[0x10]; 3016 u8 crc16[0x10]; 3017 }; 3018 3019 struct mlx5_ifc_nodnic_port_config_reg_bits { 3020 struct mlx5_ifc_nodnic_event_word_bits event; 3021 3022 u8 network_en[0x1]; 3023 u8 dma_en[0x1]; 3024 u8 promisc_en[0x1]; 3025 u8 promisc_multicast_en[0x1]; 3026 u8 reserved_0[0x17]; 3027 u8 receive_filter_en[0x5]; 3028 3029 u8 reserved_1[0x10]; 3030 u8 mac_47_32[0x10]; 3031 3032 u8 mac_31_0[0x20]; 3033 3034 u8 receive_filters_mgid_mac[64][0x8]; 3035 3036 u8 gid[16][0x8]; 3037 3038 u8 reserved_2[0x10]; 3039 u8 lid[0x10]; 3040 3041 u8 reserved_3[0xc]; 3042 u8 sm_sl[0x4]; 3043 u8 sm_lid[0x10]; 3044 3045 u8 completion_address_63_32[0x20]; 3046 3047 u8 completion_address_31_12[0x14]; 3048 u8 reserved_4[0x6]; 3049 u8 log_cq_size[0x6]; 3050 3051 u8 working_buffer_address_63_32[0x20]; 3052 3053 u8 working_buffer_address_31_12[0x14]; 3054 u8 reserved_5[0xc]; 3055 3056 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 3057 3058 u8 pkey_index[0x10]; 3059 u8 pkey[0x10]; 3060 3061 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 3062 3063 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 3064 3065 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 3066 3067 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 3068 3069 u8 reserved_6[0x400]; 3070 }; 3071 3072 union mlx5_ifc_event_auto_bits { 3073 struct mlx5_ifc_comp_event_bits comp_event; 3074 struct mlx5_ifc_dct_events_bits dct_events; 3075 struct mlx5_ifc_qp_events_bits qp_events; 3076 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3077 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3078 struct mlx5_ifc_cq_error_bits cq_error; 3079 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3080 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3081 struct mlx5_ifc_gpio_event_bits gpio_event; 3082 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3083 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3084 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3085 struct mlx5_ifc_pages_req_event_bits pages_req_event; 3086 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 3087 u8 reserved_0[0xe0]; 3088 }; 3089 3090 struct mlx5_ifc_health_buffer_bits { 3091 u8 reserved_0[0x100]; 3092 3093 u8 assert_existptr[0x20]; 3094 3095 u8 assert_callra[0x20]; 3096 3097 u8 reserved_1[0x40]; 3098 3099 u8 fw_version[0x20]; 3100 3101 u8 hw_id[0x20]; 3102 3103 u8 reserved_2[0x20]; 3104 3105 u8 irisc_index[0x8]; 3106 u8 synd[0x8]; 3107 u8 ext_synd[0x10]; 3108 }; 3109 3110 struct mlx5_ifc_register_loopback_control_bits { 3111 u8 no_lb[0x1]; 3112 u8 reserved_0[0x7]; 3113 u8 port[0x8]; 3114 u8 reserved_1[0x10]; 3115 3116 u8 reserved_2[0x60]; 3117 }; 3118 3119 struct mlx5_ifc_lrh_bits { 3120 u8 vl[4]; 3121 u8 lver[4]; 3122 u8 sl[4]; 3123 u8 reserved2[2]; 3124 u8 lnh[2]; 3125 u8 dlid[16]; 3126 u8 reserved5[5]; 3127 u8 pkt_len[11]; 3128 u8 slid[16]; 3129 }; 3130 3131 struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3132 u8 reserved_0[0x40]; 3133 3134 u8 reserved_1[0x10]; 3135 u8 rol_mode[0x8]; 3136 u8 wol_mode[0x8]; 3137 }; 3138 3139 struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3140 u8 reserved_0[0x40]; 3141 3142 u8 rol_mode_valid[0x1]; 3143 u8 wol_mode_valid[0x1]; 3144 u8 reserved_1[0xe]; 3145 u8 rol_mode[0x8]; 3146 u8 wol_mode[0x8]; 3147 3148 u8 reserved_2[0x7a0]; 3149 }; 3150 3151 struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3152 u8 virtual_mac_en[0x1]; 3153 u8 mac_aux_v[0x1]; 3154 u8 reserved_0[0x1e]; 3155 3156 u8 reserved_1[0x40]; 3157 3158 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3159 3160 u8 reserved_2[0x760]; 3161 }; 3162 3163 struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3164 u8 virtual_mac_en[0x1]; 3165 u8 mac_aux_v[0x1]; 3166 u8 reserved_0[0x1e]; 3167 3168 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3169 3170 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3171 3172 u8 reserved_1[0x760]; 3173 }; 3174 3175 struct mlx5_ifc_icmd_query_fw_info_out_bits { 3176 struct mlx5_ifc_fw_version_bits fw_version; 3177 3178 u8 reserved_0[0x10]; 3179 u8 hash_signature[0x10]; 3180 3181 u8 psid[16][0x8]; 3182 3183 u8 reserved_1[0x6e0]; 3184 }; 3185 3186 struct mlx5_ifc_icmd_query_cap_in_bits { 3187 u8 reserved_0[0x10]; 3188 u8 capability_group[0x10]; 3189 }; 3190 3191 struct mlx5_ifc_icmd_query_cap_general_bits { 3192 u8 nv_access[0x1]; 3193 u8 fw_info_psid[0x1]; 3194 u8 reserved_0[0x1e]; 3195 3196 u8 reserved_1[0x16]; 3197 u8 rol_s[0x1]; 3198 u8 rol_g[0x1]; 3199 u8 reserved_2[0x1]; 3200 u8 wol_s[0x1]; 3201 u8 wol_g[0x1]; 3202 u8 wol_a[0x1]; 3203 u8 wol_b[0x1]; 3204 u8 wol_m[0x1]; 3205 u8 wol_u[0x1]; 3206 u8 wol_p[0x1]; 3207 }; 3208 3209 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3210 u8 status[0x8]; 3211 u8 reserved_0[0x18]; 3212 3213 u8 reserved_1[0x7e0]; 3214 }; 3215 3216 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3217 u8 status[0x8]; 3218 u8 reserved_0[0x18]; 3219 3220 u8 reserved_1[0x7e0]; 3221 }; 3222 3223 struct mlx5_ifc_icmd_ocbb_init_in_bits { 3224 u8 address_hi[0x20]; 3225 3226 u8 address_lo[0x20]; 3227 3228 u8 reserved_0[0x7c0]; 3229 }; 3230 3231 struct mlx5_ifc_icmd_init_ocsd_in_bits { 3232 u8 reserved_0[0x20]; 3233 3234 u8 address_hi[0x20]; 3235 3236 u8 address_lo[0x20]; 3237 3238 u8 reserved_1[0x7a0]; 3239 }; 3240 3241 struct mlx5_ifc_icmd_access_reg_out_bits { 3242 u8 reserved_0[0x11]; 3243 u8 status[0x7]; 3244 u8 reserved_1[0x8]; 3245 3246 u8 register_id[0x10]; 3247 u8 reserved_2[0x10]; 3248 3249 u8 reserved_3[0x40]; 3250 3251 u8 reserved_4[0x5]; 3252 u8 len[0xb]; 3253 u8 reserved_5[0x10]; 3254 3255 u8 register_data[0][0x20]; 3256 }; 3257 3258 enum { 3259 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3260 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3261 }; 3262 3263 struct mlx5_ifc_icmd_access_reg_in_bits { 3264 u8 constant_1[0x5]; 3265 u8 constant_2[0xb]; 3266 u8 reserved_0[0x10]; 3267 3268 u8 register_id[0x10]; 3269 u8 reserved_1[0x1]; 3270 u8 method[0x7]; 3271 u8 constant_3[0x8]; 3272 3273 u8 reserved_2[0x40]; 3274 3275 u8 constant_4[0x5]; 3276 u8 len[0xb]; 3277 u8 reserved_3[0x10]; 3278 3279 u8 register_data[0][0x20]; 3280 }; 3281 3282 enum { 3283 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3284 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3285 }; 3286 3287 struct mlx5_ifc_teardown_hca_out_bits { 3288 u8 status[0x8]; 3289 u8 reserved_0[0x18]; 3290 3291 u8 syndrome[0x20]; 3292 3293 u8 reserved_1[0x3f]; 3294 3295 u8 state[0x1]; 3296 }; 3297 3298 enum { 3299 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3300 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3301 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3302 }; 3303 3304 struct mlx5_ifc_teardown_hca_in_bits { 3305 u8 opcode[0x10]; 3306 u8 reserved_0[0x10]; 3307 3308 u8 reserved_1[0x10]; 3309 u8 op_mod[0x10]; 3310 3311 u8 reserved_2[0x10]; 3312 u8 profile[0x10]; 3313 3314 u8 reserved_3[0x20]; 3315 }; 3316 3317 struct mlx5_ifc_set_delay_drop_params_out_bits { 3318 u8 status[0x8]; 3319 u8 reserved_at_8[0x18]; 3320 3321 u8 syndrome[0x20]; 3322 3323 u8 reserved_at_40[0x40]; 3324 }; 3325 3326 struct mlx5_ifc_set_delay_drop_params_in_bits { 3327 u8 opcode[0x10]; 3328 u8 reserved_at_10[0x10]; 3329 3330 u8 reserved_at_20[0x10]; 3331 u8 op_mod[0x10]; 3332 3333 u8 reserved_at_40[0x20]; 3334 3335 u8 reserved_at_60[0x10]; 3336 u8 delay_drop_timeout[0x10]; 3337 }; 3338 3339 struct mlx5_ifc_query_delay_drop_params_out_bits { 3340 u8 status[0x8]; 3341 u8 reserved_at_8[0x18]; 3342 3343 u8 syndrome[0x20]; 3344 3345 u8 reserved_at_40[0x20]; 3346 3347 u8 reserved_at_60[0x10]; 3348 u8 delay_drop_timeout[0x10]; 3349 }; 3350 3351 struct mlx5_ifc_query_delay_drop_params_in_bits { 3352 u8 opcode[0x10]; 3353 u8 reserved_at_10[0x10]; 3354 3355 u8 reserved_at_20[0x10]; 3356 u8 op_mod[0x10]; 3357 3358 u8 reserved_at_40[0x40]; 3359 }; 3360 3361 struct mlx5_ifc_suspend_qp_out_bits { 3362 u8 status[0x8]; 3363 u8 reserved_0[0x18]; 3364 3365 u8 syndrome[0x20]; 3366 3367 u8 reserved_1[0x40]; 3368 }; 3369 3370 struct mlx5_ifc_suspend_qp_in_bits { 3371 u8 opcode[0x10]; 3372 u8 reserved_0[0x10]; 3373 3374 u8 reserved_1[0x10]; 3375 u8 op_mod[0x10]; 3376 3377 u8 reserved_2[0x8]; 3378 u8 qpn[0x18]; 3379 3380 u8 reserved_3[0x20]; 3381 }; 3382 3383 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3384 u8 status[0x8]; 3385 u8 reserved_0[0x18]; 3386 3387 u8 syndrome[0x20]; 3388 3389 u8 reserved_1[0x40]; 3390 }; 3391 3392 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3393 u8 opcode[0x10]; 3394 u8 reserved_0[0x10]; 3395 3396 u8 reserved_1[0x10]; 3397 u8 op_mod[0x10]; 3398 3399 u8 reserved_2[0x8]; 3400 u8 qpn[0x18]; 3401 3402 u8 reserved_3[0x20]; 3403 3404 u8 opt_param_mask[0x20]; 3405 3406 u8 reserved_4[0x20]; 3407 3408 struct mlx5_ifc_qpc_bits qpc; 3409 3410 u8 reserved_5[0x80]; 3411 }; 3412 3413 struct mlx5_ifc_sqd2rts_qp_out_bits { 3414 u8 status[0x8]; 3415 u8 reserved_0[0x18]; 3416 3417 u8 syndrome[0x20]; 3418 3419 u8 reserved_1[0x40]; 3420 }; 3421 3422 struct mlx5_ifc_sqd2rts_qp_in_bits { 3423 u8 opcode[0x10]; 3424 u8 reserved_0[0x10]; 3425 3426 u8 reserved_1[0x10]; 3427 u8 op_mod[0x10]; 3428 3429 u8 reserved_2[0x8]; 3430 u8 qpn[0x18]; 3431 3432 u8 reserved_3[0x20]; 3433 3434 u8 opt_param_mask[0x20]; 3435 3436 u8 reserved_4[0x20]; 3437 3438 struct mlx5_ifc_qpc_bits qpc; 3439 3440 u8 reserved_5[0x80]; 3441 }; 3442 3443 struct mlx5_ifc_set_wol_rol_out_bits { 3444 u8 status[0x8]; 3445 u8 reserved_0[0x18]; 3446 3447 u8 syndrome[0x20]; 3448 3449 u8 reserved_1[0x40]; 3450 }; 3451 3452 struct mlx5_ifc_set_wol_rol_in_bits { 3453 u8 opcode[0x10]; 3454 u8 reserved_0[0x10]; 3455 3456 u8 reserved_1[0x10]; 3457 u8 op_mod[0x10]; 3458 3459 u8 rol_mode_valid[0x1]; 3460 u8 wol_mode_valid[0x1]; 3461 u8 reserved_2[0xe]; 3462 u8 rol_mode[0x8]; 3463 u8 wol_mode[0x8]; 3464 3465 u8 reserved_3[0x20]; 3466 }; 3467 3468 struct mlx5_ifc_set_roce_address_out_bits { 3469 u8 status[0x8]; 3470 u8 reserved_0[0x18]; 3471 3472 u8 syndrome[0x20]; 3473 3474 u8 reserved_1[0x40]; 3475 }; 3476 3477 struct mlx5_ifc_set_roce_address_in_bits { 3478 u8 opcode[0x10]; 3479 u8 reserved_0[0x10]; 3480 3481 u8 reserved_1[0x10]; 3482 u8 op_mod[0x10]; 3483 3484 u8 roce_address_index[0x10]; 3485 u8 reserved_2[0x10]; 3486 3487 u8 reserved_3[0x20]; 3488 3489 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3490 }; 3491 3492 struct mlx5_ifc_set_rdb_out_bits { 3493 u8 status[0x8]; 3494 u8 reserved_0[0x18]; 3495 3496 u8 syndrome[0x20]; 3497 3498 u8 reserved_1[0x40]; 3499 }; 3500 3501 struct mlx5_ifc_set_rdb_in_bits { 3502 u8 opcode[0x10]; 3503 u8 reserved_0[0x10]; 3504 3505 u8 reserved_1[0x10]; 3506 u8 op_mod[0x10]; 3507 3508 u8 reserved_2[0x8]; 3509 u8 qpn[0x18]; 3510 3511 u8 reserved_3[0x18]; 3512 u8 rdb_list_size[0x8]; 3513 3514 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3515 }; 3516 3517 struct mlx5_ifc_set_mad_demux_out_bits { 3518 u8 status[0x8]; 3519 u8 reserved_0[0x18]; 3520 3521 u8 syndrome[0x20]; 3522 3523 u8 reserved_1[0x40]; 3524 }; 3525 3526 enum { 3527 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3528 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3529 }; 3530 3531 struct mlx5_ifc_set_mad_demux_in_bits { 3532 u8 opcode[0x10]; 3533 u8 reserved_0[0x10]; 3534 3535 u8 reserved_1[0x10]; 3536 u8 op_mod[0x10]; 3537 3538 u8 reserved_2[0x20]; 3539 3540 u8 reserved_3[0x6]; 3541 u8 demux_mode[0x2]; 3542 u8 reserved_4[0x18]; 3543 }; 3544 3545 struct mlx5_ifc_set_l2_table_entry_out_bits { 3546 u8 status[0x8]; 3547 u8 reserved_0[0x18]; 3548 3549 u8 syndrome[0x20]; 3550 3551 u8 reserved_1[0x40]; 3552 }; 3553 3554 struct mlx5_ifc_set_l2_table_entry_in_bits { 3555 u8 opcode[0x10]; 3556 u8 reserved_0[0x10]; 3557 3558 u8 reserved_1[0x10]; 3559 u8 op_mod[0x10]; 3560 3561 u8 reserved_2[0x60]; 3562 3563 u8 reserved_3[0x8]; 3564 u8 table_index[0x18]; 3565 3566 u8 reserved_4[0x20]; 3567 3568 u8 reserved_5[0x13]; 3569 u8 vlan_valid[0x1]; 3570 u8 vlan[0xc]; 3571 3572 struct mlx5_ifc_mac_address_layout_bits mac_address; 3573 3574 u8 reserved_6[0xc0]; 3575 }; 3576 3577 struct mlx5_ifc_set_issi_out_bits { 3578 u8 status[0x8]; 3579 u8 reserved_0[0x18]; 3580 3581 u8 syndrome[0x20]; 3582 3583 u8 reserved_1[0x40]; 3584 }; 3585 3586 struct mlx5_ifc_set_issi_in_bits { 3587 u8 opcode[0x10]; 3588 u8 reserved_0[0x10]; 3589 3590 u8 reserved_1[0x10]; 3591 u8 op_mod[0x10]; 3592 3593 u8 reserved_2[0x10]; 3594 u8 current_issi[0x10]; 3595 3596 u8 reserved_3[0x20]; 3597 }; 3598 3599 struct mlx5_ifc_set_hca_cap_out_bits { 3600 u8 status[0x8]; 3601 u8 reserved_0[0x18]; 3602 3603 u8 syndrome[0x20]; 3604 3605 u8 reserved_1[0x40]; 3606 }; 3607 3608 struct mlx5_ifc_set_hca_cap_in_bits { 3609 u8 opcode[0x10]; 3610 u8 reserved_0[0x10]; 3611 3612 u8 reserved_1[0x10]; 3613 u8 op_mod[0x10]; 3614 3615 u8 reserved_2[0x40]; 3616 3617 union mlx5_ifc_hca_cap_union_bits capability; 3618 }; 3619 3620 enum { 3621 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3622 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3623 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3624 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3625 }; 3626 3627 struct mlx5_ifc_set_flow_table_root_out_bits { 3628 u8 status[0x8]; 3629 u8 reserved_0[0x18]; 3630 3631 u8 syndrome[0x20]; 3632 3633 u8 reserved_1[0x40]; 3634 }; 3635 3636 struct mlx5_ifc_set_flow_table_root_in_bits { 3637 u8 opcode[0x10]; 3638 u8 reserved_0[0x10]; 3639 3640 u8 reserved_1[0x10]; 3641 u8 op_mod[0x10]; 3642 3643 u8 other_vport[0x1]; 3644 u8 reserved_2[0xf]; 3645 u8 vport_number[0x10]; 3646 3647 u8 reserved_3[0x20]; 3648 3649 u8 table_type[0x8]; 3650 u8 reserved_4[0x18]; 3651 3652 u8 reserved_5[0x8]; 3653 u8 table_id[0x18]; 3654 3655 u8 reserved_6[0x8]; 3656 u8 underlay_qpn[0x18]; 3657 3658 u8 reserved_7[0x120]; 3659 }; 3660 3661 struct mlx5_ifc_set_fte_out_bits { 3662 u8 status[0x8]; 3663 u8 reserved_0[0x18]; 3664 3665 u8 syndrome[0x20]; 3666 3667 u8 reserved_1[0x40]; 3668 }; 3669 3670 struct mlx5_ifc_set_fte_in_bits { 3671 u8 opcode[0x10]; 3672 u8 reserved_0[0x10]; 3673 3674 u8 reserved_1[0x10]; 3675 u8 op_mod[0x10]; 3676 3677 u8 other_vport[0x1]; 3678 u8 reserved_2[0xf]; 3679 u8 vport_number[0x10]; 3680 3681 u8 reserved_3[0x20]; 3682 3683 u8 table_type[0x8]; 3684 u8 reserved_4[0x18]; 3685 3686 u8 reserved_5[0x8]; 3687 u8 table_id[0x18]; 3688 3689 u8 reserved_6[0x18]; 3690 u8 modify_enable_mask[0x8]; 3691 3692 u8 reserved_7[0x20]; 3693 3694 u8 flow_index[0x20]; 3695 3696 u8 reserved_8[0xe0]; 3697 3698 struct mlx5_ifc_flow_context_bits flow_context; 3699 }; 3700 3701 struct mlx5_ifc_set_driver_version_out_bits { 3702 u8 status[0x8]; 3703 u8 reserved_0[0x18]; 3704 3705 u8 syndrome[0x20]; 3706 3707 u8 reserved_1[0x40]; 3708 }; 3709 3710 struct mlx5_ifc_set_driver_version_in_bits { 3711 u8 opcode[0x10]; 3712 u8 reserved_0[0x10]; 3713 3714 u8 reserved_1[0x10]; 3715 u8 op_mod[0x10]; 3716 3717 u8 reserved_2[0x40]; 3718 3719 u8 driver_version[64][0x8]; 3720 }; 3721 3722 struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3723 u8 status[0x8]; 3724 u8 reserved_0[0x18]; 3725 3726 u8 syndrome[0x20]; 3727 3728 u8 reserved_1[0x40]; 3729 }; 3730 3731 struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3732 u8 opcode[0x10]; 3733 u8 reserved_0[0x10]; 3734 3735 u8 reserved_1[0x10]; 3736 u8 op_mod[0x10]; 3737 3738 u8 enable[0x1]; 3739 u8 reserved_2[0x1f]; 3740 3741 u8 reserved_3[0x160]; 3742 3743 struct mlx5_ifc_cmd_pas_bits pas; 3744 }; 3745 3746 struct mlx5_ifc_set_burst_size_out_bits { 3747 u8 status[0x8]; 3748 u8 reserved_0[0x18]; 3749 3750 u8 syndrome[0x20]; 3751 3752 u8 reserved_1[0x40]; 3753 }; 3754 3755 struct mlx5_ifc_set_burst_size_in_bits { 3756 u8 opcode[0x10]; 3757 u8 reserved_0[0x10]; 3758 3759 u8 reserved_1[0x10]; 3760 u8 op_mod[0x10]; 3761 3762 u8 reserved_2[0x20]; 3763 3764 u8 reserved_3[0x9]; 3765 u8 device_burst_size[0x17]; 3766 }; 3767 3768 struct mlx5_ifc_rts2rts_qp_out_bits { 3769 u8 status[0x8]; 3770 u8 reserved_0[0x18]; 3771 3772 u8 syndrome[0x20]; 3773 3774 u8 reserved_1[0x40]; 3775 }; 3776 3777 struct mlx5_ifc_rts2rts_qp_in_bits { 3778 u8 opcode[0x10]; 3779 u8 reserved_0[0x10]; 3780 3781 u8 reserved_1[0x10]; 3782 u8 op_mod[0x10]; 3783 3784 u8 reserved_2[0x8]; 3785 u8 qpn[0x18]; 3786 3787 u8 reserved_3[0x20]; 3788 3789 u8 opt_param_mask[0x20]; 3790 3791 u8 reserved_4[0x20]; 3792 3793 struct mlx5_ifc_qpc_bits qpc; 3794 3795 u8 reserved_5[0x80]; 3796 }; 3797 3798 struct mlx5_ifc_rtr2rts_qp_out_bits { 3799 u8 status[0x8]; 3800 u8 reserved_0[0x18]; 3801 3802 u8 syndrome[0x20]; 3803 3804 u8 reserved_1[0x40]; 3805 }; 3806 3807 struct mlx5_ifc_rtr2rts_qp_in_bits { 3808 u8 opcode[0x10]; 3809 u8 reserved_0[0x10]; 3810 3811 u8 reserved_1[0x10]; 3812 u8 op_mod[0x10]; 3813 3814 u8 reserved_2[0x8]; 3815 u8 qpn[0x18]; 3816 3817 u8 reserved_3[0x20]; 3818 3819 u8 opt_param_mask[0x20]; 3820 3821 u8 reserved_4[0x20]; 3822 3823 struct mlx5_ifc_qpc_bits qpc; 3824 3825 u8 reserved_5[0x80]; 3826 }; 3827 3828 struct mlx5_ifc_rst2init_qp_out_bits { 3829 u8 status[0x8]; 3830 u8 reserved_0[0x18]; 3831 3832 u8 syndrome[0x20]; 3833 3834 u8 reserved_1[0x40]; 3835 }; 3836 3837 struct mlx5_ifc_rst2init_qp_in_bits { 3838 u8 opcode[0x10]; 3839 u8 reserved_0[0x10]; 3840 3841 u8 reserved_1[0x10]; 3842 u8 op_mod[0x10]; 3843 3844 u8 reserved_2[0x8]; 3845 u8 qpn[0x18]; 3846 3847 u8 reserved_3[0x20]; 3848 3849 u8 opt_param_mask[0x20]; 3850 3851 u8 reserved_4[0x20]; 3852 3853 struct mlx5_ifc_qpc_bits qpc; 3854 3855 u8 reserved_5[0x80]; 3856 }; 3857 3858 struct mlx5_ifc_resume_qp_out_bits { 3859 u8 status[0x8]; 3860 u8 reserved_0[0x18]; 3861 3862 u8 syndrome[0x20]; 3863 3864 u8 reserved_1[0x40]; 3865 }; 3866 3867 struct mlx5_ifc_resume_qp_in_bits { 3868 u8 opcode[0x10]; 3869 u8 reserved_0[0x10]; 3870 3871 u8 reserved_1[0x10]; 3872 u8 op_mod[0x10]; 3873 3874 u8 reserved_2[0x8]; 3875 u8 qpn[0x18]; 3876 3877 u8 reserved_3[0x20]; 3878 }; 3879 3880 struct mlx5_ifc_query_xrc_srq_out_bits { 3881 u8 status[0x8]; 3882 u8 reserved_0[0x18]; 3883 3884 u8 syndrome[0x20]; 3885 3886 u8 reserved_1[0x40]; 3887 3888 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3889 3890 u8 reserved_2[0x600]; 3891 3892 u8 pas[0][0x40]; 3893 }; 3894 3895 struct mlx5_ifc_query_xrc_srq_in_bits { 3896 u8 opcode[0x10]; 3897 u8 reserved_0[0x10]; 3898 3899 u8 reserved_1[0x10]; 3900 u8 op_mod[0x10]; 3901 3902 u8 reserved_2[0x8]; 3903 u8 xrc_srqn[0x18]; 3904 3905 u8 reserved_3[0x20]; 3906 }; 3907 3908 struct mlx5_ifc_query_wol_rol_out_bits { 3909 u8 status[0x8]; 3910 u8 reserved_0[0x18]; 3911 3912 u8 syndrome[0x20]; 3913 3914 u8 reserved_1[0x10]; 3915 u8 rol_mode[0x8]; 3916 u8 wol_mode[0x8]; 3917 3918 u8 reserved_2[0x20]; 3919 }; 3920 3921 struct mlx5_ifc_query_wol_rol_in_bits { 3922 u8 opcode[0x10]; 3923 u8 reserved_0[0x10]; 3924 3925 u8 reserved_1[0x10]; 3926 u8 op_mod[0x10]; 3927 3928 u8 reserved_2[0x40]; 3929 }; 3930 3931 enum { 3932 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3933 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3934 }; 3935 3936 struct mlx5_ifc_query_vport_state_out_bits { 3937 u8 status[0x8]; 3938 u8 reserved_0[0x18]; 3939 3940 u8 syndrome[0x20]; 3941 3942 u8 reserved_1[0x20]; 3943 3944 u8 reserved_2[0x18]; 3945 u8 admin_state[0x4]; 3946 u8 state[0x4]; 3947 }; 3948 3949 enum { 3950 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3951 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3952 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 3953 }; 3954 3955 struct mlx5_ifc_query_vport_state_in_bits { 3956 u8 opcode[0x10]; 3957 u8 reserved_0[0x10]; 3958 3959 u8 reserved_1[0x10]; 3960 u8 op_mod[0x10]; 3961 3962 u8 other_vport[0x1]; 3963 u8 reserved_2[0xf]; 3964 u8 vport_number[0x10]; 3965 3966 u8 reserved_3[0x20]; 3967 }; 3968 3969 struct mlx5_ifc_query_vport_counter_out_bits { 3970 u8 status[0x8]; 3971 u8 reserved_0[0x18]; 3972 3973 u8 syndrome[0x20]; 3974 3975 u8 reserved_1[0x40]; 3976 3977 struct mlx5_ifc_traffic_counter_bits received_errors; 3978 3979 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3980 3981 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3982 3983 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3984 3985 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3986 3987 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3988 3989 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3990 3991 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3992 3993 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3994 3995 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3996 3997 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3998 3999 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4000 4001 u8 reserved_2[0xa00]; 4002 }; 4003 4004 enum { 4005 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4006 }; 4007 4008 struct mlx5_ifc_query_vport_counter_in_bits { 4009 u8 opcode[0x10]; 4010 u8 reserved_0[0x10]; 4011 4012 u8 reserved_1[0x10]; 4013 u8 op_mod[0x10]; 4014 4015 u8 other_vport[0x1]; 4016 u8 reserved_2[0xb]; 4017 u8 port_num[0x4]; 4018 u8 vport_number[0x10]; 4019 4020 u8 reserved_3[0x60]; 4021 4022 u8 clear[0x1]; 4023 u8 reserved_4[0x1f]; 4024 4025 u8 reserved_5[0x20]; 4026 }; 4027 4028 struct mlx5_ifc_query_tis_out_bits { 4029 u8 status[0x8]; 4030 u8 reserved_0[0x18]; 4031 4032 u8 syndrome[0x20]; 4033 4034 u8 reserved_1[0x40]; 4035 4036 struct mlx5_ifc_tisc_bits tis_context; 4037 }; 4038 4039 struct mlx5_ifc_query_tis_in_bits { 4040 u8 opcode[0x10]; 4041 u8 reserved_0[0x10]; 4042 4043 u8 reserved_1[0x10]; 4044 u8 op_mod[0x10]; 4045 4046 u8 reserved_2[0x8]; 4047 u8 tisn[0x18]; 4048 4049 u8 reserved_3[0x20]; 4050 }; 4051 4052 struct mlx5_ifc_query_tir_out_bits { 4053 u8 status[0x8]; 4054 u8 reserved_0[0x18]; 4055 4056 u8 syndrome[0x20]; 4057 4058 u8 reserved_1[0xc0]; 4059 4060 struct mlx5_ifc_tirc_bits tir_context; 4061 }; 4062 4063 struct mlx5_ifc_query_tir_in_bits { 4064 u8 opcode[0x10]; 4065 u8 reserved_0[0x10]; 4066 4067 u8 reserved_1[0x10]; 4068 u8 op_mod[0x10]; 4069 4070 u8 reserved_2[0x8]; 4071 u8 tirn[0x18]; 4072 4073 u8 reserved_3[0x20]; 4074 }; 4075 4076 struct mlx5_ifc_query_srq_out_bits { 4077 u8 status[0x8]; 4078 u8 reserved_0[0x18]; 4079 4080 u8 syndrome[0x20]; 4081 4082 u8 reserved_1[0x40]; 4083 4084 struct mlx5_ifc_srqc_bits srq_context_entry; 4085 4086 u8 reserved_2[0x600]; 4087 4088 u8 pas[0][0x40]; 4089 }; 4090 4091 struct mlx5_ifc_query_srq_in_bits { 4092 u8 opcode[0x10]; 4093 u8 reserved_0[0x10]; 4094 4095 u8 reserved_1[0x10]; 4096 u8 op_mod[0x10]; 4097 4098 u8 reserved_2[0x8]; 4099 u8 srqn[0x18]; 4100 4101 u8 reserved_3[0x20]; 4102 }; 4103 4104 struct mlx5_ifc_query_sq_out_bits { 4105 u8 status[0x8]; 4106 u8 reserved_0[0x18]; 4107 4108 u8 syndrome[0x20]; 4109 4110 u8 reserved_1[0xc0]; 4111 4112 struct mlx5_ifc_sqc_bits sq_context; 4113 }; 4114 4115 struct mlx5_ifc_query_sq_in_bits { 4116 u8 opcode[0x10]; 4117 u8 reserved_0[0x10]; 4118 4119 u8 reserved_1[0x10]; 4120 u8 op_mod[0x10]; 4121 4122 u8 reserved_2[0x8]; 4123 u8 sqn[0x18]; 4124 4125 u8 reserved_3[0x20]; 4126 }; 4127 4128 struct mlx5_ifc_query_special_contexts_out_bits { 4129 u8 status[0x8]; 4130 u8 reserved_0[0x18]; 4131 4132 u8 syndrome[0x20]; 4133 4134 u8 dump_fill_mkey[0x20]; 4135 4136 u8 resd_lkey[0x20]; 4137 }; 4138 4139 struct mlx5_ifc_query_special_contexts_in_bits { 4140 u8 opcode[0x10]; 4141 u8 reserved_0[0x10]; 4142 4143 u8 reserved_1[0x10]; 4144 u8 op_mod[0x10]; 4145 4146 u8 reserved_2[0x40]; 4147 }; 4148 4149 struct mlx5_ifc_query_scheduling_element_out_bits { 4150 u8 status[0x8]; 4151 u8 reserved_at_8[0x18]; 4152 4153 u8 syndrome[0x20]; 4154 4155 u8 reserved_at_40[0xc0]; 4156 4157 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4158 4159 u8 reserved_at_300[0x100]; 4160 }; 4161 4162 enum { 4163 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4164 }; 4165 4166 struct mlx5_ifc_query_scheduling_element_in_bits { 4167 u8 opcode[0x10]; 4168 u8 reserved_at_10[0x10]; 4169 4170 u8 reserved_at_20[0x10]; 4171 u8 op_mod[0x10]; 4172 4173 u8 scheduling_hierarchy[0x8]; 4174 u8 reserved_at_48[0x18]; 4175 4176 u8 scheduling_element_id[0x20]; 4177 4178 u8 reserved_at_80[0x180]; 4179 }; 4180 4181 struct mlx5_ifc_query_rqt_out_bits { 4182 u8 status[0x8]; 4183 u8 reserved_0[0x18]; 4184 4185 u8 syndrome[0x20]; 4186 4187 u8 reserved_1[0xc0]; 4188 4189 struct mlx5_ifc_rqtc_bits rqt_context; 4190 }; 4191 4192 struct mlx5_ifc_query_rqt_in_bits { 4193 u8 opcode[0x10]; 4194 u8 reserved_0[0x10]; 4195 4196 u8 reserved_1[0x10]; 4197 u8 op_mod[0x10]; 4198 4199 u8 reserved_2[0x8]; 4200 u8 rqtn[0x18]; 4201 4202 u8 reserved_3[0x20]; 4203 }; 4204 4205 struct mlx5_ifc_query_rq_out_bits { 4206 u8 status[0x8]; 4207 u8 reserved_0[0x18]; 4208 4209 u8 syndrome[0x20]; 4210 4211 u8 reserved_1[0xc0]; 4212 4213 struct mlx5_ifc_rqc_bits rq_context; 4214 }; 4215 4216 struct mlx5_ifc_query_rq_in_bits { 4217 u8 opcode[0x10]; 4218 u8 reserved_0[0x10]; 4219 4220 u8 reserved_1[0x10]; 4221 u8 op_mod[0x10]; 4222 4223 u8 reserved_2[0x8]; 4224 u8 rqn[0x18]; 4225 4226 u8 reserved_3[0x20]; 4227 }; 4228 4229 struct mlx5_ifc_query_roce_address_out_bits { 4230 u8 status[0x8]; 4231 u8 reserved_0[0x18]; 4232 4233 u8 syndrome[0x20]; 4234 4235 u8 reserved_1[0x40]; 4236 4237 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4238 }; 4239 4240 struct mlx5_ifc_query_roce_address_in_bits { 4241 u8 opcode[0x10]; 4242 u8 reserved_0[0x10]; 4243 4244 u8 reserved_1[0x10]; 4245 u8 op_mod[0x10]; 4246 4247 u8 roce_address_index[0x10]; 4248 u8 reserved_2[0x10]; 4249 4250 u8 reserved_3[0x20]; 4251 }; 4252 4253 struct mlx5_ifc_query_rmp_out_bits { 4254 u8 status[0x8]; 4255 u8 reserved_0[0x18]; 4256 4257 u8 syndrome[0x20]; 4258 4259 u8 reserved_1[0xc0]; 4260 4261 struct mlx5_ifc_rmpc_bits rmp_context; 4262 }; 4263 4264 struct mlx5_ifc_query_rmp_in_bits { 4265 u8 opcode[0x10]; 4266 u8 reserved_0[0x10]; 4267 4268 u8 reserved_1[0x10]; 4269 u8 op_mod[0x10]; 4270 4271 u8 reserved_2[0x8]; 4272 u8 rmpn[0x18]; 4273 4274 u8 reserved_3[0x20]; 4275 }; 4276 4277 struct mlx5_ifc_query_rdb_out_bits { 4278 u8 status[0x8]; 4279 u8 reserved_0[0x18]; 4280 4281 u8 syndrome[0x20]; 4282 4283 u8 reserved_1[0x20]; 4284 4285 u8 reserved_2[0x18]; 4286 u8 rdb_list_size[0x8]; 4287 4288 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4289 }; 4290 4291 struct mlx5_ifc_query_rdb_in_bits { 4292 u8 opcode[0x10]; 4293 u8 reserved_0[0x10]; 4294 4295 u8 reserved_1[0x10]; 4296 u8 op_mod[0x10]; 4297 4298 u8 reserved_2[0x8]; 4299 u8 qpn[0x18]; 4300 4301 u8 reserved_3[0x20]; 4302 }; 4303 4304 struct mlx5_ifc_query_qp_out_bits { 4305 u8 status[0x8]; 4306 u8 reserved_0[0x18]; 4307 4308 u8 syndrome[0x20]; 4309 4310 u8 reserved_1[0x40]; 4311 4312 u8 opt_param_mask[0x20]; 4313 4314 u8 reserved_2[0x20]; 4315 4316 struct mlx5_ifc_qpc_bits qpc; 4317 4318 u8 reserved_3[0x80]; 4319 4320 u8 pas[0][0x40]; 4321 }; 4322 4323 struct mlx5_ifc_query_qp_in_bits { 4324 u8 opcode[0x10]; 4325 u8 reserved_0[0x10]; 4326 4327 u8 reserved_1[0x10]; 4328 u8 op_mod[0x10]; 4329 4330 u8 reserved_2[0x8]; 4331 u8 qpn[0x18]; 4332 4333 u8 reserved_3[0x20]; 4334 }; 4335 4336 struct mlx5_ifc_query_q_counter_out_bits { 4337 u8 status[0x8]; 4338 u8 reserved_0[0x18]; 4339 4340 u8 syndrome[0x20]; 4341 4342 u8 reserved_1[0x40]; 4343 4344 u8 rx_write_requests[0x20]; 4345 4346 u8 reserved_2[0x20]; 4347 4348 u8 rx_read_requests[0x20]; 4349 4350 u8 reserved_3[0x20]; 4351 4352 u8 rx_atomic_requests[0x20]; 4353 4354 u8 reserved_4[0x20]; 4355 4356 u8 rx_dct_connect[0x20]; 4357 4358 u8 reserved_5[0x20]; 4359 4360 u8 out_of_buffer[0x20]; 4361 4362 u8 reserved_7[0x20]; 4363 4364 u8 out_of_sequence[0x20]; 4365 4366 u8 reserved_8[0x20]; 4367 4368 u8 duplicate_request[0x20]; 4369 4370 u8 reserved_9[0x20]; 4371 4372 u8 rnr_nak_retry_err[0x20]; 4373 4374 u8 reserved_10[0x20]; 4375 4376 u8 packet_seq_err[0x20]; 4377 4378 u8 reserved_11[0x20]; 4379 4380 u8 implied_nak_seq_err[0x20]; 4381 4382 u8 reserved_12[0x20]; 4383 4384 u8 local_ack_timeout_err[0x20]; 4385 4386 u8 reserved_13[0x20]; 4387 4388 u8 resp_rnr_nak[0x20]; 4389 4390 u8 reserved_14[0x20]; 4391 4392 u8 req_rnr_retries_exceeded[0x20]; 4393 4394 u8 reserved_15[0x460]; 4395 }; 4396 4397 struct mlx5_ifc_query_q_counter_in_bits { 4398 u8 opcode[0x10]; 4399 u8 reserved_0[0x10]; 4400 4401 u8 reserved_1[0x10]; 4402 u8 op_mod[0x10]; 4403 4404 u8 reserved_2[0x80]; 4405 4406 u8 clear[0x1]; 4407 u8 reserved_3[0x1f]; 4408 4409 u8 reserved_4[0x18]; 4410 u8 counter_set_id[0x8]; 4411 }; 4412 4413 struct mlx5_ifc_query_pages_out_bits { 4414 u8 status[0x8]; 4415 u8 reserved_0[0x18]; 4416 4417 u8 syndrome[0x20]; 4418 4419 u8 reserved_1[0x10]; 4420 u8 function_id[0x10]; 4421 4422 u8 num_pages[0x20]; 4423 }; 4424 4425 enum { 4426 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4427 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4428 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4429 }; 4430 4431 struct mlx5_ifc_query_pages_in_bits { 4432 u8 opcode[0x10]; 4433 u8 reserved_0[0x10]; 4434 4435 u8 reserved_1[0x10]; 4436 u8 op_mod[0x10]; 4437 4438 u8 reserved_2[0x10]; 4439 u8 function_id[0x10]; 4440 4441 u8 reserved_3[0x20]; 4442 }; 4443 4444 struct mlx5_ifc_query_nic_vport_context_out_bits { 4445 u8 status[0x8]; 4446 u8 reserved_0[0x18]; 4447 4448 u8 syndrome[0x20]; 4449 4450 u8 reserved_1[0x40]; 4451 4452 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4453 }; 4454 4455 struct mlx5_ifc_query_nic_vport_context_in_bits { 4456 u8 opcode[0x10]; 4457 u8 reserved_0[0x10]; 4458 4459 u8 reserved_1[0x10]; 4460 u8 op_mod[0x10]; 4461 4462 u8 other_vport[0x1]; 4463 u8 reserved_2[0xf]; 4464 u8 vport_number[0x10]; 4465 4466 u8 reserved_3[0x5]; 4467 u8 allowed_list_type[0x3]; 4468 u8 reserved_4[0x18]; 4469 }; 4470 4471 struct mlx5_ifc_query_mkey_out_bits { 4472 u8 status[0x8]; 4473 u8 reserved_0[0x18]; 4474 4475 u8 syndrome[0x20]; 4476 4477 u8 reserved_1[0x40]; 4478 4479 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4480 4481 u8 reserved_2[0x600]; 4482 4483 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4484 4485 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4486 }; 4487 4488 struct mlx5_ifc_query_mkey_in_bits { 4489 u8 opcode[0x10]; 4490 u8 reserved_0[0x10]; 4491 4492 u8 reserved_1[0x10]; 4493 u8 op_mod[0x10]; 4494 4495 u8 reserved_2[0x8]; 4496 u8 mkey_index[0x18]; 4497 4498 u8 pg_access[0x1]; 4499 u8 reserved_3[0x1f]; 4500 }; 4501 4502 struct mlx5_ifc_query_mad_demux_out_bits { 4503 u8 status[0x8]; 4504 u8 reserved_0[0x18]; 4505 4506 u8 syndrome[0x20]; 4507 4508 u8 reserved_1[0x40]; 4509 4510 u8 mad_dumux_parameters_block[0x20]; 4511 }; 4512 4513 struct mlx5_ifc_query_mad_demux_in_bits { 4514 u8 opcode[0x10]; 4515 u8 reserved_0[0x10]; 4516 4517 u8 reserved_1[0x10]; 4518 u8 op_mod[0x10]; 4519 4520 u8 reserved_2[0x40]; 4521 }; 4522 4523 struct mlx5_ifc_query_l2_table_entry_out_bits { 4524 u8 status[0x8]; 4525 u8 reserved_0[0x18]; 4526 4527 u8 syndrome[0x20]; 4528 4529 u8 reserved_1[0xa0]; 4530 4531 u8 reserved_2[0x13]; 4532 u8 vlan_valid[0x1]; 4533 u8 vlan[0xc]; 4534 4535 struct mlx5_ifc_mac_address_layout_bits mac_address; 4536 4537 u8 reserved_3[0xc0]; 4538 }; 4539 4540 struct mlx5_ifc_query_l2_table_entry_in_bits { 4541 u8 opcode[0x10]; 4542 u8 reserved_0[0x10]; 4543 4544 u8 reserved_1[0x10]; 4545 u8 op_mod[0x10]; 4546 4547 u8 reserved_2[0x60]; 4548 4549 u8 reserved_3[0x8]; 4550 u8 table_index[0x18]; 4551 4552 u8 reserved_4[0x140]; 4553 }; 4554 4555 struct mlx5_ifc_query_issi_out_bits { 4556 u8 status[0x8]; 4557 u8 reserved_0[0x18]; 4558 4559 u8 syndrome[0x20]; 4560 4561 u8 reserved_1[0x10]; 4562 u8 current_issi[0x10]; 4563 4564 u8 reserved_2[0xa0]; 4565 4566 u8 supported_issi_reserved[76][0x8]; 4567 u8 supported_issi_dw0[0x20]; 4568 }; 4569 4570 struct mlx5_ifc_query_issi_in_bits { 4571 u8 opcode[0x10]; 4572 u8 reserved_0[0x10]; 4573 4574 u8 reserved_1[0x10]; 4575 u8 op_mod[0x10]; 4576 4577 u8 reserved_2[0x40]; 4578 }; 4579 4580 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4581 u8 status[0x8]; 4582 u8 reserved_0[0x18]; 4583 4584 u8 syndrome[0x20]; 4585 4586 u8 reserved_1[0x40]; 4587 4588 struct mlx5_ifc_pkey_bits pkey[0]; 4589 }; 4590 4591 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4592 u8 opcode[0x10]; 4593 u8 reserved_0[0x10]; 4594 4595 u8 reserved_1[0x10]; 4596 u8 op_mod[0x10]; 4597 4598 u8 other_vport[0x1]; 4599 u8 reserved_2[0xb]; 4600 u8 port_num[0x4]; 4601 u8 vport_number[0x10]; 4602 4603 u8 reserved_3[0x10]; 4604 u8 pkey_index[0x10]; 4605 }; 4606 4607 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4608 u8 status[0x8]; 4609 u8 reserved_0[0x18]; 4610 4611 u8 syndrome[0x20]; 4612 4613 u8 reserved_1[0x20]; 4614 4615 u8 gids_num[0x10]; 4616 u8 reserved_2[0x10]; 4617 4618 struct mlx5_ifc_array128_auto_bits gid[0]; 4619 }; 4620 4621 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4622 u8 opcode[0x10]; 4623 u8 reserved_0[0x10]; 4624 4625 u8 reserved_1[0x10]; 4626 u8 op_mod[0x10]; 4627 4628 u8 other_vport[0x1]; 4629 u8 reserved_2[0xb]; 4630 u8 port_num[0x4]; 4631 u8 vport_number[0x10]; 4632 4633 u8 reserved_3[0x10]; 4634 u8 gid_index[0x10]; 4635 }; 4636 4637 struct mlx5_ifc_query_hca_vport_context_out_bits { 4638 u8 status[0x8]; 4639 u8 reserved_0[0x18]; 4640 4641 u8 syndrome[0x20]; 4642 4643 u8 reserved_1[0x40]; 4644 4645 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4646 }; 4647 4648 struct mlx5_ifc_query_hca_vport_context_in_bits { 4649 u8 opcode[0x10]; 4650 u8 reserved_0[0x10]; 4651 4652 u8 reserved_1[0x10]; 4653 u8 op_mod[0x10]; 4654 4655 u8 other_vport[0x1]; 4656 u8 reserved_2[0xb]; 4657 u8 port_num[0x4]; 4658 u8 vport_number[0x10]; 4659 4660 u8 reserved_3[0x20]; 4661 }; 4662 4663 struct mlx5_ifc_query_hca_cap_out_bits { 4664 u8 status[0x8]; 4665 u8 reserved_0[0x18]; 4666 4667 u8 syndrome[0x20]; 4668 4669 u8 reserved_1[0x40]; 4670 4671 union mlx5_ifc_hca_cap_union_bits capability; 4672 }; 4673 4674 struct mlx5_ifc_query_hca_cap_in_bits { 4675 u8 opcode[0x10]; 4676 u8 reserved_0[0x10]; 4677 4678 u8 reserved_1[0x10]; 4679 u8 op_mod[0x10]; 4680 4681 u8 reserved_2[0x40]; 4682 }; 4683 4684 struct mlx5_ifc_query_flow_table_out_bits { 4685 u8 status[0x8]; 4686 u8 reserved_at_8[0x18]; 4687 4688 u8 syndrome[0x20]; 4689 4690 u8 reserved_at_40[0x80]; 4691 4692 struct mlx5_ifc_flow_table_context_bits flow_table_context; 4693 }; 4694 4695 struct mlx5_ifc_query_flow_table_in_bits { 4696 u8 opcode[0x10]; 4697 u8 reserved_0[0x10]; 4698 4699 u8 reserved_1[0x10]; 4700 u8 op_mod[0x10]; 4701 4702 u8 other_vport[0x1]; 4703 u8 reserved_2[0xf]; 4704 u8 vport_number[0x10]; 4705 4706 u8 reserved_3[0x20]; 4707 4708 u8 table_type[0x8]; 4709 u8 reserved_4[0x18]; 4710 4711 u8 reserved_5[0x8]; 4712 u8 table_id[0x18]; 4713 4714 u8 reserved_6[0x140]; 4715 }; 4716 4717 struct mlx5_ifc_query_fte_out_bits { 4718 u8 status[0x8]; 4719 u8 reserved_0[0x18]; 4720 4721 u8 syndrome[0x20]; 4722 4723 u8 reserved_1[0x1c0]; 4724 4725 struct mlx5_ifc_flow_context_bits flow_context; 4726 }; 4727 4728 struct mlx5_ifc_query_fte_in_bits { 4729 u8 opcode[0x10]; 4730 u8 reserved_0[0x10]; 4731 4732 u8 reserved_1[0x10]; 4733 u8 op_mod[0x10]; 4734 4735 u8 other_vport[0x1]; 4736 u8 reserved_2[0xf]; 4737 u8 vport_number[0x10]; 4738 4739 u8 reserved_3[0x20]; 4740 4741 u8 table_type[0x8]; 4742 u8 reserved_4[0x18]; 4743 4744 u8 reserved_5[0x8]; 4745 u8 table_id[0x18]; 4746 4747 u8 reserved_6[0x40]; 4748 4749 u8 flow_index[0x20]; 4750 4751 u8 reserved_7[0xe0]; 4752 }; 4753 4754 enum { 4755 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4756 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4757 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4758 }; 4759 4760 struct mlx5_ifc_query_flow_group_out_bits { 4761 u8 status[0x8]; 4762 u8 reserved_0[0x18]; 4763 4764 u8 syndrome[0x20]; 4765 4766 u8 reserved_1[0xa0]; 4767 4768 u8 start_flow_index[0x20]; 4769 4770 u8 reserved_2[0x20]; 4771 4772 u8 end_flow_index[0x20]; 4773 4774 u8 reserved_3[0xa0]; 4775 4776 u8 reserved_4[0x18]; 4777 u8 match_criteria_enable[0x8]; 4778 4779 struct mlx5_ifc_fte_match_param_bits match_criteria; 4780 4781 u8 reserved_5[0xe00]; 4782 }; 4783 4784 struct mlx5_ifc_query_flow_group_in_bits { 4785 u8 opcode[0x10]; 4786 u8 reserved_0[0x10]; 4787 4788 u8 reserved_1[0x10]; 4789 u8 op_mod[0x10]; 4790 4791 u8 other_vport[0x1]; 4792 u8 reserved_2[0xf]; 4793 u8 vport_number[0x10]; 4794 4795 u8 reserved_3[0x20]; 4796 4797 u8 table_type[0x8]; 4798 u8 reserved_4[0x18]; 4799 4800 u8 reserved_5[0x8]; 4801 u8 table_id[0x18]; 4802 4803 u8 group_id[0x20]; 4804 4805 u8 reserved_6[0x120]; 4806 }; 4807 4808 struct mlx5_ifc_query_flow_counter_out_bits { 4809 u8 status[0x8]; 4810 u8 reserved_at_8[0x18]; 4811 4812 u8 syndrome[0x20]; 4813 4814 u8 reserved_at_40[0x40]; 4815 4816 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4817 }; 4818 4819 struct mlx5_ifc_query_flow_counter_in_bits { 4820 u8 opcode[0x10]; 4821 u8 reserved_at_10[0x10]; 4822 4823 u8 reserved_at_20[0x10]; 4824 u8 op_mod[0x10]; 4825 4826 u8 reserved_at_40[0x80]; 4827 4828 u8 clear[0x1]; 4829 u8 reserved_at_c1[0xf]; 4830 u8 num_of_counters[0x10]; 4831 4832 u8 reserved_at_e0[0x10]; 4833 u8 flow_counter_id[0x10]; 4834 }; 4835 4836 struct mlx5_ifc_query_esw_vport_context_out_bits { 4837 u8 status[0x8]; 4838 u8 reserved_0[0x18]; 4839 4840 u8 syndrome[0x20]; 4841 4842 u8 reserved_1[0x40]; 4843 4844 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4845 }; 4846 4847 struct mlx5_ifc_query_esw_vport_context_in_bits { 4848 u8 opcode[0x10]; 4849 u8 reserved_0[0x10]; 4850 4851 u8 reserved_1[0x10]; 4852 u8 op_mod[0x10]; 4853 4854 u8 other_vport[0x1]; 4855 u8 reserved_2[0xf]; 4856 u8 vport_number[0x10]; 4857 4858 u8 reserved_3[0x20]; 4859 }; 4860 4861 struct mlx5_ifc_query_eq_out_bits { 4862 u8 status[0x8]; 4863 u8 reserved_0[0x18]; 4864 4865 u8 syndrome[0x20]; 4866 4867 u8 reserved_1[0x40]; 4868 4869 struct mlx5_ifc_eqc_bits eq_context_entry; 4870 4871 u8 reserved_2[0x40]; 4872 4873 u8 event_bitmask[0x40]; 4874 4875 u8 reserved_3[0x580]; 4876 4877 u8 pas[0][0x40]; 4878 }; 4879 4880 struct mlx5_ifc_query_eq_in_bits { 4881 u8 opcode[0x10]; 4882 u8 reserved_0[0x10]; 4883 4884 u8 reserved_1[0x10]; 4885 u8 op_mod[0x10]; 4886 4887 u8 reserved_2[0x18]; 4888 u8 eq_number[0x8]; 4889 4890 u8 reserved_3[0x20]; 4891 }; 4892 4893 struct mlx5_ifc_query_dct_out_bits { 4894 u8 status[0x8]; 4895 u8 reserved_0[0x18]; 4896 4897 u8 syndrome[0x20]; 4898 4899 u8 reserved_1[0x40]; 4900 4901 struct mlx5_ifc_dctc_bits dct_context_entry; 4902 4903 u8 reserved_2[0x180]; 4904 }; 4905 4906 struct mlx5_ifc_query_dct_in_bits { 4907 u8 opcode[0x10]; 4908 u8 reserved_0[0x10]; 4909 4910 u8 reserved_1[0x10]; 4911 u8 op_mod[0x10]; 4912 4913 u8 reserved_2[0x8]; 4914 u8 dctn[0x18]; 4915 4916 u8 reserved_3[0x20]; 4917 }; 4918 4919 struct mlx5_ifc_query_dc_cnak_trace_out_bits { 4920 u8 status[0x8]; 4921 u8 reserved_0[0x18]; 4922 4923 u8 syndrome[0x20]; 4924 4925 u8 enable[0x1]; 4926 u8 reserved_1[0x1f]; 4927 4928 u8 reserved_2[0x160]; 4929 4930 struct mlx5_ifc_cmd_pas_bits pas; 4931 }; 4932 4933 struct mlx5_ifc_query_dc_cnak_trace_in_bits { 4934 u8 opcode[0x10]; 4935 u8 reserved_0[0x10]; 4936 4937 u8 reserved_1[0x10]; 4938 u8 op_mod[0x10]; 4939 4940 u8 reserved_2[0x40]; 4941 }; 4942 4943 struct mlx5_ifc_query_cq_out_bits { 4944 u8 status[0x8]; 4945 u8 reserved_0[0x18]; 4946 4947 u8 syndrome[0x20]; 4948 4949 u8 reserved_1[0x40]; 4950 4951 struct mlx5_ifc_cqc_bits cq_context; 4952 4953 u8 reserved_2[0x600]; 4954 4955 u8 pas[0][0x40]; 4956 }; 4957 4958 struct mlx5_ifc_query_cq_in_bits { 4959 u8 opcode[0x10]; 4960 u8 reserved_0[0x10]; 4961 4962 u8 reserved_1[0x10]; 4963 u8 op_mod[0x10]; 4964 4965 u8 reserved_2[0x8]; 4966 u8 cqn[0x18]; 4967 4968 u8 reserved_3[0x20]; 4969 }; 4970 4971 struct mlx5_ifc_query_cong_status_out_bits { 4972 u8 status[0x8]; 4973 u8 reserved_0[0x18]; 4974 4975 u8 syndrome[0x20]; 4976 4977 u8 reserved_1[0x20]; 4978 4979 u8 enable[0x1]; 4980 u8 tag_enable[0x1]; 4981 u8 reserved_2[0x1e]; 4982 }; 4983 4984 struct mlx5_ifc_query_cong_status_in_bits { 4985 u8 opcode[0x10]; 4986 u8 reserved_0[0x10]; 4987 4988 u8 reserved_1[0x10]; 4989 u8 op_mod[0x10]; 4990 4991 u8 reserved_2[0x18]; 4992 u8 priority[0x4]; 4993 u8 cong_protocol[0x4]; 4994 4995 u8 reserved_3[0x20]; 4996 }; 4997 4998 struct mlx5_ifc_query_cong_statistics_out_bits { 4999 u8 status[0x8]; 5000 u8 reserved_0[0x18]; 5001 5002 u8 syndrome[0x20]; 5003 5004 u8 reserved_1[0x40]; 5005 5006 u8 rp_cur_flows[0x20]; 5007 5008 u8 sum_flows[0x20]; 5009 5010 u8 rp_cnp_ignored_high[0x20]; 5011 5012 u8 rp_cnp_ignored_low[0x20]; 5013 5014 u8 rp_cnp_handled_high[0x20]; 5015 5016 u8 rp_cnp_handled_low[0x20]; 5017 5018 u8 reserved_2[0x100]; 5019 5020 u8 time_stamp_high[0x20]; 5021 5022 u8 time_stamp_low[0x20]; 5023 5024 u8 accumulators_period[0x20]; 5025 5026 u8 np_ecn_marked_roce_packets_high[0x20]; 5027 5028 u8 np_ecn_marked_roce_packets_low[0x20]; 5029 5030 u8 np_cnp_sent_high[0x20]; 5031 5032 u8 np_cnp_sent_low[0x20]; 5033 5034 u8 reserved_3[0x560]; 5035 }; 5036 5037 struct mlx5_ifc_query_cong_statistics_in_bits { 5038 u8 opcode[0x10]; 5039 u8 reserved_0[0x10]; 5040 5041 u8 reserved_1[0x10]; 5042 u8 op_mod[0x10]; 5043 5044 u8 clear[0x1]; 5045 u8 reserved_2[0x1f]; 5046 5047 u8 reserved_3[0x20]; 5048 }; 5049 5050 struct mlx5_ifc_query_cong_params_out_bits { 5051 u8 status[0x8]; 5052 u8 reserved_0[0x18]; 5053 5054 u8 syndrome[0x20]; 5055 5056 u8 reserved_1[0x40]; 5057 5058 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5059 }; 5060 5061 struct mlx5_ifc_query_cong_params_in_bits { 5062 u8 opcode[0x10]; 5063 u8 reserved_0[0x10]; 5064 5065 u8 reserved_1[0x10]; 5066 u8 op_mod[0x10]; 5067 5068 u8 reserved_2[0x1c]; 5069 u8 cong_protocol[0x4]; 5070 5071 u8 reserved_3[0x20]; 5072 }; 5073 5074 struct mlx5_ifc_query_burst_size_out_bits { 5075 u8 status[0x8]; 5076 u8 reserved_0[0x18]; 5077 5078 u8 syndrome[0x20]; 5079 5080 u8 reserved_1[0x20]; 5081 5082 u8 reserved_2[0x9]; 5083 u8 device_burst_size[0x17]; 5084 }; 5085 5086 struct mlx5_ifc_query_burst_size_in_bits { 5087 u8 opcode[0x10]; 5088 u8 reserved_0[0x10]; 5089 5090 u8 reserved_1[0x10]; 5091 u8 op_mod[0x10]; 5092 5093 u8 reserved_2[0x40]; 5094 }; 5095 5096 struct mlx5_ifc_query_adapter_out_bits { 5097 u8 status[0x8]; 5098 u8 reserved_0[0x18]; 5099 5100 u8 syndrome[0x20]; 5101 5102 u8 reserved_1[0x40]; 5103 5104 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5105 }; 5106 5107 struct mlx5_ifc_query_adapter_in_bits { 5108 u8 opcode[0x10]; 5109 u8 reserved_0[0x10]; 5110 5111 u8 reserved_1[0x10]; 5112 u8 op_mod[0x10]; 5113 5114 u8 reserved_2[0x40]; 5115 }; 5116 5117 struct mlx5_ifc_qp_2rst_out_bits { 5118 u8 status[0x8]; 5119 u8 reserved_0[0x18]; 5120 5121 u8 syndrome[0x20]; 5122 5123 u8 reserved_1[0x40]; 5124 }; 5125 5126 struct mlx5_ifc_qp_2rst_in_bits { 5127 u8 opcode[0x10]; 5128 u8 reserved_0[0x10]; 5129 5130 u8 reserved_1[0x10]; 5131 u8 op_mod[0x10]; 5132 5133 u8 reserved_2[0x8]; 5134 u8 qpn[0x18]; 5135 5136 u8 reserved_3[0x20]; 5137 }; 5138 5139 struct mlx5_ifc_qp_2err_out_bits { 5140 u8 status[0x8]; 5141 u8 reserved_0[0x18]; 5142 5143 u8 syndrome[0x20]; 5144 5145 u8 reserved_1[0x40]; 5146 }; 5147 5148 struct mlx5_ifc_qp_2err_in_bits { 5149 u8 opcode[0x10]; 5150 u8 reserved_0[0x10]; 5151 5152 u8 reserved_1[0x10]; 5153 u8 op_mod[0x10]; 5154 5155 u8 reserved_2[0x8]; 5156 u8 qpn[0x18]; 5157 5158 u8 reserved_3[0x20]; 5159 }; 5160 5161 struct mlx5_ifc_para_vport_element_bits { 5162 u8 reserved_at_0[0xc]; 5163 u8 traffic_class[0x4]; 5164 u8 qos_para_vport_number[0x10]; 5165 }; 5166 5167 struct mlx5_ifc_page_fault_resume_out_bits { 5168 u8 status[0x8]; 5169 u8 reserved_0[0x18]; 5170 5171 u8 syndrome[0x20]; 5172 5173 u8 reserved_1[0x40]; 5174 }; 5175 5176 struct mlx5_ifc_page_fault_resume_in_bits { 5177 u8 opcode[0x10]; 5178 u8 reserved_0[0x10]; 5179 5180 u8 reserved_1[0x10]; 5181 u8 op_mod[0x10]; 5182 5183 u8 error[0x1]; 5184 u8 reserved_2[0x4]; 5185 u8 rdma[0x1]; 5186 u8 read_write[0x1]; 5187 u8 req_res[0x1]; 5188 u8 qpn[0x18]; 5189 5190 u8 reserved_3[0x20]; 5191 }; 5192 5193 struct mlx5_ifc_nop_out_bits { 5194 u8 status[0x8]; 5195 u8 reserved_0[0x18]; 5196 5197 u8 syndrome[0x20]; 5198 5199 u8 reserved_1[0x40]; 5200 }; 5201 5202 struct mlx5_ifc_nop_in_bits { 5203 u8 opcode[0x10]; 5204 u8 reserved_0[0x10]; 5205 5206 u8 reserved_1[0x10]; 5207 u8 op_mod[0x10]; 5208 5209 u8 reserved_2[0x40]; 5210 }; 5211 5212 struct mlx5_ifc_modify_vport_state_out_bits { 5213 u8 status[0x8]; 5214 u8 reserved_0[0x18]; 5215 5216 u8 syndrome[0x20]; 5217 5218 u8 reserved_1[0x40]; 5219 }; 5220 5221 enum { 5222 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5223 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5224 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5225 }; 5226 5227 enum { 5228 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5229 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5230 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5231 }; 5232 5233 struct mlx5_ifc_modify_vport_state_in_bits { 5234 u8 opcode[0x10]; 5235 u8 reserved_0[0x10]; 5236 5237 u8 reserved_1[0x10]; 5238 u8 op_mod[0x10]; 5239 5240 u8 other_vport[0x1]; 5241 u8 reserved_2[0xf]; 5242 u8 vport_number[0x10]; 5243 5244 u8 reserved_3[0x18]; 5245 u8 admin_state[0x4]; 5246 u8 reserved_4[0x4]; 5247 }; 5248 5249 struct mlx5_ifc_modify_tis_out_bits { 5250 u8 status[0x8]; 5251 u8 reserved_0[0x18]; 5252 5253 u8 syndrome[0x20]; 5254 5255 u8 reserved_1[0x40]; 5256 }; 5257 5258 struct mlx5_ifc_modify_tis_bitmask_bits { 5259 u8 reserved_at_0[0x20]; 5260 5261 u8 reserved_at_20[0x1d]; 5262 u8 lag_tx_port_affinity[0x1]; 5263 u8 strict_lag_tx_port_affinity[0x1]; 5264 u8 prio[0x1]; 5265 }; 5266 5267 struct mlx5_ifc_modify_tis_in_bits { 5268 u8 opcode[0x10]; 5269 u8 reserved_0[0x10]; 5270 5271 u8 reserved_1[0x10]; 5272 u8 op_mod[0x10]; 5273 5274 u8 reserved_2[0x8]; 5275 u8 tisn[0x18]; 5276 5277 u8 reserved_3[0x20]; 5278 5279 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5280 5281 u8 reserved_4[0x40]; 5282 5283 struct mlx5_ifc_tisc_bits ctx; 5284 }; 5285 5286 struct mlx5_ifc_modify_tir_out_bits { 5287 u8 status[0x8]; 5288 u8 reserved_0[0x18]; 5289 5290 u8 syndrome[0x20]; 5291 5292 u8 reserved_1[0x40]; 5293 }; 5294 5295 enum 5296 { 5297 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5298 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5299 }; 5300 5301 struct mlx5_ifc_modify_tir_in_bits { 5302 u8 opcode[0x10]; 5303 u8 reserved_0[0x10]; 5304 5305 u8 reserved_1[0x10]; 5306 u8 op_mod[0x10]; 5307 5308 u8 reserved_2[0x8]; 5309 u8 tirn[0x18]; 5310 5311 u8 reserved_3[0x20]; 5312 5313 u8 modify_bitmask[0x40]; 5314 5315 u8 reserved_4[0x40]; 5316 5317 struct mlx5_ifc_tirc_bits tir_context; 5318 }; 5319 5320 struct mlx5_ifc_modify_sq_out_bits { 5321 u8 status[0x8]; 5322 u8 reserved_0[0x18]; 5323 5324 u8 syndrome[0x20]; 5325 5326 u8 reserved_1[0x40]; 5327 }; 5328 5329 struct mlx5_ifc_modify_sq_in_bits { 5330 u8 opcode[0x10]; 5331 u8 reserved_0[0x10]; 5332 5333 u8 reserved_1[0x10]; 5334 u8 op_mod[0x10]; 5335 5336 u8 sq_state[0x4]; 5337 u8 reserved_2[0x4]; 5338 u8 sqn[0x18]; 5339 5340 u8 reserved_3[0x20]; 5341 5342 u8 modify_bitmask[0x40]; 5343 5344 u8 reserved_4[0x40]; 5345 5346 struct mlx5_ifc_sqc_bits ctx; 5347 }; 5348 5349 struct mlx5_ifc_modify_scheduling_element_out_bits { 5350 u8 status[0x8]; 5351 u8 reserved_at_8[0x18]; 5352 5353 u8 syndrome[0x20]; 5354 5355 u8 reserved_at_40[0x1c0]; 5356 }; 5357 5358 enum { 5359 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5360 }; 5361 5362 enum { 5363 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5364 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5365 }; 5366 5367 struct mlx5_ifc_modify_scheduling_element_in_bits { 5368 u8 opcode[0x10]; 5369 u8 reserved_at_10[0x10]; 5370 5371 u8 reserved_at_20[0x10]; 5372 u8 op_mod[0x10]; 5373 5374 u8 scheduling_hierarchy[0x8]; 5375 u8 reserved_at_48[0x18]; 5376 5377 u8 scheduling_element_id[0x20]; 5378 5379 u8 reserved_at_80[0x20]; 5380 5381 u8 modify_bitmask[0x20]; 5382 5383 u8 reserved_at_c0[0x40]; 5384 5385 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5386 5387 u8 reserved_at_300[0x100]; 5388 }; 5389 5390 struct mlx5_ifc_modify_rqt_out_bits { 5391 u8 status[0x8]; 5392 u8 reserved_0[0x18]; 5393 5394 u8 syndrome[0x20]; 5395 5396 u8 reserved_1[0x40]; 5397 }; 5398 5399 struct mlx5_ifc_modify_rqt_in_bits { 5400 u8 opcode[0x10]; 5401 u8 reserved_0[0x10]; 5402 5403 u8 reserved_1[0x10]; 5404 u8 op_mod[0x10]; 5405 5406 u8 reserved_2[0x8]; 5407 u8 rqtn[0x18]; 5408 5409 u8 reserved_3[0x20]; 5410 5411 u8 modify_bitmask[0x40]; 5412 5413 u8 reserved_4[0x40]; 5414 5415 struct mlx5_ifc_rqtc_bits ctx; 5416 }; 5417 5418 struct mlx5_ifc_modify_rq_out_bits { 5419 u8 status[0x8]; 5420 u8 reserved_0[0x18]; 5421 5422 u8 syndrome[0x20]; 5423 5424 u8 reserved_1[0x40]; 5425 }; 5426 5427 enum { 5428 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5429 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5430 }; 5431 5432 struct mlx5_ifc_modify_rq_in_bits { 5433 u8 opcode[0x10]; 5434 u8 reserved_0[0x10]; 5435 5436 u8 reserved_1[0x10]; 5437 u8 op_mod[0x10]; 5438 5439 u8 rq_state[0x4]; 5440 u8 reserved_2[0x4]; 5441 u8 rqn[0x18]; 5442 5443 u8 reserved_3[0x20]; 5444 5445 u8 modify_bitmask[0x40]; 5446 5447 u8 reserved_4[0x40]; 5448 5449 struct mlx5_ifc_rqc_bits ctx; 5450 }; 5451 5452 struct mlx5_ifc_modify_rmp_out_bits { 5453 u8 status[0x8]; 5454 u8 reserved_0[0x18]; 5455 5456 u8 syndrome[0x20]; 5457 5458 u8 reserved_1[0x40]; 5459 }; 5460 5461 struct mlx5_ifc_rmp_bitmask_bits { 5462 u8 reserved[0x20]; 5463 5464 u8 reserved1[0x1f]; 5465 u8 lwm[0x1]; 5466 }; 5467 5468 struct mlx5_ifc_modify_rmp_in_bits { 5469 u8 opcode[0x10]; 5470 u8 reserved_0[0x10]; 5471 5472 u8 reserved_1[0x10]; 5473 u8 op_mod[0x10]; 5474 5475 u8 rmp_state[0x4]; 5476 u8 reserved_2[0x4]; 5477 u8 rmpn[0x18]; 5478 5479 u8 reserved_3[0x20]; 5480 5481 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5482 5483 u8 reserved_4[0x40]; 5484 5485 struct mlx5_ifc_rmpc_bits ctx; 5486 }; 5487 5488 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5489 u8 status[0x8]; 5490 u8 reserved_0[0x18]; 5491 5492 u8 syndrome[0x20]; 5493 5494 u8 reserved_1[0x40]; 5495 }; 5496 5497 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5498 u8 reserved_0[0x14]; 5499 u8 disable_uc_local_lb[0x1]; 5500 u8 disable_mc_local_lb[0x1]; 5501 u8 node_guid[0x1]; 5502 u8 port_guid[0x1]; 5503 u8 min_wqe_inline_mode[0x1]; 5504 u8 mtu[0x1]; 5505 u8 change_event[0x1]; 5506 u8 promisc[0x1]; 5507 u8 permanent_address[0x1]; 5508 u8 addresses_list[0x1]; 5509 u8 roce_en[0x1]; 5510 u8 reserved_1[0x1]; 5511 }; 5512 5513 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5514 u8 opcode[0x10]; 5515 u8 reserved_0[0x10]; 5516 5517 u8 reserved_1[0x10]; 5518 u8 op_mod[0x10]; 5519 5520 u8 other_vport[0x1]; 5521 u8 reserved_2[0xf]; 5522 u8 vport_number[0x10]; 5523 5524 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5525 5526 u8 reserved_3[0x780]; 5527 5528 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5529 }; 5530 5531 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5532 u8 status[0x8]; 5533 u8 reserved_0[0x18]; 5534 5535 u8 syndrome[0x20]; 5536 5537 u8 reserved_1[0x40]; 5538 }; 5539 5540 struct mlx5_ifc_grh_bits { 5541 u8 ip_version[4]; 5542 u8 traffic_class[8]; 5543 u8 flow_label[20]; 5544 u8 payload_length[16]; 5545 u8 next_header[8]; 5546 u8 hop_limit[8]; 5547 u8 sgid[128]; 5548 u8 dgid[128]; 5549 }; 5550 5551 struct mlx5_ifc_bth_bits { 5552 u8 opcode[8]; 5553 u8 se[1]; 5554 u8 migreq[1]; 5555 u8 pad_count[2]; 5556 u8 tver[4]; 5557 u8 p_key[16]; 5558 u8 reserved8[8]; 5559 u8 dest_qp[24]; 5560 u8 ack_req[1]; 5561 u8 reserved7[7]; 5562 u8 psn[24]; 5563 }; 5564 5565 struct mlx5_ifc_aeth_bits { 5566 u8 syndrome[8]; 5567 u8 msn[24]; 5568 }; 5569 5570 struct mlx5_ifc_dceth_bits { 5571 u8 reserved0[8]; 5572 u8 session_id[24]; 5573 u8 reserved1[8]; 5574 u8 dci_dct[24]; 5575 }; 5576 5577 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5578 u8 opcode[0x10]; 5579 u8 reserved_0[0x10]; 5580 5581 u8 reserved_1[0x10]; 5582 u8 op_mod[0x10]; 5583 5584 u8 other_vport[0x1]; 5585 u8 reserved_2[0xb]; 5586 u8 port_num[0x4]; 5587 u8 vport_number[0x10]; 5588 5589 u8 reserved_3[0x20]; 5590 5591 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5592 }; 5593 5594 struct mlx5_ifc_modify_flow_table_out_bits { 5595 u8 status[0x8]; 5596 u8 reserved_at_8[0x18]; 5597 5598 u8 syndrome[0x20]; 5599 5600 u8 reserved_at_40[0x40]; 5601 }; 5602 5603 enum { 5604 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 5605 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 5606 }; 5607 5608 struct mlx5_ifc_modify_flow_table_in_bits { 5609 u8 opcode[0x10]; 5610 u8 reserved_at_10[0x10]; 5611 5612 u8 reserved_at_20[0x10]; 5613 u8 op_mod[0x10]; 5614 5615 u8 other_vport[0x1]; 5616 u8 reserved_at_41[0xf]; 5617 u8 vport_number[0x10]; 5618 5619 u8 reserved_at_60[0x10]; 5620 u8 modify_field_select[0x10]; 5621 5622 u8 table_type[0x8]; 5623 u8 reserved_at_88[0x18]; 5624 5625 u8 reserved_at_a0[0x8]; 5626 u8 table_id[0x18]; 5627 5628 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5629 }; 5630 5631 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5632 u8 status[0x8]; 5633 u8 reserved_0[0x18]; 5634 5635 u8 syndrome[0x20]; 5636 5637 u8 reserved_1[0x40]; 5638 }; 5639 5640 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5641 u8 reserved[0x1c]; 5642 u8 vport_cvlan_insert[0x1]; 5643 u8 vport_svlan_insert[0x1]; 5644 u8 vport_cvlan_strip[0x1]; 5645 u8 vport_svlan_strip[0x1]; 5646 }; 5647 5648 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5649 u8 opcode[0x10]; 5650 u8 reserved_0[0x10]; 5651 5652 u8 reserved_1[0x10]; 5653 u8 op_mod[0x10]; 5654 5655 u8 other_vport[0x1]; 5656 u8 reserved_2[0xf]; 5657 u8 vport_number[0x10]; 5658 5659 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5660 5661 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5662 }; 5663 5664 struct mlx5_ifc_modify_cq_out_bits { 5665 u8 status[0x8]; 5666 u8 reserved_0[0x18]; 5667 5668 u8 syndrome[0x20]; 5669 5670 u8 reserved_1[0x40]; 5671 }; 5672 5673 enum { 5674 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5675 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5676 }; 5677 5678 struct mlx5_ifc_modify_cq_in_bits { 5679 u8 opcode[0x10]; 5680 u8 reserved_0[0x10]; 5681 5682 u8 reserved_1[0x10]; 5683 u8 op_mod[0x10]; 5684 5685 u8 reserved_2[0x8]; 5686 u8 cqn[0x18]; 5687 5688 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5689 5690 struct mlx5_ifc_cqc_bits cq_context; 5691 5692 u8 reserved_3[0x600]; 5693 5694 u8 pas[0][0x40]; 5695 }; 5696 5697 struct mlx5_ifc_modify_cong_status_out_bits { 5698 u8 status[0x8]; 5699 u8 reserved_0[0x18]; 5700 5701 u8 syndrome[0x20]; 5702 5703 u8 reserved_1[0x40]; 5704 }; 5705 5706 struct mlx5_ifc_modify_cong_status_in_bits { 5707 u8 opcode[0x10]; 5708 u8 reserved_0[0x10]; 5709 5710 u8 reserved_1[0x10]; 5711 u8 op_mod[0x10]; 5712 5713 u8 reserved_2[0x18]; 5714 u8 priority[0x4]; 5715 u8 cong_protocol[0x4]; 5716 5717 u8 enable[0x1]; 5718 u8 tag_enable[0x1]; 5719 u8 reserved_3[0x1e]; 5720 }; 5721 5722 struct mlx5_ifc_modify_cong_params_out_bits { 5723 u8 status[0x8]; 5724 u8 reserved_0[0x18]; 5725 5726 u8 syndrome[0x20]; 5727 5728 u8 reserved_1[0x40]; 5729 }; 5730 5731 struct mlx5_ifc_modify_cong_params_in_bits { 5732 u8 opcode[0x10]; 5733 u8 reserved_0[0x10]; 5734 5735 u8 reserved_1[0x10]; 5736 u8 op_mod[0x10]; 5737 5738 u8 reserved_2[0x1c]; 5739 u8 cong_protocol[0x4]; 5740 5741 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5742 5743 u8 reserved_3[0x80]; 5744 5745 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5746 }; 5747 5748 struct mlx5_ifc_manage_pages_out_bits { 5749 u8 status[0x8]; 5750 u8 reserved_0[0x18]; 5751 5752 u8 syndrome[0x20]; 5753 5754 u8 output_num_entries[0x20]; 5755 5756 u8 reserved_1[0x20]; 5757 5758 u8 pas[0][0x40]; 5759 }; 5760 5761 enum { 5762 MLX5_PAGES_CANT_GIVE = 0x0, 5763 MLX5_PAGES_GIVE = 0x1, 5764 MLX5_PAGES_TAKE = 0x2, 5765 }; 5766 5767 struct mlx5_ifc_manage_pages_in_bits { 5768 u8 opcode[0x10]; 5769 u8 reserved_0[0x10]; 5770 5771 u8 reserved_1[0x10]; 5772 u8 op_mod[0x10]; 5773 5774 u8 reserved_2[0x10]; 5775 u8 function_id[0x10]; 5776 5777 u8 input_num_entries[0x20]; 5778 5779 u8 pas[0][0x40]; 5780 }; 5781 5782 struct mlx5_ifc_mad_ifc_out_bits { 5783 u8 status[0x8]; 5784 u8 reserved_0[0x18]; 5785 5786 u8 syndrome[0x20]; 5787 5788 u8 reserved_1[0x40]; 5789 5790 u8 response_mad_packet[256][0x8]; 5791 }; 5792 5793 struct mlx5_ifc_mad_ifc_in_bits { 5794 u8 opcode[0x10]; 5795 u8 reserved_0[0x10]; 5796 5797 u8 reserved_1[0x10]; 5798 u8 op_mod[0x10]; 5799 5800 u8 remote_lid[0x10]; 5801 u8 reserved_2[0x8]; 5802 u8 port[0x8]; 5803 5804 u8 reserved_3[0x20]; 5805 5806 u8 mad[256][0x8]; 5807 }; 5808 5809 struct mlx5_ifc_init_hca_out_bits { 5810 u8 status[0x8]; 5811 u8 reserved_0[0x18]; 5812 5813 u8 syndrome[0x20]; 5814 5815 u8 reserved_1[0x40]; 5816 }; 5817 5818 enum { 5819 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 5820 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 5821 }; 5822 5823 struct mlx5_ifc_init_hca_in_bits { 5824 u8 opcode[0x10]; 5825 u8 reserved_0[0x10]; 5826 5827 u8 reserved_1[0x10]; 5828 u8 op_mod[0x10]; 5829 5830 u8 reserved_2[0x40]; 5831 }; 5832 5833 struct mlx5_ifc_init2rtr_qp_out_bits { 5834 u8 status[0x8]; 5835 u8 reserved_0[0x18]; 5836 5837 u8 syndrome[0x20]; 5838 5839 u8 reserved_1[0x40]; 5840 }; 5841 5842 struct mlx5_ifc_init2rtr_qp_in_bits { 5843 u8 opcode[0x10]; 5844 u8 reserved_0[0x10]; 5845 5846 u8 reserved_1[0x10]; 5847 u8 op_mod[0x10]; 5848 5849 u8 reserved_2[0x8]; 5850 u8 qpn[0x18]; 5851 5852 u8 reserved_3[0x20]; 5853 5854 u8 opt_param_mask[0x20]; 5855 5856 u8 reserved_4[0x20]; 5857 5858 struct mlx5_ifc_qpc_bits qpc; 5859 5860 u8 reserved_5[0x80]; 5861 }; 5862 5863 struct mlx5_ifc_init2init_qp_out_bits { 5864 u8 status[0x8]; 5865 u8 reserved_0[0x18]; 5866 5867 u8 syndrome[0x20]; 5868 5869 u8 reserved_1[0x40]; 5870 }; 5871 5872 struct mlx5_ifc_init2init_qp_in_bits { 5873 u8 opcode[0x10]; 5874 u8 reserved_0[0x10]; 5875 5876 u8 reserved_1[0x10]; 5877 u8 op_mod[0x10]; 5878 5879 u8 reserved_2[0x8]; 5880 u8 qpn[0x18]; 5881 5882 u8 reserved_3[0x20]; 5883 5884 u8 opt_param_mask[0x20]; 5885 5886 u8 reserved_4[0x20]; 5887 5888 struct mlx5_ifc_qpc_bits qpc; 5889 5890 u8 reserved_5[0x80]; 5891 }; 5892 5893 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5894 u8 status[0x8]; 5895 u8 reserved_0[0x18]; 5896 5897 u8 syndrome[0x20]; 5898 5899 u8 reserved_1[0x40]; 5900 5901 u8 packet_headers_log[128][0x8]; 5902 5903 u8 packet_syndrome[64][0x8]; 5904 }; 5905 5906 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5907 u8 opcode[0x10]; 5908 u8 reserved_0[0x10]; 5909 5910 u8 reserved_1[0x10]; 5911 u8 op_mod[0x10]; 5912 5913 u8 reserved_2[0x40]; 5914 }; 5915 5916 struct mlx5_ifc_gen_eqe_in_bits { 5917 u8 opcode[0x10]; 5918 u8 reserved_0[0x10]; 5919 5920 u8 reserved_1[0x10]; 5921 u8 op_mod[0x10]; 5922 5923 u8 reserved_2[0x18]; 5924 u8 eq_number[0x8]; 5925 5926 u8 reserved_3[0x20]; 5927 5928 u8 eqe[64][0x8]; 5929 }; 5930 5931 struct mlx5_ifc_gen_eq_out_bits { 5932 u8 status[0x8]; 5933 u8 reserved_0[0x18]; 5934 5935 u8 syndrome[0x20]; 5936 5937 u8 reserved_1[0x40]; 5938 }; 5939 5940 struct mlx5_ifc_enable_hca_out_bits { 5941 u8 status[0x8]; 5942 u8 reserved_0[0x18]; 5943 5944 u8 syndrome[0x20]; 5945 5946 u8 reserved_1[0x20]; 5947 }; 5948 5949 struct mlx5_ifc_enable_hca_in_bits { 5950 u8 opcode[0x10]; 5951 u8 reserved_0[0x10]; 5952 5953 u8 reserved_1[0x10]; 5954 u8 op_mod[0x10]; 5955 5956 u8 reserved_2[0x10]; 5957 u8 function_id[0x10]; 5958 5959 u8 reserved_3[0x20]; 5960 }; 5961 5962 struct mlx5_ifc_drain_dct_out_bits { 5963 u8 status[0x8]; 5964 u8 reserved_0[0x18]; 5965 5966 u8 syndrome[0x20]; 5967 5968 u8 reserved_1[0x40]; 5969 }; 5970 5971 struct mlx5_ifc_drain_dct_in_bits { 5972 u8 opcode[0x10]; 5973 u8 reserved_0[0x10]; 5974 5975 u8 reserved_1[0x10]; 5976 u8 op_mod[0x10]; 5977 5978 u8 reserved_2[0x8]; 5979 u8 dctn[0x18]; 5980 5981 u8 reserved_3[0x20]; 5982 }; 5983 5984 struct mlx5_ifc_disable_hca_out_bits { 5985 u8 status[0x8]; 5986 u8 reserved_0[0x18]; 5987 5988 u8 syndrome[0x20]; 5989 5990 u8 reserved_1[0x20]; 5991 }; 5992 5993 struct mlx5_ifc_disable_hca_in_bits { 5994 u8 opcode[0x10]; 5995 u8 reserved_0[0x10]; 5996 5997 u8 reserved_1[0x10]; 5998 u8 op_mod[0x10]; 5999 6000 u8 reserved_2[0x10]; 6001 u8 function_id[0x10]; 6002 6003 u8 reserved_3[0x20]; 6004 }; 6005 6006 struct mlx5_ifc_detach_from_mcg_out_bits { 6007 u8 status[0x8]; 6008 u8 reserved_0[0x18]; 6009 6010 u8 syndrome[0x20]; 6011 6012 u8 reserved_1[0x40]; 6013 }; 6014 6015 struct mlx5_ifc_detach_from_mcg_in_bits { 6016 u8 opcode[0x10]; 6017 u8 reserved_0[0x10]; 6018 6019 u8 reserved_1[0x10]; 6020 u8 op_mod[0x10]; 6021 6022 u8 reserved_2[0x8]; 6023 u8 qpn[0x18]; 6024 6025 u8 reserved_3[0x20]; 6026 6027 u8 multicast_gid[16][0x8]; 6028 }; 6029 6030 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6031 u8 status[0x8]; 6032 u8 reserved_0[0x18]; 6033 6034 u8 syndrome[0x20]; 6035 6036 u8 reserved_1[0x40]; 6037 }; 6038 6039 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6040 u8 opcode[0x10]; 6041 u8 reserved_0[0x10]; 6042 6043 u8 reserved_1[0x10]; 6044 u8 op_mod[0x10]; 6045 6046 u8 reserved_2[0x8]; 6047 u8 xrc_srqn[0x18]; 6048 6049 u8 reserved_3[0x20]; 6050 }; 6051 6052 struct mlx5_ifc_destroy_tis_out_bits { 6053 u8 status[0x8]; 6054 u8 reserved_0[0x18]; 6055 6056 u8 syndrome[0x20]; 6057 6058 u8 reserved_1[0x40]; 6059 }; 6060 6061 struct mlx5_ifc_destroy_tis_in_bits { 6062 u8 opcode[0x10]; 6063 u8 reserved_0[0x10]; 6064 6065 u8 reserved_1[0x10]; 6066 u8 op_mod[0x10]; 6067 6068 u8 reserved_2[0x8]; 6069 u8 tisn[0x18]; 6070 6071 u8 reserved_3[0x20]; 6072 }; 6073 6074 struct mlx5_ifc_destroy_tir_out_bits { 6075 u8 status[0x8]; 6076 u8 reserved_0[0x18]; 6077 6078 u8 syndrome[0x20]; 6079 6080 u8 reserved_1[0x40]; 6081 }; 6082 6083 struct mlx5_ifc_destroy_tir_in_bits { 6084 u8 opcode[0x10]; 6085 u8 reserved_0[0x10]; 6086 6087 u8 reserved_1[0x10]; 6088 u8 op_mod[0x10]; 6089 6090 u8 reserved_2[0x8]; 6091 u8 tirn[0x18]; 6092 6093 u8 reserved_3[0x20]; 6094 }; 6095 6096 struct mlx5_ifc_destroy_srq_out_bits { 6097 u8 status[0x8]; 6098 u8 reserved_0[0x18]; 6099 6100 u8 syndrome[0x20]; 6101 6102 u8 reserved_1[0x40]; 6103 }; 6104 6105 struct mlx5_ifc_destroy_srq_in_bits { 6106 u8 opcode[0x10]; 6107 u8 reserved_0[0x10]; 6108 6109 u8 reserved_1[0x10]; 6110 u8 op_mod[0x10]; 6111 6112 u8 reserved_2[0x8]; 6113 u8 srqn[0x18]; 6114 6115 u8 reserved_3[0x20]; 6116 }; 6117 6118 struct mlx5_ifc_destroy_sq_out_bits { 6119 u8 status[0x8]; 6120 u8 reserved_0[0x18]; 6121 6122 u8 syndrome[0x20]; 6123 6124 u8 reserved_1[0x40]; 6125 }; 6126 6127 struct mlx5_ifc_destroy_sq_in_bits { 6128 u8 opcode[0x10]; 6129 u8 reserved_0[0x10]; 6130 6131 u8 reserved_1[0x10]; 6132 u8 op_mod[0x10]; 6133 6134 u8 reserved_2[0x8]; 6135 u8 sqn[0x18]; 6136 6137 u8 reserved_3[0x20]; 6138 }; 6139 6140 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6141 u8 status[0x8]; 6142 u8 reserved_at_8[0x18]; 6143 6144 u8 syndrome[0x20]; 6145 6146 u8 reserved_at_40[0x1c0]; 6147 }; 6148 6149 enum { 6150 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6151 }; 6152 6153 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6154 u8 opcode[0x10]; 6155 u8 reserved_at_10[0x10]; 6156 6157 u8 reserved_at_20[0x10]; 6158 u8 op_mod[0x10]; 6159 6160 u8 scheduling_hierarchy[0x8]; 6161 u8 reserved_at_48[0x18]; 6162 6163 u8 scheduling_element_id[0x20]; 6164 6165 u8 reserved_at_80[0x180]; 6166 }; 6167 6168 struct mlx5_ifc_destroy_rqt_out_bits { 6169 u8 status[0x8]; 6170 u8 reserved_0[0x18]; 6171 6172 u8 syndrome[0x20]; 6173 6174 u8 reserved_1[0x40]; 6175 }; 6176 6177 struct mlx5_ifc_destroy_rqt_in_bits { 6178 u8 opcode[0x10]; 6179 u8 reserved_0[0x10]; 6180 6181 u8 reserved_1[0x10]; 6182 u8 op_mod[0x10]; 6183 6184 u8 reserved_2[0x8]; 6185 u8 rqtn[0x18]; 6186 6187 u8 reserved_3[0x20]; 6188 }; 6189 6190 struct mlx5_ifc_destroy_rq_out_bits { 6191 u8 status[0x8]; 6192 u8 reserved_0[0x18]; 6193 6194 u8 syndrome[0x20]; 6195 6196 u8 reserved_1[0x40]; 6197 }; 6198 6199 struct mlx5_ifc_destroy_rq_in_bits { 6200 u8 opcode[0x10]; 6201 u8 reserved_0[0x10]; 6202 6203 u8 reserved_1[0x10]; 6204 u8 op_mod[0x10]; 6205 6206 u8 reserved_2[0x8]; 6207 u8 rqn[0x18]; 6208 6209 u8 reserved_3[0x20]; 6210 }; 6211 6212 struct mlx5_ifc_destroy_rmp_out_bits { 6213 u8 status[0x8]; 6214 u8 reserved_0[0x18]; 6215 6216 u8 syndrome[0x20]; 6217 6218 u8 reserved_1[0x40]; 6219 }; 6220 6221 struct mlx5_ifc_destroy_rmp_in_bits { 6222 u8 opcode[0x10]; 6223 u8 reserved_0[0x10]; 6224 6225 u8 reserved_1[0x10]; 6226 u8 op_mod[0x10]; 6227 6228 u8 reserved_2[0x8]; 6229 u8 rmpn[0x18]; 6230 6231 u8 reserved_3[0x20]; 6232 }; 6233 6234 struct mlx5_ifc_destroy_qp_out_bits { 6235 u8 status[0x8]; 6236 u8 reserved_0[0x18]; 6237 6238 u8 syndrome[0x20]; 6239 6240 u8 reserved_1[0x40]; 6241 }; 6242 6243 struct mlx5_ifc_destroy_qp_in_bits { 6244 u8 opcode[0x10]; 6245 u8 reserved_0[0x10]; 6246 6247 u8 reserved_1[0x10]; 6248 u8 op_mod[0x10]; 6249 6250 u8 reserved_2[0x8]; 6251 u8 qpn[0x18]; 6252 6253 u8 reserved_3[0x20]; 6254 }; 6255 6256 struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6257 u8 status[0x8]; 6258 u8 reserved_at_8[0x18]; 6259 6260 u8 syndrome[0x20]; 6261 6262 u8 reserved_at_40[0x1c0]; 6263 }; 6264 6265 struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6266 u8 opcode[0x10]; 6267 u8 reserved_at_10[0x10]; 6268 6269 u8 reserved_at_20[0x10]; 6270 u8 op_mod[0x10]; 6271 6272 u8 reserved_at_40[0x20]; 6273 6274 u8 reserved_at_60[0x10]; 6275 u8 qos_para_vport_number[0x10]; 6276 6277 u8 reserved_at_80[0x180]; 6278 }; 6279 6280 struct mlx5_ifc_destroy_psv_out_bits { 6281 u8 status[0x8]; 6282 u8 reserved_0[0x18]; 6283 6284 u8 syndrome[0x20]; 6285 6286 u8 reserved_1[0x40]; 6287 }; 6288 6289 struct mlx5_ifc_destroy_psv_in_bits { 6290 u8 opcode[0x10]; 6291 u8 reserved_0[0x10]; 6292 6293 u8 reserved_1[0x10]; 6294 u8 op_mod[0x10]; 6295 6296 u8 reserved_2[0x8]; 6297 u8 psvn[0x18]; 6298 6299 u8 reserved_3[0x20]; 6300 }; 6301 6302 struct mlx5_ifc_destroy_mkey_out_bits { 6303 u8 status[0x8]; 6304 u8 reserved_0[0x18]; 6305 6306 u8 syndrome[0x20]; 6307 6308 u8 reserved_1[0x40]; 6309 }; 6310 6311 struct mlx5_ifc_destroy_mkey_in_bits { 6312 u8 opcode[0x10]; 6313 u8 reserved_0[0x10]; 6314 6315 u8 reserved_1[0x10]; 6316 u8 op_mod[0x10]; 6317 6318 u8 reserved_2[0x8]; 6319 u8 mkey_index[0x18]; 6320 6321 u8 reserved_3[0x20]; 6322 }; 6323 6324 struct mlx5_ifc_destroy_flow_table_out_bits { 6325 u8 status[0x8]; 6326 u8 reserved_0[0x18]; 6327 6328 u8 syndrome[0x20]; 6329 6330 u8 reserved_1[0x40]; 6331 }; 6332 6333 struct mlx5_ifc_destroy_flow_table_in_bits { 6334 u8 opcode[0x10]; 6335 u8 reserved_0[0x10]; 6336 6337 u8 reserved_1[0x10]; 6338 u8 op_mod[0x10]; 6339 6340 u8 other_vport[0x1]; 6341 u8 reserved_2[0xf]; 6342 u8 vport_number[0x10]; 6343 6344 u8 reserved_3[0x20]; 6345 6346 u8 table_type[0x8]; 6347 u8 reserved_4[0x18]; 6348 6349 u8 reserved_5[0x8]; 6350 u8 table_id[0x18]; 6351 6352 u8 reserved_6[0x140]; 6353 }; 6354 6355 struct mlx5_ifc_destroy_flow_group_out_bits { 6356 u8 status[0x8]; 6357 u8 reserved_0[0x18]; 6358 6359 u8 syndrome[0x20]; 6360 6361 u8 reserved_1[0x40]; 6362 }; 6363 6364 struct mlx5_ifc_destroy_flow_group_in_bits { 6365 u8 opcode[0x10]; 6366 u8 reserved_0[0x10]; 6367 6368 u8 reserved_1[0x10]; 6369 u8 op_mod[0x10]; 6370 6371 u8 other_vport[0x1]; 6372 u8 reserved_2[0xf]; 6373 u8 vport_number[0x10]; 6374 6375 u8 reserved_3[0x20]; 6376 6377 u8 table_type[0x8]; 6378 u8 reserved_4[0x18]; 6379 6380 u8 reserved_5[0x8]; 6381 u8 table_id[0x18]; 6382 6383 u8 group_id[0x20]; 6384 6385 u8 reserved_6[0x120]; 6386 }; 6387 6388 struct mlx5_ifc_destroy_eq_out_bits { 6389 u8 status[0x8]; 6390 u8 reserved_0[0x18]; 6391 6392 u8 syndrome[0x20]; 6393 6394 u8 reserved_1[0x40]; 6395 }; 6396 6397 struct mlx5_ifc_destroy_eq_in_bits { 6398 u8 opcode[0x10]; 6399 u8 reserved_0[0x10]; 6400 6401 u8 reserved_1[0x10]; 6402 u8 op_mod[0x10]; 6403 6404 u8 reserved_2[0x18]; 6405 u8 eq_number[0x8]; 6406 6407 u8 reserved_3[0x20]; 6408 }; 6409 6410 struct mlx5_ifc_destroy_dct_out_bits { 6411 u8 status[0x8]; 6412 u8 reserved_0[0x18]; 6413 6414 u8 syndrome[0x20]; 6415 6416 u8 reserved_1[0x40]; 6417 }; 6418 6419 struct mlx5_ifc_destroy_dct_in_bits { 6420 u8 opcode[0x10]; 6421 u8 reserved_0[0x10]; 6422 6423 u8 reserved_1[0x10]; 6424 u8 op_mod[0x10]; 6425 6426 u8 reserved_2[0x8]; 6427 u8 dctn[0x18]; 6428 6429 u8 reserved_3[0x20]; 6430 }; 6431 6432 struct mlx5_ifc_destroy_cq_out_bits { 6433 u8 status[0x8]; 6434 u8 reserved_0[0x18]; 6435 6436 u8 syndrome[0x20]; 6437 6438 u8 reserved_1[0x40]; 6439 }; 6440 6441 struct mlx5_ifc_destroy_cq_in_bits { 6442 u8 opcode[0x10]; 6443 u8 reserved_0[0x10]; 6444 6445 u8 reserved_1[0x10]; 6446 u8 op_mod[0x10]; 6447 6448 u8 reserved_2[0x8]; 6449 u8 cqn[0x18]; 6450 6451 u8 reserved_3[0x20]; 6452 }; 6453 6454 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6455 u8 status[0x8]; 6456 u8 reserved_0[0x18]; 6457 6458 u8 syndrome[0x20]; 6459 6460 u8 reserved_1[0x40]; 6461 }; 6462 6463 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6464 u8 opcode[0x10]; 6465 u8 reserved_0[0x10]; 6466 6467 u8 reserved_1[0x10]; 6468 u8 op_mod[0x10]; 6469 6470 u8 reserved_2[0x20]; 6471 6472 u8 reserved_3[0x10]; 6473 u8 vxlan_udp_port[0x10]; 6474 }; 6475 6476 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6477 u8 status[0x8]; 6478 u8 reserved_0[0x18]; 6479 6480 u8 syndrome[0x20]; 6481 6482 u8 reserved_1[0x40]; 6483 }; 6484 6485 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6486 u8 opcode[0x10]; 6487 u8 reserved_0[0x10]; 6488 6489 u8 reserved_1[0x10]; 6490 u8 op_mod[0x10]; 6491 6492 u8 reserved_2[0x60]; 6493 6494 u8 reserved_3[0x8]; 6495 u8 table_index[0x18]; 6496 6497 u8 reserved_4[0x140]; 6498 }; 6499 6500 struct mlx5_ifc_delete_fte_out_bits { 6501 u8 status[0x8]; 6502 u8 reserved_0[0x18]; 6503 6504 u8 syndrome[0x20]; 6505 6506 u8 reserved_1[0x40]; 6507 }; 6508 6509 struct mlx5_ifc_delete_fte_in_bits { 6510 u8 opcode[0x10]; 6511 u8 reserved_0[0x10]; 6512 6513 u8 reserved_1[0x10]; 6514 u8 op_mod[0x10]; 6515 6516 u8 other_vport[0x1]; 6517 u8 reserved_2[0xf]; 6518 u8 vport_number[0x10]; 6519 6520 u8 reserved_3[0x20]; 6521 6522 u8 table_type[0x8]; 6523 u8 reserved_4[0x18]; 6524 6525 u8 reserved_5[0x8]; 6526 u8 table_id[0x18]; 6527 6528 u8 reserved_6[0x40]; 6529 6530 u8 flow_index[0x20]; 6531 6532 u8 reserved_7[0xe0]; 6533 }; 6534 6535 struct mlx5_ifc_dealloc_xrcd_out_bits { 6536 u8 status[0x8]; 6537 u8 reserved_0[0x18]; 6538 6539 u8 syndrome[0x20]; 6540 6541 u8 reserved_1[0x40]; 6542 }; 6543 6544 struct mlx5_ifc_dealloc_xrcd_in_bits { 6545 u8 opcode[0x10]; 6546 u8 reserved_0[0x10]; 6547 6548 u8 reserved_1[0x10]; 6549 u8 op_mod[0x10]; 6550 6551 u8 reserved_2[0x8]; 6552 u8 xrcd[0x18]; 6553 6554 u8 reserved_3[0x20]; 6555 }; 6556 6557 struct mlx5_ifc_dealloc_uar_out_bits { 6558 u8 status[0x8]; 6559 u8 reserved_0[0x18]; 6560 6561 u8 syndrome[0x20]; 6562 6563 u8 reserved_1[0x40]; 6564 }; 6565 6566 struct mlx5_ifc_dealloc_uar_in_bits { 6567 u8 opcode[0x10]; 6568 u8 reserved_0[0x10]; 6569 6570 u8 reserved_1[0x10]; 6571 u8 op_mod[0x10]; 6572 6573 u8 reserved_2[0x8]; 6574 u8 uar[0x18]; 6575 6576 u8 reserved_3[0x20]; 6577 }; 6578 6579 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6580 u8 status[0x8]; 6581 u8 reserved_0[0x18]; 6582 6583 u8 syndrome[0x20]; 6584 6585 u8 reserved_1[0x40]; 6586 }; 6587 6588 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6589 u8 opcode[0x10]; 6590 u8 reserved_0[0x10]; 6591 6592 u8 reserved_1[0x10]; 6593 u8 op_mod[0x10]; 6594 6595 u8 reserved_2[0x8]; 6596 u8 transport_domain[0x18]; 6597 6598 u8 reserved_3[0x20]; 6599 }; 6600 6601 struct mlx5_ifc_dealloc_q_counter_out_bits { 6602 u8 status[0x8]; 6603 u8 reserved_0[0x18]; 6604 6605 u8 syndrome[0x20]; 6606 6607 u8 reserved_1[0x40]; 6608 }; 6609 6610 struct mlx5_ifc_counter_id_bits { 6611 u8 reserved[0x10]; 6612 u8 counter_id[0x10]; 6613 }; 6614 6615 struct mlx5_ifc_diagnostic_params_context_bits { 6616 u8 num_of_counters[0x10]; 6617 u8 reserved_2[0x8]; 6618 u8 log_num_of_samples[0x8]; 6619 6620 u8 single[0x1]; 6621 u8 repetitive[0x1]; 6622 u8 sync[0x1]; 6623 u8 clear[0x1]; 6624 u8 on_demand[0x1]; 6625 u8 enable[0x1]; 6626 u8 reserved_3[0x12]; 6627 u8 log_sample_period[0x8]; 6628 6629 u8 reserved_4[0x80]; 6630 6631 struct mlx5_ifc_counter_id_bits counter_id[0]; 6632 }; 6633 6634 struct mlx5_ifc_set_diagnostic_params_in_bits { 6635 u8 opcode[0x10]; 6636 u8 reserved_0[0x10]; 6637 6638 u8 reserved_1[0x10]; 6639 u8 op_mod[0x10]; 6640 6641 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 6642 }; 6643 6644 struct mlx5_ifc_set_diagnostic_params_out_bits { 6645 u8 status[0x8]; 6646 u8 reserved_0[0x18]; 6647 6648 u8 syndrome[0x20]; 6649 6650 u8 reserved_1[0x40]; 6651 }; 6652 6653 struct mlx5_ifc_query_diagnostic_counters_in_bits { 6654 u8 opcode[0x10]; 6655 u8 reserved_0[0x10]; 6656 6657 u8 reserved_1[0x10]; 6658 u8 op_mod[0x10]; 6659 6660 u8 num_of_samples[0x10]; 6661 u8 sample_index[0x10]; 6662 6663 u8 reserved_2[0x20]; 6664 }; 6665 6666 struct mlx5_ifc_diagnostic_counter_bits { 6667 u8 counter_id[0x10]; 6668 u8 sample_id[0x10]; 6669 6670 u8 time_stamp_31_0[0x20]; 6671 6672 u8 counter_value_h[0x20]; 6673 6674 u8 counter_value_l[0x20]; 6675 }; 6676 6677 struct mlx5_ifc_query_diagnostic_counters_out_bits { 6678 u8 status[0x8]; 6679 u8 reserved_0[0x18]; 6680 6681 u8 syndrome[0x20]; 6682 6683 u8 reserved_1[0x40]; 6684 6685 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 6686 }; 6687 6688 struct mlx5_ifc_dealloc_q_counter_in_bits { 6689 u8 opcode[0x10]; 6690 u8 reserved_0[0x10]; 6691 6692 u8 reserved_1[0x10]; 6693 u8 op_mod[0x10]; 6694 6695 u8 reserved_2[0x18]; 6696 u8 counter_set_id[0x8]; 6697 6698 u8 reserved_3[0x20]; 6699 }; 6700 6701 struct mlx5_ifc_dealloc_pd_out_bits { 6702 u8 status[0x8]; 6703 u8 reserved_0[0x18]; 6704 6705 u8 syndrome[0x20]; 6706 6707 u8 reserved_1[0x40]; 6708 }; 6709 6710 struct mlx5_ifc_dealloc_pd_in_bits { 6711 u8 opcode[0x10]; 6712 u8 reserved_0[0x10]; 6713 6714 u8 reserved_1[0x10]; 6715 u8 op_mod[0x10]; 6716 6717 u8 reserved_2[0x8]; 6718 u8 pd[0x18]; 6719 6720 u8 reserved_3[0x20]; 6721 }; 6722 6723 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6724 u8 status[0x8]; 6725 u8 reserved_0[0x18]; 6726 6727 u8 syndrome[0x20]; 6728 6729 u8 reserved_1[0x40]; 6730 }; 6731 6732 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6733 u8 opcode[0x10]; 6734 u8 reserved_0[0x10]; 6735 6736 u8 reserved_1[0x10]; 6737 u8 op_mod[0x10]; 6738 6739 u8 reserved_2[0x10]; 6740 u8 flow_counter_id[0x10]; 6741 6742 u8 reserved_3[0x20]; 6743 }; 6744 6745 struct mlx5_ifc_deactivate_tracer_out_bits { 6746 u8 status[0x8]; 6747 u8 reserved_0[0x18]; 6748 6749 u8 syndrome[0x20]; 6750 6751 u8 reserved_1[0x40]; 6752 }; 6753 6754 struct mlx5_ifc_deactivate_tracer_in_bits { 6755 u8 opcode[0x10]; 6756 u8 reserved_0[0x10]; 6757 6758 u8 reserved_1[0x10]; 6759 u8 op_mod[0x10]; 6760 6761 u8 mkey[0x20]; 6762 6763 u8 reserved_2[0x20]; 6764 }; 6765 6766 struct mlx5_ifc_create_xrc_srq_out_bits { 6767 u8 status[0x8]; 6768 u8 reserved_0[0x18]; 6769 6770 u8 syndrome[0x20]; 6771 6772 u8 reserved_1[0x8]; 6773 u8 xrc_srqn[0x18]; 6774 6775 u8 reserved_2[0x20]; 6776 }; 6777 6778 struct mlx5_ifc_create_xrc_srq_in_bits { 6779 u8 opcode[0x10]; 6780 u8 reserved_0[0x10]; 6781 6782 u8 reserved_1[0x10]; 6783 u8 op_mod[0x10]; 6784 6785 u8 reserved_2[0x40]; 6786 6787 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6788 6789 u8 reserved_3[0x600]; 6790 6791 u8 pas[0][0x40]; 6792 }; 6793 6794 struct mlx5_ifc_create_tis_out_bits { 6795 u8 status[0x8]; 6796 u8 reserved_0[0x18]; 6797 6798 u8 syndrome[0x20]; 6799 6800 u8 reserved_1[0x8]; 6801 u8 tisn[0x18]; 6802 6803 u8 reserved_2[0x20]; 6804 }; 6805 6806 struct mlx5_ifc_create_tis_in_bits { 6807 u8 opcode[0x10]; 6808 u8 reserved_0[0x10]; 6809 6810 u8 reserved_1[0x10]; 6811 u8 op_mod[0x10]; 6812 6813 u8 reserved_2[0xc0]; 6814 6815 struct mlx5_ifc_tisc_bits ctx; 6816 }; 6817 6818 struct mlx5_ifc_create_tir_out_bits { 6819 u8 status[0x8]; 6820 u8 reserved_0[0x18]; 6821 6822 u8 syndrome[0x20]; 6823 6824 u8 reserved_1[0x8]; 6825 u8 tirn[0x18]; 6826 6827 u8 reserved_2[0x20]; 6828 }; 6829 6830 struct mlx5_ifc_create_tir_in_bits { 6831 u8 opcode[0x10]; 6832 u8 reserved_0[0x10]; 6833 6834 u8 reserved_1[0x10]; 6835 u8 op_mod[0x10]; 6836 6837 u8 reserved_2[0xc0]; 6838 6839 struct mlx5_ifc_tirc_bits tir_context; 6840 }; 6841 6842 struct mlx5_ifc_create_srq_out_bits { 6843 u8 status[0x8]; 6844 u8 reserved_0[0x18]; 6845 6846 u8 syndrome[0x20]; 6847 6848 u8 reserved_1[0x8]; 6849 u8 srqn[0x18]; 6850 6851 u8 reserved_2[0x20]; 6852 }; 6853 6854 struct mlx5_ifc_create_srq_in_bits { 6855 u8 opcode[0x10]; 6856 u8 reserved_0[0x10]; 6857 6858 u8 reserved_1[0x10]; 6859 u8 op_mod[0x10]; 6860 6861 u8 reserved_2[0x40]; 6862 6863 struct mlx5_ifc_srqc_bits srq_context_entry; 6864 6865 u8 reserved_3[0x600]; 6866 6867 u8 pas[0][0x40]; 6868 }; 6869 6870 struct mlx5_ifc_create_sq_out_bits { 6871 u8 status[0x8]; 6872 u8 reserved_0[0x18]; 6873 6874 u8 syndrome[0x20]; 6875 6876 u8 reserved_1[0x8]; 6877 u8 sqn[0x18]; 6878 6879 u8 reserved_2[0x20]; 6880 }; 6881 6882 struct mlx5_ifc_create_sq_in_bits { 6883 u8 opcode[0x10]; 6884 u8 reserved_0[0x10]; 6885 6886 u8 reserved_1[0x10]; 6887 u8 op_mod[0x10]; 6888 6889 u8 reserved_2[0xc0]; 6890 6891 struct mlx5_ifc_sqc_bits ctx; 6892 }; 6893 6894 struct mlx5_ifc_create_scheduling_element_out_bits { 6895 u8 status[0x8]; 6896 u8 reserved_at_8[0x18]; 6897 6898 u8 syndrome[0x20]; 6899 6900 u8 reserved_at_40[0x40]; 6901 6902 u8 scheduling_element_id[0x20]; 6903 6904 u8 reserved_at_a0[0x160]; 6905 }; 6906 6907 enum { 6908 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6909 }; 6910 6911 struct mlx5_ifc_create_scheduling_element_in_bits { 6912 u8 opcode[0x10]; 6913 u8 reserved_at_10[0x10]; 6914 6915 u8 reserved_at_20[0x10]; 6916 u8 op_mod[0x10]; 6917 6918 u8 scheduling_hierarchy[0x8]; 6919 u8 reserved_at_48[0x18]; 6920 6921 u8 reserved_at_60[0xa0]; 6922 6923 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6924 6925 u8 reserved_at_300[0x100]; 6926 }; 6927 6928 struct mlx5_ifc_create_rqt_out_bits { 6929 u8 status[0x8]; 6930 u8 reserved_0[0x18]; 6931 6932 u8 syndrome[0x20]; 6933 6934 u8 reserved_1[0x8]; 6935 u8 rqtn[0x18]; 6936 6937 u8 reserved_2[0x20]; 6938 }; 6939 6940 struct mlx5_ifc_create_rqt_in_bits { 6941 u8 opcode[0x10]; 6942 u8 reserved_0[0x10]; 6943 6944 u8 reserved_1[0x10]; 6945 u8 op_mod[0x10]; 6946 6947 u8 reserved_2[0xc0]; 6948 6949 struct mlx5_ifc_rqtc_bits rqt_context; 6950 }; 6951 6952 struct mlx5_ifc_create_rq_out_bits { 6953 u8 status[0x8]; 6954 u8 reserved_0[0x18]; 6955 6956 u8 syndrome[0x20]; 6957 6958 u8 reserved_1[0x8]; 6959 u8 rqn[0x18]; 6960 6961 u8 reserved_2[0x20]; 6962 }; 6963 6964 struct mlx5_ifc_create_rq_in_bits { 6965 u8 opcode[0x10]; 6966 u8 reserved_0[0x10]; 6967 6968 u8 reserved_1[0x10]; 6969 u8 op_mod[0x10]; 6970 6971 u8 reserved_2[0xc0]; 6972 6973 struct mlx5_ifc_rqc_bits ctx; 6974 }; 6975 6976 struct mlx5_ifc_create_rmp_out_bits { 6977 u8 status[0x8]; 6978 u8 reserved_0[0x18]; 6979 6980 u8 syndrome[0x20]; 6981 6982 u8 reserved_1[0x8]; 6983 u8 rmpn[0x18]; 6984 6985 u8 reserved_2[0x20]; 6986 }; 6987 6988 struct mlx5_ifc_create_rmp_in_bits { 6989 u8 opcode[0x10]; 6990 u8 reserved_0[0x10]; 6991 6992 u8 reserved_1[0x10]; 6993 u8 op_mod[0x10]; 6994 6995 u8 reserved_2[0xc0]; 6996 6997 struct mlx5_ifc_rmpc_bits ctx; 6998 }; 6999 7000 struct mlx5_ifc_create_qp_out_bits { 7001 u8 status[0x8]; 7002 u8 reserved_0[0x18]; 7003 7004 u8 syndrome[0x20]; 7005 7006 u8 reserved_1[0x8]; 7007 u8 qpn[0x18]; 7008 7009 u8 reserved_2[0x20]; 7010 }; 7011 7012 struct mlx5_ifc_create_qp_in_bits { 7013 u8 opcode[0x10]; 7014 u8 reserved_0[0x10]; 7015 7016 u8 reserved_1[0x10]; 7017 u8 op_mod[0x10]; 7018 7019 u8 reserved_2[0x8]; 7020 u8 input_qpn[0x18]; 7021 7022 u8 reserved_3[0x20]; 7023 7024 u8 opt_param_mask[0x20]; 7025 7026 u8 reserved_4[0x20]; 7027 7028 struct mlx5_ifc_qpc_bits qpc; 7029 7030 u8 reserved_5[0x80]; 7031 7032 u8 pas[0][0x40]; 7033 }; 7034 7035 struct mlx5_ifc_create_qos_para_vport_out_bits { 7036 u8 status[0x8]; 7037 u8 reserved_at_8[0x18]; 7038 7039 u8 syndrome[0x20]; 7040 7041 u8 reserved_at_40[0x20]; 7042 7043 u8 reserved_at_60[0x10]; 7044 u8 qos_para_vport_number[0x10]; 7045 7046 u8 reserved_at_80[0x180]; 7047 }; 7048 7049 struct mlx5_ifc_create_qos_para_vport_in_bits { 7050 u8 opcode[0x10]; 7051 u8 reserved_at_10[0x10]; 7052 7053 u8 reserved_at_20[0x10]; 7054 u8 op_mod[0x10]; 7055 7056 u8 reserved_at_40[0x1c0]; 7057 }; 7058 7059 struct mlx5_ifc_create_psv_out_bits { 7060 u8 status[0x8]; 7061 u8 reserved_0[0x18]; 7062 7063 u8 syndrome[0x20]; 7064 7065 u8 reserved_1[0x40]; 7066 7067 u8 reserved_2[0x8]; 7068 u8 psv0_index[0x18]; 7069 7070 u8 reserved_3[0x8]; 7071 u8 psv1_index[0x18]; 7072 7073 u8 reserved_4[0x8]; 7074 u8 psv2_index[0x18]; 7075 7076 u8 reserved_5[0x8]; 7077 u8 psv3_index[0x18]; 7078 }; 7079 7080 struct mlx5_ifc_create_psv_in_bits { 7081 u8 opcode[0x10]; 7082 u8 reserved_0[0x10]; 7083 7084 u8 reserved_1[0x10]; 7085 u8 op_mod[0x10]; 7086 7087 u8 num_psv[0x4]; 7088 u8 reserved_2[0x4]; 7089 u8 pd[0x18]; 7090 7091 u8 reserved_3[0x20]; 7092 }; 7093 7094 struct mlx5_ifc_create_mkey_out_bits { 7095 u8 status[0x8]; 7096 u8 reserved_0[0x18]; 7097 7098 u8 syndrome[0x20]; 7099 7100 u8 reserved_1[0x8]; 7101 u8 mkey_index[0x18]; 7102 7103 u8 reserved_2[0x20]; 7104 }; 7105 7106 struct mlx5_ifc_create_mkey_in_bits { 7107 u8 opcode[0x10]; 7108 u8 reserved_0[0x10]; 7109 7110 u8 reserved_1[0x10]; 7111 u8 op_mod[0x10]; 7112 7113 u8 reserved_2[0x20]; 7114 7115 u8 pg_access[0x1]; 7116 u8 reserved_3[0x1f]; 7117 7118 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7119 7120 u8 reserved_4[0x80]; 7121 7122 u8 translations_octword_actual_size[0x20]; 7123 7124 u8 reserved_5[0x560]; 7125 7126 u8 klm_pas_mtt[0][0x20]; 7127 }; 7128 7129 struct mlx5_ifc_create_flow_table_out_bits { 7130 u8 status[0x8]; 7131 u8 reserved_0[0x18]; 7132 7133 u8 syndrome[0x20]; 7134 7135 u8 reserved_1[0x8]; 7136 u8 table_id[0x18]; 7137 7138 u8 reserved_2[0x20]; 7139 }; 7140 7141 struct mlx5_ifc_create_flow_table_in_bits { 7142 u8 opcode[0x10]; 7143 u8 reserved_at_10[0x10]; 7144 7145 u8 reserved_at_20[0x10]; 7146 u8 op_mod[0x10]; 7147 7148 u8 other_vport[0x1]; 7149 u8 reserved_at_41[0xf]; 7150 u8 vport_number[0x10]; 7151 7152 u8 reserved_at_60[0x20]; 7153 7154 u8 table_type[0x8]; 7155 u8 reserved_at_88[0x18]; 7156 7157 u8 reserved_at_a0[0x20]; 7158 7159 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7160 }; 7161 7162 struct mlx5_ifc_create_flow_group_out_bits { 7163 u8 status[0x8]; 7164 u8 reserved_0[0x18]; 7165 7166 u8 syndrome[0x20]; 7167 7168 u8 reserved_1[0x8]; 7169 u8 group_id[0x18]; 7170 7171 u8 reserved_2[0x20]; 7172 }; 7173 7174 enum { 7175 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7176 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7177 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7178 }; 7179 7180 struct mlx5_ifc_create_flow_group_in_bits { 7181 u8 opcode[0x10]; 7182 u8 reserved_0[0x10]; 7183 7184 u8 reserved_1[0x10]; 7185 u8 op_mod[0x10]; 7186 7187 u8 other_vport[0x1]; 7188 u8 reserved_2[0xf]; 7189 u8 vport_number[0x10]; 7190 7191 u8 reserved_3[0x20]; 7192 7193 u8 table_type[0x8]; 7194 u8 reserved_4[0x18]; 7195 7196 u8 reserved_5[0x8]; 7197 u8 table_id[0x18]; 7198 7199 u8 reserved_6[0x20]; 7200 7201 u8 start_flow_index[0x20]; 7202 7203 u8 reserved_7[0x20]; 7204 7205 u8 end_flow_index[0x20]; 7206 7207 u8 reserved_8[0xa0]; 7208 7209 u8 reserved_9[0x18]; 7210 u8 match_criteria_enable[0x8]; 7211 7212 struct mlx5_ifc_fte_match_param_bits match_criteria; 7213 7214 u8 reserved_10[0xe00]; 7215 }; 7216 7217 struct mlx5_ifc_create_eq_out_bits { 7218 u8 status[0x8]; 7219 u8 reserved_0[0x18]; 7220 7221 u8 syndrome[0x20]; 7222 7223 u8 reserved_1[0x18]; 7224 u8 eq_number[0x8]; 7225 7226 u8 reserved_2[0x20]; 7227 }; 7228 7229 struct mlx5_ifc_create_eq_in_bits { 7230 u8 opcode[0x10]; 7231 u8 reserved_0[0x10]; 7232 7233 u8 reserved_1[0x10]; 7234 u8 op_mod[0x10]; 7235 7236 u8 reserved_2[0x40]; 7237 7238 struct mlx5_ifc_eqc_bits eq_context_entry; 7239 7240 u8 reserved_3[0x40]; 7241 7242 u8 event_bitmask[0x40]; 7243 7244 u8 reserved_4[0x580]; 7245 7246 u8 pas[0][0x40]; 7247 }; 7248 7249 struct mlx5_ifc_create_dct_out_bits { 7250 u8 status[0x8]; 7251 u8 reserved_0[0x18]; 7252 7253 u8 syndrome[0x20]; 7254 7255 u8 reserved_1[0x8]; 7256 u8 dctn[0x18]; 7257 7258 u8 reserved_2[0x20]; 7259 }; 7260 7261 struct mlx5_ifc_create_dct_in_bits { 7262 u8 opcode[0x10]; 7263 u8 reserved_0[0x10]; 7264 7265 u8 reserved_1[0x10]; 7266 u8 op_mod[0x10]; 7267 7268 u8 reserved_2[0x40]; 7269 7270 struct mlx5_ifc_dctc_bits dct_context_entry; 7271 7272 u8 reserved_3[0x180]; 7273 }; 7274 7275 struct mlx5_ifc_create_cq_out_bits { 7276 u8 status[0x8]; 7277 u8 reserved_0[0x18]; 7278 7279 u8 syndrome[0x20]; 7280 7281 u8 reserved_1[0x8]; 7282 u8 cqn[0x18]; 7283 7284 u8 reserved_2[0x20]; 7285 }; 7286 7287 struct mlx5_ifc_create_cq_in_bits { 7288 u8 opcode[0x10]; 7289 u8 reserved_0[0x10]; 7290 7291 u8 reserved_1[0x10]; 7292 u8 op_mod[0x10]; 7293 7294 u8 reserved_2[0x40]; 7295 7296 struct mlx5_ifc_cqc_bits cq_context; 7297 7298 u8 reserved_3[0x600]; 7299 7300 u8 pas[0][0x40]; 7301 }; 7302 7303 struct mlx5_ifc_config_int_moderation_out_bits { 7304 u8 status[0x8]; 7305 u8 reserved_0[0x18]; 7306 7307 u8 syndrome[0x20]; 7308 7309 u8 reserved_1[0x4]; 7310 u8 min_delay[0xc]; 7311 u8 int_vector[0x10]; 7312 7313 u8 reserved_2[0x20]; 7314 }; 7315 7316 enum { 7317 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7318 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7319 }; 7320 7321 struct mlx5_ifc_config_int_moderation_in_bits { 7322 u8 opcode[0x10]; 7323 u8 reserved_0[0x10]; 7324 7325 u8 reserved_1[0x10]; 7326 u8 op_mod[0x10]; 7327 7328 u8 reserved_2[0x4]; 7329 u8 min_delay[0xc]; 7330 u8 int_vector[0x10]; 7331 7332 u8 reserved_3[0x20]; 7333 }; 7334 7335 struct mlx5_ifc_attach_to_mcg_out_bits { 7336 u8 status[0x8]; 7337 u8 reserved_0[0x18]; 7338 7339 u8 syndrome[0x20]; 7340 7341 u8 reserved_1[0x40]; 7342 }; 7343 7344 struct mlx5_ifc_attach_to_mcg_in_bits { 7345 u8 opcode[0x10]; 7346 u8 reserved_0[0x10]; 7347 7348 u8 reserved_1[0x10]; 7349 u8 op_mod[0x10]; 7350 7351 u8 reserved_2[0x8]; 7352 u8 qpn[0x18]; 7353 7354 u8 reserved_3[0x20]; 7355 7356 u8 multicast_gid[16][0x8]; 7357 }; 7358 7359 struct mlx5_ifc_arm_xrc_srq_out_bits { 7360 u8 status[0x8]; 7361 u8 reserved_0[0x18]; 7362 7363 u8 syndrome[0x20]; 7364 7365 u8 reserved_1[0x40]; 7366 }; 7367 7368 enum { 7369 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7370 }; 7371 7372 struct mlx5_ifc_arm_xrc_srq_in_bits { 7373 u8 opcode[0x10]; 7374 u8 reserved_0[0x10]; 7375 7376 u8 reserved_1[0x10]; 7377 u8 op_mod[0x10]; 7378 7379 u8 reserved_2[0x8]; 7380 u8 xrc_srqn[0x18]; 7381 7382 u8 reserved_3[0x10]; 7383 u8 lwm[0x10]; 7384 }; 7385 7386 struct mlx5_ifc_arm_rq_out_bits { 7387 u8 status[0x8]; 7388 u8 reserved_0[0x18]; 7389 7390 u8 syndrome[0x20]; 7391 7392 u8 reserved_1[0x40]; 7393 }; 7394 7395 enum { 7396 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7397 }; 7398 7399 struct mlx5_ifc_arm_rq_in_bits { 7400 u8 opcode[0x10]; 7401 u8 reserved_0[0x10]; 7402 7403 u8 reserved_1[0x10]; 7404 u8 op_mod[0x10]; 7405 7406 u8 reserved_2[0x8]; 7407 u8 srq_number[0x18]; 7408 7409 u8 reserved_3[0x10]; 7410 u8 lwm[0x10]; 7411 }; 7412 7413 struct mlx5_ifc_arm_dct_out_bits { 7414 u8 status[0x8]; 7415 u8 reserved_0[0x18]; 7416 7417 u8 syndrome[0x20]; 7418 7419 u8 reserved_1[0x40]; 7420 }; 7421 7422 struct mlx5_ifc_arm_dct_in_bits { 7423 u8 opcode[0x10]; 7424 u8 reserved_0[0x10]; 7425 7426 u8 reserved_1[0x10]; 7427 u8 op_mod[0x10]; 7428 7429 u8 reserved_2[0x8]; 7430 u8 dctn[0x18]; 7431 7432 u8 reserved_3[0x20]; 7433 }; 7434 7435 struct mlx5_ifc_alloc_xrcd_out_bits { 7436 u8 status[0x8]; 7437 u8 reserved_0[0x18]; 7438 7439 u8 syndrome[0x20]; 7440 7441 u8 reserved_1[0x8]; 7442 u8 xrcd[0x18]; 7443 7444 u8 reserved_2[0x20]; 7445 }; 7446 7447 struct mlx5_ifc_alloc_xrcd_in_bits { 7448 u8 opcode[0x10]; 7449 u8 reserved_0[0x10]; 7450 7451 u8 reserved_1[0x10]; 7452 u8 op_mod[0x10]; 7453 7454 u8 reserved_2[0x40]; 7455 }; 7456 7457 struct mlx5_ifc_alloc_uar_out_bits { 7458 u8 status[0x8]; 7459 u8 reserved_0[0x18]; 7460 7461 u8 syndrome[0x20]; 7462 7463 u8 reserved_1[0x8]; 7464 u8 uar[0x18]; 7465 7466 u8 reserved_2[0x20]; 7467 }; 7468 7469 struct mlx5_ifc_alloc_uar_in_bits { 7470 u8 opcode[0x10]; 7471 u8 reserved_0[0x10]; 7472 7473 u8 reserved_1[0x10]; 7474 u8 op_mod[0x10]; 7475 7476 u8 reserved_2[0x40]; 7477 }; 7478 7479 struct mlx5_ifc_alloc_transport_domain_out_bits { 7480 u8 status[0x8]; 7481 u8 reserved_0[0x18]; 7482 7483 u8 syndrome[0x20]; 7484 7485 u8 reserved_1[0x8]; 7486 u8 transport_domain[0x18]; 7487 7488 u8 reserved_2[0x20]; 7489 }; 7490 7491 struct mlx5_ifc_alloc_transport_domain_in_bits { 7492 u8 opcode[0x10]; 7493 u8 reserved_0[0x10]; 7494 7495 u8 reserved_1[0x10]; 7496 u8 op_mod[0x10]; 7497 7498 u8 reserved_2[0x40]; 7499 }; 7500 7501 struct mlx5_ifc_alloc_q_counter_out_bits { 7502 u8 status[0x8]; 7503 u8 reserved_0[0x18]; 7504 7505 u8 syndrome[0x20]; 7506 7507 u8 reserved_1[0x18]; 7508 u8 counter_set_id[0x8]; 7509 7510 u8 reserved_2[0x20]; 7511 }; 7512 7513 struct mlx5_ifc_alloc_q_counter_in_bits { 7514 u8 opcode[0x10]; 7515 u8 reserved_0[0x10]; 7516 7517 u8 reserved_1[0x10]; 7518 u8 op_mod[0x10]; 7519 7520 u8 reserved_2[0x40]; 7521 }; 7522 7523 struct mlx5_ifc_alloc_pd_out_bits { 7524 u8 status[0x8]; 7525 u8 reserved_0[0x18]; 7526 7527 u8 syndrome[0x20]; 7528 7529 u8 reserved_1[0x8]; 7530 u8 pd[0x18]; 7531 7532 u8 reserved_2[0x20]; 7533 }; 7534 7535 struct mlx5_ifc_alloc_pd_in_bits { 7536 u8 opcode[0x10]; 7537 u8 reserved_0[0x10]; 7538 7539 u8 reserved_1[0x10]; 7540 u8 op_mod[0x10]; 7541 7542 u8 reserved_2[0x40]; 7543 }; 7544 7545 struct mlx5_ifc_alloc_flow_counter_out_bits { 7546 u8 status[0x8]; 7547 u8 reserved_0[0x18]; 7548 7549 u8 syndrome[0x20]; 7550 7551 u8 reserved_1[0x10]; 7552 u8 flow_counter_id[0x10]; 7553 7554 u8 reserved_2[0x20]; 7555 }; 7556 7557 struct mlx5_ifc_alloc_flow_counter_in_bits { 7558 u8 opcode[0x10]; 7559 u8 reserved_0[0x10]; 7560 7561 u8 reserved_1[0x10]; 7562 u8 op_mod[0x10]; 7563 7564 u8 reserved_2[0x40]; 7565 }; 7566 7567 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7568 u8 status[0x8]; 7569 u8 reserved_0[0x18]; 7570 7571 u8 syndrome[0x20]; 7572 7573 u8 reserved_1[0x40]; 7574 }; 7575 7576 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7577 u8 opcode[0x10]; 7578 u8 reserved_0[0x10]; 7579 7580 u8 reserved_1[0x10]; 7581 u8 op_mod[0x10]; 7582 7583 u8 reserved_2[0x20]; 7584 7585 u8 reserved_3[0x10]; 7586 u8 vxlan_udp_port[0x10]; 7587 }; 7588 7589 struct mlx5_ifc_activate_tracer_out_bits { 7590 u8 status[0x8]; 7591 u8 reserved_0[0x18]; 7592 7593 u8 syndrome[0x20]; 7594 7595 u8 reserved_1[0x40]; 7596 }; 7597 7598 struct mlx5_ifc_activate_tracer_in_bits { 7599 u8 opcode[0x10]; 7600 u8 reserved_0[0x10]; 7601 7602 u8 reserved_1[0x10]; 7603 u8 op_mod[0x10]; 7604 7605 u8 mkey[0x20]; 7606 7607 u8 reserved_2[0x20]; 7608 }; 7609 7610 struct mlx5_ifc_set_rate_limit_out_bits { 7611 u8 status[0x8]; 7612 u8 reserved_at_8[0x18]; 7613 7614 u8 syndrome[0x20]; 7615 7616 u8 reserved_at_40[0x40]; 7617 }; 7618 7619 struct mlx5_ifc_set_rate_limit_in_bits { 7620 u8 opcode[0x10]; 7621 u8 reserved_at_10[0x10]; 7622 7623 u8 reserved_at_20[0x10]; 7624 u8 op_mod[0x10]; 7625 7626 u8 reserved_at_40[0x10]; 7627 u8 rate_limit_index[0x10]; 7628 7629 u8 reserved_at_60[0x20]; 7630 7631 u8 rate_limit[0x20]; 7632 u8 burst_upper_bound[0x20]; 7633 }; 7634 7635 struct mlx5_ifc_access_register_out_bits { 7636 u8 status[0x8]; 7637 u8 reserved_0[0x18]; 7638 7639 u8 syndrome[0x20]; 7640 7641 u8 reserved_1[0x40]; 7642 7643 u8 register_data[0][0x20]; 7644 }; 7645 7646 enum { 7647 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7648 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7649 }; 7650 7651 struct mlx5_ifc_access_register_in_bits { 7652 u8 opcode[0x10]; 7653 u8 reserved_0[0x10]; 7654 7655 u8 reserved_1[0x10]; 7656 u8 op_mod[0x10]; 7657 7658 u8 reserved_2[0x10]; 7659 u8 register_id[0x10]; 7660 7661 u8 argument[0x20]; 7662 7663 u8 register_data[0][0x20]; 7664 }; 7665 7666 struct mlx5_ifc_sltp_reg_bits { 7667 u8 status[0x4]; 7668 u8 version[0x4]; 7669 u8 local_port[0x8]; 7670 u8 pnat[0x2]; 7671 u8 reserved_0[0x2]; 7672 u8 lane[0x4]; 7673 u8 reserved_1[0x8]; 7674 7675 u8 reserved_2[0x20]; 7676 7677 u8 reserved_3[0x7]; 7678 u8 polarity[0x1]; 7679 u8 ob_tap0[0x8]; 7680 u8 ob_tap1[0x8]; 7681 u8 ob_tap2[0x8]; 7682 7683 u8 reserved_4[0xc]; 7684 u8 ob_preemp_mode[0x4]; 7685 u8 ob_reg[0x8]; 7686 u8 ob_bias[0x8]; 7687 7688 u8 reserved_5[0x20]; 7689 }; 7690 7691 struct mlx5_ifc_slrp_reg_bits { 7692 u8 status[0x4]; 7693 u8 version[0x4]; 7694 u8 local_port[0x8]; 7695 u8 pnat[0x2]; 7696 u8 reserved_0[0x2]; 7697 u8 lane[0x4]; 7698 u8 reserved_1[0x8]; 7699 7700 u8 ib_sel[0x2]; 7701 u8 reserved_2[0x11]; 7702 u8 dp_sel[0x1]; 7703 u8 dp90sel[0x4]; 7704 u8 mix90phase[0x8]; 7705 7706 u8 ffe_tap0[0x8]; 7707 u8 ffe_tap1[0x8]; 7708 u8 ffe_tap2[0x8]; 7709 u8 ffe_tap3[0x8]; 7710 7711 u8 ffe_tap4[0x8]; 7712 u8 ffe_tap5[0x8]; 7713 u8 ffe_tap6[0x8]; 7714 u8 ffe_tap7[0x8]; 7715 7716 u8 ffe_tap8[0x8]; 7717 u8 mixerbias_tap_amp[0x8]; 7718 u8 reserved_3[0x7]; 7719 u8 ffe_tap_en[0x9]; 7720 7721 u8 ffe_tap_offset0[0x8]; 7722 u8 ffe_tap_offset1[0x8]; 7723 u8 slicer_offset0[0x10]; 7724 7725 u8 mixer_offset0[0x10]; 7726 u8 mixer_offset1[0x10]; 7727 7728 u8 mixerbgn_inp[0x8]; 7729 u8 mixerbgn_inn[0x8]; 7730 u8 mixerbgn_refp[0x8]; 7731 u8 mixerbgn_refn[0x8]; 7732 7733 u8 sel_slicer_lctrl_h[0x1]; 7734 u8 sel_slicer_lctrl_l[0x1]; 7735 u8 reserved_4[0x1]; 7736 u8 ref_mixer_vreg[0x5]; 7737 u8 slicer_gctrl[0x8]; 7738 u8 lctrl_input[0x8]; 7739 u8 mixer_offset_cm1[0x8]; 7740 7741 u8 common_mode[0x6]; 7742 u8 reserved_5[0x1]; 7743 u8 mixer_offset_cm0[0x9]; 7744 u8 reserved_6[0x7]; 7745 u8 slicer_offset_cm[0x9]; 7746 }; 7747 7748 struct mlx5_ifc_slrg_reg_bits { 7749 u8 status[0x4]; 7750 u8 version[0x4]; 7751 u8 local_port[0x8]; 7752 u8 pnat[0x2]; 7753 u8 reserved_0[0x2]; 7754 u8 lane[0x4]; 7755 u8 reserved_1[0x8]; 7756 7757 u8 time_to_link_up[0x10]; 7758 u8 reserved_2[0xc]; 7759 u8 grade_lane_speed[0x4]; 7760 7761 u8 grade_version[0x8]; 7762 u8 grade[0x18]; 7763 7764 u8 reserved_3[0x4]; 7765 u8 height_grade_type[0x4]; 7766 u8 height_grade[0x18]; 7767 7768 u8 height_dz[0x10]; 7769 u8 height_dv[0x10]; 7770 7771 u8 reserved_4[0x10]; 7772 u8 height_sigma[0x10]; 7773 7774 u8 reserved_5[0x20]; 7775 7776 u8 reserved_6[0x4]; 7777 u8 phase_grade_type[0x4]; 7778 u8 phase_grade[0x18]; 7779 7780 u8 reserved_7[0x8]; 7781 u8 phase_eo_pos[0x8]; 7782 u8 reserved_8[0x8]; 7783 u8 phase_eo_neg[0x8]; 7784 7785 u8 ffe_set_tested[0x10]; 7786 u8 test_errors_per_lane[0x10]; 7787 }; 7788 7789 struct mlx5_ifc_pvlc_reg_bits { 7790 u8 reserved_0[0x8]; 7791 u8 local_port[0x8]; 7792 u8 reserved_1[0x10]; 7793 7794 u8 reserved_2[0x1c]; 7795 u8 vl_hw_cap[0x4]; 7796 7797 u8 reserved_3[0x1c]; 7798 u8 vl_admin[0x4]; 7799 7800 u8 reserved_4[0x1c]; 7801 u8 vl_operational[0x4]; 7802 }; 7803 7804 struct mlx5_ifc_pude_reg_bits { 7805 u8 swid[0x8]; 7806 u8 local_port[0x8]; 7807 u8 reserved_0[0x4]; 7808 u8 admin_status[0x4]; 7809 u8 reserved_1[0x4]; 7810 u8 oper_status[0x4]; 7811 7812 u8 reserved_2[0x60]; 7813 }; 7814 7815 enum { 7816 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 7817 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 7818 }; 7819 7820 struct mlx5_ifc_ptys_reg_bits { 7821 u8 reserved_0[0x1]; 7822 u8 an_disable_admin[0x1]; 7823 u8 an_disable_cap[0x1]; 7824 u8 reserved_1[0x4]; 7825 u8 force_tx_aba_param[0x1]; 7826 u8 local_port[0x8]; 7827 u8 reserved_2[0xd]; 7828 u8 proto_mask[0x3]; 7829 7830 u8 an_status[0x4]; 7831 u8 reserved_3[0xc]; 7832 u8 data_rate_oper[0x10]; 7833 7834 u8 fc_proto_capability[0x20]; 7835 7836 u8 eth_proto_capability[0x20]; 7837 7838 u8 ib_link_width_capability[0x10]; 7839 u8 ib_proto_capability[0x10]; 7840 7841 u8 fc_proto_admin[0x20]; 7842 7843 u8 eth_proto_admin[0x20]; 7844 7845 u8 ib_link_width_admin[0x10]; 7846 u8 ib_proto_admin[0x10]; 7847 7848 u8 fc_proto_oper[0x20]; 7849 7850 u8 eth_proto_oper[0x20]; 7851 7852 u8 ib_link_width_oper[0x10]; 7853 u8 ib_proto_oper[0x10]; 7854 7855 u8 reserved_4[0x20]; 7856 7857 u8 eth_proto_lp_advertise[0x20]; 7858 7859 u8 reserved_5[0x60]; 7860 }; 7861 7862 struct mlx5_ifc_ptas_reg_bits { 7863 u8 reserved_0[0x20]; 7864 7865 u8 algorithm_options[0x10]; 7866 u8 reserved_1[0x4]; 7867 u8 repetitions_mode[0x4]; 7868 u8 num_of_repetitions[0x8]; 7869 7870 u8 grade_version[0x8]; 7871 u8 height_grade_type[0x4]; 7872 u8 phase_grade_type[0x4]; 7873 u8 height_grade_weight[0x8]; 7874 u8 phase_grade_weight[0x8]; 7875 7876 u8 gisim_measure_bits[0x10]; 7877 u8 adaptive_tap_measure_bits[0x10]; 7878 7879 u8 ber_bath_high_error_threshold[0x10]; 7880 u8 ber_bath_mid_error_threshold[0x10]; 7881 7882 u8 ber_bath_low_error_threshold[0x10]; 7883 u8 one_ratio_high_threshold[0x10]; 7884 7885 u8 one_ratio_high_mid_threshold[0x10]; 7886 u8 one_ratio_low_mid_threshold[0x10]; 7887 7888 u8 one_ratio_low_threshold[0x10]; 7889 u8 ndeo_error_threshold[0x10]; 7890 7891 u8 mixer_offset_step_size[0x10]; 7892 u8 reserved_2[0x8]; 7893 u8 mix90_phase_for_voltage_bath[0x8]; 7894 7895 u8 mixer_offset_start[0x10]; 7896 u8 mixer_offset_end[0x10]; 7897 7898 u8 reserved_3[0x15]; 7899 u8 ber_test_time[0xb]; 7900 }; 7901 7902 struct mlx5_ifc_pspa_reg_bits { 7903 u8 swid[0x8]; 7904 u8 local_port[0x8]; 7905 u8 sub_port[0x8]; 7906 u8 reserved_0[0x8]; 7907 7908 u8 reserved_1[0x20]; 7909 }; 7910 7911 struct mlx5_ifc_ppsc_reg_bits { 7912 u8 reserved_0[0x8]; 7913 u8 local_port[0x8]; 7914 u8 reserved_1[0x10]; 7915 7916 u8 reserved_2[0x60]; 7917 7918 u8 reserved_3[0x1c]; 7919 u8 wrps_admin[0x4]; 7920 7921 u8 reserved_4[0x1c]; 7922 u8 wrps_status[0x4]; 7923 7924 u8 up_th_vld[0x1]; 7925 u8 down_th_vld[0x1]; 7926 u8 reserved_5[0x6]; 7927 u8 up_threshold[0x8]; 7928 u8 reserved_6[0x8]; 7929 u8 down_threshold[0x8]; 7930 7931 u8 reserved_7[0x20]; 7932 7933 u8 reserved_8[0x1c]; 7934 u8 srps_admin[0x4]; 7935 7936 u8 reserved_9[0x60]; 7937 }; 7938 7939 struct mlx5_ifc_pplr_reg_bits { 7940 u8 reserved_0[0x8]; 7941 u8 local_port[0x8]; 7942 u8 reserved_1[0x10]; 7943 7944 u8 reserved_2[0x8]; 7945 u8 lb_cap[0x8]; 7946 u8 reserved_3[0x8]; 7947 u8 lb_en[0x8]; 7948 }; 7949 7950 struct mlx5_ifc_pplm_reg_bits { 7951 u8 reserved_0[0x8]; 7952 u8 local_port[0x8]; 7953 u8 reserved_1[0x10]; 7954 7955 u8 reserved_2[0x20]; 7956 7957 u8 port_profile_mode[0x8]; 7958 u8 static_port_profile[0x8]; 7959 u8 active_port_profile[0x8]; 7960 u8 reserved_3[0x8]; 7961 7962 u8 retransmission_active[0x8]; 7963 u8 fec_mode_active[0x18]; 7964 7965 u8 reserved_4[0x10]; 7966 u8 v_100g_fec_override_cap[0x4]; 7967 u8 v_50g_fec_override_cap[0x4]; 7968 u8 v_25g_fec_override_cap[0x4]; 7969 u8 v_10g_40g_fec_override_cap[0x4]; 7970 7971 u8 reserved_5[0x10]; 7972 u8 v_100g_fec_override_admin[0x4]; 7973 u8 v_50g_fec_override_admin[0x4]; 7974 u8 v_25g_fec_override_admin[0x4]; 7975 u8 v_10g_40g_fec_override_admin[0x4]; 7976 }; 7977 7978 struct mlx5_ifc_ppll_reg_bits { 7979 u8 num_pll_groups[0x8]; 7980 u8 pll_group[0x8]; 7981 u8 reserved_0[0x4]; 7982 u8 num_plls[0x4]; 7983 u8 reserved_1[0x8]; 7984 7985 u8 reserved_2[0x1f]; 7986 u8 ae[0x1]; 7987 7988 u8 pll_status[4][0x40]; 7989 }; 7990 7991 struct mlx5_ifc_ppad_reg_bits { 7992 u8 reserved_0[0x3]; 7993 u8 single_mac[0x1]; 7994 u8 reserved_1[0x4]; 7995 u8 local_port[0x8]; 7996 u8 mac_47_32[0x10]; 7997 7998 u8 mac_31_0[0x20]; 7999 8000 u8 reserved_2[0x40]; 8001 }; 8002 8003 struct mlx5_ifc_pmtu_reg_bits { 8004 u8 reserved_0[0x8]; 8005 u8 local_port[0x8]; 8006 u8 reserved_1[0x10]; 8007 8008 u8 max_mtu[0x10]; 8009 u8 reserved_2[0x10]; 8010 8011 u8 admin_mtu[0x10]; 8012 u8 reserved_3[0x10]; 8013 8014 u8 oper_mtu[0x10]; 8015 u8 reserved_4[0x10]; 8016 }; 8017 8018 struct mlx5_ifc_pmpr_reg_bits { 8019 u8 reserved_0[0x8]; 8020 u8 module[0x8]; 8021 u8 reserved_1[0x10]; 8022 8023 u8 reserved_2[0x18]; 8024 u8 attenuation_5g[0x8]; 8025 8026 u8 reserved_3[0x18]; 8027 u8 attenuation_7g[0x8]; 8028 8029 u8 reserved_4[0x18]; 8030 u8 attenuation_12g[0x8]; 8031 }; 8032 8033 struct mlx5_ifc_pmpe_reg_bits { 8034 u8 reserved_0[0x8]; 8035 u8 module[0x8]; 8036 u8 reserved_1[0xc]; 8037 u8 module_status[0x4]; 8038 8039 u8 reserved_2[0x14]; 8040 u8 error_type[0x4]; 8041 u8 reserved_3[0x8]; 8042 8043 u8 reserved_4[0x40]; 8044 }; 8045 8046 struct mlx5_ifc_pmpc_reg_bits { 8047 u8 module_state_updated[32][0x8]; 8048 }; 8049 8050 struct mlx5_ifc_pmlpn_reg_bits { 8051 u8 reserved_0[0x4]; 8052 u8 mlpn_status[0x4]; 8053 u8 local_port[0x8]; 8054 u8 reserved_1[0x10]; 8055 8056 u8 e[0x1]; 8057 u8 reserved_2[0x1f]; 8058 }; 8059 8060 struct mlx5_ifc_pmlp_reg_bits { 8061 u8 rxtx[0x1]; 8062 u8 reserved_0[0x7]; 8063 u8 local_port[0x8]; 8064 u8 reserved_1[0x8]; 8065 u8 width[0x8]; 8066 8067 u8 lane0_module_mapping[0x20]; 8068 8069 u8 lane1_module_mapping[0x20]; 8070 8071 u8 lane2_module_mapping[0x20]; 8072 8073 u8 lane3_module_mapping[0x20]; 8074 8075 u8 reserved_2[0x160]; 8076 }; 8077 8078 struct mlx5_ifc_pmaos_reg_bits { 8079 u8 reserved_0[0x8]; 8080 u8 module[0x8]; 8081 u8 reserved_1[0x4]; 8082 u8 admin_status[0x4]; 8083 u8 reserved_2[0x4]; 8084 u8 oper_status[0x4]; 8085 8086 u8 ase[0x1]; 8087 u8 ee[0x1]; 8088 u8 reserved_3[0x12]; 8089 u8 error_type[0x4]; 8090 u8 reserved_4[0x6]; 8091 u8 e[0x2]; 8092 8093 u8 reserved_5[0x40]; 8094 }; 8095 8096 struct mlx5_ifc_plpc_reg_bits { 8097 u8 reserved_0[0x4]; 8098 u8 profile_id[0xc]; 8099 u8 reserved_1[0x4]; 8100 u8 proto_mask[0x4]; 8101 u8 reserved_2[0x8]; 8102 8103 u8 reserved_3[0x10]; 8104 u8 lane_speed[0x10]; 8105 8106 u8 reserved_4[0x17]; 8107 u8 lpbf[0x1]; 8108 u8 fec_mode_policy[0x8]; 8109 8110 u8 retransmission_capability[0x8]; 8111 u8 fec_mode_capability[0x18]; 8112 8113 u8 retransmission_support_admin[0x8]; 8114 u8 fec_mode_support_admin[0x18]; 8115 8116 u8 retransmission_request_admin[0x8]; 8117 u8 fec_mode_request_admin[0x18]; 8118 8119 u8 reserved_5[0x80]; 8120 }; 8121 8122 struct mlx5_ifc_pll_status_data_bits { 8123 u8 reserved_0[0x1]; 8124 u8 lock_cal[0x1]; 8125 u8 lock_status[0x2]; 8126 u8 reserved_1[0x2]; 8127 u8 algo_f_ctrl[0xa]; 8128 u8 analog_algo_num_var[0x6]; 8129 u8 f_ctrl_measure[0xa]; 8130 8131 u8 reserved_2[0x2]; 8132 u8 analog_var[0x6]; 8133 u8 reserved_3[0x2]; 8134 u8 high_var[0x6]; 8135 u8 reserved_4[0x2]; 8136 u8 low_var[0x6]; 8137 u8 reserved_5[0x2]; 8138 u8 mid_val[0x6]; 8139 }; 8140 8141 struct mlx5_ifc_plib_reg_bits { 8142 u8 reserved_0[0x8]; 8143 u8 local_port[0x8]; 8144 u8 reserved_1[0x8]; 8145 u8 ib_port[0x8]; 8146 8147 u8 reserved_2[0x60]; 8148 }; 8149 8150 struct mlx5_ifc_plbf_reg_bits { 8151 u8 reserved_0[0x8]; 8152 u8 local_port[0x8]; 8153 u8 reserved_1[0xd]; 8154 u8 lbf_mode[0x3]; 8155 8156 u8 reserved_2[0x20]; 8157 }; 8158 8159 struct mlx5_ifc_pipg_reg_bits { 8160 u8 reserved_0[0x8]; 8161 u8 local_port[0x8]; 8162 u8 reserved_1[0x10]; 8163 8164 u8 dic[0x1]; 8165 u8 reserved_2[0x19]; 8166 u8 ipg[0x4]; 8167 u8 reserved_3[0x2]; 8168 }; 8169 8170 struct mlx5_ifc_pifr_reg_bits { 8171 u8 reserved_0[0x8]; 8172 u8 local_port[0x8]; 8173 u8 reserved_1[0x10]; 8174 8175 u8 reserved_2[0xe0]; 8176 8177 u8 port_filter[8][0x20]; 8178 8179 u8 port_filter_update_en[8][0x20]; 8180 }; 8181 8182 struct mlx5_ifc_phys_layer_cntrs_bits { 8183 u8 time_since_last_clear_high[0x20]; 8184 8185 u8 time_since_last_clear_low[0x20]; 8186 8187 u8 symbol_errors_high[0x20]; 8188 8189 u8 symbol_errors_low[0x20]; 8190 8191 u8 sync_headers_errors_high[0x20]; 8192 8193 u8 sync_headers_errors_low[0x20]; 8194 8195 u8 edpl_bip_errors_lane0_high[0x20]; 8196 8197 u8 edpl_bip_errors_lane0_low[0x20]; 8198 8199 u8 edpl_bip_errors_lane1_high[0x20]; 8200 8201 u8 edpl_bip_errors_lane1_low[0x20]; 8202 8203 u8 edpl_bip_errors_lane2_high[0x20]; 8204 8205 u8 edpl_bip_errors_lane2_low[0x20]; 8206 8207 u8 edpl_bip_errors_lane3_high[0x20]; 8208 8209 u8 edpl_bip_errors_lane3_low[0x20]; 8210 8211 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 8212 8213 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 8214 8215 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 8216 8217 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 8218 8219 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 8220 8221 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 8222 8223 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 8224 8225 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 8226 8227 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 8228 8229 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 8230 8231 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 8232 8233 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 8234 8235 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 8236 8237 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 8238 8239 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 8240 8241 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 8242 8243 u8 rs_fec_corrected_blocks_high[0x20]; 8244 8245 u8 rs_fec_corrected_blocks_low[0x20]; 8246 8247 u8 rs_fec_uncorrectable_blocks_high[0x20]; 8248 8249 u8 rs_fec_uncorrectable_blocks_low[0x20]; 8250 8251 u8 rs_fec_no_errors_blocks_high[0x20]; 8252 8253 u8 rs_fec_no_errors_blocks_low[0x20]; 8254 8255 u8 rs_fec_single_error_blocks_high[0x20]; 8256 8257 u8 rs_fec_single_error_blocks_low[0x20]; 8258 8259 u8 rs_fec_corrected_symbols_total_high[0x20]; 8260 8261 u8 rs_fec_corrected_symbols_total_low[0x20]; 8262 8263 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 8264 8265 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 8266 8267 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 8268 8269 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 8270 8271 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 8272 8273 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 8274 8275 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 8276 8277 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 8278 8279 u8 link_down_events[0x20]; 8280 8281 u8 successful_recovery_events[0x20]; 8282 8283 u8 reserved_0[0x180]; 8284 }; 8285 8286 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 8287 u8 symbol_error_counter[0x10]; 8288 8289 u8 link_error_recovery_counter[0x8]; 8290 8291 u8 link_downed_counter[0x8]; 8292 8293 u8 port_rcv_errors[0x10]; 8294 8295 u8 port_rcv_remote_physical_errors[0x10]; 8296 8297 u8 port_rcv_switch_relay_errors[0x10]; 8298 8299 u8 port_xmit_discards[0x10]; 8300 8301 u8 port_xmit_constraint_errors[0x8]; 8302 8303 u8 port_rcv_constraint_errors[0x8]; 8304 8305 u8 reserved_at_70[0x8]; 8306 8307 u8 link_overrun_errors[0x8]; 8308 8309 u8 reserved_at_80[0x10]; 8310 8311 u8 vl_15_dropped[0x10]; 8312 8313 u8 reserved_at_a0[0xa0]; 8314 }; 8315 8316 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 8317 u8 time_since_last_clear_high[0x20]; 8318 8319 u8 time_since_last_clear_low[0x20]; 8320 8321 u8 phy_received_bits_high[0x20]; 8322 8323 u8 phy_received_bits_low[0x20]; 8324 8325 u8 phy_symbol_errors_high[0x20]; 8326 8327 u8 phy_symbol_errors_low[0x20]; 8328 8329 u8 phy_corrected_bits_high[0x20]; 8330 8331 u8 phy_corrected_bits_low[0x20]; 8332 8333 u8 phy_corrected_bits_lane0_high[0x20]; 8334 8335 u8 phy_corrected_bits_lane0_low[0x20]; 8336 8337 u8 phy_corrected_bits_lane1_high[0x20]; 8338 8339 u8 phy_corrected_bits_lane1_low[0x20]; 8340 8341 u8 phy_corrected_bits_lane2_high[0x20]; 8342 8343 u8 phy_corrected_bits_lane2_low[0x20]; 8344 8345 u8 phy_corrected_bits_lane3_high[0x20]; 8346 8347 u8 phy_corrected_bits_lane3_low[0x20]; 8348 8349 u8 reserved_at_200[0x5c0]; 8350 }; 8351 8352 struct mlx5_ifc_infiniband_port_cntrs_bits { 8353 u8 symbol_error_counter[0x10]; 8354 u8 link_error_recovery_counter[0x8]; 8355 u8 link_downed_counter[0x8]; 8356 8357 u8 port_rcv_errors[0x10]; 8358 u8 port_rcv_remote_physical_errors[0x10]; 8359 8360 u8 port_rcv_switch_relay_errors[0x10]; 8361 u8 port_xmit_discards[0x10]; 8362 8363 u8 port_xmit_constraint_errors[0x8]; 8364 u8 port_rcv_constraint_errors[0x8]; 8365 u8 reserved_0[0x8]; 8366 u8 local_link_integrity_errors[0x4]; 8367 u8 excessive_buffer_overrun_errors[0x4]; 8368 8369 u8 reserved_1[0x10]; 8370 u8 vl_15_dropped[0x10]; 8371 8372 u8 port_xmit_data[0x20]; 8373 8374 u8 port_rcv_data[0x20]; 8375 8376 u8 port_xmit_pkts[0x20]; 8377 8378 u8 port_rcv_pkts[0x20]; 8379 8380 u8 port_xmit_wait[0x20]; 8381 8382 u8 reserved_2[0x680]; 8383 }; 8384 8385 struct mlx5_ifc_phrr_reg_bits { 8386 u8 clr[0x1]; 8387 u8 reserved_0[0x7]; 8388 u8 local_port[0x8]; 8389 u8 reserved_1[0x10]; 8390 8391 u8 hist_group[0x8]; 8392 u8 reserved_2[0x10]; 8393 u8 hist_id[0x8]; 8394 8395 u8 reserved_3[0x40]; 8396 8397 u8 time_since_last_clear_high[0x20]; 8398 8399 u8 time_since_last_clear_low[0x20]; 8400 8401 u8 bin[10][0x20]; 8402 }; 8403 8404 struct mlx5_ifc_phbr_for_prio_reg_bits { 8405 u8 reserved_0[0x18]; 8406 u8 prio[0x8]; 8407 }; 8408 8409 struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8410 u8 reserved_0[0x18]; 8411 u8 tclass[0x8]; 8412 }; 8413 8414 struct mlx5_ifc_phbr_binding_reg_bits { 8415 u8 opcode[0x4]; 8416 u8 reserved_0[0x4]; 8417 u8 local_port[0x8]; 8418 u8 pnat[0x2]; 8419 u8 reserved_1[0xe]; 8420 8421 u8 hist_group[0x8]; 8422 u8 reserved_2[0x10]; 8423 u8 hist_id[0x8]; 8424 8425 u8 reserved_3[0x10]; 8426 u8 hist_type[0x10]; 8427 8428 u8 hist_parameters[0x20]; 8429 8430 u8 hist_min_value[0x20]; 8431 8432 u8 hist_max_value[0x20]; 8433 8434 u8 sample_time[0x20]; 8435 }; 8436 8437 enum { 8438 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 8439 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 8440 }; 8441 8442 struct mlx5_ifc_pfcc_reg_bits { 8443 u8 dcbx_operation_type[0x2]; 8444 u8 cap_local_admin[0x1]; 8445 u8 cap_remote_admin[0x1]; 8446 u8 reserved_0[0x4]; 8447 u8 local_port[0x8]; 8448 u8 pnat[0x2]; 8449 u8 reserved_1[0xc]; 8450 u8 shl_cap[0x1]; 8451 u8 shl_opr[0x1]; 8452 8453 u8 ppan[0x4]; 8454 u8 reserved_2[0x4]; 8455 u8 prio_mask_tx[0x8]; 8456 u8 reserved_3[0x8]; 8457 u8 prio_mask_rx[0x8]; 8458 8459 u8 pptx[0x1]; 8460 u8 aptx[0x1]; 8461 u8 reserved_4[0x6]; 8462 u8 pfctx[0x8]; 8463 u8 reserved_5[0x8]; 8464 u8 cbftx[0x8]; 8465 8466 u8 pprx[0x1]; 8467 u8 aprx[0x1]; 8468 u8 reserved_6[0x6]; 8469 u8 pfcrx[0x8]; 8470 u8 reserved_7[0x8]; 8471 u8 cbfrx[0x8]; 8472 8473 u8 device_stall_minor_watermark[0x10]; 8474 u8 device_stall_critical_watermark[0x10]; 8475 8476 u8 reserved_8[0x60]; 8477 }; 8478 8479 struct mlx5_ifc_pelc_reg_bits { 8480 u8 op[0x4]; 8481 u8 reserved_0[0x4]; 8482 u8 local_port[0x8]; 8483 u8 reserved_1[0x10]; 8484 8485 u8 op_admin[0x8]; 8486 u8 op_capability[0x8]; 8487 u8 op_request[0x8]; 8488 u8 op_active[0x8]; 8489 8490 u8 admin[0x40]; 8491 8492 u8 capability[0x40]; 8493 8494 u8 request[0x40]; 8495 8496 u8 active[0x40]; 8497 8498 u8 reserved_2[0x80]; 8499 }; 8500 8501 struct mlx5_ifc_peir_reg_bits { 8502 u8 reserved_0[0x8]; 8503 u8 local_port[0x8]; 8504 u8 reserved_1[0x10]; 8505 8506 u8 reserved_2[0xc]; 8507 u8 error_count[0x4]; 8508 u8 reserved_3[0x10]; 8509 8510 u8 reserved_4[0xc]; 8511 u8 lane[0x4]; 8512 u8 reserved_5[0x8]; 8513 u8 error_type[0x8]; 8514 }; 8515 8516 struct mlx5_ifc_qcam_access_reg_cap_mask { 8517 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8518 u8 qpdpm[0x1]; 8519 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8520 u8 qdpm[0x1]; 8521 u8 qpts[0x1]; 8522 u8 qcap[0x1]; 8523 u8 qcam_access_reg_cap_mask_0[0x1]; 8524 }; 8525 8526 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8527 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8528 u8 qpts_trust_both[0x1]; 8529 }; 8530 8531 struct mlx5_ifc_qcam_reg_bits { 8532 u8 reserved_at_0[0x8]; 8533 u8 feature_group[0x8]; 8534 u8 reserved_at_10[0x8]; 8535 u8 access_reg_group[0x8]; 8536 u8 reserved_at_20[0x20]; 8537 8538 union { 8539 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8540 u8 reserved_at_0[0x80]; 8541 } qos_access_reg_cap_mask; 8542 8543 u8 reserved_at_c0[0x80]; 8544 8545 union { 8546 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8547 u8 reserved_at_0[0x80]; 8548 } qos_feature_cap_mask; 8549 8550 u8 reserved_at_1c0[0x80]; 8551 }; 8552 8553 struct mlx5_ifc_pcam_enhanced_features_bits { 8554 u8 reserved_at_0[0x7e]; 8555 8556 u8 ppcnt_discard_group[0x1]; 8557 u8 ppcnt_statistical_group[0x1]; 8558 }; 8559 8560 struct mlx5_ifc_pcam_reg_bits { 8561 u8 reserved_at_0[0x8]; 8562 u8 feature_group[0x8]; 8563 u8 reserved_at_10[0x8]; 8564 u8 access_reg_group[0x8]; 8565 8566 u8 reserved_at_20[0x20]; 8567 8568 union { 8569 u8 reserved_at_0[0x80]; 8570 } port_access_reg_cap_mask; 8571 8572 u8 reserved_at_c0[0x80]; 8573 8574 union { 8575 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8576 u8 reserved_at_0[0x80]; 8577 } feature_cap_mask; 8578 8579 u8 reserved_at_1c0[0xc0]; 8580 }; 8581 8582 struct mlx5_ifc_mcam_enhanced_features_bits { 8583 u8 reserved_at_0[0x7f]; 8584 8585 u8 pcie_performance_group[0x1]; 8586 }; 8587 8588 struct mlx5_ifc_mcam_access_reg_bits { 8589 u8 reserved_at_0[0x1c]; 8590 u8 mcda[0x1]; 8591 u8 mcc[0x1]; 8592 u8 mcqi[0x1]; 8593 u8 reserved_at_1f[0x1]; 8594 8595 u8 regs_95_to_64[0x20]; 8596 u8 regs_63_to_32[0x20]; 8597 u8 regs_31_to_0[0x20]; 8598 }; 8599 8600 struct mlx5_ifc_mcam_reg_bits { 8601 u8 reserved_at_0[0x8]; 8602 u8 feature_group[0x8]; 8603 u8 reserved_at_10[0x8]; 8604 u8 access_reg_group[0x8]; 8605 8606 u8 reserved_at_20[0x20]; 8607 8608 union { 8609 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8610 u8 reserved_at_0[0x80]; 8611 } mng_access_reg_cap_mask; 8612 8613 u8 reserved_at_c0[0x80]; 8614 8615 union { 8616 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8617 u8 reserved_at_0[0x80]; 8618 } mng_feature_cap_mask; 8619 8620 u8 reserved_at_1c0[0x80]; 8621 }; 8622 8623 struct mlx5_ifc_pcap_reg_bits { 8624 u8 reserved_0[0x8]; 8625 u8 local_port[0x8]; 8626 u8 reserved_1[0x10]; 8627 8628 u8 port_capability_mask[4][0x20]; 8629 }; 8630 8631 struct mlx5_ifc_pbmc_reg_bits { 8632 u8 reserved_0[0x8]; 8633 u8 local_port[0x8]; 8634 u8 reserved_1[0x10]; 8635 8636 u8 xoff_timer_value[0x10]; 8637 u8 xoff_refresh[0x10]; 8638 8639 u8 reserved_2[0x10]; 8640 u8 port_buffer_size[0x10]; 8641 8642 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8643 8644 u8 reserved_3[0x40]; 8645 8646 u8 port_shared_buffer[0x40]; 8647 }; 8648 8649 struct mlx5_ifc_paos_reg_bits { 8650 u8 swid[0x8]; 8651 u8 local_port[0x8]; 8652 u8 reserved_0[0x4]; 8653 u8 admin_status[0x4]; 8654 u8 reserved_1[0x4]; 8655 u8 oper_status[0x4]; 8656 8657 u8 ase[0x1]; 8658 u8 ee[0x1]; 8659 u8 reserved_2[0x1c]; 8660 u8 e[0x2]; 8661 8662 u8 reserved_3[0x40]; 8663 }; 8664 8665 struct mlx5_ifc_pamp_reg_bits { 8666 u8 reserved_0[0x8]; 8667 u8 opamp_group[0x8]; 8668 u8 reserved_1[0xc]; 8669 u8 opamp_group_type[0x4]; 8670 8671 u8 start_index[0x10]; 8672 u8 reserved_2[0x4]; 8673 u8 num_of_indices[0xc]; 8674 8675 u8 index_data[18][0x10]; 8676 }; 8677 8678 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 8679 u8 llr_rx_cells_high[0x20]; 8680 8681 u8 llr_rx_cells_low[0x20]; 8682 8683 u8 llr_rx_error_high[0x20]; 8684 8685 u8 llr_rx_error_low[0x20]; 8686 8687 u8 llr_rx_crc_error_high[0x20]; 8688 8689 u8 llr_rx_crc_error_low[0x20]; 8690 8691 u8 llr_tx_cells_high[0x20]; 8692 8693 u8 llr_tx_cells_low[0x20]; 8694 8695 u8 llr_tx_ret_cells_high[0x20]; 8696 8697 u8 llr_tx_ret_cells_low[0x20]; 8698 8699 u8 llr_tx_ret_events_high[0x20]; 8700 8701 u8 llr_tx_ret_events_low[0x20]; 8702 8703 u8 reserved_0[0x640]; 8704 }; 8705 8706 struct mlx5_ifc_mtmp_reg_bits { 8707 u8 i[0x1]; 8708 u8 reserved_at_1[0x18]; 8709 u8 sensor_index[0x7]; 8710 8711 u8 reserved_at_20[0x10]; 8712 u8 temperature[0x10]; 8713 8714 u8 mte[0x1]; 8715 u8 mtr[0x1]; 8716 u8 reserved_at_42[0x0e]; 8717 u8 max_temperature[0x10]; 8718 8719 u8 tee[0x2]; 8720 u8 reserved_at_62[0x0e]; 8721 u8 temperature_threshold_hi[0x10]; 8722 8723 u8 reserved_at_80[0x10]; 8724 u8 temperature_threshold_lo[0x10]; 8725 8726 u8 reserved_at_100[0x20]; 8727 8728 u8 sensor_name[0x40]; 8729 }; 8730 8731 struct mlx5_ifc_lane_2_module_mapping_bits { 8732 u8 reserved_0[0x6]; 8733 u8 rx_lane[0x2]; 8734 u8 reserved_1[0x6]; 8735 u8 tx_lane[0x2]; 8736 u8 reserved_2[0x8]; 8737 u8 module[0x8]; 8738 }; 8739 8740 struct mlx5_ifc_eth_per_traffic_class_layout_bits { 8741 u8 transmit_queue_high[0x20]; 8742 8743 u8 transmit_queue_low[0x20]; 8744 8745 u8 reserved_0[0x780]; 8746 }; 8747 8748 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 8749 u8 no_buffer_discard_uc_high[0x20]; 8750 8751 u8 no_buffer_discard_uc_low[0x20]; 8752 8753 u8 wred_discard_high[0x20]; 8754 8755 u8 wred_discard_low[0x20]; 8756 8757 u8 reserved_0[0x740]; 8758 }; 8759 8760 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 8761 u8 rx_octets_high[0x20]; 8762 8763 u8 rx_octets_low[0x20]; 8764 8765 u8 reserved_0[0xc0]; 8766 8767 u8 rx_frames_high[0x20]; 8768 8769 u8 rx_frames_low[0x20]; 8770 8771 u8 tx_octets_high[0x20]; 8772 8773 u8 tx_octets_low[0x20]; 8774 8775 u8 reserved_1[0xc0]; 8776 8777 u8 tx_frames_high[0x20]; 8778 8779 u8 tx_frames_low[0x20]; 8780 8781 u8 rx_pause_high[0x20]; 8782 8783 u8 rx_pause_low[0x20]; 8784 8785 u8 rx_pause_duration_high[0x20]; 8786 8787 u8 rx_pause_duration_low[0x20]; 8788 8789 u8 tx_pause_high[0x20]; 8790 8791 u8 tx_pause_low[0x20]; 8792 8793 u8 tx_pause_duration_high[0x20]; 8794 8795 u8 tx_pause_duration_low[0x20]; 8796 8797 u8 rx_pause_transition_high[0x20]; 8798 8799 u8 rx_pause_transition_low[0x20]; 8800 8801 u8 rx_discards_high[0x20]; 8802 8803 u8 rx_discards_low[0x20]; 8804 8805 u8 device_stall_minor_watermark_cnt_high[0x20]; 8806 8807 u8 device_stall_minor_watermark_cnt_low[0x20]; 8808 8809 u8 device_stall_critical_watermark_cnt_high[0x20]; 8810 8811 u8 device_stall_critical_watermark_cnt_low[0x20]; 8812 8813 u8 reserved_2[0x340]; 8814 }; 8815 8816 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 8817 u8 port_transmit_wait_high[0x20]; 8818 8819 u8 port_transmit_wait_low[0x20]; 8820 8821 u8 ecn_marked_high[0x20]; 8822 8823 u8 ecn_marked_low[0x20]; 8824 8825 u8 no_buffer_discard_mc_high[0x20]; 8826 8827 u8 no_buffer_discard_mc_low[0x20]; 8828 8829 u8 rx_ebp_high[0x20]; 8830 8831 u8 rx_ebp_low[0x20]; 8832 8833 u8 tx_ebp_high[0x20]; 8834 8835 u8 tx_ebp_low[0x20]; 8836 8837 u8 rx_buffer_almost_full_high[0x20]; 8838 8839 u8 rx_buffer_almost_full_low[0x20]; 8840 8841 u8 rx_buffer_full_high[0x20]; 8842 8843 u8 rx_buffer_full_low[0x20]; 8844 8845 u8 rx_icrc_encapsulated_high[0x20]; 8846 8847 u8 rx_icrc_encapsulated_low[0x20]; 8848 8849 u8 reserved_0[0x80]; 8850 8851 u8 tx_stats_pkts64octets_high[0x20]; 8852 8853 u8 tx_stats_pkts64octets_low[0x20]; 8854 8855 u8 tx_stats_pkts65to127octets_high[0x20]; 8856 8857 u8 tx_stats_pkts65to127octets_low[0x20]; 8858 8859 u8 tx_stats_pkts128to255octets_high[0x20]; 8860 8861 u8 tx_stats_pkts128to255octets_low[0x20]; 8862 8863 u8 tx_stats_pkts256to511octets_high[0x20]; 8864 8865 u8 tx_stats_pkts256to511octets_low[0x20]; 8866 8867 u8 tx_stats_pkts512to1023octets_high[0x20]; 8868 8869 u8 tx_stats_pkts512to1023octets_low[0x20]; 8870 8871 u8 tx_stats_pkts1024to1518octets_high[0x20]; 8872 8873 u8 tx_stats_pkts1024to1518octets_low[0x20]; 8874 8875 u8 tx_stats_pkts1519to2047octets_high[0x20]; 8876 8877 u8 tx_stats_pkts1519to2047octets_low[0x20]; 8878 8879 u8 tx_stats_pkts2048to4095octets_high[0x20]; 8880 8881 u8 tx_stats_pkts2048to4095octets_low[0x20]; 8882 8883 u8 tx_stats_pkts4096to8191octets_high[0x20]; 8884 8885 u8 tx_stats_pkts4096to8191octets_low[0x20]; 8886 8887 u8 tx_stats_pkts8192to10239octets_high[0x20]; 8888 8889 u8 tx_stats_pkts8192to10239octets_low[0x20]; 8890 8891 u8 reserved_1[0x2C0]; 8892 }; 8893 8894 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 8895 u8 a_frames_transmitted_ok_high[0x20]; 8896 8897 u8 a_frames_transmitted_ok_low[0x20]; 8898 8899 u8 a_frames_received_ok_high[0x20]; 8900 8901 u8 a_frames_received_ok_low[0x20]; 8902 8903 u8 a_frame_check_sequence_errors_high[0x20]; 8904 8905 u8 a_frame_check_sequence_errors_low[0x20]; 8906 8907 u8 a_alignment_errors_high[0x20]; 8908 8909 u8 a_alignment_errors_low[0x20]; 8910 8911 u8 a_octets_transmitted_ok_high[0x20]; 8912 8913 u8 a_octets_transmitted_ok_low[0x20]; 8914 8915 u8 a_octets_received_ok_high[0x20]; 8916 8917 u8 a_octets_received_ok_low[0x20]; 8918 8919 u8 a_multicast_frames_xmitted_ok_high[0x20]; 8920 8921 u8 a_multicast_frames_xmitted_ok_low[0x20]; 8922 8923 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 8924 8925 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 8926 8927 u8 a_multicast_frames_received_ok_high[0x20]; 8928 8929 u8 a_multicast_frames_received_ok_low[0x20]; 8930 8931 u8 a_broadcast_frames_recieved_ok_high[0x20]; 8932 8933 u8 a_broadcast_frames_recieved_ok_low[0x20]; 8934 8935 u8 a_in_range_length_errors_high[0x20]; 8936 8937 u8 a_in_range_length_errors_low[0x20]; 8938 8939 u8 a_out_of_range_length_field_high[0x20]; 8940 8941 u8 a_out_of_range_length_field_low[0x20]; 8942 8943 u8 a_frame_too_long_errors_high[0x20]; 8944 8945 u8 a_frame_too_long_errors_low[0x20]; 8946 8947 u8 a_symbol_error_during_carrier_high[0x20]; 8948 8949 u8 a_symbol_error_during_carrier_low[0x20]; 8950 8951 u8 a_mac_control_frames_transmitted_high[0x20]; 8952 8953 u8 a_mac_control_frames_transmitted_low[0x20]; 8954 8955 u8 a_mac_control_frames_received_high[0x20]; 8956 8957 u8 a_mac_control_frames_received_low[0x20]; 8958 8959 u8 a_unsupported_opcodes_received_high[0x20]; 8960 8961 u8 a_unsupported_opcodes_received_low[0x20]; 8962 8963 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 8964 8965 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 8966 8967 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 8968 8969 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 8970 8971 u8 reserved_0[0x300]; 8972 }; 8973 8974 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 8975 u8 dot3stats_alignment_errors_high[0x20]; 8976 8977 u8 dot3stats_alignment_errors_low[0x20]; 8978 8979 u8 dot3stats_fcs_errors_high[0x20]; 8980 8981 u8 dot3stats_fcs_errors_low[0x20]; 8982 8983 u8 dot3stats_single_collision_frames_high[0x20]; 8984 8985 u8 dot3stats_single_collision_frames_low[0x20]; 8986 8987 u8 dot3stats_multiple_collision_frames_high[0x20]; 8988 8989 u8 dot3stats_multiple_collision_frames_low[0x20]; 8990 8991 u8 dot3stats_sqe_test_errors_high[0x20]; 8992 8993 u8 dot3stats_sqe_test_errors_low[0x20]; 8994 8995 u8 dot3stats_deferred_transmissions_high[0x20]; 8996 8997 u8 dot3stats_deferred_transmissions_low[0x20]; 8998 8999 u8 dot3stats_late_collisions_high[0x20]; 9000 9001 u8 dot3stats_late_collisions_low[0x20]; 9002 9003 u8 dot3stats_excessive_collisions_high[0x20]; 9004 9005 u8 dot3stats_excessive_collisions_low[0x20]; 9006 9007 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 9008 9009 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 9010 9011 u8 dot3stats_carrier_sense_errors_high[0x20]; 9012 9013 u8 dot3stats_carrier_sense_errors_low[0x20]; 9014 9015 u8 dot3stats_frame_too_longs_high[0x20]; 9016 9017 u8 dot3stats_frame_too_longs_low[0x20]; 9018 9019 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 9020 9021 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 9022 9023 u8 dot3stats_symbol_errors_high[0x20]; 9024 9025 u8 dot3stats_symbol_errors_low[0x20]; 9026 9027 u8 dot3control_in_unknown_opcodes_high[0x20]; 9028 9029 u8 dot3control_in_unknown_opcodes_low[0x20]; 9030 9031 u8 dot3in_pause_frames_high[0x20]; 9032 9033 u8 dot3in_pause_frames_low[0x20]; 9034 9035 u8 dot3out_pause_frames_high[0x20]; 9036 9037 u8 dot3out_pause_frames_low[0x20]; 9038 9039 u8 reserved_0[0x3c0]; 9040 }; 9041 9042 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 9043 u8 if_in_octets_high[0x20]; 9044 9045 u8 if_in_octets_low[0x20]; 9046 9047 u8 if_in_ucast_pkts_high[0x20]; 9048 9049 u8 if_in_ucast_pkts_low[0x20]; 9050 9051 u8 if_in_discards_high[0x20]; 9052 9053 u8 if_in_discards_low[0x20]; 9054 9055 u8 if_in_errors_high[0x20]; 9056 9057 u8 if_in_errors_low[0x20]; 9058 9059 u8 if_in_unknown_protos_high[0x20]; 9060 9061 u8 if_in_unknown_protos_low[0x20]; 9062 9063 u8 if_out_octets_high[0x20]; 9064 9065 u8 if_out_octets_low[0x20]; 9066 9067 u8 if_out_ucast_pkts_high[0x20]; 9068 9069 u8 if_out_ucast_pkts_low[0x20]; 9070 9071 u8 if_out_discards_high[0x20]; 9072 9073 u8 if_out_discards_low[0x20]; 9074 9075 u8 if_out_errors_high[0x20]; 9076 9077 u8 if_out_errors_low[0x20]; 9078 9079 u8 if_in_multicast_pkts_high[0x20]; 9080 9081 u8 if_in_multicast_pkts_low[0x20]; 9082 9083 u8 if_in_broadcast_pkts_high[0x20]; 9084 9085 u8 if_in_broadcast_pkts_low[0x20]; 9086 9087 u8 if_out_multicast_pkts_high[0x20]; 9088 9089 u8 if_out_multicast_pkts_low[0x20]; 9090 9091 u8 if_out_broadcast_pkts_high[0x20]; 9092 9093 u8 if_out_broadcast_pkts_low[0x20]; 9094 9095 u8 reserved_0[0x480]; 9096 }; 9097 9098 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 9099 u8 ether_stats_drop_events_high[0x20]; 9100 9101 u8 ether_stats_drop_events_low[0x20]; 9102 9103 u8 ether_stats_octets_high[0x20]; 9104 9105 u8 ether_stats_octets_low[0x20]; 9106 9107 u8 ether_stats_pkts_high[0x20]; 9108 9109 u8 ether_stats_pkts_low[0x20]; 9110 9111 u8 ether_stats_broadcast_pkts_high[0x20]; 9112 9113 u8 ether_stats_broadcast_pkts_low[0x20]; 9114 9115 u8 ether_stats_multicast_pkts_high[0x20]; 9116 9117 u8 ether_stats_multicast_pkts_low[0x20]; 9118 9119 u8 ether_stats_crc_align_errors_high[0x20]; 9120 9121 u8 ether_stats_crc_align_errors_low[0x20]; 9122 9123 u8 ether_stats_undersize_pkts_high[0x20]; 9124 9125 u8 ether_stats_undersize_pkts_low[0x20]; 9126 9127 u8 ether_stats_oversize_pkts_high[0x20]; 9128 9129 u8 ether_stats_oversize_pkts_low[0x20]; 9130 9131 u8 ether_stats_fragments_high[0x20]; 9132 9133 u8 ether_stats_fragments_low[0x20]; 9134 9135 u8 ether_stats_jabbers_high[0x20]; 9136 9137 u8 ether_stats_jabbers_low[0x20]; 9138 9139 u8 ether_stats_collisions_high[0x20]; 9140 9141 u8 ether_stats_collisions_low[0x20]; 9142 9143 u8 ether_stats_pkts64octets_high[0x20]; 9144 9145 u8 ether_stats_pkts64octets_low[0x20]; 9146 9147 u8 ether_stats_pkts65to127octets_high[0x20]; 9148 9149 u8 ether_stats_pkts65to127octets_low[0x20]; 9150 9151 u8 ether_stats_pkts128to255octets_high[0x20]; 9152 9153 u8 ether_stats_pkts128to255octets_low[0x20]; 9154 9155 u8 ether_stats_pkts256to511octets_high[0x20]; 9156 9157 u8 ether_stats_pkts256to511octets_low[0x20]; 9158 9159 u8 ether_stats_pkts512to1023octets_high[0x20]; 9160 9161 u8 ether_stats_pkts512to1023octets_low[0x20]; 9162 9163 u8 ether_stats_pkts1024to1518octets_high[0x20]; 9164 9165 u8 ether_stats_pkts1024to1518octets_low[0x20]; 9166 9167 u8 ether_stats_pkts1519to2047octets_high[0x20]; 9168 9169 u8 ether_stats_pkts1519to2047octets_low[0x20]; 9170 9171 u8 ether_stats_pkts2048to4095octets_high[0x20]; 9172 9173 u8 ether_stats_pkts2048to4095octets_low[0x20]; 9174 9175 u8 ether_stats_pkts4096to8191octets_high[0x20]; 9176 9177 u8 ether_stats_pkts4096to8191octets_low[0x20]; 9178 9179 u8 ether_stats_pkts8192to10239octets_high[0x20]; 9180 9181 u8 ether_stats_pkts8192to10239octets_low[0x20]; 9182 9183 u8 reserved_0[0x280]; 9184 }; 9185 9186 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 9187 u8 symbol_error_counter[0x10]; 9188 u8 link_error_recovery_counter[0x8]; 9189 u8 link_downed_counter[0x8]; 9190 9191 u8 port_rcv_errors[0x10]; 9192 u8 port_rcv_remote_physical_errors[0x10]; 9193 9194 u8 port_rcv_switch_relay_errors[0x10]; 9195 u8 port_xmit_discards[0x10]; 9196 9197 u8 port_xmit_constraint_errors[0x8]; 9198 u8 port_rcv_constraint_errors[0x8]; 9199 u8 reserved_0[0x8]; 9200 u8 local_link_integrity_errors[0x4]; 9201 u8 excessive_buffer_overrun_errors[0x4]; 9202 9203 u8 reserved_1[0x10]; 9204 u8 vl_15_dropped[0x10]; 9205 9206 u8 port_xmit_data[0x20]; 9207 9208 u8 port_rcv_data[0x20]; 9209 9210 u8 port_xmit_pkts[0x20]; 9211 9212 u8 port_rcv_pkts[0x20]; 9213 9214 u8 port_xmit_wait[0x20]; 9215 9216 u8 reserved_2[0x680]; 9217 }; 9218 9219 struct mlx5_ifc_trc_tlb_reg_bits { 9220 u8 reserved_0[0x80]; 9221 9222 u8 tlb_addr[0][0x40]; 9223 }; 9224 9225 struct mlx5_ifc_trc_read_fifo_reg_bits { 9226 u8 reserved_0[0x10]; 9227 u8 requested_event_num[0x10]; 9228 9229 u8 reserved_1[0x20]; 9230 9231 u8 reserved_2[0x10]; 9232 u8 acual_event_num[0x10]; 9233 9234 u8 reserved_3[0x20]; 9235 9236 u8 event[0][0x40]; 9237 }; 9238 9239 struct mlx5_ifc_trc_lock_reg_bits { 9240 u8 reserved_0[0x1f]; 9241 u8 lock[0x1]; 9242 9243 u8 reserved_1[0x60]; 9244 }; 9245 9246 struct mlx5_ifc_trc_filter_reg_bits { 9247 u8 status[0x1]; 9248 u8 reserved_0[0xf]; 9249 u8 filter_index[0x10]; 9250 9251 u8 reserved_1[0x20]; 9252 9253 u8 filter_val[0x20]; 9254 9255 u8 reserved_2[0x1a0]; 9256 }; 9257 9258 struct mlx5_ifc_trc_event_reg_bits { 9259 u8 status[0x1]; 9260 u8 reserved_0[0xf]; 9261 u8 event_index[0x10]; 9262 9263 u8 reserved_1[0x20]; 9264 9265 u8 event_id[0x20]; 9266 9267 u8 event_selector_val[0x10]; 9268 u8 event_selector_size[0x10]; 9269 9270 u8 reserved_2[0x180]; 9271 }; 9272 9273 struct mlx5_ifc_trc_conf_reg_bits { 9274 u8 limit_en[0x1]; 9275 u8 reserved_0[0x3]; 9276 u8 dump_mode[0x4]; 9277 u8 reserved_1[0x15]; 9278 u8 state[0x3]; 9279 9280 u8 reserved_2[0x20]; 9281 9282 u8 limit_event_index[0x20]; 9283 9284 u8 mkey[0x20]; 9285 9286 u8 fifo_ready_ev_num[0x20]; 9287 9288 u8 reserved_3[0x160]; 9289 }; 9290 9291 struct mlx5_ifc_trc_cap_reg_bits { 9292 u8 reserved_0[0x18]; 9293 u8 dump_mode[0x8]; 9294 9295 u8 reserved_1[0x20]; 9296 9297 u8 num_of_events[0x10]; 9298 u8 num_of_filters[0x10]; 9299 9300 u8 fifo_size[0x20]; 9301 9302 u8 tlb_size[0x10]; 9303 u8 event_size[0x10]; 9304 9305 u8 reserved_2[0x160]; 9306 }; 9307 9308 struct mlx5_ifc_set_node_in_bits { 9309 u8 node_description[64][0x8]; 9310 }; 9311 9312 struct mlx5_ifc_register_power_settings_bits { 9313 u8 reserved_0[0x18]; 9314 u8 power_settings_level[0x8]; 9315 9316 u8 reserved_1[0x60]; 9317 }; 9318 9319 struct mlx5_ifc_register_host_endianess_bits { 9320 u8 he[0x1]; 9321 u8 reserved_0[0x1f]; 9322 9323 u8 reserved_1[0x60]; 9324 }; 9325 9326 struct mlx5_ifc_register_diag_buffer_ctrl_bits { 9327 u8 physical_address[0x40]; 9328 }; 9329 9330 struct mlx5_ifc_qtct_reg_bits { 9331 u8 operation_type[0x2]; 9332 u8 cap_local_admin[0x1]; 9333 u8 cap_remote_admin[0x1]; 9334 u8 reserved_0[0x4]; 9335 u8 port_number[0x8]; 9336 u8 reserved_1[0xd]; 9337 u8 prio[0x3]; 9338 9339 u8 reserved_2[0x1d]; 9340 u8 tclass[0x3]; 9341 }; 9342 9343 struct mlx5_ifc_qpdp_reg_bits { 9344 u8 reserved_0[0x8]; 9345 u8 port_number[0x8]; 9346 u8 reserved_1[0x10]; 9347 9348 u8 reserved_2[0x1d]; 9349 u8 pprio[0x3]; 9350 }; 9351 9352 struct mlx5_ifc_port_info_ro_fields_param_bits { 9353 u8 reserved_0[0x8]; 9354 u8 port[0x8]; 9355 u8 max_gid[0x10]; 9356 9357 u8 reserved_1[0x20]; 9358 9359 u8 port_guid[0x40]; 9360 }; 9361 9362 struct mlx5_ifc_nvqc_reg_bits { 9363 u8 type[0x20]; 9364 9365 u8 reserved_0[0x18]; 9366 u8 version[0x4]; 9367 u8 reserved_1[0x2]; 9368 u8 support_wr[0x1]; 9369 u8 support_rd[0x1]; 9370 }; 9371 9372 struct mlx5_ifc_nvia_reg_bits { 9373 u8 reserved_0[0x1d]; 9374 u8 target[0x3]; 9375 9376 u8 reserved_1[0x20]; 9377 }; 9378 9379 struct mlx5_ifc_nvdi_reg_bits { 9380 struct mlx5_ifc_config_item_bits configuration_item_header; 9381 }; 9382 9383 struct mlx5_ifc_nvda_reg_bits { 9384 struct mlx5_ifc_config_item_bits configuration_item_header; 9385 9386 u8 configuration_item_data[0x20]; 9387 }; 9388 9389 struct mlx5_ifc_node_info_ro_fields_param_bits { 9390 u8 system_image_guid[0x40]; 9391 9392 u8 reserved_0[0x40]; 9393 9394 u8 node_guid[0x40]; 9395 9396 u8 reserved_1[0x10]; 9397 u8 max_pkey[0x10]; 9398 9399 u8 reserved_2[0x20]; 9400 }; 9401 9402 struct mlx5_ifc_ets_tcn_config_reg_bits { 9403 u8 g[0x1]; 9404 u8 b[0x1]; 9405 u8 r[0x1]; 9406 u8 reserved_0[0x9]; 9407 u8 group[0x4]; 9408 u8 reserved_1[0x9]; 9409 u8 bw_allocation[0x7]; 9410 9411 u8 reserved_2[0xc]; 9412 u8 max_bw_units[0x4]; 9413 u8 reserved_3[0x8]; 9414 u8 max_bw_value[0x8]; 9415 }; 9416 9417 struct mlx5_ifc_ets_global_config_reg_bits { 9418 u8 reserved_0[0x2]; 9419 u8 r[0x1]; 9420 u8 reserved_1[0x1d]; 9421 9422 u8 reserved_2[0xc]; 9423 u8 max_bw_units[0x4]; 9424 u8 reserved_3[0x8]; 9425 u8 max_bw_value[0x8]; 9426 }; 9427 9428 struct mlx5_ifc_qetc_reg_bits { 9429 u8 reserved_at_0[0x8]; 9430 u8 port_number[0x8]; 9431 u8 reserved_at_10[0x30]; 9432 9433 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9434 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9435 }; 9436 9437 struct mlx5_ifc_nodnic_mac_filters_bits { 9438 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 9439 9440 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 9441 9442 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 9443 9444 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 9445 9446 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 9447 9448 u8 reserved_0[0xc0]; 9449 }; 9450 9451 struct mlx5_ifc_nodnic_gid_filters_bits { 9452 u8 mgid_filter0[16][0x8]; 9453 9454 u8 mgid_filter1[16][0x8]; 9455 9456 u8 mgid_filter2[16][0x8]; 9457 9458 u8 mgid_filter3[16][0x8]; 9459 }; 9460 9461 enum { 9462 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 9463 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 9464 }; 9465 9466 enum { 9467 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 9468 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 9469 }; 9470 9471 struct mlx5_ifc_nodnic_config_reg_bits { 9472 u8 no_dram_nic_revision[0x8]; 9473 u8 hardware_format[0x8]; 9474 u8 support_receive_filter[0x1]; 9475 u8 support_promisc_filter[0x1]; 9476 u8 support_promisc_multicast_filter[0x1]; 9477 u8 reserved_0[0x2]; 9478 u8 log_working_buffer_size[0x3]; 9479 u8 log_pkey_table_size[0x4]; 9480 u8 reserved_1[0x3]; 9481 u8 num_ports[0x1]; 9482 9483 u8 reserved_2[0x2]; 9484 u8 log_max_ring_size[0x6]; 9485 u8 reserved_3[0x18]; 9486 9487 u8 lkey[0x20]; 9488 9489 u8 cqe_format[0x4]; 9490 u8 reserved_4[0x1c]; 9491 9492 u8 node_guid[0x40]; 9493 9494 u8 reserved_5[0x740]; 9495 9496 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 9497 9498 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 9499 }; 9500 9501 struct mlx5_ifc_vlan_layout_bits { 9502 u8 reserved_0[0x14]; 9503 u8 vlan[0xc]; 9504 9505 u8 reserved_1[0x20]; 9506 }; 9507 9508 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9509 u8 reserved_0[0x20]; 9510 9511 u8 mkey[0x20]; 9512 9513 u8 addressh_63_32[0x20]; 9514 9515 u8 addressl_31_0[0x20]; 9516 }; 9517 9518 struct mlx5_ifc_ud_adrs_vector_bits { 9519 u8 dc_key[0x40]; 9520 9521 u8 ext[0x1]; 9522 u8 reserved_0[0x7]; 9523 u8 destination_qp_dct[0x18]; 9524 9525 u8 static_rate[0x4]; 9526 u8 sl_eth_prio[0x4]; 9527 u8 fl[0x1]; 9528 u8 mlid[0x7]; 9529 u8 rlid_udp_sport[0x10]; 9530 9531 u8 reserved_1[0x20]; 9532 9533 u8 rmac_47_16[0x20]; 9534 9535 u8 rmac_15_0[0x10]; 9536 u8 tclass[0x8]; 9537 u8 hop_limit[0x8]; 9538 9539 u8 reserved_2[0x1]; 9540 u8 grh[0x1]; 9541 u8 reserved_3[0x2]; 9542 u8 src_addr_index[0x8]; 9543 u8 flow_label[0x14]; 9544 9545 u8 rgid_rip[16][0x8]; 9546 }; 9547 9548 struct mlx5_ifc_port_module_event_bits { 9549 u8 reserved_0[0x8]; 9550 u8 module[0x8]; 9551 u8 reserved_1[0xc]; 9552 u8 module_status[0x4]; 9553 9554 u8 reserved_2[0x14]; 9555 u8 error_type[0x4]; 9556 u8 reserved_3[0x8]; 9557 9558 u8 reserved_4[0xa0]; 9559 }; 9560 9561 struct mlx5_ifc_icmd_control_bits { 9562 u8 opcode[0x10]; 9563 u8 status[0x8]; 9564 u8 reserved_0[0x7]; 9565 u8 busy[0x1]; 9566 }; 9567 9568 struct mlx5_ifc_eqe_bits { 9569 u8 reserved_0[0x8]; 9570 u8 event_type[0x8]; 9571 u8 reserved_1[0x8]; 9572 u8 event_sub_type[0x8]; 9573 9574 u8 reserved_2[0xe0]; 9575 9576 union mlx5_ifc_event_auto_bits event_data; 9577 9578 u8 reserved_3[0x10]; 9579 u8 signature[0x8]; 9580 u8 reserved_4[0x7]; 9581 u8 owner[0x1]; 9582 }; 9583 9584 enum { 9585 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9586 }; 9587 9588 struct mlx5_ifc_cmd_queue_entry_bits { 9589 u8 type[0x8]; 9590 u8 reserved_0[0x18]; 9591 9592 u8 input_length[0x20]; 9593 9594 u8 input_mailbox_pointer_63_32[0x20]; 9595 9596 u8 input_mailbox_pointer_31_9[0x17]; 9597 u8 reserved_1[0x9]; 9598 9599 u8 command_input_inline_data[16][0x8]; 9600 9601 u8 command_output_inline_data[16][0x8]; 9602 9603 u8 output_mailbox_pointer_63_32[0x20]; 9604 9605 u8 output_mailbox_pointer_31_9[0x17]; 9606 u8 reserved_2[0x9]; 9607 9608 u8 output_length[0x20]; 9609 9610 u8 token[0x8]; 9611 u8 signature[0x8]; 9612 u8 reserved_3[0x8]; 9613 u8 status[0x7]; 9614 u8 ownership[0x1]; 9615 }; 9616 9617 struct mlx5_ifc_cmd_out_bits { 9618 u8 status[0x8]; 9619 u8 reserved_0[0x18]; 9620 9621 u8 syndrome[0x20]; 9622 9623 u8 command_output[0x20]; 9624 }; 9625 9626 struct mlx5_ifc_cmd_in_bits { 9627 u8 opcode[0x10]; 9628 u8 reserved_0[0x10]; 9629 9630 u8 reserved_1[0x10]; 9631 u8 op_mod[0x10]; 9632 9633 u8 command[0][0x20]; 9634 }; 9635 9636 struct mlx5_ifc_cmd_if_box_bits { 9637 u8 mailbox_data[512][0x8]; 9638 9639 u8 reserved_0[0x180]; 9640 9641 u8 next_pointer_63_32[0x20]; 9642 9643 u8 next_pointer_31_10[0x16]; 9644 u8 reserved_1[0xa]; 9645 9646 u8 block_number[0x20]; 9647 9648 u8 reserved_2[0x8]; 9649 u8 token[0x8]; 9650 u8 ctrl_signature[0x8]; 9651 u8 signature[0x8]; 9652 }; 9653 9654 struct mlx5_ifc_mtt_bits { 9655 u8 ptag_63_32[0x20]; 9656 9657 u8 ptag_31_8[0x18]; 9658 u8 reserved_0[0x6]; 9659 u8 wr_en[0x1]; 9660 u8 rd_en[0x1]; 9661 }; 9662 9663 /* Vendor Specific Capabilities, VSC */ 9664 enum { 9665 MLX5_VSC_DOMAIN_ICMD = 0x1, 9666 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 9667 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 9668 }; 9669 9670 struct mlx5_ifc_vendor_specific_cap_bits { 9671 u8 type[0x8]; 9672 u8 length[0x8]; 9673 u8 next_pointer[0x8]; 9674 u8 capability_id[0x8]; 9675 9676 u8 status[0x3]; 9677 u8 reserved_0[0xd]; 9678 u8 space[0x10]; 9679 9680 u8 counter[0x20]; 9681 9682 u8 semaphore[0x20]; 9683 9684 u8 flag[0x1]; 9685 u8 reserved_1[0x1]; 9686 u8 address[0x1e]; 9687 9688 u8 data[0x20]; 9689 }; 9690 9691 enum { 9692 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9693 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9694 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9695 }; 9696 9697 enum { 9698 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9699 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9700 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9701 }; 9702 9703 enum { 9704 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 9705 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 9706 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 9707 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 9708 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 9709 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 9710 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 9711 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 9712 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 9713 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 9714 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 9715 }; 9716 9717 struct mlx5_ifc_initial_seg_bits { 9718 u8 fw_rev_minor[0x10]; 9719 u8 fw_rev_major[0x10]; 9720 9721 u8 cmd_interface_rev[0x10]; 9722 u8 fw_rev_subminor[0x10]; 9723 9724 u8 reserved_0[0x40]; 9725 9726 u8 cmdq_phy_addr_63_32[0x20]; 9727 9728 u8 cmdq_phy_addr_31_12[0x14]; 9729 u8 reserved_1[0x2]; 9730 u8 nic_interface[0x2]; 9731 u8 log_cmdq_size[0x4]; 9732 u8 log_cmdq_stride[0x4]; 9733 9734 u8 command_doorbell_vector[0x20]; 9735 9736 u8 reserved_2[0xf00]; 9737 9738 u8 initializing[0x1]; 9739 u8 reserved_3[0x4]; 9740 u8 nic_interface_supported[0x3]; 9741 u8 reserved_4[0x18]; 9742 9743 struct mlx5_ifc_health_buffer_bits health_buffer; 9744 9745 u8 no_dram_nic_offset[0x20]; 9746 9747 u8 reserved_5[0x6de0]; 9748 9749 u8 internal_timer_h[0x20]; 9750 9751 u8 internal_timer_l[0x20]; 9752 9753 u8 reserved_6[0x20]; 9754 9755 u8 reserved_7[0x1f]; 9756 u8 clear_int[0x1]; 9757 9758 u8 health_syndrome[0x8]; 9759 u8 health_counter[0x18]; 9760 9761 u8 reserved_8[0x17fc0]; 9762 }; 9763 9764 union mlx5_ifc_icmd_interface_document_bits { 9765 struct mlx5_ifc_fw_version_bits fw_version; 9766 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 9767 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 9768 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 9769 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 9770 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 9771 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 9772 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 9773 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 9774 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 9775 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 9776 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 9777 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 9778 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 9779 u8 reserved_0[0x42c0]; 9780 }; 9781 9782 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 9783 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9784 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9785 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9786 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9787 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9788 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 9789 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9790 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9791 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 9792 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 9793 u8 reserved_0[0x7c0]; 9794 }; 9795 9796 struct mlx5_ifc_ppcnt_reg_bits { 9797 u8 swid[0x8]; 9798 u8 local_port[0x8]; 9799 u8 pnat[0x2]; 9800 u8 reserved_0[0x8]; 9801 u8 grp[0x6]; 9802 9803 u8 clr[0x1]; 9804 u8 reserved_1[0x1c]; 9805 u8 prio_tc[0x3]; 9806 9807 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9808 }; 9809 9810 struct mlx5_ifc_pcie_performance_counters_data_layout_bits { 9811 u8 life_time_counter_high[0x20]; 9812 9813 u8 life_time_counter_low[0x20]; 9814 9815 u8 rx_errors[0x20]; 9816 9817 u8 tx_errors[0x20]; 9818 9819 u8 l0_to_recovery_eieos[0x20]; 9820 9821 u8 l0_to_recovery_ts[0x20]; 9822 9823 u8 l0_to_recovery_framing[0x20]; 9824 9825 u8 l0_to_recovery_retrain[0x20]; 9826 9827 u8 crc_error_dllp[0x20]; 9828 9829 u8 crc_error_tlp[0x20]; 9830 9831 u8 reserved_0[0x680]; 9832 }; 9833 9834 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits { 9835 u8 life_time_counter_high[0x20]; 9836 9837 u8 life_time_counter_low[0x20]; 9838 9839 u8 time_to_boot_image_start[0x20]; 9840 9841 u8 time_to_link_image[0x20]; 9842 9843 u8 calibration_time[0x20]; 9844 9845 u8 time_to_first_perst[0x20]; 9846 9847 u8 time_to_detect_state[0x20]; 9848 9849 u8 time_to_l0[0x20]; 9850 9851 u8 time_to_crs_en[0x20]; 9852 9853 u8 time_to_plastic_image_start[0x20]; 9854 9855 u8 time_to_iron_image_start[0x20]; 9856 9857 u8 perst_handler[0x20]; 9858 9859 u8 times_in_l1[0x20]; 9860 9861 u8 times_in_l23[0x20]; 9862 9863 u8 dl_down[0x20]; 9864 9865 u8 config_cycle1usec[0x20]; 9866 9867 u8 config_cycle2to7usec[0x20]; 9868 9869 u8 config_cycle8to15usec[0x20]; 9870 9871 u8 config_cycle16to63usec[0x20]; 9872 9873 u8 config_cycle64usec[0x20]; 9874 9875 u8 correctable_err_msg_sent[0x20]; 9876 9877 u8 non_fatal_err_msg_sent[0x20]; 9878 9879 u8 fatal_err_msg_sent[0x20]; 9880 9881 u8 reserved_0[0x4e0]; 9882 }; 9883 9884 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits { 9885 u8 life_time_counter_high[0x20]; 9886 9887 u8 life_time_counter_low[0x20]; 9888 9889 u8 error_counter_lane0[0x20]; 9890 9891 u8 error_counter_lane1[0x20]; 9892 9893 u8 error_counter_lane2[0x20]; 9894 9895 u8 error_counter_lane3[0x20]; 9896 9897 u8 error_counter_lane4[0x20]; 9898 9899 u8 error_counter_lane5[0x20]; 9900 9901 u8 error_counter_lane6[0x20]; 9902 9903 u8 error_counter_lane7[0x20]; 9904 9905 u8 error_counter_lane8[0x20]; 9906 9907 u8 error_counter_lane9[0x20]; 9908 9909 u8 error_counter_lane10[0x20]; 9910 9911 u8 error_counter_lane11[0x20]; 9912 9913 u8 error_counter_lane12[0x20]; 9914 9915 u8 error_counter_lane13[0x20]; 9916 9917 u8 error_counter_lane14[0x20]; 9918 9919 u8 error_counter_lane15[0x20]; 9920 9921 u8 reserved_0[0x580]; 9922 }; 9923 9924 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits { 9925 struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout; 9926 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout; 9927 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout; 9928 u8 reserved_0[0xf8]; 9929 }; 9930 9931 struct mlx5_ifc_mpcnt_reg_bits { 9932 u8 reserved_0[0x8]; 9933 u8 pcie_index[0x8]; 9934 u8 reserved_1[0xa]; 9935 u8 grp[0x6]; 9936 9937 u8 clr[0x1]; 9938 u8 reserved_2[0x1f]; 9939 9940 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set; 9941 }; 9942 9943 struct mlx5_ifc_mcqi_cap_bits { 9944 u8 supported_info_bitmask[0x20]; 9945 9946 u8 component_size[0x20]; 9947 9948 u8 max_component_size[0x20]; 9949 9950 u8 log_mcda_word_size[0x4]; 9951 u8 reserved_at_64[0xc]; 9952 u8 mcda_max_write_size[0x10]; 9953 9954 u8 rd_en[0x1]; 9955 u8 reserved_at_81[0x1]; 9956 u8 match_chip_id[0x1]; 9957 u8 match_psid[0x1]; 9958 u8 check_user_timestamp[0x1]; 9959 u8 match_base_guid_mac[0x1]; 9960 u8 reserved_at_86[0x1a]; 9961 }; 9962 9963 struct mlx5_ifc_mcqi_reg_bits { 9964 u8 read_pending_component[0x1]; 9965 u8 reserved_at_1[0xf]; 9966 u8 component_index[0x10]; 9967 9968 u8 reserved_at_20[0x20]; 9969 9970 u8 reserved_at_40[0x1b]; 9971 u8 info_type[0x5]; 9972 9973 u8 info_size[0x20]; 9974 9975 u8 offset[0x20]; 9976 9977 u8 reserved_at_a0[0x10]; 9978 u8 data_size[0x10]; 9979 9980 u8 data[0][0x20]; 9981 }; 9982 9983 struct mlx5_ifc_mcc_reg_bits { 9984 u8 reserved_at_0[0x4]; 9985 u8 time_elapsed_since_last_cmd[0xc]; 9986 u8 reserved_at_10[0x8]; 9987 u8 instruction[0x8]; 9988 9989 u8 reserved_at_20[0x10]; 9990 u8 component_index[0x10]; 9991 9992 u8 reserved_at_40[0x8]; 9993 u8 update_handle[0x18]; 9994 9995 u8 handle_owner_type[0x4]; 9996 u8 handle_owner_host_id[0x4]; 9997 u8 reserved_at_68[0x1]; 9998 u8 control_progress[0x7]; 9999 u8 error_code[0x8]; 10000 u8 reserved_at_78[0x4]; 10001 u8 control_state[0x4]; 10002 10003 u8 component_size[0x20]; 10004 10005 u8 reserved_at_a0[0x60]; 10006 }; 10007 10008 struct mlx5_ifc_mcda_reg_bits { 10009 u8 reserved_at_0[0x8]; 10010 u8 update_handle[0x18]; 10011 10012 u8 offset[0x20]; 10013 10014 u8 reserved_at_40[0x10]; 10015 u8 size[0x10]; 10016 10017 u8 reserved_at_60[0x20]; 10018 10019 u8 data[0][0x20]; 10020 }; 10021 10022 union mlx5_ifc_ports_control_registers_document_bits { 10023 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 10024 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10025 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10026 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10027 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10028 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10029 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10030 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10031 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10032 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 10033 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 10034 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10035 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 10036 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10037 struct mlx5_ifc_paos_reg_bits paos_reg; 10038 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 10039 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10040 struct mlx5_ifc_peir_reg_bits peir_reg; 10041 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10042 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10043 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 10044 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 10045 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 10046 struct mlx5_ifc_phrr_reg_bits phrr_reg; 10047 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10048 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10049 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10050 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10051 struct mlx5_ifc_plib_reg_bits plib_reg; 10052 struct mlx5_ifc_pll_status_data_bits pll_status_data; 10053 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10054 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10055 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10056 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10057 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10058 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10059 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10060 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10061 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10062 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10063 struct mlx5_ifc_ppll_reg_bits ppll_reg; 10064 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10065 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10066 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10067 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10068 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10069 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10070 struct mlx5_ifc_pude_reg_bits pude_reg; 10071 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10072 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10073 struct mlx5_ifc_slrp_reg_bits slrp_reg; 10074 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10075 u8 reserved_0[0x7880]; 10076 }; 10077 10078 union mlx5_ifc_debug_enhancements_document_bits { 10079 struct mlx5_ifc_health_buffer_bits health_buffer; 10080 u8 reserved_0[0x200]; 10081 }; 10082 10083 union mlx5_ifc_no_dram_nic_document_bits { 10084 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 10085 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 10086 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 10087 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 10088 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 10089 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 10090 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 10091 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 10092 u8 reserved_0[0x3160]; 10093 }; 10094 10095 union mlx5_ifc_uplink_pci_interface_document_bits { 10096 struct mlx5_ifc_initial_seg_bits initial_seg; 10097 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 10098 u8 reserved_0[0x20120]; 10099 }; 10100 10101 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10102 u8 e[0x1]; 10103 u8 reserved_at_01[0x0b]; 10104 u8 prio[0x04]; 10105 }; 10106 10107 struct mlx5_ifc_qpdpm_reg_bits { 10108 u8 reserved_at_0[0x8]; 10109 u8 local_port[0x8]; 10110 u8 reserved_at_10[0x10]; 10111 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10112 }; 10113 10114 struct mlx5_ifc_qpts_reg_bits { 10115 u8 reserved_at_0[0x8]; 10116 u8 local_port[0x8]; 10117 u8 reserved_at_10[0x2d]; 10118 u8 trust_state[0x3]; 10119 }; 10120 10121 #endif /* MLX5_IFC_H */ 10122