1 /*- 2 * Copyright (c) 2019 Mellanox Technologies. All rights reserved. 3 * Copyright (c) 2022 NVIDIA corporation & affiliates. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifndef _MLX5_TLS_H_ 28 #define _MLX5_TLS_H_ 29 30 #define MLX5E_TLS_TAG_LOCK(tag) mtx_lock(&(tag)->mtx) 31 #define MLX5E_TLS_TAG_UNLOCK(tag) mtx_unlock(&(tag)->mtx) 32 33 #define MLX5E_TLS_STAT_INC(tag, field, num) \ 34 counter_u64_add((tag)->tls->stats.field, num) 35 36 enum { 37 MLX5E_TLS_LOOP = 0, 38 MLX5E_TLS_FAILURE = 1, 39 MLX5E_TLS_DEFERRED = 2, 40 MLX5E_TLS_CONTINUE = 3, 41 }; 42 43 struct mlx5e_tls; 44 struct mlx5e_tls_tag { 45 struct m_snd_tag tag; 46 uint32_t tisn; /* HW TIS context number */ 47 uint32_t dek_index; /* HW TLS context number */ 48 struct mlx5e_tls *tls; 49 struct m_snd_tag *rl_tag; 50 struct mtx mtx; 51 uint32_t expected_seq; /* expected TCP sequence number */ 52 uint32_t state; /* see MLX5E_TLS_ST_XXX */ 53 #define MLX5E_TLS_ST_INIT 0 54 #define MLX5E_TLS_ST_SETUP 1 55 #define MLX5E_TLS_ST_TXRDY 2 56 #define MLX5E_TLS_ST_RELEASE 3 57 #define MLX5E_TLS_ST_FREED 4 58 struct work_struct work; 59 60 uint32_t dek_index_ok:1; 61 62 /* parameters needed */ 63 uint8_t crypto_params[128] __aligned(4); 64 } __aligned(MLX5E_CACHELINE_SIZE); 65 66 #define MLX5E_TLS_STATS(m) \ 67 m(+1, u64, tx_packets, "tx_packets", "Transmitted packets") \ 68 m(+1, u64, tx_bytes, "tx_bytes", "Transmitted bytes") \ 69 m(+1, u64, tx_packets_ooo, "tx_packets_ooo", "Transmitted packets out of order") \ 70 m(+1, u64, tx_bytes_ooo, "tx_bytes_ooo", "Transmitted bytes out of order") \ 71 m(+1, u64, tx_error, "tx_error", "Transmitted packets with error") 72 73 #define MLX5E_TLS_STATS_NUM (0 MLX5E_TLS_STATS(MLX5E_STATS_COUNT)) 74 75 struct mlx5e_tls_stats { 76 struct sysctl_ctx_list ctx; 77 counter_u64_t arg[0]; 78 MLX5E_TLS_STATS(MLX5E_STATS_COUNTER) 79 }; 80 81 struct mlx5e_tls { 82 struct sysctl_ctx_list ctx; 83 struct mlx5e_tls_stats stats; 84 struct workqueue_struct *wq; 85 uma_zone_t zone; 86 uint32_t max_resources; /* max number of resources */ 87 int zone_max; 88 int init; /* set when ready */ 89 char zname[32]; 90 }; 91 92 int mlx5e_tls_init(struct mlx5e_priv *); 93 void mlx5e_tls_cleanup(struct mlx5e_priv *); 94 int mlx5e_sq_tls_xmit(struct mlx5e_sq *, struct mlx5e_xmit_args *, struct mbuf **); 95 96 if_snd_tag_alloc_t mlx5e_tls_snd_tag_alloc; 97 98 #endif /* _MLX5_TLS_H_ */ 99