xref: /freebsd/sys/dev/mii/e1000phy.c (revision cc426dd31990b8b50b210efc450e404596548ca1)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-NetBSD
3  *
4  * Principal Author: Parag Patel
5  * Copyright (c) 2001
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice unmodified, this list of conditions, and the following
13  *    disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  * Additional Copyright (c) 2001 by Traakan Software under same licence.
31  * Secondary Author: Matthew Jacob
32  */
33 
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36 
37 /*
38  * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
39  */
40 
41 /*
42  * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and
43  * 1000baseSX PHY.
44  * Nathan Binkert <nate@openbsd.org>
45  * Jung-uk Kim <jkim@niksun.com>
46  */
47 
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
51 #include <sys/module.h>
52 #include <sys/socket.h>
53 #include <sys/bus.h>
54 
55 #include <net/if.h>
56 #include <net/if_var.h>
57 #include <net/if_media.h>
58 
59 #include <dev/mii/mii.h>
60 #include <dev/mii/miivar.h>
61 #include "miidevs.h"
62 
63 #include <dev/mii/e1000phyreg.h>
64 
65 #include "miibus_if.h"
66 
67 static int	e1000phy_probe(device_t);
68 static int	e1000phy_attach(device_t);
69 
70 static device_method_t e1000phy_methods[] = {
71 	/* device interface */
72 	DEVMETHOD(device_probe,		e1000phy_probe),
73 	DEVMETHOD(device_attach,	e1000phy_attach),
74 	DEVMETHOD(device_detach,	mii_phy_detach),
75 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
76 	DEVMETHOD_END
77 };
78 
79 static devclass_t e1000phy_devclass;
80 static driver_t e1000phy_driver = {
81 	"e1000phy",
82 	e1000phy_methods,
83 	sizeof(struct mii_softc)
84 };
85 
86 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0);
87 
88 static int	e1000phy_service(struct mii_softc *, struct mii_data *, int);
89 static void	e1000phy_status(struct mii_softc *);
90 static void	e1000phy_reset(struct mii_softc *);
91 static int	e1000phy_mii_phy_auto(struct mii_softc *, int);
92 
93 static const struct mii_phydesc e1000phys[] = {
94 	MII_PHY_DESC(MARVELL, E1000),
95 	MII_PHY_DESC(MARVELL, E1011),
96 	MII_PHY_DESC(MARVELL, E1000_3),
97 	MII_PHY_DESC(MARVELL, E1000_5),
98 	MII_PHY_DESC(MARVELL, E1111),
99 	MII_PHY_DESC(xxMARVELL, E1000),
100 	MII_PHY_DESC(xxMARVELL, E1011),
101 	MII_PHY_DESC(xxMARVELL, E1000_3),
102 	MII_PHY_DESC(xxMARVELL, E1000S),
103 	MII_PHY_DESC(xxMARVELL, E1000_5),
104 	MII_PHY_DESC(xxMARVELL, E1101),
105 	MII_PHY_DESC(xxMARVELL, E3082),
106 	MII_PHY_DESC(xxMARVELL, E1112),
107 	MII_PHY_DESC(xxMARVELL, E1149),
108 	MII_PHY_DESC(xxMARVELL, E1111),
109 	MII_PHY_DESC(xxMARVELL, E1116),
110 	MII_PHY_DESC(xxMARVELL, E1116R),
111 	MII_PHY_DESC(xxMARVELL, E1116R_29),
112 	MII_PHY_DESC(xxMARVELL, E1118),
113 	MII_PHY_DESC(xxMARVELL, E1145),
114 	MII_PHY_DESC(xxMARVELL, E1149R),
115 	MII_PHY_DESC(xxMARVELL, E3016),
116 	MII_PHY_DESC(xxMARVELL, PHYG65G),
117 	MII_PHY_END
118 };
119 
120 static const struct mii_phy_funcs e1000phy_funcs = {
121 	e1000phy_service,
122 	e1000phy_status,
123 	e1000phy_reset
124 };
125 
126 static int
127 e1000phy_probe(device_t	dev)
128 {
129 
130 	return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT));
131 }
132 
133 static int
134 e1000phy_attach(device_t dev)
135 {
136 	struct mii_softc *sc;
137 
138 	sc = device_get_softc(dev);
139 
140 	mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &e1000phy_funcs, 0);
141 
142 	if (mii_dev_mac_match(dev, "msk") &&
143 	    (sc->mii_flags & MIIF_MACPRIV0) != 0)
144 		sc->mii_flags |= MIIF_PHYPRIV0;
145 
146 	switch (sc->mii_mpd_model) {
147 	case MII_MODEL_xxMARVELL_E1011:
148 	case MII_MODEL_xxMARVELL_E1112:
149 		if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK)
150 			sc->mii_flags |= MIIF_HAVEFIBER;
151 		break;
152 	case MII_MODEL_xxMARVELL_E1149:
153 	case MII_MODEL_xxMARVELL_E1149R:
154 		/*
155 		 * Some 88E1149 PHY's page select is initialized to
156 		 * point to other bank instead of copper/fiber bank
157 		 * which in turn resulted in wrong registers were
158 		 * accessed during PHY operation. It is believed that
159 		 * page 0 should be used for copper PHY so reinitialize
160 		 * E1000_EADR to select default copper PHY. If parent
161 		 * device know the type of PHY(either copper or fiber),
162 		 * that information should be used to select default
163 		 * type of PHY.
164 		 */
165 		PHY_WRITE(sc, E1000_EADR, 0);
166 		break;
167 	}
168 
169 	PHY_RESET(sc);
170 
171 	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
172 	if (sc->mii_capabilities & BMSR_EXTSTAT) {
173 		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
174 		if ((sc->mii_extcapabilities &
175 		    (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
176 			sc->mii_flags |= MIIF_HAVE_GTCR;
177 	}
178 	device_printf(dev, " ");
179 	mii_phy_add_media(sc);
180 	printf("\n");
181 
182 	MIIBUS_MEDIAINIT(sc->mii_dev);
183 	return (0);
184 }
185 
186 static void
187 e1000phy_reset(struct mii_softc *sc)
188 {
189 	uint16_t reg, page;
190 
191 	reg = PHY_READ(sc, E1000_SCR);
192 	if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) {
193 		reg &= ~E1000_SCR_AUTO_X_MODE;
194 		PHY_WRITE(sc, E1000_SCR, reg);
195 		if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1112) {
196 			/* Select 1000BASE-X only mode. */
197 			page = PHY_READ(sc, E1000_EADR);
198 			PHY_WRITE(sc, E1000_EADR, 2);
199 			reg = PHY_READ(sc, E1000_SCR);
200 			reg &= ~E1000_SCR_MODE_MASK;
201 			reg |= E1000_SCR_MODE_1000BX;
202 			PHY_WRITE(sc, E1000_SCR, reg);
203 			if ((sc->mii_flags & MIIF_PHYPRIV0) != 0) {
204 				/* Set SIGDET polarity low for SFP module. */
205 				PHY_WRITE(sc, E1000_EADR, 1);
206 				reg = PHY_READ(sc, E1000_SCR);
207 				reg |= E1000_SCR_FIB_SIGDET_POLARITY;
208 				PHY_WRITE(sc, E1000_SCR, reg);
209 			}
210 			PHY_WRITE(sc, E1000_EADR, page);
211 		}
212 	} else {
213 		switch (sc->mii_mpd_model) {
214 		case MII_MODEL_xxMARVELL_E1111:
215 		case MII_MODEL_xxMARVELL_E1112:
216 		case MII_MODEL_xxMARVELL_E1116:
217 		case MII_MODEL_xxMARVELL_E1116R_29:
218 		case MII_MODEL_xxMARVELL_E1118:
219 		case MII_MODEL_xxMARVELL_E1149:
220 		case MII_MODEL_xxMARVELL_E1149R:
221 		case MII_MODEL_xxMARVELL_PHYG65G:
222 			/* Disable energy detect mode. */
223 			reg &= ~E1000_SCR_EN_DETECT_MASK;
224 			reg |= E1000_SCR_AUTO_X_MODE;
225 			if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 ||
226 			    sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29)
227 				reg &= ~E1000_SCR_POWER_DOWN;
228 			reg |= E1000_SCR_ASSERT_CRS_ON_TX;
229 			break;
230 		case MII_MODEL_xxMARVELL_E3082:
231 			reg |= (E1000_SCR_AUTO_X_MODE >> 1);
232 			reg |= E1000_SCR_ASSERT_CRS_ON_TX;
233 			break;
234 		case MII_MODEL_xxMARVELL_E3016:
235 			reg |= E1000_SCR_AUTO_MDIX;
236 			reg &= ~(E1000_SCR_EN_DETECT |
237 			    E1000_SCR_SCRAMBLER_DISABLE);
238 			reg |= E1000_SCR_LPNP;
239 			/* XXX Enable class A driver for Yukon FE+ A0. */
240 			PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001);
241 			break;
242 		default:
243 			reg &= ~E1000_SCR_AUTO_X_MODE;
244 			reg |= E1000_SCR_ASSERT_CRS_ON_TX;
245 			break;
246 		}
247 		if (sc->mii_mpd_model != MII_MODEL_xxMARVELL_E3016) {
248 			/* Auto correction for reversed cable polarity. */
249 			reg &= ~E1000_SCR_POLARITY_REVERSAL;
250 		}
251 		PHY_WRITE(sc, E1000_SCR, reg);
252 
253 		if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 ||
254 		    sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29 ||
255 		    sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149 ||
256 		    sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149R) {
257 			PHY_WRITE(sc, E1000_EADR, 2);
258 			reg = PHY_READ(sc, E1000_SCR);
259 			reg |= E1000_SCR_RGMII_POWER_UP;
260 			PHY_WRITE(sc, E1000_SCR, reg);
261 			PHY_WRITE(sc, E1000_EADR, 0);
262 		}
263 	}
264 
265 	switch (sc->mii_mpd_model) {
266 	case MII_MODEL_xxMARVELL_E3082:
267 	case MII_MODEL_xxMARVELL_E1112:
268 	case MII_MODEL_xxMARVELL_E1118:
269 		break;
270 	case MII_MODEL_xxMARVELL_E1116:
271 	case MII_MODEL_xxMARVELL_E1116R_29:
272 		page = PHY_READ(sc, E1000_EADR);
273 		/* Select page 3, LED control register. */
274 		PHY_WRITE(sc, E1000_EADR, 3);
275 		PHY_WRITE(sc, E1000_SCR,
276 		    E1000_SCR_LED_LOS(1) |	/* Link/Act */
277 		    E1000_SCR_LED_INIT(8) |	/* 10Mbps */
278 		    E1000_SCR_LED_STAT1(7) |	/* 100Mbps */
279 		    E1000_SCR_LED_STAT0(7));	/* 1000Mbps */
280 		/* Set blink rate. */
281 		PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) |
282 		    E1000_BLINK_RATE(E1000_BLINK_84MS));
283 		PHY_WRITE(sc, E1000_EADR, page);
284 		break;
285 	case MII_MODEL_xxMARVELL_E3016:
286 		/* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */
287 		PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04);
288 		/* Integrated register calibration workaround. */
289 		PHY_WRITE(sc, 0x1D, 17);
290 		PHY_WRITE(sc, 0x1E, 0x3F60);
291 		break;
292 	default:
293 		/* Force TX_CLK to 25MHz clock. */
294 		reg = PHY_READ(sc, E1000_ESCR);
295 		reg |= E1000_ESCR_TX_CLK_25;
296 		PHY_WRITE(sc, E1000_ESCR, reg);
297 		break;
298 	}
299 
300 	/* Reset the PHY so all changes take effect. */
301 	reg = PHY_READ(sc, E1000_CR);
302 	reg |= E1000_CR_RESET;
303 	PHY_WRITE(sc, E1000_CR, reg);
304 }
305 
306 static int
307 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
308 {
309 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
310 	uint16_t speed, gig;
311 	int reg;
312 
313 	switch (cmd) {
314 	case MII_POLLSTAT:
315 		break;
316 
317 	case MII_MEDIACHG:
318 		if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
319 			e1000phy_mii_phy_auto(sc, ife->ifm_media);
320 			break;
321 		}
322 
323 		speed = 0;
324 		switch (IFM_SUBTYPE(ife->ifm_media)) {
325 		case IFM_1000_T:
326 			if ((sc->mii_flags & MIIF_HAVE_GTCR) == 0)
327 				return (EINVAL);
328 			speed = E1000_CR_SPEED_1000;
329 			break;
330 		case IFM_1000_SX:
331 			if ((sc->mii_extcapabilities &
332 			    (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0)
333 				return (EINVAL);
334 			speed = E1000_CR_SPEED_1000;
335 			break;
336 		case IFM_100_TX:
337 			speed = E1000_CR_SPEED_100;
338 			break;
339 		case IFM_10_T:
340 			speed = E1000_CR_SPEED_10;
341 			break;
342 		case IFM_NONE:
343 			reg = PHY_READ(sc, E1000_CR);
344 			PHY_WRITE(sc, E1000_CR,
345 			    reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN);
346 			goto done;
347 		default:
348 			return (EINVAL);
349 		}
350 
351 		if ((ife->ifm_media & IFM_FDX) != 0) {
352 			speed |= E1000_CR_FULL_DUPLEX;
353 			gig = E1000_1GCR_1000T_FD;
354 		} else
355 			gig = E1000_1GCR_1000T;
356 
357 		reg = PHY_READ(sc, E1000_CR);
358 		reg &= ~E1000_CR_AUTO_NEG_ENABLE;
359 		PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);
360 
361 		if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
362 			gig |= E1000_1GCR_MS_ENABLE;
363 			if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
364 				gig |= E1000_1GCR_MS_VALUE;
365 		} else if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0)
366 			gig = 0;
367 		PHY_WRITE(sc, E1000_1GCR, gig);
368 		PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD);
369 		PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET);
370 done:
371 		break;
372 	case MII_TICK:
373 		/*
374 		 * Only used for autonegotiation.
375 		 */
376 		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
377 			sc->mii_ticks = 0;
378 			break;
379 		}
380 
381 		/*
382 		 * check for link.
383 		 * Read the status register twice; BMSR_LINK is latch-low.
384 		 */
385 		reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
386 		if (reg & BMSR_LINK) {
387 			sc->mii_ticks = 0;
388 			break;
389 		}
390 
391 		/* Announce link loss right after it happens. */
392 		if (sc->mii_ticks++ == 0)
393 			break;
394 		if (sc->mii_ticks <= sc->mii_anegticks)
395 			break;
396 
397 		sc->mii_ticks = 0;
398 		PHY_RESET(sc);
399 		e1000phy_mii_phy_auto(sc, ife->ifm_media);
400 		break;
401 	}
402 
403 	/* Update the media status. */
404 	PHY_STATUS(sc);
405 
406 	/* Callback if something changed. */
407 	mii_phy_update(sc, cmd);
408 	return (0);
409 }
410 
411 static void
412 e1000phy_status(struct mii_softc *sc)
413 {
414 	struct mii_data *mii = sc->mii_pdata;
415 	int bmcr, bmsr, ssr;
416 
417 	mii->mii_media_status = IFM_AVALID;
418 	mii->mii_media_active = IFM_ETHER;
419 
420 	bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
421 	bmcr = PHY_READ(sc, E1000_CR);
422 	ssr = PHY_READ(sc, E1000_SSR);
423 
424 	if (bmsr & E1000_SR_LINK_STATUS)
425 		mii->mii_media_status |= IFM_ACTIVE;
426 
427 	if (bmcr & E1000_CR_LOOPBACK)
428 		mii->mii_media_active |= IFM_LOOP;
429 
430 	if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 &&
431 	    (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) {
432 		/* Erg, still trying, I guess... */
433 		mii->mii_media_active |= IFM_NONE;
434 		return;
435 	}
436 
437 	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
438 		switch (ssr & E1000_SSR_SPEED) {
439 		case E1000_SSR_1000MBS:
440 			mii->mii_media_active |= IFM_1000_T;
441 			break;
442 		case E1000_SSR_100MBS:
443 			mii->mii_media_active |= IFM_100_TX;
444 			break;
445 		case E1000_SSR_10MBS:
446 			mii->mii_media_active |= IFM_10_T;
447 			break;
448 		default:
449 			mii->mii_media_active |= IFM_NONE;
450 			return;
451 		}
452 	} else {
453 		/*
454 		 * Some fiber PHY(88E1112) does not seem to set resolved
455 		 * speed so always assume we've got IFM_1000_SX.
456 		 */
457 		mii->mii_media_active |= IFM_1000_SX;
458 	}
459 
460 	if (ssr & E1000_SSR_DUPLEX) {
461 		mii->mii_media_active |= IFM_FDX;
462 		if ((sc->mii_flags & MIIF_HAVEFIBER) == 0)
463 			mii->mii_media_active |= mii_phy_flowstatus(sc);
464 	} else
465 		mii->mii_media_active |= IFM_HDX;
466 
467 	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
468 		if (((PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR)) &
469 		    E1000_1GSR_MS_CONFIG_RES) != 0)
470 			mii->mii_media_active |= IFM_ETH_MASTER;
471 	}
472 }
473 
474 static int
475 e1000phy_mii_phy_auto(struct mii_softc *sc, int media)
476 {
477 	uint16_t reg;
478 
479 	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
480 		reg = PHY_READ(sc, E1000_AR);
481 		reg &= ~(E1000_AR_PAUSE | E1000_AR_ASM_DIR);
482 		reg |= E1000_AR_10T | E1000_AR_10T_FD |
483 		    E1000_AR_100TX | E1000_AR_100TX_FD;
484 		if ((media & IFM_FLOW) != 0 ||
485 		    (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
486 			reg |= E1000_AR_PAUSE | E1000_AR_ASM_DIR;
487 		PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD);
488 	} else
489 		PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X);
490 	if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) {
491 		reg = 0;
492 		if ((sc->mii_extcapabilities & EXTSR_1000TFDX) != 0)
493 			reg |= E1000_1GCR_1000T_FD;
494 		if ((sc->mii_extcapabilities & EXTSR_1000THDX) != 0)
495 			reg |= E1000_1GCR_1000T;
496 		PHY_WRITE(sc, E1000_1GCR, reg);
497 	}
498 	PHY_WRITE(sc, E1000_CR,
499 	    E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG);
500 
501 	return (EJUSTRETURN);
502 }
503