1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Principal Author: Parag Patel 5 * Copyright (c) 2001 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * Additional Copyright (c) 2001 by Traakan Software under same licence. 31 * Secondary Author: Matthew Jacob 32 */ 33 34 #include <sys/cdefs.h> 35 /* 36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY. 37 */ 38 39 /* 40 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and 41 * 1000baseSX PHY. 42 * Nathan Binkert <nate@openbsd.org> 43 * Jung-uk Kim <jkim@niksun.com> 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/module.h> 50 #include <sys/socket.h> 51 #include <sys/bus.h> 52 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_media.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 #include "miidevs.h" 60 61 #include <dev/mii/e1000phyreg.h> 62 63 #include "miibus_if.h" 64 65 static int e1000phy_probe(device_t); 66 static int e1000phy_attach(device_t); 67 68 static device_method_t e1000phy_methods[] = { 69 /* device interface */ 70 DEVMETHOD(device_probe, e1000phy_probe), 71 DEVMETHOD(device_attach, e1000phy_attach), 72 DEVMETHOD(device_detach, mii_phy_detach), 73 DEVMETHOD(device_shutdown, bus_generic_shutdown), 74 DEVMETHOD_END 75 }; 76 77 static driver_t e1000phy_driver = { 78 "e1000phy", 79 e1000phy_methods, 80 sizeof(struct mii_softc) 81 }; 82 83 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, 0, 0); 84 85 static int e1000phy_service(struct mii_softc *, struct mii_data *, int); 86 static void e1000phy_status(struct mii_softc *); 87 static void e1000phy_reset(struct mii_softc *); 88 static int e1000phy_mii_phy_auto(struct mii_softc *, int); 89 90 static const struct mii_phydesc e1000phys[] = { 91 MII_PHY_DESC(MARVELL, E1000), 92 MII_PHY_DESC(MARVELL, E1011), 93 MII_PHY_DESC(MARVELL, E1000_3), 94 MII_PHY_DESC(MARVELL, E1000_5), 95 MII_PHY_DESC(MARVELL, E1111), 96 MII_PHY_DESC(xxMARVELL, E1000), 97 MII_PHY_DESC(xxMARVELL, E1011), 98 MII_PHY_DESC(xxMARVELL, E1000_3), 99 MII_PHY_DESC(xxMARVELL, E1000S), 100 MII_PHY_DESC(xxMARVELL, E1000_5), 101 MII_PHY_DESC(xxMARVELL, E1101), 102 MII_PHY_DESC(xxMARVELL, E3082), 103 MII_PHY_DESC(xxMARVELL, E1112), 104 MII_PHY_DESC(xxMARVELL, E1149), 105 MII_PHY_DESC(xxMARVELL, E1111), 106 MII_PHY_DESC(xxMARVELL, E1116), 107 MII_PHY_DESC(xxMARVELL, E1116R), 108 MII_PHY_DESC(xxMARVELL, E1116R_29), 109 MII_PHY_DESC(xxMARVELL, E1118), 110 MII_PHY_DESC(xxMARVELL, E1145), 111 MII_PHY_DESC(xxMARVELL, E1149R), 112 MII_PHY_DESC(xxMARVELL, E3016), 113 MII_PHY_DESC(xxMARVELL, PHYG65G), 114 MII_PHY_END 115 }; 116 117 static const struct mii_phy_funcs e1000phy_funcs = { 118 e1000phy_service, 119 e1000phy_status, 120 e1000phy_reset 121 }; 122 123 static int 124 e1000phy_probe(device_t dev) 125 { 126 127 return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT)); 128 } 129 130 static int 131 e1000phy_attach(device_t dev) 132 { 133 struct mii_softc *sc; 134 135 sc = device_get_softc(dev); 136 137 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &e1000phy_funcs, 0); 138 139 if (mii_dev_mac_match(dev, "msk") && 140 (sc->mii_flags & MIIF_MACPRIV0) != 0) 141 sc->mii_flags |= MIIF_PHYPRIV0; 142 143 switch (sc->mii_mpd_model) { 144 case MII_MODEL_xxMARVELL_E1011: 145 case MII_MODEL_xxMARVELL_E1112: 146 if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK) 147 sc->mii_flags |= MIIF_HAVEFIBER; 148 break; 149 case MII_MODEL_xxMARVELL_E1149: 150 case MII_MODEL_xxMARVELL_E1149R: 151 /* 152 * Some 88E1149 PHY's page select is initialized to 153 * point to other bank instead of copper/fiber bank 154 * which in turn resulted in wrong registers were 155 * accessed during PHY operation. It is believed that 156 * page 0 should be used for copper PHY so reinitialize 157 * E1000_EADR to select default copper PHY. If parent 158 * device know the type of PHY(either copper or fiber), 159 * that information should be used to select default 160 * type of PHY. 161 */ 162 PHY_WRITE(sc, E1000_EADR, 0); 163 break; 164 } 165 166 PHY_RESET(sc); 167 168 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 169 if (sc->mii_capabilities & BMSR_EXTSTAT) { 170 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 171 if ((sc->mii_extcapabilities & 172 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 173 sc->mii_flags |= MIIF_HAVE_GTCR; 174 } 175 device_printf(dev, " "); 176 mii_phy_add_media(sc); 177 printf("\n"); 178 179 MIIBUS_MEDIAINIT(sc->mii_dev); 180 return (0); 181 } 182 183 static void 184 e1000phy_reset(struct mii_softc *sc) 185 { 186 uint16_t reg, page; 187 188 /* Undo power-down / isolate */ 189 reg = PHY_READ(sc, E1000_CR); 190 reg &= ~(E1000_CR_ISOLATE | E1000_CR_POWER_DOWN); 191 PHY_WRITE(sc, E1000_CR, reg); 192 193 reg = PHY_READ(sc, E1000_SCR); 194 if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) { 195 reg &= ~E1000_SCR_AUTO_X_MODE; 196 PHY_WRITE(sc, E1000_SCR, reg); 197 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1112) { 198 /* Select 1000BASE-X only mode. */ 199 page = PHY_READ(sc, E1000_EADR); 200 PHY_WRITE(sc, E1000_EADR, 2); 201 reg = PHY_READ(sc, E1000_SCR); 202 reg &= ~E1000_SCR_MODE_MASK; 203 reg |= E1000_SCR_MODE_1000BX; 204 PHY_WRITE(sc, E1000_SCR, reg); 205 if ((sc->mii_flags & MIIF_PHYPRIV0) != 0) { 206 /* Set SIGDET polarity low for SFP module. */ 207 PHY_WRITE(sc, E1000_EADR, 1); 208 reg = PHY_READ(sc, E1000_SCR); 209 reg |= E1000_SCR_FIB_SIGDET_POLARITY; 210 PHY_WRITE(sc, E1000_SCR, reg); 211 } 212 PHY_WRITE(sc, E1000_EADR, page); 213 } 214 } else { 215 switch (sc->mii_mpd_model) { 216 case MII_MODEL_xxMARVELL_E1111: 217 case MII_MODEL_xxMARVELL_E1112: 218 case MII_MODEL_xxMARVELL_E1116: 219 case MII_MODEL_xxMARVELL_E1116R_29: 220 case MII_MODEL_xxMARVELL_E1118: 221 case MII_MODEL_xxMARVELL_E1149: 222 case MII_MODEL_xxMARVELL_E1149R: 223 case MII_MODEL_xxMARVELL_PHYG65G: 224 /* Disable energy detect mode. */ 225 reg &= ~E1000_SCR_EN_DETECT_MASK; 226 reg |= E1000_SCR_AUTO_X_MODE; 227 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 || 228 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29) 229 reg &= ~E1000_SCR_POWER_DOWN; 230 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 231 break; 232 case MII_MODEL_xxMARVELL_E3082: 233 reg |= (E1000_SCR_AUTO_X_MODE >> 1); 234 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 235 break; 236 case MII_MODEL_xxMARVELL_E3016: 237 reg |= E1000_SCR_AUTO_MDIX; 238 reg &= ~(E1000_SCR_EN_DETECT | 239 E1000_SCR_SCRAMBLER_DISABLE); 240 reg |= E1000_SCR_LPNP; 241 /* XXX Enable class A driver for Yukon FE+ A0. */ 242 PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001); 243 break; 244 default: 245 reg &= ~E1000_SCR_AUTO_X_MODE; 246 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 247 break; 248 } 249 if (sc->mii_mpd_model != MII_MODEL_xxMARVELL_E3016) { 250 /* Auto correction for reversed cable polarity. */ 251 reg &= ~E1000_SCR_POLARITY_REVERSAL; 252 } 253 PHY_WRITE(sc, E1000_SCR, reg); 254 255 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 || 256 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29 || 257 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149 || 258 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149R) { 259 PHY_WRITE(sc, E1000_EADR, 2); 260 reg = PHY_READ(sc, E1000_SCR); 261 reg |= E1000_SCR_RGMII_POWER_UP; 262 PHY_WRITE(sc, E1000_SCR, reg); 263 PHY_WRITE(sc, E1000_EADR, 0); 264 } 265 } 266 267 switch (sc->mii_mpd_model) { 268 case MII_MODEL_xxMARVELL_E3082: 269 case MII_MODEL_xxMARVELL_E1112: 270 case MII_MODEL_xxMARVELL_E1118: 271 break; 272 case MII_MODEL_xxMARVELL_E1116: 273 case MII_MODEL_xxMARVELL_E1116R_29: 274 page = PHY_READ(sc, E1000_EADR); 275 /* Select page 3, LED control register. */ 276 PHY_WRITE(sc, E1000_EADR, 3); 277 PHY_WRITE(sc, E1000_SCR, 278 E1000_SCR_LED_LOS(1) | /* Link/Act */ 279 E1000_SCR_LED_INIT(8) | /* 10Mbps */ 280 E1000_SCR_LED_STAT1(7) | /* 100Mbps */ 281 E1000_SCR_LED_STAT0(7)); /* 1000Mbps */ 282 /* Set blink rate. */ 283 PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) | 284 E1000_BLINK_RATE(E1000_BLINK_84MS)); 285 PHY_WRITE(sc, E1000_EADR, page); 286 break; 287 case MII_MODEL_xxMARVELL_E3016: 288 /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */ 289 PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04); 290 /* Integrated register calibration workaround. */ 291 PHY_WRITE(sc, 0x1D, 17); 292 PHY_WRITE(sc, 0x1E, 0x3F60); 293 break; 294 default: 295 /* Force TX_CLK to 25MHz clock. */ 296 reg = PHY_READ(sc, E1000_ESCR); 297 reg |= E1000_ESCR_TX_CLK_25; 298 PHY_WRITE(sc, E1000_ESCR, reg); 299 break; 300 } 301 302 /* Reset the PHY so all changes take effect. */ 303 reg = PHY_READ(sc, E1000_CR); 304 reg |= E1000_CR_RESET; 305 PHY_WRITE(sc, E1000_CR, reg); 306 } 307 308 static int 309 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 310 { 311 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 312 uint16_t speed, gig; 313 int reg; 314 315 switch (cmd) { 316 case MII_POLLSTAT: 317 break; 318 319 case MII_MEDIACHG: 320 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 321 e1000phy_mii_phy_auto(sc, ife->ifm_media); 322 break; 323 } 324 325 speed = 0; 326 switch (IFM_SUBTYPE(ife->ifm_media)) { 327 case IFM_1000_T: 328 if ((sc->mii_flags & MIIF_HAVE_GTCR) == 0) 329 return (EINVAL); 330 speed = E1000_CR_SPEED_1000; 331 break; 332 case IFM_1000_SX: 333 if ((sc->mii_extcapabilities & 334 (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0) 335 return (EINVAL); 336 speed = E1000_CR_SPEED_1000; 337 break; 338 case IFM_100_TX: 339 speed = E1000_CR_SPEED_100; 340 break; 341 case IFM_10_T: 342 speed = E1000_CR_SPEED_10; 343 break; 344 case IFM_NONE: 345 reg = PHY_READ(sc, E1000_CR); 346 PHY_WRITE(sc, E1000_CR, 347 reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN); 348 goto done; 349 default: 350 return (EINVAL); 351 } 352 353 if ((ife->ifm_media & IFM_FDX) != 0) { 354 speed |= E1000_CR_FULL_DUPLEX; 355 gig = E1000_1GCR_1000T_FD; 356 } else 357 gig = E1000_1GCR_1000T; 358 359 reg = PHY_READ(sc, E1000_CR); 360 reg &= ~E1000_CR_AUTO_NEG_ENABLE; 361 /* Undo power-down / isolate */ 362 reg &= ~(E1000_CR_ISOLATE | E1000_CR_POWER_DOWN); 363 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET); 364 365 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 366 gig |= E1000_1GCR_MS_ENABLE; 367 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 368 gig |= E1000_1GCR_MS_VALUE; 369 } else if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) 370 gig = 0; 371 PHY_WRITE(sc, E1000_1GCR, gig); 372 PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD); 373 PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET); 374 done: 375 break; 376 case MII_TICK: 377 /* 378 * Only used for autonegotiation. 379 */ 380 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 381 sc->mii_ticks = 0; 382 break; 383 } 384 385 /* 386 * check for link. 387 * Read the status register twice; BMSR_LINK is latch-low. 388 */ 389 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 390 if (reg & BMSR_LINK) { 391 sc->mii_ticks = 0; 392 break; 393 } 394 395 /* Announce link loss right after it happens. */ 396 if (sc->mii_ticks++ == 0) 397 break; 398 if (sc->mii_ticks <= sc->mii_anegticks) 399 break; 400 401 sc->mii_ticks = 0; 402 PHY_RESET(sc); 403 e1000phy_mii_phy_auto(sc, ife->ifm_media); 404 break; 405 } 406 407 /* Update the media status. */ 408 PHY_STATUS(sc); 409 410 /* Callback if something changed. */ 411 mii_phy_update(sc, cmd); 412 return (0); 413 } 414 415 static void 416 e1000phy_status(struct mii_softc *sc) 417 { 418 struct mii_data *mii = sc->mii_pdata; 419 int bmcr, bmsr, ssr; 420 421 mii->mii_media_status = IFM_AVALID; 422 mii->mii_media_active = IFM_ETHER; 423 424 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR); 425 bmcr = PHY_READ(sc, E1000_CR); 426 ssr = PHY_READ(sc, E1000_SSR); 427 428 if (bmsr & E1000_SR_LINK_STATUS) 429 mii->mii_media_status |= IFM_ACTIVE; 430 431 if (bmcr & E1000_CR_LOOPBACK) 432 mii->mii_media_active |= IFM_LOOP; 433 434 if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 && 435 (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) { 436 /* Erg, still trying, I guess... */ 437 mii->mii_media_active |= IFM_NONE; 438 return; 439 } 440 441 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 442 switch (ssr & E1000_SSR_SPEED) { 443 case E1000_SSR_1000MBS: 444 mii->mii_media_active |= IFM_1000_T; 445 break; 446 case E1000_SSR_100MBS: 447 mii->mii_media_active |= IFM_100_TX; 448 break; 449 case E1000_SSR_10MBS: 450 mii->mii_media_active |= IFM_10_T; 451 break; 452 default: 453 mii->mii_media_active |= IFM_NONE; 454 return; 455 } 456 } else { 457 /* 458 * Some fiber PHY(88E1112) does not seem to set resolved 459 * speed so always assume we've got IFM_1000_SX. 460 */ 461 mii->mii_media_active |= IFM_1000_SX; 462 } 463 464 if (ssr & E1000_SSR_DUPLEX) { 465 mii->mii_media_active |= IFM_FDX; 466 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) 467 mii->mii_media_active |= mii_phy_flowstatus(sc); 468 } else 469 mii->mii_media_active |= IFM_HDX; 470 471 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 472 if (((PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR)) & 473 E1000_1GSR_MS_CONFIG_RES) != 0) 474 mii->mii_media_active |= IFM_ETH_MASTER; 475 } 476 } 477 478 static int 479 e1000phy_mii_phy_auto(struct mii_softc *sc, int media) 480 { 481 uint16_t reg; 482 483 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 484 reg = PHY_READ(sc, E1000_AR); 485 reg &= ~(E1000_AR_PAUSE | E1000_AR_ASM_DIR); 486 reg |= E1000_AR_10T | E1000_AR_10T_FD | 487 E1000_AR_100TX | E1000_AR_100TX_FD; 488 if ((media & IFM_FLOW) != 0 || 489 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 490 reg |= E1000_AR_PAUSE | E1000_AR_ASM_DIR; 491 PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD); 492 } else 493 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X); 494 if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) { 495 reg = 0; 496 if ((sc->mii_extcapabilities & EXTSR_1000TFDX) != 0) 497 reg |= E1000_1GCR_1000T_FD; 498 if ((sc->mii_extcapabilities & EXTSR_1000THDX) != 0) 499 reg |= E1000_1GCR_1000T; 500 PHY_WRITE(sc, E1000_1GCR, reg); 501 } 502 PHY_WRITE(sc, E1000_CR, 503 E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG); 504 505 return (EJUSTRETURN); 506 } 507