1 /*- 2 * Principal Author: Parag Patel 3 * Copyright (c) 2001 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Additional Copyright (c) 2001 by Traakan Software under same licence. 29 * Secondary Author: Matthew Jacob 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY. 37 */ 38 39 /* 40 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and 41 * 1000baseSX PHY. 42 * Nathan Binkert <nate@openbsd.org> 43 * Jung-uk Kim <jkim@niksun.com> 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/module.h> 50 #include <sys/socket.h> 51 #include <sys/bus.h> 52 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_media.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 #include "miidevs.h" 60 61 #include <dev/mii/e1000phyreg.h> 62 63 #include "miibus_if.h" 64 65 static int e1000phy_probe(device_t); 66 static int e1000phy_attach(device_t); 67 68 static device_method_t e1000phy_methods[] = { 69 /* device interface */ 70 DEVMETHOD(device_probe, e1000phy_probe), 71 DEVMETHOD(device_attach, e1000phy_attach), 72 DEVMETHOD(device_detach, mii_phy_detach), 73 DEVMETHOD(device_shutdown, bus_generic_shutdown), 74 DEVMETHOD_END 75 }; 76 77 static devclass_t e1000phy_devclass; 78 static driver_t e1000phy_driver = { 79 "e1000phy", 80 e1000phy_methods, 81 sizeof(struct mii_softc) 82 }; 83 84 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0); 85 86 static int e1000phy_service(struct mii_softc *, struct mii_data *, int); 87 static void e1000phy_status(struct mii_softc *); 88 static void e1000phy_reset(struct mii_softc *); 89 static int e1000phy_mii_phy_auto(struct mii_softc *, int); 90 91 static const struct mii_phydesc e1000phys[] = { 92 MII_PHY_DESC(MARVELL, E1000), 93 MII_PHY_DESC(MARVELL, E1011), 94 MII_PHY_DESC(MARVELL, E1000_3), 95 MII_PHY_DESC(MARVELL, E1000_5), 96 MII_PHY_DESC(MARVELL, E1111), 97 MII_PHY_DESC(xxMARVELL, E1000), 98 MII_PHY_DESC(xxMARVELL, E1011), 99 MII_PHY_DESC(xxMARVELL, E1000_3), 100 MII_PHY_DESC(xxMARVELL, E1000S), 101 MII_PHY_DESC(xxMARVELL, E1000_5), 102 MII_PHY_DESC(xxMARVELL, E1101), 103 MII_PHY_DESC(xxMARVELL, E3082), 104 MII_PHY_DESC(xxMARVELL, E1112), 105 MII_PHY_DESC(xxMARVELL, E1149), 106 MII_PHY_DESC(xxMARVELL, E1111), 107 MII_PHY_DESC(xxMARVELL, E1116), 108 MII_PHY_DESC(xxMARVELL, E1116R), 109 MII_PHY_DESC(xxMARVELL, E1116R_29), 110 MII_PHY_DESC(xxMARVELL, E1118), 111 MII_PHY_DESC(xxMARVELL, E1145), 112 MII_PHY_DESC(xxMARVELL, E1149R), 113 MII_PHY_DESC(xxMARVELL, E3016), 114 MII_PHY_DESC(xxMARVELL, PHYG65G), 115 MII_PHY_END 116 }; 117 118 static const struct mii_phy_funcs e1000phy_funcs = { 119 e1000phy_service, 120 e1000phy_status, 121 e1000phy_reset 122 }; 123 124 static int 125 e1000phy_probe(device_t dev) 126 { 127 128 return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT)); 129 } 130 131 static int 132 e1000phy_attach(device_t dev) 133 { 134 struct mii_softc *sc; 135 struct ifnet *ifp; 136 137 sc = device_get_softc(dev); 138 139 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &e1000phy_funcs, 0); 140 141 ifp = sc->mii_pdata->mii_ifp; 142 if (strcmp(ifp->if_dname, "msk") == 0 && 143 (sc->mii_flags & MIIF_MACPRIV0) != 0) 144 sc->mii_flags |= MIIF_PHYPRIV0; 145 146 switch (sc->mii_mpd_model) { 147 case MII_MODEL_xxMARVELL_E1011: 148 case MII_MODEL_xxMARVELL_E1112: 149 if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK) 150 sc->mii_flags |= MIIF_HAVEFIBER; 151 break; 152 case MII_MODEL_xxMARVELL_E1149: 153 case MII_MODEL_xxMARVELL_E1149R: 154 /* 155 * Some 88E1149 PHY's page select is initialized to 156 * point to other bank instead of copper/fiber bank 157 * which in turn resulted in wrong registers were 158 * accessed during PHY operation. It is believed that 159 * page 0 should be used for copper PHY so reinitialize 160 * E1000_EADR to select default copper PHY. If parent 161 * device know the type of PHY(either copper or fiber), 162 * that information should be used to select default 163 * type of PHY. 164 */ 165 PHY_WRITE(sc, E1000_EADR, 0); 166 break; 167 } 168 169 PHY_RESET(sc); 170 171 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 172 if (sc->mii_capabilities & BMSR_EXTSTAT) 173 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 174 device_printf(dev, " "); 175 mii_phy_add_media(sc); 176 printf("\n"); 177 178 MIIBUS_MEDIAINIT(sc->mii_dev); 179 return (0); 180 } 181 182 static void 183 e1000phy_reset(struct mii_softc *sc) 184 { 185 uint16_t reg, page; 186 187 reg = PHY_READ(sc, E1000_SCR); 188 if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) { 189 reg &= ~E1000_SCR_AUTO_X_MODE; 190 PHY_WRITE(sc, E1000_SCR, reg); 191 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1112) { 192 /* Select 1000BASE-X only mode. */ 193 page = PHY_READ(sc, E1000_EADR); 194 PHY_WRITE(sc, E1000_EADR, 2); 195 reg = PHY_READ(sc, E1000_SCR); 196 reg &= ~E1000_SCR_MODE_MASK; 197 reg |= E1000_SCR_MODE_1000BX; 198 PHY_WRITE(sc, E1000_SCR, reg); 199 if ((sc->mii_flags & MIIF_PHYPRIV0) != 0) { 200 /* Set SIGDET polarity low for SFP module. */ 201 PHY_WRITE(sc, E1000_EADR, 1); 202 reg = PHY_READ(sc, E1000_SCR); 203 reg |= E1000_SCR_FIB_SIGDET_POLARITY; 204 PHY_WRITE(sc, E1000_SCR, reg); 205 } 206 PHY_WRITE(sc, E1000_EADR, page); 207 } 208 } else { 209 switch (sc->mii_mpd_model) { 210 case MII_MODEL_xxMARVELL_E1111: 211 case MII_MODEL_xxMARVELL_E1112: 212 case MII_MODEL_xxMARVELL_E1116: 213 case MII_MODEL_xxMARVELL_E1116R_29: 214 case MII_MODEL_xxMARVELL_E1118: 215 case MII_MODEL_xxMARVELL_E1149: 216 case MII_MODEL_xxMARVELL_E1149R: 217 case MII_MODEL_xxMARVELL_PHYG65G: 218 /* Disable energy detect mode. */ 219 reg &= ~E1000_SCR_EN_DETECT_MASK; 220 reg |= E1000_SCR_AUTO_X_MODE; 221 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 || 222 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29) 223 reg &= ~E1000_SCR_POWER_DOWN; 224 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 225 break; 226 case MII_MODEL_xxMARVELL_E3082: 227 reg |= (E1000_SCR_AUTO_X_MODE >> 1); 228 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 229 break; 230 case MII_MODEL_xxMARVELL_E3016: 231 reg |= E1000_SCR_AUTO_MDIX; 232 reg &= ~(E1000_SCR_EN_DETECT | 233 E1000_SCR_SCRAMBLER_DISABLE); 234 reg |= E1000_SCR_LPNP; 235 /* XXX Enable class A driver for Yukon FE+ A0. */ 236 PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001); 237 break; 238 default: 239 reg &= ~E1000_SCR_AUTO_X_MODE; 240 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 241 break; 242 } 243 if (sc->mii_mpd_model != MII_MODEL_xxMARVELL_E3016) { 244 /* Auto correction for reversed cable polarity. */ 245 reg &= ~E1000_SCR_POLARITY_REVERSAL; 246 } 247 PHY_WRITE(sc, E1000_SCR, reg); 248 249 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 || 250 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29 || 251 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149 || 252 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149R) { 253 PHY_WRITE(sc, E1000_EADR, 2); 254 reg = PHY_READ(sc, E1000_SCR); 255 reg |= E1000_SCR_RGMII_POWER_UP; 256 PHY_WRITE(sc, E1000_SCR, reg); 257 PHY_WRITE(sc, E1000_EADR, 0); 258 } 259 } 260 261 switch (sc->mii_mpd_model) { 262 case MII_MODEL_xxMARVELL_E3082: 263 case MII_MODEL_xxMARVELL_E1112: 264 case MII_MODEL_xxMARVELL_E1118: 265 break; 266 case MII_MODEL_xxMARVELL_E1116: 267 case MII_MODEL_xxMARVELL_E1116R_29: 268 page = PHY_READ(sc, E1000_EADR); 269 /* Select page 3, LED control register. */ 270 PHY_WRITE(sc, E1000_EADR, 3); 271 PHY_WRITE(sc, E1000_SCR, 272 E1000_SCR_LED_LOS(1) | /* Link/Act */ 273 E1000_SCR_LED_INIT(8) | /* 10Mbps */ 274 E1000_SCR_LED_STAT1(7) | /* 100Mbps */ 275 E1000_SCR_LED_STAT0(7)); /* 1000Mbps */ 276 /* Set blink rate. */ 277 PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) | 278 E1000_BLINK_RATE(E1000_BLINK_84MS)); 279 PHY_WRITE(sc, E1000_EADR, page); 280 break; 281 case MII_MODEL_xxMARVELL_E3016: 282 /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */ 283 PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04); 284 /* Integrated register calibration workaround. */ 285 PHY_WRITE(sc, 0x1D, 17); 286 PHY_WRITE(sc, 0x1E, 0x3F60); 287 break; 288 default: 289 /* Force TX_CLK to 25MHz clock. */ 290 reg = PHY_READ(sc, E1000_ESCR); 291 reg |= E1000_ESCR_TX_CLK_25; 292 PHY_WRITE(sc, E1000_ESCR, reg); 293 break; 294 } 295 296 /* Reset the PHY so all changes take effect. */ 297 reg = PHY_READ(sc, E1000_CR); 298 reg |= E1000_CR_RESET; 299 PHY_WRITE(sc, E1000_CR, reg); 300 } 301 302 static int 303 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 304 { 305 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 306 uint16_t speed, gig; 307 int reg; 308 309 switch (cmd) { 310 case MII_POLLSTAT: 311 break; 312 313 case MII_MEDIACHG: 314 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 315 e1000phy_mii_phy_auto(sc, ife->ifm_media); 316 break; 317 } 318 319 speed = 0; 320 switch (IFM_SUBTYPE(ife->ifm_media)) { 321 case IFM_1000_T: 322 if ((sc->mii_extcapabilities & 323 (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0) 324 return (EINVAL); 325 speed = E1000_CR_SPEED_1000; 326 break; 327 case IFM_1000_SX: 328 if ((sc->mii_extcapabilities & 329 (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0) 330 return (EINVAL); 331 speed = E1000_CR_SPEED_1000; 332 break; 333 case IFM_100_TX: 334 speed = E1000_CR_SPEED_100; 335 break; 336 case IFM_10_T: 337 speed = E1000_CR_SPEED_10; 338 break; 339 case IFM_NONE: 340 reg = PHY_READ(sc, E1000_CR); 341 PHY_WRITE(sc, E1000_CR, 342 reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN); 343 goto done; 344 default: 345 return (EINVAL); 346 } 347 348 if ((ife->ifm_media & IFM_FDX) != 0) { 349 speed |= E1000_CR_FULL_DUPLEX; 350 gig = E1000_1GCR_1000T_FD; 351 } else 352 gig = E1000_1GCR_1000T; 353 354 reg = PHY_READ(sc, E1000_CR); 355 reg &= ~E1000_CR_AUTO_NEG_ENABLE; 356 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET); 357 358 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 359 gig |= E1000_1GCR_MS_ENABLE; 360 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 361 gig |= E1000_1GCR_MS_VALUE; 362 } else if ((sc->mii_extcapabilities & 363 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 364 gig = 0; 365 PHY_WRITE(sc, E1000_1GCR, gig); 366 PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD); 367 PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET); 368 done: 369 break; 370 case MII_TICK: 371 /* 372 * Only used for autonegotiation. 373 */ 374 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 375 sc->mii_ticks = 0; 376 break; 377 } 378 379 /* 380 * check for link. 381 * Read the status register twice; BMSR_LINK is latch-low. 382 */ 383 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 384 if (reg & BMSR_LINK) { 385 sc->mii_ticks = 0; 386 break; 387 } 388 389 /* Announce link loss right after it happens. */ 390 if (sc->mii_ticks++ == 0) 391 break; 392 if (sc->mii_ticks <= sc->mii_anegticks) 393 break; 394 395 sc->mii_ticks = 0; 396 PHY_RESET(sc); 397 e1000phy_mii_phy_auto(sc, ife->ifm_media); 398 break; 399 } 400 401 /* Update the media status. */ 402 PHY_STATUS(sc); 403 404 /* Callback if something changed. */ 405 mii_phy_update(sc, cmd); 406 return (0); 407 } 408 409 static void 410 e1000phy_status(struct mii_softc *sc) 411 { 412 struct mii_data *mii = sc->mii_pdata; 413 int bmcr, bmsr, ssr; 414 415 mii->mii_media_status = IFM_AVALID; 416 mii->mii_media_active = IFM_ETHER; 417 418 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR); 419 bmcr = PHY_READ(sc, E1000_CR); 420 ssr = PHY_READ(sc, E1000_SSR); 421 422 if (bmsr & E1000_SR_LINK_STATUS) 423 mii->mii_media_status |= IFM_ACTIVE; 424 425 if (bmcr & E1000_CR_LOOPBACK) 426 mii->mii_media_active |= IFM_LOOP; 427 428 if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 && 429 (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) { 430 /* Erg, still trying, I guess... */ 431 mii->mii_media_active |= IFM_NONE; 432 return; 433 } 434 435 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 436 switch (ssr & E1000_SSR_SPEED) { 437 case E1000_SSR_1000MBS: 438 mii->mii_media_active |= IFM_1000_T; 439 break; 440 case E1000_SSR_100MBS: 441 mii->mii_media_active |= IFM_100_TX; 442 break; 443 case E1000_SSR_10MBS: 444 mii->mii_media_active |= IFM_10_T; 445 break; 446 default: 447 mii->mii_media_active |= IFM_NONE; 448 return; 449 } 450 } else { 451 /* 452 * Some fiber PHY(88E1112) does not seem to set resolved 453 * speed so always assume we've got IFM_1000_SX. 454 */ 455 mii->mii_media_active |= IFM_1000_SX; 456 } 457 458 if (ssr & E1000_SSR_DUPLEX) { 459 mii->mii_media_active |= IFM_FDX; 460 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) 461 mii->mii_media_active |= mii_phy_flowstatus(sc); 462 } else 463 mii->mii_media_active |= IFM_HDX; 464 465 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 466 if (((PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR)) & 467 E1000_1GSR_MS_CONFIG_RES) != 0) 468 mii->mii_media_active |= IFM_ETH_MASTER; 469 } 470 } 471 472 static int 473 e1000phy_mii_phy_auto(struct mii_softc *sc, int media) 474 { 475 uint16_t reg; 476 477 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 478 reg = PHY_READ(sc, E1000_AR); 479 reg &= ~(E1000_AR_PAUSE | E1000_AR_ASM_DIR); 480 reg |= E1000_AR_10T | E1000_AR_10T_FD | 481 E1000_AR_100TX | E1000_AR_100TX_FD; 482 if ((media & IFM_FLOW) != 0 || 483 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 484 reg |= E1000_AR_PAUSE | E1000_AR_ASM_DIR; 485 PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD); 486 } else 487 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X); 488 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 489 PHY_WRITE(sc, E1000_1GCR, 490 E1000_1GCR_1000T_FD | E1000_1GCR_1000T); 491 PHY_WRITE(sc, E1000_CR, 492 E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG); 493 494 return (EJUSTRETURN); 495 } 496