1 /*- 2 * Principal Author: Parag Patel 3 * Copyright (c) 2001 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Additonal Copyright (c) 2001 by Traakan Software under same licence. 29 * Secondary Author: Matthew Jacob 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY. 37 */ 38 39 /* 40 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and 41 * 1000baseSX PHY. 42 * Nathan Binkert <nate@openbsd.org> 43 * Jung-uk Kim <jkim@niksun.com> 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/module.h> 50 #include <sys/socket.h> 51 #include <sys/bus.h> 52 53 54 #include <net/if.h> 55 #include <net/if_media.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 #include "miidevs.h" 60 61 #include <dev/mii/e1000phyreg.h> 62 63 #include "miibus_if.h" 64 65 static int e1000phy_probe(device_t); 66 static int e1000phy_attach(device_t); 67 68 struct e1000phy_softc { 69 struct mii_softc mii_sc; 70 int mii_model; 71 }; 72 73 static device_method_t e1000phy_methods[] = { 74 /* device interface */ 75 DEVMETHOD(device_probe, e1000phy_probe), 76 DEVMETHOD(device_attach, e1000phy_attach), 77 DEVMETHOD(device_detach, mii_phy_detach), 78 DEVMETHOD(device_shutdown, bus_generic_shutdown), 79 { 0, 0 } 80 }; 81 82 static devclass_t e1000phy_devclass; 83 static driver_t e1000phy_driver = { 84 "e1000phy", 85 e1000phy_methods, 86 sizeof(struct e1000phy_softc) 87 }; 88 89 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0); 90 91 static int e1000phy_service(struct mii_softc *, struct mii_data *, int); 92 static void e1000phy_status(struct mii_softc *); 93 static void e1000phy_reset(struct mii_softc *); 94 static int e1000phy_mii_phy_auto(struct e1000phy_softc *); 95 96 static const struct mii_phydesc e1000phys[] = { 97 MII_PHY_DESC(MARVELL, E1000), 98 MII_PHY_DESC(MARVELL, E1011), 99 MII_PHY_DESC(MARVELL, E1000_3), 100 MII_PHY_DESC(MARVELL, E1000S), 101 MII_PHY_DESC(MARVELL, E1000_5), 102 MII_PHY_DESC(MARVELL, E1000_6), 103 MII_PHY_DESC(MARVELL, E3082), 104 MII_PHY_DESC(MARVELL, E1112), 105 MII_PHY_DESC(MARVELL, E1149), 106 MII_PHY_DESC(MARVELL, E1111), 107 MII_PHY_DESC(MARVELL, E1116), 108 MII_PHY_DESC(MARVELL, E1116R), 109 MII_PHY_DESC(MARVELL, E1118), 110 MII_PHY_DESC(MARVELL, E3016), 111 MII_PHY_DESC(xxMARVELL, E1000), 112 MII_PHY_DESC(xxMARVELL, E1011), 113 MII_PHY_DESC(xxMARVELL, E1000_3), 114 MII_PHY_DESC(xxMARVELL, E1000_5), 115 MII_PHY_DESC(xxMARVELL, E1111), 116 MII_PHY_END 117 }; 118 119 static int 120 e1000phy_probe(device_t dev) 121 { 122 123 return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT)); 124 } 125 126 static int 127 e1000phy_attach(device_t dev) 128 { 129 struct e1000phy_softc *esc; 130 struct mii_softc *sc; 131 struct mii_attach_args *ma; 132 struct mii_data *mii; 133 134 esc = device_get_softc(dev); 135 sc = &esc->mii_sc; 136 ma = device_get_ivars(dev); 137 sc->mii_dev = device_get_parent(dev); 138 mii = device_get_softc(sc->mii_dev); 139 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 140 141 sc->mii_inst = mii->mii_instance; 142 sc->mii_phy = ma->mii_phyno; 143 sc->mii_service = e1000phy_service; 144 sc->mii_pdata = mii; 145 mii->mii_instance++; 146 147 esc->mii_model = MII_MODEL(ma->mii_id2); 148 switch (esc->mii_model) { 149 case MII_MODEL_MARVELL_E1011: 150 case MII_MODEL_MARVELL_E1112: 151 if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK) 152 sc->mii_flags |= MIIF_HAVEFIBER; 153 break; 154 case MII_MODEL_MARVELL_E1149: 155 /* 156 * Some 88E1149 PHY's page select is initialized to 157 * point to other bank instead of copper/fiber bank 158 * which in turn resulted in wrong registers were 159 * accessed during PHY operation. It is believed that 160 * page 0 should be used for copper PHY so reinitialize 161 * E1000_EADR to select default copper PHY. If parent 162 * device know the type of PHY(either copper or fiber), 163 * that information should be used to select default 164 * type of PHY. 165 */ 166 PHY_WRITE(sc, E1000_EADR, 0); 167 break; 168 } 169 170 e1000phy_reset(sc); 171 172 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 173 if (sc->mii_capabilities & BMSR_EXTSTAT) 174 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 175 device_printf(dev, " "); 176 mii_phy_add_media(sc); 177 printf("\n"); 178 179 MIIBUS_MEDIAINIT(sc->mii_dev); 180 return (0); 181 } 182 183 static void 184 e1000phy_reset(struct mii_softc *sc) 185 { 186 struct e1000phy_softc *esc; 187 uint16_t reg, page; 188 189 esc = (struct e1000phy_softc *)sc; 190 reg = PHY_READ(sc, E1000_SCR); 191 if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) { 192 reg &= ~E1000_SCR_AUTO_X_MODE; 193 PHY_WRITE(sc, E1000_SCR, reg); 194 if (esc->mii_model == MII_MODEL_MARVELL_E1112) { 195 /* Select 1000BASE-X only mode. */ 196 page = PHY_READ(sc, E1000_EADR); 197 PHY_WRITE(sc, E1000_EADR, 2); 198 reg = PHY_READ(sc, E1000_SCR); 199 reg &= ~E1000_SCR_MODE_MASK; 200 reg |= E1000_SCR_MODE_1000BX; 201 PHY_WRITE(sc, E1000_SCR, reg); 202 PHY_WRITE(sc, E1000_EADR, page); 203 } 204 } else { 205 switch (esc->mii_model) { 206 case MII_MODEL_MARVELL_E1111: 207 case MII_MODEL_MARVELL_E1112: 208 case MII_MODEL_MARVELL_E1116: 209 case MII_MODEL_MARVELL_E1118: 210 case MII_MODEL_MARVELL_E1149: 211 /* Disable energy detect mode. */ 212 reg &= ~E1000_SCR_EN_DETECT_MASK; 213 reg |= E1000_SCR_AUTO_X_MODE; 214 if (esc->mii_model == MII_MODEL_MARVELL_E1116) 215 reg &= ~E1000_SCR_POWER_DOWN; 216 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 217 break; 218 case MII_MODEL_MARVELL_E3082: 219 reg |= (E1000_SCR_AUTO_X_MODE >> 1); 220 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 221 break; 222 case MII_MODEL_MARVELL_E3016: 223 reg |= E1000_SCR_AUTO_MDIX; 224 reg &= ~(E1000_SCR_EN_DETECT | 225 E1000_SCR_SCRAMBLER_DISABLE); 226 reg |= E1000_SCR_LPNP; 227 /* XXX Enable class A driver for Yukon FE+ A0. */ 228 PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001); 229 break; 230 default: 231 reg &= ~E1000_SCR_AUTO_X_MODE; 232 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 233 break; 234 } 235 if (esc->mii_model != MII_MODEL_MARVELL_E3016) { 236 /* Auto correction for reversed cable polarity. */ 237 reg &= ~E1000_SCR_POLARITY_REVERSAL; 238 } 239 PHY_WRITE(sc, E1000_SCR, reg); 240 241 if (esc->mii_model == MII_MODEL_MARVELL_E1116 || 242 esc->mii_model == MII_MODEL_MARVELL_E1149) { 243 PHY_WRITE(sc, E1000_EADR, 2); 244 reg = PHY_READ(sc, E1000_SCR); 245 reg |= E1000_SCR_RGMII_POWER_UP; 246 PHY_WRITE(sc, E1000_SCR, reg); 247 PHY_WRITE(sc, E1000_EADR, 0); 248 } 249 } 250 251 switch (MII_MODEL(esc->mii_model)) { 252 case MII_MODEL_MARVELL_E3082: 253 case MII_MODEL_MARVELL_E1112: 254 case MII_MODEL_MARVELL_E1118: 255 break; 256 case MII_MODEL_MARVELL_E1116: 257 case MII_MODEL_MARVELL_E1149: 258 page = PHY_READ(sc, E1000_EADR); 259 /* Select page 3, LED control register. */ 260 PHY_WRITE(sc, E1000_EADR, 3); 261 PHY_WRITE(sc, E1000_SCR, 262 E1000_SCR_LED_LOS(1) | /* Link/Act */ 263 E1000_SCR_LED_INIT(8) | /* 10Mbps */ 264 E1000_SCR_LED_STAT1(7) | /* 100Mbps */ 265 E1000_SCR_LED_STAT0(7)); /* 1000Mbps */ 266 /* Set blink rate. */ 267 PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) | 268 E1000_BLINK_RATE(E1000_BLINK_84MS)); 269 PHY_WRITE(sc, E1000_EADR, page); 270 break; 271 case MII_MODEL_MARVELL_E3016: 272 /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */ 273 PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04); 274 /* Integrated register calibration workaround. */ 275 PHY_WRITE(sc, 0x1D, 17); 276 PHY_WRITE(sc, 0x1E, 0x3F60); 277 break; 278 default: 279 /* Force TX_CLK to 25MHz clock. */ 280 reg = PHY_READ(sc, E1000_ESCR); 281 reg |= E1000_ESCR_TX_CLK_25; 282 PHY_WRITE(sc, E1000_ESCR, reg); 283 break; 284 } 285 286 /* Reset the PHY so all changes take effect. */ 287 reg = PHY_READ(sc, E1000_CR); 288 reg |= E1000_CR_RESET; 289 PHY_WRITE(sc, E1000_CR, reg); 290 } 291 292 static int 293 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 294 { 295 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 296 struct e1000phy_softc *esc = (struct e1000phy_softc *)sc; 297 uint16_t speed, gig; 298 int reg; 299 300 switch (cmd) { 301 case MII_POLLSTAT: 302 /* 303 * If we're not polling our PHY instance, just return. 304 */ 305 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 306 return (0); 307 break; 308 309 case MII_MEDIACHG: 310 /* 311 * If the media indicates a different PHY instance, 312 * isolate ourselves. 313 */ 314 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 315 reg = PHY_READ(sc, E1000_CR); 316 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_ISOLATE); 317 return (0); 318 } 319 320 /* 321 * If the interface is not up, don't do anything. 322 */ 323 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 324 break; 325 326 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 327 e1000phy_mii_phy_auto(esc); 328 break; 329 } 330 331 speed = 0; 332 switch (IFM_SUBTYPE(ife->ifm_media)) { 333 case IFM_1000_T: 334 if ((sc->mii_extcapabilities & 335 (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0) 336 return (EINVAL); 337 speed = E1000_CR_SPEED_1000; 338 break; 339 case IFM_1000_SX: 340 if ((sc->mii_extcapabilities & 341 (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0) 342 return (EINVAL); 343 speed = E1000_CR_SPEED_1000; 344 break; 345 case IFM_100_TX: 346 speed = E1000_CR_SPEED_100; 347 break; 348 case IFM_10_T: 349 speed = E1000_CR_SPEED_10; 350 break; 351 case IFM_NONE: 352 reg = PHY_READ(sc, E1000_CR); 353 PHY_WRITE(sc, E1000_CR, 354 reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN); 355 goto done; 356 default: 357 return (EINVAL); 358 } 359 360 if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) { 361 speed |= E1000_CR_FULL_DUPLEX; 362 gig = E1000_1GCR_1000T_FD; 363 } else 364 gig = E1000_1GCR_1000T; 365 366 reg = PHY_READ(sc, E1000_CR); 367 reg &= ~E1000_CR_AUTO_NEG_ENABLE; 368 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET); 369 370 /* 371 * When setting the link manually, one side must 372 * be the master and the other the slave. However 373 * ifmedia doesn't give us a good way to specify 374 * this, so we fake it by using one of the LINK 375 * flags. If LINK0 is set, we program the PHY to 376 * be a master, otherwise it's a slave. 377 */ 378 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T || 379 (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_SX)) { 380 if ((mii->mii_ifp->if_flags & IFF_LINK0)) 381 PHY_WRITE(sc, E1000_1GCR, gig | 382 E1000_1GCR_MS_ENABLE | E1000_1GCR_MS_VALUE); 383 else 384 PHY_WRITE(sc, E1000_1GCR, gig | 385 E1000_1GCR_MS_ENABLE); 386 } else { 387 if ((sc->mii_extcapabilities & 388 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 389 PHY_WRITE(sc, E1000_1GCR, 0); 390 } 391 PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD); 392 PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET); 393 done: 394 break; 395 case MII_TICK: 396 /* 397 * If we're not currently selected, just return. 398 */ 399 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 400 return (0); 401 402 /* 403 * Is the interface even up? 404 */ 405 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 406 return (0); 407 408 /* 409 * Only used for autonegotiation. 410 */ 411 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 412 sc->mii_ticks = 0; 413 break; 414 } 415 416 /* 417 * check for link. 418 * Read the status register twice; BMSR_LINK is latch-low. 419 */ 420 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 421 if (reg & BMSR_LINK) { 422 sc->mii_ticks = 0; 423 break; 424 } 425 426 /* Announce link loss right after it happens. */ 427 if (sc->mii_ticks++ == 0) 428 break; 429 if (sc->mii_ticks <= sc->mii_anegticks) 430 break; 431 432 sc->mii_ticks = 0; 433 e1000phy_reset(sc); 434 e1000phy_mii_phy_auto(esc); 435 break; 436 } 437 438 /* Update the media status. */ 439 e1000phy_status(sc); 440 441 /* Callback if something changed. */ 442 mii_phy_update(sc, cmd); 443 return (0); 444 } 445 446 static void 447 e1000phy_status(struct mii_softc *sc) 448 { 449 struct mii_data *mii = sc->mii_pdata; 450 int bmcr, bmsr, gsr, ssr, ar, lpar; 451 452 mii->mii_media_status = IFM_AVALID; 453 mii->mii_media_active = IFM_ETHER; 454 455 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR); 456 bmcr = PHY_READ(sc, E1000_CR); 457 ssr = PHY_READ(sc, E1000_SSR); 458 459 if (bmsr & E1000_SR_LINK_STATUS) 460 mii->mii_media_status |= IFM_ACTIVE; 461 462 if (bmcr & E1000_CR_LOOPBACK) 463 mii->mii_media_active |= IFM_LOOP; 464 465 if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 && 466 (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) { 467 /* Erg, still trying, I guess... */ 468 mii->mii_media_active |= IFM_NONE; 469 return; 470 } 471 472 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 473 switch (ssr & E1000_SSR_SPEED) { 474 case E1000_SSR_1000MBS: 475 mii->mii_media_active |= IFM_1000_T; 476 break; 477 case E1000_SSR_100MBS: 478 mii->mii_media_active |= IFM_100_TX; 479 break; 480 case E1000_SSR_10MBS: 481 mii->mii_media_active |= IFM_10_T; 482 break; 483 default: 484 mii->mii_media_active |= IFM_NONE; 485 return; 486 } 487 } else { 488 if (ssr & E1000_SSR_1000MBS) 489 mii->mii_media_active |= IFM_1000_SX; 490 } 491 492 if (ssr & E1000_SSR_DUPLEX) 493 mii->mii_media_active |= IFM_FDX; 494 else 495 mii->mii_media_active |= IFM_HDX; 496 497 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 498 ar = PHY_READ(sc, E1000_AR); 499 lpar = PHY_READ(sc, E1000_LPAR); 500 /* FLAG0==rx-flow-control FLAG1==tx-flow-control */ 501 if ((ar & E1000_AR_PAUSE) && (lpar & E1000_LPAR_PAUSE)) { 502 mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1; 503 } else if (!(ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) && 504 (lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) { 505 mii->mii_media_active |= IFM_FLAG1; 506 } else if ((ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) && 507 !(lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) { 508 mii->mii_media_active |= IFM_FLAG0; 509 } 510 } 511 512 /* FLAG2 : local PHY resolved to MASTER */ 513 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) || 514 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)) { 515 PHY_READ(sc, E1000_1GSR); 516 gsr = PHY_READ(sc, E1000_1GSR); 517 if ((gsr & E1000_1GSR_MS_CONFIG_RES) != 0) 518 mii->mii_media_active |= IFM_FLAG2; 519 } 520 } 521 522 static int 523 e1000phy_mii_phy_auto(struct e1000phy_softc *esc) 524 { 525 struct mii_softc *sc; 526 uint16_t reg; 527 528 sc = &esc->mii_sc; 529 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 530 reg = PHY_READ(sc, E1000_AR); 531 reg |= E1000_AR_10T | E1000_AR_10T_FD | 532 E1000_AR_100TX | E1000_AR_100TX_FD | 533 E1000_AR_PAUSE | E1000_AR_ASM_DIR; 534 PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD); 535 } else 536 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X | 537 E1000_FA_SYM_PAUSE | E1000_FA_ASYM_PAUSE); 538 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 539 PHY_WRITE(sc, E1000_1GCR, 540 E1000_1GCR_1000T_FD | E1000_1GCR_1000T); 541 PHY_WRITE(sc, E1000_CR, 542 E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG); 543 544 return (EJUSTRETURN); 545 } 546