1 /*- 2 * Principal Author: Parag Patel 3 * Copyright (c) 2001 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Additional Copyright (c) 2001 by Traakan Software under same licence. 29 * Secondary Author: Matthew Jacob 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY. 37 */ 38 39 /* 40 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and 41 * 1000baseSX PHY. 42 * Nathan Binkert <nate@openbsd.org> 43 * Jung-uk Kim <jkim@niksun.com> 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/module.h> 50 #include <sys/socket.h> 51 #include <sys/bus.h> 52 53 54 #include <net/if.h> 55 #include <net/if_media.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 #include "miidevs.h" 60 61 #include <dev/mii/e1000phyreg.h> 62 63 #include "miibus_if.h" 64 65 static int e1000phy_probe(device_t); 66 static int e1000phy_attach(device_t); 67 68 static device_method_t e1000phy_methods[] = { 69 /* device interface */ 70 DEVMETHOD(device_probe, e1000phy_probe), 71 DEVMETHOD(device_attach, e1000phy_attach), 72 DEVMETHOD(device_detach, mii_phy_detach), 73 DEVMETHOD(device_shutdown, bus_generic_shutdown), 74 DEVMETHOD_END 75 }; 76 77 static devclass_t e1000phy_devclass; 78 static driver_t e1000phy_driver = { 79 "e1000phy", 80 e1000phy_methods, 81 sizeof(struct mii_softc) 82 }; 83 84 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0); 85 86 static int e1000phy_service(struct mii_softc *, struct mii_data *, int); 87 static void e1000phy_status(struct mii_softc *); 88 static void e1000phy_reset(struct mii_softc *); 89 static int e1000phy_mii_phy_auto(struct mii_softc *, int); 90 91 static const struct mii_phydesc e1000phys[] = { 92 MII_PHY_DESC(MARVELL, E1000), 93 MII_PHY_DESC(MARVELL, E1011), 94 MII_PHY_DESC(MARVELL, E1000_3), 95 MII_PHY_DESC(MARVELL, E1000_5), 96 MII_PHY_DESC(MARVELL, E1111), 97 MII_PHY_DESC(xxMARVELL, E1000), 98 MII_PHY_DESC(xxMARVELL, E1011), 99 MII_PHY_DESC(xxMARVELL, E1000_3), 100 MII_PHY_DESC(xxMARVELL, E1000S), 101 MII_PHY_DESC(xxMARVELL, E1000_5), 102 MII_PHY_DESC(xxMARVELL, E1101), 103 MII_PHY_DESC(xxMARVELL, E3082), 104 MII_PHY_DESC(xxMARVELL, E1112), 105 MII_PHY_DESC(xxMARVELL, E1149), 106 MII_PHY_DESC(xxMARVELL, E1111), 107 MII_PHY_DESC(xxMARVELL, E1116), 108 MII_PHY_DESC(xxMARVELL, E1116R), 109 MII_PHY_DESC(xxMARVELL, E1116R_29), 110 MII_PHY_DESC(xxMARVELL, E1118), 111 MII_PHY_DESC(xxMARVELL, E1149R), 112 MII_PHY_DESC(xxMARVELL, E3016), 113 MII_PHY_DESC(xxMARVELL, PHYG65G), 114 MII_PHY_END 115 }; 116 117 static const struct mii_phy_funcs e1000phy_funcs = { 118 e1000phy_service, 119 e1000phy_status, 120 e1000phy_reset 121 }; 122 123 static int 124 e1000phy_probe(device_t dev) 125 { 126 127 return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT)); 128 } 129 130 static int 131 e1000phy_attach(device_t dev) 132 { 133 struct mii_softc *sc; 134 struct ifnet *ifp; 135 136 sc = device_get_softc(dev); 137 138 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &e1000phy_funcs, 0); 139 140 ifp = sc->mii_pdata->mii_ifp; 141 if (strcmp(ifp->if_dname, "msk") == 0 && 142 (sc->mii_flags & MIIF_MACPRIV0) != 0) 143 sc->mii_flags |= MIIF_PHYPRIV0; 144 145 switch (sc->mii_mpd_model) { 146 case MII_MODEL_xxMARVELL_E1011: 147 case MII_MODEL_xxMARVELL_E1112: 148 if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK) 149 sc->mii_flags |= MIIF_HAVEFIBER; 150 break; 151 case MII_MODEL_xxMARVELL_E1149: 152 case MII_MODEL_xxMARVELL_E1149R: 153 /* 154 * Some 88E1149 PHY's page select is initialized to 155 * point to other bank instead of copper/fiber bank 156 * which in turn resulted in wrong registers were 157 * accessed during PHY operation. It is believed that 158 * page 0 should be used for copper PHY so reinitialize 159 * E1000_EADR to select default copper PHY. If parent 160 * device know the type of PHY(either copper or fiber), 161 * that information should be used to select default 162 * type of PHY. 163 */ 164 PHY_WRITE(sc, E1000_EADR, 0); 165 break; 166 } 167 168 PHY_RESET(sc); 169 170 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 171 if (sc->mii_capabilities & BMSR_EXTSTAT) 172 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 173 device_printf(dev, " "); 174 mii_phy_add_media(sc); 175 printf("\n"); 176 177 MIIBUS_MEDIAINIT(sc->mii_dev); 178 return (0); 179 } 180 181 static void 182 e1000phy_reset(struct mii_softc *sc) 183 { 184 uint16_t reg, page; 185 186 reg = PHY_READ(sc, E1000_SCR); 187 if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) { 188 reg &= ~E1000_SCR_AUTO_X_MODE; 189 PHY_WRITE(sc, E1000_SCR, reg); 190 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1112) { 191 /* Select 1000BASE-X only mode. */ 192 page = PHY_READ(sc, E1000_EADR); 193 PHY_WRITE(sc, E1000_EADR, 2); 194 reg = PHY_READ(sc, E1000_SCR); 195 reg &= ~E1000_SCR_MODE_MASK; 196 reg |= E1000_SCR_MODE_1000BX; 197 PHY_WRITE(sc, E1000_SCR, reg); 198 if ((sc->mii_flags & MIIF_PHYPRIV0) != 0) { 199 /* Set SIGDET polarity low for SFP module. */ 200 PHY_WRITE(sc, E1000_EADR, 1); 201 reg = PHY_READ(sc, E1000_SCR); 202 reg |= E1000_SCR_FIB_SIGDET_POLARITY; 203 PHY_WRITE(sc, E1000_SCR, reg); 204 } 205 PHY_WRITE(sc, E1000_EADR, page); 206 } 207 } else { 208 switch (sc->mii_mpd_model) { 209 case MII_MODEL_xxMARVELL_E1111: 210 case MII_MODEL_xxMARVELL_E1112: 211 case MII_MODEL_xxMARVELL_E1116: 212 case MII_MODEL_xxMARVELL_E1116R_29: 213 case MII_MODEL_xxMARVELL_E1118: 214 case MII_MODEL_xxMARVELL_E1149: 215 case MII_MODEL_xxMARVELL_E1149R: 216 case MII_MODEL_xxMARVELL_PHYG65G: 217 /* Disable energy detect mode. */ 218 reg &= ~E1000_SCR_EN_DETECT_MASK; 219 reg |= E1000_SCR_AUTO_X_MODE; 220 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 || 221 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29) 222 reg &= ~E1000_SCR_POWER_DOWN; 223 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 224 break; 225 case MII_MODEL_xxMARVELL_E3082: 226 reg |= (E1000_SCR_AUTO_X_MODE >> 1); 227 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 228 break; 229 case MII_MODEL_xxMARVELL_E3016: 230 reg |= E1000_SCR_AUTO_MDIX; 231 reg &= ~(E1000_SCR_EN_DETECT | 232 E1000_SCR_SCRAMBLER_DISABLE); 233 reg |= E1000_SCR_LPNP; 234 /* XXX Enable class A driver for Yukon FE+ A0. */ 235 PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001); 236 break; 237 default: 238 reg &= ~E1000_SCR_AUTO_X_MODE; 239 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 240 break; 241 } 242 if (sc->mii_mpd_model != MII_MODEL_xxMARVELL_E3016) { 243 /* Auto correction for reversed cable polarity. */ 244 reg &= ~E1000_SCR_POLARITY_REVERSAL; 245 } 246 PHY_WRITE(sc, E1000_SCR, reg); 247 248 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 || 249 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29 || 250 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149 || 251 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149R) { 252 PHY_WRITE(sc, E1000_EADR, 2); 253 reg = PHY_READ(sc, E1000_SCR); 254 reg |= E1000_SCR_RGMII_POWER_UP; 255 PHY_WRITE(sc, E1000_SCR, reg); 256 PHY_WRITE(sc, E1000_EADR, 0); 257 } 258 } 259 260 switch (sc->mii_mpd_model) { 261 case MII_MODEL_xxMARVELL_E3082: 262 case MII_MODEL_xxMARVELL_E1112: 263 case MII_MODEL_xxMARVELL_E1118: 264 break; 265 case MII_MODEL_xxMARVELL_E1116: 266 case MII_MODEL_xxMARVELL_E1116R_29: 267 page = PHY_READ(sc, E1000_EADR); 268 /* Select page 3, LED control register. */ 269 PHY_WRITE(sc, E1000_EADR, 3); 270 PHY_WRITE(sc, E1000_SCR, 271 E1000_SCR_LED_LOS(1) | /* Link/Act */ 272 E1000_SCR_LED_INIT(8) | /* 10Mbps */ 273 E1000_SCR_LED_STAT1(7) | /* 100Mbps */ 274 E1000_SCR_LED_STAT0(7)); /* 1000Mbps */ 275 /* Set blink rate. */ 276 PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) | 277 E1000_BLINK_RATE(E1000_BLINK_84MS)); 278 PHY_WRITE(sc, E1000_EADR, page); 279 break; 280 case MII_MODEL_xxMARVELL_E3016: 281 /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */ 282 PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04); 283 /* Integrated register calibration workaround. */ 284 PHY_WRITE(sc, 0x1D, 17); 285 PHY_WRITE(sc, 0x1E, 0x3F60); 286 break; 287 default: 288 /* Force TX_CLK to 25MHz clock. */ 289 reg = PHY_READ(sc, E1000_ESCR); 290 reg |= E1000_ESCR_TX_CLK_25; 291 PHY_WRITE(sc, E1000_ESCR, reg); 292 break; 293 } 294 295 /* Reset the PHY so all changes take effect. */ 296 reg = PHY_READ(sc, E1000_CR); 297 reg |= E1000_CR_RESET; 298 PHY_WRITE(sc, E1000_CR, reg); 299 } 300 301 static int 302 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 303 { 304 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 305 uint16_t speed, gig; 306 int reg; 307 308 switch (cmd) { 309 case MII_POLLSTAT: 310 break; 311 312 case MII_MEDIACHG: 313 /* 314 * If the interface is not up, don't do anything. 315 */ 316 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 317 break; 318 319 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 320 e1000phy_mii_phy_auto(sc, ife->ifm_media); 321 break; 322 } 323 324 speed = 0; 325 switch (IFM_SUBTYPE(ife->ifm_media)) { 326 case IFM_1000_T: 327 if ((sc->mii_extcapabilities & 328 (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0) 329 return (EINVAL); 330 speed = E1000_CR_SPEED_1000; 331 break; 332 case IFM_1000_SX: 333 if ((sc->mii_extcapabilities & 334 (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0) 335 return (EINVAL); 336 speed = E1000_CR_SPEED_1000; 337 break; 338 case IFM_100_TX: 339 speed = E1000_CR_SPEED_100; 340 break; 341 case IFM_10_T: 342 speed = E1000_CR_SPEED_10; 343 break; 344 case IFM_NONE: 345 reg = PHY_READ(sc, E1000_CR); 346 PHY_WRITE(sc, E1000_CR, 347 reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN); 348 goto done; 349 default: 350 return (EINVAL); 351 } 352 353 if ((ife->ifm_media & IFM_FDX) != 0) { 354 speed |= E1000_CR_FULL_DUPLEX; 355 gig = E1000_1GCR_1000T_FD; 356 } else 357 gig = E1000_1GCR_1000T; 358 359 reg = PHY_READ(sc, E1000_CR); 360 reg &= ~E1000_CR_AUTO_NEG_ENABLE; 361 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET); 362 363 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 364 gig |= E1000_1GCR_MS_ENABLE; 365 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 366 gig |= E1000_1GCR_MS_VALUE; 367 } else if ((sc->mii_extcapabilities & 368 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 369 gig = 0; 370 PHY_WRITE(sc, E1000_1GCR, gig); 371 PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD); 372 PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET); 373 done: 374 break; 375 case MII_TICK: 376 /* 377 * Is the interface even up? 378 */ 379 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 380 return (0); 381 382 /* 383 * Only used for autonegotiation. 384 */ 385 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 386 sc->mii_ticks = 0; 387 break; 388 } 389 390 /* 391 * check for link. 392 * Read the status register twice; BMSR_LINK is latch-low. 393 */ 394 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 395 if (reg & BMSR_LINK) { 396 sc->mii_ticks = 0; 397 break; 398 } 399 400 /* Announce link loss right after it happens. */ 401 if (sc->mii_ticks++ == 0) 402 break; 403 if (sc->mii_ticks <= sc->mii_anegticks) 404 break; 405 406 sc->mii_ticks = 0; 407 PHY_RESET(sc); 408 e1000phy_mii_phy_auto(sc, ife->ifm_media); 409 break; 410 } 411 412 /* Update the media status. */ 413 PHY_STATUS(sc); 414 415 /* Callback if something changed. */ 416 mii_phy_update(sc, cmd); 417 return (0); 418 } 419 420 static void 421 e1000phy_status(struct mii_softc *sc) 422 { 423 struct mii_data *mii = sc->mii_pdata; 424 int bmcr, bmsr, ssr; 425 426 mii->mii_media_status = IFM_AVALID; 427 mii->mii_media_active = IFM_ETHER; 428 429 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR); 430 bmcr = PHY_READ(sc, E1000_CR); 431 ssr = PHY_READ(sc, E1000_SSR); 432 433 if (bmsr & E1000_SR_LINK_STATUS) 434 mii->mii_media_status |= IFM_ACTIVE; 435 436 if (bmcr & E1000_CR_LOOPBACK) 437 mii->mii_media_active |= IFM_LOOP; 438 439 if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 && 440 (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) { 441 /* Erg, still trying, I guess... */ 442 mii->mii_media_active |= IFM_NONE; 443 return; 444 } 445 446 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 447 switch (ssr & E1000_SSR_SPEED) { 448 case E1000_SSR_1000MBS: 449 mii->mii_media_active |= IFM_1000_T; 450 break; 451 case E1000_SSR_100MBS: 452 mii->mii_media_active |= IFM_100_TX; 453 break; 454 case E1000_SSR_10MBS: 455 mii->mii_media_active |= IFM_10_T; 456 break; 457 default: 458 mii->mii_media_active |= IFM_NONE; 459 return; 460 } 461 } else { 462 /* 463 * Some fiber PHY(88E1112) does not seem to set resolved 464 * speed so always assume we've got IFM_1000_SX. 465 */ 466 mii->mii_media_active |= IFM_1000_SX; 467 } 468 469 if (ssr & E1000_SSR_DUPLEX) { 470 mii->mii_media_active |= IFM_FDX; 471 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) 472 mii->mii_media_active |= mii_phy_flowstatus(sc); 473 } else 474 mii->mii_media_active |= IFM_HDX; 475 476 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 477 if (((PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR)) & 478 E1000_1GSR_MS_CONFIG_RES) != 0) 479 mii->mii_media_active |= IFM_ETH_MASTER; 480 } 481 } 482 483 static int 484 e1000phy_mii_phy_auto(struct mii_softc *sc, int media) 485 { 486 uint16_t reg; 487 488 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 489 reg = PHY_READ(sc, E1000_AR); 490 reg &= ~(E1000_AR_PAUSE | E1000_AR_ASM_DIR); 491 reg |= E1000_AR_10T | E1000_AR_10T_FD | 492 E1000_AR_100TX | E1000_AR_100TX_FD; 493 if ((media & IFM_FLOW) != 0 || 494 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 495 reg |= E1000_AR_PAUSE | E1000_AR_ASM_DIR; 496 PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD); 497 } else 498 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X); 499 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 500 PHY_WRITE(sc, E1000_1GCR, 501 E1000_1GCR_1000T_FD | E1000_1GCR_1000T); 502 PHY_WRITE(sc, E1000_CR, 503 E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG); 504 505 return (EJUSTRETURN); 506 } 507