1 /*- 2 * Principal Author: Parag Patel 3 * Copyright (c) 2001 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Additonal Copyright (c) 2001 by Traakan Software under same licence. 29 * Secondary Author: Matthew Jacob 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY. 37 */ 38 39 /* 40 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and 41 * 1000baseSX PHY. 42 * Nathan Binkert <nate@openbsd.org> 43 * Jung-uk Kim <jkim@niksun.com> 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/module.h> 50 #include <sys/socket.h> 51 #include <sys/bus.h> 52 53 54 #include <net/if.h> 55 #include <net/if_media.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 #include "miidevs.h" 60 61 #include <dev/mii/e1000phyreg.h> 62 63 #include "miibus_if.h" 64 65 static int e1000phy_probe(device_t); 66 static int e1000phy_attach(device_t); 67 68 struct e1000phy_softc { 69 struct mii_softc mii_sc; 70 int mii_model; 71 }; 72 73 static device_method_t e1000phy_methods[] = { 74 /* device interface */ 75 DEVMETHOD(device_probe, e1000phy_probe), 76 DEVMETHOD(device_attach, e1000phy_attach), 77 DEVMETHOD(device_detach, mii_phy_detach), 78 DEVMETHOD(device_shutdown, bus_generic_shutdown), 79 { 0, 0 } 80 }; 81 82 static devclass_t e1000phy_devclass; 83 static driver_t e1000phy_driver = { 84 "e1000phy", 85 e1000phy_methods, 86 sizeof(struct e1000phy_softc) 87 }; 88 89 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0); 90 91 static int e1000phy_service(struct mii_softc *, struct mii_data *, int); 92 static void e1000phy_status(struct mii_softc *); 93 static void e1000phy_reset(struct mii_softc *); 94 static int e1000phy_mii_phy_auto(struct e1000phy_softc *); 95 96 static const struct mii_phydesc e1000phys[] = { 97 MII_PHY_DESC(MARVELL, E1000), 98 MII_PHY_DESC(MARVELL, E1011), 99 MII_PHY_DESC(MARVELL, E1000_3), 100 MII_PHY_DESC(MARVELL, E1000S), 101 MII_PHY_DESC(MARVELL, E1000_5), 102 MII_PHY_DESC(MARVELL, E1000_6), 103 MII_PHY_DESC(MARVELL, E3082), 104 MII_PHY_DESC(MARVELL, E1112), 105 MII_PHY_DESC(MARVELL, E1149), 106 MII_PHY_DESC(MARVELL, E1111), 107 MII_PHY_DESC(MARVELL, E1116), 108 MII_PHY_DESC(MARVELL, E1116R), 109 MII_PHY_DESC(MARVELL, E1118), 110 MII_PHY_DESC(MARVELL, E3016), 111 MII_PHY_DESC(xxMARVELL, E1000), 112 MII_PHY_DESC(xxMARVELL, E1011), 113 MII_PHY_DESC(xxMARVELL, E1000_3), 114 MII_PHY_DESC(xxMARVELL, E1000_5), 115 MII_PHY_DESC(xxMARVELL, E1111), 116 MII_PHY_END 117 }; 118 119 static int 120 e1000phy_probe(device_t dev) 121 { 122 123 return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT)); 124 } 125 126 static int 127 e1000phy_attach(device_t dev) 128 { 129 struct e1000phy_softc *esc; 130 struct mii_softc *sc; 131 struct mii_attach_args *ma; 132 struct mii_data *mii; 133 134 esc = device_get_softc(dev); 135 sc = &esc->mii_sc; 136 ma = device_get_ivars(dev); 137 sc->mii_dev = device_get_parent(dev); 138 mii = device_get_softc(sc->mii_dev); 139 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 140 141 sc->mii_inst = mii->mii_instance; 142 sc->mii_phy = ma->mii_phyno; 143 sc->mii_service = e1000phy_service; 144 sc->mii_pdata = mii; 145 mii->mii_instance++; 146 147 esc->mii_model = MII_MODEL(ma->mii_id2); 148 switch (esc->mii_model) { 149 case MII_MODEL_MARVELL_E1011: 150 case MII_MODEL_MARVELL_E1112: 151 if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK) 152 sc->mii_flags |= MIIF_HAVEFIBER; 153 break; 154 case MII_MODEL_MARVELL_E1149: 155 /* 156 * Some 88E1149 PHY's page select is initialized to 157 * point to other bank instead of copper/fiber bank 158 * which in turn resulted in wrong registers were 159 * accessed during PHY operation. It is believed that 160 * page 0 should be used for copper PHY so reinitialize 161 * E1000_EADR to select default copper PHY. If parent 162 * device know the type of PHY(either copper or fiber), 163 * that information should be used to select default 164 * type of PHY. 165 */ 166 PHY_WRITE(sc, E1000_EADR, 0); 167 break; 168 } 169 170 e1000phy_reset(sc); 171 172 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 173 if (sc->mii_capabilities & BMSR_EXTSTAT) 174 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 175 device_printf(dev, " "); 176 mii_phy_add_media(sc); 177 printf("\n"); 178 179 MIIBUS_MEDIAINIT(sc->mii_dev); 180 return (0); 181 } 182 183 static void 184 e1000phy_reset(struct mii_softc *sc) 185 { 186 struct e1000phy_softc *esc; 187 uint16_t reg, page; 188 189 esc = (struct e1000phy_softc *)sc; 190 reg = PHY_READ(sc, E1000_SCR); 191 if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) { 192 reg &= ~E1000_SCR_AUTO_X_MODE; 193 PHY_WRITE(sc, E1000_SCR, reg); 194 if (esc->mii_model == MII_MODEL_MARVELL_E1112) { 195 /* Select 1000BASE-X only mode. */ 196 page = PHY_READ(sc, E1000_EADR); 197 PHY_WRITE(sc, E1000_EADR, 2); 198 reg = PHY_READ(sc, E1000_SCR); 199 reg &= ~E1000_SCR_MODE_MASK; 200 reg |= E1000_SCR_MODE_1000BX; 201 PHY_WRITE(sc, E1000_SCR, reg); 202 PHY_WRITE(sc, E1000_EADR, page); 203 } 204 } else { 205 switch (esc->mii_model) { 206 case MII_MODEL_MARVELL_E1111: 207 case MII_MODEL_MARVELL_E1112: 208 case MII_MODEL_MARVELL_E1116: 209 case MII_MODEL_MARVELL_E1118: 210 case MII_MODEL_MARVELL_E1149: 211 /* Disable energy detect mode. */ 212 reg &= ~E1000_SCR_EN_DETECT_MASK; 213 reg |= E1000_SCR_AUTO_X_MODE; 214 if (esc->mii_model == MII_MODEL_MARVELL_E1116) 215 reg &= ~E1000_SCR_POWER_DOWN; 216 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 217 break; 218 case MII_MODEL_MARVELL_E3082: 219 reg |= (E1000_SCR_AUTO_X_MODE >> 1); 220 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 221 break; 222 case MII_MODEL_MARVELL_E3016: 223 reg |= E1000_SCR_AUTO_MDIX; 224 reg &= ~(E1000_SCR_EN_DETECT | 225 E1000_SCR_SCRAMBLER_DISABLE); 226 reg |= E1000_SCR_LPNP; 227 /* XXX Enable class A driver for Yukon FE+ A0. */ 228 PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001); 229 break; 230 default: 231 reg &= ~E1000_SCR_AUTO_X_MODE; 232 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 233 break; 234 } 235 if (esc->mii_model != MII_MODEL_MARVELL_E3016) { 236 /* Auto correction for reversed cable polarity. */ 237 reg &= ~E1000_SCR_POLARITY_REVERSAL; 238 } 239 PHY_WRITE(sc, E1000_SCR, reg); 240 241 if (esc->mii_model == MII_MODEL_MARVELL_E1116) { 242 PHY_WRITE(sc, E1000_EADR, 2); 243 reg = PHY_READ(sc, E1000_SCR); 244 reg |= E1000_SCR_RGMII_POWER_UP; 245 PHY_WRITE(sc, E1000_SCR, reg); 246 PHY_WRITE(sc, E1000_EADR, 0); 247 } 248 } 249 250 switch (MII_MODEL(esc->mii_model)) { 251 case MII_MODEL_MARVELL_E3082: 252 case MII_MODEL_MARVELL_E1112: 253 case MII_MODEL_MARVELL_E1116: 254 case MII_MODEL_MARVELL_E1118: 255 case MII_MODEL_MARVELL_E1149: 256 break; 257 case MII_MODEL_MARVELL_E3016: 258 /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */ 259 PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04); 260 /* Integrated register calibration workaround. */ 261 PHY_WRITE(sc, 0x1D, 17); 262 PHY_WRITE(sc, 0x1E, 0x3F60); 263 break; 264 default: 265 /* Force TX_CLK to 25MHz clock. */ 266 reg = PHY_READ(sc, E1000_ESCR); 267 reg |= E1000_ESCR_TX_CLK_25; 268 PHY_WRITE(sc, E1000_ESCR, reg); 269 break; 270 } 271 272 /* Reset the PHY so all changes take effect. */ 273 reg = PHY_READ(sc, E1000_CR); 274 reg |= E1000_CR_RESET; 275 PHY_WRITE(sc, E1000_CR, reg); 276 } 277 278 static int 279 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 280 { 281 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 282 struct e1000phy_softc *esc = (struct e1000phy_softc *)sc; 283 uint16_t speed, gig; 284 int reg; 285 286 switch (cmd) { 287 case MII_POLLSTAT: 288 /* 289 * If we're not polling our PHY instance, just return. 290 */ 291 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 292 return (0); 293 break; 294 295 case MII_MEDIACHG: 296 /* 297 * If the media indicates a different PHY instance, 298 * isolate ourselves. 299 */ 300 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 301 reg = PHY_READ(sc, E1000_CR); 302 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_ISOLATE); 303 return (0); 304 } 305 306 /* 307 * If the interface is not up, don't do anything. 308 */ 309 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 310 break; 311 312 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 313 e1000phy_mii_phy_auto(esc); 314 break; 315 } 316 317 speed = 0; 318 switch (IFM_SUBTYPE(ife->ifm_media)) { 319 case IFM_1000_T: 320 if ((sc->mii_extcapabilities & 321 (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0) 322 return (EINVAL); 323 speed = E1000_CR_SPEED_1000; 324 break; 325 case IFM_1000_SX: 326 if ((sc->mii_extcapabilities & 327 (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0) 328 return (EINVAL); 329 speed = E1000_CR_SPEED_1000; 330 break; 331 case IFM_100_TX: 332 speed = E1000_CR_SPEED_100; 333 break; 334 case IFM_10_T: 335 speed = E1000_CR_SPEED_10; 336 break; 337 case IFM_NONE: 338 reg = PHY_READ(sc, E1000_CR); 339 PHY_WRITE(sc, E1000_CR, 340 reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN); 341 goto done; 342 default: 343 return (EINVAL); 344 } 345 346 if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) { 347 speed |= E1000_CR_FULL_DUPLEX; 348 gig = E1000_1GCR_1000T_FD; 349 } else 350 gig = E1000_1GCR_1000T; 351 352 reg = PHY_READ(sc, E1000_CR); 353 reg &= ~E1000_CR_AUTO_NEG_ENABLE; 354 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET); 355 356 /* 357 * When setting the link manually, one side must 358 * be the master and the other the slave. However 359 * ifmedia doesn't give us a good way to specify 360 * this, so we fake it by using one of the LINK 361 * flags. If LINK0 is set, we program the PHY to 362 * be a master, otherwise it's a slave. 363 */ 364 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T || 365 (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_SX)) { 366 if ((mii->mii_ifp->if_flags & IFF_LINK0)) 367 PHY_WRITE(sc, E1000_1GCR, gig | 368 E1000_1GCR_MS_ENABLE | E1000_1GCR_MS_VALUE); 369 else 370 PHY_WRITE(sc, E1000_1GCR, gig | 371 E1000_1GCR_MS_ENABLE); 372 } else { 373 if ((sc->mii_extcapabilities & 374 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 375 PHY_WRITE(sc, E1000_1GCR, 0); 376 } 377 PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD); 378 PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET); 379 done: 380 break; 381 case MII_TICK: 382 /* 383 * If we're not currently selected, just return. 384 */ 385 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 386 return (0); 387 388 /* 389 * Is the interface even up? 390 */ 391 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 392 return (0); 393 394 /* 395 * Only used for autonegotiation. 396 */ 397 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 398 sc->mii_ticks = 0; 399 break; 400 } 401 402 /* 403 * check for link. 404 * Read the status register twice; BMSR_LINK is latch-low. 405 */ 406 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 407 if (reg & BMSR_LINK) { 408 sc->mii_ticks = 0; 409 break; 410 } 411 412 /* Announce link loss right after it happens. */ 413 if (sc->mii_ticks++ == 0) 414 break; 415 if (sc->mii_ticks <= sc->mii_anegticks) 416 break; 417 418 sc->mii_ticks = 0; 419 e1000phy_reset(sc); 420 e1000phy_mii_phy_auto(esc); 421 break; 422 } 423 424 /* Update the media status. */ 425 e1000phy_status(sc); 426 427 /* Callback if something changed. */ 428 mii_phy_update(sc, cmd); 429 return (0); 430 } 431 432 static void 433 e1000phy_status(struct mii_softc *sc) 434 { 435 struct mii_data *mii = sc->mii_pdata; 436 int bmcr, bmsr, gsr, ssr, ar, lpar; 437 438 mii->mii_media_status = IFM_AVALID; 439 mii->mii_media_active = IFM_ETHER; 440 441 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR); 442 bmcr = PHY_READ(sc, E1000_CR); 443 ssr = PHY_READ(sc, E1000_SSR); 444 445 if (bmsr & E1000_SR_LINK_STATUS) 446 mii->mii_media_status |= IFM_ACTIVE; 447 448 if (bmcr & E1000_CR_LOOPBACK) 449 mii->mii_media_active |= IFM_LOOP; 450 451 if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 && 452 (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) { 453 /* Erg, still trying, I guess... */ 454 mii->mii_media_active |= IFM_NONE; 455 return; 456 } 457 458 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 459 switch (ssr & E1000_SSR_SPEED) { 460 case E1000_SSR_1000MBS: 461 mii->mii_media_active |= IFM_1000_T; 462 break; 463 case E1000_SSR_100MBS: 464 mii->mii_media_active |= IFM_100_TX; 465 break; 466 case E1000_SSR_10MBS: 467 mii->mii_media_active |= IFM_10_T; 468 break; 469 default: 470 mii->mii_media_active |= IFM_NONE; 471 return; 472 } 473 } else { 474 if (ssr & E1000_SSR_1000MBS) 475 mii->mii_media_active |= IFM_1000_SX; 476 } 477 478 if (ssr & E1000_SSR_DUPLEX) 479 mii->mii_media_active |= IFM_FDX; 480 else 481 mii->mii_media_active |= IFM_HDX; 482 483 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 484 ar = PHY_READ(sc, E1000_AR); 485 lpar = PHY_READ(sc, E1000_LPAR); 486 /* FLAG0==rx-flow-control FLAG1==tx-flow-control */ 487 if ((ar & E1000_AR_PAUSE) && (lpar & E1000_LPAR_PAUSE)) { 488 mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1; 489 } else if (!(ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) && 490 (lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) { 491 mii->mii_media_active |= IFM_FLAG1; 492 } else if ((ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) && 493 !(lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) { 494 mii->mii_media_active |= IFM_FLAG0; 495 } 496 } 497 498 /* FLAG2 : local PHY resolved to MASTER */ 499 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) || 500 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)) { 501 PHY_READ(sc, E1000_1GSR); 502 gsr = PHY_READ(sc, E1000_1GSR); 503 if ((gsr & E1000_1GSR_MS_CONFIG_RES) != 0) 504 mii->mii_media_active |= IFM_FLAG2; 505 } 506 } 507 508 static int 509 e1000phy_mii_phy_auto(struct e1000phy_softc *esc) 510 { 511 struct mii_softc *sc; 512 uint16_t reg; 513 514 sc = &esc->mii_sc; 515 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 516 reg = PHY_READ(sc, E1000_AR); 517 reg |= E1000_AR_10T | E1000_AR_10T_FD | 518 E1000_AR_100TX | E1000_AR_100TX_FD | 519 E1000_AR_PAUSE | E1000_AR_ASM_DIR; 520 PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD); 521 } else 522 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X | 523 E1000_FA_SYM_PAUSE | E1000_FA_ASYM_PAUSE); 524 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 525 PHY_WRITE(sc, E1000_1GCR, 526 E1000_1GCR_1000T_FD | E1000_1GCR_1000T); 527 PHY_WRITE(sc, E1000_CR, 528 E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG); 529 530 return (EJUSTRETURN); 531 } 532