1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 __FBSDID("$FreeBSD$"); 28 29 #ifndef __IOAT_HW_H__ 30 #define __IOAT_HW_H__ 31 32 #define IOAT_MAX_CHANNELS 32 33 34 #define IOAT_CHANCNT_OFFSET 0x00 35 36 #define IOAT_XFERCAP_OFFSET 0x01 37 38 #define IOAT_GENCTRL_OFFSET 0x02 39 40 #define IOAT_INTRCTRL_OFFSET 0x03 41 #define IOAT_INTRCTRL_MASTER_INT_EN 0x01 42 43 #define IOAT_ATTNSTATUS_OFFSET 0x04 44 45 #define IOAT_CBVER_OFFSET 0x08 46 47 #define IOAT_VER_3_0 0x30 48 #define IOAT_VER_3_3 0x33 49 50 #define IOAT_INTRDELAY_OFFSET 0x0C 51 52 #define IOAT_CS_STATUS_OFFSET 0x0E 53 54 #define IOAT_DMACAPABILITY_OFFSET 0x10 55 56 /* DMA Channel Registers */ 57 #define IOAT_CHANCTRL_OFFSET 0x80 58 #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 59 #define IOAT_CHANCTRL_COMPL_DCA_EN 0x0200 60 #define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 61 #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 62 #define IOAT_CHANCTRL_ERR_INT_EN 0x0010 63 #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 64 #define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 65 #define IOAT_CHANCTRL_INT_REARM 0x0001 66 #define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\ 67 IOAT_CHANCTRL_ANY_ERR_ABORT_EN) 68 69 #define IOAT_CHANCMD_OFFSET 0x84 70 #define IOAT_CHANCMD_RESET 0x20 71 #define IOAT_CHANCMD_SUSPEND 0x04 72 73 #define IOAT_DMACOUNT_OFFSET 0x86 74 75 #define IOAT_CHANSTS_OFFSET_LOW 0x88 76 #define IOAT_CHANSTS_OFFSET_HIGH 0x8C 77 #define IOAT_CHANSTS_OFFSET 0x88 78 79 #define IOAT_CHANSTS_STATUS 0x7ULL 80 #define IOAT_CHANSTS_ACTIVE 0x0 81 #define IOAT_CHANSTS_IDLE 0x1 82 #define IOAT_CHANSTS_SUSPENDED 0x2 83 #define IOAT_CHANSTS_HALTED 0x3 84 85 #define IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL 86 #define IOAT_CHANSTS_SOFT_ERROR 0x10ULL 87 88 #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK (~0x3FULL) 89 90 #define IOAT_CHAINADDR_OFFSET_LOW 0x90 91 #define IOAT_CHAINADDR_OFFSET_HIGH 0x94 92 93 #define IOAT_CHANCMP_OFFSET_LOW 0x98 94 #define IOAT_CHANCMP_OFFSET_HIGH 0x9C 95 96 #define IOAT_CHANERR_OFFSET 0xA8 97 98 #define IOAT_CFG_CHANERR_INT_OFFSET 0x180 99 #define IOAT_CFG_CHANERRMASK_INT_OFFSET 0x184 100 101 #define IOAT_MIN_ORDER 4 102 #define IOAT_MAX_ORDER 16 103 104 #endif /* __IOAT_HW_H__ */ 105