1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/proc.h> 36 #include <sys/rman.h> 37 38 #include <machine/bus.h> 39 #include <machine/resource.h> 40 41 #include <dev/spibus/spi.h> 42 #include <dev/spibus/spibusvar.h> 43 44 #include <dev/intel/spi.h> 45 46 /** 47 * Macros for driver mutex locking 48 */ 49 #define INTELSPI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 50 #define INTELSPI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 51 #define INTELSPI_LOCK_INIT(_sc) \ 52 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 53 "intelspi", MTX_DEF) 54 #define INTELSPI_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 55 #define INTELSPI_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 56 #define INTELSPI_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 57 58 #define INTELSPI_WRITE(_sc, _off, _val) \ 59 bus_write_4((_sc)->sc_mem_res, (_off), (_val)) 60 #define INTELSPI_READ(_sc, _off) \ 61 bus_read_4((_sc)->sc_mem_res, (_off)) 62 63 #define INTELSPI_BUSY 0x1 64 #define TX_FIFO_THRESHOLD 2 65 #define RX_FIFO_THRESHOLD 2 66 #define CLOCK_DIV_10MHZ 5 67 #define DATA_SIZE_8BITS 8 68 #define MAX_CLOCK_RATE 50000000 69 70 #define CS_LOW 0 71 #define CS_HIGH 1 72 73 #define INTELSPI_SSPREG_SSCR0 0x0 74 #define SSCR0_SCR(n) ((((n) - 1) & 0xfff) << 8) 75 #define SSCR0_SSE (1 << 7) 76 #define SSCR0_FRF_SPI (0 << 4) 77 #define SSCR0_DSS(n) (((n) - 1) << 0) 78 #define INTELSPI_SSPREG_SSCR1 0x4 79 #define SSCR1_TINTE (1 << 19) 80 #define SSCR1_RFT(n) (((n) - 1) << 10) 81 #define SSCR1_RFT_MASK (0xf << 10) 82 #define SSCR1_TFT(n) (((n) - 1) << 6) 83 #define SSCR1_SPI_SPH (1 << 4) 84 #define SSCR1_SPI_SPO (1 << 3) 85 #define SSCR1_MODE_MASK (SSCR1_SPI_SPO | SSCR1_SPI_SPH) 86 #define SSCR1_TIE (1 << 1) 87 #define SSCR1_RIE (1 << 0) 88 #define INTELSPI_SSPREG_SSSR 0x8 89 #define SSSR_RFL_MASK (0xf << 12) 90 #define SSSR_TFL_MASK (0xf << 8) 91 #define SSSR_RNE (1 << 3) 92 #define SSSR_TNF (1 << 2) 93 #define INTELSPI_SSPREG_SSITR 0xC 94 #define INTELSPI_SSPREG_SSDR 0x10 95 #define INTELSPI_SSPREG_SSTO 0x28 96 #define INTELSPI_SSPREG_SSPSP 0x2C 97 #define INTELSPI_SSPREG_SSTSA 0x30 98 #define INTELSPI_SSPREG_SSRSA 0x34 99 #define INTELSPI_SSPREG_SSTSS 0x38 100 #define INTELSPI_SSPREG_SSACD 0x3C 101 #define INTELSPI_SSPREG_ITF 0x40 102 #define INTELSPI_SSPREG_SITF 0x44 103 #define INTELSPI_SSPREG_SIRF 0x48 104 #define SPI_CS_CTRL(sc) \ 105 (intelspi_infos[sc->sc_vers].reg_lpss_base + \ 106 intelspi_infos[sc->sc_vers].reg_cs_ctrl) 107 #define SPI_CS_CTRL_CS_MASK (3) 108 #define SPI_CS_CTRL_SW_MODE (1 << 0) 109 #define SPI_CS_CTRL_HW_MODE (1 << 0) 110 #define SPI_CS_CTRL_CS_HIGH (1 << 1) 111 112 static void intelspi_intr(void *); 113 114 static int 115 intelspi_txfifo_full(struct intelspi_softc *sc) 116 { 117 uint32_t sssr; 118 119 INTELSPI_ASSERT_LOCKED(sc); 120 121 sssr = INTELSPI_READ(sc, INTELSPI_SSPREG_SSSR); 122 if (sssr & SSSR_TNF) 123 return (0); 124 125 return (1); 126 } 127 128 static int 129 intelspi_rxfifo_empty(struct intelspi_softc *sc) 130 { 131 uint32_t sssr; 132 133 INTELSPI_ASSERT_LOCKED(sc); 134 135 sssr = INTELSPI_READ(sc, INTELSPI_SSPREG_SSSR); 136 if (sssr & SSSR_RNE) 137 return (0); 138 else 139 return (1); 140 } 141 142 static void 143 intelspi_fill_tx_fifo(struct intelspi_softc *sc) 144 { 145 struct spi_command *cmd; 146 uint32_t written; 147 uint8_t *data; 148 149 INTELSPI_ASSERT_LOCKED(sc); 150 151 cmd = sc->sc_cmd; 152 while (sc->sc_written < sc->sc_len && 153 !intelspi_txfifo_full(sc)) { 154 data = (uint8_t *)cmd->tx_cmd; 155 written = sc->sc_written++; 156 157 if (written >= cmd->tx_cmd_sz) { 158 data = (uint8_t *)cmd->tx_data; 159 written -= cmd->tx_cmd_sz; 160 } 161 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSDR, data[written]); 162 } 163 } 164 165 static void 166 intelspi_drain_rx_fifo(struct intelspi_softc *sc) 167 { 168 struct spi_command *cmd; 169 uint32_t read; 170 uint8_t *data; 171 172 INTELSPI_ASSERT_LOCKED(sc); 173 174 cmd = sc->sc_cmd; 175 while (sc->sc_read < sc->sc_len && 176 !intelspi_rxfifo_empty(sc)) { 177 data = (uint8_t *)cmd->rx_cmd; 178 read = sc->sc_read++; 179 if (read >= cmd->rx_cmd_sz) { 180 data = (uint8_t *)cmd->rx_data; 181 read -= cmd->rx_cmd_sz; 182 } 183 data[read] = INTELSPI_READ(sc, INTELSPI_SSPREG_SSDR) & 0xff; 184 } 185 } 186 187 static int 188 intelspi_transaction_done(struct intelspi_softc *sc) 189 { 190 int txfifo_empty; 191 uint32_t sssr; 192 193 INTELSPI_ASSERT_LOCKED(sc); 194 195 if (sc->sc_written != sc->sc_len || 196 sc->sc_read != sc->sc_len) 197 return (0); 198 199 sssr = INTELSPI_READ(sc, INTELSPI_SSPREG_SSSR); 200 txfifo_empty = ((sssr & SSSR_TFL_MASK) == 0) && 201 (sssr & SSSR_TNF); 202 203 if (txfifo_empty && !(sssr & SSSR_RNE)) 204 return (1); 205 206 return (0); 207 } 208 209 static int 210 intelspi_transact(struct intelspi_softc *sc) 211 { 212 213 INTELSPI_ASSERT_LOCKED(sc); 214 215 /* TX - Fill up the FIFO. */ 216 intelspi_fill_tx_fifo(sc); 217 218 /* RX - Drain the FIFO. */ 219 intelspi_drain_rx_fifo(sc); 220 221 /* Check for end of transfer. */ 222 return intelspi_transaction_done(sc); 223 } 224 225 static void 226 intelspi_intr(void *arg) 227 { 228 struct intelspi_softc *sc; 229 uint32_t reg; 230 231 sc = (struct intelspi_softc *)arg; 232 233 INTELSPI_LOCK(sc); 234 if ((sc->sc_flags & INTELSPI_BUSY) == 0) { 235 INTELSPI_UNLOCK(sc); 236 return; 237 } 238 239 /* Check if SSP if off */ 240 reg = INTELSPI_READ(sc, INTELSPI_SSPREG_SSSR); 241 if (reg == 0xffffffffU) { 242 INTELSPI_UNLOCK(sc); 243 return; 244 } 245 246 /* Check for end of transfer. */ 247 if (intelspi_transact(sc)) { 248 /* Disable interrupts */ 249 reg = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR1); 250 reg &= ~(SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE); 251 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, reg); 252 wakeup(sc->sc_dev); 253 } 254 255 INTELSPI_UNLOCK(sc); 256 } 257 258 static void 259 intelspi_init(struct intelspi_softc *sc) 260 { 261 uint32_t reg; 262 263 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR0, 0); 264 265 /* Manual CS control */ 266 reg = INTELSPI_READ(sc, SPI_CS_CTRL(sc)); 267 reg &= ~(SPI_CS_CTRL_CS_MASK); 268 reg |= (SPI_CS_CTRL_SW_MODE | SPI_CS_CTRL_CS_HIGH); 269 INTELSPI_WRITE(sc, SPI_CS_CTRL(sc), reg); 270 271 /* Set TX/RX FIFO IRQ threshold levels */ 272 reg = SSCR1_TFT(TX_FIFO_THRESHOLD) | SSCR1_RFT(RX_FIFO_THRESHOLD); 273 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, reg); 274 275 reg = SSCR0_SCR(CLOCK_DIV_10MHZ); 276 /* Put SSP in SPI mode */ 277 reg |= SSCR0_FRF_SPI; 278 /* Data size */ 279 reg |= SSCR0_DSS(DATA_SIZE_8BITS); 280 /* Enable SSP */ 281 reg |= SSCR0_SSE; 282 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR0, reg); 283 } 284 285 static void 286 intelspi_set_cs(struct intelspi_softc *sc, int level) 287 { 288 uint32_t reg; 289 290 reg = INTELSPI_READ(sc, SPI_CS_CTRL(sc)); 291 reg &= ~(SPI_CS_CTRL_CS_MASK); 292 reg |= SPI_CS_CTRL_SW_MODE; 293 294 if (level == CS_HIGH) 295 reg |= SPI_CS_CTRL_CS_HIGH; 296 297 INTELSPI_WRITE(sc, SPI_CS_CTRL(sc), reg); 298 } 299 300 int 301 intelspi_transfer(device_t dev, device_t child, struct spi_command *cmd) 302 { 303 struct intelspi_softc *sc; 304 int err, poll_limit; 305 uint32_t sscr0, sscr1, mode, clock, cs_delay; 306 bool restart = false; 307 308 sc = device_get_softc(dev); 309 err = 0; 310 311 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, 312 ("TX/RX command sizes should be equal")); 313 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, 314 ("TX/RX data sizes should be equal")); 315 316 INTELSPI_LOCK(sc); 317 318 /* If the controller is in use wait until it is available. */ 319 while (sc->sc_flags & INTELSPI_BUSY) { 320 if ((cmd->flags & SPI_FLAG_NO_SLEEP) == SPI_FLAG_NO_SLEEP) 321 return (EBUSY); 322 err = mtx_sleep(dev, &sc->sc_mtx, 0, "intelspi", 0); 323 if (err == EINTR) { 324 INTELSPI_UNLOCK(sc); 325 return (err); 326 } 327 } 328 329 /* Now we have control over SPI controller. */ 330 sc->sc_flags = INTELSPI_BUSY; 331 332 /* Configure the clock rate and SPI mode. */ 333 spibus_get_clock(child, &clock); 334 spibus_get_mode(child, &mode); 335 336 if (clock != sc->sc_clock || mode != sc->sc_mode) { 337 sscr0 = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR0); 338 sscr0 &= ~SSCR0_SSE; 339 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR0, sscr0); 340 restart = true; 341 } 342 343 if (clock != sc->sc_clock) { 344 sscr0 = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR0); 345 sscr0 &= ~SSCR0_SCR(0xfff); 346 if (clock == 0) 347 sscr0 |= SSCR0_SCR(CLOCK_DIV_10MHZ); 348 else 349 sscr0 |= SSCR0_SCR(howmany(MAX_CLOCK_RATE, min(MAX_CLOCK_RATE, clock))); 350 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR0, sscr0); 351 sc->sc_clock = clock; 352 } 353 354 if (mode != sc->sc_mode) { 355 sscr1 = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR1); 356 sscr1 &= ~SSCR1_MODE_MASK; 357 if (mode & SPIBUS_MODE_CPHA) 358 sscr1 |= SSCR1_SPI_SPH; 359 if (mode & SPIBUS_MODE_CPOL) 360 sscr1 |= SSCR1_SPI_SPO; 361 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, sscr1); 362 sc->sc_mode = mode; 363 } 364 365 if (restart) { 366 sscr0 = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR0); 367 sscr0 |= SSCR0_SSE; 368 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR0, sscr0); 369 } 370 371 /* Save a pointer to the SPI command. */ 372 sc->sc_cmd = cmd; 373 sc->sc_read = 0; 374 sc->sc_written = 0; 375 sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz; 376 377 /* Enable CS */ 378 intelspi_set_cs(sc, CS_LOW); 379 380 /* Wait the CS delay */ 381 spibus_get_cs_delay(child, &cs_delay); 382 DELAY(cs_delay); 383 384 /* Transfer as much as possible to FIFOs */ 385 if ((cmd->flags & SPI_FLAG_NO_SLEEP) == SPI_FLAG_NO_SLEEP) { 386 /* We cannot wait with mtx_sleep if we're called from e.g. an ithread */ 387 poll_limit = 2000; 388 while (!intelspi_transact(sc) && poll_limit-- > 0) 389 DELAY(1000); 390 if (poll_limit == 0) { 391 device_printf(dev, "polling was stuck, transaction not finished\n"); 392 err = EIO; 393 } 394 } else { 395 if (!intelspi_transact(sc)) { 396 /* If FIFO is not large enough - enable interrupts */ 397 sscr1 = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR1); 398 sscr1 |= (SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE); 399 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, sscr1); 400 401 /* and wait for transaction to complete */ 402 err = mtx_sleep(dev, &sc->sc_mtx, 0, "intelspi", hz * 2); 403 } 404 } 405 406 /* De-assert CS */ 407 if ((cmd->flags & SPI_FLAG_KEEP_CS) == 0) 408 intelspi_set_cs(sc, CS_HIGH); 409 410 /* Clear transaction details */ 411 sc->sc_cmd = NULL; 412 sc->sc_read = 0; 413 sc->sc_written = 0; 414 sc->sc_len = 0; 415 416 /* Make sure the SPI engine and interrupts are disabled. */ 417 sscr1 = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR1); 418 sscr1 &= ~(SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE); 419 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, sscr1); 420 421 /* Release the controller and wakeup the next thread waiting for it. */ 422 sc->sc_flags = 0; 423 wakeup_one(dev); 424 INTELSPI_UNLOCK(sc); 425 426 /* 427 * Check for transfer timeout. The SPI controller doesn't 428 * return errors. 429 */ 430 if (err == EWOULDBLOCK) { 431 device_printf(sc->sc_dev, "transfer timeout\n"); 432 err = EIO; 433 } 434 435 return (err); 436 } 437 438 int 439 intelspi_attach(device_t dev) 440 { 441 struct intelspi_softc *sc; 442 443 sc = device_get_softc(dev); 444 sc->sc_dev = dev; 445 446 INTELSPI_LOCK_INIT(sc); 447 448 sc->sc_mem_res = bus_alloc_resource_any(sc->sc_dev, 449 SYS_RES_MEMORY, &sc->sc_mem_rid, RF_ACTIVE); 450 if (sc->sc_mem_res == NULL) { 451 device_printf(dev, "can't allocate memory resource\n"); 452 goto error; 453 } 454 455 sc->sc_irq_res = bus_alloc_resource_any(sc->sc_dev, 456 SYS_RES_IRQ, &sc->sc_irq_rid, RF_ACTIVE | RF_SHAREABLE); 457 if (sc->sc_irq_res == NULL) { 458 device_printf(dev, "can't allocate IRQ resource\n"); 459 goto error; 460 } 461 462 /* Hook up our interrupt handler. */ 463 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 464 NULL, intelspi_intr, sc, &sc->sc_irq_ih)) { 465 device_printf(dev, "cannot setup the interrupt handler\n"); 466 goto error; 467 } 468 469 intelspi_init(sc); 470 471 device_add_child(dev, "spibus", -1); 472 473 return (bus_delayed_attach_children(dev)); 474 475 error: 476 INTELSPI_LOCK_DESTROY(sc); 477 478 if (sc->sc_mem_res != NULL) 479 bus_release_resource(dev, SYS_RES_MEMORY, 480 sc->sc_mem_rid, sc->sc_mem_res); 481 482 if (sc->sc_irq_res != NULL) 483 bus_release_resource(dev, SYS_RES_IRQ, 484 sc->sc_irq_rid, sc->sc_irq_res); 485 486 return (ENXIO); 487 } 488 489 int 490 intelspi_detach(device_t dev) 491 { 492 struct intelspi_softc *sc; 493 494 sc = device_get_softc(dev); 495 496 INTELSPI_LOCK_DESTROY(sc); 497 498 if (sc->sc_irq_ih) 499 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_ih); 500 501 if (sc->sc_mem_res != NULL) 502 bus_release_resource(dev, SYS_RES_MEMORY, 503 sc->sc_mem_rid, sc->sc_mem_res); 504 505 if (sc->sc_irq_res != NULL) 506 bus_release_resource(dev, SYS_RES_IRQ, 507 sc->sc_irq_rid, sc->sc_irq_res); 508 509 return (bus_generic_detach(dev)); 510 } 511 512 int 513 intelspi_suspend(device_t dev) 514 { 515 struct intelspi_softc *sc; 516 int err, i; 517 518 sc = device_get_softc(dev); 519 520 err = bus_generic_suspend(dev); 521 if (err) 522 return (err); 523 524 for (i = 0; i < 9; i++) { 525 unsigned long offset = i * sizeof(uint32_t); 526 sc->sc_regs[i] = INTELSPI_READ(sc, 527 intelspi_infos[sc->sc_vers].reg_lpss_base + offset); 528 } 529 530 /* Shutdown just in case */ 531 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR0, 0); 532 533 return (0); 534 } 535 536 int 537 intelspi_resume(device_t dev) 538 { 539 struct intelspi_softc *sc; 540 int i; 541 542 sc = device_get_softc(dev); 543 544 for (i = 0; i < 9; i++) { 545 unsigned long offset = i * sizeof(uint32_t); 546 INTELSPI_WRITE(sc, 547 intelspi_infos[sc->sc_vers].reg_lpss_base + offset, 548 sc->sc_regs[i]); 549 } 550 551 intelspi_init(sc); 552 553 /* Ensure the next transfer would reconfigure these */ 554 sc->sc_clock = 0; 555 sc->sc_mode = 0; 556 557 return (bus_generic_resume(dev)); 558 } 559