1 /* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported 6 * to FreeBSD by Michael Gmelin <freebsd@grem.de> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 /* 38 * Intel fourth generation mobile cpus integrated I2C device. 39 * 40 * See ig4_reg.h for datasheet reference and notes. 41 * See ig4_var.h for locking semantics. 42 */ 43 44 #include "opt_acpi.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/module.h> 50 #include <sys/errno.h> 51 #include <sys/kdb.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/proc.h> 55 #include <sys/sx.h> 56 #include <sys/syslog.h> 57 #include <sys/bus.h> 58 #include <sys/sysctl.h> 59 60 #include <machine/bus.h> 61 #include <sys/rman.h> 62 63 #ifdef DEV_ACPI 64 #include <contrib/dev/acpica/include/acpi.h> 65 #include <contrib/dev/acpica/include/accommon.h> 66 #include <dev/acpica/acpivar.h> 67 #endif 68 69 #include <dev/iicbus/iicbus.h> 70 #include <dev/iicbus/iiconf.h> 71 72 #include <dev/ichiic/ig4_reg.h> 73 #include <dev/ichiic/ig4_var.h> 74 75 #define DO_POLL(sc) (cold || kdb_active || SCHEDULER_STOPPED() || sc->poll) 76 77 /* 78 * tLOW, tHIGH periods of the SCL clock and maximal falling time of both 79 * lines are taken from I2C specifications. 80 */ 81 #define IG4_SPEED_STD_THIGH 4000 /* nsec */ 82 #define IG4_SPEED_STD_TLOW 4700 /* nsec */ 83 #define IG4_SPEED_STD_TF_MAX 300 /* nsec */ 84 #define IG4_SPEED_FAST_THIGH 600 /* nsec */ 85 #define IG4_SPEED_FAST_TLOW 1300 /* nsec */ 86 #define IG4_SPEED_FAST_TF_MAX 300 /* nsec */ 87 88 /* 89 * Ig4 hardware parameters except Haswell are taken from intel_lpss driver 90 */ 91 static const struct ig4_hw ig4iic_hw[] = { 92 [IG4_HASWELL] = { 93 .ic_clock_rate = 100, /* MHz */ 94 .sda_hold_time = 90, /* nsec */ 95 .txfifo_depth = 32, 96 .rxfifo_depth = 32, 97 }, 98 [IG4_ATOM] = { 99 .ic_clock_rate = 100, 100 .sda_fall_time = 280, 101 .scl_fall_time = 240, 102 .sda_hold_time = 60, 103 .txfifo_depth = 32, 104 .rxfifo_depth = 32, 105 }, 106 [IG4_SKYLAKE] = { 107 .ic_clock_rate = 120, 108 .sda_hold_time = 230, 109 }, 110 [IG4_APL] = { 111 .ic_clock_rate = 133, 112 .sda_fall_time = 171, 113 .scl_fall_time = 208, 114 .sda_hold_time = 207, 115 }, 116 [IG4_CANNONLAKE] = { 117 .ic_clock_rate = 216, 118 .sda_hold_time = 230, 119 }, 120 [IG4_TIGERLAKE] = { 121 .ic_clock_rate = 133, 122 .sda_fall_time = 171, 123 .scl_fall_time = 208, 124 .sda_hold_time = 42, 125 }, 126 [IG4_GEMINILAKE] = { 127 .ic_clock_rate = 133, 128 .sda_fall_time = 171, 129 .scl_fall_time = 290, 130 .sda_hold_time = 313, 131 }, 132 }; 133 134 static int ig4iic_set_config(ig4iic_softc_t *sc, bool reset); 135 static driver_filter_t ig4iic_intr; 136 static void ig4iic_dump(ig4iic_softc_t *sc); 137 138 static int ig4_dump; 139 SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW, 140 &ig4_dump, 0, "Dump controller registers"); 141 142 /* 143 * Clock registers initialization control 144 * 0 - Try read clock registers from ACPI and fallback to p.1. 145 * 1 - Calculate values based on controller type (IC clock rate). 146 * 2 - Use values inherited from DragonflyBSD driver (old behavior). 147 * 3 - Keep clock registers intact. 148 */ 149 static int ig4_timings; 150 SYSCTL_INT(_debug, OID_AUTO, ig4_timings, CTLFLAG_RDTUN, &ig4_timings, 0, 151 "Controller timings 0=ACPI, 1=predefined, 2=legacy, 3=do not change"); 152 153 /* 154 * Low-level inline support functions 155 */ 156 static __inline void 157 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value) 158 { 159 bus_write_4(sc->regs_res, reg, value); 160 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE); 161 } 162 163 static __inline uint32_t 164 reg_read(ig4iic_softc_t *sc, uint32_t reg) 165 { 166 uint32_t value; 167 168 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ); 169 value = bus_read_4(sc->regs_res, reg); 170 return (value); 171 } 172 173 static void 174 ig4iic_set_intr_mask(ig4iic_softc_t *sc, uint32_t val) 175 { 176 if (sc->intr_mask != val) { 177 reg_write(sc, IG4_REG_INTR_MASK, val); 178 sc->intr_mask = val; 179 } 180 } 181 182 static int 183 intrstat2iic(ig4iic_softc_t *sc, uint32_t val) 184 { 185 uint32_t src; 186 187 if (val & IG4_INTR_RX_UNDER) 188 reg_read(sc, IG4_REG_CLR_RX_UNDER); 189 if (val & IG4_INTR_RX_OVER) 190 reg_read(sc, IG4_REG_CLR_RX_OVER); 191 if (val & IG4_INTR_TX_OVER) 192 reg_read(sc, IG4_REG_CLR_TX_OVER); 193 194 if (val & IG4_INTR_TX_ABRT) { 195 src = reg_read(sc, IG4_REG_TX_ABRT_SOURCE); 196 reg_read(sc, IG4_REG_CLR_TX_ABORT); 197 /* User-requested abort. Not really a error */ 198 if (src & IG4_ABRTSRC_TRANSFER) 199 return (IIC_ESTATUS); 200 /* Master has lost arbitration */ 201 if (src & IG4_ABRTSRC_ARBLOST) 202 return (IIC_EBUSBSY); 203 /* Did not receive an acknowledge from the remote slave */ 204 if (src & (IG4_ABRTSRC_TXNOACK_ADDR7 | 205 IG4_ABRTSRC_TXNOACK_ADDR10_1 | 206 IG4_ABRTSRC_TXNOACK_ADDR10_2 | 207 IG4_ABRTSRC_TXNOACK_DATA | 208 IG4_ABRTSRC_GENCALL_NOACK)) 209 return (IIC_ENOACK); 210 /* Programming errors */ 211 if (src & (IG4_ABRTSRC_GENCALL_READ | 212 IG4_ABRTSRC_NORESTART_START | 213 IG4_ABRTSRC_NORESTART_10)) 214 return (IIC_ENOTSUPP); 215 /* Other errors */ 216 if (src & IG4_ABRTSRC_ACKED_START) 217 return (IIC_EBUSERR); 218 } 219 /* 220 * TX_OVER, RX_OVER and RX_UNDER are caused by wrong RX/TX FIFO depth 221 * detection or driver's read/write pipelining errors. 222 */ 223 if (val & (IG4_INTR_TX_OVER | IG4_INTR_RX_OVER)) 224 return (IIC_EOVERFLOW); 225 if (val & IG4_INTR_RX_UNDER) 226 return (IIC_EUNDERFLOW); 227 228 return (IIC_NOERR); 229 } 230 231 /* 232 * Enable or disable the controller and wait for the controller to acknowledge 233 * the state change. 234 */ 235 static int 236 set_controller(ig4iic_softc_t *sc, uint32_t ctl) 237 { 238 int retry; 239 int error; 240 uint32_t v; 241 242 /* 243 * When the controller is enabled, interrupt on STOP detect 244 * or receive character ready and clear pending interrupts. 245 */ 246 ig4iic_set_intr_mask(sc, 0); 247 if (ctl & IG4_I2C_ENABLE) 248 reg_read(sc, IG4_REG_CLR_INTR); 249 250 reg_write(sc, IG4_REG_I2C_EN, ctl); 251 error = IIC_ETIMEOUT; 252 253 for (retry = 100; retry > 0; --retry) { 254 v = reg_read(sc, IG4_REG_ENABLE_STATUS); 255 if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) { 256 error = 0; 257 break; 258 } 259 pause("i2cslv", 1); 260 } 261 return (error); 262 } 263 264 /* 265 * Wait up to 25ms for the requested interrupt using a 25uS polling loop. 266 */ 267 static int 268 wait_intr(ig4iic_softc_t *sc, uint32_t intr) 269 { 270 uint32_t v; 271 int error; 272 int txlvl = -1; 273 u_int count_us = 0; 274 u_int limit_us = 1000000; /* 1sec */ 275 276 for (;;) { 277 /* 278 * Check requested status 279 */ 280 v = reg_read(sc, IG4_REG_RAW_INTR_STAT); 281 error = intrstat2iic(sc, v & IG4_INTR_ERR_MASK); 282 if (error || (v & intr)) 283 break; 284 285 /* 286 * When waiting for the transmit FIFO to become empty, 287 * reset the timeout if we see a change in the transmit 288 * FIFO level as progress is being made. 289 */ 290 if (intr & (IG4_INTR_TX_EMPTY | IG4_INTR_STOP_DET)) { 291 v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK; 292 if (txlvl != v) { 293 txlvl = v; 294 count_us = 0; 295 } 296 } 297 298 /* 299 * Stop if we've run out of time. 300 */ 301 if (count_us >= limit_us) { 302 error = IIC_ETIMEOUT; 303 break; 304 } 305 306 /* 307 * When polling is not requested let the interrupt do its work. 308 */ 309 if (!DO_POLL(sc)) { 310 mtx_lock_spin(&sc->io_lock); 311 ig4iic_set_intr_mask(sc, intr | IG4_INTR_ERR_MASK); 312 msleep_spin(sc, &sc->io_lock, "i2cwait", 313 (hz + 99) / 100); /* sleep up to 10ms */ 314 ig4iic_set_intr_mask(sc, 0); 315 mtx_unlock_spin(&sc->io_lock); 316 count_us += 10000; 317 } else { 318 DELAY(25); 319 count_us += 25; 320 } 321 } 322 323 return (error); 324 } 325 326 /* 327 * Set the slave address. The controller must be disabled when 328 * changing the address. 329 * 330 * This operation does not issue anything to the I2C bus but sets 331 * the target address for when the controller later issues a START. 332 */ 333 static void 334 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave) 335 { 336 uint32_t tar; 337 uint32_t ctl; 338 bool use_10bit; 339 340 use_10bit = false; 341 if (sc->slave_valid && sc->last_slave == slave && 342 sc->use_10bit == use_10bit) { 343 return; 344 } 345 sc->use_10bit = use_10bit; 346 347 /* 348 * Wait for TXFIFO to drain before disabling the controller. 349 */ 350 wait_intr(sc, IG4_INTR_TX_EMPTY); 351 352 set_controller(sc, 0); 353 ctl = reg_read(sc, IG4_REG_CTL); 354 ctl &= ~IG4_CTL_10BIT; 355 ctl |= IG4_CTL_RESTARTEN; 356 357 tar = slave; 358 if (sc->use_10bit) { 359 tar |= IG4_TAR_10BIT; 360 ctl |= IG4_CTL_10BIT; 361 } 362 reg_write(sc, IG4_REG_CTL, ctl); 363 reg_write(sc, IG4_REG_TAR_ADD, tar); 364 set_controller(sc, IG4_I2C_ENABLE); 365 sc->slave_valid = true; 366 sc->last_slave = slave; 367 } 368 369 /* 370 * IICBUS API FUNCTIONS 371 */ 372 static int 373 ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave, bool repeated_start) 374 { 375 set_slave_addr(sc, slave >> 1); 376 377 if (!repeated_start) { 378 /* 379 * Clear any previous TX/RX FIFOs overflow/underflow bits 380 * and I2C bus STOP condition. 381 */ 382 reg_read(sc, IG4_REG_CLR_INTR); 383 } 384 385 return (0); 386 } 387 388 static bool 389 ig4iic_xfer_is_started(ig4iic_softc_t *sc) 390 { 391 /* 392 * It requires that no IG4_REG_CLR_INTR or IG4_REG_CLR_START/STOP_DET 393 * register reads is issued after START condition. 394 */ 395 return ((reg_read(sc, IG4_REG_RAW_INTR_STAT) & 396 (IG4_INTR_START_DET | IG4_INTR_STOP_DET)) == IG4_INTR_START_DET); 397 } 398 399 static int 400 ig4iic_xfer_abort(ig4iic_softc_t *sc) 401 { 402 int error; 403 404 /* Request send of STOP condition and flush of TX FIFO */ 405 set_controller(sc, IG4_I2C_ABORT | IG4_I2C_ENABLE); 406 /* 407 * Wait for the TX_ABRT interrupt with ABRTSRC_TRANSFER 408 * bit set in TX_ABRT_SOURCE register. 409 */ 410 error = wait_intr(sc, IG4_INTR_STOP_DET); 411 set_controller(sc, IG4_I2C_ENABLE); 412 413 return (error == IIC_ESTATUS ? 0 : error); 414 } 415 416 /* 417 * Amount of unread data before next burst to get better I2C bus utilization. 418 * 2 bytes is enough in FAST mode. 8 bytes is better in FAST+ and HIGH modes. 419 * Intel-recommended value is 16 for DMA transfers with 64-byte depth FIFOs. 420 */ 421 #define IG4_FIFO_LOWAT 2 422 423 static int 424 ig4iic_read(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len, 425 bool repeated_start, bool stop) 426 { 427 uint32_t cmd; 428 int requested = 0; 429 int received = 0; 430 int burst, target, lowat = 0; 431 int error; 432 433 if (len == 0) 434 return (0); 435 436 while (received < len) { 437 burst = sc->cfg.txfifo_depth - 438 (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK); 439 if (burst <= 0) { 440 error = wait_intr(sc, IG4_INTR_TX_EMPTY); 441 if (error) 442 break; 443 burst = sc->cfg.txfifo_depth; 444 } 445 /* Ensure we have enough free space in RXFIFO */ 446 burst = MIN(burst, sc->cfg.rxfifo_depth - lowat); 447 target = MIN(requested + burst, (int)len); 448 while (requested < target) { 449 cmd = IG4_DATA_COMMAND_RD; 450 if (repeated_start && requested == 0) 451 cmd |= IG4_DATA_RESTART; 452 if (stop && requested == len - 1) 453 cmd |= IG4_DATA_STOP; 454 reg_write(sc, IG4_REG_DATA_CMD, cmd); 455 requested++; 456 } 457 /* Leave some data queued to maintain the hardware pipeline */ 458 lowat = 0; 459 if (requested != len && requested - received > IG4_FIFO_LOWAT) 460 lowat = IG4_FIFO_LOWAT; 461 /* After TXFLR fills up, clear it by reading available data */ 462 while (received < requested - lowat) { 463 burst = MIN((int)len - received, 464 reg_read(sc, IG4_REG_RXFLR) & IG4_FIFOLVL_MASK); 465 if (burst > 0) { 466 while (burst--) 467 buf[received++] = 0xFF & 468 reg_read(sc, IG4_REG_DATA_CMD); 469 } else { 470 error = wait_intr(sc, IG4_INTR_RX_FULL); 471 if (error) 472 goto out; 473 } 474 } 475 } 476 out: 477 return (error); 478 } 479 480 static int 481 ig4iic_write(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len, 482 bool repeated_start, bool stop) 483 { 484 uint32_t cmd; 485 int sent = 0; 486 int burst, target; 487 int error; 488 bool lowat_set = false; 489 490 if (len == 0) 491 return (0); 492 493 while (sent < len) { 494 burst = sc->cfg.txfifo_depth - 495 (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK); 496 target = MIN(sent + burst, (int)len); 497 /* Leave some data queued to maintain the hardware pipeline */ 498 if (!lowat_set && target != len) { 499 lowat_set = true; 500 reg_write(sc, IG4_REG_TX_TL, IG4_FIFO_LOWAT); 501 } 502 while(sent < target) { 503 cmd = buf[sent]; 504 if (repeated_start && sent == 0) 505 cmd |= IG4_DATA_RESTART; 506 if (stop && sent == len - 1) 507 cmd |= IG4_DATA_STOP; 508 reg_write(sc, IG4_REG_DATA_CMD, cmd); 509 sent++; 510 } 511 if (sent < len) { 512 error = wait_intr(sc, IG4_INTR_TX_EMPTY); 513 if (error) 514 break; 515 } 516 } 517 if (lowat_set) 518 reg_write(sc, IG4_REG_TX_TL, 0); 519 520 return (error); 521 } 522 523 int 524 ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 525 { 526 ig4iic_softc_t *sc = device_get_softc(dev); 527 const char *reason = NULL; 528 uint32_t i; 529 int error; 530 int unit; 531 bool rpstart; 532 bool stop; 533 bool allocated; 534 535 /* 536 * The hardware interface imposes limits on allowed I2C messages. 537 * It is not possible to explicitly send a start or stop. 538 * They are automatically sent (or not sent, depending on the 539 * configuration) when a data byte is transferred. 540 * For this reason it's impossible to send a message with no data 541 * at all (like an SMBus quick message). 542 * The start condition is automatically generated after the stop 543 * condition, so it's impossible to not have a start after a stop. 544 * The repeated start condition is automatically sent if a change 545 * of the transfer direction happens, so it's impossible to have 546 * a change of direction without a (repeated) start. 547 * The repeated start can be forced even without the change of 548 * direction. 549 * Changing the target slave address requires resetting the hardware 550 * state, so it's impossible to do that without the stop followed 551 * by the start. 552 */ 553 for (i = 0; i < nmsgs; i++) { 554 #if 0 555 if (i == 0 && (msgs[i].flags & IIC_M_NOSTART) != 0) { 556 reason = "first message without start"; 557 break; 558 } 559 if (i == nmsgs - 1 && (msgs[i].flags & IIC_M_NOSTOP) != 0) { 560 reason = "last message without stop"; 561 break; 562 } 563 #endif 564 if (msgs[i].len == 0) { 565 reason = "message with no data"; 566 break; 567 } 568 if (i > 0) { 569 if ((msgs[i].flags & IIC_M_NOSTART) != 0 && 570 (msgs[i - 1].flags & IIC_M_NOSTOP) == 0) { 571 reason = "stop not followed by start"; 572 break; 573 } 574 if ((msgs[i - 1].flags & IIC_M_NOSTOP) != 0 && 575 msgs[i].slave != msgs[i - 1].slave) { 576 reason = "change of slave without stop"; 577 break; 578 } 579 if ((msgs[i].flags & IIC_M_NOSTART) != 0 && 580 (msgs[i].flags & IIC_M_RD) != 581 (msgs[i - 1].flags & IIC_M_RD)) { 582 reason = "change of direction without repeated" 583 " start"; 584 break; 585 } 586 } 587 } 588 if (reason != NULL) { 589 if (bootverbose) 590 device_printf(dev, "%s\n", reason); 591 return (IIC_ENOTSUPP); 592 } 593 594 /* Check if device is already allocated with iicbus_request_bus() */ 595 allocated = sx_xlocked(&sc->call_lock) != 0; 596 if (!allocated) 597 sx_xlock(&sc->call_lock); 598 599 /* Debugging - dump registers. */ 600 if (ig4_dump) { 601 unit = device_get_unit(dev); 602 if (ig4_dump & (1 << unit)) { 603 ig4_dump &= ~(1 << unit); 604 ig4iic_dump(sc); 605 } 606 } 607 608 /* 609 * Clear any previous abort condition that may have been holding 610 * the txfifo in reset. 611 */ 612 reg_read(sc, IG4_REG_CLR_TX_ABORT); 613 614 rpstart = false; 615 error = 0; 616 for (i = 0; i < nmsgs; i++) { 617 if ((msgs[i].flags & IIC_M_NOSTART) == 0) { 618 error = ig4iic_xfer_start(sc, msgs[i].slave, rpstart); 619 } else { 620 if (!sc->slave_valid || 621 (msgs[i].slave >> 1) != sc->last_slave) { 622 device_printf(dev, "start condition suppressed" 623 "but slave address is not set up"); 624 error = EINVAL; 625 break; 626 } 627 rpstart = false; 628 } 629 if (error != 0) 630 break; 631 632 stop = (msgs[i].flags & IIC_M_NOSTOP) == 0; 633 if (msgs[i].flags & IIC_M_RD) 634 error = ig4iic_read(sc, msgs[i].buf, msgs[i].len, 635 rpstart, stop); 636 else 637 error = ig4iic_write(sc, msgs[i].buf, msgs[i].len, 638 rpstart, stop); 639 640 /* Wait for error or stop condition occurred on the I2C bus */ 641 if (stop && error == 0) { 642 error = wait_intr(sc, IG4_INTR_STOP_DET); 643 if (error == 0) 644 reg_read(sc, IG4_REG_CLR_INTR); 645 } 646 647 if (error != 0) { 648 /* 649 * Send STOP condition if it's not done yet and flush 650 * both FIFOs. Do a controller soft reset if transfer 651 * abort is failed. 652 */ 653 if (ig4iic_xfer_is_started(sc) && 654 ig4iic_xfer_abort(sc) != 0) { 655 device_printf(sc->dev, "Failed to abort " 656 "transfer. Do the controller reset.\n"); 657 ig4iic_set_config(sc, true); 658 } else { 659 while (reg_read(sc, IG4_REG_I2C_STA) & 660 IG4_STATUS_RX_NOTEMPTY) 661 reg_read(sc, IG4_REG_DATA_CMD); 662 reg_read(sc, IG4_REG_TX_ABRT_SOURCE); 663 reg_read(sc, IG4_REG_CLR_INTR); 664 } 665 break; 666 } 667 668 rpstart = !stop; 669 } 670 671 if (!allocated) 672 sx_unlock(&sc->call_lock); 673 return (error); 674 } 675 676 int 677 ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 678 { 679 ig4iic_softc_t *sc = device_get_softc(dev); 680 bool allocated; 681 682 allocated = sx_xlocked(&sc->call_lock) != 0; 683 if (!allocated) 684 sx_xlock(&sc->call_lock); 685 686 /* TODO handle speed configuration? */ 687 if (oldaddr != NULL) 688 *oldaddr = sc->last_slave << 1; 689 set_slave_addr(sc, addr >> 1); 690 if (addr == IIC_UNKNOWN) 691 sc->slave_valid = false; 692 693 if (!allocated) 694 sx_unlock(&sc->call_lock); 695 return (0); 696 } 697 698 int 699 ig4iic_callback(device_t dev, int index, caddr_t data) 700 { 701 ig4iic_softc_t *sc = device_get_softc(dev); 702 int error = 0; 703 int how; 704 705 switch (index) { 706 case IIC_REQUEST_BUS: 707 /* force polling if ig4iic is requested with IIC_DONTWAIT */ 708 how = *(int *)data; 709 if ((how & IIC_WAIT) == 0) { 710 if (sx_try_xlock(&sc->call_lock) == 0) 711 error = IIC_EBUSBSY; 712 else 713 sc->poll = true; 714 } else 715 sx_xlock(&sc->call_lock); 716 break; 717 718 case IIC_RELEASE_BUS: 719 sc->poll = false; 720 sx_unlock(&sc->call_lock); 721 break; 722 723 default: 724 error = errno2iic(EINVAL); 725 } 726 727 return (error); 728 } 729 730 /* 731 * Clock register values can be calculated with following rough equations: 732 * SCL_HCNT = ceil(IC clock rate * tHIGH) 733 * SCL_LCNT = ceil(IC clock rate * tLOW) 734 * SDA_HOLD = ceil(IC clock rate * SDA hold time) 735 * Precise equations take signal's falling, rising and spike suppression 736 * times in to account. They can be found in Synopsys or Intel documentation. 737 * 738 * Here we snarf formulas and defaults from Linux driver to be able to use 739 * timing values provided by Intel LPSS driver "as is". 740 */ 741 static int 742 ig4iic_clk_params(const struct ig4_hw *hw, int speed, 743 uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold) 744 { 745 uint32_t thigh, tlow, tf_max; /* nsec */ 746 uint32_t sda_fall_time; /* nsec */ 747 uint32_t scl_fall_time; /* nsec */ 748 749 switch (speed) { 750 case IG4_CTL_SPEED_STD: 751 thigh = IG4_SPEED_STD_THIGH; 752 tlow = IG4_SPEED_STD_TLOW; 753 tf_max = IG4_SPEED_STD_TF_MAX; 754 break; 755 756 case IG4_CTL_SPEED_FAST: 757 thigh = IG4_SPEED_FAST_THIGH; 758 tlow = IG4_SPEED_FAST_TLOW; 759 tf_max = IG4_SPEED_FAST_TF_MAX; 760 break; 761 762 default: 763 return (EINVAL); 764 } 765 766 /* Use slowest falling time defaults to be on the safe side */ 767 sda_fall_time = hw->sda_fall_time == 0 ? tf_max : hw->sda_fall_time; 768 *scl_hcnt = (uint16_t) 769 ((hw->ic_clock_rate * (thigh + sda_fall_time) + 500) / 1000 - 3); 770 771 scl_fall_time = hw->scl_fall_time == 0 ? tf_max : hw->scl_fall_time; 772 *scl_lcnt = (uint16_t) 773 ((hw->ic_clock_rate * (tlow + scl_fall_time) + 500) / 1000 - 1); 774 775 /* 776 * There is no "known good" default value for tHD;DAT so keep SDA_HOLD 777 * intact if sda_hold_time value is not provided. 778 */ 779 if (hw->sda_hold_time != 0) 780 *sda_hold = (uint16_t) 781 ((hw->ic_clock_rate * hw->sda_hold_time + 500) / 1000); 782 783 return (0); 784 } 785 786 #ifdef DEV_ACPI 787 static ACPI_STATUS 788 ig4iic_acpi_params(ACPI_HANDLE handle, char *method, 789 uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold) 790 { 791 ACPI_BUFFER buf; 792 ACPI_OBJECT *obj, *elems; 793 ACPI_STATUS status; 794 795 buf.Pointer = NULL; 796 buf.Length = ACPI_ALLOCATE_BUFFER; 797 798 status = AcpiEvaluateObject(handle, method, NULL, &buf); 799 if (ACPI_FAILURE(status)) 800 return (status); 801 802 status = AE_TYPE; 803 obj = (ACPI_OBJECT *)buf.Pointer; 804 if (obj->Type == ACPI_TYPE_PACKAGE && obj->Package.Count == 3) { 805 elems = obj->Package.Elements; 806 *scl_hcnt = elems[0].Integer.Value & IG4_SCL_CLOCK_MASK; 807 *scl_lcnt = elems[1].Integer.Value & IG4_SCL_CLOCK_MASK; 808 *sda_hold = elems[2].Integer.Value & IG4_SDA_TX_HOLD_MASK; 809 status = AE_OK; 810 } 811 812 AcpiOsFree(obj); 813 814 return (status); 815 } 816 #endif /* DEV_ACPI */ 817 818 static void 819 ig4iic_get_config(ig4iic_softc_t *sc) 820 { 821 const struct ig4_hw *hw; 822 uint32_t v; 823 #ifdef DEV_ACPI 824 ACPI_HANDLE handle; 825 #endif 826 /* Fetch default hardware config from controller */ 827 sc->cfg.version = reg_read(sc, IG4_REG_COMP_VER); 828 sc->cfg.bus_speed = reg_read(sc, IG4_REG_CTL) & IG4_CTL_SPEED_MASK; 829 sc->cfg.ss_scl_hcnt = 830 reg_read(sc, IG4_REG_SS_SCL_HCNT) & IG4_SCL_CLOCK_MASK; 831 sc->cfg.ss_scl_lcnt = 832 reg_read(sc, IG4_REG_SS_SCL_LCNT) & IG4_SCL_CLOCK_MASK; 833 sc->cfg.fs_scl_hcnt = 834 reg_read(sc, IG4_REG_FS_SCL_HCNT) & IG4_SCL_CLOCK_MASK; 835 sc->cfg.fs_scl_lcnt = 836 reg_read(sc, IG4_REG_FS_SCL_LCNT) & IG4_SCL_CLOCK_MASK; 837 sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = 838 reg_read(sc, IG4_REG_SDA_HOLD) & IG4_SDA_TX_HOLD_MASK; 839 840 if (sc->cfg.bus_speed != IG4_CTL_SPEED_STD) 841 sc->cfg.bus_speed = IG4_CTL_SPEED_FAST; 842 843 /* REG_COMP_PARAM1 is not documented in latest Intel specs */ 844 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 845 v = reg_read(sc, IG4_REG_COMP_PARAM1); 846 if (IG4_PARAM1_TXFIFO_DEPTH(v) != 0) 847 sc->cfg.txfifo_depth = IG4_PARAM1_TXFIFO_DEPTH(v); 848 if (IG4_PARAM1_RXFIFO_DEPTH(v) != 0) 849 sc->cfg.rxfifo_depth = IG4_PARAM1_RXFIFO_DEPTH(v); 850 } else { 851 /* 852 * Hardware does not allow FIFO Threshold Levels value to be 853 * set larger than the depth of the buffer. If an attempt is 854 * made to do that, the actual value set will be the maximum 855 * depth of the buffer. 856 */ 857 v = reg_read(sc, IG4_REG_TX_TL); 858 reg_write(sc, IG4_REG_TX_TL, v | IG4_FIFO_MASK); 859 sc->cfg.txfifo_depth = 860 (reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1; 861 reg_write(sc, IG4_REG_TX_TL, v); 862 v = reg_read(sc, IG4_REG_RX_TL); 863 reg_write(sc, IG4_REG_RX_TL, v | IG4_FIFO_MASK); 864 sc->cfg.rxfifo_depth = 865 (reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1; 866 reg_write(sc, IG4_REG_RX_TL, v); 867 } 868 869 /* Override hardware config with IC_clock-based counter values */ 870 if (ig4_timings < 2 && sc->version < nitems(ig4iic_hw)) { 871 hw = &ig4iic_hw[sc->version]; 872 sc->cfg.bus_speed = IG4_CTL_SPEED_FAST; 873 ig4iic_clk_params(hw, IG4_CTL_SPEED_STD, &sc->cfg.ss_scl_hcnt, 874 &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold); 875 ig4iic_clk_params(hw, IG4_CTL_SPEED_FAST, &sc->cfg.fs_scl_hcnt, 876 &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold); 877 if (hw->txfifo_depth != 0) 878 sc->cfg.txfifo_depth = hw->txfifo_depth; 879 if (hw->rxfifo_depth != 0) 880 sc->cfg.rxfifo_depth = hw->rxfifo_depth; 881 } else if (ig4_timings == 2) { 882 /* 883 * Timings of original ig4 driver: 884 * Program based on a 25000 Hz clock. This is a bit of a 885 * hack (obviously). The defaults are 400 and 470 for standard 886 * and 60 and 130 for fast. The defaults for standard fail 887 * utterly (presumably cause an abort) because the clock time 888 * is ~18.8ms by default. This brings it down to ~4ms. 889 */ 890 sc->cfg.bus_speed = IG4_CTL_SPEED_STD; 891 sc->cfg.ss_scl_hcnt = sc->cfg.fs_scl_hcnt = 100; 892 sc->cfg.ss_scl_lcnt = sc->cfg.fs_scl_lcnt = 125; 893 if (sc->version == IG4_SKYLAKE) 894 sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = 28; 895 } 896 897 #ifdef DEV_ACPI 898 /* Evaluate SSCN and FMCN ACPI methods to fetch timings */ 899 if (ig4_timings == 0 && (handle = acpi_get_handle(sc->dev)) != NULL) { 900 ig4iic_acpi_params(handle, "SSCN", &sc->cfg.ss_scl_hcnt, 901 &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold); 902 ig4iic_acpi_params(handle, "FMCN", &sc->cfg.fs_scl_hcnt, 903 &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold); 904 } 905 #endif 906 907 if (bootverbose) { 908 device_printf(sc->dev, "Controller parameters:\n"); 909 printf(" Speed: %s\n", 910 sc->cfg.bus_speed == IG4_CTL_SPEED_STD ? "Std" : "Fast"); 911 printf(" Regs: HCNT :LCNT :SDAHLD\n"); 912 printf(" Std: 0x%04hx:0x%04hx:0x%04hx\n", 913 sc->cfg.ss_scl_hcnt, sc->cfg.ss_scl_lcnt, 914 sc->cfg.ss_sda_hold); 915 printf(" Fast: 0x%04hx:0x%04hx:0x%04hx\n", 916 sc->cfg.fs_scl_hcnt, sc->cfg.fs_scl_lcnt, 917 sc->cfg.fs_sda_hold); 918 printf(" FIFO: RX:0x%04x: TX:0x%04x\n", 919 sc->cfg.rxfifo_depth, sc->cfg.txfifo_depth); 920 } 921 } 922 923 static int 924 ig4iic_set_config(ig4iic_softc_t *sc, bool reset) 925 { 926 uint32_t v; 927 928 v = reg_read(sc, IG4_REG_DEVIDLE_CTRL); 929 if (IG4_HAS_ADDREGS(sc->version) && (v & IG4_RESTORE_REQUIRED)) { 930 reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE | IG4_RESTORE_REQUIRED); 931 reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0); 932 pause("i2crst", 1); 933 reset = true; 934 } 935 936 if ((sc->version == IG4_HASWELL || sc->version == IG4_ATOM) && reset) { 937 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW); 938 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW); 939 } else if (IG4_HAS_ADDREGS(sc->version) && reset) { 940 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); 941 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL); 942 } 943 944 if (sc->version == IG4_ATOM) 945 v = reg_read(sc, IG4_REG_COMP_TYPE); 946 947 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 948 v = reg_read(sc, IG4_REG_COMP_PARAM1); 949 v = reg_read(sc, IG4_REG_GENERAL); 950 /* 951 * The content of IG4_REG_GENERAL is different for each 952 * controller version. 953 */ 954 if (sc->version == IG4_HASWELL && 955 (v & IG4_GENERAL_SWMODE) == 0) { 956 v |= IG4_GENERAL_SWMODE; 957 reg_write(sc, IG4_REG_GENERAL, v); 958 v = reg_read(sc, IG4_REG_GENERAL); 959 } 960 } 961 962 if (sc->version == IG4_HASWELL) { 963 v = reg_read(sc, IG4_REG_SW_LTR_VALUE); 964 v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE); 965 } else if (IG4_HAS_ADDREGS(sc->version)) { 966 v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE); 967 v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE); 968 } 969 970 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 971 v = reg_read(sc, IG4_REG_COMP_VER); 972 if (v < IG4_COMP_MIN_VER) 973 return(ENXIO); 974 } 975 976 if (set_controller(sc, 0)) { 977 device_printf(sc->dev, "controller error during attach-1\n"); 978 return (ENXIO); 979 } 980 981 reg_read(sc, IG4_REG_CLR_INTR); 982 reg_write(sc, IG4_REG_INTR_MASK, 0); 983 sc->intr_mask = 0; 984 985 reg_write(sc, IG4_REG_SS_SCL_HCNT, sc->cfg.ss_scl_hcnt); 986 reg_write(sc, IG4_REG_SS_SCL_LCNT, sc->cfg.ss_scl_lcnt); 987 reg_write(sc, IG4_REG_FS_SCL_HCNT, sc->cfg.fs_scl_hcnt); 988 reg_write(sc, IG4_REG_FS_SCL_LCNT, sc->cfg.fs_scl_lcnt); 989 reg_write(sc, IG4_REG_SDA_HOLD, 990 (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK) == IG4_CTL_SPEED_STD ? 991 sc->cfg.ss_sda_hold : sc->cfg.fs_sda_hold); 992 993 /* 994 * Use a threshold of 1 so we get interrupted on each character, 995 * allowing us to use mtx_sleep() in our poll code. Not perfect 996 * but this is better than using DELAY() for receiving data. 997 * 998 * See ig4_var.h for details on interrupt handler synchronization. 999 */ 1000 reg_write(sc, IG4_REG_RX_TL, 0); 1001 reg_write(sc, IG4_REG_TX_TL, 0); 1002 1003 reg_write(sc, IG4_REG_CTL, 1004 IG4_CTL_MASTER | 1005 IG4_CTL_SLAVE_DISABLE | 1006 IG4_CTL_RESTARTEN | 1007 (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK)); 1008 1009 /* Force setting of the target address on the next transfer */ 1010 sc->slave_valid = false; 1011 1012 return (0); 1013 } 1014 1015 /* 1016 * Called from ig4iic_pci_attach/detach() 1017 */ 1018 int 1019 ig4iic_attach(ig4iic_softc_t *sc) 1020 { 1021 int error; 1022 1023 mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_SPIN); 1024 sx_init(&sc->call_lock, "IG4 call lock"); 1025 1026 ig4iic_get_config(sc); 1027 1028 error = ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version)); 1029 if (error) 1030 goto done; 1031 1032 sc->iicbus = device_add_child(sc->dev, "iicbus", -1); 1033 if (sc->iicbus == NULL) { 1034 device_printf(sc->dev, "iicbus driver not found\n"); 1035 error = ENXIO; 1036 goto done; 1037 } 1038 1039 if (set_controller(sc, IG4_I2C_ENABLE)) { 1040 device_printf(sc->dev, "controller error during attach-2\n"); 1041 error = ENXIO; 1042 goto done; 1043 } 1044 if (set_controller(sc, 0)) { 1045 device_printf(sc->dev, "controller error during attach-3\n"); 1046 error = ENXIO; 1047 goto done; 1048 } 1049 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC | INTR_MPSAFE, 1050 ig4iic_intr, NULL, sc, &sc->intr_handle); 1051 if (error) { 1052 device_printf(sc->dev, 1053 "Unable to setup irq: error %d\n", error); 1054 } 1055 1056 error = bus_generic_attach(sc->dev); 1057 if (error) { 1058 device_printf(sc->dev, 1059 "failed to attach child: error %d\n", error); 1060 } 1061 1062 done: 1063 return (error); 1064 } 1065 1066 int 1067 ig4iic_detach(ig4iic_softc_t *sc) 1068 { 1069 int error; 1070 1071 if (device_is_attached(sc->dev)) { 1072 error = bus_generic_detach(sc->dev); 1073 if (error) 1074 return (error); 1075 } 1076 if (sc->iicbus) 1077 device_delete_child(sc->dev, sc->iicbus); 1078 if (sc->intr_handle) 1079 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle); 1080 1081 sx_xlock(&sc->call_lock); 1082 1083 sc->iicbus = NULL; 1084 sc->intr_handle = NULL; 1085 reg_write(sc, IG4_REG_INTR_MASK, 0); 1086 set_controller(sc, 0); 1087 1088 sx_xunlock(&sc->call_lock); 1089 1090 mtx_destroy(&sc->io_lock); 1091 sx_destroy(&sc->call_lock); 1092 1093 return (0); 1094 } 1095 1096 int 1097 ig4iic_suspend(ig4iic_softc_t *sc) 1098 { 1099 int error; 1100 1101 /* suspend all children */ 1102 error = bus_generic_suspend(sc->dev); 1103 1104 sx_xlock(&sc->call_lock); 1105 set_controller(sc, 0); 1106 if (IG4_HAS_ADDREGS(sc->version)) { 1107 /* 1108 * Place the device in the idle state, just to be safe 1109 */ 1110 reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE); 1111 /* 1112 * Controller can become dysfunctional if I2C lines are pulled 1113 * down when suspend procedure turns off power to I2C device. 1114 * Place device in the reset state to avoid this. 1115 */ 1116 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); 1117 } 1118 sx_xunlock(&sc->call_lock); 1119 1120 return (error); 1121 } 1122 1123 int ig4iic_resume(ig4iic_softc_t *sc) 1124 { 1125 int error; 1126 1127 sx_xlock(&sc->call_lock); 1128 if (ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version))) 1129 device_printf(sc->dev, "controller error during resume\n"); 1130 sx_xunlock(&sc->call_lock); 1131 1132 error = bus_generic_resume(sc->dev); 1133 1134 return (error); 1135 } 1136 1137 /* 1138 * Interrupt Operation, see ig4_var.h for locking semantics. 1139 */ 1140 static int 1141 ig4iic_intr(void *cookie) 1142 { 1143 ig4iic_softc_t *sc = cookie; 1144 int retval = FILTER_STRAY; 1145 1146 mtx_lock_spin(&sc->io_lock); 1147 /* Ignore stray interrupts */ 1148 if (sc->intr_mask != 0 && reg_read(sc, IG4_REG_INTR_STAT) != 0) { 1149 /* Interrupt bits are cleared in wait_intr() loop */ 1150 ig4iic_set_intr_mask(sc, 0); 1151 wakeup(sc); 1152 retval = FILTER_HANDLED; 1153 } 1154 mtx_unlock_spin(&sc->io_lock); 1155 1156 return (retval); 1157 } 1158 1159 #define REGDUMP(sc, reg) \ 1160 device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg)) 1161 1162 static void 1163 ig4iic_dump(ig4iic_softc_t *sc) 1164 { 1165 device_printf(sc->dev, "ig4iic register dump:\n"); 1166 REGDUMP(sc, IG4_REG_CTL); 1167 REGDUMP(sc, IG4_REG_TAR_ADD); 1168 REGDUMP(sc, IG4_REG_SS_SCL_HCNT); 1169 REGDUMP(sc, IG4_REG_SS_SCL_LCNT); 1170 REGDUMP(sc, IG4_REG_FS_SCL_HCNT); 1171 REGDUMP(sc, IG4_REG_FS_SCL_LCNT); 1172 REGDUMP(sc, IG4_REG_INTR_STAT); 1173 REGDUMP(sc, IG4_REG_INTR_MASK); 1174 REGDUMP(sc, IG4_REG_RAW_INTR_STAT); 1175 REGDUMP(sc, IG4_REG_RX_TL); 1176 REGDUMP(sc, IG4_REG_TX_TL); 1177 REGDUMP(sc, IG4_REG_I2C_EN); 1178 REGDUMP(sc, IG4_REG_I2C_STA); 1179 REGDUMP(sc, IG4_REG_TXFLR); 1180 REGDUMP(sc, IG4_REG_RXFLR); 1181 REGDUMP(sc, IG4_REG_SDA_HOLD); 1182 REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE); 1183 REGDUMP(sc, IG4_REG_SLV_DATA_NACK); 1184 REGDUMP(sc, IG4_REG_DMA_CTRL); 1185 REGDUMP(sc, IG4_REG_DMA_TDLR); 1186 REGDUMP(sc, IG4_REG_DMA_RDLR); 1187 REGDUMP(sc, IG4_REG_SDA_SETUP); 1188 REGDUMP(sc, IG4_REG_ENABLE_STATUS); 1189 REGDUMP(sc, IG4_REG_COMP_PARAM1); 1190 REGDUMP(sc, IG4_REG_COMP_VER); 1191 if (sc->version == IG4_ATOM) { 1192 REGDUMP(sc, IG4_REG_COMP_TYPE); 1193 REGDUMP(sc, IG4_REG_CLK_PARMS); 1194 } 1195 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 1196 REGDUMP(sc, IG4_REG_RESETS_HSW); 1197 REGDUMP(sc, IG4_REG_GENERAL); 1198 } else if (sc->version == IG4_SKYLAKE) { 1199 REGDUMP(sc, IG4_REG_RESETS_SKL); 1200 } 1201 if (sc->version == IG4_HASWELL) { 1202 REGDUMP(sc, IG4_REG_SW_LTR_VALUE); 1203 REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE); 1204 } else if (IG4_HAS_ADDREGS(sc->version)) { 1205 REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE); 1206 REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE); 1207 } 1208 } 1209 #undef REGDUMP 1210 1211 DRIVER_MODULE(iicbus, ig4iic, iicbus_driver, NULL, NULL); 1212 #ifdef DEV_ACPI 1213 DRIVER_MODULE(acpi_iicbus, ig4iic, acpi_iicbus_driver, NULL, NULL); 1214 #endif 1215 MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); 1216 MODULE_VERSION(ig4iic, 1); 1217