xref: /freebsd/sys/dev/ichiic/ig4_iic.c (revision d9f0ce31900a48d1a2bfc1c8c86f79d1e831451a)
1 /*
2  * Copyright (c) 2014 The DragonFly Project.  All rights reserved.
3  *
4  * This code is derived from software contributed to The DragonFly Project
5  * by Matthew Dillon <dillon@backplane.com> and was subsequently ported
6  * to FreeBSD by Michael Gmelin <freebsd@grem.de>
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  *
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in
16  *    the documentation and/or other materials provided with the
17  *    distribution.
18  * 3. Neither the name of The DragonFly Project nor the names of its
19  *    contributors may be used to endorse or promote products derived
20  *    from this software without specific, prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
26  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
28  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33  * SUCH DAMAGE.
34  */
35 
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
38 
39 /*
40  * Intel fourth generation mobile cpus integrated I2C device, smbus driver.
41  *
42  * See ig4_reg.h for datasheet reference and notes.
43  * See ig4_var.h for locking semantics.
44  */
45 
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50 #include <sys/errno.h>
51 #include <sys/lock.h>
52 #include <sys/mutex.h>
53 #include <sys/sx.h>
54 #include <sys/syslog.h>
55 #include <sys/bus.h>
56 #include <sys/sysctl.h>
57 
58 #include <machine/bus.h>
59 #include <sys/rman.h>
60 
61 #include <dev/pci/pcivar.h>
62 #include <dev/pci/pcireg.h>
63 #include <dev/smbus/smbconf.h>
64 
65 #include <dev/ichiic/ig4_reg.h>
66 #include <dev/ichiic/ig4_var.h>
67 
68 #define TRANS_NORMAL	1
69 #define TRANS_PCALL	2
70 #define TRANS_BLOCK	3
71 
72 static void ig4iic_start(void *xdev);
73 static void ig4iic_intr(void *cookie);
74 static void ig4iic_dump(ig4iic_softc_t *sc);
75 
76 static int ig4_dump;
77 SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW,
78 	   &ig4_dump, 0, "Dump controller registers");
79 
80 /*
81  * Low-level inline support functions
82  */
83 static __inline void
84 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value)
85 {
86 	bus_write_4(sc->regs_res, reg, value);
87 	bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE);
88 }
89 
90 static __inline uint32_t
91 reg_read(ig4iic_softc_t *sc, uint32_t reg)
92 {
93 	uint32_t value;
94 
95 	bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ);
96 	value = bus_read_4(sc->regs_res, reg);
97 	return (value);
98 }
99 
100 /*
101  * Enable or disable the controller and wait for the controller to acknowledge
102  * the state change.
103  */
104 static int
105 set_controller(ig4iic_softc_t *sc, uint32_t ctl)
106 {
107 	int retry;
108 	int error;
109 	uint32_t v;
110 
111 	reg_write(sc, IG4_REG_I2C_EN, ctl);
112 	error = SMB_ETIMEOUT;
113 
114 	for (retry = 100; retry > 0; --retry) {
115 		v = reg_read(sc, IG4_REG_ENABLE_STATUS);
116 		if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) {
117 			error = 0;
118 			break;
119 		}
120 		if (cold)
121 			DELAY(1000);
122 		else
123 			mtx_sleep(sc, &sc->io_lock, 0, "i2cslv", 1);
124 	}
125 	return (error);
126 }
127 
128 /*
129  * Wait up to 25ms for the requested status using a 25uS polling loop.
130  */
131 static int
132 wait_status(ig4iic_softc_t *sc, uint32_t status)
133 {
134 	uint32_t v;
135 	int error;
136 	int txlvl = -1;
137 	u_int count_us = 0;
138 	u_int limit_us = 25000; /* 25ms */
139 
140 	error = SMB_ETIMEOUT;
141 
142 	for (;;) {
143 		/*
144 		 * Check requested status
145 		 */
146 		v = reg_read(sc, IG4_REG_I2C_STA);
147 		if (v & status) {
148 			error = 0;
149 			break;
150 		}
151 
152 		/*
153 		 * When waiting for receive data break-out if the interrupt
154 		 * loaded data into the FIFO.
155 		 */
156 		if (status & IG4_STATUS_RX_NOTEMPTY) {
157 			if (sc->rpos != sc->rnext) {
158 				error = 0;
159 				break;
160 			}
161 		}
162 
163 		/*
164 		 * When waiting for the transmit FIFO to become empty,
165 		 * reset the timeout if we see a change in the transmit
166 		 * FIFO level as progress is being made.
167 		 */
168 		if (status & IG4_STATUS_TX_EMPTY) {
169 			v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;
170 			if (txlvl != v) {
171 				txlvl = v;
172 				count_us = 0;
173 			}
174 		}
175 
176 		/*
177 		 * Stop if we've run out of time.
178 		 */
179 		if (count_us >= limit_us)
180 			break;
181 
182 		/*
183 		 * When waiting for receive data let the interrupt do its
184 		 * work, otherwise poll with the lock held.
185 		 */
186 		if (status & IG4_STATUS_RX_NOTEMPTY) {
187 			mtx_sleep(sc, &sc->io_lock, 0, "i2cwait",
188 				  (hz + 99) / 100); /* sleep up to 10ms */
189 			count_us += 10000;
190 		} else {
191 			DELAY(25);
192 			count_us += 25;
193 		}
194 	}
195 
196 	return (error);
197 }
198 
199 /*
200  * Read I2C data.  The data might have already been read by
201  * the interrupt code, otherwise it is sitting in the data
202  * register.
203  */
204 static uint8_t
205 data_read(ig4iic_softc_t *sc)
206 {
207 	uint8_t c;
208 
209 	if (sc->rpos == sc->rnext) {
210 		c = (uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
211 	} else {
212 		c = sc->rbuf[sc->rpos & IG4_RBUFMASK];
213 		++sc->rpos;
214 	}
215 	return (c);
216 }
217 
218 /*
219  * Set the slave address.  The controller must be disabled when
220  * changing the address.
221  *
222  * This operation does not issue anything to the I2C bus but sets
223  * the target address for when the controller later issues a START.
224  */
225 static void
226 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave, int trans_op)
227 {
228 	uint32_t tar;
229 	uint32_t ctl;
230 	int use_10bit;
231 
232 	use_10bit = sc->use_10bit;
233 	if (trans_op & SMB_TRANS_7BIT)
234 		use_10bit = 0;
235 	if (trans_op & SMB_TRANS_10BIT)
236 		use_10bit = 1;
237 
238 	if (sc->slave_valid && sc->last_slave == slave &&
239 	    sc->use_10bit == use_10bit) {
240 		return;
241 	}
242 	sc->use_10bit = use_10bit;
243 
244 	/*
245 	 * Wait for TXFIFO to drain before disabling the controller.
246 	 *
247 	 * If a write message has not been completed it's really a
248 	 * programming error, but for now in that case issue an extra
249 	 * byte + STOP.
250 	 *
251 	 * If a read message has not been completed it's also a programming
252 	 * error, for now just ignore it.
253 	 */
254 	wait_status(sc, IG4_STATUS_TX_NOTFULL);
255 	if (sc->write_started) {
256 		reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_STOP);
257 		sc->write_started = 0;
258 	}
259 	if (sc->read_started)
260 		sc->read_started = 0;
261 	wait_status(sc, IG4_STATUS_TX_EMPTY);
262 
263 	set_controller(sc, 0);
264 	ctl = reg_read(sc, IG4_REG_CTL);
265 	ctl &= ~IG4_CTL_10BIT;
266 	ctl |= IG4_CTL_RESTARTEN;
267 
268 	tar = slave;
269 	if (sc->use_10bit) {
270 		tar |= IG4_TAR_10BIT;
271 		ctl |= IG4_CTL_10BIT;
272 	}
273 	reg_write(sc, IG4_REG_CTL, ctl);
274 	reg_write(sc, IG4_REG_TAR_ADD, tar);
275 	set_controller(sc, IG4_I2C_ENABLE);
276 	sc->slave_valid = 1;
277 	sc->last_slave = slave;
278 }
279 
280 /*
281  * Issue START with byte command, possible count, and a variable length
282  * read or write buffer, then possible turn-around read.  The read also
283  * has a possible count received.
284  *
285  * For SMBUS -
286  *
287  * Quick:		START+ADDR+RD/WR STOP
288  *
289  * Normal:		START+ADDR+WR CMD DATA..DATA STOP
290  *
291  *			START+ADDR+RD CMD
292  *			RESTART+ADDR RDATA..RDATA STOP
293  *			(can also be used for I2C transactions)
294  *
295  * Process Call:	START+ADDR+WR CMD DATAL DATAH
296  *			RESTART+ADDR+RD RDATAL RDATAH STOP
297  *
298  * Block:		START+ADDR+RD CMD
299  *			RESTART+ADDR+RD RCOUNT DATA... STOP
300  *
301  * 			START+ADDR+WR CMD
302  *			RESTART+ADDR+WR WCOUNT DATA... STOP
303  *
304  * For I2C - basically, no *COUNT fields, possibly no *CMD field.  If the
305  *	     sender needs to issue a 2-byte command it will incorporate it
306  *	     into the write buffer and also set NOCMD.
307  *
308  * Generally speaking, the START+ADDR / RESTART+ADDR is handled automatically
309  * by the controller at the beginning of a command sequence or on a data
310  * direction turn-around, and we only need to tell it when to issue the STOP.
311  */
312 static int
313 smb_transaction(ig4iic_softc_t *sc, char cmd, int op,
314 		char *wbuf, int wcount, char *rbuf, int rcount, int *actualp)
315 {
316 	int error;
317 	int unit;
318 	uint32_t last;
319 
320 	/*
321 	 * Debugging - dump registers
322 	 */
323 	if (ig4_dump) {
324 		unit = device_get_unit(sc->dev);
325 		if (ig4_dump & (1 << unit)) {
326 			ig4_dump &= ~(1 << unit);
327 			ig4iic_dump(sc);
328 		}
329 	}
330 
331 	/*
332 	 * Issue START or RESTART with next data byte, clear any previous
333 	 * abort condition that may have been holding the txfifo in reset.
334 	 */
335 	last = IG4_DATA_RESTART;
336 	reg_read(sc, IG4_REG_CLR_TX_ABORT);
337 	if (actualp)
338 		*actualp = 0;
339 
340 	/*
341 	 * Issue command if not told otherwise (smbus).
342 	 */
343 	if ((op & SMB_TRANS_NOCMD) == 0) {
344 		error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
345 		if (error)
346 			goto done;
347 		last |= (u_char)cmd;
348 		if (wcount == 0 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0)
349 			last |= IG4_DATA_STOP;
350 		reg_write(sc, IG4_REG_DATA_CMD, last);
351 		last = 0;
352 	}
353 
354 	/*
355 	 * Clean out any previously received data.
356 	 */
357 	if (sc->rpos != sc->rnext &&
358 	    (op & SMB_TRANS_NOREPORT) == 0) {
359 		device_printf(sc->dev,
360 			      "discarding %d bytes of spurious data\n",
361 			      sc->rnext - sc->rpos);
362 	}
363 	sc->rpos = 0;
364 	sc->rnext = 0;
365 
366 	/*
367 	 * If writing and not told otherwise, issue the write count (smbus).
368 	 */
369 	if (wcount && (op & SMB_TRANS_NOCNT) == 0) {
370 		error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
371 		if (error)
372 			goto done;
373 		last |= (u_char)cmd;
374 		reg_write(sc, IG4_REG_DATA_CMD, last);
375 		last = 0;
376 	}
377 
378 	/*
379 	 * Bulk write (i2c)
380 	 */
381 	while (wcount) {
382 		error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
383 		if (error)
384 			goto done;
385 		last |= (u_char)*wbuf;
386 		if (wcount == 1 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0)
387 			last |= IG4_DATA_STOP;
388 		reg_write(sc, IG4_REG_DATA_CMD, last);
389 		--wcount;
390 		++wbuf;
391 		last = 0;
392 	}
393 
394 	/*
395 	 * Issue reads to xmit FIFO (strange, I know) to tell the controller
396 	 * to clock in data.  At the moment just issue one read ahead to
397 	 * pipeline the incoming data.
398 	 *
399 	 * NOTE: In the case of NOCMD and wcount == 0 we still issue a
400 	 *	 RESTART here, even if the data direction has not changed
401 	 *	 from the previous CHAINing call.  This we force the RESTART.
402 	 *	 (A new START is issued automatically by the controller in
403 	 *	 the other nominal cases such as a data direction change or
404 	 *	 a previous STOP was issued).
405 	 *
406 	 * If this will be the last byte read we must also issue the STOP
407 	 * at the end of the read.
408 	 */
409 	if (rcount) {
410 		last = IG4_DATA_RESTART | IG4_DATA_COMMAND_RD;
411 		if (rcount == 1 &&
412 		    (op & (SMB_TRANS_NOSTOP | SMB_TRANS_NOCNT)) ==
413 		    SMB_TRANS_NOCNT) {
414 			last |= IG4_DATA_STOP;
415 		}
416 		reg_write(sc, IG4_REG_DATA_CMD, last);
417 		last = IG4_DATA_COMMAND_RD;
418 	}
419 
420 	/*
421 	 * Bulk read (i2c) and count field handling (smbus)
422 	 */
423 	while (rcount) {
424 		/*
425 		 * Maintain a pipeline by queueing the allowance for the next
426 		 * read before waiting for the current read.
427 		 */
428 		if (rcount > 1) {
429 			if (op & SMB_TRANS_NOCNT)
430 				last = (rcount == 2) ? IG4_DATA_STOP : 0;
431 			else
432 				last = 0;
433 			reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD |
434 							last);
435 		}
436 		error = wait_status(sc, IG4_STATUS_RX_NOTEMPTY);
437 		if (error) {
438 			if ((op & SMB_TRANS_NOREPORT) == 0) {
439 				device_printf(sc->dev,
440 					      "rx timeout addr 0x%02x\n",
441 					      sc->last_slave);
442 			}
443 			goto done;
444 		}
445 		last = data_read(sc);
446 
447 		if (op & SMB_TRANS_NOCNT) {
448 			*rbuf = (u_char)last;
449 			++rbuf;
450 			--rcount;
451 			if (actualp)
452 				++*actualp;
453 		} else {
454 			/*
455 			 * Handle count field (smbus), which is not part of
456 			 * the rcount'ed buffer.  The first read data in a
457 			 * bulk transfer is the count.
458 			 *
459 			 * XXX if rcount is loaded as 0 how do I generate a
460 			 *     STOP now without issuing another RD or WR?
461 			 */
462 			if (rcount > (u_char)last)
463 				rcount = (u_char)last;
464 			op |= SMB_TRANS_NOCNT;
465 		}
466 	}
467 	error = 0;
468 done:
469 	/* XXX wait for xmit buffer to become empty */
470 	last = reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
471 
472 	return (error);
473 }
474 
475 /*
476  *				SMBUS API FUNCTIONS
477  *
478  * Called from ig4iic_pci_attach/detach()
479  */
480 int
481 ig4iic_attach(ig4iic_softc_t *sc)
482 {
483 	int error;
484 	uint32_t v;
485 
486 	v = reg_read(sc, IG4_REG_COMP_TYPE);
487 	v = reg_read(sc, IG4_REG_COMP_PARAM1);
488 	v = reg_read(sc, IG4_REG_GENERAL);
489 	if ((v & IG4_GENERAL_SWMODE) == 0) {
490 		v |= IG4_GENERAL_SWMODE;
491 		reg_write(sc, IG4_REG_GENERAL, v);
492 		v = reg_read(sc, IG4_REG_GENERAL);
493 	}
494 
495 	v = reg_read(sc, IG4_REG_SW_LTR_VALUE);
496 	v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);
497 
498 	v = reg_read(sc, IG4_REG_COMP_VER);
499 	if (v != IG4_COMP_VER) {
500 		error = ENXIO;
501 		goto done;
502 	}
503 	v = reg_read(sc, IG4_REG_SS_SCL_HCNT);
504 	v = reg_read(sc, IG4_REG_SS_SCL_LCNT);
505 	v = reg_read(sc, IG4_REG_FS_SCL_HCNT);
506 	v = reg_read(sc, IG4_REG_FS_SCL_LCNT);
507 	v = reg_read(sc, IG4_REG_SDA_HOLD);
508 
509 	v = reg_read(sc, IG4_REG_SS_SCL_HCNT);
510 	reg_write(sc, IG4_REG_FS_SCL_HCNT, v);
511 	v = reg_read(sc, IG4_REG_SS_SCL_LCNT);
512 	reg_write(sc, IG4_REG_FS_SCL_LCNT, v);
513 
514 	/*
515 	 * Program based on a 25000 Hz clock.  This is a bit of a
516 	 * hack (obviously).  The defaults are 400 and 470 for standard
517 	 * and 60 and 130 for fast.  The defaults for standard fail
518 	 * utterly (presumably cause an abort) because the clock time
519 	 * is ~18.8ms by default.  This brings it down to ~4ms (for now).
520 	 */
521 	reg_write(sc, IG4_REG_SS_SCL_HCNT, 100);
522 	reg_write(sc, IG4_REG_SS_SCL_LCNT, 125);
523 	reg_write(sc, IG4_REG_FS_SCL_HCNT, 100);
524 	reg_write(sc, IG4_REG_FS_SCL_LCNT, 125);
525 
526 	/*
527 	 * Use a threshold of 1 so we get interrupted on each character,
528 	 * allowing us to use mtx_sleep() in our poll code.  Not perfect
529 	 * but this is better than using DELAY() for receiving data.
530 	 *
531 	 * See ig4_var.h for details on interrupt handler synchronization.
532 	 */
533 	reg_write(sc, IG4_REG_RX_TL, 1);
534 
535 	reg_write(sc, IG4_REG_CTL,
536 		  IG4_CTL_MASTER |
537 		  IG4_CTL_SLAVE_DISABLE |
538 		  IG4_CTL_RESTARTEN |
539 		  IG4_CTL_SPEED_STD);
540 
541 	sc->smb = device_add_child(sc->dev, "smbus", -1);
542 	if (sc->smb == NULL) {
543 		device_printf(sc->dev, "smbus driver not found\n");
544 		error = ENXIO;
545 		goto done;
546 	}
547 
548 #if 0
549 	/*
550 	 * Don't do this, it blows up the PCI config
551 	 */
552 	reg_write(sc, IG4_REG_RESETS, IG4_RESETS_ASSERT);
553 	reg_write(sc, IG4_REG_RESETS, IG4_RESETS_DEASSERT);
554 #endif
555 
556 	/*
557 	 * Interrupt on STOP detect or receive character ready
558 	 */
559 	reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET |
560 					 IG4_INTR_RX_FULL);
561 	mtx_lock(&sc->io_lock);
562 	if (set_controller(sc, 0))
563 		device_printf(sc->dev, "controller error during attach-1\n");
564 	if (set_controller(sc, IG4_I2C_ENABLE))
565 		device_printf(sc->dev, "controller error during attach-2\n");
566 	mtx_unlock(&sc->io_lock);
567 	error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC | INTR_MPSAFE,
568 			       NULL, ig4iic_intr, sc, &sc->intr_handle);
569 	if (error) {
570 		device_printf(sc->dev,
571 			      "Unable to setup irq: error %d\n", error);
572 	}
573 
574 	sc->enum_hook.ich_func = ig4iic_start;
575 	sc->enum_hook.ich_arg = sc->dev;
576 
577 	/* We have to wait until interrupts are enabled. I2C read and write
578 	 * only works if the interrupts are available.
579 	 */
580 	if (config_intrhook_establish(&sc->enum_hook) != 0)
581 		error = ENOMEM;
582 	else
583 		error = 0;
584 
585 done:
586 	return (error);
587 }
588 
589 void
590 ig4iic_start(void *xdev)
591 {
592 	int error;
593 	ig4iic_softc_t *sc;
594 	device_t dev = (device_t)xdev;
595 
596 	sc = device_get_softc(dev);
597 
598 	config_intrhook_disestablish(&sc->enum_hook);
599 
600 	/* Attach us to the smbus */
601 	error = bus_generic_attach(sc->dev);
602 	if (error) {
603 		device_printf(sc->dev,
604 			      "failed to attach child: error %d\n", error);
605 	}
606 }
607 
608 
609 
610 int
611 ig4iic_detach(ig4iic_softc_t *sc)
612 {
613 	int error;
614 
615 	if (device_is_attached(sc->dev)) {
616 		error = bus_generic_detach(sc->dev);
617 		if (error)
618 			return (error);
619 	}
620 	if (sc->smb)
621 		device_delete_child(sc->dev, sc->smb);
622 	if (sc->intr_handle)
623 		bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle);
624 
625 	sx_xlock(&sc->call_lock);
626 	mtx_lock(&sc->io_lock);
627 
628 	sc->smb = NULL;
629 	sc->intr_handle = NULL;
630 	reg_write(sc, IG4_REG_INTR_MASK, 0);
631 	reg_read(sc, IG4_REG_CLR_INTR);
632 	set_controller(sc, 0);
633 
634 	mtx_unlock(&sc->io_lock);
635 	sx_xunlock(&sc->call_lock);
636 	return (0);
637 }
638 
639 int
640 ig4iic_smb_callback(device_t dev, int index, void *data)
641 {
642 	int error;
643 
644 	switch (index) {
645 	case SMB_REQUEST_BUS:
646 		error = 0;
647 		break;
648 	case SMB_RELEASE_BUS:
649 		error = 0;
650 		break;
651 	default:
652 		error = SMB_EABORT;
653 		break;
654 	}
655 
656 	return (error);
657 }
658 
659 /*
660  * Quick command.  i.e. START + cmd + R/W + STOP and no data.  It is
661  * unclear to me how I could implement this with the intel i2c controller
662  * because the controler sends STARTs and STOPs automatically with data.
663  */
664 int
665 ig4iic_smb_quick(device_t dev, u_char slave, int how)
666 {
667 
668 	return (SMB_ENOTSUPP);
669 }
670 
671 /*
672  * Incremental send byte without stop (?).  It is unclear why the slave
673  * address is specified if this presumably is used in combination with
674  * ig4iic_smb_quick().
675  *
676  * (Also, how would this work anyway?  Issue the last byte with writeb()?)
677  */
678 int
679 ig4iic_smb_sendb(device_t dev, u_char slave, char byte)
680 {
681 	ig4iic_softc_t *sc = device_get_softc(dev);
682 	uint32_t cmd;
683 	int error;
684 
685 	sx_xlock(&sc->call_lock);
686 	mtx_lock(&sc->io_lock);
687 
688 	set_slave_addr(sc, slave, 0);
689 	cmd = byte;
690 	if (wait_status(sc, IG4_STATUS_TX_NOTFULL) == 0) {
691 		reg_write(sc, IG4_REG_DATA_CMD, cmd);
692 		error = 0;
693 	} else {
694 		error = SMB_ETIMEOUT;
695 	}
696 
697 	mtx_unlock(&sc->io_lock);
698 	sx_xunlock(&sc->call_lock);
699 	return (error);
700 }
701 
702 /*
703  * Incremental receive byte without stop (?).  It is unclear why the slave
704  * address is specified if this presumably is used in combination with
705  * ig4iic_smb_quick().
706  */
707 int
708 ig4iic_smb_recvb(device_t dev, u_char slave, char *byte)
709 {
710 	ig4iic_softc_t *sc = device_get_softc(dev);
711 	int error;
712 
713 	sx_xlock(&sc->call_lock);
714 	mtx_lock(&sc->io_lock);
715 
716 	set_slave_addr(sc, slave, 0);
717 	reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD);
718 	if (wait_status(sc, IG4_STATUS_RX_NOTEMPTY) == 0) {
719 		*byte = data_read(sc);
720 		error = 0;
721 	} else {
722 		*byte = 0;
723 		error = SMB_ETIMEOUT;
724 	}
725 
726 	mtx_unlock(&sc->io_lock);
727 	sx_xunlock(&sc->call_lock);
728 	return (error);
729 }
730 
731 /*
732  * Write command and single byte in transaction.
733  */
734 int
735 ig4iic_smb_writeb(device_t dev, u_char slave, char cmd, char byte)
736 {
737 	ig4iic_softc_t *sc = device_get_softc(dev);
738 	int error;
739 
740 	sx_xlock(&sc->call_lock);
741 	mtx_lock(&sc->io_lock);
742 
743 	set_slave_addr(sc, slave, 0);
744 	error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
745 				&byte, 1, NULL, 0, NULL);
746 
747 	mtx_unlock(&sc->io_lock);
748 	sx_xunlock(&sc->call_lock);
749 	return (error);
750 }
751 
752 /*
753  * Write command and single word in transaction.
754  */
755 int
756 ig4iic_smb_writew(device_t dev, u_char slave, char cmd, short word)
757 {
758 	ig4iic_softc_t *sc = device_get_softc(dev);
759 	char buf[2];
760 	int error;
761 
762 	sx_xlock(&sc->call_lock);
763 	mtx_lock(&sc->io_lock);
764 
765 	set_slave_addr(sc, slave, 0);
766 	buf[0] = word & 0xFF;
767 	buf[1] = word >> 8;
768 	error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
769 				buf, 2, NULL, 0, NULL);
770 
771 	mtx_unlock(&sc->io_lock);
772 	sx_xunlock(&sc->call_lock);
773 	return (error);
774 }
775 
776 /*
777  * write command and read single byte in transaction.
778  */
779 int
780 ig4iic_smb_readb(device_t dev, u_char slave, char cmd, char *byte)
781 {
782 	ig4iic_softc_t *sc = device_get_softc(dev);
783 	int error;
784 
785 	sx_xlock(&sc->call_lock);
786 	mtx_lock(&sc->io_lock);
787 
788 	set_slave_addr(sc, slave, 0);
789 	error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
790 				NULL, 0, byte, 1, NULL);
791 
792 	mtx_unlock(&sc->io_lock);
793 	sx_xunlock(&sc->call_lock);
794 	return (error);
795 }
796 
797 /*
798  * write command and read word in transaction.
799  */
800 int
801 ig4iic_smb_readw(device_t dev, u_char slave, char cmd, short *word)
802 {
803 	ig4iic_softc_t *sc = device_get_softc(dev);
804 	char buf[2];
805 	int error;
806 
807 	sx_xlock(&sc->call_lock);
808 	mtx_lock(&sc->io_lock);
809 
810 	set_slave_addr(sc, slave, 0);
811 	if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
812 				     NULL, 0, buf, 2, NULL)) == 0) {
813 		*word = (u_char)buf[0] | ((u_char)buf[1] << 8);
814 	}
815 
816 	mtx_unlock(&sc->io_lock);
817 	sx_xunlock(&sc->call_lock);
818 	return (error);
819 }
820 
821 /*
822  * write command and word and read word in transaction
823  */
824 int
825 ig4iic_smb_pcall(device_t dev, u_char slave, char cmd,
826 		 short sdata, short *rdata)
827 {
828 	ig4iic_softc_t *sc = device_get_softc(dev);
829 	char rbuf[2];
830 	char wbuf[2];
831 	int error;
832 
833 	sx_xlock(&sc->call_lock);
834 	mtx_lock(&sc->io_lock);
835 
836 	set_slave_addr(sc, slave, 0);
837 	wbuf[0] = sdata & 0xFF;
838 	wbuf[1] = sdata >> 8;
839 	if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
840 				     wbuf, 2, rbuf, 2, NULL)) == 0) {
841 		*rdata = (u_char)rbuf[0] | ((u_char)rbuf[1] << 8);
842 	}
843 
844 	mtx_unlock(&sc->io_lock);
845 	sx_xunlock(&sc->call_lock);
846 	return (error);
847 }
848 
849 int
850 ig4iic_smb_bwrite(device_t dev, u_char slave, char cmd,
851 		  u_char wcount, char *buf)
852 {
853 	ig4iic_softc_t *sc = device_get_softc(dev);
854 	int error;
855 
856 	sx_xlock(&sc->call_lock);
857 	mtx_lock(&sc->io_lock);
858 
859 	set_slave_addr(sc, slave, 0);
860 	error = smb_transaction(sc, cmd, 0,
861 				buf, wcount, NULL, 0, NULL);
862 
863 	mtx_unlock(&sc->io_lock);
864 	sx_xunlock(&sc->call_lock);
865 	return (error);
866 }
867 
868 int
869 ig4iic_smb_bread(device_t dev, u_char slave, char cmd,
870 		 u_char *countp_char, char *buf)
871 {
872 	ig4iic_softc_t *sc = device_get_softc(dev);
873 	int rcount = *countp_char;
874 	int error;
875 
876 	sx_xlock(&sc->call_lock);
877 	mtx_lock(&sc->io_lock);
878 
879 	set_slave_addr(sc, slave, 0);
880 	error = smb_transaction(sc, cmd, 0,
881 				NULL, 0, buf, rcount, &rcount);
882 	*countp_char = rcount;
883 
884 	mtx_unlock(&sc->io_lock);
885 	sx_xunlock(&sc->call_lock);
886 	return (error);
887 }
888 
889 int
890 ig4iic_smb_trans(device_t dev, int slave, char cmd, int op,
891 		 char *wbuf, int wcount, char *rbuf, int rcount,
892 		 int *actualp)
893 {
894 	ig4iic_softc_t *sc = device_get_softc(dev);
895 	int error;
896 
897 	sx_xlock(&sc->call_lock);
898 	mtx_lock(&sc->io_lock);
899 
900 	set_slave_addr(sc, slave, op);
901 	error = smb_transaction(sc, cmd, op,
902 				wbuf, wcount, rbuf, rcount, actualp);
903 
904 	mtx_unlock(&sc->io_lock);
905 	sx_xunlock(&sc->call_lock);
906 	return (error);
907 }
908 
909 /*
910  * Interrupt Operation, see ig4_var.h for locking semantics.
911  */
912 static void
913 ig4iic_intr(void *cookie)
914 {
915 	ig4iic_softc_t *sc = cookie;
916 	uint32_t status;
917 
918 	mtx_lock(&sc->io_lock);
919 /*	reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET);*/
920 	status = reg_read(sc, IG4_REG_I2C_STA);
921 	while (status & IG4_STATUS_RX_NOTEMPTY) {
922 		sc->rbuf[sc->rnext & IG4_RBUFMASK] =
923 		    (uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
924 		++sc->rnext;
925 		status = reg_read(sc, IG4_REG_I2C_STA);
926 	}
927 	reg_read(sc, IG4_REG_CLR_INTR);
928 	wakeup(sc);
929 	mtx_unlock(&sc->io_lock);
930 }
931 
932 #define REGDUMP(sc, reg)	\
933 	device_printf(sc->dev, "  %-23s %08x\n", #reg, reg_read(sc, reg))
934 
935 static void
936 ig4iic_dump(ig4iic_softc_t *sc)
937 {
938 	device_printf(sc->dev, "ig4iic register dump:\n");
939 	REGDUMP(sc, IG4_REG_CTL);
940 	REGDUMP(sc, IG4_REG_TAR_ADD);
941 	REGDUMP(sc, IG4_REG_SS_SCL_HCNT);
942 	REGDUMP(sc, IG4_REG_SS_SCL_LCNT);
943 	REGDUMP(sc, IG4_REG_FS_SCL_HCNT);
944 	REGDUMP(sc, IG4_REG_FS_SCL_LCNT);
945 	REGDUMP(sc, IG4_REG_INTR_STAT);
946 	REGDUMP(sc, IG4_REG_INTR_MASK);
947 	REGDUMP(sc, IG4_REG_RAW_INTR_STAT);
948 	REGDUMP(sc, IG4_REG_RX_TL);
949 	REGDUMP(sc, IG4_REG_TX_TL);
950 	REGDUMP(sc, IG4_REG_I2C_EN);
951 	REGDUMP(sc, IG4_REG_I2C_STA);
952 	REGDUMP(sc, IG4_REG_TXFLR);
953 	REGDUMP(sc, IG4_REG_RXFLR);
954 	REGDUMP(sc, IG4_REG_SDA_HOLD);
955 	REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE);
956 	REGDUMP(sc, IG4_REG_SLV_DATA_NACK);
957 	REGDUMP(sc, IG4_REG_DMA_CTRL);
958 	REGDUMP(sc, IG4_REG_DMA_TDLR);
959 	REGDUMP(sc, IG4_REG_DMA_RDLR);
960 	REGDUMP(sc, IG4_REG_SDA_SETUP);
961 	REGDUMP(sc, IG4_REG_ENABLE_STATUS);
962 	REGDUMP(sc, IG4_REG_COMP_PARAM1);
963 	REGDUMP(sc, IG4_REG_COMP_VER);
964 	REGDUMP(sc, IG4_REG_COMP_TYPE);
965 	REGDUMP(sc, IG4_REG_CLK_PARMS);
966 	REGDUMP(sc, IG4_REG_RESETS);
967 	REGDUMP(sc, IG4_REG_GENERAL);
968 	REGDUMP(sc, IG4_REG_SW_LTR_VALUE);
969 	REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);
970 }
971 #undef REGDUMP
972 
973 DRIVER_MODULE(smbus, ig4iic, smbus_driver, smbus_devclass, NULL, NULL);
974