1 /* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported 6 * to FreeBSD by Michael Gmelin <freebsd@grem.de> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 /* 38 * Intel fourth generation mobile cpus integrated I2C device. 39 * 40 * See ig4_reg.h for datasheet reference and notes. 41 * See ig4_var.h for locking semantics. 42 */ 43 44 #include "opt_acpi.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/module.h> 50 #include <sys/errno.h> 51 #include <sys/kdb.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/proc.h> 55 #include <sys/sx.h> 56 #include <sys/syslog.h> 57 #include <sys/bus.h> 58 #include <sys/sysctl.h> 59 60 #include <machine/bus.h> 61 #include <sys/rman.h> 62 63 #ifdef DEV_ACPI 64 #include <contrib/dev/acpica/include/acpi.h> 65 #include <contrib/dev/acpica/include/accommon.h> 66 #include <dev/acpica/acpivar.h> 67 #endif 68 69 #include <dev/iicbus/iicbus.h> 70 #include <dev/iicbus/iiconf.h> 71 72 #include <dev/ichiic/ig4_reg.h> 73 #include <dev/ichiic/ig4_var.h> 74 75 #define DO_POLL(sc) (cold || kdb_active || SCHEDULER_STOPPED() || sc->poll) 76 77 /* 78 * tLOW, tHIGH periods of the SCL clock and maximal falling time of both 79 * lines are taken from I2C specifications. 80 */ 81 #define IG4_SPEED_STD_THIGH 4000 /* nsec */ 82 #define IG4_SPEED_STD_TLOW 4700 /* nsec */ 83 #define IG4_SPEED_STD_TF_MAX 300 /* nsec */ 84 #define IG4_SPEED_FAST_THIGH 600 /* nsec */ 85 #define IG4_SPEED_FAST_TLOW 1300 /* nsec */ 86 #define IG4_SPEED_FAST_TF_MAX 300 /* nsec */ 87 88 /* 89 * Ig4 hardware parameters except Haswell are taken from intel_lpss driver 90 */ 91 static const struct ig4_hw ig4iic_hw[] = { 92 [IG4_EMAG] = { 93 .ic_clock_rate = 100, /* MHz */ 94 }, 95 [IG4_HASWELL] = { 96 .ic_clock_rate = 100, /* MHz */ 97 .sda_hold_time = 90, /* nsec */ 98 .txfifo_depth = 32, 99 .rxfifo_depth = 32, 100 }, 101 [IG4_ATOM] = { 102 .ic_clock_rate = 100, 103 .sda_fall_time = 280, 104 .scl_fall_time = 240, 105 .sda_hold_time = 60, 106 .txfifo_depth = 32, 107 .rxfifo_depth = 32, 108 }, 109 [IG4_SKYLAKE] = { 110 .ic_clock_rate = 120, 111 .sda_hold_time = 230, 112 }, 113 [IG4_APL] = { 114 .ic_clock_rate = 133, 115 .sda_fall_time = 171, 116 .scl_fall_time = 208, 117 .sda_hold_time = 207, 118 }, 119 [IG4_CANNONLAKE] = { 120 .ic_clock_rate = 216, 121 .sda_hold_time = 230, 122 }, 123 [IG4_TIGERLAKE] = { 124 .ic_clock_rate = 133, 125 .sda_fall_time = 171, 126 .scl_fall_time = 208, 127 .sda_hold_time = 42, 128 }, 129 [IG4_GEMINILAKE] = { 130 .ic_clock_rate = 133, 131 .sda_fall_time = 171, 132 .scl_fall_time = 290, 133 .sda_hold_time = 313, 134 }, 135 }; 136 137 static int ig4iic_set_config(ig4iic_softc_t *sc, bool reset); 138 static driver_filter_t ig4iic_intr; 139 static void ig4iic_dump(ig4iic_softc_t *sc); 140 141 static int ig4_dump; 142 SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW, 143 &ig4_dump, 0, "Dump controller registers"); 144 145 /* 146 * Clock registers initialization control 147 * 0 - Try read clock registers from ACPI and fallback to p.1. 148 * 1 - Calculate values based on controller type (IC clock rate). 149 * 2 - Use values inherited from DragonflyBSD driver (old behavior). 150 * 3 - Keep clock registers intact. 151 */ 152 static int ig4_timings; 153 SYSCTL_INT(_debug, OID_AUTO, ig4_timings, CTLFLAG_RDTUN, &ig4_timings, 0, 154 "Controller timings 0=ACPI, 1=predefined, 2=legacy, 3=do not change"); 155 156 /* 157 * Low-level inline support functions 158 */ 159 static __inline void 160 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value) 161 { 162 bus_write_4(sc->regs_res, reg, value); 163 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE); 164 } 165 166 static __inline uint32_t 167 reg_read(ig4iic_softc_t *sc, uint32_t reg) 168 { 169 uint32_t value; 170 171 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ); 172 value = bus_read_4(sc->regs_res, reg); 173 return (value); 174 } 175 176 static void 177 ig4iic_set_intr_mask(ig4iic_softc_t *sc, uint32_t val) 178 { 179 if (sc->intr_mask != val) { 180 reg_write(sc, IG4_REG_INTR_MASK, val); 181 sc->intr_mask = val; 182 } 183 } 184 185 static int 186 intrstat2iic(ig4iic_softc_t *sc, uint32_t val) 187 { 188 uint32_t src; 189 190 if (val & IG4_INTR_RX_UNDER) 191 reg_read(sc, IG4_REG_CLR_RX_UNDER); 192 if (val & IG4_INTR_RX_OVER) 193 reg_read(sc, IG4_REG_CLR_RX_OVER); 194 if (val & IG4_INTR_TX_OVER) 195 reg_read(sc, IG4_REG_CLR_TX_OVER); 196 197 if (val & IG4_INTR_TX_ABRT) { 198 src = reg_read(sc, IG4_REG_TX_ABRT_SOURCE); 199 reg_read(sc, IG4_REG_CLR_TX_ABORT); 200 /* User-requested abort. Not really a error */ 201 if (src & IG4_ABRTSRC_TRANSFER) 202 return (IIC_ESTATUS); 203 /* Master has lost arbitration */ 204 if (src & IG4_ABRTSRC_ARBLOST) 205 return (IIC_EBUSBSY); 206 /* Did not receive an acknowledge from the remote slave */ 207 if (src & (IG4_ABRTSRC_TXNOACK_ADDR7 | 208 IG4_ABRTSRC_TXNOACK_ADDR10_1 | 209 IG4_ABRTSRC_TXNOACK_ADDR10_2 | 210 IG4_ABRTSRC_TXNOACK_DATA | 211 IG4_ABRTSRC_GENCALL_NOACK)) 212 return (IIC_ENOACK); 213 /* Programming errors */ 214 if (src & (IG4_ABRTSRC_GENCALL_READ | 215 IG4_ABRTSRC_NORESTART_START | 216 IG4_ABRTSRC_NORESTART_10)) 217 return (IIC_ENOTSUPP); 218 /* Other errors */ 219 if (src & IG4_ABRTSRC_ACKED_START) 220 return (IIC_EBUSERR); 221 } 222 /* 223 * TX_OVER, RX_OVER and RX_UNDER are caused by wrong RX/TX FIFO depth 224 * detection or driver's read/write pipelining errors. 225 */ 226 if (val & (IG4_INTR_TX_OVER | IG4_INTR_RX_OVER)) 227 return (IIC_EOVERFLOW); 228 if (val & IG4_INTR_RX_UNDER) 229 return (IIC_EUNDERFLOW); 230 231 return (IIC_NOERR); 232 } 233 234 /* 235 * Enable or disable the controller and wait for the controller to acknowledge 236 * the state change. 237 */ 238 static int 239 set_controller(ig4iic_softc_t *sc, uint32_t ctl) 240 { 241 int retry; 242 int error; 243 uint32_t v; 244 245 /* 246 * When the controller is enabled, interrupt on STOP detect 247 * or receive character ready and clear pending interrupts. 248 */ 249 ig4iic_set_intr_mask(sc, 0); 250 if (ctl & IG4_I2C_ENABLE) 251 reg_read(sc, IG4_REG_CLR_INTR); 252 253 reg_write(sc, IG4_REG_I2C_EN, ctl); 254 error = IIC_ETIMEOUT; 255 256 for (retry = 100; retry > 0; --retry) { 257 v = reg_read(sc, IG4_REG_ENABLE_STATUS); 258 if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) { 259 error = 0; 260 break; 261 } 262 pause("i2cslv", 1); 263 } 264 return (error); 265 } 266 267 /* 268 * Wait up to 25ms for the requested interrupt using a 25uS polling loop. 269 */ 270 static int 271 wait_intr(ig4iic_softc_t *sc, uint32_t intr) 272 { 273 uint32_t v; 274 int error; 275 int txlvl = -1; 276 u_int count_us = 0; 277 u_int limit_us = 1000000; /* 1sec */ 278 279 for (;;) { 280 /* 281 * Check requested status 282 */ 283 v = reg_read(sc, IG4_REG_RAW_INTR_STAT); 284 error = intrstat2iic(sc, v & IG4_INTR_ERR_MASK); 285 if (error || (v & intr)) 286 break; 287 288 /* 289 * When waiting for the transmit FIFO to become empty, 290 * reset the timeout if we see a change in the transmit 291 * FIFO level as progress is being made. 292 */ 293 if (intr & (IG4_INTR_TX_EMPTY | IG4_INTR_STOP_DET)) { 294 v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK; 295 if (txlvl != v) { 296 txlvl = v; 297 count_us = 0; 298 } 299 } 300 301 /* 302 * Stop if we've run out of time. 303 */ 304 if (count_us >= limit_us) { 305 error = IIC_ETIMEOUT; 306 break; 307 } 308 309 /* 310 * When polling is not requested let the interrupt do its work. 311 */ 312 if (!DO_POLL(sc)) { 313 mtx_lock_spin(&sc->io_lock); 314 ig4iic_set_intr_mask(sc, intr | IG4_INTR_ERR_MASK); 315 msleep_spin(sc, &sc->io_lock, "i2cwait", 316 (hz + 99) / 100); /* sleep up to 10ms */ 317 ig4iic_set_intr_mask(sc, 0); 318 mtx_unlock_spin(&sc->io_lock); 319 count_us += 10000; 320 } else { 321 DELAY(25); 322 count_us += 25; 323 } 324 } 325 326 return (error); 327 } 328 329 /* 330 * Set the slave address. The controller must be disabled when 331 * changing the address. 332 * 333 * This operation does not issue anything to the I2C bus but sets 334 * the target address for when the controller later issues a START. 335 */ 336 static void 337 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave) 338 { 339 uint32_t tar; 340 uint32_t ctl; 341 bool use_10bit; 342 343 use_10bit = false; 344 if (sc->slave_valid && sc->last_slave == slave && 345 sc->use_10bit == use_10bit) { 346 return; 347 } 348 sc->use_10bit = use_10bit; 349 350 /* 351 * Wait for TXFIFO to drain before disabling the controller. 352 */ 353 reg_write(sc, IG4_REG_TX_TL, 0); 354 wait_intr(sc, IG4_INTR_TX_EMPTY); 355 356 set_controller(sc, 0); 357 ctl = reg_read(sc, IG4_REG_CTL); 358 ctl &= ~IG4_CTL_10BIT; 359 ctl |= IG4_CTL_RESTARTEN; 360 361 tar = slave; 362 if (sc->use_10bit) { 363 tar |= IG4_TAR_10BIT; 364 ctl |= IG4_CTL_10BIT; 365 } 366 reg_write(sc, IG4_REG_CTL, ctl); 367 reg_write(sc, IG4_REG_TAR_ADD, tar); 368 set_controller(sc, IG4_I2C_ENABLE); 369 sc->slave_valid = true; 370 sc->last_slave = slave; 371 } 372 373 /* 374 * IICBUS API FUNCTIONS 375 */ 376 static int 377 ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave, bool repeated_start) 378 { 379 set_slave_addr(sc, slave >> 1); 380 381 if (!repeated_start) { 382 /* 383 * Clear any previous TX/RX FIFOs overflow/underflow bits 384 * and I2C bus STOP condition. 385 */ 386 reg_read(sc, IG4_REG_CLR_INTR); 387 } 388 389 return (0); 390 } 391 392 static bool 393 ig4iic_xfer_is_started(ig4iic_softc_t *sc) 394 { 395 /* 396 * It requires that no IG4_REG_CLR_INTR or IG4_REG_CLR_START/STOP_DET 397 * register reads is issued after START condition. 398 */ 399 return ((reg_read(sc, IG4_REG_RAW_INTR_STAT) & 400 (IG4_INTR_START_DET | IG4_INTR_STOP_DET)) == IG4_INTR_START_DET); 401 } 402 403 static int 404 ig4iic_xfer_abort(ig4iic_softc_t *sc) 405 { 406 int error; 407 408 /* Request send of STOP condition and flush of TX FIFO */ 409 set_controller(sc, IG4_I2C_ABORT | IG4_I2C_ENABLE); 410 /* 411 * Wait for the TX_ABRT interrupt with ABRTSRC_TRANSFER 412 * bit set in TX_ABRT_SOURCE register. 413 */ 414 error = wait_intr(sc, IG4_INTR_STOP_DET); 415 set_controller(sc, IG4_I2C_ENABLE); 416 417 return (error == IIC_ESTATUS ? 0 : error); 418 } 419 420 /* 421 * Amount of unread data before next burst to get better I2C bus utilization. 422 * 2 bytes is enough in FAST mode. 8 bytes is better in FAST+ and HIGH modes. 423 * Intel-recommended value is 16 for DMA transfers with 64-byte depth FIFOs. 424 */ 425 #define IG4_FIFO_LOWAT 2 426 427 static int 428 ig4iic_read(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len, 429 bool repeated_start, bool stop) 430 { 431 uint32_t cmd; 432 int requested = 0; 433 int received = 0; 434 int burst, target, lowat = 0; 435 int error; 436 437 if (len == 0) 438 return (0); 439 440 while (received < len) { 441 /* Ensure we have some free space in TXFIFO */ 442 burst = sc->cfg.txfifo_depth - 443 (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK); 444 if (burst <= 0) { 445 reg_write(sc, IG4_REG_TX_TL, IG4_FIFO_LOWAT); 446 error = wait_intr(sc, IG4_INTR_TX_EMPTY); 447 if (error) 448 break; 449 burst = sc->cfg.txfifo_depth - 450 (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK); 451 } 452 /* Ensure we have enough free space in RXFIFO */ 453 burst = MIN(burst, sc->cfg.rxfifo_depth - 454 (requested - received)); 455 target = MIN(requested + burst, (int)len); 456 while (requested < target) { 457 cmd = IG4_DATA_COMMAND_RD; 458 if (repeated_start && requested == 0) 459 cmd |= IG4_DATA_RESTART; 460 if (stop && requested == len - 1) 461 cmd |= IG4_DATA_STOP; 462 reg_write(sc, IG4_REG_DATA_CMD, cmd); 463 requested++; 464 } 465 /* Leave some data queued to maintain the hardware pipeline */ 466 lowat = 0; 467 if (requested != len && requested - received > IG4_FIFO_LOWAT) 468 lowat = IG4_FIFO_LOWAT; 469 /* After TXFLR fills up, clear it by reading available data */ 470 while (received < requested - lowat) { 471 burst = MIN(requested - received, 472 reg_read(sc, IG4_REG_RXFLR) & IG4_FIFOLVL_MASK); 473 if (burst > 0) { 474 while (burst--) 475 buf[received++] = 0xFF & 476 reg_read(sc, IG4_REG_DATA_CMD); 477 } else { 478 reg_write(sc, IG4_REG_RX_TL, 479 requested - received - lowat - 1); 480 error = wait_intr(sc, IG4_INTR_RX_FULL); 481 if (error) 482 goto out; 483 } 484 } 485 } 486 out: 487 return (error); 488 } 489 490 static int 491 ig4iic_write(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len, 492 bool repeated_start, bool stop) 493 { 494 uint32_t cmd; 495 int sent = 0; 496 int burst, target; 497 int error, lowat; 498 499 if (len == 0) 500 return (0); 501 502 while (sent < len) { 503 burst = sc->cfg.txfifo_depth - 504 (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK); 505 target = MIN(sent + burst, (int)len); 506 while (sent < target) { 507 cmd = buf[sent]; 508 if (repeated_start && sent == 0) 509 cmd |= IG4_DATA_RESTART; 510 if (stop && sent == len - 1) 511 cmd |= IG4_DATA_STOP; 512 reg_write(sc, IG4_REG_DATA_CMD, cmd); 513 sent++; 514 } 515 if (sent < len) { 516 if (len - sent <= sc->cfg.txfifo_depth) 517 lowat = sc->cfg.txfifo_depth - (len - sent); 518 else 519 lowat = IG4_FIFO_LOWAT; 520 reg_write(sc, IG4_REG_TX_TL, lowat); 521 error = wait_intr(sc, IG4_INTR_TX_EMPTY); 522 if (error) 523 break; 524 } 525 } 526 527 return (error); 528 } 529 530 int 531 ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 532 { 533 ig4iic_softc_t *sc = device_get_softc(dev); 534 const char *reason = NULL; 535 uint32_t i; 536 int error; 537 int unit; 538 bool rpstart; 539 bool stop; 540 bool allocated; 541 542 /* 543 * The hardware interface imposes limits on allowed I2C messages. 544 * It is not possible to explicitly send a start or stop. 545 * They are automatically sent (or not sent, depending on the 546 * configuration) when a data byte is transferred. 547 * For this reason it's impossible to send a message with no data 548 * at all (like an SMBus quick message). 549 * The start condition is automatically generated after the stop 550 * condition, so it's impossible to not have a start after a stop. 551 * The repeated start condition is automatically sent if a change 552 * of the transfer direction happens, so it's impossible to have 553 * a change of direction without a (repeated) start. 554 * The repeated start can be forced even without the change of 555 * direction. 556 * Changing the target slave address requires resetting the hardware 557 * state, so it's impossible to do that without the stop followed 558 * by the start. 559 */ 560 for (i = 0; i < nmsgs; i++) { 561 #if 0 562 if (i == 0 && (msgs[i].flags & IIC_M_NOSTART) != 0) { 563 reason = "first message without start"; 564 break; 565 } 566 if (i == nmsgs - 1 && (msgs[i].flags & IIC_M_NOSTOP) != 0) { 567 reason = "last message without stop"; 568 break; 569 } 570 #endif 571 if (msgs[i].len == 0) { 572 reason = "message with no data"; 573 break; 574 } 575 if (i > 0) { 576 if ((msgs[i].flags & IIC_M_NOSTART) != 0 && 577 (msgs[i - 1].flags & IIC_M_NOSTOP) == 0) { 578 reason = "stop not followed by start"; 579 break; 580 } 581 if ((msgs[i - 1].flags & IIC_M_NOSTOP) != 0 && 582 msgs[i].slave != msgs[i - 1].slave) { 583 reason = "change of slave without stop"; 584 break; 585 } 586 if ((msgs[i].flags & IIC_M_NOSTART) != 0 && 587 (msgs[i].flags & IIC_M_RD) != 588 (msgs[i - 1].flags & IIC_M_RD)) { 589 reason = "change of direction without repeated" 590 " start"; 591 break; 592 } 593 } 594 } 595 if (reason != NULL) { 596 if (bootverbose) 597 device_printf(dev, "%s\n", reason); 598 return (IIC_ENOTSUPP); 599 } 600 601 /* Check if device is already allocated with iicbus_request_bus() */ 602 allocated = sx_xlocked(&sc->call_lock) != 0; 603 if (!allocated) 604 sx_xlock(&sc->call_lock); 605 606 /* Debugging - dump registers. */ 607 if (ig4_dump) { 608 unit = device_get_unit(dev); 609 if (ig4_dump & (1 << unit)) { 610 ig4_dump &= ~(1 << unit); 611 ig4iic_dump(sc); 612 } 613 } 614 615 /* 616 * Clear any previous abort condition that may have been holding 617 * the txfifo in reset. 618 */ 619 reg_read(sc, IG4_REG_CLR_TX_ABORT); 620 621 rpstart = false; 622 error = 0; 623 for (i = 0; i < nmsgs; i++) { 624 if ((msgs[i].flags & IIC_M_NOSTART) == 0) { 625 error = ig4iic_xfer_start(sc, msgs[i].slave, rpstart); 626 } else { 627 if (!sc->slave_valid || 628 (msgs[i].slave >> 1) != sc->last_slave) { 629 device_printf(dev, "start condition suppressed" 630 "but slave address is not set up"); 631 error = EINVAL; 632 break; 633 } 634 rpstart = false; 635 } 636 if (error != 0) 637 break; 638 639 stop = (msgs[i].flags & IIC_M_NOSTOP) == 0; 640 if (msgs[i].flags & IIC_M_RD) 641 error = ig4iic_read(sc, msgs[i].buf, msgs[i].len, 642 rpstart, stop); 643 else 644 error = ig4iic_write(sc, msgs[i].buf, msgs[i].len, 645 rpstart, stop); 646 647 /* Wait for error or stop condition occurred on the I2C bus */ 648 if (stop && error == 0) { 649 error = wait_intr(sc, IG4_INTR_STOP_DET); 650 if (error == 0) 651 reg_read(sc, IG4_REG_CLR_INTR); 652 } 653 654 if (error != 0) { 655 /* 656 * Send STOP condition if it's not done yet and flush 657 * both FIFOs. Do a controller soft reset if transfer 658 * abort is failed. 659 */ 660 if (ig4iic_xfer_is_started(sc) && 661 ig4iic_xfer_abort(sc) != 0) { 662 device_printf(sc->dev, "Failed to abort " 663 "transfer. Do the controller reset.\n"); 664 ig4iic_set_config(sc, true); 665 } else { 666 while (reg_read(sc, IG4_REG_I2C_STA) & 667 IG4_STATUS_RX_NOTEMPTY) 668 reg_read(sc, IG4_REG_DATA_CMD); 669 reg_read(sc, IG4_REG_TX_ABRT_SOURCE); 670 reg_read(sc, IG4_REG_CLR_INTR); 671 } 672 break; 673 } 674 675 rpstart = !stop; 676 } 677 678 if (!allocated) 679 sx_unlock(&sc->call_lock); 680 return (error); 681 } 682 683 int 684 ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 685 { 686 ig4iic_softc_t *sc = device_get_softc(dev); 687 bool allocated; 688 689 allocated = sx_xlocked(&sc->call_lock) != 0; 690 if (!allocated) 691 sx_xlock(&sc->call_lock); 692 693 /* TODO handle speed configuration? */ 694 if (oldaddr != NULL) 695 *oldaddr = sc->last_slave << 1; 696 set_slave_addr(sc, addr >> 1); 697 if (addr == IIC_UNKNOWN) 698 sc->slave_valid = false; 699 700 if (!allocated) 701 sx_unlock(&sc->call_lock); 702 return (0); 703 } 704 705 int 706 ig4iic_callback(device_t dev, int index, caddr_t data) 707 { 708 ig4iic_softc_t *sc = device_get_softc(dev); 709 int error = 0; 710 int how; 711 712 switch (index) { 713 case IIC_REQUEST_BUS: 714 /* force polling if ig4iic is requested with IIC_DONTWAIT */ 715 how = *(int *)data; 716 if ((how & IIC_WAIT) == 0) { 717 if (sx_try_xlock(&sc->call_lock) == 0) 718 error = IIC_EBUSBSY; 719 else 720 sc->poll = true; 721 } else 722 sx_xlock(&sc->call_lock); 723 break; 724 725 case IIC_RELEASE_BUS: 726 sc->poll = false; 727 sx_unlock(&sc->call_lock); 728 break; 729 730 default: 731 error = errno2iic(EINVAL); 732 } 733 734 return (error); 735 } 736 737 /* 738 * Clock register values can be calculated with following rough equations: 739 * SCL_HCNT = ceil(IC clock rate * tHIGH) 740 * SCL_LCNT = ceil(IC clock rate * tLOW) 741 * SDA_HOLD = ceil(IC clock rate * SDA hold time) 742 * Precise equations take signal's falling, rising and spike suppression 743 * times in to account. They can be found in Synopsys or Intel documentation. 744 * 745 * Here we snarf formulas and defaults from Linux driver to be able to use 746 * timing values provided by Intel LPSS driver "as is". 747 */ 748 static int 749 ig4iic_clk_params(const struct ig4_hw *hw, int speed, 750 uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold) 751 { 752 uint32_t thigh, tlow, tf_max; /* nsec */ 753 uint32_t sda_fall_time; /* nsec */ 754 uint32_t scl_fall_time; /* nsec */ 755 756 switch (speed) { 757 case IG4_CTL_SPEED_STD: 758 thigh = IG4_SPEED_STD_THIGH; 759 tlow = IG4_SPEED_STD_TLOW; 760 tf_max = IG4_SPEED_STD_TF_MAX; 761 break; 762 763 case IG4_CTL_SPEED_FAST: 764 thigh = IG4_SPEED_FAST_THIGH; 765 tlow = IG4_SPEED_FAST_TLOW; 766 tf_max = IG4_SPEED_FAST_TF_MAX; 767 break; 768 769 default: 770 return (EINVAL); 771 } 772 773 /* Use slowest falling time defaults to be on the safe side */ 774 sda_fall_time = hw->sda_fall_time == 0 ? tf_max : hw->sda_fall_time; 775 *scl_hcnt = (uint16_t) 776 ((hw->ic_clock_rate * (thigh + sda_fall_time) + 500) / 1000 - 3); 777 778 scl_fall_time = hw->scl_fall_time == 0 ? tf_max : hw->scl_fall_time; 779 *scl_lcnt = (uint16_t) 780 ((hw->ic_clock_rate * (tlow + scl_fall_time) + 500) / 1000 - 1); 781 782 /* 783 * There is no "known good" default value for tHD;DAT so keep SDA_HOLD 784 * intact if sda_hold_time value is not provided. 785 */ 786 if (hw->sda_hold_time != 0) 787 *sda_hold = (uint16_t) 788 ((hw->ic_clock_rate * hw->sda_hold_time + 500) / 1000); 789 790 return (0); 791 } 792 793 #ifdef DEV_ACPI 794 static ACPI_STATUS 795 ig4iic_acpi_params(ACPI_HANDLE handle, char *method, 796 uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold) 797 { 798 ACPI_BUFFER buf; 799 ACPI_OBJECT *obj, *elems; 800 ACPI_STATUS status; 801 802 buf.Pointer = NULL; 803 buf.Length = ACPI_ALLOCATE_BUFFER; 804 805 status = AcpiEvaluateObject(handle, method, NULL, &buf); 806 if (ACPI_FAILURE(status)) 807 return (status); 808 809 status = AE_TYPE; 810 obj = (ACPI_OBJECT *)buf.Pointer; 811 if (obj->Type == ACPI_TYPE_PACKAGE && obj->Package.Count == 3) { 812 elems = obj->Package.Elements; 813 *scl_hcnt = elems[0].Integer.Value & IG4_SCL_CLOCK_MASK; 814 *scl_lcnt = elems[1].Integer.Value & IG4_SCL_CLOCK_MASK; 815 *sda_hold = elems[2].Integer.Value & IG4_SDA_TX_HOLD_MASK; 816 status = AE_OK; 817 } 818 819 AcpiOsFree(obj); 820 821 return (status); 822 } 823 #endif /* DEV_ACPI */ 824 825 static void 826 ig4iic_get_config(ig4iic_softc_t *sc) 827 { 828 const struct ig4_hw *hw; 829 uint32_t v; 830 #ifdef DEV_ACPI 831 ACPI_HANDLE handle; 832 #endif 833 /* Fetch default hardware config from controller */ 834 sc->cfg.version = reg_read(sc, IG4_REG_COMP_VER); 835 sc->cfg.bus_speed = reg_read(sc, IG4_REG_CTL) & IG4_CTL_SPEED_MASK; 836 sc->cfg.ss_scl_hcnt = 837 reg_read(sc, IG4_REG_SS_SCL_HCNT) & IG4_SCL_CLOCK_MASK; 838 sc->cfg.ss_scl_lcnt = 839 reg_read(sc, IG4_REG_SS_SCL_LCNT) & IG4_SCL_CLOCK_MASK; 840 sc->cfg.fs_scl_hcnt = 841 reg_read(sc, IG4_REG_FS_SCL_HCNT) & IG4_SCL_CLOCK_MASK; 842 sc->cfg.fs_scl_lcnt = 843 reg_read(sc, IG4_REG_FS_SCL_LCNT) & IG4_SCL_CLOCK_MASK; 844 sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = 845 reg_read(sc, IG4_REG_SDA_HOLD) & IG4_SDA_TX_HOLD_MASK; 846 847 if (sc->cfg.bus_speed != IG4_CTL_SPEED_STD) 848 sc->cfg.bus_speed = IG4_CTL_SPEED_FAST; 849 850 /* REG_COMP_PARAM1 is not documented in latest Intel specs */ 851 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 852 v = reg_read(sc, IG4_REG_COMP_PARAM1); 853 if (IG4_PARAM1_TXFIFO_DEPTH(v) != 0) 854 sc->cfg.txfifo_depth = IG4_PARAM1_TXFIFO_DEPTH(v); 855 if (IG4_PARAM1_RXFIFO_DEPTH(v) != 0) 856 sc->cfg.rxfifo_depth = IG4_PARAM1_RXFIFO_DEPTH(v); 857 } 858 859 /* Override hardware config with IC_clock-based counter values */ 860 if (ig4_timings < 2 && sc->version < nitems(ig4iic_hw)) { 861 hw = &ig4iic_hw[sc->version]; 862 sc->cfg.bus_speed = IG4_CTL_SPEED_FAST; 863 ig4iic_clk_params(hw, IG4_CTL_SPEED_STD, &sc->cfg.ss_scl_hcnt, 864 &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold); 865 ig4iic_clk_params(hw, IG4_CTL_SPEED_FAST, &sc->cfg.fs_scl_hcnt, 866 &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold); 867 if (hw->txfifo_depth != 0) 868 sc->cfg.txfifo_depth = hw->txfifo_depth; 869 if (hw->rxfifo_depth != 0) 870 sc->cfg.rxfifo_depth = hw->rxfifo_depth; 871 } else if (ig4_timings == 2) { 872 /* 873 * Timings of original ig4 driver: 874 * Program based on a 25000 Hz clock. This is a bit of a 875 * hack (obviously). The defaults are 400 and 470 for standard 876 * and 60 and 130 for fast. The defaults for standard fail 877 * utterly (presumably cause an abort) because the clock time 878 * is ~18.8ms by default. This brings it down to ~4ms. 879 */ 880 sc->cfg.bus_speed = IG4_CTL_SPEED_STD; 881 sc->cfg.ss_scl_hcnt = sc->cfg.fs_scl_hcnt = 100; 882 sc->cfg.ss_scl_lcnt = sc->cfg.fs_scl_lcnt = 125; 883 if (sc->version == IG4_SKYLAKE) 884 sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = 28; 885 } 886 887 #ifdef DEV_ACPI 888 /* Evaluate SSCN and FMCN ACPI methods to fetch timings */ 889 if (ig4_timings == 0 && (handle = acpi_get_handle(sc->dev)) != NULL) { 890 ig4iic_acpi_params(handle, "SSCN", &sc->cfg.ss_scl_hcnt, 891 &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold); 892 ig4iic_acpi_params(handle, "FMCN", &sc->cfg.fs_scl_hcnt, 893 &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold); 894 } 895 #endif 896 897 if (bootverbose) { 898 device_printf(sc->dev, "Controller parameters:\n"); 899 printf(" Speed: %s\n", 900 sc->cfg.bus_speed == IG4_CTL_SPEED_STD ? "Std" : "Fast"); 901 printf(" Regs: HCNT :LCNT :SDAHLD\n"); 902 printf(" Std: 0x%04hx:0x%04hx:0x%04hx\n", 903 sc->cfg.ss_scl_hcnt, sc->cfg.ss_scl_lcnt, 904 sc->cfg.ss_sda_hold); 905 printf(" Fast: 0x%04hx:0x%04hx:0x%04hx\n", 906 sc->cfg.fs_scl_hcnt, sc->cfg.fs_scl_lcnt, 907 sc->cfg.fs_sda_hold); 908 } 909 } 910 911 static int 912 ig4iic_set_config(ig4iic_softc_t *sc, bool reset) 913 { 914 uint32_t v; 915 916 v = reg_read(sc, IG4_REG_DEVIDLE_CTRL); 917 if (IG4_HAS_ADDREGS(sc->version) && (v & IG4_RESTORE_REQUIRED)) { 918 reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE | IG4_RESTORE_REQUIRED); 919 reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0); 920 pause("i2crst", 1); 921 reset = true; 922 } 923 924 if ((sc->version == IG4_HASWELL || sc->version == IG4_ATOM) && reset) { 925 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW); 926 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW); 927 } else if (IG4_HAS_ADDREGS(sc->version) && reset) { 928 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); 929 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL); 930 } 931 932 if (sc->version == IG4_ATOM) 933 v = reg_read(sc, IG4_REG_COMP_TYPE); 934 935 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 936 v = reg_read(sc, IG4_REG_COMP_PARAM1); 937 v = reg_read(sc, IG4_REG_GENERAL); 938 /* 939 * The content of IG4_REG_GENERAL is different for each 940 * controller version. 941 */ 942 if (sc->version == IG4_HASWELL && 943 (v & IG4_GENERAL_SWMODE) == 0) { 944 v |= IG4_GENERAL_SWMODE; 945 reg_write(sc, IG4_REG_GENERAL, v); 946 v = reg_read(sc, IG4_REG_GENERAL); 947 } 948 } 949 950 if (sc->version == IG4_HASWELL) { 951 v = reg_read(sc, IG4_REG_SW_LTR_VALUE); 952 v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE); 953 } else if (IG4_HAS_ADDREGS(sc->version)) { 954 v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE); 955 v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE); 956 } 957 958 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 959 v = reg_read(sc, IG4_REG_COMP_VER); 960 if (v < IG4_COMP_MIN_VER) 961 return(ENXIO); 962 } 963 964 if (set_controller(sc, 0)) { 965 device_printf(sc->dev, "controller error during attach-1\n"); 966 return (ENXIO); 967 } 968 969 reg_read(sc, IG4_REG_CLR_INTR); 970 reg_write(sc, IG4_REG_INTR_MASK, 0); 971 sc->intr_mask = 0; 972 973 reg_write(sc, IG4_REG_SS_SCL_HCNT, sc->cfg.ss_scl_hcnt); 974 reg_write(sc, IG4_REG_SS_SCL_LCNT, sc->cfg.ss_scl_lcnt); 975 reg_write(sc, IG4_REG_FS_SCL_HCNT, sc->cfg.fs_scl_hcnt); 976 reg_write(sc, IG4_REG_FS_SCL_LCNT, sc->cfg.fs_scl_lcnt); 977 reg_write(sc, IG4_REG_SDA_HOLD, 978 (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK) == IG4_CTL_SPEED_STD ? 979 sc->cfg.ss_sda_hold : sc->cfg.fs_sda_hold); 980 981 reg_write(sc, IG4_REG_RX_TL, 0); 982 reg_write(sc, IG4_REG_TX_TL, 0); 983 984 reg_write(sc, IG4_REG_CTL, 985 IG4_CTL_MASTER | 986 IG4_CTL_SLAVE_DISABLE | 987 IG4_CTL_RESTARTEN | 988 (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK)); 989 990 /* Force setting of the target address on the next transfer */ 991 sc->slave_valid = false; 992 993 return (0); 994 } 995 996 static void 997 ig4iic_get_fifo(ig4iic_softc_t *sc) 998 { 999 uint32_t v; 1000 1001 /* 1002 * Hardware does not allow FIFO Threshold Levels value to be set larger 1003 * than the depth of the buffer. If an attempt is made to do that, the 1004 * actual value set will be the maximum depth of the buffer. 1005 */ 1006 if (sc->cfg.txfifo_depth == 0) { 1007 v = reg_read(sc, IG4_REG_TX_TL); 1008 reg_write(sc, IG4_REG_TX_TL, v | IG4_FIFO_MASK); 1009 sc->cfg.txfifo_depth = 1010 (reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1; 1011 reg_write(sc, IG4_REG_TX_TL, v); 1012 } 1013 if (sc->cfg.rxfifo_depth == 0) { 1014 v = reg_read(sc, IG4_REG_RX_TL); 1015 reg_write(sc, IG4_REG_RX_TL, v | IG4_FIFO_MASK); 1016 sc->cfg.rxfifo_depth = 1017 (reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1; 1018 reg_write(sc, IG4_REG_RX_TL, v); 1019 } 1020 if (bootverbose) { 1021 printf(" FIFO: RX:0x%04x: TX:0x%04x\n", 1022 sc->cfg.rxfifo_depth, sc->cfg.txfifo_depth); 1023 } 1024 } 1025 1026 /* 1027 * Called from ig4iic_pci_attach/detach() 1028 */ 1029 int 1030 ig4iic_attach(ig4iic_softc_t *sc) 1031 { 1032 int error; 1033 1034 mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_SPIN); 1035 sx_init(&sc->call_lock, "IG4 call lock"); 1036 1037 ig4iic_get_config(sc); 1038 1039 error = ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version)); 1040 if (error) 1041 goto done; 1042 ig4iic_get_fifo(sc); 1043 1044 sc->iicbus = device_add_child(sc->dev, "iicbus", -1); 1045 if (sc->iicbus == NULL) { 1046 device_printf(sc->dev, "iicbus driver not found\n"); 1047 error = ENXIO; 1048 goto done; 1049 } 1050 1051 if (set_controller(sc, IG4_I2C_ENABLE)) { 1052 device_printf(sc->dev, "controller error during attach-2\n"); 1053 error = ENXIO; 1054 goto done; 1055 } 1056 if (set_controller(sc, 0)) { 1057 device_printf(sc->dev, "controller error during attach-3\n"); 1058 error = ENXIO; 1059 goto done; 1060 } 1061 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC | INTR_MPSAFE, 1062 ig4iic_intr, NULL, sc, &sc->intr_handle); 1063 if (error) { 1064 device_printf(sc->dev, 1065 "Unable to setup irq: error %d\n", error); 1066 } 1067 1068 error = bus_generic_attach(sc->dev); 1069 if (error) { 1070 device_printf(sc->dev, 1071 "failed to attach child: error %d\n", error); 1072 } 1073 1074 done: 1075 return (error); 1076 } 1077 1078 int 1079 ig4iic_detach(ig4iic_softc_t *sc) 1080 { 1081 int error; 1082 1083 if (device_is_attached(sc->dev)) { 1084 error = bus_generic_detach(sc->dev); 1085 if (error) 1086 return (error); 1087 } 1088 if (sc->iicbus) 1089 device_delete_child(sc->dev, sc->iicbus); 1090 if (sc->intr_handle) 1091 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle); 1092 1093 sx_xlock(&sc->call_lock); 1094 1095 sc->iicbus = NULL; 1096 sc->intr_handle = NULL; 1097 reg_write(sc, IG4_REG_INTR_MASK, 0); 1098 set_controller(sc, 0); 1099 1100 sx_xunlock(&sc->call_lock); 1101 1102 mtx_destroy(&sc->io_lock); 1103 sx_destroy(&sc->call_lock); 1104 1105 return (0); 1106 } 1107 1108 int 1109 ig4iic_suspend(ig4iic_softc_t *sc) 1110 { 1111 int error; 1112 1113 /* suspend all children */ 1114 error = bus_generic_suspend(sc->dev); 1115 1116 sx_xlock(&sc->call_lock); 1117 set_controller(sc, 0); 1118 if (IG4_HAS_ADDREGS(sc->version)) { 1119 /* 1120 * Place the device in the idle state, just to be safe 1121 */ 1122 reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE); 1123 /* 1124 * Controller can become dysfunctional if I2C lines are pulled 1125 * down when suspend procedure turns off power to I2C device. 1126 * Place device in the reset state to avoid this. 1127 */ 1128 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); 1129 } 1130 sx_xunlock(&sc->call_lock); 1131 1132 return (error); 1133 } 1134 1135 int ig4iic_resume(ig4iic_softc_t *sc) 1136 { 1137 int error; 1138 1139 sx_xlock(&sc->call_lock); 1140 if (ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version))) 1141 device_printf(sc->dev, "controller error during resume\n"); 1142 sx_xunlock(&sc->call_lock); 1143 1144 error = bus_generic_resume(sc->dev); 1145 1146 return (error); 1147 } 1148 1149 /* 1150 * Interrupt Operation, see ig4_var.h for locking semantics. 1151 */ 1152 static int 1153 ig4iic_intr(void *cookie) 1154 { 1155 ig4iic_softc_t *sc = cookie; 1156 int retval = FILTER_STRAY; 1157 1158 mtx_lock_spin(&sc->io_lock); 1159 /* Ignore stray interrupts */ 1160 if (sc->intr_mask != 0 && reg_read(sc, IG4_REG_INTR_STAT) != 0) { 1161 /* Interrupt bits are cleared in wait_intr() loop */ 1162 ig4iic_set_intr_mask(sc, 0); 1163 wakeup(sc); 1164 retval = FILTER_HANDLED; 1165 } 1166 mtx_unlock_spin(&sc->io_lock); 1167 1168 return (retval); 1169 } 1170 1171 #define REGDUMP(sc, reg) \ 1172 device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg)) 1173 1174 static void 1175 ig4iic_dump(ig4iic_softc_t *sc) 1176 { 1177 device_printf(sc->dev, "ig4iic register dump:\n"); 1178 REGDUMP(sc, IG4_REG_CTL); 1179 REGDUMP(sc, IG4_REG_TAR_ADD); 1180 REGDUMP(sc, IG4_REG_SS_SCL_HCNT); 1181 REGDUMP(sc, IG4_REG_SS_SCL_LCNT); 1182 REGDUMP(sc, IG4_REG_FS_SCL_HCNT); 1183 REGDUMP(sc, IG4_REG_FS_SCL_LCNT); 1184 REGDUMP(sc, IG4_REG_INTR_STAT); 1185 REGDUMP(sc, IG4_REG_INTR_MASK); 1186 REGDUMP(sc, IG4_REG_RAW_INTR_STAT); 1187 REGDUMP(sc, IG4_REG_RX_TL); 1188 REGDUMP(sc, IG4_REG_TX_TL); 1189 REGDUMP(sc, IG4_REG_I2C_EN); 1190 REGDUMP(sc, IG4_REG_I2C_STA); 1191 REGDUMP(sc, IG4_REG_TXFLR); 1192 REGDUMP(sc, IG4_REG_RXFLR); 1193 REGDUMP(sc, IG4_REG_SDA_HOLD); 1194 REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE); 1195 REGDUMP(sc, IG4_REG_SLV_DATA_NACK); 1196 REGDUMP(sc, IG4_REG_DMA_CTRL); 1197 REGDUMP(sc, IG4_REG_DMA_TDLR); 1198 REGDUMP(sc, IG4_REG_DMA_RDLR); 1199 REGDUMP(sc, IG4_REG_SDA_SETUP); 1200 REGDUMP(sc, IG4_REG_ENABLE_STATUS); 1201 REGDUMP(sc, IG4_REG_COMP_PARAM1); 1202 REGDUMP(sc, IG4_REG_COMP_VER); 1203 if (sc->version == IG4_ATOM) { 1204 REGDUMP(sc, IG4_REG_COMP_TYPE); 1205 REGDUMP(sc, IG4_REG_CLK_PARMS); 1206 } 1207 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 1208 REGDUMP(sc, IG4_REG_RESETS_HSW); 1209 REGDUMP(sc, IG4_REG_GENERAL); 1210 } else if (sc->version == IG4_SKYLAKE) { 1211 REGDUMP(sc, IG4_REG_RESETS_SKL); 1212 } 1213 if (sc->version == IG4_HASWELL) { 1214 REGDUMP(sc, IG4_REG_SW_LTR_VALUE); 1215 REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE); 1216 } else if (IG4_HAS_ADDREGS(sc->version)) { 1217 REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE); 1218 REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE); 1219 } 1220 } 1221 #undef REGDUMP 1222 1223 DRIVER_MODULE(iicbus, ig4iic, iicbus_driver, NULL, NULL); 1224 #ifdef DEV_ACPI 1225 DRIVER_MODULE(acpi_iicbus, ig4iic, acpi_iicbus_driver, NULL, NULL); 1226 #endif 1227 MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); 1228 MODULE_VERSION(ig4iic, 1); 1229