1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2021, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IAVF_TYPE_H_ 33 #define _IAVF_TYPE_H_ 34 35 #include "iavf_status.h" 36 #include "iavf_osdep.h" 37 #include "iavf_register.h" 38 #include "iavf_adminq.h" 39 #include "iavf_devids.h" 40 41 #define IAVF_RXQ_CTX_DBUFF_SHIFT 7 42 43 #define BIT(a) (1UL << (a)) 44 #define BIT_ULL(a) (1ULL << (a)) 45 46 #ifndef IAVF_MASK 47 /* IAVF_MASK is a macro used on 32 bit registers */ 48 #define IAVF_MASK(mask, shift) (mask << shift) 49 #endif 50 51 #define IAVF_MAX_PF 16 52 #define IAVF_MAX_PF_VSI 64 53 #define IAVF_MAX_PF_QP 128 54 #define IAVF_MAX_VSI_QP 16 55 #define IAVF_MAX_VF_VSI 4 56 #define IAVF_MAX_CHAINED_RX_BUFFERS 5 57 58 /* something less than 1 minute */ 59 #define IAVF_HEARTBEAT_TIMEOUT (HZ * 50) 60 61 /* Check whether address is multicast. */ 62 #define IAVF_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01)) 63 64 /* Check whether an address is broadcast. */ 65 #define IAVF_IS_BROADCAST(address) \ 66 ((((u8 *)(address))[0] == ((u8)0xff)) && \ 67 (((u8 *)(address))[1] == ((u8)0xff))) 68 69 /* forward declaration */ 70 struct iavf_hw; 71 typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct iavf_aq_desc *); 72 73 #define ETH_ALEN 6 74 /* Data type manipulation macros. */ 75 #define IAVF_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 76 #define IAVF_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 77 78 #define IAVF_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 79 #define IAVF_LO_WORD(x) ((u16)((x) & 0xFFFF)) 80 81 #define IAVF_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) 82 #define IAVF_LO_BYTE(x) ((u8)((x) & 0xFF)) 83 84 /* Number of Transmit Descriptors must be a multiple of 8. */ 85 #define IAVF_REQ_TX_DESCRIPTOR_MULTIPLE 8 86 /* Number of Receive Descriptors must be a multiple of 32 if 87 * the number of descriptors is greater than 32. 88 */ 89 #define IAVF_REQ_RX_DESCRIPTOR_MULTIPLE 32 90 91 #define IAVF_DESC_UNUSED(R) \ 92 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 93 (R)->next_to_clean - (R)->next_to_use - 1) 94 95 /* bitfields for Tx queue mapping in QTX_CTL */ 96 #define IAVF_QTX_CTL_VF_QUEUE 0x0 97 #define IAVF_QTX_CTL_VM_QUEUE 0x1 98 #define IAVF_QTX_CTL_PF_QUEUE 0x2 99 100 /* debug masks - set these bits in hw->debug_mask to control output */ 101 enum iavf_debug_mask { 102 IAVF_DEBUG_INIT = 0x00000001, 103 IAVF_DEBUG_RELEASE = 0x00000002, 104 105 IAVF_DEBUG_LINK = 0x00000010, 106 IAVF_DEBUG_PHY = 0x00000020, 107 IAVF_DEBUG_HMC = 0x00000040, 108 IAVF_DEBUG_NVM = 0x00000080, 109 IAVF_DEBUG_LAN = 0x00000100, 110 IAVF_DEBUG_FLOW = 0x00000200, 111 IAVF_DEBUG_DCB = 0x00000400, 112 IAVF_DEBUG_DIAG = 0x00000800, 113 IAVF_DEBUG_FD = 0x00001000, 114 IAVF_DEBUG_PACKAGE = 0x00002000, 115 116 IAVF_DEBUG_IWARP = 0x00F00000, 117 118 IAVF_DEBUG_AQ_MESSAGE = 0x01000000, 119 IAVF_DEBUG_AQ_DESCRIPTOR = 0x02000000, 120 IAVF_DEBUG_AQ_DESC_BUFFER = 0x04000000, 121 IAVF_DEBUG_AQ_COMMAND = 0x06000000, 122 IAVF_DEBUG_AQ = 0x0F000000, 123 124 IAVF_DEBUG_USER = 0xF0000000, 125 126 IAVF_DEBUG_ALL = 0xFFFFFFFF 127 }; 128 129 /* PCI Bus Info */ 130 #define IAVF_PCI_LINK_STATUS 0xB2 131 #define IAVF_PCI_LINK_WIDTH 0x3F0 132 #define IAVF_PCI_LINK_WIDTH_1 0x10 133 #define IAVF_PCI_LINK_WIDTH_2 0x20 134 #define IAVF_PCI_LINK_WIDTH_4 0x40 135 #define IAVF_PCI_LINK_WIDTH_8 0x80 136 #define IAVF_PCI_LINK_SPEED 0xF 137 #define IAVF_PCI_LINK_SPEED_2500 0x1 138 #define IAVF_PCI_LINK_SPEED_5000 0x2 139 #define IAVF_PCI_LINK_SPEED_8000 0x3 140 141 #define IAVF_MDIO_CLAUSE22_STCODE_MASK IAVF_MASK(1, \ 142 IAVF_GLGEN_MSCA_STCODE_SHIFT) 143 #define IAVF_MDIO_CLAUSE22_OPCODE_WRITE_MASK IAVF_MASK(1, \ 144 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 145 #define IAVF_MDIO_CLAUSE22_OPCODE_READ_MASK IAVF_MASK(2, \ 146 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 147 148 #define IAVF_MDIO_CLAUSE45_STCODE_MASK IAVF_MASK(0, \ 149 IAVF_GLGEN_MSCA_STCODE_SHIFT) 150 #define IAVF_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK IAVF_MASK(0, \ 151 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 152 #define IAVF_MDIO_CLAUSE45_OPCODE_WRITE_MASK IAVF_MASK(1, \ 153 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 154 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK IAVF_MASK(2, \ 155 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 156 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_MASK IAVF_MASK(3, \ 157 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 158 159 #define IAVF_PHY_COM_REG_PAGE 0x1E 160 #define IAVF_PHY_LED_LINK_MODE_MASK 0xF0 161 #define IAVF_PHY_LED_MANUAL_ON 0x100 162 #define IAVF_PHY_LED_PROV_REG_1 0xC430 163 #define IAVF_PHY_LED_MODE_MASK 0xFFFF 164 #define IAVF_PHY_LED_MODE_ORIG 0x80000000 165 166 /* Memory types */ 167 enum iavf_memset_type { 168 IAVF_NONDMA_MEM = 0, 169 IAVF_DMA_MEM 170 }; 171 172 /* Memcpy types */ 173 enum iavf_memcpy_type { 174 IAVF_NONDMA_TO_NONDMA = 0, 175 IAVF_NONDMA_TO_DMA, 176 IAVF_DMA_TO_DMA, 177 IAVF_DMA_TO_NONDMA 178 }; 179 180 /* These are structs for managing the hardware information and the operations. 181 * The structures of function pointers are filled out at init time when we 182 * know for sure exactly which hardware we're working with. This gives us the 183 * flexibility of using the same main driver code but adapting to slightly 184 * different hardware needs as new parts are developed. For this architecture, 185 * the Firmware and AdminQ are intended to insulate the driver from most of the 186 * future changes, but these structures will also do part of the job. 187 */ 188 enum iavf_mac_type { 189 IAVF_MAC_UNKNOWN = 0, 190 IAVF_MAC_XL710, 191 IAVF_MAC_VF, 192 IAVF_MAC_X722, 193 IAVF_MAC_X722_VF, 194 IAVF_MAC_GENERIC, 195 }; 196 197 enum iavf_vsi_type { 198 IAVF_VSI_MAIN = 0, 199 IAVF_VSI_VMDQ1 = 1, 200 IAVF_VSI_VMDQ2 = 2, 201 IAVF_VSI_CTRL = 3, 202 IAVF_VSI_FCOE = 4, 203 IAVF_VSI_MIRROR = 5, 204 IAVF_VSI_SRIOV = 6, 205 IAVF_VSI_FDIR = 7, 206 IAVF_VSI_IWARP = 8, 207 IAVF_VSI_TYPE_UNKNOWN 208 }; 209 210 enum iavf_queue_type { 211 IAVF_QUEUE_TYPE_RX = 0, 212 IAVF_QUEUE_TYPE_TX, 213 IAVF_QUEUE_TYPE_PE_CEQ, 214 IAVF_QUEUE_TYPE_UNKNOWN 215 }; 216 217 #define IAVF_HW_CAP_MAX_GPIO 30 218 #define IAVF_HW_CAP_MDIO_PORT_MODE_MDIO 0 219 #define IAVF_HW_CAP_MDIO_PORT_MODE_I2C 1 220 221 enum iavf_acpi_programming_method { 222 IAVF_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, 223 IAVF_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 224 }; 225 226 #define IAVF_WOL_SUPPORT_MASK 0x1 227 #define IAVF_ACPI_PROGRAMMING_METHOD_MASK 0x2 228 #define IAVF_PROXY_SUPPORT_MASK 0x4 229 230 /* Capabilities of a PF or a VF or the whole device */ 231 struct iavf_hw_capabilities { 232 /* Cloud filter modes: 233 * Mode1: Filter on L4 port only 234 * Mode2: Filter for non-tunneled traffic 235 * Mode3: Filter for tunnel traffic 236 */ 237 #define IAVF_CLOUD_FILTER_MODE1 0x6 238 #define IAVF_CLOUD_FILTER_MODE2 0x7 239 #define IAVF_CLOUD_FILTER_MODE3 0x8 240 #define IAVF_SWITCH_MODE_MASK 0xF 241 242 bool dcb; 243 bool fcoe; 244 bool iwarp; 245 u32 num_vsis; 246 u32 num_rx_qp; 247 u32 num_tx_qp; 248 u32 base_queue; 249 u32 num_msix_vectors_vf; 250 bool apm_wol_support; 251 enum iavf_acpi_programming_method acpi_prog_method; 252 bool proxy_support; 253 }; 254 255 struct iavf_mac_info { 256 enum iavf_mac_type type; 257 u8 addr[ETH_ALEN]; 258 u8 perm_addr[ETH_ALEN]; 259 u8 san_addr[ETH_ALEN]; 260 u8 port_addr[ETH_ALEN]; 261 u16 max_fcoeq; 262 }; 263 264 #define IAVF_NVM_EXEC_GET_AQ_RESULT 0x0 265 #define IAVF_NVM_EXEC_FEATURES 0xe 266 #define IAVF_NVM_EXEC_STATUS 0xf 267 268 /* NVMUpdate features API */ 269 #define IAVF_NVMUPD_FEATURES_API_VER_MAJOR 0 270 #define IAVF_NVMUPD_FEATURES_API_VER_MINOR 14 271 #define IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN 12 272 273 #define IAVF_NVMUPD_FEATURE_FLAT_NVM_SUPPORT BIT(0) 274 275 struct iavf_nvmupd_features { 276 u8 major; 277 u8 minor; 278 u16 size; 279 u8 features[IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN]; 280 }; 281 282 #define IAVF_MODULE_SFF_DIAG_CAPAB 0x40 283 /* PCI bus types */ 284 enum iavf_bus_type { 285 iavf_bus_type_unknown = 0, 286 iavf_bus_type_pci, 287 iavf_bus_type_pcix, 288 iavf_bus_type_pci_express, 289 iavf_bus_type_reserved 290 }; 291 292 /* PCI bus speeds */ 293 enum iavf_bus_speed { 294 iavf_bus_speed_unknown = 0, 295 iavf_bus_speed_33 = 33, 296 iavf_bus_speed_66 = 66, 297 iavf_bus_speed_100 = 100, 298 iavf_bus_speed_120 = 120, 299 iavf_bus_speed_133 = 133, 300 iavf_bus_speed_2500 = 2500, 301 iavf_bus_speed_5000 = 5000, 302 iavf_bus_speed_8000 = 8000, 303 iavf_bus_speed_reserved 304 }; 305 306 /* PCI bus widths */ 307 enum iavf_bus_width { 308 iavf_bus_width_unknown = 0, 309 iavf_bus_width_pcie_x1 = 1, 310 iavf_bus_width_pcie_x2 = 2, 311 iavf_bus_width_pcie_x4 = 4, 312 iavf_bus_width_pcie_x8 = 8, 313 iavf_bus_width_32 = 32, 314 iavf_bus_width_64 = 64, 315 iavf_bus_width_reserved 316 }; 317 318 /* Bus parameters */ 319 struct iavf_bus_info { 320 enum iavf_bus_speed speed; 321 enum iavf_bus_width width; 322 enum iavf_bus_type type; 323 324 u16 func; 325 u16 device; 326 u16 lan_id; 327 u16 bus_id; 328 }; 329 330 #define IAVF_MAX_USER_PRIORITY 8 331 #define IAVF_TLV_STATUS_OPER 0x1 332 #define IAVF_TLV_STATUS_SYNC 0x2 333 #define IAVF_TLV_STATUS_ERR 0x4 334 #define IAVF_CEE_OPER_MAX_APPS 3 335 #define IAVF_APP_PROTOID_FCOE 0x8906 336 #define IAVF_APP_PROTOID_ISCSI 0x0cbc 337 #define IAVF_APP_PROTOID_FIP 0x8914 338 #define IAVF_APP_SEL_ETHTYPE 0x1 339 #define IAVF_APP_SEL_TCPIP 0x2 340 #define IAVF_CEE_APP_SEL_ETHTYPE 0x0 341 #define IAVF_CEE_APP_SEL_TCPIP 0x1 342 343 /* Port hardware description */ 344 struct iavf_hw { 345 u8 *hw_addr; 346 void *back; 347 348 /* subsystem structs */ 349 struct iavf_mac_info mac; 350 struct iavf_bus_info bus; 351 352 /* pci info */ 353 u16 device_id; 354 u16 vendor_id; 355 u16 subsystem_device_id; 356 u16 subsystem_vendor_id; 357 u8 revision_id; 358 359 /* capabilities for entire device and PCI func */ 360 struct iavf_hw_capabilities dev_caps; 361 362 /* Admin Queue info */ 363 struct iavf_adminq_info aq; 364 365 /* WoL and proxy support */ 366 u16 num_wol_proxy_filters; 367 u16 wol_proxy_vsi_seid; 368 369 #define IAVF_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0) 370 #define IAVF_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1) 371 #define IAVF_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2) 372 #define IAVF_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3) 373 #define IAVF_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4) 374 u64 flags; 375 376 /* NVMUpdate features */ 377 struct iavf_nvmupd_features nvmupd_features; 378 379 /* debug mask */ 380 u32 debug_mask; 381 char err_str[16]; 382 }; 383 384 struct iavf_driver_version { 385 u8 major_version; 386 u8 minor_version; 387 u8 build_version; 388 u8 subbuild_version; 389 u8 driver_string[32]; 390 }; 391 392 /* RX Descriptors */ 393 union iavf_16byte_rx_desc { 394 struct { 395 __le64 pkt_addr; /* Packet buffer address */ 396 __le64 hdr_addr; /* Header buffer address */ 397 } read; 398 struct { 399 struct { 400 struct { 401 union { 402 __le16 mirroring_status; 403 __le16 fcoe_ctx_id; 404 } mirr_fcoe; 405 __le16 l2tag1; 406 } lo_dword; 407 union { 408 __le32 rss; /* RSS Hash */ 409 __le32 fd_id; /* Flow director filter id */ 410 __le32 fcoe_param; /* FCoE DDP Context id */ 411 } hi_dword; 412 } qword0; 413 struct { 414 /* ext status/error/pktype/length */ 415 __le64 status_error_len; 416 } qword1; 417 } wb; /* writeback */ 418 }; 419 420 union iavf_32byte_rx_desc { 421 struct { 422 __le64 pkt_addr; /* Packet buffer address */ 423 __le64 hdr_addr; /* Header buffer address */ 424 /* bit 0 of hdr_buffer_addr is DD bit */ 425 __le64 rsvd1; 426 __le64 rsvd2; 427 } read; 428 struct { 429 struct { 430 struct { 431 union { 432 __le16 mirroring_status; 433 __le16 fcoe_ctx_id; 434 } mirr_fcoe; 435 __le16 l2tag1; 436 } lo_dword; 437 union { 438 __le32 rss; /* RSS Hash */ 439 __le32 fcoe_param; /* FCoE DDP Context id */ 440 /* Flow director filter id in case of 441 * Programming status desc WB 442 */ 443 __le32 fd_id; 444 } hi_dword; 445 } qword0; 446 struct { 447 /* status/error/pktype/length */ 448 __le64 status_error_len; 449 } qword1; 450 struct { 451 __le16 ext_status; /* extended status */ 452 __le16 rsvd; 453 __le16 l2tag2_1; 454 __le16 l2tag2_2; 455 } qword2; 456 struct { 457 union { 458 __le32 flex_bytes_lo; 459 __le32 pe_status; 460 } lo_dword; 461 union { 462 __le32 flex_bytes_hi; 463 __le32 fd_id; 464 } hi_dword; 465 } qword3; 466 } wb; /* writeback */ 467 }; 468 469 #define IAVF_RXD_QW0_MIRROR_STATUS_SHIFT 8 470 #define IAVF_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \ 471 IAVF_RXD_QW0_MIRROR_STATUS_SHIFT) 472 #define IAVF_RXD_QW0_FCOEINDX_SHIFT 0 473 #define IAVF_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \ 474 IAVF_RXD_QW0_FCOEINDX_SHIFT) 475 476 enum iavf_rx_desc_status_bits { 477 /* Note: These are predefined bit offsets */ 478 IAVF_RX_DESC_STATUS_DD_SHIFT = 0, 479 IAVF_RX_DESC_STATUS_EOF_SHIFT = 1, 480 IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, 481 IAVF_RX_DESC_STATUS_L3L4P_SHIFT = 3, 482 IAVF_RX_DESC_STATUS_CRCP_SHIFT = 4, 483 IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ 484 IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, 485 IAVF_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8, 486 487 IAVF_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ 488 IAVF_RX_DESC_STATUS_FLM_SHIFT = 11, 489 IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ 490 IAVF_RX_DESC_STATUS_LPBK_SHIFT = 14, 491 IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, 492 IAVF_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */ 493 IAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18, 494 IAVF_RX_DESC_STATUS_LAST /* this entry must be last!!! */ 495 }; 496 497 #define IAVF_RXD_QW1_STATUS_SHIFT 0 498 #define IAVF_RXD_QW1_STATUS_MASK ((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) \ 499 << IAVF_RXD_QW1_STATUS_SHIFT) 500 501 #define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT 502 #define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ 503 IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT) 504 505 #define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT 506 #define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT) 507 508 #define IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT IAVF_RX_DESC_STATUS_UMBCAST 509 #define IAVF_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \ 510 IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT) 511 512 enum iavf_rx_desc_fltstat_values { 513 IAVF_RX_DESC_FLTSTAT_NO_DATA = 0, 514 IAVF_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ 515 IAVF_RX_DESC_FLTSTAT_RSV = 2, 516 IAVF_RX_DESC_FLTSTAT_RSS_HASH = 3, 517 }; 518 519 #define IAVF_RXD_PACKET_TYPE_UNICAST 0 520 #define IAVF_RXD_PACKET_TYPE_MULTICAST 1 521 #define IAVF_RXD_PACKET_TYPE_BROADCAST 2 522 #define IAVF_RXD_PACKET_TYPE_MIRRORED 3 523 524 #define IAVF_RXD_QW1_ERROR_SHIFT 19 525 #define IAVF_RXD_QW1_ERROR_MASK (0xFFUL << IAVF_RXD_QW1_ERROR_SHIFT) 526 527 enum iavf_rx_desc_error_bits { 528 /* Note: These are predefined bit offsets */ 529 IAVF_RX_DESC_ERROR_RXE_SHIFT = 0, 530 IAVF_RX_DESC_ERROR_RECIPE_SHIFT = 1, 531 IAVF_RX_DESC_ERROR_HBO_SHIFT = 2, 532 IAVF_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ 533 IAVF_RX_DESC_ERROR_IPE_SHIFT = 3, 534 IAVF_RX_DESC_ERROR_L4E_SHIFT = 4, 535 IAVF_RX_DESC_ERROR_EIPE_SHIFT = 5, 536 IAVF_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, 537 IAVF_RX_DESC_ERROR_PPRS_SHIFT = 7 538 }; 539 540 enum iavf_rx_desc_error_l3l4e_fcoe_masks { 541 IAVF_RX_DESC_ERROR_L3L4E_NONE = 0, 542 IAVF_RX_DESC_ERROR_L3L4E_PROT = 1, 543 IAVF_RX_DESC_ERROR_L3L4E_FC = 2, 544 IAVF_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, 545 IAVF_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 546 }; 547 548 #define IAVF_RXD_QW1_PTYPE_SHIFT 30 549 #define IAVF_RXD_QW1_PTYPE_MASK (0xFFULL << IAVF_RXD_QW1_PTYPE_SHIFT) 550 551 /* Packet type non-ip values */ 552 enum iavf_rx_l2_ptype { 553 IAVF_RX_PTYPE_L2_RESERVED = 0, 554 IAVF_RX_PTYPE_L2_MAC_PAY2 = 1, 555 IAVF_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, 556 IAVF_RX_PTYPE_L2_FIP_PAY2 = 3, 557 IAVF_RX_PTYPE_L2_OUI_PAY2 = 4, 558 IAVF_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, 559 IAVF_RX_PTYPE_L2_LLDP_PAY2 = 6, 560 IAVF_RX_PTYPE_L2_ECP_PAY2 = 7, 561 IAVF_RX_PTYPE_L2_EVB_PAY2 = 8, 562 IAVF_RX_PTYPE_L2_QCN_PAY2 = 9, 563 IAVF_RX_PTYPE_L2_EAPOL_PAY2 = 10, 564 IAVF_RX_PTYPE_L2_ARP = 11, 565 IAVF_RX_PTYPE_L2_FCOE_PAY3 = 12, 566 IAVF_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, 567 IAVF_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, 568 IAVF_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, 569 IAVF_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, 570 IAVF_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, 571 IAVF_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, 572 IAVF_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, 573 IAVF_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, 574 IAVF_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, 575 IAVF_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, 576 IAVF_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, 577 IAVF_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, 578 IAVF_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153, 579 IAVF_RX_PTYPE_PARSER_ABORTED = 255 580 }; 581 582 struct iavf_rx_ptype_decoded { 583 u32 ptype:8; 584 u32 known:1; 585 u32 outer_ip:1; 586 u32 outer_ip_ver:1; 587 u32 outer_frag:1; 588 u32 tunnel_type:3; 589 u32 tunnel_end_prot:2; 590 u32 tunnel_end_frag:1; 591 u32 inner_prot:4; 592 u32 payload_layer:3; 593 }; 594 595 enum iavf_rx_ptype_outer_ip { 596 IAVF_RX_PTYPE_OUTER_L2 = 0, 597 IAVF_RX_PTYPE_OUTER_IP = 1 598 }; 599 600 enum iavf_rx_ptype_outer_ip_ver { 601 IAVF_RX_PTYPE_OUTER_NONE = 0, 602 IAVF_RX_PTYPE_OUTER_IPV4 = 0, 603 IAVF_RX_PTYPE_OUTER_IPV6 = 1 604 }; 605 606 enum iavf_rx_ptype_outer_fragmented { 607 IAVF_RX_PTYPE_NOT_FRAG = 0, 608 IAVF_RX_PTYPE_FRAG = 1 609 }; 610 611 enum iavf_rx_ptype_tunnel_type { 612 IAVF_RX_PTYPE_TUNNEL_NONE = 0, 613 IAVF_RX_PTYPE_TUNNEL_IP_IP = 1, 614 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 615 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 616 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 617 }; 618 619 enum iavf_rx_ptype_tunnel_end_prot { 620 IAVF_RX_PTYPE_TUNNEL_END_NONE = 0, 621 IAVF_RX_PTYPE_TUNNEL_END_IPV4 = 1, 622 IAVF_RX_PTYPE_TUNNEL_END_IPV6 = 2, 623 }; 624 625 enum iavf_rx_ptype_inner_prot { 626 IAVF_RX_PTYPE_INNER_PROT_NONE = 0, 627 IAVF_RX_PTYPE_INNER_PROT_UDP = 1, 628 IAVF_RX_PTYPE_INNER_PROT_TCP = 2, 629 IAVF_RX_PTYPE_INNER_PROT_SCTP = 3, 630 IAVF_RX_PTYPE_INNER_PROT_ICMP = 4, 631 IAVF_RX_PTYPE_INNER_PROT_TIMESYNC = 5 632 }; 633 634 enum iavf_rx_ptype_payload_layer { 635 IAVF_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 636 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 637 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 638 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 639 }; 640 641 #define IAVF_RX_PTYPE_BIT_MASK 0x0FFFFFFF 642 #define IAVF_RX_PTYPE_SHIFT 56 643 644 #define IAVF_RXD_QW1_LENGTH_PBUF_SHIFT 38 645 #define IAVF_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 646 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) 647 648 #define IAVF_RXD_QW1_LENGTH_HBUF_SHIFT 52 649 #define IAVF_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ 650 IAVF_RXD_QW1_LENGTH_HBUF_SHIFT) 651 652 #define IAVF_RXD_QW1_LENGTH_SPH_SHIFT 63 653 #define IAVF_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT) 654 655 #define IAVF_RXD_QW1_NEXTP_SHIFT 38 656 #define IAVF_RXD_QW1_NEXTP_MASK (0x1FFFULL << IAVF_RXD_QW1_NEXTP_SHIFT) 657 658 #define IAVF_RXD_QW2_EXT_STATUS_SHIFT 0 659 #define IAVF_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \ 660 IAVF_RXD_QW2_EXT_STATUS_SHIFT) 661 662 enum iavf_rx_desc_ext_status_bits { 663 /* Note: These are predefined bit offsets */ 664 IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, 665 IAVF_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, 666 IAVF_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ 667 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ 668 IAVF_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, 669 IAVF_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, 670 IAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, 671 }; 672 673 #define IAVF_RXD_QW2_L2TAG2_SHIFT 0 674 #define IAVF_RXD_QW2_L2TAG2_MASK (0xFFFFUL << IAVF_RXD_QW2_L2TAG2_SHIFT) 675 676 #define IAVF_RXD_QW2_L2TAG3_SHIFT 16 677 #define IAVF_RXD_QW2_L2TAG3_MASK (0xFFFFUL << IAVF_RXD_QW2_L2TAG3_SHIFT) 678 679 enum iavf_rx_desc_pe_status_bits { 680 /* Note: These are predefined bit offsets */ 681 IAVF_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ 682 IAVF_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ 683 IAVF_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ 684 IAVF_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, 685 IAVF_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, 686 IAVF_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, 687 IAVF_RX_DESC_PE_STATUS_URG_SHIFT = 27, 688 IAVF_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, 689 IAVF_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 690 }; 691 692 #define IAVF_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 693 #define IAVF_RX_PROG_STATUS_DESC_LENGTH 0x2000000 694 695 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 696 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ 697 IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) 698 699 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0 700 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \ 701 IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT) 702 703 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 704 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ 705 IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) 706 707 enum iavf_rx_prog_status_desc_status_bits { 708 /* Note: These are predefined bit offsets */ 709 IAVF_RX_PROG_STATUS_DESC_DD_SHIFT = 0, 710 IAVF_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ 711 }; 712 713 enum iavf_rx_prog_status_desc_prog_id_masks { 714 IAVF_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, 715 IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, 716 IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, 717 }; 718 719 enum iavf_rx_prog_status_desc_error_bits { 720 /* Note: These are predefined bit offsets */ 721 IAVF_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, 722 IAVF_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, 723 IAVF_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, 724 IAVF_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 725 }; 726 727 #define IAVF_TWO_BIT_MASK 0x3 728 #define IAVF_THREE_BIT_MASK 0x7 729 #define IAVF_FOUR_BIT_MASK 0xF 730 #define IAVF_EIGHTEEN_BIT_MASK 0x3FFFF 731 732 /* TX Descriptor */ 733 struct iavf_tx_desc { 734 __le64 buffer_addr; /* Address of descriptor's data buf */ 735 __le64 cmd_type_offset_bsz; 736 }; 737 738 #define IAVF_TXD_QW1_DTYPE_SHIFT 0 739 #define IAVF_TXD_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT) 740 741 enum iavf_tx_desc_dtype_value { 742 IAVF_TX_DESC_DTYPE_DATA = 0x0, 743 IAVF_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ 744 IAVF_TX_DESC_DTYPE_CONTEXT = 0x1, 745 IAVF_TX_DESC_DTYPE_FCOE_CTX = 0x2, 746 IAVF_TX_DESC_DTYPE_FILTER_PROG = 0x8, 747 IAVF_TX_DESC_DTYPE_DDP_CTX = 0x9, 748 IAVF_TX_DESC_DTYPE_FLEX_DATA = 0xB, 749 IAVF_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, 750 IAVF_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, 751 IAVF_TX_DESC_DTYPE_DESC_DONE = 0xF 752 }; 753 754 #define IAVF_TXD_QW1_CMD_SHIFT 4 755 #define IAVF_TXD_QW1_CMD_MASK (0x3FFUL << IAVF_TXD_QW1_CMD_SHIFT) 756 757 enum iavf_tx_desc_cmd_bits { 758 IAVF_TX_DESC_CMD_EOP = 0x0001, 759 IAVF_TX_DESC_CMD_RS = 0x0002, 760 IAVF_TX_DESC_CMD_ICRC = 0x0004, 761 IAVF_TX_DESC_CMD_IL2TAG1 = 0x0008, 762 IAVF_TX_DESC_CMD_DUMMY = 0x0010, 763 IAVF_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 764 IAVF_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 765 IAVF_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 766 IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 767 IAVF_TX_DESC_CMD_FCOET = 0x0080, 768 IAVF_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 769 IAVF_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 770 IAVF_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 771 IAVF_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 772 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ 773 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ 774 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ 775 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ 776 }; 777 778 #define IAVF_TXD_QW1_OFFSET_SHIFT 16 779 #define IAVF_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ 780 IAVF_TXD_QW1_OFFSET_SHIFT) 781 782 enum iavf_tx_desc_length_fields { 783 /* Note: These are predefined bit offsets */ 784 IAVF_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ 785 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ 786 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ 787 }; 788 789 #define IAVF_TXD_QW1_MACLEN_MASK (0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT) 790 #define IAVF_TXD_QW1_IPLEN_MASK (0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT) 791 #define IAVF_TXD_QW1_L4LEN_MASK (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 792 #define IAVF_TXD_QW1_FCLEN_MASK (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 793 794 #define IAVF_TXD_QW1_TX_BUF_SZ_SHIFT 34 795 #define IAVF_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ 796 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) 797 798 #define IAVF_TXD_QW1_L2TAG1_SHIFT 48 799 #define IAVF_TXD_QW1_L2TAG1_MASK (0xFFFFULL << IAVF_TXD_QW1_L2TAG1_SHIFT) 800 801 /* Context descriptors */ 802 struct iavf_tx_context_desc { 803 __le32 tunneling_params; 804 __le16 l2tag2; 805 __le16 rsvd; 806 __le64 type_cmd_tso_mss; 807 }; 808 809 #define IAVF_TXD_CTX_QW1_DTYPE_SHIFT 0 810 #define IAVF_TXD_CTX_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_CTX_QW1_DTYPE_SHIFT) 811 812 #define IAVF_TXD_CTX_QW1_CMD_SHIFT 4 813 #define IAVF_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << IAVF_TXD_CTX_QW1_CMD_SHIFT) 814 815 enum iavf_tx_ctx_desc_cmd_bits { 816 IAVF_TX_CTX_DESC_TSO = 0x01, 817 IAVF_TX_CTX_DESC_TSYN = 0x02, 818 IAVF_TX_CTX_DESC_IL2TAG2 = 0x04, 819 IAVF_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 820 IAVF_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 821 IAVF_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 822 IAVF_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 823 IAVF_TX_CTX_DESC_SWTCH_VSI = 0x30, 824 IAVF_TX_CTX_DESC_SWPE = 0x40 825 }; 826 827 struct iavf_nop_desc { 828 __le64 rsvd; 829 __le64 dtype_cmd; 830 }; 831 832 #define IAVF_TXD_NOP_QW1_DTYPE_SHIFT 0 833 #define IAVF_TXD_NOP_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_NOP_QW1_DTYPE_SHIFT) 834 835 #define IAVF_TXD_NOP_QW1_CMD_SHIFT 4 836 #define IAVF_TXD_NOP_QW1_CMD_MASK (0x7FUL << IAVF_TXD_NOP_QW1_CMD_SHIFT) 837 838 enum iavf_tx_nop_desc_cmd_bits { 839 /* Note: These are predefined bit offsets */ 840 IAVF_TX_NOP_DESC_EOP_SHIFT = 0, 841 IAVF_TX_NOP_DESC_RS_SHIFT = 1, 842 IAVF_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */ 843 }; 844 845 /* Packet Classifier Types for filters */ 846 enum iavf_filter_pctype { 847 /* Note: Values 0-28 are reserved for future use. 848 * Value 29, 30, 32 are not supported on XL710 and X710. 849 */ 850 IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, 851 IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, 852 IAVF_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 853 IAVF_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, 854 IAVF_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 855 IAVF_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 856 IAVF_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 857 IAVF_FILTER_PCTYPE_FRAG_IPV4 = 36, 858 /* Note: Values 37-38 are reserved for future use. 859 * Value 39, 40, 42 are not supported on XL710 and X710. 860 */ 861 IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, 862 IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, 863 IAVF_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 864 IAVF_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, 865 IAVF_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 866 IAVF_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 867 IAVF_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 868 IAVF_FILTER_PCTYPE_FRAG_IPV6 = 46, 869 /* Note: Value 47 is reserved for future use */ 870 IAVF_FILTER_PCTYPE_FCOE_OX = 48, 871 IAVF_FILTER_PCTYPE_FCOE_RX = 49, 872 IAVF_FILTER_PCTYPE_FCOE_OTHER = 50, 873 /* Note: Values 51-62 are reserved for future use */ 874 IAVF_FILTER_PCTYPE_L2_PAYLOAD = 63, 875 }; 876 877 #define IAVF_TXD_FLTR_QW1_DTYPE_SHIFT 0 878 #define IAVF_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_FLTR_QW1_DTYPE_SHIFT) 879 880 #define IAVF_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \ 881 IAVF_TXD_FLTR_QW1_CMD_SHIFT) 882 #define IAVF_TXD_FLTR_QW1_ATR_MASK BIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT) 883 884 885 #define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT 30 886 #define IAVF_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ 887 IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) 888 889 #define IAVF_TXD_CTX_QW1_MSS_SHIFT 50 890 #define IAVF_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ 891 IAVF_TXD_CTX_QW1_MSS_SHIFT) 892 893 #define IAVF_TXD_CTX_QW1_VSI_SHIFT 50 894 #define IAVF_TXD_CTX_QW1_VSI_MASK (0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT) 895 896 #define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT 0 897 #define IAVF_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ 898 IAVF_TXD_CTX_QW0_EXT_IP_SHIFT) 899 900 enum iavf_tx_ctx_desc_eipt_offload { 901 IAVF_TX_CTX_EXT_IP_NONE = 0x0, 902 IAVF_TX_CTX_EXT_IP_IPV6 = 0x1, 903 IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, 904 IAVF_TX_CTX_EXT_IP_IPV4 = 0x3 905 }; 906 907 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 908 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ 909 IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT) 910 911 #define IAVF_TXD_CTX_QW0_NATT_SHIFT 9 912 #define IAVF_TXD_CTX_QW0_NATT_MASK (0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT) 913 914 #define IAVF_TXD_CTX_UDP_TUNNELING BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT) 915 #define IAVF_TXD_CTX_GRE_TUNNELING (0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT) 916 917 #define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 918 #define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK \ 919 BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT) 920 921 #define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST IAVF_TXD_CTX_QW0_EIP_NOINC_MASK 922 923 #define IAVF_TXD_CTX_QW0_NATLEN_SHIFT 12 924 #define IAVF_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ 925 IAVF_TXD_CTX_QW0_NATLEN_SHIFT) 926 927 #define IAVF_TXD_CTX_QW0_DECTTL_SHIFT 19 928 #define IAVF_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ 929 IAVF_TXD_CTX_QW0_DECTTL_SHIFT) 930 931 #define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT 23 932 #define IAVF_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT) 933 934 /* Statistics collected by each port, VSI, VEB, and S-channel */ 935 struct iavf_eth_stats { 936 u64 rx_bytes; /* gorc */ 937 u64 rx_unicast; /* uprc */ 938 u64 rx_multicast; /* mprc */ 939 u64 rx_broadcast; /* bprc */ 940 u64 rx_discards; /* rdpc */ 941 u64 rx_unknown_protocol; /* rupp */ 942 u64 tx_bytes; /* gotc */ 943 u64 tx_unicast; /* uptc */ 944 u64 tx_multicast; /* mptc */ 945 u64 tx_broadcast; /* bptc */ 946 u64 tx_discards; /* tdpc */ 947 u64 tx_errors; /* tepc */ 948 }; 949 #define IAVF_SR_PCIE_ANALOG_CONFIG_PTR 0x03 950 #define IAVF_SR_PHY_ANALOG_CONFIG_PTR 0x04 951 #define IAVF_SR_OPTION_ROM_PTR 0x05 952 #define IAVF_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 953 #define IAVF_SR_AUTO_GENERATED_POINTERS_PTR 0x07 954 #define IAVF_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 955 #define IAVF_SR_EMP_GLOBAL_MODULE_PTR 0x09 956 #define IAVF_SR_RO_PCIE_LCB_PTR 0x0A 957 #define IAVF_SR_EMP_IMAGE_PTR 0x0B 958 #define IAVF_SR_PE_IMAGE_PTR 0x0C 959 #define IAVF_SR_CSR_PROTECTED_LIST_PTR 0x0D 960 #define IAVF_SR_MNG_CONFIG_PTR 0x0E 961 #define IAVF_SR_PBA_FLAGS 0x15 962 #define IAVF_SR_PBA_BLOCK_PTR 0x16 963 #define IAVF_SR_BOOT_CONFIG_PTR 0x17 964 #define IAVF_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28 965 #define IAVF_SR_NVM_MAP_VERSION 0x29 966 #define IAVF_SR_NVM_IMAGE_VERSION 0x2A 967 #define IAVF_SR_NVM_STRUCTURE_VERSION 0x2B 968 #define IAVF_SR_PXE_SETUP_PTR 0x30 969 #define IAVF_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31 970 #define IAVF_SR_NVM_ORIGINAL_EETRACK_LO 0x34 971 #define IAVF_SR_NVM_ORIGINAL_EETRACK_HI 0x35 972 #define IAVF_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37 973 #define IAVF_SR_POR_REGS_AUTO_LOAD_PTR 0x38 974 #define IAVF_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 975 #define IAVF_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 976 #define IAVF_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 977 #define IAVF_SR_PHY_ACTIVITY_LIST_PTR 0x3D 978 #define IAVF_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 979 #define IAVF_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 980 #define IAVF_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 981 #define IAVF_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 982 #define IAVF_SR_EMP_SR_SETTINGS_PTR 0x48 983 #define IAVF_SR_FEATURE_CONFIGURATION_PTR 0x49 984 #define IAVF_SR_CONFIGURATION_METADATA_PTR 0x4D 985 #define IAVF_SR_IMMEDIATE_VALUES_PTR 0x4E 986 #define IAVF_SR_OCP_CFG_WORD0 0x2B 987 #define IAVF_SR_OCP_ENABLED BIT(15) 988 #define IAVF_SR_BUF_ALIGNMENT 4096 989 990 struct iavf_lldp_variables { 991 u16 length; 992 u16 adminstatus; 993 u16 msgfasttx; 994 u16 msgtxinterval; 995 u16 txparams; 996 u16 timers; 997 u16 crc8; 998 }; 999 1000 /* Offsets into Alternate Ram */ 1001 #define IAVF_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */ 1002 #define IAVF_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */ 1003 #define IAVF_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */ 1004 #define IAVF_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */ 1005 #define IAVF_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */ 1006 #define IAVF_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */ 1007 1008 /* Alternate Ram Bandwidth Masks */ 1009 #define IAVF_ALT_BW_VALUE_MASK 0xFF 1010 #define IAVF_ALT_BW_RELATIVE_MASK 0x40000000 1011 #define IAVF_ALT_BW_VALID_MASK 0x80000000 1012 1013 #define IAVF_DDP_TRACKID_RDONLY 0 1014 #define IAVF_DDP_TRACKID_INVALID 0xFFFFFFFF 1015 #define SECTION_TYPE_RB_MMIO 0x00001800 1016 #define SECTION_TYPE_RB_AQ 0x00001801 1017 #define SECTION_TYPE_PROTO 0x80000002 1018 #define SECTION_TYPE_PCTYPE 0x80000003 1019 #define SECTION_TYPE_PTYPE 0x80000004 1020 struct iavf_profile_tlv_section_record { 1021 u8 rtype; 1022 u8 type; 1023 u16 len; 1024 u8 data[12]; 1025 }; 1026 1027 /* Generic AQ section in proflie */ 1028 struct iavf_profile_aq_section { 1029 u16 opcode; 1030 u16 flags; 1031 u8 param[16]; 1032 u16 datalen; 1033 u8 data[1]; 1034 }; 1035 1036 #endif /* _IAVF_TYPE_H_ */ 1037