1 /*- 2 * Copyright (c) 2005 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _DEV_HWPMC_PMC_EVENTS_H_ 30 #define _DEV_HWPMC_PMC_EVENTS_H_ 31 32 /* 33 * PMC event codes. 34 * 35 * __PMC_EV(CLASS, SYMBOLIC-NAME, VALUE, READABLE-NAME) 36 * 37 */ 38 39 /* 40 * AMD K7 Events, from "The AMD Athlon(tm) Processor x86 Code 41 * Optimization Guide" [Doc#22007K, Feb 2002] 42 */ 43 44 #define __PMC_EV_K7() \ 45 __PMC_EV(K7, DC_ACCESSES) \ 46 __PMC_EV(K7, DC_MISSES) \ 47 __PMC_EV(K7, DC_REFILLS_FROM_L2) \ 48 __PMC_EV(K7, DC_REFILLS_FROM_SYSTEM) \ 49 __PMC_EV(K7, DC_WRITEBACKS) \ 50 __PMC_EV(K7, L1_DTLB_MISS_AND_L2_DTLB_HITS) \ 51 __PMC_EV(K7, L1_AND_L2_DTLB_MISSES) \ 52 __PMC_EV(K7, MISALIGNED_REFERENCES) \ 53 __PMC_EV(K7, IC_FETCHES) \ 54 __PMC_EV(K7, IC_MISSES) \ 55 __PMC_EV(K7, L1_ITLB_MISSES) \ 56 __PMC_EV(K7, L1_L2_ITLB_MISSES) \ 57 __PMC_EV(K7, RETIRED_INSTRUCTIONS) \ 58 __PMC_EV(K7, RETIRED_OPS) \ 59 __PMC_EV(K7, RETIRED_BRANCHES) \ 60 __PMC_EV(K7, RETIRED_BRANCHES_MISPREDICTED) \ 61 __PMC_EV(K7, RETIRED_TAKEN_BRANCHES) \ 62 __PMC_EV(K7, RETIRED_TAKEN_BRANCHES_MISPREDICTED) \ 63 __PMC_EV(K7, RETIRED_FAR_CONTROL_TRANSFERS) \ 64 __PMC_EV(K7, RETIRED_RESYNC_BRANCHES) \ 65 __PMC_EV(K7, INTERRUPTS_MASKED_CYCLES) \ 66 __PMC_EV(K7, INTERRUPTS_MASKED_WHILE_PENDING_CYCLES) \ 67 __PMC_EV(K7, HARDWARE_INTERRUPTS) 68 69 #define PMC_EV_K7_FIRST PMC_EV_K7_DC_ACCESSES 70 #define PMC_EV_K7_LAST PMC_EV_K7_HARDWARE_INTERRUPTS 71 72 /* 73 * Intel P4 Events, from "IA-32 Intel(r) Architecture Software 74 * Developer's Manual, Volume 3: System Programming Guide" [245472-012] 75 */ 76 77 #define __PMC_EV_P4() \ 78 __PMC_EV(P4, TC_DELIVER_MODE) \ 79 __PMC_EV(P4, BPU_FETCH_REQUEST) \ 80 __PMC_EV(P4, ITLB_REFERENCE) \ 81 __PMC_EV(P4, MEMORY_CANCEL) \ 82 __PMC_EV(P4, MEMORY_COMPLETE) \ 83 __PMC_EV(P4, LOAD_PORT_REPLAY) \ 84 __PMC_EV(P4, STORE_PORT_REPLAY) \ 85 __PMC_EV(P4, MOB_LOAD_REPLAY) \ 86 __PMC_EV(P4, PAGE_WALK_TYPE) \ 87 __PMC_EV(P4, BSQ_CACHE_REFERENCE) \ 88 __PMC_EV(P4, IOQ_ALLOCATION) \ 89 __PMC_EV(P4, IOQ_ACTIVE_ENTRIES) \ 90 __PMC_EV(P4, FSB_DATA_ACTIVITY) \ 91 __PMC_EV(P4, BSQ_ALLOCATION) \ 92 __PMC_EV(P4, BSQ_ACTIVE_ENTRIES) \ 93 __PMC_EV(P4, SSE_INPUT_ASSIST) \ 94 __PMC_EV(P4, PACKED_SP_UOP) \ 95 __PMC_EV(P4, PACKED_DP_UOP) \ 96 __PMC_EV(P4, SCALAR_SP_UOP) \ 97 __PMC_EV(P4, SCALAR_DP_UOP) \ 98 __PMC_EV(P4, 64BIT_MMX_UOP) \ 99 __PMC_EV(P4, 128BIT_MMX_UOP) \ 100 __PMC_EV(P4, X87_FP_UOP) \ 101 __PMC_EV(P4, X87_SIMD_MOVES_UOP) \ 102 __PMC_EV(P4, GLOBAL_POWER_EVENTS) \ 103 __PMC_EV(P4, TC_MS_XFER) \ 104 __PMC_EV(P4, UOP_QUEUE_WRITES) \ 105 __PMC_EV(P4, RETIRED_MISPRED_BRANCH_TYPE) \ 106 __PMC_EV(P4, RETIRED_BRANCH_TYPE) \ 107 __PMC_EV(P4, RESOURCE_STALL) \ 108 __PMC_EV(P4, WC_BUFFER) \ 109 __PMC_EV(P4, B2B_CYCLES) \ 110 __PMC_EV(P4, BNR) \ 111 __PMC_EV(P4, SNOOP) \ 112 __PMC_EV(P4, RESPONSE) \ 113 __PMC_EV(P4, FRONT_END_EVENT) \ 114 __PMC_EV(P4, EXECUTION_EVENT) \ 115 __PMC_EV(P4, REPLAY_EVENT) \ 116 __PMC_EV(P4, INSTR_RETIRED) \ 117 __PMC_EV(P4, UOPS_RETIRED) \ 118 __PMC_EV(P4, UOP_TYPE) \ 119 __PMC_EV(P4, BRANCH_RETIRED) \ 120 __PMC_EV(P4, MISPRED_BRANCH_RETIRED) \ 121 __PMC_EV(P4, X87_ASSIST) \ 122 __PMC_EV(P4, MACHINE_CLEAR) 123 124 #define PMC_EV_P4_FIRST PMC_EV_P4_TC_DELIVER_MODE 125 #define PMC_EV_P4_LAST PMC_EV_P4_MACHINE_CLEAR 126 127 /* Intel Pentium Pro, P-II, P-III and Pentium-M style events */ 128 129 #define __PMC_EV_P6() \ 130 __PMC_EV(P6, DATA_MEM_REFS) \ 131 __PMC_EV(P6, DCU_LINES_IN) \ 132 __PMC_EV(P6, DCU_M_LINES_IN) \ 133 __PMC_EV(P6, DCU_M_LINES_OUT) \ 134 __PMC_EV(P6, DCU_MISS_OUTSTANDING) \ 135 __PMC_EV(P6, IFU_FETCH) \ 136 __PMC_EV(P6, IFU_FETCH_MISS) \ 137 __PMC_EV(P6, ITLB_MISS) \ 138 __PMC_EV(P6, IFU_MEM_STALL) \ 139 __PMC_EV(P6, ILD_STALL) \ 140 __PMC_EV(P6, L2_IFETCH) \ 141 __PMC_EV(P6, L2_LD) \ 142 __PMC_EV(P6, L2_ST) \ 143 __PMC_EV(P6, L2_LINES_IN) \ 144 __PMC_EV(P6, L2_LINES_OUT) \ 145 __PMC_EV(P6, L2_M_LINES_INM) \ 146 __PMC_EV(P6, L2_M_LINES_OUTM) \ 147 __PMC_EV(P6, L2_RQSTS) \ 148 __PMC_EV(P6, L2_ADS) \ 149 __PMC_EV(P6, L2_DBUS_BUSY) \ 150 __PMC_EV(P6, L2_DBUS_BUSY_RD) \ 151 __PMC_EV(P6, BUS_DRDY_CLOCKS) \ 152 __PMC_EV(P6, BUS_LOCK_CLOCKS) \ 153 __PMC_EV(P6, BUS_REQ_OUTSTANDING) \ 154 __PMC_EV(P6, BUS_TRAN_BRD) \ 155 __PMC_EV(P6, BUS_TRAN_RFO) \ 156 __PMC_EV(P6, BUS_TRANS_WB) \ 157 __PMC_EV(P6, BUS_TRAN_IFETCH) \ 158 __PMC_EV(P6, BUS_TRAN_INVAL) \ 159 __PMC_EV(P6, BUS_TRAN_PWR) \ 160 __PMC_EV(P6, BUS_TRANS_P) \ 161 __PMC_EV(P6, BUS_TRANS_IO) \ 162 __PMC_EV(P6, BUS_TRAN_DEF) \ 163 __PMC_EV(P6, BUS_TRAN_BURST) \ 164 __PMC_EV(P6, BUS_TRAN_ANY) \ 165 __PMC_EV(P6, BUS_TRAN_MEM) \ 166 __PMC_EV(P6, BUS_DATA_RCV) \ 167 __PMC_EV(P6, BUS_BNR_DRV) \ 168 __PMC_EV(P6, BUS_HIT_DRV) \ 169 __PMC_EV(P6, BUS_HITM_DRV) \ 170 __PMC_EV(P6, BUS_SNOOP_STALL) \ 171 __PMC_EV(P6, FLOPS) \ 172 __PMC_EV(P6, FP_COMPS_OPS_EXE) \ 173 __PMC_EV(P6, FP_ASSIST) \ 174 __PMC_EV(P6, MUL) \ 175 __PMC_EV(P6, DIV) \ 176 __PMC_EV(P6, CYCLES_DIV_BUSY) \ 177 __PMC_EV(P6, LD_BLOCKS) \ 178 __PMC_EV(P6, SB_DRAINS) \ 179 __PMC_EV(P6, MISALIGN_MEM_REF) \ 180 __PMC_EV(P6, EMON_KNI_PREF_DISPATCHED) \ 181 __PMC_EV(P6, EMON_KNI_PREF_MISS) \ 182 __PMC_EV(P6, INST_RETIRED) \ 183 __PMC_EV(P6, UOPS_RETIRED) \ 184 __PMC_EV(P6, INST_DECODED) \ 185 __PMC_EV(P6, EMON_KNI_INST_RETIRED) \ 186 __PMC_EV(P6, EMON_KNI_COMP_INST_RET) \ 187 __PMC_EV(P6, HW_INT_RX) \ 188 __PMC_EV(P6, CYCLES_INT_MASKED) \ 189 __PMC_EV(P6, CYCLES_INT_PENDING_AND_MASKED) \ 190 __PMC_EV(P6, BR_INST_RETIRED) \ 191 __PMC_EV(P6, BR_MISS_PRED_RETIRED) \ 192 __PMC_EV(P6, BR_TAKEN_RETIRED) \ 193 __PMC_EV(P6, BR_MISS_PRED_TAKEN_RET) \ 194 __PMC_EV(P6, BR_INST_DECODED) \ 195 __PMC_EV(P6, BTB_MISSES) \ 196 __PMC_EV(P6, BR_BOGUS) \ 197 __PMC_EV(P6, BACLEARS) \ 198 __PMC_EV(P6, RESOURCE_STALLS) \ 199 __PMC_EV(P6, PARTIAL_RAT_STALLS) \ 200 __PMC_EV(P6, SEGMENT_REG_LOADS) \ 201 __PMC_EV(P6, CPU_CLK_UNHALTED) \ 202 __PMC_EV(P6, MMX_INSTR_EXEC) \ 203 __PMC_EV(P6, MMX_SAT_INSTR_EXEC) \ 204 __PMC_EV(P6, MMX_UOPS_EXEC) \ 205 __PMC_EV(P6, MMX_INSTR_TYPE_EXEC) \ 206 __PMC_EV(P6, FP_MMX_TRANS) \ 207 __PMC_EV(P6, MMX_ASSIST) \ 208 __PMC_EV(P6, MMX_INSTR_RET) \ 209 __PMC_EV(P6, SEG_RENAME_STALLS) \ 210 __PMC_EV(P6, SEG_REG_RENAMES) \ 211 __PMC_EV(P6, RET_SEG_RENAMES) \ 212 __PMC_EV(P6, EMON_EST_TRANS) \ 213 __PMC_EV(P6, EMON_THERMAL_TRIP) \ 214 __PMC_EV(P6, BR_INST_EXEC) \ 215 __PMC_EV(P6, BR_MISSP_EXEC) \ 216 __PMC_EV(P6, BR_BAC_MISSP_EXEC) \ 217 __PMC_EV(P6, BR_CND_EXEC) \ 218 __PMC_EV(P6, BR_CND_MISSP_EXEC) \ 219 __PMC_EV(P6, BR_IND_EXEC) \ 220 __PMC_EV(P6, BR_IND_MISSP_EXEC) \ 221 __PMC_EV(P6, BR_RET_EXEC) \ 222 __PMC_EV(P6, BR_RET_MISSP_EXEC) \ 223 __PMC_EV(P6, BR_RET_BAC_MISSP_EXEC) \ 224 __PMC_EV(P6, BR_CALL_EXEC) \ 225 __PMC_EV(P6, BR_CALL_MISSP_EXEC) \ 226 __PMC_EV(P6, BR_IND_CALL_EXEC) \ 227 __PMC_EV(P6, EMON_SIMD_INSTR_RETIRED) \ 228 __PMC_EV(P6, EMON_SYNCH_UOPS) \ 229 __PMC_EV(P6, EMON_ESP_UOPS) \ 230 __PMC_EV(P6, EMON_FUSED_UOPS_RET) \ 231 __PMC_EV(P6, EMON_UNFUSION) \ 232 __PMC_EV(P6, EMON_PREF_RQSTS_UP) \ 233 __PMC_EV(P6, EMON_PREF_RQSTS_DN) \ 234 __PMC_EV(P6, EMON_SSE_SSE2_INST_RETIRED) \ 235 __PMC_EV(P6, EMON_SSE_SSE2_COMP_INST_RETIRED) 236 237 238 #define PMC_EV_P6_FIRST PMC_EV_P6_DATA_MEM_REFS 239 #define PMC_EV_P6_LAST PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED 240 241 /* AMD K8 PMCs */ 242 243 #define __PMC_EV_K8() \ 244 __PMC_EV(K8, FP_DISPATCHED_FPU_OPS) \ 245 __PMC_EV(K8, FP_CYCLES_WITH_NO_FPU_OPS_RETIRED) \ 246 __PMC_EV(K8, FP_DISPATCHED_FPU_FAST_FLAG_OPS) \ 247 __PMC_EV(K8, LS_SEGMENT_REGISTER_LOAD) \ 248 __PMC_EV(K8, LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE) \ 249 __PMC_EV(K8, LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP) \ 250 __PMC_EV(K8, LS_BUFFER2_FULL) \ 251 __PMC_EV(K8, LS_LOCKED_OPERATION) \ 252 __PMC_EV(K8, LS_MICROARCHITECTURAL_LATE_CANCEL) \ 253 __PMC_EV(K8, LS_RETIRED_CFLUSH_INSTRUCTIONS) \ 254 __PMC_EV(K8, LS_RETIRED_CPUID_INSTRUCTIONS) \ 255 __PMC_EV(K8, DC_ACCESS) \ 256 __PMC_EV(K8, DC_MISS) \ 257 __PMC_EV(K8, DC_REFILL_FROM_L2) \ 258 __PMC_EV(K8, DC_REFILL_FROM_SYSTEM) \ 259 __PMC_EV(K8, DC_COPYBACK) \ 260 __PMC_EV(K8, DC_L1_DTLB_MISS_AND_L2_DTLB_HIT) \ 261 __PMC_EV(K8, DC_L1_DTLB_MISS_AND_L2_DTLB_MISS) \ 262 __PMC_EV(K8, DC_MISALIGNED_DATA_REFERENCE) \ 263 __PMC_EV(K8, DC_MICROARCHITECTURAL_LATE_CANCEL) \ 264 __PMC_EV(K8, DC_MICROARCHITECTURAL_EARLY_CANCEL) \ 265 __PMC_EV(K8, DC_ONE_BIT_ECC_ERROR) \ 266 __PMC_EV(K8, DC_DISPATCHED_PREFETCH_INSTRUCTIONS) \ 267 __PMC_EV(K8, DC_DCACHE_ACCESSES_BY_LOCKS) \ 268 __PMC_EV(K8, BU_CPU_CLK_UNHALTED) \ 269 __PMC_EV(K8, BU_INTERNAL_L2_REQUEST) \ 270 __PMC_EV(K8, BU_FILL_REQUEST_L2_MISS) \ 271 __PMC_EV(K8, BU_FILL_INTO_L2) \ 272 __PMC_EV(K8, IC_FETCH) \ 273 __PMC_EV(K8, IC_MISS) \ 274 __PMC_EV(K8, IC_REFILL_FROM_L2) \ 275 __PMC_EV(K8, IC_REFILL_FROM_SYSTEM) \ 276 __PMC_EV(K8, IC_L1_ITLB_MISS_AND_L2_ITLB_HIT) \ 277 __PMC_EV(K8, IC_L1_ITLB_MISS_AND_L2_ITLB_MISS) \ 278 __PMC_EV(K8, IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP) \ 279 __PMC_EV(K8, IC_INSTRUCTION_FETCH_STALL) \ 280 __PMC_EV(K8, IC_RETURN_STACK_HIT) \ 281 __PMC_EV(K8, IC_RETURN_STACK_OVERFLOW) \ 282 __PMC_EV(K8, FR_RETIRED_X86_INSTRUCTIONS) \ 283 __PMC_EV(K8, FR_RETIRED_UOPS) \ 284 __PMC_EV(K8, FR_RETIRED_BRANCHES) \ 285 __PMC_EV(K8, FR_RETIRED_BRANCHES_MISPREDICTED) \ 286 __PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES) \ 287 __PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED) \ 288 __PMC_EV(K8, FR_RETIRED_FAR_CONTROL_TRANSFERS) \ 289 __PMC_EV(K8, FR_RETIRED_RESYNCS) \ 290 __PMC_EV(K8, FR_RETIRED_NEAR_RETURNS) \ 291 __PMC_EV(K8, FR_RETIRED_NEAR_RETURNS_MISPREDICTED) \ 292 __PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE) \ 293 __PMC_EV(K8, FR_RETIRED_FPU_INSTRUCTIONS) \ 294 __PMC_EV(K8, FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS) \ 295 __PMC_EV(K8, FR_INTERRUPTS_MASKED_CYCLES) \ 296 __PMC_EV(K8, FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES) \ 297 __PMC_EV(K8, FR_TAKEN_HARDWARE_INTERRUPTS) \ 298 __PMC_EV(K8, FR_DECODER_EMPTY) \ 299 __PMC_EV(K8, FR_DISPATCH_STALLS) \ 300 __PMC_EV(K8, FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE) \ 301 __PMC_EV(K8, FR_DISPATCH_STALL_FOR_SERIALIZATION) \ 302 __PMC_EV(K8, FR_DISPATCH_STALL_FOR_SEGMENT_LOAD) \ 303 __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL) \ 304 __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL) \ 305 __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_FPU_IS_FULL) \ 306 __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_LS_IS_FULL) \ 307 __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET) \ 308 __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING) \ 309 __PMC_EV(K8, FR_FPU_EXCEPTIONS) \ 310 __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR0) \ 311 __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR1) \ 312 __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR2) \ 313 __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR3) \ 314 __PMC_EV(K8, NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT) \ 315 __PMC_EV(K8, NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW) \ 316 __PMC_EV(K8, NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED) \ 317 __PMC_EV(K8, NB_MEMORY_CONTROLLER_TURNAROUND) \ 318 __PMC_EV(K8, NB_MEMORY_CONTROLLER_BYPASS_SATURATION) \ 319 __PMC_EV(K8, NB_SIZED_COMMANDS) \ 320 __PMC_EV(K8, NB_PROBE_RESULT) \ 321 __PMC_EV(K8, NB_HT_BUS0_BANDWIDTH) \ 322 __PMC_EV(K8, NB_HT_BUS1_BANDWIDTH) \ 323 __PMC_EV(K8, NB_HT_BUS2_BANDWIDTH) 324 325 #define PMC_EV_K8_FIRST PMC_EV_K8_FP_DISPATCHED_FPU_OPS 326 #define PMC_EV_K8_LAST PMC_EV_K8_NB_HT_BUS2_BANDWIDTH 327 328 329 /* 330 * Intel Pentium and Pentium MMX Events, from the "Intel 64 and IA-32 331 * Intel(R) Architectures Software Developer's Manual, Volume 3B: 332 * System Programming Guide, Part 2, August 2007". 333 */ 334 #define __PMC_EV_P5() \ 335 __PMC_EV(P5, DATA_READ) \ 336 __PMC_EV(P5, DATA_WRITE) \ 337 __PMC_EV(P5, DATA_TLB_MISS) \ 338 __PMC_EV(P5, DATA_READ_MISS) \ 339 __PMC_EV(P5, DATA_WRITE_MISS) \ 340 __PMC_EV(P5, WRITE_HIT_TO_M_OR_E_STATE_LINES) \ 341 __PMC_EV(P5, DATA_CACHE_LINES_WRITTEN_BACK) \ 342 __PMC_EV(P5, EXTERNAL_SNOOPS) \ 343 __PMC_EV(P5, EXTERNAL_DATA_CACHE_SNOOP_HITS) \ 344 __PMC_EV(P5, MEMORY_ACCESSES_IN_BOTH_PIPES) \ 345 __PMC_EV(P5, BANK_CONFLICTS) \ 346 __PMC_EV(P5, MISALIGNED_DATA_OR_IO_REFERENCES) \ 347 __PMC_EV(P5, CODE_READ) \ 348 __PMC_EV(P5, CODE_TLB_MISS) \ 349 __PMC_EV(P5, CODE_CACHE_MISS) \ 350 __PMC_EV(P5, ANY_SEGMENT_REGISTER_LOADED) \ 351 __PMC_EV(P5, BRANCHES) \ 352 __PMC_EV(P5, BTB_HITS) \ 353 __PMC_EV(P5, TAKEN_BRANCH_OR_BTB_HIT) \ 354 __PMC_EV(P5, PIPELINE_FLUSHES) \ 355 __PMC_EV(P5, INSTRUCTIONS_EXECUTED) \ 356 __PMC_EV(P5, INSTRUCTIONS_EXECUTED_V_PIPE) \ 357 __PMC_EV(P5, BUS_CYCLE_DURATION) \ 358 __PMC_EV(P5, WRITE_BUFFER_FULL_STALL_DURATION) \ 359 __PMC_EV(P5, WAITING_FOR_DATA_MEMORY_READ_STALL_DURATION) \ 360 __PMC_EV(P5, STALL_ON_WRITE_TO_AN_E_OR_M_STATE_LINE) \ 361 __PMC_EV(P5, LOCKED_BUS_CYCLE) \ 362 __PMC_EV(P5, IO_READ_OR_WRITE_CYCLE) \ 363 __PMC_EV(P5, NONCACHEABLE_MEMORY_READS) \ 364 __PMC_EV(P5, PIPELINE_AGI_STALLS) \ 365 __PMC_EV(P5, FLOPS) \ 366 __PMC_EV(P5, BREAKPOINT_MATCH_ON_DR0_REGISTER) \ 367 __PMC_EV(P5, BREAKPOINT_MATCH_ON_DR1_REGISTER) \ 368 __PMC_EV(P5, BREAKPOINT_MATCH_ON_DR2_REGISTER) \ 369 __PMC_EV(P5, BREAKPOINT_MATCH_ON_DR3_REGISTER) \ 370 __PMC_EV(P5, HARDWARE_INTERRUPTS) \ 371 __PMC_EV(P5, DATA_READ_OR_WRITE) \ 372 __PMC_EV(P5, DATA_READ_MISS_OR_WRITE_MISS) \ 373 __PMC_EV(P5, BUS_OWNERSHIP_LATENCY) \ 374 __PMC_EV(P5, BUS_OWNERSHIP_TRANSFERS) \ 375 __PMC_EV(P5, MMX_INSTRUCTIONS_EXECUTED_U_PIPE) \ 376 __PMC_EV(P5, MMX_INSTRUCTIONS_EXECUTED_V_PIPE) \ 377 __PMC_EV(P5, CACHE_M_LINE_SHARING) \ 378 __PMC_EV(P5, CACHE_LINE_SHARING) \ 379 __PMC_EV(P5, EMMS_INSTRUCTIONS_EXECUTED) \ 380 __PMC_EV(P5, TRANSITIONS_BETWEEN_MMX_AND_FP_INSTRUCTIONS) \ 381 __PMC_EV(P5, BUS_UTILIZATION_DUE_TO_PROCESSOR_ACTIVITY) \ 382 __PMC_EV(P5, WRITES_TO_NONCACHEABLE_MEMORY) \ 383 __PMC_EV(P5, SATURATING_MMX_INSTRUCTIONS_EXECUTED) \ 384 __PMC_EV(P5, SATURATIONS_PERFORMED) \ 385 __PMC_EV(P5, NUMBER_OF_CYCLES_NOT_IN_HALT_STATE) \ 386 __PMC_EV(P5, DATA_CACHE_TLB_MISS_STALL_DURATION) \ 387 __PMC_EV(P5, MMX_INSTRUCTION_DATA_READS) \ 388 __PMC_EV(P5, MMX_INSTRUCTION_DATA_READ_MISSES) \ 389 __PMC_EV(P5, FLOATING_POINT_STALLS_DURATION) \ 390 __PMC_EV(P5, TAKEN_BRANCHES) \ 391 __PMC_EV(P5, D1_STARVATION_AND_FIFO_IS_EMPTY) \ 392 __PMC_EV(P5, D1_STARVATION_AND_ONLY_ONE_INSTRUCTION_IN_FIFO) \ 393 __PMC_EV(P5, MMX_INSTRUCTION_DATA_WRITES) \ 394 __PMC_EV(P5, MMX_INSTRUCTION_DATA_WRITE_MISSES) \ 395 __PMC_EV(P5, PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS) \ 396 __PMC_EV(P5, \ 397 PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS_RESOLVED_IN_WB_STAGE) \ 398 __PMC_EV(P5, MISALIGNED_DATA_MEMORY_REFERENCE_ON_MMX_INSTRUCTIONS) \ 399 __PMC_EV(P5, PIPELINE_STALL_FOR_MMX_INSTRUCTION_DATA_MEMORY_READS) \ 400 __PMC_EV(P5, MISPREDICTED_OR_UNPREDICTED_RETURNS) \ 401 __PMC_EV(P5, PREDICTED_RETURNS) \ 402 __PMC_EV(P5, MMX_MULTIPLY_UNIT_INTERLOCK) \ 403 __PMC_EV(P5, MOVD_MOVQ_STORE_STALL_DUE_TO_PREVIOUS_MMX_OPERATION) \ 404 __PMC_EV(P5, RETURNS) \ 405 __PMC_EV(P5, BTB_FALSE_ENTRIES) \ 406 __PMC_EV(P5, BTB_MISS_PREDICTION_ON_NOT_TAKEN_BRANCH) \ 407 __PMC_EV(P5, \ 408 FULL_WRITE_BUFFER_STALL_DURATION_WHILE_EXECUTING_MMX_INSTRUCTIONS) \ 409 __PMC_EV(P5, STALL_ON_MMX_INSTRUCTION_WRITE_TO_E_OR_M_STATE_LINE) 410 411 #define PMC_EV_P5_FIRST PMC_EV_P5_DATA_READ 412 #define PMC_EV_P5_LAST \ 413 PMC_EV_P5_STALL_ON_MMX_INSTRUCTION_WRITE_TO_E_OR_M_STATE_LINE 414 415 #define __PMC_EV_IAF() /* Intel architectural fixed function */ 416 #define __PMC_EV_IAP() /* Intel architectural programmable */ 417 418 /* timestamp counters. */ 419 #define __PMC_EV_TSC() \ 420 __PMC_EV(TSC, TSC) 421 422 #define PMC_EV_TSC_FIRST PMC_EV_TSC_TSC 423 #define PMC_EV_TSC_LAST PMC_EV_TSC_TSC 424 425 /* 426 * All known PMC events. 427 * 428 * PMC event numbers are allocated sparsely to allow new PMC events to 429 * be added to a PMC class without breaking ABI compatibility. The 430 * current allocation scheme is: 431 * 432 * START #EVENTS DESCRIPTION 433 * 0 0x1000 Reserved 434 * 0x1000 0x0001 TSC 435 * 0x2000 0x0080 AMD K7 events 436 * 0x2080 0x0100 AMD K8 events 437 * 0x10000 0x0080 INTEL architectural fixed-function events 438 * 0x10080 0x0F80 INTEL architectural programmable events 439 * 0x11000 0x0080 INTEL Pentium 4 events 440 * 0x11080 0x0080 INTEL Pentium MMX events 441 * 0x11100 0x0100 INTEL Pentium Pro/P-II/P-III/Pentium-M events 442 */ 443 #define __PMC_EVENTS() \ 444 __PMC_EV_BLOCK(TSC, 0x01000) \ 445 __PMC_EV_TSC() \ 446 __PMC_EV_BLOCK(K7, 0x2000) \ 447 __PMC_EV_K7() \ 448 __PMC_EV_BLOCK(K8, 0x2080) \ 449 __PMC_EV_K8() \ 450 __PMC_EV_BLOCK(IAF, 0x10000) \ 451 __PMC_EV_IAF() \ 452 __PMC_EV_BLOCK(IAP, 0x10080) \ 453 __PMC_EV_IAP() \ 454 __PMC_EV_BLOCK(P4, 0x11000) \ 455 __PMC_EV_P4() \ 456 __PMC_EV_BLOCK(P5, 0x11080) \ 457 __PMC_EV_P5() \ 458 __PMC_EV_BLOCK(P6, 0x11100) \ 459 __PMC_EV_P6() 460 461 #define PMC_EVENT_FIRST PMC_EV_TSC_TSC 462 #define PMC_EVENT_LAST PMC_EV_P6_LAST 463 464 #endif /* _DEV_HWPMC_PMC_EVENTS_H_ */ 465