1*a99d04f3SAndre Silva /* 2*a99d04f3SAndre Silva * Copyright (c) 2026 Advanced Micro Devices, Inc. 3*a99d04f3SAndre Silva * 4*a99d04f3SAndre Silva * SPDX-License-Identifier: BSD-2-Clause 5*a99d04f3SAndre Silva */ 6*a99d04f3SAndre Silva 7*a99d04f3SAndre Silva /* 8*a99d04f3SAndre Silva * AMD/Intel RAPL energy counters exposed as an hwpmc(4) PMC class. 9*a99d04f3SAndre Silva */ 10*a99d04f3SAndre Silva 11*a99d04f3SAndre Silva #ifndef _DEV_HWPMC_RAPL_H_ 12*a99d04f3SAndre Silva #define _DEV_HWPMC_RAPL_H_ 1 13*a99d04f3SAndre Silva 14*a99d04f3SAndre Silva #ifdef _KERNEL 15*a99d04f3SAndre Silva 16*a99d04f3SAndre Silva struct pmc_mdep; 17*a99d04f3SAndre Silva 18*a99d04f3SAndre Silva /* 19*a99d04f3SAndre Silva * Max RAPL rows per CPU: package, "cores" and (Intel only) DRAM. The actual 20*a99d04f3SAndre Silva * per-vendor count is determined at initialize time (pcd_num). 21*a99d04f3SAndre Silva */ 22*a99d04f3SAndre Silva #define RAPL_MAX_NPMCS 3 23*a99d04f3SAndre Silva 24*a99d04f3SAndre Silva int pmc_rapl_initialize(struct pmc_mdep *_md, int _maxcpu, int _classindex); 25*a99d04f3SAndre Silva void pmc_rapl_finalize(struct pmc_mdep *_md); 26*a99d04f3SAndre Silva 27*a99d04f3SAndre Silva #endif /* _KERNEL */ 28*a99d04f3SAndre Silva #endif /* _DEV_HWPMC_RAPL_H_ */ 29