1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2026, Ali Jose Mashtizadeh 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _DEV_HWPMC_IBS_H_ 30 #define _DEV_HWPMC_IBS_H_ 1 31 32 #define IBS_NPMCS 2 33 #define IBS_PMC_FETCH 0 34 #define IBS_PMC_OP 1 35 36 /* 37 * All of the CPUID definitions come from AMD PPR Vol 1 for AMD Family 1Ah 38 * Model 02h C1 (57238) 2024-09-29 Revision 0.24. 39 */ 40 #define CPUID_IBSID 0x8000001B 41 #define CPUID_IBSID_IBSFFV 0x00000001 /* IBS Feature Flags Valid */ 42 #define CPUID_IBSID_FETCHSAM 0x00000002 /* IBS Fetch Sampling */ 43 #define CPUID_IBSID_OPSAM 0x00000004 /* IBS Execution Sampling */ 44 #define CPUID_IBSID_RDWROPCNT 0x00000008 /* RdWr Operationg Counter */ 45 #define CPUID_IBSID_OPCNT 0x00000010 /* Operation Counter */ 46 #define CPUID_IBSID_BRNTRGT 0x00000020 /* Branch Target Address */ 47 #define CPUID_IBSID_OPCNTEXT 0x00000040 /* Extend Counter */ 48 #define CPUID_IBSID_RIPINVALIDCHK 0x00000080 /* Invalid RIP Indication */ 49 #define CPUID_IBSID_OPFUSE 0x00000010 /* Fused Branch Operation */ 50 #define CPUID_IBSID_IBSFETCHCTLEXTD 0x00000020 /* IBS Fetch Control Ext */ 51 #define CPUID_IBSID_IBSOPDATA4 0x00000040 /* IBS OP DATA4 */ 52 #define CPUID_IBSID_ZEN4IBSEXTENSIONS 0x00000080 /* IBS Zen 4 Extensions */ 53 #define CPUID_IBSID_IBSLOADLATENCYFILT 0x00000100 /* Load Latency Filtering */ 54 #define CPUID_IBSID_IBSUPDTDDTLBSTATS 0x00080000 /* Simplified DTLB Stats */ 55 56 /* 57 * All of these definitions here come from AMD64 Architecture Programmer's 58 * Manual Volume 2: System Programming (24593) 2025-07-02 Version 3.43. with 59 * the following exceptions: 60 * 61 * OpData4 and fields come from the BKDG for AMD Family 15h Model 70-7Fh 62 * (55072) 2018-06-20 Revision 3.09. 63 */ 64 65 /* IBS MSRs */ 66 #define IBS_CTL 0xC001103A /* IBS Control */ 67 #define IBS_CTL_LVTOFFSETVALID (1ULL << 8) 68 #define IBS_CTL_LVTOFFSETMASK 0x0000000F 69 70 /* IBS Fetch Control */ 71 #define IBS_FETCH_CTL 0xC0011030 /* IBS Fetch Control */ 72 #define IBS_FETCH_CTL_L3MISS (1ULL << 61) /* L3 Cache Miss */ 73 #define IBS_FETCH_CTL_OPCACHEMISS (1ULL << 60) /* Op Cache Miss */ 74 #define IBS_FETCH_CTL_L3MISSONLY (1ULL << 59) /* L3 Miss Filtering */ 75 #define IBS_FETCH_CTL_RANDOMIZE (1ULL << 57) /* Randomized Tagging */ 76 #define IBS_FETCH_CTL_L1TLBMISS (1ULL << 55) /* L1 TLB Miss */ 77 // Page size 54:53 78 #define IBS_FETCH_CTL_PHYSADDRVALID (1ULL << 52) /* PHYSADDR Valid */ 79 #define IBS_FETCH_CTL_ICMISS (1ULL << 51) /* Inst. Cache Miss */ 80 #define IBS_FETCH_CTL_COMPLETE (1ULL << 50) /* Complete */ 81 #define IBS_FETCH_CTL_VALID (1ULL << 49) /* Valid */ 82 #define IBS_FETCH_CTL_ENABLE (1ULL << 48) /* Enable */ 83 #define IBS_FETCH_CTL_MAXCNTMASK 0x0000FFFFULL 84 85 #define IBS_FETCH_CTL_TO_LAT(_c) ((_c >> 32) & 0x0000FFFF) 86 87 #define IBS_FETCH_LINADDR 0xC0011031 /* Fetch Linear Address */ 88 #define IBS_FETCH_PHYSADDR 0xC0011032 /* Fetch Physical Address */ 89 #define IBS_FETCH_EXTCTL 0xC001103C /* Fetch Control Extended */ 90 91 #define PMC_MPIDX_FETCH_CTL 0 92 #define PMC_MPIDX_FETCH_EXTCTL 1 93 #define PMC_MPIDX_FETCH_LINADDR 2 94 #define PMC_MPIDX_FETCH_PHYSADDR 3 95 96 /* IBS Execution Control */ 97 #define IBS_OP_CTL 0xC0011033 /* IBS Execution Control */ 98 #define IBS_OP_CTL_COUNTERCONTROL (1ULL << 19) /* Counter Control */ 99 #define IBS_OP_CTL_VALID (1ULL << 18) /* Valid */ 100 #define IBS_OP_CTL_ENABLE (1ULL << 17) /* Enable */ 101 #define IBS_OP_CTL_L3MISSONLY (1ULL << 16) /* L3 Miss Filtering */ 102 #define IBS_OP_CTL_MAXCNTMASK 0x0000FFFFULL 103 104 #define IBS_OP_RIP 0xC0011034 /* IBS Op RIP */ 105 #define IBS_OP_DATA 0xC0011035 /* IBS Op Data */ 106 #define IBS_OP_DATA_RIPINVALID (1ULL << 38) /* RIP Invalid */ 107 #define IBS_OP_DATA_BRANCHRETIRED (1ULL << 37) /* Branch Retired */ 108 #define IBS_OP_DATA_BRANCHMISPREDICTED (1ULL << 36) /* Branch Mispredicted */ 109 #define IBS_OP_DATA_BRANCHTAKEN (1ULL << 35) /* Branch Taken */ 110 #define IBS_OP_DATA_RETURN (1ULL << 34) /* Return */ 111 112 #define IBS_OP_DATA2 0xC0011036 /* IBS Op Data 2 */ 113 #define IBS_OP_DATA3 0xC0011037 /* IBS Op Data 3 */ 114 #define IBS_OP_DATA3_DCPHYADDRVALID (1ULL << 18) /* DC Physical Address */ 115 #define IBS_OP_DATA3_DCLINADDRVALID (1ULL << 17) /* DC Linear Address */ 116 #define IBS_OP_DATA3_LOCKEDOP (1ULL << 15) /* DC Locked Op */ 117 #define IBS_OP_DATA3_UCMEMACCESS (1ULL << 14) /* DC UC Memory Access */ 118 #define IBS_OP_DATA3_WCMEMACCESS (1ULL << 13) /* DC WC Memory Access */ 119 #define IBS_OP_DATA3_DCMISALIGN (1ULL << 8) /* DC Misaligned Access */ 120 #define IBS_OP_DATA3_DCMISS (1ULL << 7) /* DC Miss */ 121 #define IBS_OP_DATA3_DCL1TLBHIT1G (1ULL << 5) /* DC L1 TLB Hit 1-GB */ 122 #define IBS_OP_DATA3_DCL1TLBHIT2M (1ULL << 4) /* DC L1 TLB Hit 2-MB */ 123 #define IBS_OP_DATA3_DCL1TLBMISS (1ULL << 2) /* DC L1 TLB Miss */ 124 #define IBS_OP_DATA3_STORE (1ULL << 1) /* Store */ 125 #define IBS_OP_DATA3_LOAD (1ULL << 0) /* Load */ 126 #define IBS_OP_DATA3_TO_DCLAT(_c) ((_c >> 32) & 0x0000FFFF) 127 128 #define IBS_OP_DC_LINADDR 0xC0011038 /* IBS DC Linear Address */ 129 #define IBS_OP_DC_PHYSADDR 0xC0011039 /* IBS DC Physical Address */ 130 #define IBS_TGT_RIP 0xC001103B /* IBS Branch Target */ 131 #define IBS_OP_DATA4 0xC001103D /* IBS Op Data 4 */ 132 #define IBS_OP_DATA4_LDRESYNC (1ULL << 0) /* Load Resync */ 133 134 #define PMC_MPIDX_OP_CTL 0 135 #define PMC_MPIDX_OP_RIP 1 136 #define PMC_MPIDX_OP_DATA 2 137 #define PMC_MPIDX_OP_DATA2 3 138 #define PMC_MPIDX_OP_DATA3 4 139 #define PMC_MPIDX_OP_DC_LINADDR 5 140 #define PMC_MPIDX_OP_DC_PHYSADDR 6 141 #define PMC_MPIDX_OP_TGT_RIP 7 142 #define PMC_MPIDX_OP_DATA4 8 143 144 /* 145 * IBS data is encoded as using the multipart flag in the existing callchain 146 * structure. The PMC ID number tells you if the sample contains a fetch or an 147 * op sample. The available payload will be encoded in the MSR order with a 148 * variable length. 149 */ 150 151 struct pmc_md_ibs_op_pmcallocate { 152 uint32_t ibs_flag; 153 uint32_t ibs_type; 154 uint64_t ibs_ctl; 155 uint64_t ibs_ctl2; 156 }; 157 158 #ifdef _KERNEL 159 160 /* MD extension for 'struct pmc' */ 161 struct pmc_md_ibs_pmc { 162 uint32_t ibs_flag; 163 uint32_t ibs_type; 164 uint64_t ibs_ctl; 165 uint64_t ibs_ctl2; 166 }; 167 168 #define IBS_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_SYSTEM | \ 169 PMC_CAP_EDGE | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 170 171 int pmc_ibs_initialize(struct pmc_mdep *md, int ncpu); 172 void pmc_ibs_finalize(struct pmc_mdep *md); 173 int pmc_ibs_intr(struct trapframe *tf); 174 175 #endif /* _KERNEL */ 176 #endif /* _DEV_HWPMC_IBS_H_ */ 177