xref: /freebsd/sys/dev/exca/excareg.h (revision 74fe6c29fb7eef3418d7919dcd41dc1a04a982a1)
1 /*	$NetBSD: i82365reg.h,v 1.3 1998/12/20 17:53:28 nathanw Exp $	*/
2 /* $FreeBSD$ */
3 
4 /*-
5  * SPDX-License-Identifier: BSD-4-Clause AND BSD-2-Clause-FreeBSD
6  *
7  * Copyright (c) 2002 M Warner Losh.  All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  *
29  * This software may be derived from NetBSD i82365.c and other files with
30  * the following copyright:
31  *
32  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
33  *
34  * Redistribution and use in source and binary forms, with or without
35  * modification, are permitted provided that the following conditions
36  * are met:
37  * 1. Redistributions of source code must retain the above copyright
38  *    notice, this list of conditions and the following disclaimer.
39  * 2. Redistributions in binary form must reproduce the above copyright
40  *    notice, this list of conditions and the following disclaimer in the
41  *    documentation and/or other materials provided with the distribution.
42  * 3. All advertising materials mentioning features or use of this software
43  *    must display the following acknowledgement:
44  *	This product includes software developed by Marc Horowitz.
45  * 4. The name of the author may not be used to endorse or promote products
46  *    derived from this software without specific prior written permission.
47  *
48  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
49  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
50  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
51  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
52  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
53  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
54  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
55  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
56  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
57  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
58  */
59 
60 #ifndef _SYS_DEV_EXCA_EXCAREG_H
61 #define _SYS_DEV_EXCA_EXCAREG_H
62 
63 /*
64  * All information is from the intel 82365sl PC Card Interface Controller
65  * (PCIC) data sheet, marked "preliminary".  Order number 290423-002, January
66  * 1993.
67  */
68 
69 #define	EXCA_IOSIZE		2
70 
71 #define	EXCA_REG_INDEX		0
72 #define	EXCA_REG_DATA		1
73 
74 #define EXCA_NSLOTS		4	/* 2 in 2 chips */
75 
76 /*
77  * I/o ports
78  */
79 #define EXCA_INDEX0		0x3e0
80 
81 /*
82  * The PCIC allows two chips to share the same address.  In order not to run
83  * afoul of the bsd device model, this driver will treat those chips as
84  * the same device.
85  */
86 
87 #define	EXCA_CHIP0_BASE		0x00
88 #define	EXCA_CHIP1_BASE		0x80
89 
90 /* Each PCIC chip can drive two sockets */
91 
92 #define EXCA_SOCKET_SIZE	0x40
93 #define	EXCA_SOCKETA_INDEX	0x00
94 #define	EXCA_SOCKETB_INDEX	EXCA_SOCKET_SIZE
95 
96 /* general setup registers */
97 
98 #define	EXCA_IDENT				0x00	/* RO */
99 #define	EXCA_IDENT_IFTYPE_MASK			0xC0
100 #define	EXCA_IDENT_IFTYPE_IO_ONLY		0x00
101 #define	EXCA_IDENT_IFTYPE_MEM_ONLY		0x40
102 #define	EXCA_IDENT_IFTYPE_MEM_AND_IO		0x80
103 #define	EXCA_IDENT_IFTYPE_RESERVED		0xC0
104 #define	EXCA_IDENT_ZERO				0x30
105 #define	EXCA_IDENT_REV_MASK			0x0F
106 #define	EXCA_IDENT_REV_I82365SLR0		0x02	/* step a/b */
107 #define	EXCA_IDENT_REV_I82365SLR1		0x03	/* step c */
108 #define	EXCA_IDENT_REV_I82365SLDF		0x04	/* step df */
109 #define	EXCA_IDENT_REV_IBM1			0x08	/* ibm clone */
110 #define	EXCA_IDENT_REV_IBM2			0x09	/* ibm clone */
111 #define	EXCA_IDENT_REV_IBM_KING			0x0a	/* ibm king */
112 
113 #define	EXCA_IF_STATUS				0x01	/* RO */
114 #define	EXCA_IF_STATUS_GPI			0x80 /* General Purpose Input */
115 #define	EXCA_IF_STATUS_POWERACTIVE		0x40
116 #define	EXCA_IF_STATUS_READY			0x20 /* really READY/!BUSY */
117 #define	EXCA_IF_STATUS_MEM_WP			0x10
118 #define	EXCA_IF_STATUS_CARDDETECT_MASK		0x0C
119 #define	EXCA_IF_STATUS_CARDDETECT_PRESENT	0x0C
120 #define	EXCA_IF_STATUS_BATTERY_MASK		0x03
121 #define	EXCA_IF_STATUS_BATTERY_DEAD1		0x00
122 #define	EXCA_IF_STATUS_BATTERY_DEAD2		0x01
123 #define	EXCA_IF_STATUS_BATTERY_WARNING		0x02
124 #define	EXCA_IF_STATUS_BATTERY_GOOD		0x03
125 
126 #define	EXCA_PWRCTL				0x02	/* RW */
127 #define	EXCA_PWRCTL_OE				0x80	/* output enable */
128 #define	EXCA_PWRCTL_DISABLE_RESETDRV		0x40
129 #define	EXCA_PWRCTL_AUTOSWITCH_ENABLE		0x20
130 #define	EXCA_PWRCTL_PWR_ENABLE			0x10
131 #define	EXCA_PWRCTL_VPP2_MASK			0x0C
132 /* XXX these are a little unclear from the data sheet */
133 #define	EXCA_PWRCTL_VPP2_RESERVED		0x0C
134 #define	EXCA_PWRCTL_VPP2_EN1			0x08
135 #define	EXCA_PWRCTL_VPP2_EN0			0x04
136 #define	EXCA_PWRCTL_VPP2_ENX			0x00
137 #define	EXCA_PWRCTL_VPP1_MASK			0x03
138 /* XXX these are a little unclear from the data sheet */
139 #define	EXCA_PWRCTL_VPP1_RESERVED		0x03
140 #define	EXCA_PWRCTL_VPP1_EN1			0x02
141 #define	EXCA_PWRCTL_VPP1_EN0			0x01
142 #define	EXCA_PWRCTL_VPP1_ENX			0x00
143 
144 #define	EXCA_CSC				0x04	/* RW */
145 #define	EXCA_CSC_ZERO				0xE0
146 #define	EXCA_CSC_GPI				0x10
147 #define	EXCA_CSC_CD				0x08 /* Card Detect Change */
148 #define	EXCA_CSC_READY				0x04
149 #define	EXCA_CSC_BATTWARN			0x02
150 #define	EXCA_CSC_BATTDEAD			0x01	/* for memory cards */
151 #define	EXCA_CSC_RI				0x01	/* for i/o cards */
152 
153 #define	EXCA_ADDRWIN_ENABLE			0x06	/* RW */
154 #define	EXCA_ADDRWIN_ENABLE_IO1			0x80
155 #define	EXCA_ADDRWIN_ENABLE_IO0			0x40
156 #define	EXCA_ADDRWIN_ENABLE_MEMCS16		0x20	/* rtfds if you care */
157 #define	EXCA_ADDRWIN_ENABLE_MEM4		0x10
158 #define	EXCA_ADDRWIN_ENABLE_MEM3		0x08
159 #define	EXCA_ADDRWIN_ENABLE_MEM2		0x04
160 #define	EXCA_ADDRWIN_ENABLE_MEM1		0x02
161 #define	EXCA_ADDRWIN_ENABLE_MEM0		0x01
162 
163 #define	EXCA_CARD_DETECT			0x16	/* RW */
164 #define	EXCA_CARD_DETECT_RESERVED		0xC0
165 #define	EXCA_CARD_DETECT_SW_INTR		0x20
166 #define	EXCA_CARD_DETECT_RESUME_ENABLE		0x10
167 #define	EXCA_CARD_DETECT_GPI_TRANSCTL		0x08
168 #define	EXCA_CARD_DETECT_GPI_ENABLE		0x04
169 #define	EXCA_CARD_DETECT_CFGRST_ENABLE		0x02
170 #define	EXCA_CARD_DETECT_MEMDLY_INHIBIT		0x01
171 
172 /* interrupt registers */
173 
174 #define	EXCA_INTR				0x03	/* RW */
175 #define	EXCA_INTR_RI_ENABLE			0x80
176 #define	EXCA_INTR_RESET				0x40	/* active low (zero) */
177 #define	EXCA_INTR_CARDTYPE_MASK			0x20
178 #define	EXCA_INTR_CARDTYPE_IO			0x20
179 #define	EXCA_INTR_CARDTYPE_MEM			0x00
180 #define	EXCA_INTR_ENABLE			0x10
181 #define	EXCA_INTR_IRQ_MASK			0x0F
182 #define	EXCA_INTR_IRQ_SHIFT			0
183 #define	EXCA_INTR_IRQ_NONE			0x00
184 #define	EXCA_INTR_IRQ_RESERVED1			0x01
185 #define	EXCA_INTR_IRQ_RESERVED2			0x02
186 #define	EXCA_INTR_IRQ3				0x03
187 #define	EXCA_INTR_IRQ4				0x04
188 #define	EXCA_INTR_IRQ5				0x05
189 #define	EXCA_INTR_IRQ_RESERVED6			0x06
190 #define	EXCA_INTR_IRQ7				0x07
191 #define	EXCA_INTR_IRQ_RESERVED8			0x08
192 #define	EXCA_INTR_IRQ9				0x09
193 #define	EXCA_INTR_IRQ10				0x0A
194 #define	EXCA_INTR_IRQ11				0x0B
195 #define	EXCA_INTR_IRQ12				0x0C
196 #define	EXCA_INTR_IRQ_RESERVED13		0x0D
197 #define	EXCA_INTR_IRQ14				0x0E
198 #define	EXCA_INTR_IRQ15				0x0F
199 
200 #define	EXCA_INTR_IRQ_VALIDMASK			0xDEB8 /* 1101 1110 1011 1000 */
201 
202 #define	EXCA_CSC_INTR				0x05	/* RW */
203 #define	EXCA_CSC_INTR_IRQ_MASK			0xF0
204 #define	EXCA_CSC_INTR_IRQ_SHIFT			4
205 #define	EXCA_CSC_INTR_IRQ_NONE			0x00
206 #define	EXCA_CSC_INTR_IRQ_RESERVED1		0x10
207 #define	EXCA_CSC_INTR_IRQ_RESERVED2		0x20
208 #define	EXCA_CSC_INTR_IRQ3			0x30
209 #define	EXCA_CSC_INTR_IRQ4			0x40
210 #define	EXCA_CSC_INTR_IRQ5			0x50
211 #define	EXCA_CSC_INTR_IRQ_RESERVED6		0x60
212 #define	EXCA_CSC_INTR_IRQ7			0x70
213 #define	EXCA_CSC_INTR_IRQ_RESERVED8		0x80
214 #define	EXCA_CSC_INTR_IRQ9			0x90
215 #define	EXCA_CSC_INTR_IRQ10			0xA0
216 #define	EXCA_CSC_INTR_IRQ11			0xB0
217 #define	EXCA_CSC_INTR_IRQ12			0xC0
218 #define	EXCA_CSC_INTR_IRQ_RESERVED13		0xD0
219 #define	EXCA_CSC_INTR_IRQ14			0xE0
220 #define	EXCA_CSC_INTR_IRQ15			0xF0
221 #define	EXCA_CSC_INTR_CD_ENABLE			0x08
222 #define	EXCA_CSC_INTR_READY_ENABLE		0x04
223 #define	EXCA_CSC_INTR_BATTWARN_ENABLE		0x02
224 #define	EXCA_CSC_INTR_BATTDEAD_ENABLE		0x01	/* for memory cards */
225 #define	EXCA_CSC_INTR_RI_ENABLE			0x01	/* for I/O cards */
226 
227 #define	EXCA_CSC_INTR_IRQ_VALIDMASK		0xDEB8 /* 1101 1110 1011 1000 */
228 
229 /* I/O registers */
230 
231 #define	EXCA_IO_WINS				2
232 
233 #define	EXCA_IOCTL				0x07	/* RW */
234 #define	EXCA_IOCTL_IO1_WAITSTATE		0x80
235 #define	EXCA_IOCTL_IO1_ZEROWAIT			0x40
236 #define	EXCA_IOCTL_IO1_IOCS16SRC_MASK		0x20
237 #define	EXCA_IOCTL_IO1_IOCS16SRC_CARD		0x20
238 #define	EXCA_IOCTL_IO1_IOCS16SRC_DATASIZE	0x00
239 #define	EXCA_IOCTL_IO1_DATASIZE_MASK		0x10
240 #define	EXCA_IOCTL_IO1_DATASIZE_16BIT		0x10
241 #define	EXCA_IOCTL_IO1_DATASIZE_8BIT		0x00
242 #define	EXCA_IOCTL_IO0_WAITSTATE		0x08
243 #define	EXCA_IOCTL_IO0_ZEROWAIT			0x04
244 #define	EXCA_IOCTL_IO0_IOCS16SRC_MASK		0x02
245 #define	EXCA_IOCTL_IO0_IOCS16SRC_CARD		0x02
246 #define	EXCA_IOCTL_IO0_IOCS16SRC_DATASIZE	0x00
247 #define	EXCA_IOCTL_IO0_DATASIZE_MASK		0x01
248 #define	EXCA_IOCTL_IO0_DATASIZE_16BIT		0x01
249 #define	EXCA_IOCTL_IO0_DATASIZE_8BIT		0x00
250 
251 #define	EXCA_IOADDR0_START_LSB			0x08
252 #define	EXCA_IOADDR0_START_MSB			0x09
253 #define	EXCA_IOADDR0_STOP_LSB			0x0A
254 #define	EXCA_IOADDR0_STOP_MSB			0x0B
255 #define	EXCA_IOADDR1_START_LSB			0x0C
256 #define	EXCA_IOADDR1_START_MSB			0x0D
257 #define	EXCA_IOADDR1_STOP_LSB			0x0E
258 #define	EXCA_IOADDR1_STOP_MSB			0x0F
259 
260 /* memory registers */
261 
262 /*
263  * memory window addresses refer to bits A23-A12 of the ISA system memory
264  * address.  This is a shift of 12 bits.  The LSB contains A19-A12, and the
265  * MSB contains A23-A20, plus some other bits.
266  */
267 
268 #define	EXCA_MEM_WINS				5
269 
270 #define	EXCA_MEM_SHIFT				12
271 #define	EXCA_MEM_PAGESIZE			(1<<EXCA_MEM_SHIFT)
272 
273 #define	EXCA_SYSMEM_ADDRX_SHIFT				EXCA_MEM_SHIFT
274 #define	EXCA_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK	0x80
275 #define	EXCA_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT	0x80
276 #define	EXCA_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT	0x00
277 #define	EXCA_SYSMEM_ADDRX_START_MSB_ZEROWAIT		0x40
278 #define	EXCA_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK	0x30
279 #define	EXCA_SYSMEM_ADDRX_START_MSB_ADDR_MASK		0x0F
280 
281 #define	EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK		0xC0
282 #define	EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT0		0x00
283 #define	EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT1		0x40
284 #define	EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT2		0x80
285 #define	EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT3		0xC0
286 #define	EXCA_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK		0x0F
287 
288 /*
289  * The card side of a memory mapping consists of bits A19-A12 of the card
290  * memory address in the LSB, and A25-A20 plus some other bits in the MSB.
291  * Again, the shift is 12 bits.
292  */
293 
294 #define	EXCA_CARDMEM_ADDRX_SHIFT		EXCA_MEM_SHIFT
295 #define	EXCA_CARDMEM_ADDRX_MSB_WP		0x80
296 #define	EXCA_CARDMEM_ADDRX_MSB_REGACTIVE_MASK	0x40
297 #define	EXCA_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR	0x40
298 #define	EXCA_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON	0x00
299 #define	EXCA_CARDMEM_ADDRX_MSB_ADDR_MASK	0x3F
300 
301 #define	EXCA_SYSMEM_ADDR0_START_LSB		0x10
302 #define	EXCA_SYSMEM_ADDR0_START_MSB		0x11
303 #define	EXCA_SYSMEM_ADDR0_STOP_LSB		0x12
304 #define	EXCA_SYSMEM_ADDR0_STOP_MSB		0x13
305 
306 #define	EXCA_CARDMEM_ADDR0_LSB			0x14
307 #define	EXCA_CARDMEM_ADDR0_MSB			0x15
308 
309 /* #define	EXCA_RESERVED			0x17 */
310 
311 #define	EXCA_SYSMEM_ADDR1_START_LSB		0x18
312 #define	EXCA_SYSMEM_ADDR1_START_MSB		0x19
313 #define	EXCA_SYSMEM_ADDR1_STOP_LSB		0x1A
314 #define	EXCA_SYSMEM_ADDR1_STOP_MSB		0x1B
315 
316 #define	EXCA_CARDMEM_ADDR1_LSB			0x1C
317 #define	EXCA_CARDMEM_ADDR1_MSB			0x1D
318 
319 #define	EXCA_SYSMEM_ADDR2_START_LSB		0x20
320 #define	EXCA_SYSMEM_ADDR2_START_MSB		0x21
321 #define	EXCA_SYSMEM_ADDR2_STOP_LSB		0x22
322 #define	EXCA_SYSMEM_ADDR2_STOP_MSB		0x23
323 
324 #define	EXCA_CARDMEM_ADDR2_LSB			0x24
325 #define	EXCA_CARDMEM_ADDR2_MSB			0x25
326 
327 /* #define	EXCA_RESERVED			0x26 */
328 /* #define	EXCA_RESERVED			0x27 */
329 
330 #define	EXCA_SYSMEM_ADDR3_START_LSB		0x28
331 #define	EXCA_SYSMEM_ADDR3_START_MSB		0x29
332 #define	EXCA_SYSMEM_ADDR3_STOP_LSB		0x2A
333 #define	EXCA_SYSMEM_ADDR3_STOP_MSB		0x2B
334 
335 #define	EXCA_CARDMEM_ADDR3_LSB			0x2C
336 #define	EXCA_CARDMEM_ADDR3_MSB			0x2D
337 
338 /* #define	EXCA_RESERVED			0x2E */
339 /* #define	EXCA_RESERVED			0x2F */
340 
341 #define	EXCA_SYSMEM_ADDR4_START_LSB		0x30
342 #define	EXCA_SYSMEM_ADDR4_START_MSB		0x31
343 #define	EXCA_SYSMEM_ADDR4_STOP_LSB		0x32
344 #define	EXCA_SYSMEM_ADDR4_STOP_MSB		0x33
345 
346 #define	EXCA_CARDMEM_ADDR4_LSB			0x34
347 #define	EXCA_CARDMEM_ADDR4_MSB			0x35
348 
349 /* #define	EXCA_RESERVED			0x36 */
350 /* #define	EXCA_RESERVED			0x37 */
351 /* #define	EXCA_RESERVED			0x38 */
352 /* #define	EXCA_RESERVED			0x39 */
353 /* #define	EXCA_RESERVED			0x3A */
354 /* #define	EXCA_RESERVED			0x3B */
355 /* #define	EXCA_RESERVED			0x3C */
356 /* #define	EXCA_RESERVED			0x3D */
357 /* #define	EXCA_RESERVED			0x3E */
358 /* #define	EXCA_RESERVED			0x3F */
359 
360 /* CardBus extensions - memory window page registers */
361 
362 #define	EXCA_MEMREG_WIN_SHIFT			24
363 #define	EXCA_SYSMEM_ADDR0_WIN			0x40
364 #define	EXCA_SYSMEM_ADDR1_WIN			0x41
365 #define	EXCA_SYSMEM_ADDR2_WIN			0x42
366 #define	EXCA_SYSMEM_ADDR3_WIN			0x43
367 #define	EXCA_SYSMEM_ADDR4_WIN			0x44
368 
369 /* vendor-specific registers */
370 
371 #define	EXCA_INTEL_GLOBAL_CTL			0x1E	/* RW */
372 #define	EXCA_INTEL_GLOBAL_CTL_RESERVED		0xF0
373 #define	EXCA_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE	0x08
374 #define	EXCA_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK	0x04
375 #define	EXCA_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE	0x02
376 #define	EXCA_INTEL_GLOBAL_CTL_POWERDOWN		0x01
377 
378 #define	EXCA_CIRRUS_MISC_CTL_2			0x1E
379 #define	EXCA_CIRRUS_MISC_CTL_2_SUSPEND		0x04
380 
381 #define	EXCA_CIRRUS_CHIP_INFO			0x1F
382 #define	EXCA_CIRRUS_CHIP_INFO_CHIP_ID		0xC0
383 #define	EXCA_CIRRUS_CHIP_INFO_SLOTS		0x20
384 #define	EXCA_CIRRUS_CHIP_INFO_REV		0x1F
385 
386 #define EXCA_CIRRUS_EXTENDED_INDEX		0x2E
387 #define EXCA_CIRRUS_EXTENDED_DATA		0x2F
388 #define EXCA_CIRRUS_EXT_CONTROL_1		0x03
389 #define EXCA_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK	0x18
390 
391 #define EXCA_VADEM_VMISC			0x3a
392 #define EXCA_VADEM_REV				0x40
393 #define EXCA_VADEM_COOKIE1			0x0E
394 #define EXCA_VADEM_COOKIE2			0x37
395 
396 #define EXCA_RICOH_ID				0x3a
397 #define EXCA_RID_296				0x32
398 #define EXCA_RID_396				0xb2
399 
400 /*
401  * o2 micro specific registers
402  */
403 #define EXCA_O2MICRO_CTRL_C			0x3a
404 #define EXCA_O2CC_IREQ_INTC			0x80
405 #define EXCA_O2CC_STSCHG_INTC			0x20
406 
407 /*
408  * TOPIC specific registers
409  */
410 #define EXCA_TOPIC97_CTRL			0x3e
411 #define EXCA_TOPIC97_CTRL_LV_MASK		0x03
412 
413 /* Plug and play */
414 #define EXCA_PNP_ACTIONTEC	0x1802A904	/* AEI0218 */
415 #define EXCA_PNP_IBM3765	0x65374d24	/* IBM3765 */
416 #define EXCA_PNP_82365		0x000ED041	/* PNP0E00 */
417 #define EXCA_PNP_CL_PD6720	0x010ED041	/* PNP0E01 */
418 #define EXCA_PNP_VLSI_82C146	0x020ED041	/* PNP0E02 */
419 #define EXCA_PNP_82365_CARDBUS	0x030ED041	/* PNP0E03 */
420 #define EXCA_PNP_SCM_SWAPBOX	0x69046d4c	/* SMC0469 */
421 
422 /*
423  *	Mask of allowable interrupts.
424  *
425  *	For IBM-AT machines, irqs 3, 4, 5, 7, 9, 10, 11, 12, 14, 15 are
426  *	allowed.  Nearly all IBM-AT machines with pcic cards or bridges
427  *	wire these interrupts (or a subset thereof) to the corresponding
428  *	pins on the ISA bus.  Some older laptops are reported to not route
429  *	all the interrupt pins to the bus because the designers knew that
430  *	some would conflict with builtin devices.  Older versions of Windows
431  *	NT had a special device that would probe for conflicts early in the
432  *	boot process and formulate a mapping table.  Maybe we should do
433  *	something similar.
434  */
435 #define	EXCA_INT_MASK_ALLOWED	0xDEB8		/* AT */
436 
437 #endif /* !_SYS_DEV_EXCA_EXCAREG_H */
438