1 /*- 2 * Copyright (c) 2011-2012 Stefan Bethke. 3 * Copyright (c) 2012 Adrian Chadd. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #include <sys/param.h> 31 #include <sys/bus.h> 32 #include <sys/errno.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/module.h> 36 #include <sys/mutex.h> 37 #include <sys/socket.h> 38 #include <sys/sockio.h> 39 #include <sys/sysctl.h> 40 #include <sys/systm.h> 41 42 #include <net/if.h> 43 #include <net/if_media.h> 44 45 #include <machine/bus.h> 46 #include <dev/iicbus/iic.h> 47 #include <dev/iicbus/iiconf.h> 48 #include <dev/iicbus/iicbus.h> 49 #include <dev/mii/mii.h> 50 #include <dev/mii/miivar.h> 51 #include <dev/mdio/mdio.h> 52 53 #include <dev/etherswitch/etherswitch.h> 54 55 #include <dev/etherswitch/arswitch/arswitchreg.h> 56 #include <dev/etherswitch/arswitch/arswitchvar.h> 57 58 #include <dev/etherswitch/arswitch/arswitch_reg.h> 59 #include <dev/etherswitch/arswitch/arswitch_phy.h> 60 61 #include "mdio_if.h" 62 #include "miibus_if.h" 63 #include "etherswitch_if.h" 64 65 #if defined(DEBUG) 66 static SYSCTL_NODE(_debug, OID_AUTO, arswitch, CTLFLAG_RD, 0, "arswitch"); 67 #endif 68 69 /* 70 * Access PHYs integrated into the switch by going direct 71 * to the PHY space itself, rather than through the switch 72 * MDIO register. 73 */ 74 int 75 arswitch_readphy_external(device_t dev, int phy, int reg) 76 { 77 int ret; 78 struct arswitch_softc *sc; 79 80 sc = device_get_softc(dev); 81 82 ARSWITCH_LOCK(sc); 83 ret = (MDIO_READREG(device_get_parent(dev), phy, reg)); 84 ARSWITCH_UNLOCK(sc); 85 86 return (ret); 87 } 88 89 int 90 arswitch_writephy_external(device_t dev, int phy, int reg, int data) 91 { 92 struct arswitch_softc *sc; 93 94 sc = device_get_softc(dev); 95 96 ARSWITCH_LOCK(sc); 97 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 98 reg, data); 99 ARSWITCH_UNLOCK(sc); 100 101 return (0); 102 } 103 104 /* 105 * Access PHYs integrated into the switch chip through the switch's MDIO 106 * control register. 107 */ 108 int 109 arswitch_readphy_internal(device_t dev, int phy, int reg) 110 { 111 struct arswitch_softc *sc; 112 uint32_t data = 0, ctrl; 113 int err, timeout; 114 uint32_t a; 115 116 sc = device_get_softc(dev); 117 ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED); 118 119 if (phy < 0 || phy >= 32) 120 return (ENXIO); 121 if (reg < 0 || reg >= 32) 122 return (ENXIO); 123 124 if (AR8X16_IS_SWITCH(sc, AR8327)) 125 a = AR8327_REG_MDIO_CTRL; 126 else 127 a = AR8X16_REG_MDIO_CTRL; 128 129 ARSWITCH_LOCK(sc); 130 err = arswitch_writereg_msb(dev, a, 131 AR8X16_MDIO_CTRL_BUSY | AR8X16_MDIO_CTRL_MASTER_EN | 132 AR8X16_MDIO_CTRL_CMD_READ | 133 (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) | 134 (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT)); 135 DEVERR(dev, err, "arswitch_readphy()=%d: phy=%d.%02x\n", phy, reg); 136 if (err != 0) 137 goto fail; 138 for (timeout = 100; timeout--; ) { 139 ctrl = arswitch_readreg_msb(dev, a); 140 if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0) 141 break; 142 } 143 if (timeout < 0) { 144 DPRINTF(dev, "arswitch_readphy(): phy=%d.%02x; timeout=%d\n", phy, reg, timeout); 145 goto fail; 146 } 147 data = arswitch_readreg_lsb(dev, a) & 148 AR8X16_MDIO_CTRL_DATA_MASK; 149 ARSWITCH_UNLOCK(sc); 150 return (data); 151 152 fail: 153 ARSWITCH_UNLOCK(sc); 154 return (-1); 155 } 156 157 int 158 arswitch_writephy_internal(device_t dev, int phy, int reg, int data) 159 { 160 struct arswitch_softc *sc; 161 uint32_t ctrl; 162 int err, timeout; 163 uint32_t a; 164 165 sc = device_get_softc(dev); 166 ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED); 167 168 if (reg < 0 || reg >= 32) 169 return (ENXIO); 170 171 if (AR8X16_IS_SWITCH(sc, AR8327)) 172 a = AR8327_REG_MDIO_CTRL; 173 else 174 a = AR8X16_REG_MDIO_CTRL; 175 176 ARSWITCH_LOCK(sc); 177 err = arswitch_writereg(dev, a, 178 AR8X16_MDIO_CTRL_BUSY | 179 AR8X16_MDIO_CTRL_MASTER_EN | 180 AR8X16_MDIO_CTRL_CMD_WRITE | 181 (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) | 182 (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT) | 183 (data & AR8X16_MDIO_CTRL_DATA_MASK)); 184 if (err != 0) 185 goto out; 186 for (timeout = 100; timeout--; ) { 187 ctrl = arswitch_readreg(dev, a); 188 if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0) 189 break; 190 } 191 if (timeout < 0) 192 err = EIO; 193 out: 194 DEVERR(dev, err, "arswitch_writephy()=%d: phy=%d.%02x\n", phy, reg); 195 ARSWITCH_UNLOCK(sc); 196 return (err); 197 } 198