1a043e8c7SAdrian Chadd /*- 2a043e8c7SAdrian Chadd * Copyright (c) 2011-2012 Stefan Bethke. 3a043e8c7SAdrian Chadd * Copyright (c) 2012 Adrian Chadd. 4a043e8c7SAdrian Chadd * All rights reserved. 5a043e8c7SAdrian Chadd * 6a043e8c7SAdrian Chadd * Redistribution and use in source and binary forms, with or without 7a043e8c7SAdrian Chadd * modification, are permitted provided that the following conditions 8a043e8c7SAdrian Chadd * are met: 9a043e8c7SAdrian Chadd * 1. Redistributions of source code must retain the above copyright 10a043e8c7SAdrian Chadd * notice, this list of conditions and the following disclaimer. 11a043e8c7SAdrian Chadd * 2. Redistributions in binary form must reproduce the above copyright 12a043e8c7SAdrian Chadd * notice, this list of conditions and the following disclaimer in the 13a043e8c7SAdrian Chadd * documentation and/or other materials provided with the distribution. 14a043e8c7SAdrian Chadd * 15a043e8c7SAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16a043e8c7SAdrian Chadd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17a043e8c7SAdrian Chadd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18a043e8c7SAdrian Chadd * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19a043e8c7SAdrian Chadd * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20a043e8c7SAdrian Chadd * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21a043e8c7SAdrian Chadd * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22a043e8c7SAdrian Chadd * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23a043e8c7SAdrian Chadd * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24a043e8c7SAdrian Chadd * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25a043e8c7SAdrian Chadd * SUCH DAMAGE. 26a043e8c7SAdrian Chadd * 27a043e8c7SAdrian Chadd * $FreeBSD$ 28a043e8c7SAdrian Chadd */ 29a043e8c7SAdrian Chadd 30a043e8c7SAdrian Chadd #include <sys/param.h> 31a043e8c7SAdrian Chadd #include <sys/bus.h> 32a043e8c7SAdrian Chadd #include <sys/errno.h> 33a043e8c7SAdrian Chadd #include <sys/kernel.h> 34104dc214SGleb Smirnoff #include <sys/lock.h> 35a043e8c7SAdrian Chadd #include <sys/module.h> 36104dc214SGleb Smirnoff #include <sys/mutex.h> 37a043e8c7SAdrian Chadd #include <sys/socket.h> 38a043e8c7SAdrian Chadd #include <sys/sockio.h> 39a043e8c7SAdrian Chadd #include <sys/sysctl.h> 40a043e8c7SAdrian Chadd #include <sys/systm.h> 41a043e8c7SAdrian Chadd 42a043e8c7SAdrian Chadd #include <net/if.h> 43a043e8c7SAdrian Chadd #include <net/if_media.h> 44a043e8c7SAdrian Chadd 45a043e8c7SAdrian Chadd #include <machine/bus.h> 46efce3748SRui Paulo #include <dev/iicbus/iic.h> 47a043e8c7SAdrian Chadd #include <dev/iicbus/iiconf.h> 48a043e8c7SAdrian Chadd #include <dev/iicbus/iicbus.h> 49a043e8c7SAdrian Chadd #include <dev/mii/mii.h> 50a043e8c7SAdrian Chadd #include <dev/mii/miivar.h> 51a043e8c7SAdrian Chadd #include <dev/etherswitch/mdio.h> 52a043e8c7SAdrian Chadd 53a043e8c7SAdrian Chadd #include <dev/etherswitch/etherswitch.h> 54a043e8c7SAdrian Chadd 55a043e8c7SAdrian Chadd #include <dev/etherswitch/arswitch/arswitchreg.h> 56a043e8c7SAdrian Chadd #include <dev/etherswitch/arswitch/arswitchvar.h> 57a043e8c7SAdrian Chadd 58a043e8c7SAdrian Chadd #include <dev/etherswitch/arswitch/arswitch_reg.h> 59a043e8c7SAdrian Chadd #include <dev/etherswitch/arswitch/arswitch_phy.h> 60a043e8c7SAdrian Chadd 61a043e8c7SAdrian Chadd #include "mdio_if.h" 62a043e8c7SAdrian Chadd #include "miibus_if.h" 63a043e8c7SAdrian Chadd #include "etherswitch_if.h" 64a043e8c7SAdrian Chadd 65a043e8c7SAdrian Chadd #if defined(DEBUG) 66a043e8c7SAdrian Chadd static SYSCTL_NODE(_debug, OID_AUTO, arswitch, CTLFLAG_RD, 0, "arswitch"); 67a043e8c7SAdrian Chadd #endif 68a043e8c7SAdrian Chadd 69a043e8c7SAdrian Chadd /* 70*78549b94SAdrian Chadd * Access PHYs integrated into the switch by going direct 71*78549b94SAdrian Chadd * to the PHY space itself, rather than through the switch 72*78549b94SAdrian Chadd * MDIO register. 73*78549b94SAdrian Chadd */ 74*78549b94SAdrian Chadd int 75*78549b94SAdrian Chadd arswitch_readphy_external(device_t dev, int phy, int reg) 76*78549b94SAdrian Chadd { 77*78549b94SAdrian Chadd int ret; 78*78549b94SAdrian Chadd struct arswitch_softc *sc; 79*78549b94SAdrian Chadd 80*78549b94SAdrian Chadd sc = device_get_softc(dev); 81*78549b94SAdrian Chadd 82*78549b94SAdrian Chadd ARSWITCH_LOCK(sc); 83*78549b94SAdrian Chadd ret = (MDIO_READREG(device_get_parent(dev), phy, reg)); 84*78549b94SAdrian Chadd ARSWITCH_UNLOCK(sc); 85*78549b94SAdrian Chadd 86*78549b94SAdrian Chadd return (ret); 87*78549b94SAdrian Chadd } 88*78549b94SAdrian Chadd 89*78549b94SAdrian Chadd int 90*78549b94SAdrian Chadd arswitch_writephy_external(device_t dev, int phy, int reg, int data) 91*78549b94SAdrian Chadd { 92*78549b94SAdrian Chadd struct arswitch_softc *sc; 93*78549b94SAdrian Chadd 94*78549b94SAdrian Chadd sc = device_get_softc(dev); 95*78549b94SAdrian Chadd 96*78549b94SAdrian Chadd ARSWITCH_LOCK(sc); 97*78549b94SAdrian Chadd (void) MDIO_WRITEREG(device_get_parent(dev), phy, 98*78549b94SAdrian Chadd reg, data); 99*78549b94SAdrian Chadd ARSWITCH_UNLOCK(sc); 100*78549b94SAdrian Chadd 101*78549b94SAdrian Chadd return (0); 102*78549b94SAdrian Chadd } 103*78549b94SAdrian Chadd 104*78549b94SAdrian Chadd /* 105*78549b94SAdrian Chadd * Access PHYs integrated into the switch chip through the switch's MDIO 106a043e8c7SAdrian Chadd * control register. 107a043e8c7SAdrian Chadd */ 108a043e8c7SAdrian Chadd int 109*78549b94SAdrian Chadd arswitch_readphy_internal(device_t dev, int phy, int reg) 110a043e8c7SAdrian Chadd { 111454d507aSAleksandr Rybalko struct arswitch_softc *sc; 112a043e8c7SAdrian Chadd uint32_t data = 0, ctrl; 113a043e8c7SAdrian Chadd int err, timeout; 114e765499eSAdrian Chadd uint32_t a; 115a043e8c7SAdrian Chadd 116454d507aSAleksandr Rybalko sc = device_get_softc(dev); 117454d507aSAleksandr Rybalko ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED); 118454d507aSAleksandr Rybalko 119a043e8c7SAdrian Chadd if (phy < 0 || phy >= 32) 120a043e8c7SAdrian Chadd return (ENXIO); 121a043e8c7SAdrian Chadd if (reg < 0 || reg >= 32) 122a043e8c7SAdrian Chadd return (ENXIO); 123454d507aSAleksandr Rybalko 124e765499eSAdrian Chadd if (AR8X16_IS_SWITCH(sc, AR8327)) 125e765499eSAdrian Chadd a = AR8327_REG_MDIO_CTRL; 126e765499eSAdrian Chadd else 127e765499eSAdrian Chadd a = AR8X16_REG_MDIO_CTRL; 128e765499eSAdrian Chadd 129454d507aSAleksandr Rybalko ARSWITCH_LOCK(sc); 130e765499eSAdrian Chadd err = arswitch_writereg_msb(dev, a, 131a043e8c7SAdrian Chadd AR8X16_MDIO_CTRL_BUSY | AR8X16_MDIO_CTRL_MASTER_EN | 132a043e8c7SAdrian Chadd AR8X16_MDIO_CTRL_CMD_READ | 133a043e8c7SAdrian Chadd (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) | 134a043e8c7SAdrian Chadd (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT)); 135a043e8c7SAdrian Chadd DEVERR(dev, err, "arswitch_readphy()=%d: phy=%d.%02x\n", phy, reg); 136a043e8c7SAdrian Chadd if (err != 0) 137454d507aSAleksandr Rybalko goto fail; 138a043e8c7SAdrian Chadd for (timeout = 100; timeout--; ) { 139e765499eSAdrian Chadd ctrl = arswitch_readreg_msb(dev, a); 140a043e8c7SAdrian Chadd if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0) 141a043e8c7SAdrian Chadd break; 142a043e8c7SAdrian Chadd } 143*78549b94SAdrian Chadd if (timeout < 0) { 144*78549b94SAdrian Chadd DPRINTF(dev, "arswitch_readphy(): phy=%d.%02x; timeout=%d\n", phy, reg, timeout); 145454d507aSAleksandr Rybalko goto fail; 146*78549b94SAdrian Chadd } 147e765499eSAdrian Chadd data = arswitch_readreg_lsb(dev, a) & 148a043e8c7SAdrian Chadd AR8X16_MDIO_CTRL_DATA_MASK; 149454d507aSAleksandr Rybalko ARSWITCH_UNLOCK(sc); 150a043e8c7SAdrian Chadd return (data); 151454d507aSAleksandr Rybalko 152454d507aSAleksandr Rybalko fail: 153454d507aSAleksandr Rybalko ARSWITCH_UNLOCK(sc); 154454d507aSAleksandr Rybalko return (-1); 155a043e8c7SAdrian Chadd } 156a043e8c7SAdrian Chadd 157a043e8c7SAdrian Chadd int 158*78549b94SAdrian Chadd arswitch_writephy_internal(device_t dev, int phy, int reg, int data) 159a043e8c7SAdrian Chadd { 160454d507aSAleksandr Rybalko struct arswitch_softc *sc; 161a043e8c7SAdrian Chadd uint32_t ctrl; 162a043e8c7SAdrian Chadd int err, timeout; 163e765499eSAdrian Chadd uint32_t a; 164a043e8c7SAdrian Chadd 165454d507aSAleksandr Rybalko sc = device_get_softc(dev); 166454d507aSAleksandr Rybalko ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED); 167454d507aSAleksandr Rybalko 168a043e8c7SAdrian Chadd if (reg < 0 || reg >= 32) 169a043e8c7SAdrian Chadd return (ENXIO); 170454d507aSAleksandr Rybalko 171e765499eSAdrian Chadd if (AR8X16_IS_SWITCH(sc, AR8327)) 172e765499eSAdrian Chadd a = AR8327_REG_MDIO_CTRL; 173e765499eSAdrian Chadd else 174e765499eSAdrian Chadd a = AR8X16_REG_MDIO_CTRL; 175e765499eSAdrian Chadd 176454d507aSAleksandr Rybalko ARSWITCH_LOCK(sc); 177e765499eSAdrian Chadd err = arswitch_writereg(dev, a, 178a043e8c7SAdrian Chadd AR8X16_MDIO_CTRL_BUSY | 179a043e8c7SAdrian Chadd AR8X16_MDIO_CTRL_MASTER_EN | 180a043e8c7SAdrian Chadd AR8X16_MDIO_CTRL_CMD_WRITE | 181a043e8c7SAdrian Chadd (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) | 1829604b6acSLuiz Otavio O Souza (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT) | 1839604b6acSLuiz Otavio O Souza (data & AR8X16_MDIO_CTRL_DATA_MASK)); 184a043e8c7SAdrian Chadd if (err != 0) 185454d507aSAleksandr Rybalko goto out; 186a043e8c7SAdrian Chadd for (timeout = 100; timeout--; ) { 187e765499eSAdrian Chadd ctrl = arswitch_readreg(dev, a); 188a043e8c7SAdrian Chadd if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0) 189a043e8c7SAdrian Chadd break; 190a043e8c7SAdrian Chadd } 191a043e8c7SAdrian Chadd if (timeout < 0) 192a043e8c7SAdrian Chadd err = EIO; 193454d507aSAleksandr Rybalko out: 194a043e8c7SAdrian Chadd DEVERR(dev, err, "arswitch_writephy()=%d: phy=%d.%02x\n", phy, reg); 195454d507aSAleksandr Rybalko ARSWITCH_UNLOCK(sc); 196a043e8c7SAdrian Chadd return (err); 197a043e8c7SAdrian Chadd } 198