xref: /freebsd/sys/dev/etherswitch/arswitch/arswitch_phy.c (revision 4d846d260e2b9a3d4d0a701462568268cbfe7a5b)
1a043e8c7SAdrian Chadd /*-
2*4d846d26SWarner Losh  * SPDX-License-Identifier: BSD-2-Clause
3718cf2ccSPedro F. Giffuni  *
4a043e8c7SAdrian Chadd  * Copyright (c) 2011-2012 Stefan Bethke.
5a043e8c7SAdrian Chadd  * Copyright (c) 2012 Adrian Chadd.
6a043e8c7SAdrian Chadd  * All rights reserved.
7a043e8c7SAdrian Chadd  *
8a043e8c7SAdrian Chadd  * Redistribution and use in source and binary forms, with or without
9a043e8c7SAdrian Chadd  * modification, are permitted provided that the following conditions
10a043e8c7SAdrian Chadd  * are met:
11a043e8c7SAdrian Chadd  * 1. Redistributions of source code must retain the above copyright
12a043e8c7SAdrian Chadd  *    notice, this list of conditions and the following disclaimer.
13a043e8c7SAdrian Chadd  * 2. Redistributions in binary form must reproduce the above copyright
14a043e8c7SAdrian Chadd  *    notice, this list of conditions and the following disclaimer in the
15a043e8c7SAdrian Chadd  *    documentation and/or other materials provided with the distribution.
16a043e8c7SAdrian Chadd  *
17a043e8c7SAdrian Chadd  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18a043e8c7SAdrian Chadd  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19a043e8c7SAdrian Chadd  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20a043e8c7SAdrian Chadd  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21a043e8c7SAdrian Chadd  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22a043e8c7SAdrian Chadd  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23a043e8c7SAdrian Chadd  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24a043e8c7SAdrian Chadd  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25a043e8c7SAdrian Chadd  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26a043e8c7SAdrian Chadd  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27a043e8c7SAdrian Chadd  * SUCH DAMAGE.
28a043e8c7SAdrian Chadd  *
29a043e8c7SAdrian Chadd  * $FreeBSD$
30a043e8c7SAdrian Chadd  */
31a043e8c7SAdrian Chadd 
32a043e8c7SAdrian Chadd #include <sys/param.h>
33a043e8c7SAdrian Chadd #include <sys/bus.h>
34a043e8c7SAdrian Chadd #include <sys/errno.h>
35a043e8c7SAdrian Chadd #include <sys/kernel.h>
36104dc214SGleb Smirnoff #include <sys/lock.h>
37a043e8c7SAdrian Chadd #include <sys/module.h>
38104dc214SGleb Smirnoff #include <sys/mutex.h>
39a043e8c7SAdrian Chadd #include <sys/socket.h>
40a043e8c7SAdrian Chadd #include <sys/sockio.h>
41a043e8c7SAdrian Chadd #include <sys/sysctl.h>
42a043e8c7SAdrian Chadd #include <sys/systm.h>
43a043e8c7SAdrian Chadd 
44a043e8c7SAdrian Chadd #include <net/if.h>
45a043e8c7SAdrian Chadd #include <net/if_media.h>
46a043e8c7SAdrian Chadd 
47a043e8c7SAdrian Chadd #include <machine/bus.h>
48efce3748SRui Paulo #include <dev/iicbus/iic.h>
49a043e8c7SAdrian Chadd #include <dev/iicbus/iiconf.h>
50a043e8c7SAdrian Chadd #include <dev/iicbus/iicbus.h>
51a043e8c7SAdrian Chadd #include <dev/mii/mii.h>
52a043e8c7SAdrian Chadd #include <dev/mii/miivar.h>
5371e8eac4SAdrian Chadd #include <dev/mdio/mdio.h>
54a043e8c7SAdrian Chadd 
55a043e8c7SAdrian Chadd #include <dev/etherswitch/etherswitch.h>
56a043e8c7SAdrian Chadd 
57a043e8c7SAdrian Chadd #include <dev/etherswitch/arswitch/arswitchreg.h>
58a043e8c7SAdrian Chadd #include <dev/etherswitch/arswitch/arswitchvar.h>
59a043e8c7SAdrian Chadd 
60a043e8c7SAdrian Chadd #include <dev/etherswitch/arswitch/arswitch_reg.h>
61a043e8c7SAdrian Chadd #include <dev/etherswitch/arswitch/arswitch_phy.h>
62a043e8c7SAdrian Chadd 
63a043e8c7SAdrian Chadd #include "mdio_if.h"
64a043e8c7SAdrian Chadd #include "miibus_if.h"
65a043e8c7SAdrian Chadd #include "etherswitch_if.h"
66a043e8c7SAdrian Chadd 
67a043e8c7SAdrian Chadd /*
6878549b94SAdrian Chadd  * Access PHYs integrated into the switch by going direct
6978549b94SAdrian Chadd  * to the PHY space itself, rather than through the switch
7078549b94SAdrian Chadd  * MDIO register.
7178549b94SAdrian Chadd  */
7278549b94SAdrian Chadd int
7378549b94SAdrian Chadd arswitch_readphy_external(device_t dev, int phy, int reg)
7478549b94SAdrian Chadd {
7578549b94SAdrian Chadd 	int ret;
7678549b94SAdrian Chadd 	struct arswitch_softc *sc;
7778549b94SAdrian Chadd 
7878549b94SAdrian Chadd 	sc = device_get_softc(dev);
7978549b94SAdrian Chadd 
8078549b94SAdrian Chadd 	ARSWITCH_LOCK(sc);
8178549b94SAdrian Chadd 	ret = (MDIO_READREG(device_get_parent(dev), phy, reg));
821b334c8bSAdrian Chadd 	DPRINTF(sc, ARSWITCH_DBG_PHYIO,
831b334c8bSAdrian Chadd 	    "%s: phy=0x%08x, reg=0x%08x, ret=0x%08x\n",
841b334c8bSAdrian Chadd 	    __func__, phy, reg, ret);
8578549b94SAdrian Chadd 	ARSWITCH_UNLOCK(sc);
8678549b94SAdrian Chadd 
8778549b94SAdrian Chadd 	return (ret);
8878549b94SAdrian Chadd }
8978549b94SAdrian Chadd 
9078549b94SAdrian Chadd int
9178549b94SAdrian Chadd arswitch_writephy_external(device_t dev, int phy, int reg, int data)
9278549b94SAdrian Chadd {
9378549b94SAdrian Chadd 	struct arswitch_softc *sc;
9478549b94SAdrian Chadd 
9578549b94SAdrian Chadd 	sc = device_get_softc(dev);
9678549b94SAdrian Chadd 
9778549b94SAdrian Chadd 	ARSWITCH_LOCK(sc);
9878549b94SAdrian Chadd 	(void) MDIO_WRITEREG(device_get_parent(dev), phy,
9978549b94SAdrian Chadd 	    reg, data);
1001b334c8bSAdrian Chadd 	DPRINTF(sc, ARSWITCH_DBG_PHYIO,
1011b334c8bSAdrian Chadd 	    "%s: phy=0x%08x, reg=0x%08x, data=0x%08x\n",
1021b334c8bSAdrian Chadd 	    __func__, phy, reg, data);
10378549b94SAdrian Chadd 	ARSWITCH_UNLOCK(sc);
10478549b94SAdrian Chadd 
10578549b94SAdrian Chadd 	return (0);
10678549b94SAdrian Chadd }
10778549b94SAdrian Chadd 
10878549b94SAdrian Chadd /*
10978549b94SAdrian Chadd  * Access PHYs integrated into the switch chip through the switch's MDIO
110a043e8c7SAdrian Chadd  * control register.
111a043e8c7SAdrian Chadd  */
112a043e8c7SAdrian Chadd int
11378549b94SAdrian Chadd arswitch_readphy_internal(device_t dev, int phy, int reg)
114a043e8c7SAdrian Chadd {
115454d507aSAleksandr Rybalko 	struct arswitch_softc *sc;
116a043e8c7SAdrian Chadd 	uint32_t data = 0, ctrl;
117a043e8c7SAdrian Chadd 	int err, timeout;
118e765499eSAdrian Chadd 	uint32_t a;
119a043e8c7SAdrian Chadd 
120454d507aSAleksandr Rybalko 	sc = device_get_softc(dev);
121454d507aSAleksandr Rybalko 	ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
122454d507aSAleksandr Rybalko 
123a043e8c7SAdrian Chadd 	if (phy < 0 || phy >= 32)
124a043e8c7SAdrian Chadd 		return (ENXIO);
125a043e8c7SAdrian Chadd 	if (reg < 0 || reg >= 32)
126a043e8c7SAdrian Chadd 		return (ENXIO);
127454d507aSAleksandr Rybalko 
128e765499eSAdrian Chadd 	if (AR8X16_IS_SWITCH(sc, AR8327))
129e765499eSAdrian Chadd 		a = AR8327_REG_MDIO_CTRL;
130e765499eSAdrian Chadd 	else
131e765499eSAdrian Chadd 		a = AR8X16_REG_MDIO_CTRL;
132e765499eSAdrian Chadd 
133454d507aSAleksandr Rybalko 	ARSWITCH_LOCK(sc);
134e765499eSAdrian Chadd 	err = arswitch_writereg_msb(dev, a,
135a043e8c7SAdrian Chadd 	    AR8X16_MDIO_CTRL_BUSY | AR8X16_MDIO_CTRL_MASTER_EN |
136a043e8c7SAdrian Chadd 	    AR8X16_MDIO_CTRL_CMD_READ |
137a043e8c7SAdrian Chadd 	    (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |
138a043e8c7SAdrian Chadd 	    (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT));
139a043e8c7SAdrian Chadd 	DEVERR(dev, err, "arswitch_readphy()=%d: phy=%d.%02x\n", phy, reg);
140a043e8c7SAdrian Chadd 	if (err != 0)
141454d507aSAleksandr Rybalko 		goto fail;
142a043e8c7SAdrian Chadd 	for (timeout = 100; timeout--; ) {
143e765499eSAdrian Chadd 		ctrl = arswitch_readreg_msb(dev, a);
144a043e8c7SAdrian Chadd 		if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0)
145a043e8c7SAdrian Chadd 			break;
146a043e8c7SAdrian Chadd 	}
14778549b94SAdrian Chadd 	if (timeout < 0) {
1481b334c8bSAdrian Chadd 		DPRINTF(sc, ARSWITCH_DBG_ANY,
1491b334c8bSAdrian Chadd 		    "arswitch_readphy(): phy=%d.%02x; timeout=%d\n",
1501b334c8bSAdrian Chadd 		    phy, reg, timeout);
151454d507aSAleksandr Rybalko 		goto fail;
15278549b94SAdrian Chadd 	}
153e765499eSAdrian Chadd 	data = arswitch_readreg_lsb(dev, a) &
154a043e8c7SAdrian Chadd 	    AR8X16_MDIO_CTRL_DATA_MASK;
155454d507aSAleksandr Rybalko 	ARSWITCH_UNLOCK(sc);
156e08d8565SAdrian Chadd 
157e08d8565SAdrian Chadd 	DPRINTF(sc, ARSWITCH_DBG_PHYIO,
158e08d8565SAdrian Chadd 	    "%s: phy=0x%08x, reg=0x%08x, ret=0x%08x\n",
159e08d8565SAdrian Chadd 	    __func__, phy, reg, data);
160e08d8565SAdrian Chadd 
161a043e8c7SAdrian Chadd 	return (data);
162454d507aSAleksandr Rybalko 
163454d507aSAleksandr Rybalko fail:
164454d507aSAleksandr Rybalko 	ARSWITCH_UNLOCK(sc);
165e08d8565SAdrian Chadd 
166e08d8565SAdrian Chadd 	DPRINTF(sc, ARSWITCH_DBG_PHYIO,
167e08d8565SAdrian Chadd 	    "%s: phy=0x%08x, reg=0x%08x, fail; err=%d\n",
168e08d8565SAdrian Chadd 	    __func__, phy, reg, err);
169e08d8565SAdrian Chadd 
170454d507aSAleksandr Rybalko 	return (-1);
171a043e8c7SAdrian Chadd }
172a043e8c7SAdrian Chadd 
173a043e8c7SAdrian Chadd int
17478549b94SAdrian Chadd arswitch_writephy_internal(device_t dev, int phy, int reg, int data)
175a043e8c7SAdrian Chadd {
176454d507aSAleksandr Rybalko 	struct arswitch_softc *sc;
177a043e8c7SAdrian Chadd 	uint32_t ctrl;
178a043e8c7SAdrian Chadd 	int err, timeout;
179e765499eSAdrian Chadd 	uint32_t a;
180a043e8c7SAdrian Chadd 
181454d507aSAleksandr Rybalko 	sc = device_get_softc(dev);
182454d507aSAleksandr Rybalko 	ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
183454d507aSAleksandr Rybalko 
184a043e8c7SAdrian Chadd 	if (reg < 0 || reg >= 32)
185a043e8c7SAdrian Chadd 		return (ENXIO);
186454d507aSAleksandr Rybalko 
187e765499eSAdrian Chadd 	if (AR8X16_IS_SWITCH(sc, AR8327))
188e765499eSAdrian Chadd 		a = AR8327_REG_MDIO_CTRL;
189e765499eSAdrian Chadd 	else
190e765499eSAdrian Chadd 		a = AR8X16_REG_MDIO_CTRL;
191e765499eSAdrian Chadd 
192454d507aSAleksandr Rybalko 	ARSWITCH_LOCK(sc);
193e765499eSAdrian Chadd 	err = arswitch_writereg(dev, a,
194a043e8c7SAdrian Chadd 	    AR8X16_MDIO_CTRL_BUSY |
195a043e8c7SAdrian Chadd 	    AR8X16_MDIO_CTRL_MASTER_EN |
196a043e8c7SAdrian Chadd 	    AR8X16_MDIO_CTRL_CMD_WRITE |
197a043e8c7SAdrian Chadd 	    (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |
1989604b6acSLuiz Otavio O Souza 	    (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT) |
1999604b6acSLuiz Otavio O Souza 	    (data & AR8X16_MDIO_CTRL_DATA_MASK));
200a043e8c7SAdrian Chadd 	if (err != 0)
201454d507aSAleksandr Rybalko 		goto out;
202a043e8c7SAdrian Chadd 	for (timeout = 100; timeout--; ) {
203e765499eSAdrian Chadd 		ctrl = arswitch_readreg(dev, a);
204a043e8c7SAdrian Chadd 		if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0)
205a043e8c7SAdrian Chadd 			break;
206a043e8c7SAdrian Chadd 	}
207a043e8c7SAdrian Chadd 	if (timeout < 0)
208a043e8c7SAdrian Chadd 		err = EIO;
209e08d8565SAdrian Chadd 
210e08d8565SAdrian Chadd 	DPRINTF(sc, ARSWITCH_DBG_PHYIO,
211e08d8565SAdrian Chadd 	    "%s: phy=0x%08x, reg=0x%08x, data=0x%08x, err=%d\n",
212e08d8565SAdrian Chadd 	    __func__, phy, reg, data, err);
213e08d8565SAdrian Chadd 
214454d507aSAleksandr Rybalko out:
215a043e8c7SAdrian Chadd 	DEVERR(dev, err, "arswitch_writephy()=%d: phy=%d.%02x\n", phy, reg);
216454d507aSAleksandr Rybalko 	ARSWITCH_UNLOCK(sc);
217a043e8c7SAdrian Chadd 	return (err);
218a043e8c7SAdrian Chadd }
219