1*7a40b8a8SJustin Hibbits /* 2*7a40b8a8SJustin Hibbits * Copyright (c) 2026 Justin Hibbits 3fd8d34ceSJustin Hibbits * Copyright (c) 2011-2012 Semihalf. 4fd8d34ceSJustin Hibbits * 5*7a40b8a8SJustin Hibbits * SPDX-License-Identifier: BSD-2-Clause 6fd8d34ceSJustin Hibbits */ 7fd8d34ceSJustin Hibbits 8fd8d34ceSJustin Hibbits #ifndef IF_MEMAC_H_ 9fd8d34ceSJustin Hibbits #define IF_MEMAC_H_ 10fd8d34ceSJustin Hibbits 11fd8d34ceSJustin Hibbits /** 12fd8d34ceSJustin Hibbits * @group dTSEC common API. 13fd8d34ceSJustin Hibbits * @{ 14fd8d34ceSJustin Hibbits */ 15fd8d34ceSJustin Hibbits #define MEMAC_MODE_REGULAR 0 16fd8d34ceSJustin Hibbits 17fd8d34ceSJustin Hibbits #define MEMAC_LOCK(sc) mtx_lock(&(sc)->sc_base.sc_lock) 18fd8d34ceSJustin Hibbits #define MEMAC_UNLOCK(sc) mtx_unlock(&(sc)->sc_base.sc_lock) 19fd8d34ceSJustin Hibbits #define MEMAC_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_base.sc_lock, MA_OWNED) 20fd8d34ceSJustin Hibbits #define MEMAC_MII_LOCK(sc) mtx_lock(&(sc)->sc_base.sc_mii_lock) 21fd8d34ceSJustin Hibbits #define MEMAC_MII_UNLOCK(sc) mtx_unlock(&(sc)->sc_base.sc_mii_lock) 22fd8d34ceSJustin Hibbits 23fd8d34ceSJustin Hibbits enum eth_dev_type { 24fd8d34ceSJustin Hibbits ETH_MEMAC = 0x1, 25fd8d34ceSJustin Hibbits ETH_10GSEC = 0x2 26fd8d34ceSJustin Hibbits }; 27fd8d34ceSJustin Hibbits 28fd8d34ceSJustin Hibbits struct memac_softc { 29fd8d34ceSJustin Hibbits struct dpaa_eth_softc sc_base; 30fd8d34ceSJustin Hibbits bool sc_fixed_link; 31fd8d34ceSJustin Hibbits }; 32fd8d34ceSJustin Hibbits /** @} */ 33fd8d34ceSJustin Hibbits 34fd8d34ceSJustin Hibbits 35fd8d34ceSJustin Hibbits /** 36fd8d34ceSJustin Hibbits * @group dTSEC bus interface. 37fd8d34ceSJustin Hibbits * @{ 38fd8d34ceSJustin Hibbits */ 39fd8d34ceSJustin Hibbits int memac_attach(device_t dev); 40fd8d34ceSJustin Hibbits int memac_detach(device_t dev); 41fd8d34ceSJustin Hibbits int memac_suspend(device_t dev); 42fd8d34ceSJustin Hibbits int memac_resume(device_t dev); 43fd8d34ceSJustin Hibbits int memac_shutdown(device_t dev); 44fd8d34ceSJustin Hibbits int memac_miibus_readreg(device_t dev, int phy, int reg); 45fd8d34ceSJustin Hibbits int memac_miibus_writereg(device_t dev, int phy, int reg, 46fd8d34ceSJustin Hibbits int value); 47fd8d34ceSJustin Hibbits void memac_miibus_statchg(device_t dev); 48fd8d34ceSJustin Hibbits /** @} */ 49fd8d34ceSJustin Hibbits 50fd8d34ceSJustin Hibbits #endif /* IF_MEMAC_H_ */ 51