1 /* 2 * Copyright (c) 2026 Justin Hibbits 3 * Copyright (c) 2011-2012 Semihalf. 4 * 5 * SPDX-License-Identifier: BSD-2-Clause 6 */ 7 8 #ifndef IF_MEMAC_H_ 9 #define IF_MEMAC_H_ 10 11 /** 12 * @group dTSEC common API. 13 * @{ 14 */ 15 #define MEMAC_MODE_REGULAR 0 16 17 #define MEMAC_LOCK(sc) mtx_lock(&(sc)->sc_base.sc_lock) 18 #define MEMAC_UNLOCK(sc) mtx_unlock(&(sc)->sc_base.sc_lock) 19 #define MEMAC_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_base.sc_lock, MA_OWNED) 20 #define MEMAC_MII_LOCK(sc) mtx_lock(&(sc)->sc_base.sc_mii_lock) 21 #define MEMAC_MII_UNLOCK(sc) mtx_unlock(&(sc)->sc_base.sc_mii_lock) 22 23 enum eth_dev_type { 24 ETH_MEMAC = 0x1, 25 ETH_10GSEC = 0x2 26 }; 27 28 struct memac_softc { 29 struct dpaa_eth_softc sc_base; 30 bool sc_fixed_link; 31 }; 32 /** @} */ 33 34 35 /** 36 * @group dTSEC bus interface. 37 * @{ 38 */ 39 int memac_attach(device_t dev); 40 int memac_detach(device_t dev); 41 int memac_suspend(device_t dev); 42 int memac_resume(device_t dev); 43 int memac_shutdown(device_t dev); 44 int memac_miibus_readreg(device_t dev, int phy, int reg); 45 int memac_miibus_writereg(device_t dev, int phy, int reg, 46 int value); 47 void memac_miibus_statchg(device_t dev); 48 /** @} */ 49 50 #endif /* IF_MEMAC_H_ */ 51