1 /*- 2 * Copyright (c) 2012 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifndef DPAA_ETH_H_ 28 #define DPAA_ETH_H_ 29 30 /* * TX csum-offload hwassist mask for dTSEC and mEMAC. */ 31 #define DPAA_CSUM_TX_OFFLOAD \ 32 (CSUM_IP | CSUM_DELAY_DATA | CSUM_DELAY_DATA_IPV6) 33 34 struct dpaa_pcpu_cnt { 35 u_int cnt; 36 } __aligned(CACHE_LINE_SIZE); 37 38 struct dpaa_eth_softc { 39 /* XXX MII bus requires that struct ifnet is first!!! */ 40 if_t sc_ifnet; 41 42 device_t sc_dev; 43 struct resource *sc_mem; 44 struct mtx sc_lock; 45 46 int sc_mac_enet_mode; 47 48 /* RX Pool */ 49 struct bman_pool *sc_rx_pool; 50 uint8_t sc_rx_bpid; 51 uma_zone_t sc_rx_zone; 52 char sc_rx_zname[64]; 53 struct dpaa_pcpu_cnt *sc_rx_pool_check_cnt; /* per-CPU */ 54 55 /* RX Frame Queue */ 56 struct qman_fq *sc_rx_fq; 57 uint32_t sc_rx_fqid; 58 59 /* TX Frame Queue */ 60 struct qman_fq *sc_tx_fq; 61 volatile u_int sc_tx_fq_full; 62 u_int sc_tx_queue_check_cnt; 63 struct qman_fq *sc_tx_conf_fq; 64 uint32_t sc_tx_conf_fqid; 65 u_int sc_tx_conf_check_cnt; 66 67 /* Methods */ 68 int (*sc_port_rx_init) 69 (struct dpaa_eth_softc *sc, int unit); 70 int (*sc_port_tx_init) 71 (struct dpaa_eth_softc *sc, int unit); 72 void (*sc_start_locked) 73 (struct dpaa_eth_softc *sc); 74 75 /* dTSEC data */ 76 uint8_t sc_eth_id; /* Ethernet ID within its frame manager */ 77 uintptr_t sc_mac_mem_offset; 78 int sc_mac_mdio_irq; 79 uint8_t sc_mac_addr[6]; 80 int sc_port_rx_hw_id; 81 int sc_port_tx_hw_id; 82 uint32_t sc_port_tx_qman_chan; 83 int sc_phy_addr; 84 bool sc_hidden; 85 device_t sc_mdio; 86 int sc_rev_major; 87 int sc_rev_minor; 88 89 device_t sc_rx_port; 90 device_t sc_tx_port; 91 92 int sc_rx_channel; 93 94 /* MII data */ 95 struct mii_data *sc_mii; 96 device_t sc_mii_dev; 97 struct mtx sc_mii_lock; 98 99 struct callout sc_tick_callout; 100 101 /* Frame Info Zone */ 102 uma_zone_t sc_fi_zone; 103 char sc_fi_zname[64]; 104 }; 105 106 /** 107 * @group dTSEC Regular Mode API. 108 * @{ 109 */ 110 int dpaa_eth_fm_port_rx_init(struct dpaa_eth_softc *sc); 111 int dpaa_eth_fm_port_tx_init(struct dpaa_eth_softc *sc); 112 113 void dpaa_eth_if_start_locked(struct dpaa_eth_softc *sc); 114 115 int dpaa_eth_pool_rx_init(struct dpaa_eth_softc *sc); 116 void dpaa_eth_pool_rx_free(struct dpaa_eth_softc *sc); 117 118 int dpaa_eth_fi_pool_init(struct dpaa_eth_softc *sc); 119 void dpaa_eth_fi_pool_free(struct dpaa_eth_softc *sc); 120 121 int dpaa_eth_fq_rx_init(struct dpaa_eth_softc *sc); 122 int dpaa_eth_fq_tx_init(struct dpaa_eth_softc *sc); 123 void dpaa_eth_fq_rx_free(struct dpaa_eth_softc *sc); 124 void dpaa_eth_fq_tx_free(struct dpaa_eth_softc *sc); 125 /** @} */ 126 127 #endif /* DPAA_ETH_H_ */ 128