1 /*- 2 * Copyright (c) 2012 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifndef DPAA_ETH_H_ 28 #define DPAA_ETH_H_ 29 30 struct dpaa_eth_softc { 31 /* XXX MII bus requires that struct ifnet is first!!! */ 32 if_t sc_ifnet; 33 34 device_t sc_dev; 35 struct resource *sc_mem; 36 struct mtx sc_lock; 37 38 int sc_mac_enet_mode; 39 40 /* RX Pool */ 41 struct bman_pool *sc_rx_pool; 42 uint8_t sc_rx_bpid; 43 uma_zone_t sc_rx_zone; 44 char sc_rx_zname[64]; 45 46 /* RX Frame Queue */ 47 struct qman_fq *sc_rx_fq; 48 uint32_t sc_rx_fqid; 49 50 /* TX Frame Queue */ 51 struct qman_fq *sc_tx_fq; 52 bool sc_tx_fq_full; 53 struct qman_fq *sc_tx_conf_fq; 54 uint32_t sc_tx_conf_fqid; 55 56 /* Methods */ 57 int (*sc_port_rx_init) 58 (struct dpaa_eth_softc *sc, int unit); 59 int (*sc_port_tx_init) 60 (struct dpaa_eth_softc *sc, int unit); 61 void (*sc_start_locked) 62 (struct dpaa_eth_softc *sc); 63 64 /* dTSEC data */ 65 uint8_t sc_eth_id; /* Ethernet ID within its frame manager */ 66 uintptr_t sc_mac_mem_offset; 67 int sc_mac_mdio_irq; 68 uint8_t sc_mac_addr[6]; 69 int sc_port_rx_hw_id; 70 int sc_port_tx_hw_id; 71 uint32_t sc_port_tx_qman_chan; 72 int sc_phy_addr; 73 bool sc_hidden; 74 device_t sc_mdio; 75 int sc_rev_major; 76 int sc_rev_minor; 77 78 device_t sc_rx_port; 79 device_t sc_tx_port; 80 81 int sc_rx_channel; 82 83 /* MII data */ 84 struct mii_data *sc_mii; 85 device_t sc_mii_dev; 86 struct mtx sc_mii_lock; 87 88 struct callout sc_tick_callout; 89 90 /* Frame Info Zone */ 91 uma_zone_t sc_fi_zone; 92 char sc_fi_zname[64]; 93 }; 94 95 /** 96 * @group dTSEC Regular Mode API. 97 * @{ 98 */ 99 int dpaa_eth_fm_port_rx_init(struct dpaa_eth_softc *sc); 100 int dpaa_eth_fm_port_tx_init(struct dpaa_eth_softc *sc); 101 102 void dpaa_eth_if_start_locked(struct dpaa_eth_softc *sc); 103 104 int dpaa_eth_pool_rx_init(struct dpaa_eth_softc *sc); 105 void dpaa_eth_pool_rx_free(struct dpaa_eth_softc *sc); 106 107 int dpaa_eth_fi_pool_init(struct dpaa_eth_softc *sc); 108 void dpaa_eth_fi_pool_free(struct dpaa_eth_softc *sc); 109 110 int dpaa_eth_fq_rx_init(struct dpaa_eth_softc *sc); 111 int dpaa_eth_fq_tx_init(struct dpaa_eth_softc *sc); 112 void dpaa_eth_fq_rx_free(struct dpaa_eth_softc *sc); 113 void dpaa_eth_fq_tx_free(struct dpaa_eth_softc *sc); 114 /** @} */ 115 116 #endif /* DPAA_ETH_H_ */ 117