1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * 21143 and clone common register definitions. 37 */ 38 39 #define DC_BUSCTL 0x00 /* bus control */ 40 #define DC_TXSTART 0x08 /* tx start demand */ 41 #define DC_RXSTART 0x10 /* rx start demand */ 42 #define DC_RXADDR 0x18 /* rx descriptor list start addr */ 43 #define DC_TXADDR 0x20 /* tx descriptor list start addr */ 44 #define DC_ISR 0x28 /* interrupt status register */ 45 #define DC_NETCFG 0x30 /* network config register */ 46 #define DC_IMR 0x38 /* interrupt mask */ 47 #define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ 48 #define DC_SIO 0x48 /* MII and ROM/EEPROM access */ 49 #define DC_ROM 0x50 /* ROM programming address */ 50 #define DC_TIMER 0x58 /* general timer */ 51 #define DC_10BTSTAT 0x60 /* SIA status */ 52 #define DC_SIARESET 0x68 /* SIA connectivity */ 53 #define DC_10BTCTRL 0x70 /* SIA transmit and receive */ 54 #define DC_WATCHDOG 0x78 /* SIA and general purpose port */ 55 #define DC_SIAGP 0x78 /* SIA and general purpose port (X3201) */ 56 57 /* 58 * There are two general 'types' of MX chips that we need to be 59 * concerned with. One is the original 98713, which has its internal 60 * NWAY support controlled via the MDIO bits in the serial I/O 61 * register. The other is everything else (from the 98713A on up), 62 * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, 63 * just like the 21143. This type setting also governs which of the 64 * 'magic' numbers we write to CSR16. The PNIC II falls into the 65 * 98713A/98715/98715A/98725 category. 66 */ 67 #define DC_TYPE_98713 0x1 68 #define DC_TYPE_98713A 0x2 69 #define DC_TYPE_987x5 0x3 70 71 /* Other type of supported chips. */ 72 #define DC_TYPE_21143 0x4 /* Intel 21143 */ 73 #define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ 74 #define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ 75 #define DC_TYPE_AN985 0x7 /* ADMtek AN985 Centaur */ 76 #define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ 77 #define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ 78 #define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ 79 #define DC_TYPE_XIRCOM 0xB /* Xircom X3201 */ 80 81 #define DC_IS_MACRONIX(x) \ 82 (x->dc_type == DC_TYPE_98713 || \ 83 x->dc_type == DC_TYPE_98713A || \ 84 x->dc_type == DC_TYPE_987x5) 85 86 #define DC_IS_ADMTEK(x) \ 87 (x->dc_type == DC_TYPE_AL981 || \ 88 x->dc_type == DC_TYPE_AN985) 89 90 #define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) 91 #define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) 92 #define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) 93 #define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN985) 94 #define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) 95 #define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) 96 #define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) 97 #define DC_IS_XIRCOM(x) (x->dc_type == DC_TYPE_XIRCOM) 98 99 /* MII/symbol mode port types */ 100 #define DC_PMODE_MII 0x1 101 #define DC_PMODE_SYM 0x2 102 #define DC_PMODE_SIA 0x3 103 104 /* 105 * Bus control bits. 106 */ 107 #define DC_BUSCTL_RESET 0x00000001 108 #define DC_BUSCTL_ARBITRATION 0x00000002 109 #define DC_BUSCTL_SKIPLEN 0x0000007C 110 #define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 111 #define DC_BUSCTL_BURSTLEN 0x00003F00 112 #define DC_BUSCTL_CACHEALIGN 0x0000C000 113 #define DC_BUSCTL_TXPOLL 0x000E0000 114 #define DC_BUSCTL_DBO 0x00100000 115 #define DC_BUSCTL_MRME 0x00200000 116 #define DC_BUSCTL_MRLE 0x00800000 117 #define DC_BUSCTL_MWIE 0x01000000 118 #define DC_BUSCTL_ONNOW_ENB 0x04000000 119 120 #define DC_SKIPLEN_1LONG 0x00000004 121 #define DC_SKIPLEN_2LONG 0x00000008 122 #define DC_SKIPLEN_3LONG 0x00000010 123 #define DC_SKIPLEN_4LONG 0x00000020 124 #define DC_SKIPLEN_5LONG 0x00000040 125 126 #define DC_CACHEALIGN_NONE 0x00000000 127 #define DC_CACHEALIGN_8LONG 0x00004000 128 #define DC_CACHEALIGN_16LONG 0x00008000 129 #define DC_CACHEALIGN_32LONG 0x0000C000 130 131 #define DC_BURSTLEN_USECA 0x00000000 132 #define DC_BURSTLEN_1LONG 0x00000100 133 #define DC_BURSTLEN_2LONG 0x00000200 134 #define DC_BURSTLEN_4LONG 0x00000400 135 #define DC_BURSTLEN_8LONG 0x00000800 136 #define DC_BURSTLEN_16LONG 0x00001000 137 #define DC_BURSTLEN_32LONG 0x00002000 138 139 #define DC_TXPOLL_OFF 0x00000000 140 #define DC_TXPOLL_1 0x00020000 141 #define DC_TXPOLL_2 0x00040000 142 #define DC_TXPOLL_3 0x00060000 143 #define DC_TXPOLL_4 0x00080000 144 #define DC_TXPOLL_5 0x000A0000 145 #define DC_TXPOLL_6 0x000C0000 146 #define DC_TXPOLL_7 0x000E0000 147 148 /* 149 * Interrupt status bits. 150 */ 151 #define DC_ISR_TX_OK 0x00000001 152 #define DC_ISR_TX_IDLE 0x00000002 153 #define DC_ISR_TX_NOBUF 0x00000004 154 #define DC_ISR_TX_JABBERTIMEO 0x00000008 155 #define DC_ISR_LINKGOOD 0x00000010 156 #define DC_ISR_TX_UNDERRUN 0x00000020 157 #define DC_ISR_RX_OK 0x00000040 158 #define DC_ISR_RX_NOBUF 0x00000080 159 #define DC_ISR_RX_READ 0x00000100 160 #define DC_ISR_RX_WATDOGTIMEO 0x00000200 161 #define DC_ISR_TX_EARLY 0x00000400 162 #define DC_ISR_TIMER_EXPIRED 0x00000800 163 #define DC_ISR_LINKFAIL 0x00001000 164 #define DC_ISR_BUS_ERR 0x00002000 165 #define DC_ISR_RX_EARLY 0x00004000 166 #define DC_ISR_ABNORMAL 0x00008000 167 #define DC_ISR_NORMAL 0x00010000 168 #define DC_ISR_RX_STATE 0x000E0000 169 #define DC_ISR_TX_STATE 0x00700000 170 #define DC_ISR_BUSERRTYPE 0x03800000 171 #define DC_ISR_100MBPSLINK 0x08000000 172 #define DC_ISR_MAGICKPACK 0x10000000 173 174 #define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ 175 #define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ 176 #define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ 177 #define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ 178 #define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ 179 #define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ 180 #define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ 181 #define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ 182 183 #define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ 184 #define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ 185 #define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ 186 #define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ 187 #define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ 188 #define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ 189 #define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ 190 #define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ 191 192 /* 193 * Network config bits. 194 */ 195 #define DC_NETCFG_RX_HASHPERF 0x00000001 196 #define DC_NETCFG_RX_ON 0x00000002 197 #define DC_NETCFG_RX_HASHONLY 0x00000004 198 #define DC_NETCFG_RX_BADFRAMES 0x00000008 199 #define DC_NETCFG_RX_INVFILT 0x00000010 200 #define DC_NETCFG_BACKOFFCNT 0x00000020 201 #define DC_NETCFG_RX_PROMISC 0x00000040 202 #define DC_NETCFG_RX_ALLMULTI 0x00000080 203 #define DC_NETCFG_FULLDUPLEX 0x00000200 204 #define DC_NETCFG_LOOPBACK 0x00000C00 205 #define DC_NETCFG_FORCECOLL 0x00001000 206 #define DC_NETCFG_TX_ON 0x00002000 207 #define DC_NETCFG_TX_THRESH 0x0000C000 208 #define DC_NETCFG_TX_BACKOFF 0x00020000 209 #define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ 210 #define DC_NETCFG_HEARTBEAT 0x00080000 211 #define DC_NETCFG_STORENFWD 0x00200000 212 #define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ 213 #define DC_NETCFG_PCS 0x00800000 214 #define DC_NETCFG_SCRAMBLER 0x01000000 215 #define DC_NETCFG_NO_RXCRC 0x02000000 216 #define DC_NETCFG_RX_ALL 0x40000000 217 #define DC_NETCFG_CAPEFFECT 0x80000000 218 219 #define DC_OPMODE_NORM 0x00000000 220 #define DC_OPMODE_INTLOOP 0x00000400 221 #define DC_OPMODE_EXTLOOP 0x00000800 222 223 #define DC_TXTHRESH_72BYTES 0x00000000 224 #define DC_TXTHRESH_96BYTES 0x00004000 225 #define DC_TXTHRESH_128BYTES 0x00008000 226 #define DC_TXTHRESH_160BYTES 0x0000C000 227 228 229 /* 230 * Interrupt mask bits. 231 */ 232 #define DC_IMR_TX_OK 0x00000001 233 #define DC_IMR_TX_IDLE 0x00000002 234 #define DC_IMR_TX_NOBUF 0x00000004 235 #define DC_IMR_TX_JABBERTIMEO 0x00000008 236 #define DC_IMR_LINKGOOD 0x00000010 237 #define DC_IMR_TX_UNDERRUN 0x00000020 238 #define DC_IMR_RX_OK 0x00000040 239 #define DC_IMR_RX_NOBUF 0x00000080 240 #define DC_IMR_RX_READ 0x00000100 241 #define DC_IMR_RX_WATDOGTIMEO 0x00000200 242 #define DC_IMR_TX_EARLY 0x00000400 243 #define DC_IMR_TIMER_EXPIRED 0x00000800 244 #define DC_IMR_LINKFAIL 0x00001000 245 #define DC_IMR_BUS_ERR 0x00002000 246 #define DC_IMR_RX_EARLY 0x00004000 247 #define DC_IMR_ABNORMAL 0x00008000 248 #define DC_IMR_NORMAL 0x00010000 249 #define DC_IMR_100MBPSLINK 0x08000000 250 #define DC_IMR_MAGICKPACK 0x10000000 251 252 #define DC_INTRS \ 253 (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ 254 DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ 255 DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) 256 /* 257 * Serial I/O (EEPROM/ROM) bits. 258 */ 259 #define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ 260 #define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ 261 #define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ 262 #define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ 263 #define DC_SIO_ROMDATA4 0x00000010 264 #define DC_SIO_ROMDATA5 0x00000020 265 #define DC_SIO_ROMDATA6 0x00000040 266 #define DC_SIO_ROMDATA7 0x00000080 267 #define DC_SIO_EESEL 0x00000800 268 #define DC_SIO_ROMSEL 0x00001000 269 #define DC_SIO_ROMCTL_WRITE 0x00002000 270 #define DC_SIO_ROMCTL_READ 0x00004000 271 #define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ 272 #define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ 273 #define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ 274 #define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ 275 276 #define DC_EECMD_WRITE 0x140 277 #define DC_EECMD_READ 0x180 278 #define DC_EECMD_ERASE 0x1c0 279 280 #define DC_EE_NODEADDR_OFFSET 0x70 281 #define DC_EE_NODEADDR 10 282 283 /* 284 * General purpose timer register 285 */ 286 #define DC_TIMER_VALUE 0x0000FFFF 287 #define DC_TIMER_CONTINUOUS 0x00010000 288 289 /* 290 * 10baseT status register 291 */ 292 #define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ 293 #define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ 294 #define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ 295 #define DC_TSTAT_AUTOPOLARITY 0x00000008 296 #define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ 297 #define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ 298 #define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ 299 #define DC_TSTAT_REMFAULT 0x00000800 300 #define DC_TSTAT_ANEGSTAT 0x00007000 301 #define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ 302 #define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ 303 304 #define DC_ASTAT_DISABLE 0x00000000 305 #define DC_ASTAT_TXDISABLE 0x00001000 306 #define DC_ASTAT_ABDETECT 0x00002000 307 #define DC_ASTAT_ACKDETECT 0x00003000 308 #define DC_ASTAT_CMPACKDETECT 0x00004000 309 #define DC_ASTAT_AUTONEGCMP 0x00005000 310 #define DC_ASTAT_LINKCHECK 0x00006000 311 312 /* 313 * PHY reset register 314 */ 315 #define DC_SIA_RESET 0x00000001 316 #define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ 317 318 /* 319 * 10baseT control register 320 */ 321 #define DC_TCTL_ENCODER_ENB 0x00000001 322 #define DC_TCTL_LOOPBACK 0x00000002 323 #define DC_TCTL_DRIVER_ENB 0x00000004 324 #define DC_TCTL_LNKPULSE_ENB 0x00000008 325 #define DC_TCTL_HALFDUPLEX 0x00000040 326 #define DC_TCTL_AUTONEGENBL 0x00000080 327 #define DC_TCTL_RX_SQUELCH 0x00000100 328 #define DC_TCTL_COLL_SQUELCH 0x00000200 329 #define DC_TCTL_COLL_DETECT 0x00000400 330 #define DC_TCTL_SQE_ENB 0x00000800 331 #define DC_TCTL_LINKTEST 0x00001000 332 #define DC_TCTL_AUTOPOLARITY 0x00002000 333 #define DC_TCTL_SET_POL_PLUS 0x00004000 334 #define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ 335 #define DC_TCTL_100BTXHALF 0x00010000 336 #define DC_TCTL_100BTXFULL 0x00020000 337 #define DC_TCTL_100BT4 0x00040000 338 339 /* 340 * Watchdog timer register 341 */ 342 #define DC_WDOG_JABBERDIS 0x00000001 343 #define DC_WDOG_HOSTUNJAB 0x00000002 344 #define DC_WDOG_JABBERCLK 0x00000004 345 #define DC_WDOG_RXWDOGDIS 0x00000010 346 #define DC_WDOG_RXWDOGCLK 0x00000020 347 #define DC_WDOG_MUSTBEZERO 0x00000100 348 #define DC_WDOG_AUIBNC 0x00100000 349 #define DC_WDOG_ACTIVITY 0x00200000 350 #define DC_WDOG_RX_MATCH 0x00400000 351 #define DC_WDOG_LINK 0x00800000 352 #define DC_WDOG_CTLWREN 0x08000000 353 354 /* 355 * SIA and General Purpose Port register (X3201) 356 */ 357 #define DC_SIAGP_RXMATCH 0x40000000 358 #define DC_SIAGP_INT1 0x20000000 359 #define DC_SIAGP_INT0 0x10000000 360 #define DC_SIAGP_WRITE_EN 0x08000000 361 #define DC_SIAGP_RXMATCH_EN 0x04000000 362 #define DC_SIAGP_INT1_EN 0x02000000 363 #define DC_SIAGP_INT0_EN 0x01000000 364 #define DC_SIAGP_LED3 0x00800000 365 #define DC_SIAGP_LED2 0x00400000 366 #define DC_SIAGP_LED1 0x00200000 367 #define DC_SIAGP_LED0 0x00100000 368 #define DC_SIAGP_MD_GP3_OUTPUT 0x00080000 369 #define DC_SIAGP_MD_GP2_OUTPUT 0x00040000 370 #define DC_SIAGP_MD_GP1_OUTPUT 0x00020000 371 #define DC_SIAGP_MD_GP0_OUTPUT 0x00010000 372 373 /* 374 * Size of a setup frame. 375 */ 376 #define DC_SFRAME_LEN 192 377 378 /* 379 * 21x4x TX/RX list structure. 380 */ 381 382 struct dc_desc { 383 u_int32_t dc_status; 384 u_int32_t dc_ctl; 385 u_int32_t dc_ptr1; 386 u_int32_t dc_ptr2; 387 }; 388 389 #define dc_data dc_ptr1 390 #define dc_next dc_ptr2 391 392 #define DC_RXSTAT_FIFOOFLOW 0x00000001 393 #define DC_RXSTAT_CRCERR 0x00000002 394 #define DC_RXSTAT_DRIBBLE 0x00000004 395 #define DC_RXSTAT_WATCHDOG 0x00000010 396 #define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ 397 #define DC_RXSTAT_COLLSEEN 0x00000040 398 #define DC_RXSTAT_GIANT 0x00000080 399 #define DC_RXSTAT_LASTFRAG 0x00000100 400 #define DC_RXSTAT_FIRSTFRAG 0x00000200 401 #define DC_RXSTAT_MULTICAST 0x00000400 402 #define DC_RXSTAT_RUNT 0x00000800 403 #define DC_RXSTAT_RXTYPE 0x00003000 404 #define DC_RXSTAT_RXERR 0x00008000 405 #define DC_RXSTAT_RXLEN 0x3FFF0000 406 #define DC_RXSTAT_OWN 0x80000000 407 408 #define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) 409 #define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) 410 411 #define DC_RXCTL_BUFLEN1 0x00000FFF 412 #define DC_RXCTL_BUFLEN2 0x00FFF000 413 #define DC_RXCTL_RLINK 0x01000000 414 #define DC_RXCTL_RLAST 0x02000000 415 416 #define DC_TXSTAT_DEFER 0x00000001 417 #define DC_TXSTAT_UNDERRUN 0x00000002 418 #define DC_TXSTAT_LINKFAIL 0x00000003 419 #define DC_TXSTAT_COLLCNT 0x00000078 420 #define DC_TXSTAT_SQE 0x00000080 421 #define DC_TXSTAT_EXCESSCOLL 0x00000100 422 #define DC_TXSTAT_LATECOLL 0x00000200 423 #define DC_TXSTAT_NOCARRIER 0x00000400 424 #define DC_TXSTAT_CARRLOST 0x00000800 425 #define DC_TXSTAT_JABTIMEO 0x00004000 426 #define DC_TXSTAT_ERRSUM 0x00008000 427 #define DC_TXSTAT_OWN 0x80000000 428 429 #define DC_TXCTL_BUFLEN1 0x000007FF 430 #define DC_TXCTL_BUFLEN2 0x003FF800 431 #define DC_TXCTL_FILTTYPE0 0x00400000 432 #define DC_TXCTL_PAD 0x00800000 433 #define DC_TXCTL_TLINK 0x01000000 434 #define DC_TXCTL_TLAST 0x02000000 435 #define DC_TXCTL_NOCRC 0x04000000 436 #define DC_TXCTL_SETUP 0x08000000 437 #define DC_TXCTL_FILTTYPE1 0x10000000 438 #define DC_TXCTL_FIRSTFRAG 0x20000000 439 #define DC_TXCTL_LASTFRAG 0x40000000 440 #define DC_TXCTL_FINT 0x80000000 441 442 #define DC_FILTER_PERFECT 0x00000000 443 #define DC_FILTER_HASHPERF 0x00400000 444 #define DC_FILTER_INVERSE 0x10000000 445 #define DC_FILTER_HASHONLY 0x10400000 446 447 #define DC_MAXFRAGS 16 448 #define DC_RX_LIST_CNT 64 449 #define DC_TX_LIST_CNT 256 450 #define DC_MIN_FRAMELEN 60 451 #define DC_RXLEN 1536 452 453 #define DC_INC(x, y) (x) = (x + 1) % y 454 455 struct dc_list_data { 456 struct dc_desc dc_rx_list[DC_RX_LIST_CNT]; 457 struct dc_desc dc_tx_list[DC_TX_LIST_CNT]; 458 }; 459 460 struct dc_chain_data { 461 struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; 462 struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; 463 u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)]; 464 u_int8_t dc_pad[DC_MIN_FRAMELEN]; 465 int dc_tx_prod; 466 int dc_tx_cons; 467 int dc_tx_cnt; 468 int dc_rx_prod; 469 }; 470 471 struct dc_mediainfo { 472 int dc_media; 473 u_int8_t *dc_gp_ptr; 474 u_int8_t dc_gp_len; 475 u_int8_t *dc_reset_ptr; 476 u_int8_t dc_reset_len; 477 struct dc_mediainfo *dc_next; 478 }; 479 480 481 struct dc_type { 482 u_int16_t dc_vid; 483 u_int16_t dc_did; 484 char *dc_name; 485 }; 486 487 struct dc_mii_frame { 488 u_int8_t mii_stdelim; 489 u_int8_t mii_opcode; 490 u_int8_t mii_phyaddr; 491 u_int8_t mii_regaddr; 492 u_int8_t mii_turnaround; 493 u_int16_t mii_data; 494 }; 495 496 /* 497 * MII constants 498 */ 499 #define DC_MII_STARTDELIM 0x01 500 #define DC_MII_READOP 0x02 501 #define DC_MII_WRITEOP 0x01 502 #define DC_MII_TURNAROUND 0x02 503 504 505 /* 506 * Registers specific to clone devices. 507 * This mainly relates to RX filter programming: not all 21x4x clones 508 * use the standard DEC filter programming mechanism. 509 */ 510 511 /* 512 * ADMtek specific registers and constants for the AL981 and AN985. 513 * The AN985 doesn't use the magic PHY registers. 514 */ 515 #define DC_AL_PAR0 0xA4 /* station address */ 516 #define DC_AL_PAR1 0xA8 /* station address */ 517 #define DC_AL_MAR0 0xAC /* multicast hash filter */ 518 #define DC_AL_MAR1 0xB0 /* multicast hash filter */ 519 #define DC_AL_BMCR 0xB4 /* built in PHY control */ 520 #define DC_AL_BMSR 0xB8 /* built in PHY status */ 521 #define DC_AL_VENID 0xBC /* built in PHY ID0 */ 522 #define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ 523 #define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ 524 #define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ 525 #define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ 526 527 #define DC_ADMTEK_PHYADDR 0x1 528 #define DC_AL_EE_NODEADDR 4 529 /* End of ADMtek specific registers */ 530 531 /* 532 * ASIX specific registers. 533 */ 534 #define DC_AX_FILTIDX 0x68 /* RX filter index */ 535 #define DC_AX_FILTDATA 0x70 /* RX filter data */ 536 537 /* 538 * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). 539 */ 540 #define DC_AX_NETCFG_RX_BROAD 0x00000100 541 542 /* 543 * RX Filter Index Register values 544 */ 545 #define DC_AX_FILTIDX_PAR0 0x00000000 546 #define DC_AX_FILTIDX_PAR1 0x00000001 547 #define DC_AX_FILTIDX_MAR0 0x00000002 548 #define DC_AX_FILTIDX_MAR1 0x00000003 549 /* End of ASIX specific registers */ 550 551 /* 552 * Macronix specific registers. The Macronix chips have a special 553 * register for reading the NWAY status, which we don't use, plus 554 * a magic packet register, which we need to tweak a bit per the 555 * Macronix application notes. 556 */ 557 #define DC_MX_MAGICPACKET 0x80 558 #define DC_MX_NWAYSTAT 0xA0 559 560 /* 561 * Magic packet register 562 */ 563 #define DC_MX_MPACK_DISABLE 0x00400000 564 565 /* 566 * NWAY status register. 567 */ 568 #define DC_MX_NWAY_10BTHALF 0x08000000 569 #define DC_MX_NWAY_10BTFULL 0x10000000 570 #define DC_MX_NWAY_100BTHALF 0x20000000 571 #define DC_MX_NWAY_100BTFULL 0x40000000 572 #define DC_MX_NWAY_100BT4 0x80000000 573 574 /* 575 * These are magic values that must be written into CSR16 576 * (DC_MX_MAGICPACKET) in order to put the chip into proper 577 * operating mode. The magic numbers are documented in the 578 * Macronix 98715 application notes. 579 */ 580 #define DC_MX_MAGIC_98713 0x0F370000 581 #define DC_MX_MAGIC_98713A 0x0B3C0000 582 #define DC_MX_MAGIC_98715 0x0B3C0000 583 #define DC_MX_MAGIC_98725 0x0B3C0000 584 /* End of Macronix specific registers */ 585 586 /* 587 * PNIC 82c168/82c169 specific registers. 588 * The PNIC has its own special NWAY support, which doesn't work, 589 * and shortcut ways of reading the EEPROM and MII bus. 590 */ 591 #define DC_PN_GPIO 0x60 /* general purpose pins control */ 592 #define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ 593 #define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ 594 #define DC_PN_MII 0xA0 /* MII access register */ 595 #define DC_PN_NWAY 0xB8 /* Internal NWAY register */ 596 597 /* Serial I/O EEPROM register */ 598 #define DC_PN_SIOCTL_DATA 0x0000003F 599 #define DC_PN_SIOCTL_OPCODE 0x00000300 600 #define DC_PN_SIOCTL_BUSY 0x80000000 601 602 #define DC_PN_EEOPCODE_ERASE 0x00000300 603 #define DC_PN_EEOPCODE_READ 0x00000600 604 #define DC_PN_EEOPCODE_WRITE 0x00000100 605 606 /* 607 * The first two general purpose pins control speed selection and 608 * 100Mbps loopback on the 82c168 chip. The control bits should always 609 * be set (to make the data pins outputs) and the speed selction and 610 * loopback bits set accordingly when changing media. Physically, this 611 * will set the state of a relay mounted on the card. 612 */ 613 #define DC_PN_GPIO_DATA0 0x000000001 614 #define DC_PN_GPIO_DATA1 0x000000002 615 #define DC_PN_GPIO_DATA2 0x000000004 616 #define DC_PN_GPIO_DATA3 0x000000008 617 #define DC_PN_GPIO_CTL0 0x000000010 618 #define DC_PN_GPIO_CTL1 0x000000020 619 #define DC_PN_GPIO_CTL2 0x000000040 620 #define DC_PN_GPIO_CTL3 0x000000080 621 #define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ 622 #define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ 623 #define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 624 #define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 625 #define DC_PN_GPIO_SETBIT(sc, r) \ 626 DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) 627 #define DC_PN_GPIO_CLRBIT(sc, r) \ 628 { \ 629 DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ 630 DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ 631 } 632 633 /* shortcut MII access register */ 634 #define DC_PN_MII_DATA 0x0000FFFF 635 #define DC_PN_MII_RESERVER 0x00020000 636 #define DC_PN_MII_REGADDR 0x007C0000 637 #define DC_PN_MII_PHYADDR 0x0F800000 638 #define DC_PN_MII_OPCODE 0x30000000 639 #define DC_PN_MII_BUSY 0x80000000 640 641 #define DC_PN_MIIOPCODE_READ 0x60020000 642 #define DC_PN_MIIOPCODE_WRITE 0x50020000 643 644 /* Internal NWAY bits */ 645 #define DC_PN_NWAY_RESET 0x00000001 /* reset */ 646 #define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ 647 #define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ 648 #define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ 649 #define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ 650 #define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ 651 #define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ 652 #define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ 653 #define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ 654 #define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ 655 #define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ 656 #define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ 657 #define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ 658 #define DC_PN_NWAY_CAP10HDX 0x00002000 659 #define DC_PN_NWAY_CAP10FDX 0x00004000 660 #define DC_PN_NWAY_CAP100FDX 0x00008000 661 #define DC_PN_NWAY_CAP100HDX 0x00010000 662 #define DC_PN_NWAY_CAP100T4 0x00020000 663 #define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ 664 #define DC_PN_NWAY_REMFAULT 0x04000000 665 #define DC_PN_NWAY_LPAR10HDX 0x08000000 666 #define DC_PN_NWAY_LPAR10FDX 0x10000000 667 #define DC_PN_NWAY_LPAR100FDX 0x20000000 668 #define DC_PN_NWAY_LPAR100HDX 0x40000000 669 #define DC_PN_NWAY_LPAR100T4 0x80000000 670 671 /* End of PNIC specific registers */ 672 673 struct dc_softc { 674 struct arpcom arpcom; /* interface info */ 675 bus_space_handle_t dc_bhandle; /* bus space handle */ 676 bus_space_tag_t dc_btag; /* bus space tag */ 677 void *dc_intrhand; 678 struct resource *dc_irq; 679 struct resource *dc_res; 680 struct dc_type *dc_info; /* adapter info */ 681 device_t dc_miibus; 682 u_int8_t dc_unit; /* interface number */ 683 u_int8_t dc_type; 684 u_int8_t dc_pmode; 685 u_int8_t dc_link; 686 u_int8_t dc_cachesize; 687 int dc_pnic_rx_bug_save; 688 unsigned char *dc_pnic_rx_buf; 689 int dc_if_flags; 690 int dc_if_media; 691 u_int32_t dc_flags; 692 u_int32_t dc_txthresh; 693 u_int8_t dc_srom[1024]; 694 struct dc_mediainfo *dc_mi; 695 struct dc_list_data *dc_ldata; 696 struct dc_chain_data dc_cdata; 697 struct callout dc_stat_ch; 698 #ifdef SRM_MEDIA 699 int dc_srm_media; 700 #endif 701 struct mtx dc_mtx; 702 }; 703 704 705 #define DC_LOCK(_sc) mtx_enter(&(_sc)->dc_mtx, MTX_DEF) 706 #define DC_UNLOCK(_sc) mtx_exit(&(_sc)->dc_mtx, MTX_DEF) 707 708 #define DC_TX_POLL 0x00000001 709 #define DC_TX_COALESCE 0x00000002 710 #define DC_TX_ADMTEK_WAR 0x00000004 711 #define DC_TX_USE_TX_INTR 0x00000008 712 #define DC_RX_FILTER_TULIP 0x00000010 713 #define DC_TX_INTR_FIRSTFRAG 0x00000020 714 #define DC_PNIC_RX_BUG_WAR 0x00000040 715 #define DC_TX_FIXED_RING 0x00000080 716 #define DC_TX_STORENFWD 0x00000100 717 #define DC_REDUCED_MII_POLL 0x00000200 718 #define DC_TX_INTR_ALWAYS 0x00000400 719 #define DC_21143_NWAY 0x00000800 720 #define DC_128BIT_HASH 0x00001000 721 #define DC_64BIT_HASH 0x00002000 722 #define DC_TULIP_LEDS 0x00004000 723 #define DC_TX_ONE 0x00008000 724 725 /* 726 * register space access macros 727 */ 728 #define CSR_WRITE_4(sc, reg, val) \ 729 bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val) 730 731 #define CSR_READ_4(sc, reg) \ 732 bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg) 733 734 #define DC_TIMEOUT 1000 735 #define ETHER_ALIGN 2 736 737 /* 738 * General constants that are fun to know. 739 */ 740 741 /* 742 * DEC PCI vendor ID 743 */ 744 #define DC_VENDORID_DEC 0x1011 745 746 /* 747 * DEC/Intel 21143 PCI device ID 748 */ 749 #define DC_DEVICEID_21143 0x0019 750 751 /* 752 * Macronix PCI vendor ID 753 */ 754 #define DC_VENDORID_MX 0x10D9 755 756 /* 757 * Macronix PMAC device IDs. 758 */ 759 #define DC_DEVICEID_98713 0x0512 760 #define DC_DEVICEID_987x5 0x0531 761 #define DC_DEVICEID_98727 0x0532 762 #define DC_DEVICEID_98732 0x0532 763 764 /* Macronix PCI revision codes. */ 765 #define DC_REVISION_98713 0x00 766 #define DC_REVISION_98713A 0x10 767 #define DC_REVISION_98715 0x20 768 #define DC_REVISION_98715AEC_C 0x25 769 #define DC_REVISION_98725 0x30 770 771 /* 772 * Compex PCI vendor ID. 773 */ 774 #define DC_VENDORID_CP 0x11F6 775 776 /* 777 * Compex PMAC PCI device IDs. 778 */ 779 #define DC_DEVICEID_98713_CP 0x9881 780 781 /* 782 * Lite-On PNIC PCI vendor ID 783 */ 784 #define DC_VENDORID_LO 0x11AD 785 786 /* 787 * 82c168/82c169 PNIC device IDs. Both chips have the same device 788 * ID but different revisions. Revision 0x10 is the 82c168, and 789 * 0x20 is the 82c169. 790 */ 791 #define DC_DEVICEID_82C168 0x0002 792 793 #define DC_REVISION_82C168 0x10 794 #define DC_REVISION_82C169 0x20 795 796 /* 797 * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A 798 * with wake on lan/magic packet support. 799 */ 800 #define DC_DEVICEID_82C115 0xc115 801 802 /* 803 * Davicom vendor ID. 804 */ 805 #define DC_VENDORID_DAVICOM 0x1282 806 807 /* 808 * Davicom device IDs. 809 */ 810 #define DC_DEVICEID_DM9100 0x9100 811 #define DC_DEVICEID_DM9102 0x9102 812 813 /* 814 * The DM9102A has the same PCI device ID as the DM9102, 815 * but a higher revision code. 816 */ 817 #define DC_REVISION_DM9102 0x10 818 #define DC_REVISION_DM9102A 0x30 819 820 /* 821 * ADMtek vendor ID. 822 */ 823 #define DC_VENDORID_ADMTEK 0x1317 824 825 /* 826 * ADMtek device IDs. 827 */ 828 #define DC_DEVICEID_AL981 0x0981 829 #define DC_DEVICEID_AN985 0x0985 830 831 /* 832 * ASIX vendor ID. 833 */ 834 #define DC_VENDORID_ASIX 0x125B 835 836 /* 837 * ASIX device IDs. 838 */ 839 #define DC_DEVICEID_AX88140A 0x1400 840 841 /* 842 * The ASIX AX88140 and ASIX AX88141 have the same vendor and 843 * device IDs but different revision values. 844 */ 845 #define DC_REVISION_88140 0x00 846 #define DC_REVISION_88141 0x10 847 848 /* 849 * Accton vendor ID. 850 */ 851 #define DC_VENDORID_ACCTON 0x1113 852 853 /* 854 * Accton device IDs. 855 */ 856 #define DC_DEVICEID_EN1217 0x1217 857 #define DC_DEVICEID_EN2242 0x1216 858 859 /* 860 * Xircom vendor ID 861 */ 862 #define DC_VENDORID_XIRCOM 0x115d 863 864 /* 865 * Xircom device IDs. 866 */ 867 #define DC_DEVICEID_X3201 0x0003 868 869 /* 870 * Abocom vendor ID 871 */ 872 #define DC_VENDORID_ABOCOM 0x13d1 873 874 /* 875 * Abocom device IDs. 876 */ 877 #define DC_DEVICEID_FE2500 0xAB02 878 879 /* 880 * PCI low memory base and low I/O base register, and 881 * other PCI registers. 882 */ 883 884 #define DC_PCI_CFID 0x00 /* Id */ 885 #define DC_PCI_CFCS 0x04 /* Command and status */ 886 #define DC_PCI_CFRV 0x08 /* Revision */ 887 #define DC_PCI_CFLT 0x0C /* Latency timer */ 888 #define DC_PCI_CFBIO 0x10 /* Base I/O address */ 889 #define DC_PCI_CFBMA 0x14 /* Base memory address */ 890 #define DC_PCI_CCIS 0x28 /* Card info struct */ 891 #define DC_PCI_CSID 0x2C /* Subsystem ID */ 892 #define DC_PCI_CBER 0x30 /* Expansion ROM base address */ 893 #define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */ 894 #define DC_PCI_CFIT 0x3C /* Interrupt */ 895 #define DC_PCI_CFDD 0x40 /* Device and driver area */ 896 #define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ 897 #define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ 898 #define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ 899 #define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ 900 #define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ 901 #define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */ 902 #define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */ 903 904 /* PCI ID register */ 905 #define DC_CFID_VENDOR 0x0000FFFF 906 #define DC_CFID_DEVICE 0xFFFF0000 907 908 /* PCI command/status register */ 909 #define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */ 910 #define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */ 911 #define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */ 912 #define DC_CFCS_MWI_ENB 0x00000008 /* mem write and inval enable */ 913 #define DC_CFCS_PARITYERR_ENB 0x00000020 /* parity error enable */ 914 #define DC_CFCS_SYSERR_ENB 0x00000080 /* system error enable */ 915 #define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */ 916 #define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */ 917 #define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */ 918 #define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */ 919 #define DC_CFCS_TGTABRT 0x10000000 /* received target abort */ 920 #define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */ 921 #define DC_CFCS_SYSERR 0x40000000 /* asserted system error */ 922 #define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */ 923 924 /* PCI revision register */ 925 #define DC_CFRV_STEPPING 0x0000000F 926 #define DC_CFRV_REVISION 0x000000F0 927 #define DC_CFRV_SUBCLASS 0x00FF0000 928 #define DC_CFRV_BASECLASS 0xFF000000 929 930 #define DC_21143_PB_REV 0x00000030 931 #define DC_21143_TB_REV 0x00000030 932 #define DC_21143_PC_REV 0x00000030 933 #define DC_21143_TC_REV 0x00000030 934 #define DC_21143_PD_REV 0x00000041 935 #define DC_21143_TD_REV 0x00000041 936 937 /* PCI latency timer register */ 938 #define DC_CFLT_CACHELINESIZE 0x000000FF 939 #define DC_CFLT_LATENCYTIMER 0x0000FF00 940 941 /* PCI subsystem ID register */ 942 #define DC_CSID_VENDOR 0x0000FFFF 943 #define DC_CSID_DEVICE 0xFFFF0000 944 945 /* PCI cababilities pointer */ 946 #define DC_CCAP_OFFSET 0x000000FF 947 948 /* PCI interrupt config register */ 949 #define DC_CFIT_INTLINE 0x000000FF 950 #define DC_CFIT_INTPIN 0x0000FF00 951 #define DC_CFIT_MIN_GNT 0x00FF0000 952 #define DC_CFIT_MAX_LAT 0xFF000000 953 954 /* PCI capability register */ 955 #define DC_CCID_CAPID 0x000000FF 956 #define DC_CCID_NEXTPTR 0x0000FF00 957 #define DC_CCID_PM_VERS 0x00070000 958 #define DC_CCID_PME_CLK 0x00080000 959 #define DC_CCID_DVSPEC_INT 0x00200000 960 #define DC_CCID_STATE_D1 0x02000000 961 #define DC_CCID_STATE_D2 0x04000000 962 #define DC_CCID_PME_D0 0x08000000 963 #define DC_CCID_PME_D1 0x10000000 964 #define DC_CCID_PME_D2 0x20000000 965 #define DC_CCID_PME_D3HOT 0x40000000 966 #define DC_CCID_PME_D3COLD 0x80000000 967 968 /* PCI power management control/status register */ 969 #define DC_CPMC_STATE 0x00000003 970 #define DC_CPMC_PME_ENB 0x00000100 971 #define DC_CPMC_PME_STS 0x00008000 972 973 #define DC_PSTATE_D0 0x0 974 #define DC_PSTATE_D1 0x1 975 #define DC_PSTATE_D2 0x2 976 #define DC_PSTATE_D3 0x3 977 978 /* Device specific region */ 979 /* Configuration and driver area */ 980 #define DC_CFDD_DRVUSE 0x0000FFFF 981 #define DC_CFDD_SNOOZE_MODE 0x40000000 982 #define DC_CFDD_SLEEP_MODE 0x80000000 983 984 /* Configuration wake-up command register */ 985 #define DC_CWUC_MUST_BE_ZERO 0x00000001 986 #define DC_CWUC_SECUREON_ENB 0x00000002 987 #define DC_CWUC_FORCE_WUL 0x00000004 988 #define DC_CWUC_BNC_ABILITY 0x00000008 989 #define DC_CWUC_AUI_ABILITY 0x00000010 990 #define DC_CWUC_TP10_ABILITY 0x00000020 991 #define DC_CWUC_MII_ABILITY 0x00000040 992 #define DC_CWUC_SYM_ABILITY 0x00000080 993 #define DC_CWUC_LOCK 0x00000100 994 995 /* 996 * SROM nonsense. 997 */ 998 999 #define DC_IB_CTLRCNT 0x13 1000 #define DC_IB_LEAF0_CNUM 0x1A 1001 #define DC_IB_LEAF0_OFFSET 0x1B 1002 1003 struct dc_info_leaf { 1004 u_int16_t dc_conntype; 1005 u_int8_t dc_blkcnt; 1006 u_int8_t dc_rsvd; 1007 u_int16_t dc_infoblk; 1008 }; 1009 1010 #define DC_CTYPE_10BT 0x0000 1011 #define DC_CTYPE_10BT_NWAY 0x0100 1012 #define DC_CTYPE_10BT_FDX 0x0204 1013 #define DC_CTYPE_10B2 0x0001 1014 #define DC_CTYPE_10B5 0x0002 1015 #define DC_CTYPE_100BT 0x0003 1016 #define DC_CTYPE_100BT_FDX 0x0205 1017 #define DC_CTYPE_100T4 0x0006 1018 #define DC_CTYPE_100FX 0x0007 1019 #define DC_CTYPE_100FX_FDX 0x0208 1020 #define DC_CTYPE_MII_10BT 0x0009 1021 #define DC_CTYPE_MII_10BT_FDX 0x020A 1022 #define DC_CTYPE_MII_100BT 0x000D 1023 #define DC_CTYPE_MII_100BT_FDX 0x020E 1024 #define DC_CTYPE_MII_100T4 0x000F 1025 #define DC_CTYPE_MII_100FX 0x0010 1026 #define DC_CTYPE_MII_100FX_FDX 0x0211 1027 #define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800 1028 #define DC_CTYPE_PUP_AUTOSENSe 0x8800 1029 #define DC_CTYPE_NOMEDIA 0xFFFF 1030 1031 #define DC_EBLOCK_SIA 0x0002 1032 #define DC_EBLOCK_MII 0x0003 1033 #define DC_EBLOCK_SYM 0x0004 1034 #define DC_EBLOCK_RESET 0x0005 1035 #define DC_EBLOCK_PHY_SHUTDOWN 0x0006 1036 1037 struct dc_leaf_hdr { 1038 u_int16_t dc_mtype; 1039 u_int8_t dc_mcnt; 1040 u_int8_t dc_rsvd; 1041 }; 1042 1043 struct dc_eblock_hdr { 1044 u_int8_t dc_len; 1045 u_int8_t dc_type; 1046 }; 1047 1048 struct dc_eblock_sia { 1049 struct dc_eblock_hdr dc_sia_hdr; 1050 u_int8_t dc_sia_code; 1051 u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */ 1052 u_int8_t dc_sia_gpio_ctl[2]; 1053 u_int8_t dc_sia_gpio_dat[2]; 1054 }; 1055 1056 #define DC_SIA_CODE_10BT 0x00 1057 #define DC_SIA_CODE_10B2 0x01 1058 #define DC_SIA_CODE_10B5 0x02 1059 #define DC_SIA_CODE_10BT_FDX 0x04 1060 #define DC_SIA_CODE_EXT 0x40 1061 1062 /* 1063 * Note that the first word in the gpr and reset 1064 * sequences is always a control word. 1065 */ 1066 struct dc_eblock_mii { 1067 struct dc_eblock_hdr dc_mii_hdr; 1068 u_int8_t dc_mii_phynum; 1069 u_int8_t dc_gpr_len; 1070 /* u_int16_t dc_gpr_dat[n]; */ 1071 /* u_int8_t dc_reset_len; */ 1072 /* u_int16_t dc_reset_dat[n]; */ 1073 /* There are other fields after these, but we don't 1074 * care about them since they can be determined by looking 1075 * at the PHY. 1076 */ 1077 }; 1078 1079 struct dc_eblock_sym { 1080 struct dc_eblock_hdr dc_sym_hdr; 1081 u_int8_t dc_sym_code; 1082 u_int8_t dc_sym_gpio_ctl[2]; 1083 u_int8_t dc_sym_gpio_dat[2]; 1084 u_int8_t dc_sym_cmd[2]; 1085 }; 1086 1087 #define DC_SYM_CODE_100BT 0x03 1088 #define DC_SYM_CODE_100BT_FDX 0x05 1089 #define DC_SYM_CODE_100T4 0x06 1090 #define DC_SYM_CODE_100FX 0x07 1091 #define DC_SYM_CODE_100FX_FDX 0x08 1092 1093 struct dc_eblock_reset { 1094 struct dc_eblock_hdr dc_reset_hdr; 1095 u_int8_t dc_reset_len; 1096 /* u_int16_t dc_reset_dat[n]; */ 1097 }; 1098 1099 #ifdef __alpha__ 1100 #undef vtophys 1101 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1102 #endif 1103