1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * 21143 and clone common register definitions. 37 */ 38 39 #define DC_BUSCTL 0x00 /* bus control */ 40 #define DC_TXSTART 0x08 /* tx start demand */ 41 #define DC_RXSTART 0x10 /* rx start demand */ 42 #define DC_RXADDR 0x18 /* rx descriptor list start addr */ 43 #define DC_TXADDR 0x20 /* tx descriptor list start addr */ 44 #define DC_ISR 0x28 /* interrupt status register */ 45 #define DC_NETCFG 0x30 /* network config register */ 46 #define DC_IMR 0x38 /* interrupt mask */ 47 #define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ 48 #define DC_SIO 0x48 /* MII and ROM/EEPROM access */ 49 #define DC_ROM 0x50 /* ROM programming address */ 50 #define DC_TIMER 0x58 /* general timer */ 51 #define DC_10BTSTAT 0x60 /* SIA status */ 52 #define DC_SIARESET 0x68 /* SIA connectivity */ 53 #define DC_10BTCTRL 0x70 /* SIA transmit and receive */ 54 #define DC_WATCHDOG 0x78 /* SIA and general purpose port */ 55 #define DC_SIAGP 0x78 /* SIA and general purpose port (X3201) */ 56 57 /* 58 * There are two general 'types' of MX chips that we need to be 59 * concerned with. One is the original 98713, which has its internal 60 * NWAY support controlled via the MDIO bits in the serial I/O 61 * register. The other is everything else (from the 98713A on up), 62 * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, 63 * just like the 21143. This type setting also governs which of the 64 * 'magic' numbers we write to CSR16. The PNIC II falls into the 65 * 98713A/98715/98715A/98725 category. 66 */ 67 #define DC_TYPE_98713 0x1 68 #define DC_TYPE_98713A 0x2 69 #define DC_TYPE_987x5 0x3 70 71 /* Other type of supported chips. */ 72 #define DC_TYPE_21143 0x4 /* Intel 21143 */ 73 #define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ 74 #define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ 75 #define DC_TYPE_AN983 0x7 /* ADMtek AN983 Centaur */ 76 #define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ 77 #define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ 78 #define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ 79 #define DC_TYPE_XIRCOM 0xB /* Xircom X3201 */ 80 #define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */ 81 #define DC_TYPE_ULI_M5261 0xD /* ALi/ULi M5261 */ 82 #define DC_TYPE_ULI_M5263 0xE /* ALi/ULi M5263 */ 83 84 #define DC_IS_MACRONIX(x) \ 85 (x->dc_type == DC_TYPE_98713 || \ 86 x->dc_type == DC_TYPE_98713A || \ 87 x->dc_type == DC_TYPE_987x5) 88 89 #define DC_IS_ADMTEK(x) \ 90 (x->dc_type == DC_TYPE_AL981 || \ 91 x->dc_type == DC_TYPE_AN983) 92 93 #define DC_IS_ULI(x) \ 94 (x->dc_type == DC_TYPE_ULI_M5261 || \ 95 x->dc_type == DC_TYPE_ULI_M5263) 96 97 #define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) 98 #define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) 99 #define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) 100 #define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN983) 101 #define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) 102 #define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) 103 #define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) 104 #define DC_IS_XIRCOM(x) (x->dc_type == DC_TYPE_XIRCOM) 105 #define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT) 106 107 /* MII/symbol mode port types */ 108 #define DC_PMODE_MII 0x1 109 #define DC_PMODE_SYM 0x2 110 #define DC_PMODE_SIA 0x3 111 112 /* 113 * Bus control bits. 114 */ 115 #define DC_BUSCTL_RESET 0x00000001 116 #define DC_BUSCTL_ARBITRATION 0x00000002 117 #define DC_BUSCTL_SKIPLEN 0x0000007C 118 #define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 119 #define DC_BUSCTL_BURSTLEN 0x00003F00 120 #define DC_BUSCTL_CACHEALIGN 0x0000C000 121 #define DC_BUSCTL_TXPOLL 0x000E0000 122 #define DC_BUSCTL_DBO 0x00100000 123 #define DC_BUSCTL_MRME 0x00200000 124 #define DC_BUSCTL_MRLE 0x00800000 125 #define DC_BUSCTL_MWIE 0x01000000 126 #define DC_BUSCTL_ONNOW_ENB 0x04000000 127 128 #define DC_SKIPLEN_1LONG 0x00000004 129 #define DC_SKIPLEN_2LONG 0x00000008 130 #define DC_SKIPLEN_3LONG 0x00000010 131 #define DC_SKIPLEN_4LONG 0x00000020 132 #define DC_SKIPLEN_5LONG 0x00000040 133 134 #define DC_CACHEALIGN_NONE 0x00000000 135 #define DC_CACHEALIGN_8LONG 0x00004000 136 #define DC_CACHEALIGN_16LONG 0x00008000 137 #define DC_CACHEALIGN_32LONG 0x0000C000 138 139 #define DC_BURSTLEN_USECA 0x00000000 140 #define DC_BURSTLEN_1LONG 0x00000100 141 #define DC_BURSTLEN_2LONG 0x00000200 142 #define DC_BURSTLEN_4LONG 0x00000400 143 #define DC_BURSTLEN_8LONG 0x00000800 144 #define DC_BURSTLEN_16LONG 0x00001000 145 #define DC_BURSTLEN_32LONG 0x00002000 146 147 #define DC_TXPOLL_OFF 0x00000000 148 #define DC_TXPOLL_1 0x00020000 149 #define DC_TXPOLL_2 0x00040000 150 #define DC_TXPOLL_3 0x00060000 151 #define DC_TXPOLL_4 0x00080000 152 #define DC_TXPOLL_5 0x000A0000 153 #define DC_TXPOLL_6 0x000C0000 154 #define DC_TXPOLL_7 0x000E0000 155 156 /* 157 * Interrupt status bits. 158 */ 159 #define DC_ISR_TX_OK 0x00000001 160 #define DC_ISR_TX_IDLE 0x00000002 161 #define DC_ISR_TX_NOBUF 0x00000004 162 #define DC_ISR_TX_JABBERTIMEO 0x00000008 163 #define DC_ISR_LINKGOOD 0x00000010 164 #define DC_ISR_TX_UNDERRUN 0x00000020 165 #define DC_ISR_RX_OK 0x00000040 166 #define DC_ISR_RX_NOBUF 0x00000080 167 #define DC_ISR_RX_READ 0x00000100 168 #define DC_ISR_RX_WATDOGTIMEO 0x00000200 169 #define DC_ISR_TX_EARLY 0x00000400 170 #define DC_ISR_TIMER_EXPIRED 0x00000800 171 #define DC_ISR_LINKFAIL 0x00001000 172 #define DC_ISR_BUS_ERR 0x00002000 173 #define DC_ISR_RX_EARLY 0x00004000 174 #define DC_ISR_ABNORMAL 0x00008000 175 #define DC_ISR_NORMAL 0x00010000 176 #define DC_ISR_RX_STATE 0x000E0000 177 #define DC_ISR_TX_STATE 0x00700000 178 #define DC_ISR_BUSERRTYPE 0x03800000 179 #define DC_ISR_100MBPSLINK 0x08000000 180 #define DC_ISR_MAGICKPACK 0x10000000 181 182 #define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ 183 #define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ 184 #define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ 185 #define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ 186 #define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ 187 #define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ 188 #define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ 189 #define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ 190 191 #define DC_HAS_BROKEN_RXSTATE(x) \ 192 (DC_IS_CENTAUR(x) || DC_IS_CONEXANT(x) || (DC_IS_DAVICOM(x) && \ 193 pci_get_revid((x)->dc_dev) >= DC_REVISION_DM9102A)) 194 195 #define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ 196 #define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ 197 #define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ 198 #define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ 199 #define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ 200 #define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ 201 #define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ 202 #define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ 203 204 /* 205 * Network config bits. 206 */ 207 #define DC_NETCFG_RX_HASHPERF 0x00000001 208 #define DC_NETCFG_RX_ON 0x00000002 209 #define DC_NETCFG_RX_HASHONLY 0x00000004 210 #define DC_NETCFG_RX_BADFRAMES 0x00000008 211 #define DC_NETCFG_RX_INVFILT 0x00000010 212 #define DC_NETCFG_BACKOFFCNT 0x00000020 213 #define DC_NETCFG_RX_PROMISC 0x00000040 214 #define DC_NETCFG_RX_ALLMULTI 0x00000080 215 #define DC_NETCFG_FULLDUPLEX 0x00000200 216 #define DC_NETCFG_LOOPBACK 0x00000C00 217 #define DC_NETCFG_FORCECOLL 0x00001000 218 #define DC_NETCFG_TX_ON 0x00002000 219 #define DC_NETCFG_TX_THRESH 0x0000C000 220 #define DC_NETCFG_TX_BACKOFF 0x00020000 221 #define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ 222 #define DC_NETCFG_HEARTBEAT 0x00080000 223 #define DC_NETCFG_STORENFWD 0x00200000 224 #define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ 225 #define DC_NETCFG_PCS 0x00800000 226 #define DC_NETCFG_SCRAMBLER 0x01000000 227 #define DC_NETCFG_NO_RXCRC 0x02000000 228 #define DC_NETCFG_RX_ALL 0x40000000 229 #define DC_NETCFG_CAPEFFECT 0x80000000 230 231 #define DC_OPMODE_NORM 0x00000000 232 #define DC_OPMODE_INTLOOP 0x00000400 233 #define DC_OPMODE_EXTLOOP 0x00000800 234 235 #if 0 236 #define DC_TXTHRESH_72BYTES 0x00000000 237 #define DC_TXTHRESH_96BYTES 0x00004000 238 #define DC_TXTHRESH_128BYTES 0x00008000 239 #define DC_TXTHRESH_160BYTES 0x0000C000 240 #endif 241 242 #define DC_TXTHRESH_MIN 0x00000000 243 #define DC_TXTHRESH_INC 0x00004000 244 #define DC_TXTHRESH_MAX 0x0000C000 245 246 247 /* 248 * Interrupt mask bits. 249 */ 250 #define DC_IMR_TX_OK 0x00000001 251 #define DC_IMR_TX_IDLE 0x00000002 252 #define DC_IMR_TX_NOBUF 0x00000004 253 #define DC_IMR_TX_JABBERTIMEO 0x00000008 254 #define DC_IMR_LINKGOOD 0x00000010 255 #define DC_IMR_TX_UNDERRUN 0x00000020 256 #define DC_IMR_RX_OK 0x00000040 257 #define DC_IMR_RX_NOBUF 0x00000080 258 #define DC_IMR_RX_READ 0x00000100 259 #define DC_IMR_RX_WATDOGTIMEO 0x00000200 260 #define DC_IMR_TX_EARLY 0x00000400 261 #define DC_IMR_TIMER_EXPIRED 0x00000800 262 #define DC_IMR_LINKFAIL 0x00001000 263 #define DC_IMR_BUS_ERR 0x00002000 264 #define DC_IMR_RX_EARLY 0x00004000 265 #define DC_IMR_ABNORMAL 0x00008000 266 #define DC_IMR_NORMAL 0x00010000 267 #define DC_IMR_100MBPSLINK 0x08000000 268 #define DC_IMR_MAGICKPACK 0x10000000 269 270 #define DC_INTRS \ 271 (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ 272 DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ 273 DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) 274 /* 275 * Serial I/O (EEPROM/ROM) bits. 276 */ 277 #define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ 278 #define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ 279 #define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ 280 #define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ 281 #define DC_SIO_ROMDATA4 0x00000010 282 #define DC_SIO_ROMDATA5 0x00000020 283 #define DC_SIO_ROMDATA6 0x00000040 284 #define DC_SIO_ROMDATA7 0x00000080 285 #define DC_SIO_EESEL 0x00000800 286 #define DC_SIO_ROMSEL 0x00001000 287 #define DC_SIO_ROMCTL_WRITE 0x00002000 288 #define DC_SIO_ROMCTL_READ 0x00004000 289 #define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ 290 #define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ 291 #define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ 292 #define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ 293 294 #define DC_EECMD_WRITE 0x140 295 #define DC_EECMD_READ 0x180 296 #define DC_EECMD_ERASE 0x1c0 297 298 #define DC_EE_NODEADDR_OFFSET 0x70 299 #define DC_EE_NODEADDR 10 300 301 /* 302 * General purpose timer register 303 */ 304 #define DC_TIMER_VALUE 0x0000FFFF 305 #define DC_TIMER_CONTINUOUS 0x00010000 306 307 /* 308 * 10baseT status register 309 */ 310 #define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ 311 #define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ 312 #define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ 313 #define DC_TSTAT_AUTOPOLARITY 0x00000008 314 #define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ 315 #define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ 316 #define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ 317 #define DC_TSTAT_REMFAULT 0x00000800 318 #define DC_TSTAT_ANEGSTAT 0x00007000 319 #define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ 320 #define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ 321 322 #define DC_ASTAT_DISABLE 0x00000000 323 #define DC_ASTAT_TXDISABLE 0x00001000 324 #define DC_ASTAT_ABDETECT 0x00002000 325 #define DC_ASTAT_ACKDETECT 0x00003000 326 #define DC_ASTAT_CMPACKDETECT 0x00004000 327 #define DC_ASTAT_AUTONEGCMP 0x00005000 328 #define DC_ASTAT_LINKCHECK 0x00006000 329 330 /* 331 * PHY reset register 332 */ 333 #define DC_SIA_RESET 0x00000001 334 #define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ 335 336 /* 337 * 10baseT control register 338 */ 339 #define DC_TCTL_ENCODER_ENB 0x00000001 340 #define DC_TCTL_LOOPBACK 0x00000002 341 #define DC_TCTL_DRIVER_ENB 0x00000004 342 #define DC_TCTL_LNKPULSE_ENB 0x00000008 343 #define DC_TCTL_HALFDUPLEX 0x00000040 344 #define DC_TCTL_AUTONEGENBL 0x00000080 345 #define DC_TCTL_RX_SQUELCH 0x00000100 346 #define DC_TCTL_COLL_SQUELCH 0x00000200 347 #define DC_TCTL_COLL_DETECT 0x00000400 348 #define DC_TCTL_SQE_ENB 0x00000800 349 #define DC_TCTL_LINKTEST 0x00001000 350 #define DC_TCTL_AUTOPOLARITY 0x00002000 351 #define DC_TCTL_SET_POL_PLUS 0x00004000 352 #define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ 353 #define DC_TCTL_100BTXHALF 0x00010000 354 #define DC_TCTL_100BTXFULL 0x00020000 355 #define DC_TCTL_100BT4 0x00040000 356 357 /* 358 * Watchdog timer register 359 */ 360 #define DC_WDOG_JABBERDIS 0x00000001 361 #define DC_WDOG_HOSTUNJAB 0x00000002 362 #define DC_WDOG_JABBERCLK 0x00000004 363 #define DC_WDOG_RXWDOGDIS 0x00000010 364 #define DC_WDOG_RXWDOGCLK 0x00000020 365 #define DC_WDOG_MUSTBEZERO 0x00000100 366 #define DC_WDOG_AUIBNC 0x00100000 367 #define DC_WDOG_ACTIVITY 0x00200000 368 #define DC_WDOG_RX_MATCH 0x00400000 369 #define DC_WDOG_LINK 0x00800000 370 #define DC_WDOG_CTLWREN 0x08000000 371 372 /* 373 * SIA and General Purpose Port register (X3201) 374 */ 375 #define DC_SIAGP_RXMATCH 0x40000000 376 #define DC_SIAGP_INT1 0x20000000 377 #define DC_SIAGP_INT0 0x10000000 378 #define DC_SIAGP_WRITE_EN 0x08000000 379 #define DC_SIAGP_RXMATCH_EN 0x04000000 380 #define DC_SIAGP_INT1_EN 0x02000000 381 #define DC_SIAGP_INT0_EN 0x01000000 382 #define DC_SIAGP_LED3 0x00800000 383 #define DC_SIAGP_LED2 0x00400000 384 #define DC_SIAGP_LED1 0x00200000 385 #define DC_SIAGP_LED0 0x00100000 386 #define DC_SIAGP_MD_GP3_OUTPUT 0x00080000 387 #define DC_SIAGP_MD_GP2_OUTPUT 0x00040000 388 #define DC_SIAGP_MD_GP1_OUTPUT 0x00020000 389 #define DC_SIAGP_MD_GP0_OUTPUT 0x00010000 390 391 /* 392 * Size of a setup frame. 393 */ 394 #define DC_SFRAME_LEN 192 395 396 /* 397 * 21x4x TX/RX list structure. 398 */ 399 400 struct dc_desc { 401 uint32_t dc_status; 402 uint32_t dc_ctl; 403 uint32_t dc_ptr1; 404 uint32_t dc_ptr2; 405 }; 406 407 #define dc_data dc_ptr1 408 #define dc_next dc_ptr2 409 410 #define DC_RXSTAT_FIFOOFLOW 0x00000001 411 #define DC_RXSTAT_CRCERR 0x00000002 412 #define DC_RXSTAT_DRIBBLE 0x00000004 413 #define DC_RXSTAT_MIIERE 0x00000008 414 #define DC_RXSTAT_WATCHDOG 0x00000010 415 #define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ 416 #define DC_RXSTAT_COLLSEEN 0x00000040 417 #define DC_RXSTAT_GIANT 0x00000080 418 #define DC_RXSTAT_LASTFRAG 0x00000100 419 #define DC_RXSTAT_FIRSTFRAG 0x00000200 420 #define DC_RXSTAT_MULTICAST 0x00000400 421 #define DC_RXSTAT_RUNT 0x00000800 422 #define DC_RXSTAT_RXTYPE 0x00003000 423 #define DC_RXSTAT_DE 0x00004000 424 #define DC_RXSTAT_RXERR 0x00008000 425 #define DC_RXSTAT_RXLEN 0x3FFF0000 426 #define DC_RXSTAT_OWN 0x80000000 427 428 #define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) 429 #define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) 430 431 #define DC_RXCTL_BUFLEN1 0x00000FFF 432 #define DC_RXCTL_BUFLEN2 0x00FFF000 433 #define DC_RXCTL_RLINK 0x01000000 434 #define DC_RXCTL_RLAST 0x02000000 435 436 #define DC_TXSTAT_DEFER 0x00000001 437 #define DC_TXSTAT_UNDERRUN 0x00000002 438 #define DC_TXSTAT_LINKFAIL 0x00000003 439 #define DC_TXSTAT_COLLCNT 0x00000078 440 #define DC_TXSTAT_SQE 0x00000080 441 #define DC_TXSTAT_EXCESSCOLL 0x00000100 442 #define DC_TXSTAT_LATECOLL 0x00000200 443 #define DC_TXSTAT_NOCARRIER 0x00000400 444 #define DC_TXSTAT_CARRLOST 0x00000800 445 #define DC_TXSTAT_JABTIMEO 0x00004000 446 #define DC_TXSTAT_ERRSUM 0x00008000 447 #define DC_TXSTAT_OWN 0x80000000 448 449 #define DC_TXCTL_BUFLEN1 0x000007FF 450 #define DC_TXCTL_BUFLEN2 0x003FF800 451 #define DC_TXCTL_FILTTYPE0 0x00400000 452 #define DC_TXCTL_PAD 0x00800000 453 #define DC_TXCTL_TLINK 0x01000000 454 #define DC_TXCTL_TLAST 0x02000000 455 #define DC_TXCTL_NOCRC 0x04000000 456 #define DC_TXCTL_SETUP 0x08000000 457 #define DC_TXCTL_FILTTYPE1 0x10000000 458 #define DC_TXCTL_FIRSTFRAG 0x20000000 459 #define DC_TXCTL_LASTFRAG 0x40000000 460 #define DC_TXCTL_FINT 0x80000000 461 462 #define DC_FILTER_PERFECT 0x00000000 463 #define DC_FILTER_HASHPERF 0x00400000 464 #define DC_FILTER_INVERSE 0x10000000 465 #define DC_FILTER_HASHONLY 0x10400000 466 467 #define DC_MAXFRAGS 16 468 #ifdef DEVICE_POLLING 469 #define DC_RX_LIST_CNT 192 470 #else 471 #define DC_RX_LIST_CNT 64 472 #endif 473 #define DC_TX_LIST_CNT 256 474 #define DC_TX_LIST_RSVD 5 475 #define DC_MIN_FRAMELEN 60 476 #define DC_RXLEN 1536 477 478 #define DC_INC(x, y) (x) = (x + 1) % y 479 480 #define DC_LIST_ALIGN (sizeof(struct dc_desc)) 481 #define DC_RXBUF_ALIGN 4 482 483 /* Macros to easily get the DMA address of a descriptor. */ 484 #define DC_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF) 485 #define DC_RXDESC(sc, i) \ 486 (DC_ADDR_LO(sc->dc_ldata.dc_rx_list_paddr + (sizeof(struct dc_desc) * i))) 487 #define DC_TXDESC(sc, i) \ 488 (DC_ADDR_LO(sc->dc_ldata.dc_tx_list_paddr + (sizeof(struct dc_desc) * i))) 489 490 #if BYTE_ORDER == BIG_ENDIAN 491 #define DC_SP_MAC(x) ((x) << 16) 492 #else 493 #define DC_SP_MAC(x) (x) 494 #endif 495 496 struct dc_list_data { 497 struct dc_desc *dc_rx_list; 498 bus_addr_t dc_rx_list_paddr; 499 struct dc_desc *dc_tx_list; 500 bus_addr_t dc_tx_list_paddr; 501 }; 502 503 #define DC_RX_LIST_SZ ((sizeof(struct dc_desc) * DC_RX_LIST_CNT)) 504 #define DC_TX_LIST_SZ ((sizeof(struct dc_desc) * DC_TX_LIST_CNT)) 505 506 struct dc_chain_data { 507 struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; 508 struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; 509 bus_dmamap_t dc_rx_map[DC_RX_LIST_CNT]; 510 bus_dmamap_t dc_tx_map[DC_TX_LIST_CNT]; 511 uint32_t *dc_sbuf; 512 uint8_t dc_pad[DC_MIN_FRAMELEN]; 513 int dc_tx_pkts; 514 int dc_tx_first; 515 int dc_tx_prod; 516 int dc_tx_cons; 517 int dc_tx_cnt; 518 int dc_rx_prod; 519 }; 520 521 struct dc_mediainfo { 522 int dc_media; 523 uint8_t *dc_gp_ptr; 524 uint8_t dc_gp_len; 525 uint8_t *dc_reset_ptr; 526 uint8_t dc_reset_len; 527 struct dc_mediainfo *dc_next; 528 }; 529 530 531 struct dc_type { 532 uint32_t dc_devid; 533 uint8_t dc_minrev; 534 const char *dc_name; 535 }; 536 537 /* 538 * Registers specific to clone devices. 539 * This mainly relates to RX filter programming: not all 21x4x clones 540 * use the standard DEC filter programming mechanism. 541 */ 542 543 /* 544 * ADMtek specific registers and constants for the AL981 and AN983. 545 * The AN983 doesn't use the magic PHY registers. 546 */ 547 #define DC_AL_CR 0x88 /* command register */ 548 #define DC_AL_PAR0 0xA4 /* station address */ 549 #define DC_AL_PAR1 0xA8 /* station address */ 550 #define DC_AL_MAR0 0xAC /* multicast hash filter */ 551 #define DC_AL_MAR1 0xB0 /* multicast hash filter */ 552 #define DC_AL_BMCR 0xB4 /* built in PHY control */ 553 #define DC_AL_BMSR 0xB8 /* built in PHY status */ 554 #define DC_AL_VENID 0xBC /* built in PHY ID0 */ 555 #define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ 556 #define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ 557 #define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ 558 #define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ 559 560 #define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */ 561 #define DC_ADMTEK_PHYADDR 0x1 562 #define DC_AL_EE_NODEADDR 4 563 /* End of ADMtek specific registers */ 564 565 /* 566 * ASIX specific registers. 567 */ 568 #define DC_AX_FILTIDX 0x68 /* RX filter index */ 569 #define DC_AX_FILTDATA 0x70 /* RX filter data */ 570 571 /* 572 * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). 573 */ 574 #define DC_AX_NETCFG_RX_BROAD 0x00000100 575 576 /* 577 * RX Filter Index Register values 578 */ 579 #define DC_AX_FILTIDX_PAR0 0x00000000 580 #define DC_AX_FILTIDX_PAR1 0x00000001 581 #define DC_AX_FILTIDX_MAR0 0x00000002 582 #define DC_AX_FILTIDX_MAR1 0x00000003 583 /* End of ASIX specific registers */ 584 585 /* 586 * Macronix specific registers. The Macronix chips have a special 587 * register for reading the NWAY status, which we don't use, plus 588 * a magic packet register, which we need to tweak a bit per the 589 * Macronix application notes. 590 */ 591 #define DC_MX_MAGICPACKET 0x80 592 #define DC_MX_NWAYSTAT 0xA0 593 594 /* 595 * Magic packet register 596 */ 597 #define DC_MX_MPACK_DISABLE 0x00400000 598 599 /* 600 * NWAY status register. 601 */ 602 #define DC_MX_NWAY_10BTHALF 0x08000000 603 #define DC_MX_NWAY_10BTFULL 0x10000000 604 #define DC_MX_NWAY_100BTHALF 0x20000000 605 #define DC_MX_NWAY_100BTFULL 0x40000000 606 #define DC_MX_NWAY_100BT4 0x80000000 607 608 /* 609 * These are magic values that must be written into CSR16 610 * (DC_MX_MAGICPACKET) in order to put the chip into proper 611 * operating mode. The magic numbers are documented in the 612 * Macronix 98715 application notes. 613 */ 614 #define DC_MX_MAGIC_98713 0x0F370000 615 #define DC_MX_MAGIC_98713A 0x0B3C0000 616 #define DC_MX_MAGIC_98715 0x0B3C0000 617 #define DC_MX_MAGIC_98725 0x0B3C0000 618 /* End of Macronix specific registers */ 619 620 /* 621 * PNIC 82c168/82c169 specific registers. 622 * The PNIC has its own special NWAY support, which doesn't work, 623 * and shortcut ways of reading the EEPROM and MII bus. 624 */ 625 #define DC_PN_GPIO 0x60 /* general purpose pins control */ 626 #define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ 627 #define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ 628 #define DC_PN_MII 0xA0 /* MII access register */ 629 #define DC_PN_NWAY 0xB8 /* Internal NWAY register */ 630 631 /* Serial I/O EEPROM register */ 632 #define DC_PN_SIOCTL_DATA 0x0000003F 633 #define DC_PN_SIOCTL_OPCODE 0x00000300 634 #define DC_PN_SIOCTL_BUSY 0x80000000 635 636 #define DC_PN_EEOPCODE_ERASE 0x00000300 637 #define DC_PN_EEOPCODE_READ 0x00000600 638 #define DC_PN_EEOPCODE_WRITE 0x00000100 639 640 /* 641 * The first two general purpose pins control speed selection and 642 * 100Mbps loopback on the 82c168 chip. The control bits should always 643 * be set (to make the data pins outputs) and the speed selction and 644 * loopback bits set accordingly when changing media. Physically, this 645 * will set the state of a relay mounted on the card. 646 */ 647 #define DC_PN_GPIO_DATA0 0x000000001 648 #define DC_PN_GPIO_DATA1 0x000000002 649 #define DC_PN_GPIO_DATA2 0x000000004 650 #define DC_PN_GPIO_DATA3 0x000000008 651 #define DC_PN_GPIO_CTL0 0x000000010 652 #define DC_PN_GPIO_CTL1 0x000000020 653 #define DC_PN_GPIO_CTL2 0x000000040 654 #define DC_PN_GPIO_CTL3 0x000000080 655 #define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ 656 #define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ 657 #define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 658 #define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 659 #define DC_PN_GPIO_SETBIT(sc, r) \ 660 DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) 661 #define DC_PN_GPIO_CLRBIT(sc, r) \ 662 { \ 663 DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ 664 DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ 665 } 666 667 /* shortcut MII access register */ 668 #define DC_PN_MII_DATA 0x0000FFFF 669 #define DC_PN_MII_RESERVER 0x00020000 670 #define DC_PN_MII_REGADDR 0x007C0000 671 #define DC_PN_MII_PHYADDR 0x0F800000 672 #define DC_PN_MII_OPCODE 0x30000000 673 #define DC_PN_MII_BUSY 0x80000000 674 675 #define DC_PN_MIIOPCODE_READ 0x60020000 676 #define DC_PN_MIIOPCODE_WRITE 0x50020000 677 678 /* Internal NWAY bits */ 679 #define DC_PN_NWAY_RESET 0x00000001 /* reset */ 680 #define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ 681 #define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ 682 #define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ 683 #define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ 684 #define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ 685 #define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ 686 #define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ 687 #define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ 688 #define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ 689 #define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ 690 #define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ 691 #define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ 692 #define DC_PN_NWAY_CAP10HDX 0x00002000 693 #define DC_PN_NWAY_CAP10FDX 0x00004000 694 #define DC_PN_NWAY_CAP100FDX 0x00008000 695 #define DC_PN_NWAY_CAP100HDX 0x00010000 696 #define DC_PN_NWAY_CAP100T4 0x00020000 697 #define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ 698 #define DC_PN_NWAY_REMFAULT 0x04000000 699 #define DC_PN_NWAY_LPAR10HDX 0x08000000 700 #define DC_PN_NWAY_LPAR10FDX 0x10000000 701 #define DC_PN_NWAY_LPAR100FDX 0x20000000 702 #define DC_PN_NWAY_LPAR100HDX 0x40000000 703 #define DC_PN_NWAY_LPAR100T4 0x80000000 704 705 /* End of PNIC specific registers */ 706 707 /* 708 * CONEXANT specific registers. 709 */ 710 711 #define DC_CONEXANT_PHYADDR 0x1 712 #define DC_CONEXANT_EE_NODEADDR 0x19A 713 714 /* End of CONEXANT specific registers */ 715 716 /* 717 * ULi M5263 specific registers. 718 */ 719 #define DC_ULI_FILTER_NPERF 14 720 721 #define DC_ULI_PHY_DATA_MASK 0x0000FFFF 722 #define DC_ULI_PHY_REG_MASK 0x001F0000 723 #define DC_ULI_PHY_ADDR_MASK 0x03E00000 724 #define DC_ULI_PHY_OP_WRITE 0x04000000 725 #define DC_ULI_PHY_OP_READ 0x08000000 726 #define DC_ULI_PHY_OP_DONE 0x10000000 727 728 #define DC_ULI_PHY_DATA_SHIFT 0 729 #define DC_ULI_PHY_REG_SHIFT 16 730 #define DC_ULI_PHY_ADDR_SHIFT 21 731 732 /* End of ULi M5263 specific registers */ 733 734 struct dc_softc { 735 struct ifnet *dc_ifp; /* interface info */ 736 device_t dc_dev; /* device info */ 737 bus_space_handle_t dc_bhandle; /* bus space handle */ 738 bus_space_tag_t dc_btag; /* bus space tag */ 739 bus_dma_tag_t dc_ptag; /* parent DMA tag */ 740 bus_dmamap_t dc_sparemap; 741 bus_dma_tag_t dc_rx_ltag; /* tag for RX descriptors */ 742 bus_dmamap_t dc_rx_lmap; 743 bus_dma_tag_t dc_tx_ltag; /* tag for TX descriptors */ 744 bus_dmamap_t dc_tx_lmap; 745 bus_dma_tag_t dc_stag; /* tag for the setup frame */ 746 bus_dmamap_t dc_smap; /* map for the setup frame */ 747 bus_addr_t dc_saddr; /* DMA address of setup frame */ 748 bus_dma_tag_t dc_rx_mtag; /* tag for RX mbufs */ 749 bus_dma_tag_t dc_tx_mtag; /* tag for TX mbufs */ 750 void *dc_intrhand; 751 struct resource *dc_irq; 752 struct resource *dc_res; 753 const struct dc_type *dc_info; /* adapter info */ 754 device_t dc_miibus; 755 uint8_t dc_type; 756 uint8_t dc_pmode; 757 uint8_t dc_link; 758 uint8_t dc_cachesize; 759 int dc_romwidth; 760 int dc_pnic_rx_bug_save; 761 unsigned char *dc_pnic_rx_buf; 762 int dc_if_flags; 763 uint32_t dc_flags; 764 uint32_t dc_txthresh; 765 uint32_t dc_eaddr[2]; 766 uint8_t *dc_srom; 767 struct dc_mediainfo *dc_mi; 768 struct dc_list_data dc_ldata; 769 struct dc_chain_data dc_cdata; 770 struct callout dc_stat_ch; 771 struct callout dc_wdog_ch; 772 int dc_wdog_timer; 773 struct mtx dc_mtx; 774 #ifdef DEVICE_POLLING 775 int rxcycles; /* ... when polling */ 776 #endif 777 int suspended; /* 0 = normal 1 = suspended */ 778 }; 779 780 781 #define DC_LOCK(_sc) mtx_lock(&(_sc)->dc_mtx) 782 #define DC_UNLOCK(_sc) mtx_unlock(&(_sc)->dc_mtx) 783 #define DC_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->dc_mtx, MA_OWNED) 784 785 #define DC_TX_POLL 0x00000001 786 #define DC_TX_COALESCE 0x00000002 787 #define DC_TX_ADMTEK_WAR 0x00000004 788 #define DC_TX_USE_TX_INTR 0x00000008 789 #define DC_RX_FILTER_TULIP 0x00000010 790 #define DC_TX_INTR_FIRSTFRAG 0x00000020 791 #define DC_PNIC_RX_BUG_WAR 0x00000040 792 #define DC_TX_FIXED_RING 0x00000080 793 #define DC_TX_STORENFWD 0x00000100 794 #define DC_REDUCED_MII_POLL 0x00000200 795 #define DC_TX_INTR_ALWAYS 0x00000400 796 #define DC_21143_NWAY 0x00000800 797 #define DC_128BIT_HASH 0x00001000 798 #define DC_64BIT_HASH 0x00002000 799 #define DC_TULIP_LEDS 0x00004000 800 #define DC_TX_ALIGN 0x00010000 /* align mbuf on tx */ 801 802 /* 803 * register space access macros 804 */ 805 #define CSR_WRITE_4(sc, reg, val) \ 806 bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val) 807 808 #define CSR_READ_4(sc, reg) \ 809 bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg) 810 811 #define CSR_BARRIER_4(sc, reg, flags) \ 812 bus_space_barrier(sc->dc_btag, sc->dc_bhandle, reg, 4, flags) 813 814 #define DC_TIMEOUT 1000 815 816 /* 817 * General constants that are fun to know. 818 */ 819 820 /* 821 * DEC PCI vendor ID 822 */ 823 #define DC_VENDORID_DEC 0x1011 824 825 /* 826 * DEC/Intel 21143 PCI device ID 827 */ 828 #define DC_DEVICEID_21143 0x0019 829 830 /* 831 * Macronix PCI vendor ID 832 */ 833 #define DC_VENDORID_MX 0x10D9 834 835 /* 836 * Macronix PMAC device IDs. 837 */ 838 #define DC_DEVICEID_98713 0x0512 839 #define DC_DEVICEID_987x5 0x0531 840 #define DC_DEVICEID_98727 0x0532 841 #define DC_DEVICEID_98732 0x0532 842 843 /* Macronix PCI revision codes. */ 844 #define DC_REVISION_98713 0x00 845 #define DC_REVISION_98713A 0x10 846 #define DC_REVISION_98715 0x20 847 #define DC_REVISION_98715AEC_C 0x25 848 #define DC_REVISION_98725 0x30 849 850 /* 851 * Compex PCI vendor ID. 852 */ 853 #define DC_VENDORID_CP 0x11F6 854 855 /* 856 * Compex PMAC PCI device IDs. 857 */ 858 #define DC_DEVICEID_98713_CP 0x9881 859 860 /* 861 * Lite-On PNIC PCI vendor ID 862 */ 863 #define DC_VENDORID_LO 0x11AD 864 865 /* 866 * 82c168/82c169 PNIC device IDs. Both chips have the same device 867 * ID but different revisions. Revision 0x10 is the 82c168, and 868 * 0x20 is the 82c169. 869 */ 870 #define DC_DEVICEID_82C168 0x0002 871 872 #define DC_REVISION_82C168 0x10 873 #define DC_REVISION_82C169 0x20 874 875 /* 876 * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A 877 * with wake on lan/magic packet support. 878 */ 879 #define DC_DEVICEID_82C115 0xc115 880 881 /* 882 * Davicom vendor ID. 883 */ 884 #define DC_VENDORID_DAVICOM 0x1282 885 886 /* 887 * Davicom device IDs. 888 */ 889 #define DC_DEVICEID_DM9009 0x9009 890 #define DC_DEVICEID_DM9100 0x9100 891 #define DC_DEVICEID_DM9102 0x9102 892 893 /* 894 * The DM9102A has the same PCI device ID as the DM9102, 895 * but a higher revision code. 896 */ 897 #define DC_REVISION_DM9102 0x10 898 #define DC_REVISION_DM9102A 0x30 899 900 /* 901 * ADMtek vendor ID. 902 */ 903 #define DC_VENDORID_ADMTEK 0x1317 904 905 /* 906 * ADMtek device IDs. 907 */ 908 #define DC_DEVICEID_AL981 0x0981 909 #define DC_DEVICEID_AN983 0x0985 910 #define DC_DEVICEID_AN985 0x1985 911 #define DC_DEVICEID_ADM9511 0x9511 912 #define DC_DEVICEID_ADM9513 0x9513 913 914 /* 915 * 3COM PCI vendor ID 916 */ 917 #define DC_VENDORID_3COM 0x10b7 918 919 /* 920 * 3COM OfficeConnect 10/100B (3CSOHO100B-TX) 921 */ 922 #define DC_DEVICEID_3CSOHOB 0x9300 923 924 /* 925 * ASIX vendor ID. 926 */ 927 #define DC_VENDORID_ASIX 0x125B 928 929 /* 930 * ASIX device IDs. 931 */ 932 #define DC_DEVICEID_AX88140A 0x1400 933 934 /* 935 * The ASIX AX88140 and ASIX AX88141 have the same vendor and 936 * device IDs but different revision values. 937 */ 938 #define DC_REVISION_88140 0x00 939 #define DC_REVISION_88141 0x10 940 941 /* 942 * Accton vendor ID. 943 */ 944 #define DC_VENDORID_ACCTON 0x1113 945 946 /* 947 * Accton device IDs. 948 */ 949 #define DC_DEVICEID_EN1217 0x1217 950 #define DC_DEVICEID_EN2242 0x1216 951 952 /* 953 * Xircom vendor ID 954 */ 955 #define DC_VENDORID_XIRCOM 0x115d 956 957 /* 958 * Xircom device IDs. 959 */ 960 #define DC_DEVICEID_X3201 0x0003 961 962 /* 963 * D-Link vendor ID 964 */ 965 #define DC_VENDORID_DLINK 0x1186 966 967 /* 968 * D-Link device IDs. 969 */ 970 #define DC_DEVICEID_DRP32TXD 0x1561 971 972 /* 973 * Abocom vendor ID 974 */ 975 #define DC_VENDORID_ABOCOM 0x13d1 976 977 /* 978 * Abocom device IDs. 979 */ 980 #define DC_DEVICEID_FE2500 0xAB02 981 #define DC_DEVICEID_FE2500MX 0xab08 982 983 /* 984 * Conexant vendor ID. 985 */ 986 #define DC_VENDORID_CONEXANT 0x14f1 987 988 /* 989 * Conexant device IDs. 990 */ 991 #define DC_DEVICEID_RS7112 0x1803 992 993 /* 994 * Planex vendor ID 995 */ 996 #define DC_VENDORID_PLANEX 0x14ea 997 998 /* 999 * Planex device IDs. 1000 */ 1001 #define DC_DEVICEID_FNW3602T 0xab08 1002 1003 /* 1004 * Not sure who this vendor should be, so we'll go with HAWKING until 1005 * I can locate the right one. 1006 */ 1007 #define DC_VENDORID_HAWKING 0x17b3 1008 1009 /* 1010 * Sure looks like an abocom device ID, but it found on my hawking PN672TX 1011 * card. Use that for now, and upgrade later. 1012 */ 1013 #define DC_DEVICEID_HAWKING_PN672TX 0xab08 1014 1015 /* 1016 * Microsoft device ID. 1017 */ 1018 #define DC_VENDORID_MICROSOFT 0x1414 1019 1020 /* 1021 * Supported Microsoft PCI and CardBus NICs. These are really 1022 * ADMtek parts in disguise. 1023 */ 1024 1025 #define DC_DEVICEID_MSMN120 0x0001 1026 #define DC_DEVICEID_MSMN130 0x0002 1027 1028 /* 1029 * Linksys vendor ID. 1030 */ 1031 #define DC_VENDORID_LINKSYS 0x1737 1032 1033 /* 1034 * Linksys device IDs. 1035 */ 1036 #define DC_DEVICEID_PCMPC200_AB08 0xab08 1037 #define DC_DEVICEID_PCMPC200_AB09 0xab09 1038 1039 /* 1040 * ULi vendor ID. 1041 */ 1042 #define DC_VENDORID_ULI 0x10b9 1043 1044 /* 1045 * ULi device IDs. 1046 */ 1047 #define DC_DEVICEID_M5261 0x5261 1048 #define DC_DEVICEID_M5263 0x5263 1049 1050 #define DC_DEVID(vendor, device) ((device) << 16 | (vendor)) 1051 1052 /* 1053 * PCI low memory base and low I/O base register, and 1054 * other PCI registers. 1055 */ 1056 1057 #define DC_PCI_CFBIO PCIR_BAR(0) /* Base I/O address */ 1058 #define DC_PCI_CFBMA PCIR_BAR(1) /* Base memory address */ 1059 #define DC_PCI_CFDD 0x40 /* Device and driver area */ 1060 #define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ 1061 #define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ 1062 #define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ 1063 #define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ 1064 #define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ 1065 1066 #define DC_21143_PB_REV 0x00000030 1067 #define DC_21143_TB_REV 0x00000030 1068 #define DC_21143_PC_REV 0x00000030 1069 #define DC_21143_TC_REV 0x00000030 1070 #define DC_21143_PD_REV 0x00000041 1071 #define DC_21143_TD_REV 0x00000041 1072 1073 /* Configuration and driver area */ 1074 #define DC_CFDD_DRVUSE 0x0000FFFF 1075 #define DC_CFDD_SNOOZE_MODE 0x40000000 1076 #define DC_CFDD_SLEEP_MODE 0x80000000 1077 1078 /* Configuration wake-up command register */ 1079 #define DC_CWUC_MUST_BE_ZERO 0x00000001 1080 #define DC_CWUC_SECUREON_ENB 0x00000002 1081 #define DC_CWUC_FORCE_WUL 0x00000004 1082 #define DC_CWUC_BNC_ABILITY 0x00000008 1083 #define DC_CWUC_AUI_ABILITY 0x00000010 1084 #define DC_CWUC_TP10_ABILITY 0x00000020 1085 #define DC_CWUC_MII_ABILITY 0x00000040 1086 #define DC_CWUC_SYM_ABILITY 0x00000080 1087 #define DC_CWUC_LOCK 0x00000100 1088 1089 /* 1090 * SROM nonsense. 1091 */ 1092 1093 #define DC_ROM_SIZE(bits) (2 << (bits)) 1094 1095 #define DC_IB_CTLRCNT 0x13 1096 #define DC_IB_LEAF0_CNUM 0x1A 1097 #define DC_IB_LEAF0_OFFSET 0x1B 1098 1099 struct dc_info_leaf { 1100 uint16_t dc_conntype; 1101 uint8_t dc_blkcnt; 1102 uint8_t dc_rsvd; 1103 uint16_t dc_infoblk; 1104 }; 1105 1106 #define DC_CTYPE_10BT 0x0000 1107 #define DC_CTYPE_10BT_NWAY 0x0100 1108 #define DC_CTYPE_10BT_FDX 0x0204 1109 #define DC_CTYPE_10B2 0x0001 1110 #define DC_CTYPE_10B5 0x0002 1111 #define DC_CTYPE_100BT 0x0003 1112 #define DC_CTYPE_100BT_FDX 0x0205 1113 #define DC_CTYPE_100T4 0x0006 1114 #define DC_CTYPE_100FX 0x0007 1115 #define DC_CTYPE_100FX_FDX 0x0208 1116 #define DC_CTYPE_MII_10BT 0x0009 1117 #define DC_CTYPE_MII_10BT_FDX 0x020A 1118 #define DC_CTYPE_MII_100BT 0x000D 1119 #define DC_CTYPE_MII_100BT_FDX 0x020E 1120 #define DC_CTYPE_MII_100T4 0x000F 1121 #define DC_CTYPE_MII_100FX 0x0010 1122 #define DC_CTYPE_MII_100FX_FDX 0x0211 1123 #define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800 1124 #define DC_CTYPE_PUP_AUTOSENSE 0x8800 1125 #define DC_CTYPE_NOMEDIA 0xFFFF 1126 1127 #define DC_EBLOCK_SIA 0x0002 1128 #define DC_EBLOCK_MII 0x0003 1129 #define DC_EBLOCK_SYM 0x0004 1130 #define DC_EBLOCK_RESET 0x0005 1131 #define DC_EBLOCK_PHY_SHUTDOWN 0x0006 1132 1133 struct dc_leaf_hdr { 1134 uint16_t dc_mtype; 1135 uint8_t dc_mcnt; 1136 uint8_t dc_rsvd; 1137 }; 1138 1139 struct dc_eblock_hdr { 1140 uint8_t dc_len; 1141 uint8_t dc_type; 1142 }; 1143 1144 struct dc_eblock_sia { 1145 struct dc_eblock_hdr dc_sia_hdr; 1146 uint8_t dc_sia_code; 1147 union { 1148 struct dc_sia_ext { /* if (dc_sia_code & DC_SIA_CODE_EXT) */ 1149 uint8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */ 1150 uint8_t dc_sia_gpio_ctl[2]; 1151 uint8_t dc_sia_gpio_dat[2]; 1152 } dc_sia_ext; 1153 struct dc_sia_noext { 1154 uint8_t dc_sia_gpio_ctl[2]; 1155 uint8_t dc_sia_gpio_dat[2]; 1156 } dc_sia_noext; 1157 } dc_un; 1158 }; 1159 1160 #define DC_SIA_CODE_10BT 0x00 1161 #define DC_SIA_CODE_10B2 0x01 1162 #define DC_SIA_CODE_10B5 0x02 1163 #define DC_SIA_CODE_10BT_FDX 0x04 1164 #define DC_SIA_CODE_EXT 0x40 1165 1166 /* 1167 * Note that the first word in the gpr and reset 1168 * sequences is always a control word. 1169 */ 1170 struct dc_eblock_mii { 1171 struct dc_eblock_hdr dc_mii_hdr; 1172 uint8_t dc_mii_phynum; 1173 uint8_t dc_gpr_len; 1174 /* uint16_t dc_gpr_dat[n]; */ 1175 /* uint8_t dc_reset_len; */ 1176 /* uint16_t dc_reset_dat[n]; */ 1177 /* There are other fields after these, but we don't 1178 * care about them since they can be determined by looking 1179 * at the PHY. 1180 */ 1181 }; 1182 1183 struct dc_eblock_sym { 1184 struct dc_eblock_hdr dc_sym_hdr; 1185 uint8_t dc_sym_code; 1186 uint8_t dc_sym_gpio_ctl[2]; 1187 uint8_t dc_sym_gpio_dat[2]; 1188 uint8_t dc_sym_cmd[2]; 1189 }; 1190 1191 #define DC_SYM_CODE_100BT 0x03 1192 #define DC_SYM_CODE_100BT_FDX 0x05 1193 #define DC_SYM_CODE_100T4 0x06 1194 #define DC_SYM_CODE_100FX 0x07 1195 #define DC_SYM_CODE_100FX_FDX 0x08 1196 1197 struct dc_eblock_reset { 1198 struct dc_eblock_hdr dc_reset_hdr; 1199 uint8_t dc_reset_len; 1200 /* uint16_t dc_reset_dat[n]; */ 1201 }; 1202