1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * 21143 and clone common register definitions. 37 */ 38 39 #define DC_BUSCTL 0x00 /* bus control */ 40 #define DC_TXSTART 0x08 /* tx start demand */ 41 #define DC_RXSTART 0x10 /* rx start demand */ 42 #define DC_RXADDR 0x18 /* rx descriptor list start addr */ 43 #define DC_TXADDR 0x20 /* tx descriptor list start addr */ 44 #define DC_ISR 0x28 /* interrupt status register */ 45 #define DC_NETCFG 0x30 /* network config register */ 46 #define DC_IMR 0x38 /* interrupt mask */ 47 #define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ 48 #define DC_SIO 0x48 /* MII and ROM/EEPROM access */ 49 #define DC_ROM 0x50 /* ROM programming address */ 50 #define DC_TIMER 0x58 /* general timer */ 51 #define DC_10BTSTAT 0x60 /* SIA status */ 52 #define DC_SIARESET 0x68 /* SIA connectivity */ 53 #define DC_10BTCTRL 0x70 /* SIA transmit and receive */ 54 #define DC_WATCHDOG 0x78 /* SIA and general purpose port */ 55 56 /* 57 * There are two general 'types' of MX chips that we need to be 58 * concerned with. One is the original 98713, which has its internal 59 * NWAY support controlled via the MDIO bits in the serial I/O 60 * register. The other is everything else (from the 98713A on up), 61 * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, 62 * just like the 21143. This type setting also governs which of the 63 * 'magic' numbers we write to CSR16. The PNIC II falls into the 64 * 98713A/98715/98715A/98725 category. 65 */ 66 #define DC_TYPE_98713 0x1 67 #define DC_TYPE_98713A 0x2 68 #define DC_TYPE_987x5 0x3 69 70 /* Other type of supported chips. */ 71 #define DC_TYPE_21143 0x4 /* Intel 21143 */ 72 #define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ 73 #define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ 74 #define DC_TYPE_AN985 0x7 /* ADMtek AN985 Centaur */ 75 #define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ 76 #define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ 77 #define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ 78 79 #define DC_IS_MACRONIX(x) \ 80 (x->dc_type == DC_TYPE_98713 || \ 81 x->dc_type == DC_TYPE_98713A || \ 82 x->dc_type == DC_TYPE_987x5) 83 84 #define DC_IS_ADMTEK(x) \ 85 (x->dc_type == DC_TYPE_AL981 || \ 86 x->dc_type == DC_TYPE_AN985) 87 88 #define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) 89 #define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) 90 #define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) 91 #define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN985) 92 #define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) 93 #define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) 94 #define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) 95 96 /* MII/symbol mode port types */ 97 #define DC_PMODE_MII 0x1 98 #define DC_PMODE_SYM 0x2 99 100 /* 101 * Bus control bits. 102 */ 103 #define DC_BUSCTL_RESET 0x00000001 104 #define DC_BUSCTL_ARBITRATION 0x00000002 105 #define DC_BUSCTL_SKIPLEN 0x0000007C 106 #define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 107 #define DC_BUSCTL_BURSTLEN 0x00003F00 108 #define DC_BUSCTL_CACHEALIGN 0x0000C000 109 #define DC_BUSCTL_TXPOLL 0x000E0000 110 #define DC_BUSCTL_DBO 0x00100000 111 #define DC_BUSCTL_MRME 0x00200000 112 #define DC_BUSCTL_MRLE 0x00800000 113 #define DC_BUSCTL_MWIE 0x01000000 114 #define DC_BUSCTL_ONNOW_ENB 0x04000000 115 116 #define DC_SKIPLEN_1LONG 0x00000004 117 #define DC_SKIPLEN_2LONG 0x00000008 118 #define DC_SKIPLEN_3LONG 0x00000010 119 #define DC_SKIPLEN_4LONG 0x00000020 120 #define DC_SKIPLEN_5LONG 0x00000040 121 122 #define DC_CACHEALIGN_NONE 0x00000000 123 #define DC_CACHEALIGN_8LONG 0x00004000 124 #define DC_CACHEALIGN_16LONG 0x00008000 125 #define DC_CACHEALIGN_32LONG 0x0000C000 126 127 #define DC_BURSTLEN_USECA 0x00000000 128 #define DC_BURSTLEN_1LONG 0x00000100 129 #define DC_BURSTLEN_2LONG 0x00000200 130 #define DC_BURSTLEN_4LONG 0x00000400 131 #define DC_BURSTLEN_8LONG 0x00000800 132 #define DC_BURSTLEN_16LONG 0x00001000 133 #define DC_BURSTLEN_32LONG 0x00002000 134 135 #define DC_TXPOLL_OFF 0x00000000 136 #define DC_TXPOLL_1 0x00020000 137 #define DC_TXPOLL_2 0x00040000 138 #define DC_TXPOLL_3 0x00060000 139 #define DC_TXPOLL_4 0x00080000 140 #define DC_TXPOLL_5 0x000A0000 141 #define DC_TXPOLL_6 0x000C0000 142 #define DC_TXPOLL_7 0x000E0000 143 144 /* 145 * Interrupt status bits. 146 */ 147 #define DC_ISR_TX_OK 0x00000001 148 #define DC_ISR_TX_IDLE 0x00000002 149 #define DC_ISR_TX_NOBUF 0x00000004 150 #define DC_ISR_TX_JABBERTIMEO 0x00000008 151 #define DC_ISR_LINKGOOD 0x00000010 152 #define DC_ISR_TX_UNDERRUN 0x00000020 153 #define DC_ISR_RX_OK 0x00000040 154 #define DC_ISR_RX_NOBUF 0x00000080 155 #define DC_ISR_RX_READ 0x00000100 156 #define DC_ISR_RX_WATDOGTIMEO 0x00000200 157 #define DC_ISR_TX_EARLY 0x00000400 158 #define DC_ISR_TIMER_EXPIRED 0x00000800 159 #define DC_ISR_LINKFAIL 0x00001000 160 #define DC_ISR_BUS_ERR 0x00002000 161 #define DC_ISR_RX_EARLY 0x00004000 162 #define DC_ISR_ABNORMAL 0x00008000 163 #define DC_ISR_NORMAL 0x00010000 164 #define DC_ISR_RX_STATE 0x000E0000 165 #define DC_ISR_TX_STATE 0x00700000 166 #define DC_ISR_BUSERRTYPE 0x03800000 167 #define DC_ISR_100MBPSLINK 0x08000000 168 #define DC_ISR_MAGICKPACK 0x10000000 169 170 #define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ 171 #define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ 172 #define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ 173 #define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ 174 #define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ 175 #define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ 176 #define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ 177 #define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ 178 179 #define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ 180 #define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ 181 #define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ 182 #define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ 183 #define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ 184 #define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ 185 #define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ 186 #define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ 187 188 /* 189 * Network config bits. 190 */ 191 #define DC_NETCFG_RX_HASHPERF 0x00000001 192 #define DC_NETCFG_RX_ON 0x00000002 193 #define DC_NETCFG_RX_HASHONLY 0x00000004 194 #define DC_NETCFG_RX_BADFRAMES 0x00000008 195 #define DC_NETCFG_RX_INVFILT 0x00000010 196 #define DC_NETCFG_BACKOFFCNT 0x00000020 197 #define DC_NETCFG_RX_PROMISC 0x00000040 198 #define DC_NETCFG_RX_ALLMULTI 0x00000080 199 #define DC_NETCFG_FULLDUPLEX 0x00000200 200 #define DC_NETCFG_LOOPBACK 0x00000C00 201 #define DC_NETCFG_FORCECOLL 0x00001000 202 #define DC_NETCFG_TX_ON 0x00002000 203 #define DC_NETCFG_TX_THRESH 0x0000C000 204 #define DC_NETCFG_TX_BACKOFF 0x00020000 205 #define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ 206 #define DC_NETCFG_HEARTBEAT 0x00080000 207 #define DC_NETCFG_STORENFWD 0x00200000 208 #define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ 209 #define DC_NETCFG_PCS 0x00800000 210 #define DC_NETCFG_SCRAMBLER 0x01000000 211 #define DC_NETCFG_NO_RXCRC 0x02000000 212 #define DC_NETCFG_RX_ALL 0x40000000 213 #define DC_NETCFG_CAPEFFECT 0x80000000 214 215 #define DC_OPMODE_NORM 0x00000000 216 #define DC_OPMODE_INTLOOP 0x00000400 217 #define DC_OPMODE_EXTLOOP 0x00000800 218 219 #define DC_TXTHRESH_72BYTES 0x00000000 220 #define DC_TXTHRESH_96BYTES 0x00004000 221 #define DC_TXTHRESH_128BYTES 0x00008000 222 #define DC_TXTHRESH_160BYTES 0x0000C000 223 224 225 /* 226 * Interrupt mask bits. 227 */ 228 #define DC_IMR_TX_OK 0x00000001 229 #define DC_IMR_TX_IDLE 0x00000002 230 #define DC_IMR_TX_NOBUF 0x00000004 231 #define DC_IMR_TX_JABBERTIMEO 0x00000008 232 #define DC_IMR_LINKGOOD 0x00000010 233 #define DC_IMR_TX_UNDERRUN 0x00000020 234 #define DC_IMR_RX_OK 0x00000040 235 #define DC_IMR_RX_NOBUF 0x00000080 236 #define DC_IMR_RX_READ 0x00000100 237 #define DC_IMR_RX_WATDOGTIMEO 0x00000200 238 #define DC_IMR_TX_EARLY 0x00000400 239 #define DC_IMR_TIMER_EXPIRED 0x00000800 240 #define DC_IMR_LINKFAIL 0x00001000 241 #define DC_IMR_BUS_ERR 0x00002000 242 #define DC_IMR_RX_EARLY 0x00004000 243 #define DC_IMR_ABNORMAL 0x00008000 244 #define DC_IMR_NORMAL 0x00010000 245 #define DC_IMR_100MBPSLINK 0x08000000 246 #define DC_IMR_MAGICKPACK 0x10000000 247 248 #define DC_INTRS \ 249 (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ 250 DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ 251 DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) 252 /* 253 * Serial I/O (EEPROM/ROM) bits. 254 */ 255 #define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ 256 #define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ 257 #define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ 258 #define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ 259 #define DC_SIO_ROMDATA4 0x00000010 260 #define DC_SIO_ROMDATA5 0x00000020 261 #define DC_SIO_ROMDATA6 0x00000040 262 #define DC_SIO_ROMDATA7 0x00000080 263 #define DC_SIO_EESEL 0x00000800 264 #define DC_SIO_ROMSEL 0x00001000 265 #define DC_SIO_ROMCTL_WRITE 0x00002000 266 #define DC_SIO_ROMCTL_READ 0x00004000 267 #define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ 268 #define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ 269 #define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ 270 #define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ 271 272 #define DC_EECMD_WRITE 0x140 273 #define DC_EECMD_READ 0x180 274 #define DC_EECMD_ERASE 0x1c0 275 276 #define DC_EE_NODEADDR_OFFSET 0x70 277 #define DC_EE_NODEADDR 10 278 279 /* 280 * General purpose timer register 281 */ 282 #define DC_TIMER_VALUE 0x0000FFFF 283 #define DC_TIMER_CONTINUOUS 0x00010000 284 285 /* 286 * 10baseT status register 287 */ 288 #define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ 289 #define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ 290 #define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ 291 #define DC_TSTAT_AUTOPOLARITY 0x00000008 292 #define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ 293 #define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ 294 #define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ 295 #define DC_TSTAT_REMFAULT 0x00000800 296 #define DC_TSTAT_ANEGSTAT 0x00007000 297 #define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ 298 #define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ 299 300 #define DC_ASTAT_DISABLE 0x00000000 301 #define DC_ASTAT_TXDISABLE 0x00001000 302 #define DC_ASTAT_ABDETECT 0x00002000 303 #define DC_ASTAT_ACKDETECT 0x00003000 304 #define DC_ASTAT_CMPACKDETECT 0x00004000 305 #define DC_ASTAT_AUTONEGCMP 0x00005000 306 #define DC_ASTAT_LINKCHECK 0x00006000 307 308 /* 309 * PHY reset register 310 */ 311 #define DC_SIA_RESET 0x00000001 312 #define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ 313 314 /* 315 * 10baseT control register 316 */ 317 #define DC_TCTL_ENCODER_ENB 0x00000001 318 #define DC_TCTL_LOOPBACK 0x00000002 319 #define DC_TCTL_DRIVER_ENB 0x00000004 320 #define DC_TCTL_LNKPULSE_ENB 0x00000008 321 #define DC_TCTL_HALFDUPLEX 0x00000040 322 #define DC_TCTL_AUTONEGENBL 0x00000080 323 #define DC_TCTL_RX_SQUELCH 0x00000100 324 #define DC_TCTL_COLL_SQUELCH 0x00000200 325 #define DC_TCTL_COLL_DETECT 0x00000400 326 #define DC_TCTL_SQE_ENB 0x00000800 327 #define DC_TCTL_LINKTEST 0x00001000 328 #define DC_TCTL_AUTOPOLARITY 0x00002000 329 #define DC_TCTL_SET_POL_PLUS 0x00004000 330 #define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ 331 #define DC_TCTL_100BTXHALF 0x00010000 332 #define DC_TCTL_100BTXFULL 0x00020000 333 #define DC_TCTL_100BT4 0x00040000 334 335 /* 336 * Watchdog timer register 337 */ 338 #define DC_WDOG_JABBERDIS 0x00000001 339 #define DC_WDOG_HOSTUNJAB 0x00000002 340 #define DC_WDOG_JABBERCLK 0x00000004 341 #define DC_WDOG_RXWDOGDIS 0x00000010 342 #define DC_WDOG_RXWDOGCLK 0x00000020 343 #define DC_WDOG_MUSTBEZERO 0x00000100 344 #define DC_WDOG_CTLWREN 0x08000000 345 346 /* 347 * Size of a setup frame. 348 */ 349 #define DC_SFRAME_LEN 192 350 351 /* 352 * 21x4x TX/RX list structure. 353 */ 354 355 struct dc_desc { 356 u_int32_t dc_status; 357 u_int32_t dc_ctl; 358 u_int32_t dc_ptr1; 359 u_int32_t dc_ptr2; 360 }; 361 362 #define dc_data dc_ptr1 363 #define dc_next dc_ptr2 364 365 #define DC_RXSTAT_FIFOOFLOW 0x00000001 366 #define DC_RXSTAT_CRCERR 0x00000002 367 #define DC_RXSTAT_DRIBBLE 0x00000004 368 #define DC_RXSTAT_WATCHDOG 0x00000010 369 #define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ 370 #define DC_RXSTAT_COLLSEEN 0x00000040 371 #define DC_RXSTAT_GIANT 0x00000080 372 #define DC_RXSTAT_LASTFRAG 0x00000100 373 #define DC_RXSTAT_FIRSTFRAG 0x00000200 374 #define DC_RXSTAT_MULTICAST 0x00000400 375 #define DC_RXSTAT_RUNT 0x00000800 376 #define DC_RXSTAT_RXTYPE 0x00003000 377 #define DC_RXSTAT_RXERR 0x00008000 378 #define DC_RXSTAT_RXLEN 0x3FFF0000 379 #define DC_RXSTAT_OWN 0x80000000 380 381 #define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) 382 #define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) 383 384 #define DC_RXCTL_BUFLEN1 0x00000FFF 385 #define DC_RXCTL_BUFLEN2 0x00FFF000 386 #define DC_RXCTL_RLINK 0x01000000 387 #define DC_RXCTL_RLAST 0x02000000 388 389 #define DC_TXSTAT_DEFER 0x00000001 390 #define DC_TXSTAT_UNDERRUN 0x00000002 391 #define DC_TXSTAT_LINKFAIL 0x00000003 392 #define DC_TXSTAT_COLLCNT 0x00000078 393 #define DC_TXSTAT_SQE 0x00000080 394 #define DC_TXSTAT_EXCESSCOLL 0x00000100 395 #define DC_TXSTAT_LATECOLL 0x00000200 396 #define DC_TXSTAT_NOCARRIER 0x00000400 397 #define DC_TXSTAT_CARRLOST 0x00000800 398 #define DC_TXSTAT_JABTIMEO 0x00004000 399 #define DC_TXSTAT_ERRSUM 0x00008000 400 #define DC_TXSTAT_OWN 0x80000000 401 402 #define DC_TXCTL_BUFLEN1 0x000007FF 403 #define DC_TXCTL_BUFLEN2 0x003FF800 404 #define DC_TXCTL_FILTTYPE0 0x00400000 405 #define DC_TXCTL_PAD 0x00800000 406 #define DC_TXCTL_TLINK 0x01000000 407 #define DC_TXCTL_TLAST 0x02000000 408 #define DC_TXCTL_NOCRC 0x04000000 409 #define DC_TXCTL_SETUP 0x08000000 410 #define DC_TXCTL_FILTTYPE1 0x10000000 411 #define DC_TXCTL_FIRSTFRAG 0x20000000 412 #define DC_TXCTL_LASTFRAG 0x40000000 413 #define DC_TXCTL_FINT 0x80000000 414 415 #define DC_FILTER_PERFECT 0x00000000 416 #define DC_FILTER_HASHPERF 0x00400000 417 #define DC_FILTER_INVERSE 0x10000000 418 #define DC_FILTER_HASHONLY 0x10400000 419 420 #define DC_MAXFRAGS 16 421 #define DC_RX_LIST_CNT 64 422 #define DC_TX_LIST_CNT 256 423 #define DC_MIN_FRAMELEN 60 424 #define DC_RXLEN 1536 425 426 #define DC_INC(x, y) (x) = (x + 1) % y 427 428 struct dc_list_data { 429 struct dc_desc dc_rx_list[DC_RX_LIST_CNT]; 430 struct dc_desc dc_tx_list[DC_TX_LIST_CNT]; 431 }; 432 433 struct dc_chain_data { 434 struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; 435 struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; 436 u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)]; 437 u_int8_t dc_pad[DC_MIN_FRAMELEN]; 438 int dc_tx_prod; 439 int dc_tx_cons; 440 int dc_tx_cnt; 441 int dc_rx_prod; 442 }; 443 444 struct dc_type { 445 u_int16_t dc_vid; 446 u_int16_t dc_did; 447 char *dc_name; 448 }; 449 450 struct dc_mii_frame { 451 u_int8_t mii_stdelim; 452 u_int8_t mii_opcode; 453 u_int8_t mii_phyaddr; 454 u_int8_t mii_regaddr; 455 u_int8_t mii_turnaround; 456 u_int16_t mii_data; 457 }; 458 459 /* 460 * MII constants 461 */ 462 #define DC_MII_STARTDELIM 0x01 463 #define DC_MII_READOP 0x02 464 #define DC_MII_WRITEOP 0x01 465 #define DC_MII_TURNAROUND 0x02 466 467 468 /* 469 * Registers specific to clone devices. 470 * This mainly relates to RX filter programming: not all 21x4x clones 471 * use the standard DEC filter programming mechanism. 472 */ 473 474 /* 475 * ADMtek specific registers and constants for the AL981 and AN985. 476 * The AN985 doesn't use the magic PHY registers. 477 */ 478 #define DC_AL_PAR0 0xA4 /* station address */ 479 #define DC_AL_PAR1 0xA8 /* station address */ 480 #define DC_AL_MAR0 0xAC /* multicast hash filter */ 481 #define DC_AL_MAR1 0xB0 /* multicast hash filter */ 482 #define DC_AL_BMCR 0xB4 /* built in PHY control */ 483 #define DC_AL_BMSR 0xB8 /* built in PHY status */ 484 #define DC_AL_VENID 0xBC /* built in PHY ID0 */ 485 #define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ 486 #define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ 487 #define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ 488 #define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ 489 490 #define DC_ADMTEK_PHYADDR 0x1 491 #define DC_AL_EE_NODEADDR 4 492 /* End of ADMtek specific registers */ 493 494 /* 495 * ASIX specific registers. 496 */ 497 #define DC_AX_FILTIDX 0x68 /* RX filter index */ 498 #define DC_AX_FILTDATA 0x70 /* RX filter data */ 499 500 /* 501 * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). 502 */ 503 #define DC_AX_NETCFG_RX_BROAD 0x00000100 504 505 /* 506 * RX Filter Index Register values 507 */ 508 #define DC_AX_FILTIDX_PAR0 0x00000000 509 #define DC_AX_FILTIDX_PAR1 0x00000001 510 #define DC_AX_FILTIDX_MAR0 0x00000002 511 #define DC_AX_FILTIDX_MAR1 0x00000003 512 /* End of ASIX specific registers */ 513 514 /* 515 * Macronix specific registers. The Macronix chips have a special 516 * register for reading the NWAY status, which we don't use, plus 517 * a magic packet register, which we need to tweak a bit per the 518 * Macronix application notes. 519 */ 520 #define DC_MX_MAGICPACKET 0x80 521 #define DC_MX_NWAYSTAT 0xA0 522 523 /* 524 * Magic packet register 525 */ 526 #define DC_MX_MPACK_DISABLE 0x00400000 527 528 /* 529 * NWAY status register. 530 */ 531 #define DC_MX_NWAY_10BTHALF 0x08000000 532 #define DC_MX_NWAY_10BTFULL 0x10000000 533 #define DC_MX_NWAY_100BTHALF 0x20000000 534 #define DC_MX_NWAY_100BTFULL 0x40000000 535 #define DC_MX_NWAY_100BT4 0x80000000 536 537 /* 538 * These are magic values that must be written into CSR16 539 * (DC_MX_MAGICPACKET) in order to put the chip into proper 540 * operating mode. The magic numbers are documented in the 541 * Macronix 98715 application notes. 542 */ 543 #define DC_MX_MAGIC_98713 0x0F370000 544 #define DC_MX_MAGIC_98713A 0x0B3C0000 545 #define DC_MX_MAGIC_98715 0x0B3C0000 546 #define DC_MX_MAGIC_98725 0x0B3C0000 547 /* End of Macronix specific registers */ 548 549 /* 550 * PNIC 82c168/82c169 specific registers. 551 * The PNIC has its own special NWAY support, which doesn't work, 552 * and shortcut ways of reading the EEPROM and MII bus. 553 */ 554 #define DC_PN_GPIO 0x60 /* general purpose pins control */ 555 #define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ 556 #define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ 557 #define DC_PN_MII 0xA0 /* MII access register */ 558 #define DC_PN_NWAY 0xB8 /* Internal NWAY register */ 559 560 /* Serial I/O EEPROM register */ 561 #define DC_PN_SIOCTL_DATA 0x0000003F 562 #define DC_PN_SIOCTL_OPCODE 0x00000300 563 #define DC_PN_SIOCTL_BUSY 0x80000000 564 565 #define DC_PN_EEOPCODE_ERASE 0x00000300 566 #define DC_PN_EEOPCODE_READ 0x00000600 567 #define DC_PN_EEOPCODE_WRITE 0x00000100 568 569 /* 570 * The first two general purpose pins control speed selection and 571 * 100Mbps loopback on the 82c168 chip. The control bits should always 572 * be set (to make the data pins outputs) and the speed selction and 573 * loopback bits set accordingly when changing media. Physically, this 574 * will set the state of a relay mounted on the card. 575 */ 576 #define DC_PN_GPIO_DATA0 0x000000001 577 #define DC_PN_GPIO_DATA1 0x000000002 578 #define DC_PN_GPIO_DATA2 0x000000004 579 #define DC_PN_GPIO_DATA3 0x000000008 580 #define DC_PN_GPIO_CTL0 0x000000010 581 #define DC_PN_GPIO_CTL1 0x000000020 582 #define DC_PN_GPIO_CTL2 0x000000040 583 #define DC_PN_GPIO_CTL3 0x000000080 584 #define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ 585 #define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ 586 #define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 587 #define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 588 #define DC_PN_GPIO_SETBIT(sc, r) \ 589 DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) 590 #define DC_PN_GPIO_CLRBIT(sc, r) \ 591 { \ 592 DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ 593 DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ 594 } 595 596 /* shortcut MII access register */ 597 #define DC_PN_MII_DATA 0x0000FFFF 598 #define DC_PN_MII_RESERVER 0x00020000 599 #define DC_PN_MII_REGADDR 0x007C0000 600 #define DC_PN_MII_PHYADDR 0x0F800000 601 #define DC_PN_MII_OPCODE 0x30000000 602 #define DC_PN_MII_BUSY 0x80000000 603 604 #define DC_PN_MIIOPCODE_READ 0x60020000 605 #define DC_PN_MIIOPCODE_WRITE 0x50020000 606 607 /* Internal NWAY bits */ 608 #define DC_PN_NWAY_RESET 0x00000001 /* reset */ 609 #define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ 610 #define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ 611 #define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ 612 #define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ 613 #define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ 614 #define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ 615 #define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ 616 #define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ 617 #define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ 618 #define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ 619 #define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ 620 #define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ 621 #define DC_PN_NWAY_CAP10HDX 0x00002000 622 #define DC_PN_NWAY_CAP10FDX 0x00004000 623 #define DC_PN_NWAY_CAP100FDX 0x00008000 624 #define DC_PN_NWAY_CAP100HDX 0x00010000 625 #define DC_PN_NWAY_CAP100T4 0x00020000 626 #define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ 627 #define DC_PN_NWAY_REMFAULT 0x04000000 628 #define DC_PN_NWAY_LPAR10HDX 0x08000000 629 #define DC_PN_NWAY_LPAR10FDX 0x10000000 630 #define DC_PN_NWAY_LPAR100FDX 0x20000000 631 #define DC_PN_NWAY_LPAR100HDX 0x40000000 632 #define DC_PN_NWAY_LPAR100T4 0x80000000 633 634 /* End of PNIC specific registers */ 635 636 struct dc_softc { 637 struct arpcom arpcom; /* interface info */ 638 bus_space_handle_t dc_bhandle; /* bus space handle */ 639 bus_space_tag_t dc_btag; /* bus space tag */ 640 void *dc_intrhand; 641 struct resource *dc_irq; 642 struct resource *dc_res; 643 struct dc_type *dc_info; /* adapter info */ 644 device_t dc_miibus; 645 u_int8_t dc_unit; /* interface number */ 646 u_int8_t dc_type; 647 u_int8_t dc_pmode; 648 u_int8_t dc_link; 649 u_int8_t dc_cachesize; 650 int dc_pnic_rx_bug_save; 651 unsigned char *dc_pnic_rx_buf; 652 int dc_if_flags; 653 int dc_if_media; 654 u_int32_t dc_flags; 655 u_int32_t dc_txthresh; 656 struct dc_list_data *dc_ldata; 657 struct dc_chain_data dc_cdata; 658 struct callout_handle dc_stat_ch; 659 #ifdef __alpha__ 660 int dc_srm_media; 661 #endif 662 }; 663 664 #define DC_TX_POLL 0x00000001 665 #define DC_TX_COALESCE 0x00000002 666 #define DC_TX_ADMTEK_WAR 0x00000004 667 #define DC_TX_USE_TX_INTR 0x00000008 668 #define DC_RX_FILTER_TULIP 0x00000010 669 #define DC_TX_INTR_FIRSTFRAG 0x00000020 670 #define DC_PNIC_RX_BUG_WAR 0x00000040 671 #define DC_TX_FIXED_RING 0x00000080 672 #define DC_TX_STORENFWD 0x00000100 673 #define DC_REDUCED_MII_POLL 0x00000200 674 #define DC_TX_INTR_ALWAYS 0x00000400 675 #define DC_21143_NWAY 0x00000800 676 #define DC_128BIT_HASH 0x00001000 677 #define DC_64BIT_HASH 0x00002000 678 679 /* 680 * register space access macros 681 */ 682 #define CSR_WRITE_4(sc, reg, val) \ 683 bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val) 684 685 #define CSR_READ_4(sc, reg) \ 686 bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg) 687 688 #define DC_TIMEOUT 1000 689 #define ETHER_ALIGN 2 690 691 /* 692 * General constants that are fun to know. 693 */ 694 695 /* 696 * DEC PCI vendor ID 697 */ 698 #define DC_VENDORID_DEC 0x1011 699 700 /* 701 * DEC/Intel 21143 PCI device ID 702 */ 703 #define DC_DEVICEID_21143 0x0019 704 705 /* 706 * Macronix PCI vendor ID 707 */ 708 #define DC_VENDORID_MX 0x10D9 709 710 /* 711 * Macronix PMAC device IDs. 712 */ 713 #define DC_DEVICEID_98713 0x0512 714 #define DC_DEVICEID_987x5 0x0531 715 #define DC_DEVICEID_98727 0x0532 716 #define DC_DEVICEID_98732 0x0532 717 718 /* Macronix PCI revision codes. */ 719 #define DC_REVISION_98713 0x00 720 #define DC_REVISION_98713A 0x10 721 #define DC_REVISION_98715 0x20 722 #define DC_REVISION_98715AEC_C 0x25 723 #define DC_REVISION_98725 0x30 724 725 /* 726 * Compex PCI vendor ID. 727 */ 728 #define DC_VENDORID_CP 0x11F6 729 730 /* 731 * Compex PMAC PCI device IDs. 732 */ 733 #define DC_DEVICEID_98713_CP 0x9881 734 735 /* 736 * Lite-On PNIC PCI vendor ID 737 */ 738 #define DC_VENDORID_LO 0x11AD 739 740 /* 741 * 82c168/82c169 PNIC device IDs. Both chips have the same device 742 * ID but different revisions. Revision 0x10 is the 82c168, and 743 * 0x20 is the 82c169. 744 */ 745 #define DC_DEVICEID_82C168 0x0002 746 747 #define DC_REVISION_82C168 0x10 748 #define DC_REVISION_82C169 0x20 749 750 /* 751 * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A 752 * with wake on lan/magic packet support. 753 */ 754 #define DC_DEVICEID_82C115 0xc115 755 756 /* 757 * Davicom vendor ID. 758 */ 759 #define DC_VENDORID_DAVICOM 0x1282 760 761 /* 762 * Davicom device IDs. 763 */ 764 #define DC_DEVICEID_DM9100 0x9100 765 #define DC_DEVICEID_DM9102 0x9102 766 767 /* 768 * The DM9102A has the same PCI device ID as the DM9102, 769 * but a higher revision code. 770 */ 771 #define DC_REVISION_DM9102 0x10 772 #define DC_REVISION_DM9102A 0x30 773 774 /* 775 * ADMtek vendor ID. 776 */ 777 #define DC_VENDORID_ADMTEK 0x1317 778 779 /* 780 * ADMtek device IDs. 781 */ 782 #define DC_DEVICEID_AL981 0x0981 783 #define DC_DEVICEID_AN985 0x0985 784 785 /* 786 * ASIX vendor ID. 787 */ 788 #define DC_VENDORID_ASIX 0x125B 789 790 /* 791 * ASIX device IDs. 792 */ 793 #define DC_DEVICEID_AX88140A 0x1400 794 795 /* 796 * The ASIX AX88140 and ASIX AX88141 have the same vendor and 797 * device IDs but different revision values. 798 */ 799 #define DC_REVISION_88140 0x00 800 #define DC_REVISION_88141 0x10 801 802 /* 803 * Accton vendor ID. 804 */ 805 #define DC_VENDORID_ACCTON 0x1113 806 807 /* 808 * Accton device IDs. 809 */ 810 #define DC_DEVICEID_EN1217 0x1217 811 812 /* 813 * PCI low memory base and low I/O base register, and 814 * other PCI registers. 815 */ 816 817 #define DC_PCI_CFID 0x00 /* Id */ 818 #define DC_PCI_CFCS 0x04 /* Command and status */ 819 #define DC_PCI_CFRV 0x08 /* Revision */ 820 #define DC_PCI_CFLT 0x0C /* Latency timer */ 821 #define DC_PCI_CFBIO 0x10 /* Base I/O address */ 822 #define DC_PCI_CFBMA 0x14 /* Base memory address */ 823 #define DC_PCI_CCIS 0x28 /* Card info struct */ 824 #define DC_PCI_CSID 0x2C /* Subsystem ID */ 825 #define DC_PCI_CBER 0x30 /* Expansion ROM base address */ 826 #define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */ 827 #define DC_PCI_CFIT 0x3C /* Interrupt */ 828 #define DC_PCI_CFDD 0x40 /* Device and driver area */ 829 #define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ 830 #define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ 831 #define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ 832 #define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ 833 #define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ 834 #define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */ 835 #define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */ 836 837 /* PCI ID register */ 838 #define DC_CFID_VENDOR 0x0000FFFF 839 #define DC_CFID_DEVICE 0xFFFF0000 840 841 /* PCI command/status register */ 842 #define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */ 843 #define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */ 844 #define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */ 845 #define DC_CFCS_MWI_ENB 0x00000008 /* mem write and inval enable */ 846 #define DC_CFCS_PARITYERR_ENB 0x00000020 /* parity error enable */ 847 #define DC_CFCS_SYSERR_ENB 0x00000080 /* system error enable */ 848 #define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */ 849 #define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */ 850 #define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */ 851 #define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */ 852 #define DC_CFCS_TGTABRT 0x10000000 /* received target abort */ 853 #define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */ 854 #define DC_CFCS_SYSERR 0x40000000 /* asserted system error */ 855 #define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */ 856 857 /* PCI revision register */ 858 #define DC_CFRV_STEPPING 0x0000000F 859 #define DC_CFRV_REVISION 0x000000F0 860 #define DC_CFRV_SUBCLASS 0x00FF0000 861 #define DC_CFRV_BASECLASS 0xFF000000 862 863 #define DC_21143_PB_REV 0x00000030 864 #define DC_21143_TB_REV 0x00000030 865 #define DC_21143_PC_REV 0x00000030 866 #define DC_21143_TC_REV 0x00000030 867 #define DC_21143_PD_REV 0x00000041 868 #define DC_21143_TD_REV 0x00000041 869 870 /* PCI latency timer register */ 871 #define DC_CFLT_CACHELINESIZE 0x000000FF 872 #define DC_CFLT_LATENCYTIMER 0x0000FF00 873 874 /* PCI subsystem ID register */ 875 #define DC_CSID_VENDOR 0x0000FFFF 876 #define DC_CSID_DEVICE 0xFFFF0000 877 878 /* PCI cababilities pointer */ 879 #define DC_CCAP_OFFSET 0x000000FF 880 881 /* PCI interrupt config register */ 882 #define DC_CFIT_INTLINE 0x000000FF 883 #define DC_CFIT_INTPIN 0x0000FF00 884 #define DC_CFIT_MIN_GNT 0x00FF0000 885 #define DC_CFIT_MAX_LAT 0xFF000000 886 887 /* PCI capability register */ 888 #define DC_CCID_CAPID 0x000000FF 889 #define DC_CCID_NEXTPTR 0x0000FF00 890 #define DC_CCID_PM_VERS 0x00070000 891 #define DC_CCID_PME_CLK 0x00080000 892 #define DC_CCID_DVSPEC_INT 0x00200000 893 #define DC_CCID_STATE_D1 0x02000000 894 #define DC_CCID_STATE_D2 0x04000000 895 #define DC_CCID_PME_D0 0x08000000 896 #define DC_CCID_PME_D1 0x10000000 897 #define DC_CCID_PME_D2 0x20000000 898 #define DC_CCID_PME_D3HOT 0x40000000 899 #define DC_CCID_PME_D3COLD 0x80000000 900 901 /* PCI power management control/status register */ 902 #define DC_CPMC_STATE 0x00000003 903 #define DC_CPMC_PME_ENB 0x00000100 904 #define DC_CPMC_PME_STS 0x00008000 905 906 #define DC_PSTATE_D0 0x0 907 #define DC_PSTATE_D1 0x1 908 #define DC_PSTATE_D2 0x2 909 #define DC_PSTATE_D3 0x3 910 911 /* Device specific region */ 912 /* Configuration and driver area */ 913 #define DC_CFDD_DRVUSE 0x0000FFFF 914 #define DC_CFDD_SNOOZE_MODE 0x40000000 915 #define DC_CFDD_SLEEP_MODE 0x80000000 916 917 /* Configuration wake-up command register */ 918 #define DC_CWUC_MUST_BE_ZERO 0x00000001 919 #define DC_CWUC_SECUREON_ENB 0x00000002 920 #define DC_CWUC_FORCE_WUL 0x00000004 921 #define DC_CWUC_BNC_ABILITY 0x00000008 922 #define DC_CWUC_AUI_ABILITY 0x00000010 923 #define DC_CWUC_TP10_ABILITY 0x00000020 924 #define DC_CWUC_MII_ABILITY 0x00000040 925 #define DC_CWUC_SYM_ABILITY 0x00000080 926 #define DC_CWUC_LOCK 0x00000100 927 928 #ifdef __alpha__ 929 #undef vtophys 930 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 931 #endif 932