xref: /freebsd/sys/dev/cxgbe/t4_l2t.h (revision 4dba21f17e7d77718b76685b2635b33efd520db9)
1*4dba21f1SNavdeep Parhar /*-
2*4dba21f1SNavdeep Parhar  * Copyright (c) 2011 Chelsio Communications, Inc.
3*4dba21f1SNavdeep Parhar  * All rights reserved.
4*4dba21f1SNavdeep Parhar  *
5*4dba21f1SNavdeep Parhar  * Redistribution and use in source and binary forms, with or without
6*4dba21f1SNavdeep Parhar  * modification, are permitted provided that the following conditions
7*4dba21f1SNavdeep Parhar  * are met:
8*4dba21f1SNavdeep Parhar  * 1. Redistributions of source code must retain the above copyright
9*4dba21f1SNavdeep Parhar  *    notice, this list of conditions and the following disclaimer.
10*4dba21f1SNavdeep Parhar  * 2. Redistributions in binary form must reproduce the above copyright
11*4dba21f1SNavdeep Parhar  *    notice, this list of conditions and the following disclaimer in the
12*4dba21f1SNavdeep Parhar  *    documentation and/or other materials provided with the distribution.
13*4dba21f1SNavdeep Parhar  *
14*4dba21f1SNavdeep Parhar  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15*4dba21f1SNavdeep Parhar  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16*4dba21f1SNavdeep Parhar  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17*4dba21f1SNavdeep Parhar  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18*4dba21f1SNavdeep Parhar  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19*4dba21f1SNavdeep Parhar  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20*4dba21f1SNavdeep Parhar  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21*4dba21f1SNavdeep Parhar  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22*4dba21f1SNavdeep Parhar  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23*4dba21f1SNavdeep Parhar  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24*4dba21f1SNavdeep Parhar  * SUCH DAMAGE.
25*4dba21f1SNavdeep Parhar  *
26*4dba21f1SNavdeep Parhar  * $FreeBSD$
27*4dba21f1SNavdeep Parhar  *
28*4dba21f1SNavdeep Parhar  */
29*4dba21f1SNavdeep Parhar 
30*4dba21f1SNavdeep Parhar #ifndef __T4_L2T_H
31*4dba21f1SNavdeep Parhar #define __T4_L2T_H
32*4dba21f1SNavdeep Parhar 
33*4dba21f1SNavdeep Parhar enum { L2T_SIZE = 4096 };     /* # of L2T entries */
34*4dba21f1SNavdeep Parhar 
35*4dba21f1SNavdeep Parhar /*
36*4dba21f1SNavdeep Parhar  * Each L2T entry plays multiple roles.  First of all, it keeps state for the
37*4dba21f1SNavdeep Parhar  * corresponding entry of the HW L2 table and maintains a queue of offload
38*4dba21f1SNavdeep Parhar  * packets awaiting address resolution.  Second, it is a node of a hash table
39*4dba21f1SNavdeep Parhar  * chain, where the nodes of the chain are linked together through their next
40*4dba21f1SNavdeep Parhar  * pointer.  Finally, each node is a bucket of a hash table, pointing to the
41*4dba21f1SNavdeep Parhar  * first element in its chain through its first pointer.
42*4dba21f1SNavdeep Parhar  */
43*4dba21f1SNavdeep Parhar struct l2t_entry {
44*4dba21f1SNavdeep Parhar 	uint16_t state;			/* entry state */
45*4dba21f1SNavdeep Parhar 	uint16_t idx;			/* entry index */
46*4dba21f1SNavdeep Parhar 	uint32_t addr[4];		/* next hop IP or IPv6 address */
47*4dba21f1SNavdeep Parhar 	struct ifnet *ifp;		/* outgoing interface */
48*4dba21f1SNavdeep Parhar 	uint16_t smt_idx;		/* SMT index */
49*4dba21f1SNavdeep Parhar 	uint16_t vlan;			/* VLAN TCI (id: 0-11, prio: 13-15) */
50*4dba21f1SNavdeep Parhar 	int ifindex;			/* interface index */
51*4dba21f1SNavdeep Parhar 	struct llentry *lle;		/* llentry for next hop */
52*4dba21f1SNavdeep Parhar 	struct l2t_entry *first;	/* start of hash chain */
53*4dba21f1SNavdeep Parhar 	struct l2t_entry *next;		/* next l2t_entry on chain */
54*4dba21f1SNavdeep Parhar 	struct mbuf *arpq_head;		/* list of mbufs awaiting resolution */
55*4dba21f1SNavdeep Parhar 	struct mbuf *arpq_tail;
56*4dba21f1SNavdeep Parhar 	struct mtx lock;
57*4dba21f1SNavdeep Parhar 	volatile uint32_t refcnt;	/* entry reference count */
58*4dba21f1SNavdeep Parhar 	uint16_t hash;			/* hash bucket the entry is on */
59*4dba21f1SNavdeep Parhar 	uint8_t v6;			/* whether entry is for IPv6 */
60*4dba21f1SNavdeep Parhar 	uint8_t lport;			/* associated offload logical port */
61*4dba21f1SNavdeep Parhar 	uint8_t dmac[ETHER_ADDR_LEN];	/* next hop's MAC address */
62*4dba21f1SNavdeep Parhar };
63*4dba21f1SNavdeep Parhar 
64*4dba21f1SNavdeep Parhar struct l2t_data *t4_init_l2t(int);
65*4dba21f1SNavdeep Parhar int t4_free_l2t(struct l2t_data *);
66*4dba21f1SNavdeep Parhar struct l2t_entry *t4_l2t_alloc_switching(struct l2t_data *);
67*4dba21f1SNavdeep Parhar int t4_l2t_set_switching(struct adapter *, struct l2t_entry *, uint16_t,
68*4dba21f1SNavdeep Parhar     uint8_t, uint8_t *);
69*4dba21f1SNavdeep Parhar void t4_l2t_release(struct l2t_entry *);
70*4dba21f1SNavdeep Parhar 
71*4dba21f1SNavdeep Parhar #endif  /* __T4_L2T_H */
72