1 /*- 2 * Copyright (c) 2012-2016 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _T4FW_INTERFACE_H_ 31 #define _T4FW_INTERFACE_H_ 32 33 /****************************************************************************** 34 * R E T U R N V A L U E S 35 ********************************/ 36 37 enum fw_retval { 38 FW_SUCCESS = 0, /* completed sucessfully */ 39 FW_EPERM = 1, /* operation not permitted */ 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ 48 FW_ENODEV = 19, /* no such device */ 49 FW_EINVAL = 22, /* invalid argument */ 50 FW_ENOSPC = 28, /* no space left on device */ 51 FW_ENOSYS = 38, /* functionality not implemented */ 52 FW_ENODATA = 61, /* no data available */ 53 FW_EPROTO = 71, /* protocol error */ 54 FW_EADDRINUSE = 98, /* address already in use */ 55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 56 FW_ENETDOWN = 100, /* network is down */ 57 FW_ENETUNREACH = 101, /* network is unreachable */ 58 FW_ENOBUFS = 105, /* no buffer space available */ 59 FW_ETIMEDOUT = 110, /* timeout */ 60 FW_EINPROGRESS = 115, /* fw internal */ 61 FW_SCSI_ABORT_REQUESTED = 128, /* */ 62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 63 FW_SCSI_ABORTED = 130, /* */ 64 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 65 FW_ERR_LINK_DOWN = 132, /* */ 66 FW_RDEV_NOT_READY = 133, /* */ 67 FW_ERR_RDEV_LOST = 134, /* */ 68 FW_ERR_RDEV_LOGO = 135, /* */ 69 FW_FCOE_NO_XCHG = 136, /* */ 70 FW_SCSI_RSP_ERR = 137, /* */ 71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 73 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 74 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 76 }; 77 78 /****************************************************************************** 79 * M E M O R Y T Y P E s 80 ******************************/ 81 82 enum fw_memtype { 83 FW_MEMTYPE_EDC0 = 0x0, 84 FW_MEMTYPE_EDC1 = 0x1, 85 FW_MEMTYPE_EXTMEM = 0x2, 86 FW_MEMTYPE_FLASH = 0x4, 87 FW_MEMTYPE_INTERNAL = 0x5, 88 FW_MEMTYPE_EXTMEM1 = 0x6, 89 }; 90 91 /****************************************************************************** 92 * W O R K R E Q U E S T s 93 ********************************/ 94 95 enum fw_wr_opcodes { 96 FW_FRAG_WR = 0x1d, 97 FW_FILTER_WR = 0x02, 98 FW_ULPTX_WR = 0x04, 99 FW_TP_WR = 0x05, 100 FW_ETH_TX_PKT_WR = 0x08, 101 FW_ETH_TX_PKT2_WR = 0x44, 102 FW_ETH_TX_PKTS_WR = 0x09, 103 FW_ETH_TX_EO_WR = 0x1c, 104 FW_EQ_FLUSH_WR = 0x1b, 105 FW_OFLD_CONNECTION_WR = 0x2f, 106 FW_FLOWC_WR = 0x0a, 107 FW_OFLD_TX_DATA_WR = 0x0b, 108 FW_CMD_WR = 0x10, 109 FW_ETH_TX_PKT_VM_WR = 0x11, 110 FW_RI_RES_WR = 0x0c, 111 FW_RI_RDMA_WRITE_WR = 0x14, 112 FW_RI_SEND_WR = 0x15, 113 FW_RI_RDMA_READ_WR = 0x16, 114 FW_RI_RECV_WR = 0x17, 115 FW_RI_BIND_MW_WR = 0x18, 116 FW_RI_FR_NSMR_WR = 0x19, 117 FW_RI_INV_LSTAG_WR = 0x1a, 118 FW_RI_SEND_IMMEDIATE_WR = 0x15, 119 FW_RI_ATOMIC_WR = 0x16, 120 FW_RI_WR = 0x0d, 121 FW_CHNET_IFCONF_WR = 0x6b, 122 FW_RDEV_WR = 0x38, 123 FW_FOISCSI_NODE_WR = 0x60, 124 FW_FOISCSI_CTRL_WR = 0x6a, 125 FW_FOISCSI_CHAP_WR = 0x6c, 126 FW_FCOE_ELS_CT_WR = 0x30, 127 FW_SCSI_WRITE_WR = 0x31, 128 FW_SCSI_READ_WR = 0x32, 129 FW_SCSI_CMD_WR = 0x33, 130 FW_SCSI_ABRT_CLS_WR = 0x34, 131 FW_SCSI_TGT_ACC_WR = 0x35, 132 FW_SCSI_TGT_XMIT_WR = 0x36, 133 FW_SCSI_TGT_RSP_WR = 0x37, 134 FW_POFCOE_TCB_WR = 0x42, 135 FW_POFCOE_ULPTX_WR = 0x43, 136 FW_ISCSI_TX_DATA_WR = 0x45, 137 FW_PTP_TX_PKT_WR = 0x46, 138 FW_SEC_LOOKASIDE_LPBK_WR= 0x63, 139 FW_COiSCSI_TGT_WR = 0x70, 140 FW_COiSCSI_TGT_CONN_WR = 0x71, 141 FW_COiSCSI_TGT_XMIT_WR = 0x72, 142 FW_ISNS_WR = 0x75, 143 FW_ISNS_XMIT_WR = 0x76, 144 FW_LASTC2E_WR = 0x80 145 }; 146 147 /* 148 * Generic work request header flit0 149 */ 150 struct fw_wr_hdr { 151 __be32 hi; 152 __be32 lo; 153 }; 154 155 /* work request opcode (hi) 156 */ 157 #define S_FW_WR_OP 24 158 #define M_FW_WR_OP 0xff 159 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 160 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 161 162 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 163 */ 164 #define S_FW_WR_ATOMIC 23 165 #define M_FW_WR_ATOMIC 0x1 166 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 167 #define G_FW_WR_ATOMIC(x) \ 168 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 169 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 170 171 /* flush flag (hi) - firmware flushes flushable work request buffered 172 * in the flow context. 173 */ 174 #define S_FW_WR_FLUSH 22 175 #define M_FW_WR_FLUSH 0x1 176 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 177 #define G_FW_WR_FLUSH(x) \ 178 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 179 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 180 181 /* completion flag (hi) - firmware generates a cpl_fw6_ack 182 */ 183 #define S_FW_WR_COMPL 21 184 #define M_FW_WR_COMPL 0x1 185 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 186 #define G_FW_WR_COMPL(x) \ 187 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 188 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 189 190 191 /* work request immediate data lengh (hi) 192 */ 193 #define S_FW_WR_IMMDLEN 0 194 #define M_FW_WR_IMMDLEN 0xff 195 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 196 #define G_FW_WR_IMMDLEN(x) \ 197 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 198 199 /* egress queue status update to associated ingress queue entry (lo) 200 */ 201 #define S_FW_WR_EQUIQ 31 202 #define M_FW_WR_EQUIQ 0x1 203 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 204 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 205 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 206 207 /* egress queue status update to egress queue status entry (lo) 208 */ 209 #define S_FW_WR_EQUEQ 30 210 #define M_FW_WR_EQUEQ 0x1 211 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 212 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 213 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 214 215 /* flow context identifier (lo) 216 */ 217 #define S_FW_WR_FLOWID 8 218 #define M_FW_WR_FLOWID 0xfffff 219 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 220 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 221 222 /* length in units of 16-bytes (lo) 223 */ 224 #define S_FW_WR_LEN16 0 225 #define M_FW_WR_LEN16 0xff 226 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 227 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 228 229 struct fw_frag_wr { 230 __be32 op_to_fragoff16; 231 __be32 flowid_len16; 232 __be64 r4; 233 }; 234 235 #define S_FW_FRAG_WR_EOF 15 236 #define M_FW_FRAG_WR_EOF 0x1 237 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 238 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 239 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 240 241 #define S_FW_FRAG_WR_FRAGOFF16 8 242 #define M_FW_FRAG_WR_FRAGOFF16 0x7f 243 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 244 #define G_FW_FRAG_WR_FRAGOFF16(x) \ 245 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 246 247 /* valid filter configurations for compressed tuple 248 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 249 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 250 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 251 * OV - Outer VLAN/VNIC_ID, 252 */ 253 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 254 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 255 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 256 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 257 #define HW_TPL_FR_MT_E_PR_T 0x370 258 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 259 #define HW_TPL_FR_MT_E_T_P_FC 0X353 260 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 261 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 262 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 263 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 264 #define HW_TPL_FR_M_E_PR_FC 0X2E1 265 #define HW_TPL_FR_M_E_T_FC 0X2D1 266 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 267 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 268 #define HW_TPL_FR_M_T_IV_FC 0X299 269 #define HW_TPL_FR_M_T_OV_FC 0X295 270 #define HW_TPL_FR_E_PR_T_P 0X272 271 #define HW_TPL_FR_E_PR_T_FC 0X271 272 #define HW_TPL_FR_E_IV_FC 0X249 273 #define HW_TPL_FR_E_OV_FC 0X245 274 #define HW_TPL_FR_PR_T_IV_FC 0X239 275 #define HW_TPL_FR_PR_T_OV_FC 0X235 276 #define HW_TPL_FR_IV_OV_FC 0X20D 277 #define HW_TPL_MT_M_E_PR 0X1E0 278 #define HW_TPL_MT_M_E_T 0X1D0 279 #define HW_TPL_MT_E_PR_T_FC 0X171 280 #define HW_TPL_MT_E_IV 0X148 281 #define HW_TPL_MT_E_OV 0X144 282 #define HW_TPL_MT_PR_T_IV 0X138 283 #define HW_TPL_MT_PR_T_OV 0X134 284 #define HW_TPL_M_E_PR_P 0X0E2 285 #define HW_TPL_M_E_T_P 0X0D2 286 #define HW_TPL_E_PR_T_P_FC 0X073 287 #define HW_TPL_E_IV_P 0X04A 288 #define HW_TPL_E_OV_P 0X046 289 #define HW_TPL_PR_T_IV_P 0X03A 290 #define HW_TPL_PR_T_OV_P 0X036 291 292 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 293 enum fw_filter_wr_cookie { 294 FW_FILTER_WR_SUCCESS, 295 FW_FILTER_WR_FLT_ADDED, 296 FW_FILTER_WR_FLT_DELETED, 297 FW_FILTER_WR_SMT_TBL_FULL, 298 FW_FILTER_WR_EINVAL, 299 }; 300 301 struct fw_filter_wr { 302 __be32 op_pkd; 303 __be32 len16_pkd; 304 __be64 r3; 305 __be32 tid_to_iq; 306 __be32 del_filter_to_l2tix; 307 __be16 ethtype; 308 __be16 ethtypem; 309 __u8 frag_to_ovlan_vldm; 310 __u8 smac_sel; 311 __be16 rx_chan_rx_rpl_iq; 312 __be32 maci_to_matchtypem; 313 __u8 ptcl; 314 __u8 ptclm; 315 __u8 ttyp; 316 __u8 ttypm; 317 __be16 ivlan; 318 __be16 ivlanm; 319 __be16 ovlan; 320 __be16 ovlanm; 321 __u8 lip[16]; 322 __u8 lipm[16]; 323 __u8 fip[16]; 324 __u8 fipm[16]; 325 __be16 lp; 326 __be16 lpm; 327 __be16 fp; 328 __be16 fpm; 329 __be16 r7; 330 __u8 sma[6]; 331 }; 332 333 #define S_FW_FILTER_WR_TID 12 334 #define M_FW_FILTER_WR_TID 0xfffff 335 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 336 #define G_FW_FILTER_WR_TID(x) \ 337 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 338 339 #define S_FW_FILTER_WR_RQTYPE 11 340 #define M_FW_FILTER_WR_RQTYPE 0x1 341 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 342 #define G_FW_FILTER_WR_RQTYPE(x) \ 343 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 344 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 345 346 #define S_FW_FILTER_WR_NOREPLY 10 347 #define M_FW_FILTER_WR_NOREPLY 0x1 348 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 349 #define G_FW_FILTER_WR_NOREPLY(x) \ 350 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 351 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 352 353 #define S_FW_FILTER_WR_IQ 0 354 #define M_FW_FILTER_WR_IQ 0x3ff 355 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 356 #define G_FW_FILTER_WR_IQ(x) \ 357 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 358 359 #define S_FW_FILTER_WR_DEL_FILTER 31 360 #define M_FW_FILTER_WR_DEL_FILTER 0x1 361 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 362 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 363 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 364 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 365 366 #define S_FW_FILTER_WR_RPTTID 25 367 #define M_FW_FILTER_WR_RPTTID 0x1 368 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 369 #define G_FW_FILTER_WR_RPTTID(x) \ 370 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 371 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 372 373 #define S_FW_FILTER_WR_DROP 24 374 #define M_FW_FILTER_WR_DROP 0x1 375 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 376 #define G_FW_FILTER_WR_DROP(x) \ 377 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 378 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 379 380 #define S_FW_FILTER_WR_DIRSTEER 23 381 #define M_FW_FILTER_WR_DIRSTEER 0x1 382 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 383 #define G_FW_FILTER_WR_DIRSTEER(x) \ 384 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 385 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 386 387 #define S_FW_FILTER_WR_MASKHASH 22 388 #define M_FW_FILTER_WR_MASKHASH 0x1 389 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 390 #define G_FW_FILTER_WR_MASKHASH(x) \ 391 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 392 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 393 394 #define S_FW_FILTER_WR_DIRSTEERHASH 21 395 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 396 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 397 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 398 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 399 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 400 401 #define S_FW_FILTER_WR_LPBK 20 402 #define M_FW_FILTER_WR_LPBK 0x1 403 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 404 #define G_FW_FILTER_WR_LPBK(x) \ 405 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 406 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 407 408 #define S_FW_FILTER_WR_DMAC 19 409 #define M_FW_FILTER_WR_DMAC 0x1 410 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 411 #define G_FW_FILTER_WR_DMAC(x) \ 412 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 413 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 414 415 #define S_FW_FILTER_WR_SMAC 18 416 #define M_FW_FILTER_WR_SMAC 0x1 417 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 418 #define G_FW_FILTER_WR_SMAC(x) \ 419 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 420 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 421 422 #define S_FW_FILTER_WR_INSVLAN 17 423 #define M_FW_FILTER_WR_INSVLAN 0x1 424 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 425 #define G_FW_FILTER_WR_INSVLAN(x) \ 426 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 427 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 428 429 #define S_FW_FILTER_WR_RMVLAN 16 430 #define M_FW_FILTER_WR_RMVLAN 0x1 431 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 432 #define G_FW_FILTER_WR_RMVLAN(x) \ 433 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 434 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 435 436 #define S_FW_FILTER_WR_HITCNTS 15 437 #define M_FW_FILTER_WR_HITCNTS 0x1 438 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 439 #define G_FW_FILTER_WR_HITCNTS(x) \ 440 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 441 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 442 443 #define S_FW_FILTER_WR_TXCHAN 13 444 #define M_FW_FILTER_WR_TXCHAN 0x3 445 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 446 #define G_FW_FILTER_WR_TXCHAN(x) \ 447 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 448 449 #define S_FW_FILTER_WR_PRIO 12 450 #define M_FW_FILTER_WR_PRIO 0x1 451 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 452 #define G_FW_FILTER_WR_PRIO(x) \ 453 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 454 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 455 456 #define S_FW_FILTER_WR_L2TIX 0 457 #define M_FW_FILTER_WR_L2TIX 0xfff 458 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 459 #define G_FW_FILTER_WR_L2TIX(x) \ 460 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 461 462 #define S_FW_FILTER_WR_FRAG 7 463 #define M_FW_FILTER_WR_FRAG 0x1 464 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 465 #define G_FW_FILTER_WR_FRAG(x) \ 466 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 467 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 468 469 #define S_FW_FILTER_WR_FRAGM 6 470 #define M_FW_FILTER_WR_FRAGM 0x1 471 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 472 #define G_FW_FILTER_WR_FRAGM(x) \ 473 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 474 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 475 476 #define S_FW_FILTER_WR_IVLAN_VLD 5 477 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 478 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 479 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 480 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 481 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 482 483 #define S_FW_FILTER_WR_OVLAN_VLD 4 484 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 485 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 486 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 487 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 488 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 489 490 #define S_FW_FILTER_WR_IVLAN_VLDM 3 491 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 492 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 493 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 494 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 495 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 496 497 #define S_FW_FILTER_WR_OVLAN_VLDM 2 498 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 499 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 500 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 501 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 502 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 503 504 #define S_FW_FILTER_WR_RX_CHAN 15 505 #define M_FW_FILTER_WR_RX_CHAN 0x1 506 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 507 #define G_FW_FILTER_WR_RX_CHAN(x) \ 508 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 509 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 510 511 #define S_FW_FILTER_WR_RX_RPL_IQ 0 512 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 513 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 514 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 515 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 516 517 #define S_FW_FILTER_WR_MACI 23 518 #define M_FW_FILTER_WR_MACI 0x1ff 519 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 520 #define G_FW_FILTER_WR_MACI(x) \ 521 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 522 523 #define S_FW_FILTER_WR_MACIM 14 524 #define M_FW_FILTER_WR_MACIM 0x1ff 525 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 526 #define G_FW_FILTER_WR_MACIM(x) \ 527 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 528 529 #define S_FW_FILTER_WR_FCOE 13 530 #define M_FW_FILTER_WR_FCOE 0x1 531 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 532 #define G_FW_FILTER_WR_FCOE(x) \ 533 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 534 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 535 536 #define S_FW_FILTER_WR_FCOEM 12 537 #define M_FW_FILTER_WR_FCOEM 0x1 538 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 539 #define G_FW_FILTER_WR_FCOEM(x) \ 540 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 541 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 542 543 #define S_FW_FILTER_WR_PORT 9 544 #define M_FW_FILTER_WR_PORT 0x7 545 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 546 #define G_FW_FILTER_WR_PORT(x) \ 547 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 548 549 #define S_FW_FILTER_WR_PORTM 6 550 #define M_FW_FILTER_WR_PORTM 0x7 551 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 552 #define G_FW_FILTER_WR_PORTM(x) \ 553 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 554 555 #define S_FW_FILTER_WR_MATCHTYPE 3 556 #define M_FW_FILTER_WR_MATCHTYPE 0x7 557 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 558 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 559 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 560 561 #define S_FW_FILTER_WR_MATCHTYPEM 0 562 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 563 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 564 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 565 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 566 567 struct fw_ulptx_wr { 568 __be32 op_to_compl; 569 __be32 flowid_len16; 570 __u64 cookie; 571 }; 572 573 struct fw_tp_wr { 574 __be32 op_to_immdlen; 575 __be32 flowid_len16; 576 __u64 cookie; 577 }; 578 579 struct fw_eth_tx_pkt_wr { 580 __be32 op_immdlen; 581 __be32 equiq_to_len16; 582 __be64 r3; 583 }; 584 585 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 586 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 587 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 588 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 589 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 590 591 struct fw_eth_tx_pkt2_wr { 592 __be32 op_immdlen; 593 __be32 equiq_to_len16; 594 __be32 r3; 595 __be32 L4ChkDisable_to_IpHdrLen; 596 }; 597 598 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 599 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 600 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 601 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 602 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 603 604 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 605 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 606 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 607 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 608 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 609 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 610 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 611 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 612 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 613 614 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 615 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 616 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 617 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 618 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 619 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 620 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 621 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 622 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 623 624 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 625 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 626 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 627 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 628 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 629 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 630 631 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 632 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 633 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 634 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 635 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 636 637 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 638 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 639 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 640 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 641 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 642 643 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 644 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 645 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 646 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 647 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 648 649 struct fw_eth_tx_pkts_wr { 650 __be32 op_pkd; 651 __be32 equiq_to_len16; 652 __be32 r3; 653 __be16 plen; 654 __u8 npkt; 655 __u8 type; 656 }; 657 658 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 659 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 660 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 661 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 662 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 663 664 struct fw_eth_tx_pkt_ptp_wr { 665 __be32 op_immdlen; 666 __be32 equiq_to_len16; 667 __be64 r3; 668 }; 669 670 enum fw_eth_tx_eo_type { 671 FW_ETH_TX_EO_TYPE_UDPSEG, 672 FW_ETH_TX_EO_TYPE_TCPSEG, 673 FW_ETH_TX_EO_TYPE_NVGRESEG, 674 FW_ETH_TX_EO_TYPE_VXLANSEG, 675 FW_ETH_TX_EO_TYPE_GENEVESEG, 676 }; 677 678 struct fw_eth_tx_eo_wr { 679 __be32 op_immdlen; 680 __be32 equiq_to_len16; 681 __be64 r3; 682 union fw_eth_tx_eo { 683 struct fw_eth_tx_eo_udpseg { 684 __u8 type; 685 __u8 ethlen; 686 __be16 iplen; 687 __u8 udplen; 688 __u8 rtplen; 689 __be16 r4; 690 __be16 mss; 691 __be16 schedpktsize; 692 __be32 plen; 693 } udpseg; 694 struct fw_eth_tx_eo_tcpseg { 695 __u8 type; 696 __u8 ethlen; 697 __be16 iplen; 698 __u8 tcplen; 699 __u8 tsclk_tsoff; 700 __be16 r4; 701 __be16 mss; 702 __be16 r5; 703 __be32 plen; 704 } tcpseg; 705 struct fw_eth_tx_eo_nvgreseg { 706 __u8 type; 707 __u8 iphdroffout; 708 __be16 grehdroff; 709 __be16 iphdroffin; 710 __be16 tcphdroffin; 711 __be16 mss; 712 __be16 r4; 713 __be32 plen; 714 } nvgreseg; 715 struct fw_eth_tx_eo_vxlanseg { 716 __u8 type; 717 __u8 iphdroffout; 718 __be16 vxlanhdroff; 719 __be16 iphdroffin; 720 __be16 tcphdroffin; 721 __be16 mss; 722 __be16 r4; 723 __be32 plen; 724 725 } vxlanseg; 726 struct fw_eth_tx_eo_geneveseg { 727 __u8 type; 728 __u8 iphdroffout; 729 __be16 genevehdroff; 730 __be16 iphdroffin; 731 __be16 tcphdroffin; 732 __be16 mss; 733 __be16 r4; 734 __be32 plen; 735 } geneveseg; 736 } u; 737 }; 738 739 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0 740 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 741 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 742 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 743 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 744 745 #define S_FW_ETH_TX_EO_WR_TSCLK 6 746 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3 747 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 748 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 749 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 750 751 #define S_FW_ETH_TX_EO_WR_TSOFF 0 752 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 753 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 754 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 755 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 756 757 struct fw_eq_flush_wr { 758 __u8 opcode; 759 __u8 r1[3]; 760 __be32 equiq_to_len16; 761 __be64 r3; 762 }; 763 764 struct fw_ofld_connection_wr { 765 __be32 op_compl; 766 __be32 len16_pkd; 767 __u64 cookie; 768 __be64 r2; 769 __be64 r3; 770 struct fw_ofld_connection_le { 771 __be32 version_cpl; 772 __be32 filter; 773 __be32 r1; 774 __be16 lport; 775 __be16 pport; 776 union fw_ofld_connection_leip { 777 struct fw_ofld_connection_le_ipv4 { 778 __be32 pip; 779 __be32 lip; 780 __be64 r0; 781 __be64 r1; 782 __be64 r2; 783 } ipv4; 784 struct fw_ofld_connection_le_ipv6 { 785 __be64 pip_hi; 786 __be64 pip_lo; 787 __be64 lip_hi; 788 __be64 lip_lo; 789 } ipv6; 790 } u; 791 } le; 792 struct fw_ofld_connection_tcb { 793 __be32 t_state_to_astid; 794 __be16 cplrxdataack_cplpassacceptrpl; 795 __be16 rcv_adv; 796 __be32 rcv_nxt; 797 __be32 tx_max; 798 __be64 opt0; 799 __be32 opt2; 800 __be32 r1; 801 __be64 r2; 802 __be64 r3; 803 } tcb; 804 }; 805 806 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 807 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 808 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 809 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 810 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 811 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 812 M_FW_OFLD_CONNECTION_WR_VERSION) 813 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 814 815 #define S_FW_OFLD_CONNECTION_WR_CPL 30 816 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 817 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 818 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 819 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 820 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 821 822 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 823 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 824 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 825 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 826 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 827 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 828 M_FW_OFLD_CONNECTION_WR_T_STATE) 829 830 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 831 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 832 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 833 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 834 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 835 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 836 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 837 838 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 839 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 840 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 841 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 842 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 843 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 844 845 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 846 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 847 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 848 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 849 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 850 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 851 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 852 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 853 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 854 855 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 856 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 857 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 858 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 859 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 860 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 861 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 862 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 863 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 864 865 enum fw_flowc_mnem_tcpstate { 866 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 867 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 868 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 869 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 870 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 871 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 872 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 873 * will resend FIN - equiv ESTAB 874 */ 875 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 876 * will resend FIN but have 877 * received FIN 878 */ 879 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 880 * will resend FIN but have 881 * received FIN 882 */ 883 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 884 * waiting for FIN 885 */ 886 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 887 }; 888 889 enum fw_flowc_mnem_eostate { 890 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 891 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 892 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 893 * outstanding payload 894 */ 895 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 896 * discarding outstanding payload 897 */ 898 }; 899 900 enum fw_flowc_mnem { 901 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 902 FW_FLOWC_MNEM_CH = 1, 903 FW_FLOWC_MNEM_PORT = 2, 904 FW_FLOWC_MNEM_IQID = 3, 905 FW_FLOWC_MNEM_SNDNXT = 4, 906 FW_FLOWC_MNEM_RCVNXT = 5, 907 FW_FLOWC_MNEM_SNDBUF = 6, 908 FW_FLOWC_MNEM_MSS = 7, 909 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 910 FW_FLOWC_MNEM_TCPSTATE = 9, 911 FW_FLOWC_MNEM_EOSTATE = 10, 912 FW_FLOWC_MNEM_SCHEDCLASS = 11, 913 FW_FLOWC_MNEM_DCBPRIO = 12, 914 FW_FLOWC_MNEM_SND_SCALE = 13, 915 FW_FLOWC_MNEM_RCV_SCALE = 14, 916 }; 917 918 struct fw_flowc_mnemval { 919 __u8 mnemonic; 920 __u8 r4[3]; 921 __be32 val; 922 }; 923 924 struct fw_flowc_wr { 925 __be32 op_to_nparams; 926 __be32 flowid_len16; 927 #ifndef C99_NOT_SUPPORTED 928 struct fw_flowc_mnemval mnemval[0]; 929 #endif 930 }; 931 932 #define S_FW_FLOWC_WR_NPARAMS 0 933 #define M_FW_FLOWC_WR_NPARAMS 0xff 934 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 935 #define G_FW_FLOWC_WR_NPARAMS(x) \ 936 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 937 938 struct fw_ofld_tx_data_wr { 939 __be32 op_to_immdlen; 940 __be32 flowid_len16; 941 __be32 plen; 942 __be32 lsodisable_to_flags; 943 }; 944 945 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 946 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 947 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 948 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 949 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 950 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 951 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 952 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 953 954 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 955 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 956 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 957 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 958 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 959 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 960 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 961 962 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 963 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 964 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 965 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 966 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 967 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 968 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 969 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 970 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 971 972 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0 973 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 974 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 975 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 976 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 977 978 979 /* Use fw_ofld_tx_data_wr structure */ 980 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 981 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 982 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 983 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 984 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 985 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 986 987 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 988 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 989 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 990 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 991 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 992 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 993 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 994 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 995 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 996 997 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 998 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 999 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1000 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1001 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1002 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 1003 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1004 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 1005 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1006 1007 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1008 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1009 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1010 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1011 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1012 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1013 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1014 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1015 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1016 1017 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1018 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1019 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1020 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1021 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1022 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1023 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1024 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1025 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1026 1027 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1028 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1029 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1030 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1031 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1032 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1033 1034 struct fw_cmd_wr { 1035 __be32 op_dma; 1036 __be32 len16_pkd; 1037 __be64 cookie_daddr; 1038 }; 1039 1040 #define S_FW_CMD_WR_DMA 17 1041 #define M_FW_CMD_WR_DMA 0x1 1042 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1043 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1044 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1045 1046 struct fw_eth_tx_pkt_vm_wr { 1047 __be32 op_immdlen; 1048 __be32 equiq_to_len16; 1049 __be32 r3[2]; 1050 __u8 ethmacdst[6]; 1051 __u8 ethmacsrc[6]; 1052 __be16 ethtype; 1053 __be16 vlantci; 1054 }; 1055 1056 /****************************************************************************** 1057 * R I W O R K R E Q U E S T s 1058 **************************************/ 1059 1060 enum fw_ri_wr_opcode { 1061 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1062 FW_RI_READ_REQ = 0x1, 1063 FW_RI_READ_RESP = 0x2, 1064 FW_RI_SEND = 0x3, 1065 FW_RI_SEND_WITH_INV = 0x4, 1066 FW_RI_SEND_WITH_SE = 0x5, 1067 FW_RI_SEND_WITH_SE_INV = 0x6, 1068 FW_RI_TERMINATE = 0x7, 1069 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1070 FW_RI_BIND_MW = 0x9, 1071 FW_RI_FAST_REGISTER = 0xa, 1072 FW_RI_LOCAL_INV = 0xb, 1073 FW_RI_QP_MODIFY = 0xc, 1074 FW_RI_BYPASS = 0xd, 1075 FW_RI_RECEIVE = 0xe, 1076 #if 0 1077 FW_RI_SEND_IMMEDIATE = 0x8, 1078 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1079 FW_RI_ATOMIC_REQUEST = 0xa, 1080 FW_RI_ATOMIC_RESPONSE = 0xb, 1081 1082 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1083 FW_RI_FAST_REGISTER = 0xd, 1084 FW_RI_LOCAL_INV = 0xe, 1085 #endif 1086 FW_RI_SGE_EC_CR_RETURN = 0xf 1087 }; 1088 1089 enum fw_ri_wr_flags { 1090 FW_RI_COMPLETION_FLAG = 0x01, 1091 FW_RI_NOTIFICATION_FLAG = 0x02, 1092 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1093 FW_RI_READ_FENCE_FLAG = 0x08, 1094 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1095 FW_RI_RDMA_READ_INVALIDATE = 0x20 1096 }; 1097 1098 enum fw_ri_mpa_attrs { 1099 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1100 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1101 FW_RI_MPA_CRC_ENABLE = 0x04, 1102 FW_RI_MPA_IETF_ENABLE = 0x08 1103 }; 1104 1105 enum fw_ri_qp_caps { 1106 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1107 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1108 FW_RI_QP_BIND_ENABLE = 0x04, 1109 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1110 FW_RI_QP_STAG0_ENABLE = 0x10, 1111 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1112 }; 1113 1114 enum fw_ri_addr_type { 1115 FW_RI_ZERO_BASED_TO = 0x00, 1116 FW_RI_VA_BASED_TO = 0x01 1117 }; 1118 1119 enum fw_ri_mem_perms { 1120 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1121 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1122 FW_RI_MEM_ACCESS_REM = 0x03, 1123 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1124 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1125 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1126 }; 1127 1128 enum fw_ri_stag_type { 1129 FW_RI_STAG_NSMR = 0x00, 1130 FW_RI_STAG_SMR = 0x01, 1131 FW_RI_STAG_MW = 0x02, 1132 FW_RI_STAG_MW_RELAXED = 0x03 1133 }; 1134 1135 enum fw_ri_data_op { 1136 FW_RI_DATA_IMMD = 0x81, 1137 FW_RI_DATA_DSGL = 0x82, 1138 FW_RI_DATA_ISGL = 0x83 1139 }; 1140 1141 enum fw_ri_sgl_depth { 1142 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1143 FW_RI_SGL_DEPTH_MAX_RQ = 4 1144 }; 1145 1146 enum fw_ri_cqe_err { 1147 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1148 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1149 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1150 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1151 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1152 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1153 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1154 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1155 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1156 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1157 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1158 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1159 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1160 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1161 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1162 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1163 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1164 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1165 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1166 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1167 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1168 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1169 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1170 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1171 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1172 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1173 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1174 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1175 1176 }; 1177 1178 struct fw_ri_dsge_pair { 1179 __be32 len[2]; 1180 __be64 addr[2]; 1181 }; 1182 1183 struct fw_ri_dsgl { 1184 __u8 op; 1185 __u8 r1; 1186 __be16 nsge; 1187 __be32 len0; 1188 __be64 addr0; 1189 #ifndef C99_NOT_SUPPORTED 1190 struct fw_ri_dsge_pair sge[0]; 1191 #endif 1192 }; 1193 1194 struct fw_ri_sge { 1195 __be32 stag; 1196 __be32 len; 1197 __be64 to; 1198 }; 1199 1200 struct fw_ri_isgl { 1201 __u8 op; 1202 __u8 r1; 1203 __be16 nsge; 1204 __be32 r2; 1205 #ifndef C99_NOT_SUPPORTED 1206 struct fw_ri_sge sge[0]; 1207 #endif 1208 }; 1209 1210 struct fw_ri_immd { 1211 __u8 op; 1212 __u8 r1; 1213 __be16 r2; 1214 __be32 immdlen; 1215 #ifndef C99_NOT_SUPPORTED 1216 __u8 data[0]; 1217 #endif 1218 }; 1219 1220 struct fw_ri_tpte { 1221 __be32 valid_to_pdid; 1222 __be32 locread_to_qpid; 1223 __be32 nosnoop_pbladdr; 1224 __be32 len_lo; 1225 __be32 va_hi; 1226 __be32 va_lo_fbo; 1227 __be32 dca_mwbcnt_pstag; 1228 __be32 len_hi; 1229 }; 1230 1231 #define S_FW_RI_TPTE_VALID 31 1232 #define M_FW_RI_TPTE_VALID 0x1 1233 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1234 #define G_FW_RI_TPTE_VALID(x) \ 1235 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1236 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1237 1238 #define S_FW_RI_TPTE_STAGKEY 23 1239 #define M_FW_RI_TPTE_STAGKEY 0xff 1240 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1241 #define G_FW_RI_TPTE_STAGKEY(x) \ 1242 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1243 1244 #define S_FW_RI_TPTE_STAGSTATE 22 1245 #define M_FW_RI_TPTE_STAGSTATE 0x1 1246 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1247 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1248 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1249 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1250 1251 #define S_FW_RI_TPTE_STAGTYPE 20 1252 #define M_FW_RI_TPTE_STAGTYPE 0x3 1253 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1254 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1255 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1256 1257 #define S_FW_RI_TPTE_PDID 0 1258 #define M_FW_RI_TPTE_PDID 0xfffff 1259 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1260 #define G_FW_RI_TPTE_PDID(x) \ 1261 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1262 1263 #define S_FW_RI_TPTE_PERM 28 1264 #define M_FW_RI_TPTE_PERM 0xf 1265 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1266 #define G_FW_RI_TPTE_PERM(x) \ 1267 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1268 1269 #define S_FW_RI_TPTE_REMINVDIS 27 1270 #define M_FW_RI_TPTE_REMINVDIS 0x1 1271 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1272 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1273 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1274 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1275 1276 #define S_FW_RI_TPTE_ADDRTYPE 26 1277 #define M_FW_RI_TPTE_ADDRTYPE 1 1278 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1279 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1280 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1281 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1282 1283 #define S_FW_RI_TPTE_MWBINDEN 25 1284 #define M_FW_RI_TPTE_MWBINDEN 0x1 1285 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1286 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1287 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1288 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1289 1290 #define S_FW_RI_TPTE_PS 20 1291 #define M_FW_RI_TPTE_PS 0x1f 1292 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1293 #define G_FW_RI_TPTE_PS(x) \ 1294 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1295 1296 #define S_FW_RI_TPTE_QPID 0 1297 #define M_FW_RI_TPTE_QPID 0xfffff 1298 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1299 #define G_FW_RI_TPTE_QPID(x) \ 1300 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1301 1302 #define S_FW_RI_TPTE_NOSNOOP 31 1303 #define M_FW_RI_TPTE_NOSNOOP 0x1 1304 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1305 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1306 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1307 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1308 1309 #define S_FW_RI_TPTE_PBLADDR 0 1310 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1311 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1312 #define G_FW_RI_TPTE_PBLADDR(x) \ 1313 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1314 1315 #define S_FW_RI_TPTE_DCA 24 1316 #define M_FW_RI_TPTE_DCA 0x1f 1317 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1318 #define G_FW_RI_TPTE_DCA(x) \ 1319 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1320 1321 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1322 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1323 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1324 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1325 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1326 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1327 1328 enum fw_ri_cqe_rxtx { 1329 FW_RI_CQE_RXTX_RX = 0x0, 1330 FW_RI_CQE_RXTX_TX = 0x1, 1331 }; 1332 1333 struct fw_ri_cqe { 1334 union fw_ri_rxtx { 1335 struct fw_ri_scqe { 1336 __be32 qpid_n_stat_rxtx_type; 1337 __be32 plen; 1338 __be32 reserved; 1339 __be32 wrid; 1340 } scqe; 1341 struct fw_ri_rcqe { 1342 __be32 qpid_n_stat_rxtx_type; 1343 __be32 plen; 1344 __be32 stag; 1345 __be32 msn; 1346 } rcqe; 1347 } u; 1348 }; 1349 1350 #define S_FW_RI_CQE_QPID 12 1351 #define M_FW_RI_CQE_QPID 0xfffff 1352 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1353 #define G_FW_RI_CQE_QPID(x) \ 1354 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1355 1356 #define S_FW_RI_CQE_NOTIFY 10 1357 #define M_FW_RI_CQE_NOTIFY 0x1 1358 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1359 #define G_FW_RI_CQE_NOTIFY(x) \ 1360 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1361 1362 #define S_FW_RI_CQE_STATUS 5 1363 #define M_FW_RI_CQE_STATUS 0x1f 1364 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1365 #define G_FW_RI_CQE_STATUS(x) \ 1366 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1367 1368 1369 #define S_FW_RI_CQE_RXTX 4 1370 #define M_FW_RI_CQE_RXTX 0x1 1371 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1372 #define G_FW_RI_CQE_RXTX(x) \ 1373 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1374 1375 #define S_FW_RI_CQE_TYPE 0 1376 #define M_FW_RI_CQE_TYPE 0xf 1377 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1378 #define G_FW_RI_CQE_TYPE(x) \ 1379 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1380 1381 enum fw_ri_res_type { 1382 FW_RI_RES_TYPE_SQ, 1383 FW_RI_RES_TYPE_RQ, 1384 FW_RI_RES_TYPE_CQ, 1385 FW_RI_RES_TYPE_SRQ, 1386 }; 1387 1388 enum fw_ri_res_op { 1389 FW_RI_RES_OP_WRITE, 1390 FW_RI_RES_OP_RESET, 1391 }; 1392 1393 struct fw_ri_res { 1394 union fw_ri_restype { 1395 struct fw_ri_res_sqrq { 1396 __u8 restype; 1397 __u8 op; 1398 __be16 r3; 1399 __be32 eqid; 1400 __be32 r4[2]; 1401 __be32 fetchszm_to_iqid; 1402 __be32 dcaen_to_eqsize; 1403 __be64 eqaddr; 1404 } sqrq; 1405 struct fw_ri_res_cq { 1406 __u8 restype; 1407 __u8 op; 1408 __be16 r3; 1409 __be32 iqid; 1410 __be32 r4[2]; 1411 __be32 iqandst_to_iqandstindex; 1412 __be16 iqdroprss_to_iqesize; 1413 __be16 iqsize; 1414 __be64 iqaddr; 1415 __be32 iqns_iqro; 1416 __be32 r6_lo; 1417 __be64 r7; 1418 } cq; 1419 struct fw_ri_res_srq { 1420 __u8 restype; 1421 __u8 op; 1422 __be16 r3; 1423 __be32 eqid; 1424 __be32 r4[2]; 1425 __be32 fetchszm_to_iqid; 1426 __be32 dcaen_to_eqsize; 1427 __be64 eqaddr; 1428 __be32 srqid; 1429 __be32 pdid; 1430 __be32 hwsrqsize; 1431 __be32 hwsrqaddr; 1432 } srq; 1433 } u; 1434 }; 1435 1436 struct fw_ri_res_wr { 1437 __be32 op_nres; 1438 __be32 len16_pkd; 1439 __u64 cookie; 1440 #ifndef C99_NOT_SUPPORTED 1441 struct fw_ri_res res[0]; 1442 #endif 1443 }; 1444 1445 #define S_FW_RI_RES_WR_NRES 0 1446 #define M_FW_RI_RES_WR_NRES 0xff 1447 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1448 #define G_FW_RI_RES_WR_NRES(x) \ 1449 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1450 1451 #define S_FW_RI_RES_WR_FETCHSZM 26 1452 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1453 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1454 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1455 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1456 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1457 1458 #define S_FW_RI_RES_WR_STATUSPGNS 25 1459 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1460 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1461 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1462 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1463 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1464 1465 #define S_FW_RI_RES_WR_STATUSPGRO 24 1466 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1467 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1468 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1469 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1470 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1471 1472 #define S_FW_RI_RES_WR_FETCHNS 23 1473 #define M_FW_RI_RES_WR_FETCHNS 0x1 1474 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1475 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1476 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1477 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1478 1479 #define S_FW_RI_RES_WR_FETCHRO 22 1480 #define M_FW_RI_RES_WR_FETCHRO 0x1 1481 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1482 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1483 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1484 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1485 1486 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1487 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1488 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1489 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1490 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1491 1492 #define S_FW_RI_RES_WR_CPRIO 19 1493 #define M_FW_RI_RES_WR_CPRIO 0x1 1494 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1495 #define G_FW_RI_RES_WR_CPRIO(x) \ 1496 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1497 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1498 1499 #define S_FW_RI_RES_WR_ONCHIP 18 1500 #define M_FW_RI_RES_WR_ONCHIP 0x1 1501 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1502 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1503 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1504 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1505 1506 #define S_FW_RI_RES_WR_PCIECHN 16 1507 #define M_FW_RI_RES_WR_PCIECHN 0x3 1508 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1509 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1510 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1511 1512 #define S_FW_RI_RES_WR_IQID 0 1513 #define M_FW_RI_RES_WR_IQID 0xffff 1514 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1515 #define G_FW_RI_RES_WR_IQID(x) \ 1516 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1517 1518 #define S_FW_RI_RES_WR_DCAEN 31 1519 #define M_FW_RI_RES_WR_DCAEN 0x1 1520 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1521 #define G_FW_RI_RES_WR_DCAEN(x) \ 1522 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1523 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1524 1525 #define S_FW_RI_RES_WR_DCACPU 26 1526 #define M_FW_RI_RES_WR_DCACPU 0x1f 1527 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1528 #define G_FW_RI_RES_WR_DCACPU(x) \ 1529 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1530 1531 #define S_FW_RI_RES_WR_FBMIN 23 1532 #define M_FW_RI_RES_WR_FBMIN 0x7 1533 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1534 #define G_FW_RI_RES_WR_FBMIN(x) \ 1535 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1536 1537 #define S_FW_RI_RES_WR_FBMAX 20 1538 #define M_FW_RI_RES_WR_FBMAX 0x7 1539 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1540 #define G_FW_RI_RES_WR_FBMAX(x) \ 1541 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1542 1543 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1544 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1545 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1546 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1547 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1548 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1549 1550 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1551 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1552 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1553 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1554 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1555 1556 #define S_FW_RI_RES_WR_EQSIZE 0 1557 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1558 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1559 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1560 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1561 1562 #define S_FW_RI_RES_WR_IQANDST 15 1563 #define M_FW_RI_RES_WR_IQANDST 0x1 1564 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1565 #define G_FW_RI_RES_WR_IQANDST(x) \ 1566 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1567 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1568 1569 #define S_FW_RI_RES_WR_IQANUS 14 1570 #define M_FW_RI_RES_WR_IQANUS 0x1 1571 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1572 #define G_FW_RI_RES_WR_IQANUS(x) \ 1573 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1574 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1575 1576 #define S_FW_RI_RES_WR_IQANUD 12 1577 #define M_FW_RI_RES_WR_IQANUD 0x3 1578 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1579 #define G_FW_RI_RES_WR_IQANUD(x) \ 1580 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1581 1582 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1583 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1584 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1585 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1586 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1587 1588 #define S_FW_RI_RES_WR_IQDROPRSS 15 1589 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1590 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1591 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1592 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1593 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1594 1595 #define S_FW_RI_RES_WR_IQGTSMODE 14 1596 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1597 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1598 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1599 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1600 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1601 1602 #define S_FW_RI_RES_WR_IQPCIECH 12 1603 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1604 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1605 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1606 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1607 1608 #define S_FW_RI_RES_WR_IQDCAEN 11 1609 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1610 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1611 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1612 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1613 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1614 1615 #define S_FW_RI_RES_WR_IQDCACPU 6 1616 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1617 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1618 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1619 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1620 1621 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1622 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1623 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1624 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1625 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1626 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1627 1628 #define S_FW_RI_RES_WR_IQO 3 1629 #define M_FW_RI_RES_WR_IQO 0x1 1630 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1631 #define G_FW_RI_RES_WR_IQO(x) \ 1632 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1633 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1634 1635 #define S_FW_RI_RES_WR_IQCPRIO 2 1636 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1637 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1638 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1639 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1640 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1641 1642 #define S_FW_RI_RES_WR_IQESIZE 0 1643 #define M_FW_RI_RES_WR_IQESIZE 0x3 1644 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1645 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1646 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1647 1648 #define S_FW_RI_RES_WR_IQNS 31 1649 #define M_FW_RI_RES_WR_IQNS 0x1 1650 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1651 #define G_FW_RI_RES_WR_IQNS(x) \ 1652 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1653 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1654 1655 #define S_FW_RI_RES_WR_IQRO 30 1656 #define M_FW_RI_RES_WR_IQRO 0x1 1657 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1658 #define G_FW_RI_RES_WR_IQRO(x) \ 1659 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1660 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1661 1662 struct fw_ri_rdma_write_wr { 1663 __u8 opcode; 1664 __u8 flags; 1665 __u16 wrid; 1666 __u8 r1[3]; 1667 __u8 len16; 1668 __be64 r2; 1669 __be32 plen; 1670 __be32 stag_sink; 1671 __be64 to_sink; 1672 #ifndef C99_NOT_SUPPORTED 1673 union { 1674 struct fw_ri_immd immd_src[0]; 1675 struct fw_ri_isgl isgl_src[0]; 1676 } u; 1677 #endif 1678 }; 1679 1680 struct fw_ri_send_wr { 1681 __u8 opcode; 1682 __u8 flags; 1683 __u16 wrid; 1684 __u8 r1[3]; 1685 __u8 len16; 1686 __be32 sendop_pkd; 1687 __be32 stag_inv; 1688 __be32 plen; 1689 __be32 r3; 1690 __be64 r4; 1691 #ifndef C99_NOT_SUPPORTED 1692 union { 1693 struct fw_ri_immd immd_src[0]; 1694 struct fw_ri_isgl isgl_src[0]; 1695 } u; 1696 #endif 1697 }; 1698 1699 #define S_FW_RI_SEND_WR_SENDOP 0 1700 #define M_FW_RI_SEND_WR_SENDOP 0xf 1701 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1702 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1703 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1704 1705 struct fw_ri_rdma_read_wr { 1706 __u8 opcode; 1707 __u8 flags; 1708 __u16 wrid; 1709 __u8 r1[3]; 1710 __u8 len16; 1711 __be64 r2; 1712 __be32 stag_sink; 1713 __be32 to_sink_hi; 1714 __be32 to_sink_lo; 1715 __be32 plen; 1716 __be32 stag_src; 1717 __be32 to_src_hi; 1718 __be32 to_src_lo; 1719 __be32 r5; 1720 }; 1721 1722 struct fw_ri_recv_wr { 1723 __u8 opcode; 1724 __u8 r1; 1725 __u16 wrid; 1726 __u8 r2[3]; 1727 __u8 len16; 1728 struct fw_ri_isgl isgl; 1729 }; 1730 1731 struct fw_ri_bind_mw_wr { 1732 __u8 opcode; 1733 __u8 flags; 1734 __u16 wrid; 1735 __u8 r1[3]; 1736 __u8 len16; 1737 __u8 qpbinde_to_dcacpu; 1738 __u8 pgsz_shift; 1739 __u8 addr_type; 1740 __u8 mem_perms; 1741 __be32 stag_mr; 1742 __be32 stag_mw; 1743 __be32 r3; 1744 __be64 len_mw; 1745 __be64 va_fbo; 1746 __be64 r4; 1747 }; 1748 1749 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1750 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1751 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1752 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1753 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1754 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1755 1756 #define S_FW_RI_BIND_MW_WR_NS 5 1757 #define M_FW_RI_BIND_MW_WR_NS 0x1 1758 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1759 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1760 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1761 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1762 1763 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1764 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1765 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1766 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1767 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1768 1769 struct fw_ri_fr_nsmr_wr { 1770 __u8 opcode; 1771 __u8 flags; 1772 __u16 wrid; 1773 __u8 r1[3]; 1774 __u8 len16; 1775 __u8 qpbinde_to_dcacpu; 1776 __u8 pgsz_shift; 1777 __u8 addr_type; 1778 __u8 mem_perms; 1779 __be32 stag; 1780 __be32 len_hi; 1781 __be32 len_lo; 1782 __be32 va_hi; 1783 __be32 va_lo_fbo; 1784 }; 1785 1786 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1787 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1788 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1789 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1790 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1791 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1792 1793 #define S_FW_RI_FR_NSMR_WR_NS 5 1794 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1795 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1796 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1797 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1798 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1799 1800 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1801 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1802 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1803 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1804 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1805 1806 struct fw_ri_inv_lstag_wr { 1807 __u8 opcode; 1808 __u8 flags; 1809 __u16 wrid; 1810 __u8 r1[3]; 1811 __u8 len16; 1812 __be32 r2; 1813 __be32 stag_inv; 1814 }; 1815 1816 struct fw_ri_send_immediate_wr { 1817 __u8 opcode; 1818 __u8 flags; 1819 __u16 wrid; 1820 __u8 r1[3]; 1821 __u8 len16; 1822 __be32 sendimmop_pkd; 1823 __be32 r3; 1824 __be32 plen; 1825 __be32 r4; 1826 __be64 r5; 1827 #ifndef C99_NOT_SUPPORTED 1828 struct fw_ri_immd immd_src[0]; 1829 #endif 1830 }; 1831 1832 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1833 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1834 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1835 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1836 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1837 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1838 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1839 1840 enum fw_ri_atomic_op { 1841 FW_RI_ATOMIC_OP_FETCHADD, 1842 FW_RI_ATOMIC_OP_SWAP, 1843 FW_RI_ATOMIC_OP_CMDSWAP, 1844 }; 1845 1846 struct fw_ri_atomic_wr { 1847 __u8 opcode; 1848 __u8 flags; 1849 __u16 wrid; 1850 __u8 r1[3]; 1851 __u8 len16; 1852 __be32 atomicop_pkd; 1853 __be64 r3; 1854 __be32 aopcode_pkd; 1855 __be32 reqid; 1856 __be32 stag; 1857 __be32 to_hi; 1858 __be32 to_lo; 1859 __be32 addswap_data_hi; 1860 __be32 addswap_data_lo; 1861 __be32 addswap_mask_hi; 1862 __be32 addswap_mask_lo; 1863 __be32 compare_data_hi; 1864 __be32 compare_data_lo; 1865 __be32 compare_mask_hi; 1866 __be32 compare_mask_lo; 1867 __be32 r5; 1868 }; 1869 1870 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1871 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1872 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 1873 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 1874 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 1875 1876 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 1877 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 1878 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 1879 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 1880 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 1881 1882 enum fw_ri_type { 1883 FW_RI_TYPE_INIT, 1884 FW_RI_TYPE_FINI, 1885 FW_RI_TYPE_TERMINATE 1886 }; 1887 1888 enum fw_ri_init_p2ptype { 1889 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 1890 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 1891 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 1892 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 1893 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 1894 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 1895 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 1896 }; 1897 1898 enum fw_ri_init_rqeqid_srq { 1899 FW_RI_INIT_RQEQID_SRQ = 1 << 31, 1900 }; 1901 1902 struct fw_ri_wr { 1903 __be32 op_compl; 1904 __be32 flowid_len16; 1905 __u64 cookie; 1906 union fw_ri { 1907 struct fw_ri_init { 1908 __u8 type; 1909 __u8 mpareqbit_p2ptype; 1910 __u8 r4[2]; 1911 __u8 mpa_attrs; 1912 __u8 qp_caps; 1913 __be16 nrqe; 1914 __be32 pdid; 1915 __be32 qpid; 1916 __be32 sq_eqid; 1917 __be32 rq_eqid; 1918 __be32 scqid; 1919 __be32 rcqid; 1920 __be32 ord_max; 1921 __be32 ird_max; 1922 __be32 iss; 1923 __be32 irs; 1924 __be32 hwrqsize; 1925 __be32 hwrqaddr; 1926 __be64 r5; 1927 union fw_ri_init_p2p { 1928 struct fw_ri_rdma_write_wr write; 1929 struct fw_ri_rdma_read_wr read; 1930 struct fw_ri_send_wr send; 1931 } u; 1932 } init; 1933 struct fw_ri_fini { 1934 __u8 type; 1935 __u8 r3[7]; 1936 __be64 r4; 1937 } fini; 1938 struct fw_ri_terminate { 1939 __u8 type; 1940 __u8 r3[3]; 1941 __be32 immdlen; 1942 __u8 termmsg[40]; 1943 } terminate; 1944 } u; 1945 }; 1946 1947 #define S_FW_RI_WR_MPAREQBIT 7 1948 #define M_FW_RI_WR_MPAREQBIT 0x1 1949 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 1950 #define G_FW_RI_WR_MPAREQBIT(x) \ 1951 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 1952 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 1953 1954 #define S_FW_RI_WR_0BRRBIT 6 1955 #define M_FW_RI_WR_0BRRBIT 0x1 1956 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 1957 #define G_FW_RI_WR_0BRRBIT(x) \ 1958 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 1959 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 1960 1961 #define S_FW_RI_WR_P2PTYPE 0 1962 #define M_FW_RI_WR_P2PTYPE 0xf 1963 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 1964 #define G_FW_RI_WR_P2PTYPE(x) \ 1965 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 1966 1967 /****************************************************************************** 1968 * F O i S C S I W O R K R E Q U E S T s 1969 *********************************************/ 1970 1971 #define FW_FOISCSI_NAME_MAX_LEN 224 1972 #define FW_FOISCSI_ALIAS_MAX_LEN 224 1973 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 1974 #define FW_FOISCSI_INIT_NODE_MAX 8 1975 1976 enum fw_chnet_ifconf_wr_subop { 1977 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 1978 1979 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 1980 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 1981 1982 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 1983 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 1984 1985 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 1986 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 1987 1988 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 1989 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 1990 1991 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 1992 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 1993 1994 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 1995 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 1996 1997 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 1998 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 1999 2000 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 2001 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 2002 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 2003 2004 FW_CHNET_IFCONF_WR_SUBOP_MAX, 2005 }; 2006 2007 struct fw_chnet_ifconf_wr { 2008 __be32 op_compl; 2009 __be32 flowid_len16; 2010 __be64 cookie; 2011 __be32 if_flowid; 2012 __u8 idx; 2013 __u8 subop; 2014 __u8 retval; 2015 __u8 r2; 2016 __be64 r3; 2017 struct fw_chnet_ifconf_params { 2018 __be32 r0; 2019 __be16 vlanid; 2020 __be16 mtu; 2021 union fw_chnet_ifconf_addr_type { 2022 struct fw_chnet_ifconf_ipv4 { 2023 __be32 addr; 2024 __be32 mask; 2025 __be32 router; 2026 __be32 r0; 2027 __be64 r1; 2028 } ipv4; 2029 struct fw_chnet_ifconf_ipv6 { 2030 __u8 prefix_len; 2031 __u8 r0; 2032 __be16 r1; 2033 __be32 r2; 2034 __be64 addr_hi; 2035 __be64 addr_lo; 2036 __be64 router_hi; 2037 __be64 router_lo; 2038 } ipv6; 2039 } in_attr; 2040 } param; 2041 }; 2042 2043 enum fw_foiscsi_node_type { 2044 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 2045 FW_FOISCSI_NODE_TYPE_TARGET, 2046 }; 2047 2048 enum fw_foiscsi_session_type { 2049 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 2050 FW_FOISCSI_SESSION_TYPE_NORMAL, 2051 }; 2052 2053 enum fw_foiscsi_auth_policy { 2054 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 2055 FW_FOISCSI_AUTH_POLICY_MUTUAL, 2056 }; 2057 2058 enum fw_foiscsi_auth_method { 2059 FW_FOISCSI_AUTH_METHOD_NONE = 0, 2060 FW_FOISCSI_AUTH_METHOD_CHAP, 2061 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 2062 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 2063 }; 2064 2065 enum fw_foiscsi_digest_type { 2066 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 2067 FW_FOISCSI_DIGEST_TYPE_CRC32, 2068 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 2069 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 2070 }; 2071 2072 enum fw_foiscsi_wr_subop { 2073 FW_FOISCSI_WR_SUBOP_ADD = 1, 2074 FW_FOISCSI_WR_SUBOP_DEL = 2, 2075 FW_FOISCSI_WR_SUBOP_MOD = 4, 2076 }; 2077 2078 enum fw_foiscsi_ctrl_state { 2079 FW_FOISCSI_CTRL_STATE_FREE = 0, 2080 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 2081 FW_FOISCSI_CTRL_STATE_FAILED, 2082 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 2083 FW_FOISCSI_CTRL_STATE_REDIRECT, 2084 }; 2085 2086 struct fw_rdev_wr { 2087 __be32 op_to_immdlen; 2088 __be32 alloc_to_len16; 2089 __be64 cookie; 2090 __u8 protocol; 2091 __u8 event_cause; 2092 __u8 cur_state; 2093 __u8 prev_state; 2094 __be32 flags_to_assoc_flowid; 2095 union rdev_entry { 2096 struct fcoe_rdev_entry { 2097 __be32 flowid; 2098 __u8 protocol; 2099 __u8 event_cause; 2100 __u8 flags; 2101 __u8 rjt_reason; 2102 __u8 cur_login_st; 2103 __u8 prev_login_st; 2104 __be16 rcv_fr_sz; 2105 __u8 rd_xfer_rdy_to_rport_type; 2106 __u8 vft_to_qos; 2107 __u8 org_proc_assoc_to_acc_rsp_code; 2108 __u8 enh_disc_to_tgt; 2109 __u8 wwnn[8]; 2110 __u8 wwpn[8]; 2111 __be16 iqid; 2112 __u8 fc_oui[3]; 2113 __u8 r_id[3]; 2114 } fcoe_rdev; 2115 struct iscsi_rdev_entry { 2116 __be32 flowid; 2117 __u8 protocol; 2118 __u8 event_cause; 2119 __u8 flags; 2120 __u8 r3; 2121 __be16 iscsi_opts; 2122 __be16 tcp_opts; 2123 __be16 ip_opts; 2124 __be16 max_rcv_len; 2125 __be16 max_snd_len; 2126 __be16 first_brst_len; 2127 __be16 max_brst_len; 2128 __be16 r4; 2129 __be16 def_time2wait; 2130 __be16 def_time2ret; 2131 __be16 nop_out_intrvl; 2132 __be16 non_scsi_to; 2133 __be16 isid; 2134 __be16 tsid; 2135 __be16 port; 2136 __be16 tpgt; 2137 __u8 r5[6]; 2138 __be16 iqid; 2139 } iscsi_rdev; 2140 } u; 2141 }; 2142 2143 #define S_FW_RDEV_WR_IMMDLEN 0 2144 #define M_FW_RDEV_WR_IMMDLEN 0xff 2145 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2146 #define G_FW_RDEV_WR_IMMDLEN(x) \ 2147 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2148 2149 #define S_FW_RDEV_WR_ALLOC 31 2150 #define M_FW_RDEV_WR_ALLOC 0x1 2151 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2152 #define G_FW_RDEV_WR_ALLOC(x) \ 2153 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2154 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2155 2156 #define S_FW_RDEV_WR_FREE 30 2157 #define M_FW_RDEV_WR_FREE 0x1 2158 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2159 #define G_FW_RDEV_WR_FREE(x) \ 2160 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2161 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2162 2163 #define S_FW_RDEV_WR_MODIFY 29 2164 #define M_FW_RDEV_WR_MODIFY 0x1 2165 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2166 #define G_FW_RDEV_WR_MODIFY(x) \ 2167 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2168 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2169 2170 #define S_FW_RDEV_WR_FLOWID 8 2171 #define M_FW_RDEV_WR_FLOWID 0xfffff 2172 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2173 #define G_FW_RDEV_WR_FLOWID(x) \ 2174 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2175 2176 #define S_FW_RDEV_WR_LEN16 0 2177 #define M_FW_RDEV_WR_LEN16 0xff 2178 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2179 #define G_FW_RDEV_WR_LEN16(x) \ 2180 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2181 2182 #define S_FW_RDEV_WR_FLAGS 24 2183 #define M_FW_RDEV_WR_FLAGS 0xff 2184 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2185 #define G_FW_RDEV_WR_FLAGS(x) \ 2186 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2187 2188 #define S_FW_RDEV_WR_GET_NEXT 20 2189 #define M_FW_RDEV_WR_GET_NEXT 0xf 2190 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2191 #define G_FW_RDEV_WR_GET_NEXT(x) \ 2192 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2193 2194 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 2195 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2196 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2197 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2198 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2199 2200 #define S_FW_RDEV_WR_RJT 7 2201 #define M_FW_RDEV_WR_RJT 0x1 2202 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2203 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2204 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2205 2206 #define S_FW_RDEV_WR_REASON 0 2207 #define M_FW_RDEV_WR_REASON 0x7f 2208 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2209 #define G_FW_RDEV_WR_REASON(x) \ 2210 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2211 2212 #define S_FW_RDEV_WR_RD_XFER_RDY 7 2213 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2214 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2215 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2216 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2217 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2218 2219 #define S_FW_RDEV_WR_WR_XFER_RDY 6 2220 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2221 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2222 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2223 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2224 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2225 2226 #define S_FW_RDEV_WR_FC_SP 5 2227 #define M_FW_RDEV_WR_FC_SP 0x1 2228 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2229 #define G_FW_RDEV_WR_FC_SP(x) \ 2230 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2231 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2232 2233 #define S_FW_RDEV_WR_RPORT_TYPE 0 2234 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2235 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2236 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2237 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2238 2239 #define S_FW_RDEV_WR_VFT 7 2240 #define M_FW_RDEV_WR_VFT 0x1 2241 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2242 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2243 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2244 2245 #define S_FW_RDEV_WR_NPIV 6 2246 #define M_FW_RDEV_WR_NPIV 0x1 2247 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2248 #define G_FW_RDEV_WR_NPIV(x) \ 2249 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2250 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2251 2252 #define S_FW_RDEV_WR_CLASS 4 2253 #define M_FW_RDEV_WR_CLASS 0x3 2254 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2255 #define G_FW_RDEV_WR_CLASS(x) \ 2256 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2257 2258 #define S_FW_RDEV_WR_SEQ_DEL 3 2259 #define M_FW_RDEV_WR_SEQ_DEL 0x1 2260 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2261 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2262 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2263 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2264 2265 #define S_FW_RDEV_WR_PRIO_PREEMP 2 2266 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2267 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2268 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2269 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2270 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2271 2272 #define S_FW_RDEV_WR_PREF 1 2273 #define M_FW_RDEV_WR_PREF 0x1 2274 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2275 #define G_FW_RDEV_WR_PREF(x) \ 2276 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2277 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2278 2279 #define S_FW_RDEV_WR_QOS 0 2280 #define M_FW_RDEV_WR_QOS 0x1 2281 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2282 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2283 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2284 2285 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2286 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2287 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2288 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2289 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2290 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2291 2292 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2293 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2294 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2295 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2296 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2297 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2298 2299 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2300 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2301 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2302 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2303 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2304 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2305 2306 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2307 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2308 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2309 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2310 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2311 2312 #define S_FW_RDEV_WR_ENH_DISC 7 2313 #define M_FW_RDEV_WR_ENH_DISC 0x1 2314 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2315 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2316 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2317 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2318 2319 #define S_FW_RDEV_WR_REC 6 2320 #define M_FW_RDEV_WR_REC 0x1 2321 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2322 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2323 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2324 2325 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2326 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2327 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2328 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2329 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2330 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2331 2332 #define S_FW_RDEV_WR_RETRY 4 2333 #define M_FW_RDEV_WR_RETRY 0x1 2334 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2335 #define G_FW_RDEV_WR_RETRY(x) \ 2336 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2337 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2338 2339 #define S_FW_RDEV_WR_CONF_CMPL 3 2340 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2341 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2342 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2343 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2344 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2345 2346 #define S_FW_RDEV_WR_DATA_OVLY 2 2347 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2348 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2349 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2350 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2351 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2352 2353 #define S_FW_RDEV_WR_INI 1 2354 #define M_FW_RDEV_WR_INI 0x1 2355 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2356 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2357 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2358 2359 #define S_FW_RDEV_WR_TGT 0 2360 #define M_FW_RDEV_WR_TGT 0x1 2361 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2362 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2363 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2364 2365 struct fw_foiscsi_node_wr { 2366 __be32 op_to_immdlen; 2367 __be32 flowid_len16; 2368 __u64 cookie; 2369 __u8 subop; 2370 __u8 status; 2371 __u8 alias_len; 2372 __u8 iqn_len; 2373 __be32 node_flowid; 2374 __be16 nodeid; 2375 __be16 login_retry; 2376 __be16 retry_timeout; 2377 __be16 r3; 2378 __u8 iqn[224]; 2379 __u8 alias[224]; 2380 }; 2381 2382 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2383 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2384 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2385 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2386 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2387 2388 struct fw_foiscsi_ctrl_wr { 2389 __be32 op_compl; 2390 __be32 flowid_len16; 2391 __u64 cookie; 2392 __u8 subop; 2393 __u8 status; 2394 __u8 ctrl_state; 2395 __u8 io_state; 2396 __be32 node_id; 2397 __be32 ctrl_id; 2398 __be32 io_id; 2399 struct fw_foiscsi_sess_attr { 2400 __be32 sess_type_to_erl; 2401 __be16 max_conn; 2402 __be16 max_r2t; 2403 __be16 time2wait; 2404 __be16 time2retain; 2405 __be32 max_burst; 2406 __be32 first_burst; 2407 __be32 r1; 2408 } sess_attr; 2409 struct fw_foiscsi_conn_attr { 2410 __be32 hdigest_to_ddp_pgsz; 2411 __be32 max_rcv_dsl; 2412 __be32 ping_tmo; 2413 __be16 dst_port; 2414 __be16 src_port; 2415 union fw_foiscsi_conn_attr_addr { 2416 struct fw_foiscsi_conn_attr_ipv6 { 2417 __be64 dst_addr[2]; 2418 __be64 src_addr[2]; 2419 } ipv6_addr; 2420 struct fw_foiscsi_conn_attr_ipv4 { 2421 __be32 dst_addr; 2422 __be32 src_addr; 2423 } ipv4_addr; 2424 } u; 2425 } conn_attr; 2426 __u8 tgt_name_len; 2427 __u8 r3[7]; 2428 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2429 }; 2430 2431 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2432 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2433 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2434 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2435 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2436 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2437 2438 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2439 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2440 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2441 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2442 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2443 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2444 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2445 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2446 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2447 2448 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2449 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2450 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2451 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2452 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2453 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2454 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2455 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2456 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2457 2458 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2459 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2460 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2461 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2462 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2463 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2464 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2465 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2466 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2467 2468 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2469 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2470 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2471 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2472 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2473 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2474 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2475 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2476 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2477 2478 #define S_FW_FOISCSI_CTRL_WR_ERL 24 2479 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2480 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2481 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2482 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2483 2484 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2485 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2486 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2487 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2488 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2489 2490 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2491 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2492 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2493 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2494 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2495 2496 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2497 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2498 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2499 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2500 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2501 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2502 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2503 2504 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2505 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2506 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2507 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2508 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2509 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2510 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2511 2512 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2513 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2514 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2515 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2516 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2517 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2518 2519 #define S_FW_FOISCSI_CTRL_WR_IPV6 20 2520 #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 2521 #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 2522 #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 2523 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 2524 #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 2525 2526 struct fw_foiscsi_chap_wr { 2527 __be32 op_compl; 2528 __be32 flowid_len16; 2529 __u64 cookie; 2530 __u8 status; 2531 __u8 id_len; 2532 __u8 sec_len; 2533 __u8 node_type; 2534 __be16 node_id; 2535 __u8 r3[2]; 2536 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2537 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 2538 }; 2539 2540 /****************************************************************************** 2541 * C O i S C S I W O R K R E Q U E S T S 2542 ********************************************/ 2543 2544 enum fw_chnet_addr_type { 2545 FW_CHNET_ADDD_TYPE_NONE = 0, 2546 FW_CHNET_ADDR_TYPE_IPV4, 2547 FW_CHNET_ADDR_TYPE_IPV6, 2548 }; 2549 2550 struct fw_coiscsi_tgt_wr { 2551 __be32 op_compl; 2552 __be32 flowid_len16; 2553 __u64 cookie; 2554 __u8 subop; 2555 __u8 status; 2556 __be16 r4; 2557 __be32 flags; 2558 struct fw_coiscsi_tgt_conn_attr { 2559 __be32 in_tid; 2560 __be16 in_port; 2561 __u8 in_type; 2562 __u8 r6; 2563 union fw_coiscsi_tgt_conn_attr_addr { 2564 struct fw_coiscsi_tgt_conn_attr_in_addr { 2565 __be32 addr; 2566 __be32 r7; 2567 __be32 r8[2]; 2568 } in_addr; 2569 struct fw_coiscsi_tgt_conn_attr_in_addr6 { 2570 __be64 addr[2]; 2571 } in_addr6; 2572 } u; 2573 } conn_attr; 2574 }; 2575 2576 struct fw_coiscsi_tgt_conn_wr { 2577 __be32 op_compl; 2578 __be32 flowid_len16; 2579 __u64 cookie; 2580 __u8 subop; 2581 __u8 status; 2582 __be16 iq_id; 2583 __be32 in_stid; 2584 __be32 io_id; 2585 __be32 flags; 2586 struct fw_coiscsi_tgt_conn_tcp { 2587 __be16 in_sport; 2588 __be16 in_dport; 2589 __be32 r4; 2590 union fw_coiscsi_tgt_conn_tcp_addr { 2591 struct fw_coiscsi_tgt_conn_tcp_in_addr { 2592 __be32 saddr; 2593 __be32 daddr; 2594 } in_addr; 2595 struct fw_coiscsi_tgt_conn_tcp_in_addr6 { 2596 __be64 saddr[2]; 2597 __be64 daddr[2]; 2598 } in_addr6; 2599 } u; 2600 } conn_tcp; 2601 struct fw_coiscsi_tgt_conn_iscsi { 2602 __be32 hdigest_to_ddp_pgsz; 2603 __be32 tgt_id; 2604 __be16 max_r2t; 2605 __be16 max_rcv_dsl; 2606 __be32 max_burst; 2607 __be32 nxt_statsn; 2608 __be32 r6; 2609 } conn_iscsi; 2610 }; 2611 2612 struct fw_coiscsi_tgt_xmit_wr { 2613 __be32 op_to_immdlen; 2614 __be32 flowid_len16; 2615 __be64 cookie; 2616 __be16 iq_id; 2617 __be16 r4; 2618 __be32 datasn; 2619 __be32 t_xfer_len; 2620 __be32 flags; 2621 }; 2622 2623 #define S_FW_COiSCSI_TGT_XMIT_WR_DDGST 23 2624 #define M_FW_COiSCSI_TGT_XMIT_WR_DDGST 0x1 2625 #define V_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 2626 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDGST) 2627 #define G_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 2628 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDGST) & M_FW_COiSCSI_TGT_XMIT_WR_DDGST) 2629 #define F_FW_COiSCSI_TGT_XMIT_WR_DDGST V_FW_COiSCSI_TGT_XMIT_WR_DDGST(1U) 2630 2631 #define S_FW_COiSCSI_TGT_XMIT_WR_HDGST 22 2632 #define M_FW_COiSCSI_TGT_XMIT_WR_HDGST 0x1 2633 #define V_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 2634 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_HDGST) 2635 #define G_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 2636 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_HDGST) & M_FW_COiSCSI_TGT_XMIT_WR_HDGST) 2637 #define F_FW_COiSCSI_TGT_XMIT_WR_HDGST V_FW_COiSCSI_TGT_XMIT_WR_HDGST(1U) 2638 2639 #define S_FW_COiSCSI_TGT_XMIT_WR_DDP 20 2640 #define M_FW_COiSCSI_TGT_XMIT_WR_DDP 0x1 2641 #define V_FW_COiSCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDP) 2642 #define G_FW_COiSCSI_TGT_XMIT_WR_DDP(x) \ 2643 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDP) & M_FW_COiSCSI_TGT_XMIT_WR_DDP) 2644 #define F_FW_COiSCSI_TGT_XMIT_WR_DDP V_FW_COiSCSI_TGT_XMIT_WR_DDP(1U) 2645 2646 #define S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0 2647 #define M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0xff 2648 #define V_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2649 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 2650 #define G_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2651 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) & \ 2652 M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 2653 2654 struct fw_isns_wr { 2655 __be32 op_compl; 2656 __be32 flowid_len16; 2657 __u64 cookie; 2658 __u8 subop; 2659 __u8 status; 2660 __be16 iq_id; 2661 __be32 r4; 2662 struct fw_tcp_conn_attr { 2663 __be32 in_tid; 2664 __be16 in_port; 2665 __u8 in_type; 2666 __u8 r6; 2667 union fw_tcp_conn_attr_addr { 2668 struct fw_tcp_conn_attr_in_addr { 2669 __be32 addr; 2670 __be32 r7; 2671 __be32 r8[2]; 2672 } in_addr; 2673 struct fw_tcp_conn_attr_in_addr6 { 2674 __be64 addr[2]; 2675 } in_addr6; 2676 } u; 2677 } conn_attr; 2678 }; 2679 2680 struct fw_isns_xmit_wr { 2681 __be32 op_to_immdlen; 2682 __be32 flowid_len16; 2683 __be64 cookie; 2684 __be16 iq_id; 2685 __be16 r4; 2686 __be32 xfer_len; 2687 __be64 r5; 2688 }; 2689 2690 #define S_FW_ISNS_XMIT_WR_IMMDLEN 0 2691 #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff 2692 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) 2693 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ 2694 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN) 2695 2696 2697 /****************************************************************************** 2698 * F O F C O E W O R K R E Q U E S T s 2699 *******************************************/ 2700 2701 struct fw_fcoe_els_ct_wr { 2702 __be32 op_immdlen; 2703 __be32 flowid_len16; 2704 __be64 cookie; 2705 __be16 iqid; 2706 __u8 tmo_val; 2707 __u8 els_ct_type; 2708 __u8 ctl_pri; 2709 __u8 cp_en_class; 2710 __be16 xfer_cnt; 2711 __u8 fl_to_sp; 2712 __u8 l_id[3]; 2713 __u8 r5; 2714 __u8 r_id[3]; 2715 __be64 rsp_dmaaddr; 2716 __be32 rsp_dmalen; 2717 __be32 r6; 2718 }; 2719 2720 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2721 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2722 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2723 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2724 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2725 2726 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2727 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2728 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2729 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2730 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2731 2732 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2733 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2734 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2735 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2736 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2737 2738 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 2739 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2740 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2741 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2742 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2743 2744 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2745 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2746 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2747 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2748 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2749 2750 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 2751 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2752 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2753 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2754 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2755 2756 #define S_FW_FCOE_ELS_CT_WR_FL 2 2757 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 2758 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2759 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2760 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2761 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2762 2763 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 2764 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2765 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2766 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2767 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2768 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2769 2770 #define S_FW_FCOE_ELS_CT_WR_SP 0 2771 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 2772 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2773 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2774 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2775 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2776 2777 /****************************************************************************** 2778 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 2779 *****************************************************************************/ 2780 2781 struct fw_scsi_write_wr { 2782 __be32 op_immdlen; 2783 __be32 flowid_len16; 2784 __be64 cookie; 2785 __be16 iqid; 2786 __u8 tmo_val; 2787 __u8 use_xfer_cnt; 2788 union fw_scsi_write_priv { 2789 struct fcoe_write_priv { 2790 __u8 ctl_pri; 2791 __u8 cp_en_class; 2792 __u8 r3_lo[2]; 2793 } fcoe; 2794 struct iscsi_write_priv { 2795 __u8 r3[4]; 2796 } iscsi; 2797 } u; 2798 __be32 xfer_cnt; 2799 __be32 ini_xfer_cnt; 2800 __be64 rsp_dmaaddr; 2801 __be32 rsp_dmalen; 2802 __be32 r4; 2803 }; 2804 2805 #define S_FW_SCSI_WRITE_WR_OPCODE 24 2806 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2807 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2808 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2809 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2810 2811 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2812 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2813 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2814 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2815 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2816 2817 #define S_FW_SCSI_WRITE_WR_FLOWID 8 2818 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2819 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2820 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2821 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2822 2823 #define S_FW_SCSI_WRITE_WR_LEN16 0 2824 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 2825 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2826 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 2827 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 2828 2829 #define S_FW_SCSI_WRITE_WR_CP_EN 6 2830 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 2831 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 2832 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 2833 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 2834 2835 #define S_FW_SCSI_WRITE_WR_CLASS 4 2836 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 2837 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 2838 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 2839 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 2840 2841 struct fw_scsi_read_wr { 2842 __be32 op_immdlen; 2843 __be32 flowid_len16; 2844 __be64 cookie; 2845 __be16 iqid; 2846 __u8 tmo_val; 2847 __u8 use_xfer_cnt; 2848 union fw_scsi_read_priv { 2849 struct fcoe_read_priv { 2850 __u8 ctl_pri; 2851 __u8 cp_en_class; 2852 __u8 r3_lo[2]; 2853 } fcoe; 2854 struct iscsi_read_priv { 2855 __u8 r3[4]; 2856 } iscsi; 2857 } u; 2858 __be32 xfer_cnt; 2859 __be32 ini_xfer_cnt; 2860 __be64 rsp_dmaaddr; 2861 __be32 rsp_dmalen; 2862 __be32 r4; 2863 }; 2864 2865 #define S_FW_SCSI_READ_WR_OPCODE 24 2866 #define M_FW_SCSI_READ_WR_OPCODE 0xff 2867 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 2868 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 2869 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 2870 2871 #define S_FW_SCSI_READ_WR_IMMDLEN 0 2872 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 2873 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 2874 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 2875 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 2876 2877 #define S_FW_SCSI_READ_WR_FLOWID 8 2878 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 2879 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 2880 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 2881 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 2882 2883 #define S_FW_SCSI_READ_WR_LEN16 0 2884 #define M_FW_SCSI_READ_WR_LEN16 0xff 2885 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 2886 #define G_FW_SCSI_READ_WR_LEN16(x) \ 2887 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 2888 2889 #define S_FW_SCSI_READ_WR_CP_EN 6 2890 #define M_FW_SCSI_READ_WR_CP_EN 0x3 2891 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 2892 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 2893 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 2894 2895 #define S_FW_SCSI_READ_WR_CLASS 4 2896 #define M_FW_SCSI_READ_WR_CLASS 0x3 2897 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 2898 #define G_FW_SCSI_READ_WR_CLASS(x) \ 2899 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 2900 2901 struct fw_scsi_cmd_wr { 2902 __be32 op_immdlen; 2903 __be32 flowid_len16; 2904 __be64 cookie; 2905 __be16 iqid; 2906 __u8 tmo_val; 2907 __u8 r3; 2908 union fw_scsi_cmd_priv { 2909 struct fcoe_cmd_priv { 2910 __u8 ctl_pri; 2911 __u8 cp_en_class; 2912 __u8 r4_lo[2]; 2913 } fcoe; 2914 struct iscsi_cmd_priv { 2915 __u8 r4[4]; 2916 } iscsi; 2917 } u; 2918 __u8 r5[8]; 2919 __be64 rsp_dmaaddr; 2920 __be32 rsp_dmalen; 2921 __be32 r6; 2922 }; 2923 2924 #define S_FW_SCSI_CMD_WR_OPCODE 24 2925 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 2926 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 2927 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 2928 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 2929 2930 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 2931 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 2932 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 2933 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 2934 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 2935 2936 #define S_FW_SCSI_CMD_WR_FLOWID 8 2937 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 2938 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 2939 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 2940 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 2941 2942 #define S_FW_SCSI_CMD_WR_LEN16 0 2943 #define M_FW_SCSI_CMD_WR_LEN16 0xff 2944 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 2945 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 2946 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 2947 2948 #define S_FW_SCSI_CMD_WR_CP_EN 6 2949 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 2950 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 2951 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 2952 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 2953 2954 #define S_FW_SCSI_CMD_WR_CLASS 4 2955 #define M_FW_SCSI_CMD_WR_CLASS 0x3 2956 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 2957 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 2958 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 2959 2960 struct fw_scsi_abrt_cls_wr { 2961 __be32 op_immdlen; 2962 __be32 flowid_len16; 2963 __be64 cookie; 2964 __be16 iqid; 2965 __u8 tmo_val; 2966 __u8 sub_opcode_to_chk_all_io; 2967 __u8 r3[4]; 2968 __be64 t_cookie; 2969 }; 2970 2971 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 2972 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 2973 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 2974 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 2975 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 2976 2977 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 2978 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 2979 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2980 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2981 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2982 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2983 2984 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 2985 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 2986 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 2987 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 2988 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 2989 2990 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 2991 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 2992 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 2993 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 2994 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 2995 2996 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 2997 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 2998 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2999 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3000 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3001 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 3002 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3003 3004 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 3005 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 3006 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 3007 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 3008 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 3009 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 3010 3011 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 3012 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 3013 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3014 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3015 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3016 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 3017 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3018 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 3019 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 3020 3021 struct fw_scsi_tgt_acc_wr { 3022 __be32 op_immdlen; 3023 __be32 flowid_len16; 3024 __be64 cookie; 3025 __be16 iqid; 3026 __u8 r3; 3027 __u8 use_burst_len; 3028 union fw_scsi_tgt_acc_priv { 3029 struct fcoe_tgt_acc_priv { 3030 __u8 ctl_pri; 3031 __u8 cp_en_class; 3032 __u8 r4_lo[2]; 3033 } fcoe; 3034 struct iscsi_tgt_acc_priv { 3035 __u8 r4[4]; 3036 } iscsi; 3037 } u; 3038 __be32 burst_len; 3039 __be32 rel_off; 3040 __be64 r5; 3041 __be32 r6; 3042 __be32 tot_xfer_len; 3043 }; 3044 3045 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 3046 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 3047 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 3048 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 3049 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 3050 3051 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 3052 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 3053 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3054 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 3055 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3056 3057 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 3058 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 3059 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 3060 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 3061 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 3062 3063 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 3064 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 3065 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 3066 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 3067 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 3068 3069 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 3070 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 3071 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 3072 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 3073 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 3074 3075 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 3076 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 3077 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 3078 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 3079 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 3080 3081 struct fw_scsi_tgt_xmit_wr { 3082 __be32 op_immdlen; 3083 __be32 flowid_len16; 3084 __be64 cookie; 3085 __be16 iqid; 3086 __u8 auto_rsp; 3087 __u8 use_xfer_cnt; 3088 union fw_scsi_tgt_xmit_priv { 3089 struct fcoe_tgt_xmit_priv { 3090 __u8 ctl_pri; 3091 __u8 cp_en_class; 3092 __u8 r3_lo[2]; 3093 } fcoe; 3094 struct iscsi_tgt_xmit_priv { 3095 __u8 r3[4]; 3096 } iscsi; 3097 } u; 3098 __be32 xfer_cnt; 3099 __be32 r4; 3100 __be64 r5; 3101 __be32 r6; 3102 __be32 tot_xfer_len; 3103 }; 3104 3105 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 3106 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 3107 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 3108 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 3109 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 3110 3111 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 3112 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 3113 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3114 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3115 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3116 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3117 3118 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 3119 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 3120 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 3121 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 3122 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 3123 3124 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 3125 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 3126 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 3127 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 3128 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 3129 3130 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 3131 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 3132 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 3133 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 3134 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 3135 3136 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 3137 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 3138 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 3139 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 3140 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 3141 3142 struct fw_scsi_tgt_rsp_wr { 3143 __be32 op_immdlen; 3144 __be32 flowid_len16; 3145 __be64 cookie; 3146 __be16 iqid; 3147 __u8 r3[2]; 3148 union fw_scsi_tgt_rsp_priv { 3149 struct fcoe_tgt_rsp_priv { 3150 __u8 ctl_pri; 3151 __u8 cp_en_class; 3152 __u8 r4_lo[2]; 3153 } fcoe; 3154 struct iscsi_tgt_rsp_priv { 3155 __u8 r4[4]; 3156 } iscsi; 3157 } u; 3158 __u8 r5[8]; 3159 }; 3160 3161 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 3162 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 3163 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 3164 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 3165 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 3166 3167 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 3168 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 3169 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3170 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 3171 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3172 3173 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 3174 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 3175 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 3176 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 3177 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 3178 3179 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 3180 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 3181 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 3182 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 3183 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 3184 3185 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 3186 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 3187 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 3188 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 3189 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 3190 3191 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 3192 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 3193 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 3194 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 3195 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 3196 3197 struct fw_pofcoe_tcb_wr { 3198 __be32 op_compl; 3199 __be32 equiq_to_len16; 3200 __be32 r4; 3201 __be32 xfer_len; 3202 __be32 tid_to_port; 3203 __be16 x_id; 3204 __be16 vlan_id; 3205 __be64 cookie; 3206 __be32 s_id; 3207 __be32 d_id; 3208 __be32 tag; 3209 __be16 r6; 3210 __be16 iqid; 3211 }; 3212 3213 #define S_FW_POFCOE_TCB_WR_TID 12 3214 #define M_FW_POFCOE_TCB_WR_TID 0xfffff 3215 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 3216 #define G_FW_POFCOE_TCB_WR_TID(x) \ 3217 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 3218 3219 #define S_FW_POFCOE_TCB_WR_ALLOC 4 3220 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 3221 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 3222 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 3223 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 3224 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 3225 3226 #define S_FW_POFCOE_TCB_WR_FREE 3 3227 #define M_FW_POFCOE_TCB_WR_FREE 0x1 3228 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 3229 #define G_FW_POFCOE_TCB_WR_FREE(x) \ 3230 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 3231 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 3232 3233 #define S_FW_POFCOE_TCB_WR_PORT 0 3234 #define M_FW_POFCOE_TCB_WR_PORT 0x7 3235 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 3236 #define G_FW_POFCOE_TCB_WR_PORT(x) \ 3237 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 3238 3239 struct fw_pofcoe_ulptx_wr { 3240 __be32 op_pkd; 3241 __be32 equiq_to_len16; 3242 __u64 cookie; 3243 }; 3244 3245 /******************************************************************* 3246 * T10 DIF related definition 3247 *******************************************************************/ 3248 struct fw_tx_pi_header { 3249 __be16 op_to_inline; 3250 __u8 pi_interval_tag_type; 3251 __u8 num_pi; 3252 __be32 pi_start4_pi_end4; 3253 __u8 tag_gen_enabled_pkd; 3254 __u8 num_pi_dsg; 3255 __be16 app_tag; 3256 __be32 ref_tag; 3257 }; 3258 3259 #define S_FW_TX_PI_HEADER_OP 8 3260 #define M_FW_TX_PI_HEADER_OP 0xff 3261 #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) 3262 #define G_FW_TX_PI_HEADER_OP(x) \ 3263 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) 3264 3265 #define S_FW_TX_PI_HEADER_ULPTXMORE 7 3266 #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 3267 #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) 3268 #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ 3269 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) 3270 #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) 3271 3272 #define S_FW_TX_PI_HEADER_PI_CONTROL 4 3273 #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 3274 #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) 3275 #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ 3276 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) 3277 3278 #define S_FW_TX_PI_HEADER_GUARD_TYPE 2 3279 #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 3280 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) 3281 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ 3282 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) 3283 #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) 3284 3285 #define S_FW_TX_PI_HEADER_VALIDATE 1 3286 #define M_FW_TX_PI_HEADER_VALIDATE 0x1 3287 #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) 3288 #define G_FW_TX_PI_HEADER_VALIDATE(x) \ 3289 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) 3290 #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) 3291 3292 #define S_FW_TX_PI_HEADER_INLINE 0 3293 #define M_FW_TX_PI_HEADER_INLINE 0x1 3294 #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) 3295 #define G_FW_TX_PI_HEADER_INLINE(x) \ 3296 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) 3297 #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) 3298 3299 #define S_FW_TX_PI_HEADER_PI_INTERVAL 7 3300 #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 3301 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3302 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) 3303 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3304 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) 3305 #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) 3306 3307 #define S_FW_TX_PI_HEADER_TAG_TYPE 5 3308 #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 3309 #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) 3310 #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ 3311 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) 3312 3313 #define S_FW_TX_PI_HEADER_PI_START4 22 3314 #define M_FW_TX_PI_HEADER_PI_START4 0x3ff 3315 #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) 3316 #define G_FW_TX_PI_HEADER_PI_START4(x) \ 3317 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) 3318 3319 #define S_FW_TX_PI_HEADER_PI_END4 0 3320 #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff 3321 #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) 3322 #define G_FW_TX_PI_HEADER_PI_END4(x) \ 3323 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) 3324 3325 #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 3326 #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 3327 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3328 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3329 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3330 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ 3331 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3332 3333 enum fw_pi_error_type { 3334 FW_PI_ERROR_GUARD_CHECK_FAILED = 0, 3335 }; 3336 3337 struct fw_pi_error { 3338 __be32 err_type_pkd; 3339 __be32 flowid_len16; 3340 __be16 r2; 3341 __be16 app_tag; 3342 __be32 ref_tag; 3343 __be32 pisc[4]; 3344 }; 3345 3346 #define S_FW_PI_ERROR_ERR_TYPE 24 3347 #define M_FW_PI_ERROR_ERR_TYPE 0xff 3348 #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) 3349 #define G_FW_PI_ERROR_ERR_TYPE(x) \ 3350 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) 3351 3352 3353 struct fw_sec_lookaside_lpbk_wr { 3354 __be32 op_to_cctx_size; 3355 __be32 len16_pkd; 3356 __be32 session_id; 3357 __be32 rx_chid_to_rx_q_id; 3358 __be32 key_addr; 3359 __be32 pld_size_hash_size; 3360 __be64 cookie; 3361 }; 3362 3363 #define S_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE 24 3364 #define M_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE 0xff 3365 #define V_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE(x) \ 3366 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE) 3367 #define G_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE(x) \ 3368 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE) & \ 3369 M_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE) 3370 3371 #define S_FW_SEC_LOOKASIDE_LPBK_WR_COMPL 23 3372 #define M_FW_SEC_LOOKASIDE_LPBK_WR_COMPL 0x1 3373 #define V_FW_SEC_LOOKASIDE_LPBK_WR_COMPL(x) \ 3374 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_COMPL) 3375 #define G_FW_SEC_LOOKASIDE_LPBK_WR_COMPL(x) \ 3376 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_COMPL) & \ 3377 M_FW_SEC_LOOKASIDE_LPBK_WR_COMPL) 3378 #define F_FW_SEC_LOOKASIDE_LPBK_WR_COMPL V_FW_SEC_LOOKASIDE_LPBK_WR_COMPL(1U) 3379 3380 #define S_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN 15 3381 #define M_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN 0xff 3382 #define V_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN(x) \ 3383 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN) 3384 #define G_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN(x) \ 3385 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN) & \ 3386 M_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN) 3387 3388 #define S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC 5 3389 #define M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC 0x3 3390 #define V_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC(x) \ 3391 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC) 3392 #define G_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC(x) \ 3393 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC) & \ 3394 M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC) 3395 3396 #define S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE 0 3397 #define M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE 0x1f 3398 #define V_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE(x) \ 3399 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE) 3400 #define G_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE(x) \ 3401 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE) & \ 3402 M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE) 3403 3404 #define S_FW_SEC_LOOKASIDE_LPBK_WR_LEN16 0 3405 #define M_FW_SEC_LOOKASIDE_LPBK_WR_LEN16 0xff 3406 #define V_FW_SEC_LOOKASIDE_LPBK_WR_LEN16(x) \ 3407 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_LEN16) 3408 #define G_FW_SEC_LOOKASIDE_LPBK_WR_LEN16(x) \ 3409 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_LEN16) & \ 3410 M_FW_SEC_LOOKASIDE_LPBK_WR_LEN16) 3411 3412 #define S_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID 29 3413 #define M_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID 0x3 3414 #define V_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID(x) \ 3415 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID) 3416 #define G_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID(x) \ 3417 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID) & \ 3418 M_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID) 3419 3420 #define S_FW_SEC_LOOKASIDE_LPBK_WR_LCB 27 3421 #define M_FW_SEC_LOOKASIDE_LPBK_WR_LCB 0x3 3422 #define V_FW_SEC_LOOKASIDE_LPBK_WR_LCB(x) \ 3423 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_LCB) 3424 #define G_FW_SEC_LOOKASIDE_LPBK_WR_LCB(x) \ 3425 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_LCB) & M_FW_SEC_LOOKASIDE_LPBK_WR_LCB) 3426 3427 #define S_FW_SEC_LOOKASIDE_LPBK_WR_PHASH 25 3428 #define M_FW_SEC_LOOKASIDE_LPBK_WR_PHASH 0x3 3429 #define V_FW_SEC_LOOKASIDE_LPBK_WR_PHASH(x) \ 3430 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_PHASH) 3431 #define G_FW_SEC_LOOKASIDE_LPBK_WR_PHASH(x) \ 3432 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_PHASH) & \ 3433 M_FW_SEC_LOOKASIDE_LPBK_WR_PHASH) 3434 3435 #define S_FW_SEC_LOOKASIDE_LPBK_WR_IV 23 3436 #define M_FW_SEC_LOOKASIDE_LPBK_WR_IV 0x3 3437 #define V_FW_SEC_LOOKASIDE_LPBK_WR_IV(x) \ 3438 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_IV) 3439 #define G_FW_SEC_LOOKASIDE_LPBK_WR_IV(x) \ 3440 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_IV) & M_FW_SEC_LOOKASIDE_LPBK_WR_IV) 3441 3442 #define S_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH 10 3443 #define M_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH 0x3 3444 #define V_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH(x) \ 3445 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH) 3446 #define G_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH(x) \ 3447 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH) & \ 3448 M_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH) 3449 3450 #define S_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID 0 3451 #define M_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID 0x3ff 3452 #define V_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID(x) \ 3453 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID) 3454 #define G_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID(x) \ 3455 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID) & \ 3456 M_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID) 3457 3458 #define S_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE 24 3459 #define M_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE 0xff 3460 #define V_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE(x) \ 3461 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE) 3462 #define G_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE(x) \ 3463 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE) & \ 3464 M_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE) 3465 3466 #define S_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE 17 3467 #define M_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE 0x7f 3468 #define V_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE(x) \ 3469 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE) 3470 #define G_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE(x) \ 3471 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE) & \ 3472 M_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE) 3473 3474 /****************************************************************************** 3475 * C O M M A N D s 3476 *********************/ 3477 3478 /* 3479 * The maximum length of time, in miliseconds, that we expect any firmware 3480 * command to take to execute and return a reply to the host. The RESET 3481 * and INITIALIZE commands can take a fair amount of time to execute but 3482 * most execute in far less time than this maximum. This constant is used 3483 * by host software to determine how long to wait for a firmware command 3484 * reply before declaring the firmware as dead/unreachable ... 3485 */ 3486 #define FW_CMD_MAX_TIMEOUT 10000 3487 3488 /* 3489 * If a host driver does a HELLO and discovers that there's already a MASTER 3490 * selected, we may have to wait for that MASTER to finish issuing RESET, 3491 * configuration and INITIALIZE commands. Also, there's a possibility that 3492 * our own HELLO may get lost if it happens right as the MASTER is issuign a 3493 * RESET command, so we need to be willing to make a few retries of our HELLO. 3494 */ 3495 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 3496 #define FW_CMD_HELLO_RETRIES 3 3497 3498 enum fw_cmd_opcodes { 3499 FW_LDST_CMD = 0x01, 3500 FW_RESET_CMD = 0x03, 3501 FW_HELLO_CMD = 0x04, 3502 FW_BYE_CMD = 0x05, 3503 FW_INITIALIZE_CMD = 0x06, 3504 FW_CAPS_CONFIG_CMD = 0x07, 3505 FW_PARAMS_CMD = 0x08, 3506 FW_PFVF_CMD = 0x09, 3507 FW_IQ_CMD = 0x10, 3508 FW_EQ_MNGT_CMD = 0x11, 3509 FW_EQ_ETH_CMD = 0x12, 3510 FW_EQ_CTRL_CMD = 0x13, 3511 FW_EQ_OFLD_CMD = 0x21, 3512 FW_VI_CMD = 0x14, 3513 FW_VI_MAC_CMD = 0x15, 3514 FW_VI_RXMODE_CMD = 0x16, 3515 FW_VI_ENABLE_CMD = 0x17, 3516 FW_VI_STATS_CMD = 0x1a, 3517 FW_ACL_MAC_CMD = 0x18, 3518 FW_ACL_VLAN_CMD = 0x19, 3519 FW_PORT_CMD = 0x1b, 3520 FW_PORT_STATS_CMD = 0x1c, 3521 FW_PORT_LB_STATS_CMD = 0x1d, 3522 FW_PORT_TRACE_CMD = 0x1e, 3523 FW_PORT_TRACE_MMAP_CMD = 0x1f, 3524 FW_RSS_IND_TBL_CMD = 0x20, 3525 FW_RSS_GLB_CONFIG_CMD = 0x22, 3526 FW_RSS_VI_CONFIG_CMD = 0x23, 3527 FW_SCHED_CMD = 0x24, 3528 FW_DEVLOG_CMD = 0x25, 3529 FW_WATCHDOG_CMD = 0x27, 3530 FW_CLIP_CMD = 0x28, 3531 FW_CHNET_IFACE_CMD = 0x26, 3532 FW_FCOE_RES_INFO_CMD = 0x31, 3533 FW_FCOE_LINK_CMD = 0x32, 3534 FW_FCOE_VNP_CMD = 0x33, 3535 FW_FCOE_SPARAMS_CMD = 0x35, 3536 FW_FCOE_STATS_CMD = 0x37, 3537 FW_FCOE_FCF_CMD = 0x38, 3538 FW_PTP_CMD = 0x39, 3539 FW_DCB_IEEE_CMD = 0x3a, 3540 FW_LASTC2E_CMD = 0x40, 3541 FW_ERROR_CMD = 0x80, 3542 FW_DEBUG_CMD = 0x81, 3543 }; 3544 3545 enum fw_cmd_cap { 3546 FW_CMD_CAP_PF = 0x01, 3547 FW_CMD_CAP_DMAQ = 0x02, 3548 FW_CMD_CAP_PORT = 0x04, 3549 FW_CMD_CAP_PORTPROMISC = 0x08, 3550 FW_CMD_CAP_PORTSTATS = 0x10, 3551 FW_CMD_CAP_VF = 0x80, 3552 }; 3553 3554 /* 3555 * Generic command header flit0 3556 */ 3557 struct fw_cmd_hdr { 3558 __be32 hi; 3559 __be32 lo; 3560 }; 3561 3562 #define S_FW_CMD_OP 24 3563 #define M_FW_CMD_OP 0xff 3564 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 3565 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 3566 3567 #define S_FW_CMD_REQUEST 23 3568 #define M_FW_CMD_REQUEST 0x1 3569 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 3570 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 3571 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 3572 3573 #define S_FW_CMD_READ 22 3574 #define M_FW_CMD_READ 0x1 3575 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 3576 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 3577 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 3578 3579 #define S_FW_CMD_WRITE 21 3580 #define M_FW_CMD_WRITE 0x1 3581 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 3582 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 3583 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 3584 3585 #define S_FW_CMD_EXEC 20 3586 #define M_FW_CMD_EXEC 0x1 3587 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 3588 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 3589 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 3590 3591 #define S_FW_CMD_RAMASK 20 3592 #define M_FW_CMD_RAMASK 0xf 3593 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 3594 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 3595 3596 #define S_FW_CMD_RETVAL 8 3597 #define M_FW_CMD_RETVAL 0xff 3598 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 3599 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 3600 3601 #define S_FW_CMD_LEN16 0 3602 #define M_FW_CMD_LEN16 0xff 3603 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 3604 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 3605 3606 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 3607 3608 /* 3609 * address spaces 3610 */ 3611 enum fw_ldst_addrspc { 3612 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 3613 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 3614 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 3615 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 3616 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 3617 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 3618 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 3619 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 3620 FW_LDST_ADDRSPC_MDIO = 0x0018, 3621 FW_LDST_ADDRSPC_MPS = 0x0020, 3622 FW_LDST_ADDRSPC_FUNC = 0x0028, 3623 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 3624 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 3625 FW_LDST_ADDRSPC_LE = 0x0030, 3626 FW_LDST_ADDRSPC_I2C = 0x0038, 3627 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 3628 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 3629 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 3630 FW_LDST_ADDRSPC_CIM_Q = 0x0048, 3631 }; 3632 3633 /* 3634 * MDIO VSC8634 register access control field 3635 */ 3636 enum fw_ldst_mdio_vsc8634_aid { 3637 FW_LDST_MDIO_VS_STANDARD, 3638 FW_LDST_MDIO_VS_EXTENDED, 3639 FW_LDST_MDIO_VS_GPIO 3640 }; 3641 3642 enum fw_ldst_mps_fid { 3643 FW_LDST_MPS_ATRB, 3644 FW_LDST_MPS_RPLC 3645 }; 3646 3647 enum fw_ldst_func_access_ctl { 3648 FW_LDST_FUNC_ACC_CTL_VIID, 3649 FW_LDST_FUNC_ACC_CTL_FID 3650 }; 3651 3652 enum fw_ldst_func_mod_index { 3653 FW_LDST_FUNC_MPS 3654 }; 3655 3656 struct fw_ldst_cmd { 3657 __be32 op_to_addrspace; 3658 __be32 cycles_to_len16; 3659 union fw_ldst { 3660 struct fw_ldst_addrval { 3661 __be32 addr; 3662 __be32 val; 3663 } addrval; 3664 struct fw_ldst_idctxt { 3665 __be32 physid; 3666 __be32 msg_ctxtflush; 3667 __be32 ctxt_data7; 3668 __be32 ctxt_data6; 3669 __be32 ctxt_data5; 3670 __be32 ctxt_data4; 3671 __be32 ctxt_data3; 3672 __be32 ctxt_data2; 3673 __be32 ctxt_data1; 3674 __be32 ctxt_data0; 3675 } idctxt; 3676 struct fw_ldst_mdio { 3677 __be16 paddr_mmd; 3678 __be16 raddr; 3679 __be16 vctl; 3680 __be16 rval; 3681 } mdio; 3682 struct fw_ldst_cim_rq { 3683 __u8 req_first64[8]; 3684 __u8 req_second64[8]; 3685 __u8 resp_first64[8]; 3686 __u8 resp_second64[8]; 3687 __be32 r3[2]; 3688 } cim_rq; 3689 union fw_ldst_mps { 3690 struct fw_ldst_mps_rplc { 3691 __be16 fid_idx; 3692 __be16 rplcpf_pkd; 3693 __be32 rplc255_224; 3694 __be32 rplc223_192; 3695 __be32 rplc191_160; 3696 __be32 rplc159_128; 3697 __be32 rplc127_96; 3698 __be32 rplc95_64; 3699 __be32 rplc63_32; 3700 __be32 rplc31_0; 3701 } rplc; 3702 struct fw_ldst_mps_atrb { 3703 __be16 fid_mpsid; 3704 __be16 r2[3]; 3705 __be32 r3[2]; 3706 __be32 r4; 3707 __be32 atrb; 3708 __be16 vlan[16]; 3709 } atrb; 3710 } mps; 3711 struct fw_ldst_func { 3712 __u8 access_ctl; 3713 __u8 mod_index; 3714 __be16 ctl_id; 3715 __be32 offset; 3716 __be64 data0; 3717 __be64 data1; 3718 } func; 3719 struct fw_ldst_pcie { 3720 __u8 ctrl_to_fn; 3721 __u8 bnum; 3722 __u8 r; 3723 __u8 ext_r; 3724 __u8 select_naccess; 3725 __u8 pcie_fn; 3726 __be16 nset_pkd; 3727 __be32 data[12]; 3728 } pcie; 3729 struct fw_ldst_i2c_deprecated { 3730 __u8 pid_pkd; 3731 __u8 base; 3732 __u8 boffset; 3733 __u8 data; 3734 __be32 r9; 3735 } i2c_deprecated; 3736 struct fw_ldst_i2c { 3737 __u8 pid; 3738 __u8 did; 3739 __u8 boffset; 3740 __u8 blen; 3741 __be32 r9; 3742 __u8 data[48]; 3743 } i2c; 3744 struct fw_ldst_le { 3745 __be32 index; 3746 __be32 r9; 3747 __u8 val[33]; 3748 __u8 r11[7]; 3749 } le; 3750 } u; 3751 }; 3752 3753 #define S_FW_LDST_CMD_ADDRSPACE 0 3754 #define M_FW_LDST_CMD_ADDRSPACE 0xff 3755 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 3756 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 3757 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 3758 3759 #define S_FW_LDST_CMD_CYCLES 16 3760 #define M_FW_LDST_CMD_CYCLES 0xffff 3761 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 3762 #define G_FW_LDST_CMD_CYCLES(x) \ 3763 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 3764 3765 #define S_FW_LDST_CMD_MSG 31 3766 #define M_FW_LDST_CMD_MSG 0x1 3767 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 3768 #define G_FW_LDST_CMD_MSG(x) \ 3769 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 3770 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 3771 3772 #define S_FW_LDST_CMD_CTXTFLUSH 30 3773 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 3774 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 3775 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 3776 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 3777 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 3778 3779 #define S_FW_LDST_CMD_PADDR 8 3780 #define M_FW_LDST_CMD_PADDR 0x1f 3781 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 3782 #define G_FW_LDST_CMD_PADDR(x) \ 3783 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 3784 3785 #define S_FW_LDST_CMD_MMD 0 3786 #define M_FW_LDST_CMD_MMD 0x1f 3787 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 3788 #define G_FW_LDST_CMD_MMD(x) \ 3789 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 3790 3791 #define S_FW_LDST_CMD_FID 15 3792 #define M_FW_LDST_CMD_FID 0x1 3793 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 3794 #define G_FW_LDST_CMD_FID(x) \ 3795 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 3796 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 3797 3798 #define S_FW_LDST_CMD_IDX 0 3799 #define M_FW_LDST_CMD_IDX 0x7fff 3800 #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) 3801 #define G_FW_LDST_CMD_IDX(x) \ 3802 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) 3803 3804 #define S_FW_LDST_CMD_RPLCPF 0 3805 #define M_FW_LDST_CMD_RPLCPF 0xff 3806 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 3807 #define G_FW_LDST_CMD_RPLCPF(x) \ 3808 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 3809 3810 #define S_FW_LDST_CMD_MPSID 0 3811 #define M_FW_LDST_CMD_MPSID 0x7fff 3812 #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) 3813 #define G_FW_LDST_CMD_MPSID(x) \ 3814 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) 3815 3816 #define S_FW_LDST_CMD_CTRL 7 3817 #define M_FW_LDST_CMD_CTRL 0x1 3818 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 3819 #define G_FW_LDST_CMD_CTRL(x) \ 3820 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 3821 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 3822 3823 #define S_FW_LDST_CMD_LC 4 3824 #define M_FW_LDST_CMD_LC 0x1 3825 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 3826 #define G_FW_LDST_CMD_LC(x) \ 3827 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 3828 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 3829 3830 #define S_FW_LDST_CMD_AI 3 3831 #define M_FW_LDST_CMD_AI 0x1 3832 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 3833 #define G_FW_LDST_CMD_AI(x) \ 3834 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 3835 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 3836 3837 #define S_FW_LDST_CMD_FN 0 3838 #define M_FW_LDST_CMD_FN 0x7 3839 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 3840 #define G_FW_LDST_CMD_FN(x) \ 3841 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 3842 3843 #define S_FW_LDST_CMD_SELECT 4 3844 #define M_FW_LDST_CMD_SELECT 0xf 3845 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 3846 #define G_FW_LDST_CMD_SELECT(x) \ 3847 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 3848 3849 #define S_FW_LDST_CMD_NACCESS 0 3850 #define M_FW_LDST_CMD_NACCESS 0xf 3851 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 3852 #define G_FW_LDST_CMD_NACCESS(x) \ 3853 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 3854 3855 #define S_FW_LDST_CMD_NSET 14 3856 #define M_FW_LDST_CMD_NSET 0x3 3857 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 3858 #define G_FW_LDST_CMD_NSET(x) \ 3859 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 3860 3861 #define S_FW_LDST_CMD_PID 6 3862 #define M_FW_LDST_CMD_PID 0x3 3863 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 3864 #define G_FW_LDST_CMD_PID(x) \ 3865 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 3866 3867 struct fw_reset_cmd { 3868 __be32 op_to_write; 3869 __be32 retval_len16; 3870 __be32 val; 3871 __be32 halt_pkd; 3872 }; 3873 3874 #define S_FW_RESET_CMD_HALT 31 3875 #define M_FW_RESET_CMD_HALT 0x1 3876 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 3877 #define G_FW_RESET_CMD_HALT(x) \ 3878 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 3879 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 3880 3881 enum { 3882 FW_HELLO_CMD_STAGE_OS = 0, 3883 FW_HELLO_CMD_STAGE_PREOS0 = 1, 3884 FW_HELLO_CMD_STAGE_PREOS1 = 2, 3885 FW_HELLO_CMD_STAGE_POSTOS = 3, 3886 }; 3887 3888 struct fw_hello_cmd { 3889 __be32 op_to_write; 3890 __be32 retval_len16; 3891 __be32 err_to_clearinit; 3892 __be32 fwrev; 3893 }; 3894 3895 #define S_FW_HELLO_CMD_ERR 31 3896 #define M_FW_HELLO_CMD_ERR 0x1 3897 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 3898 #define G_FW_HELLO_CMD_ERR(x) \ 3899 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 3900 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 3901 3902 #define S_FW_HELLO_CMD_INIT 30 3903 #define M_FW_HELLO_CMD_INIT 0x1 3904 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 3905 #define G_FW_HELLO_CMD_INIT(x) \ 3906 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 3907 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 3908 3909 #define S_FW_HELLO_CMD_MASTERDIS 29 3910 #define M_FW_HELLO_CMD_MASTERDIS 0x1 3911 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 3912 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 3913 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 3914 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 3915 3916 #define S_FW_HELLO_CMD_MASTERFORCE 28 3917 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 3918 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 3919 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 3920 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 3921 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 3922 3923 #define S_FW_HELLO_CMD_MBMASTER 24 3924 #define M_FW_HELLO_CMD_MBMASTER 0xf 3925 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 3926 #define G_FW_HELLO_CMD_MBMASTER(x) \ 3927 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 3928 3929 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 3930 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 3931 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 3932 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 3933 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 3934 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 3935 3936 #define S_FW_HELLO_CMD_MBASYNCNOT 20 3937 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 3938 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 3939 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 3940 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 3941 3942 #define S_FW_HELLO_CMD_STAGE 17 3943 #define M_FW_HELLO_CMD_STAGE 0x7 3944 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 3945 #define G_FW_HELLO_CMD_STAGE(x) \ 3946 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 3947 3948 #define S_FW_HELLO_CMD_CLEARINIT 16 3949 #define M_FW_HELLO_CMD_CLEARINIT 0x1 3950 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 3951 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 3952 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 3953 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 3954 3955 struct fw_bye_cmd { 3956 __be32 op_to_write; 3957 __be32 retval_len16; 3958 __be64 r3; 3959 }; 3960 3961 struct fw_initialize_cmd { 3962 __be32 op_to_write; 3963 __be32 retval_len16; 3964 __be64 r3; 3965 }; 3966 3967 enum fw_caps_config_hm { 3968 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 3969 FW_CAPS_CONFIG_HM_PL = 0x00000002, 3970 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 3971 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 3972 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 3973 FW_CAPS_CONFIG_HM_TP = 0x00000020, 3974 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 3975 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 3976 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 3977 FW_CAPS_CONFIG_HM_MC = 0x00000200, 3978 FW_CAPS_CONFIG_HM_LE = 0x00000400, 3979 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 3980 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 3981 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 3982 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 3983 FW_CAPS_CONFIG_HM_MI = 0x00008000, 3984 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 3985 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 3986 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 3987 FW_CAPS_CONFIG_HM_MA = 0x00080000, 3988 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 3989 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 3990 FW_CAPS_CONFIG_HM_UART = 0x00400000, 3991 FW_CAPS_CONFIG_HM_SF = 0x00800000, 3992 }; 3993 3994 /* 3995 * The VF Register Map. 3996 * 3997 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 3998 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 3999 * the Slice to Module Map Table (see below) in the Physical Function Register 4000 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 4001 * and Offset registers in the PF Register Map. The MBDATA base address is 4002 * quite constrained as it determines the Mailbox Data addresses for both PFs 4003 * and VFs, and therefore must fit in both the VF and PF Register Maps without 4004 * overlapping other registers. 4005 */ 4006 #define FW_T4VF_SGE_BASE_ADDR 0x0000 4007 #define FW_T4VF_MPS_BASE_ADDR 0x0100 4008 #define FW_T4VF_PL_BASE_ADDR 0x0200 4009 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 4010 #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */ 4011 #define FW_T4VF_CIM_BASE_ADDR 0x0300 4012 4013 #define FW_T4VF_REGMAP_START 0x0000 4014 #define FW_T4VF_REGMAP_SIZE 0x0400 4015 4016 enum fw_caps_config_nbm { 4017 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 4018 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 4019 }; 4020 4021 enum fw_caps_config_link { 4022 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 4023 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 4024 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 4025 }; 4026 4027 enum fw_caps_config_switch { 4028 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 4029 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 4030 }; 4031 4032 enum fw_caps_config_nic { 4033 FW_CAPS_CONFIG_NIC = 0x00000001, 4034 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 4035 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 4036 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 4037 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 4038 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 4039 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 4040 }; 4041 4042 enum fw_caps_config_toe { 4043 FW_CAPS_CONFIG_TOE = 0x00000001, 4044 }; 4045 4046 enum fw_caps_config_rdma { 4047 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 4048 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 4049 }; 4050 4051 enum fw_caps_config_iscsi { 4052 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 4053 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 4054 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 4055 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 4056 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 4057 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 4058 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, 4059 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080, 4060 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100, 4061 }; 4062 4063 enum fw_caps_config_tls { 4064 FW_CAPS_CONFIG_TLSKEYS = 0x00000001, 4065 }; 4066 4067 enum fw_caps_config_fcoe { 4068 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 4069 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 4070 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 4071 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 4072 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 4073 }; 4074 4075 enum fw_memtype_cf { 4076 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 4077 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 4078 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 4079 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 4080 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 4081 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 4082 }; 4083 4084 struct fw_caps_config_cmd { 4085 __be32 op_to_write; 4086 __be32 cfvalid_to_len16; 4087 __be32 r2; 4088 __be32 hwmbitmap; 4089 __be16 nbmcaps; 4090 __be16 linkcaps; 4091 __be16 switchcaps; 4092 __be16 r3; 4093 __be16 niccaps; 4094 __be16 toecaps; 4095 __be16 rdmacaps; 4096 __be16 tlscaps; 4097 __be16 iscsicaps; 4098 __be16 fcoecaps; 4099 __be32 cfcsum; 4100 __be32 finiver; 4101 __be32 finicsum; 4102 }; 4103 4104 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 4105 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 4106 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 4107 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 4108 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 4109 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 4110 4111 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 4112 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 4113 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4114 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4115 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4116 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 4117 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4118 4119 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 4120 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 4121 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4122 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4123 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4124 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 4125 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4126 4127 /* 4128 * params command mnemonics 4129 */ 4130 enum fw_params_mnem { 4131 FW_PARAMS_MNEM_DEV = 1, /* device params */ 4132 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 4133 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 4134 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 4135 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 4136 FW_PARAMS_MNEM_LAST 4137 }; 4138 4139 /* 4140 * device parameters 4141 */ 4142 enum fw_params_param_dev { 4143 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 4144 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 4145 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 4146 * allocated by the device's 4147 * Lookup Engine 4148 */ 4149 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 4150 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 4151 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 4152 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 4153 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 4154 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 4155 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 4156 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 4157 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 4158 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 4159 FW_PARAMS_PARAM_DEV_CF = 0x0D, 4160 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 4161 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 4162 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 4163 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 4164 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 4165 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 4166 */ 4167 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 4168 */ 4169 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 4170 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 4171 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 4172 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 4173 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, 4174 }; 4175 4176 /* 4177 * dev bypass parameters; actions and modes 4178 */ 4179 enum fw_params_param_dev_bypass { 4180 4181 /* actions 4182 */ 4183 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 4184 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 4185 4186 /* modes 4187 */ 4188 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 4189 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 4190 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 4191 }; 4192 4193 enum fw_params_param_dev_phyfw { 4194 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 4195 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 4196 }; 4197 4198 enum fw_params_param_dev_diag { 4199 FW_PARAM_DEV_DIAG_TMP = 0x00, 4200 FW_PARAM_DEV_DIAG_VDD = 0x01, 4201 }; 4202 4203 enum fw_params_param_dev_fwcache { 4204 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 4205 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 4206 }; 4207 4208 /* 4209 * physical and virtual function parameters 4210 */ 4211 enum fw_params_param_pfvf { 4212 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 4213 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 4214 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 4215 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 4216 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 4217 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 4218 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 4219 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 4220 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 4221 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 4222 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 4223 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 4224 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 4225 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 4226 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 4227 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 4228 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 4229 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 4230 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 4231 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 4232 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 4233 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 4234 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 4235 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 4236 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 4237 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 4238 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 4239 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 4240 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 4241 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 4242 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 4243 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 4244 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 4245 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 4246 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 4247 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 4248 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 4249 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 4250 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 4251 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 4252 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 4253 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 4254 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 4255 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 4256 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 4257 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 4258 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 4259 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 4260 }; 4261 4262 /* 4263 * dma queue parameters 4264 */ 4265 enum fw_params_param_dmaq { 4266 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 4267 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 4268 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 4269 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03, 4270 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 4271 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 4272 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 4273 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 4274 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14, 4275 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 4276 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30 4277 }; 4278 4279 /* 4280 * chnet parameters 4281 */ 4282 enum fw_params_param_chnet { 4283 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, 4284 }; 4285 4286 enum fw_params_param_chnet_flags { 4287 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, 4288 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, 4289 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, 4290 }; 4291 4292 #define S_FW_PARAMS_MNEM 24 4293 #define M_FW_PARAMS_MNEM 0xff 4294 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 4295 #define G_FW_PARAMS_MNEM(x) \ 4296 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 4297 4298 #define S_FW_PARAMS_PARAM_X 16 4299 #define M_FW_PARAMS_PARAM_X 0xff 4300 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 4301 #define G_FW_PARAMS_PARAM_X(x) \ 4302 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 4303 4304 #define S_FW_PARAMS_PARAM_Y 8 4305 #define M_FW_PARAMS_PARAM_Y 0xff 4306 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 4307 #define G_FW_PARAMS_PARAM_Y(x) \ 4308 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 4309 4310 #define S_FW_PARAMS_PARAM_Z 0 4311 #define M_FW_PARAMS_PARAM_Z 0xff 4312 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 4313 #define G_FW_PARAMS_PARAM_Z(x) \ 4314 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 4315 4316 #define S_FW_PARAMS_PARAM_XYZ 0 4317 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 4318 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 4319 #define G_FW_PARAMS_PARAM_XYZ(x) \ 4320 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 4321 4322 #define S_FW_PARAMS_PARAM_YZ 0 4323 #define M_FW_PARAMS_PARAM_YZ 0xffff 4324 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 4325 #define G_FW_PARAMS_PARAM_YZ(x) \ 4326 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 4327 4328 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31 4329 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1 4330 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4331 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4332 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4333 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \ 4334 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4335 4336 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24 4337 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3 4338 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4339 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4340 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4341 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \ 4342 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4343 4344 #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0 4345 #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff 4346 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4347 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4348 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4349 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4350 4351 struct fw_params_cmd { 4352 __be32 op_to_vfn; 4353 __be32 retval_len16; 4354 struct fw_params_param { 4355 __be32 mnem; 4356 __be32 val; 4357 } param[7]; 4358 }; 4359 4360 #define S_FW_PARAMS_CMD_PFN 8 4361 #define M_FW_PARAMS_CMD_PFN 0x7 4362 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 4363 #define G_FW_PARAMS_CMD_PFN(x) \ 4364 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 4365 4366 #define S_FW_PARAMS_CMD_VFN 0 4367 #define M_FW_PARAMS_CMD_VFN 0xff 4368 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 4369 #define G_FW_PARAMS_CMD_VFN(x) \ 4370 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 4371 4372 struct fw_pfvf_cmd { 4373 __be32 op_to_vfn; 4374 __be32 retval_len16; 4375 __be32 niqflint_niq; 4376 __be32 type_to_neq; 4377 __be32 tc_to_nexactf; 4378 __be32 r_caps_to_nethctrl; 4379 __be16 nricq; 4380 __be16 nriqp; 4381 __be32 r4; 4382 }; 4383 4384 #define S_FW_PFVF_CMD_PFN 8 4385 #define M_FW_PFVF_CMD_PFN 0x7 4386 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 4387 #define G_FW_PFVF_CMD_PFN(x) \ 4388 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 4389 4390 #define S_FW_PFVF_CMD_VFN 0 4391 #define M_FW_PFVF_CMD_VFN 0xff 4392 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 4393 #define G_FW_PFVF_CMD_VFN(x) \ 4394 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 4395 4396 #define S_FW_PFVF_CMD_NIQFLINT 20 4397 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 4398 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 4399 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 4400 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 4401 4402 #define S_FW_PFVF_CMD_NIQ 0 4403 #define M_FW_PFVF_CMD_NIQ 0xfffff 4404 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 4405 #define G_FW_PFVF_CMD_NIQ(x) \ 4406 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 4407 4408 #define S_FW_PFVF_CMD_TYPE 31 4409 #define M_FW_PFVF_CMD_TYPE 0x1 4410 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 4411 #define G_FW_PFVF_CMD_TYPE(x) \ 4412 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 4413 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 4414 4415 #define S_FW_PFVF_CMD_CMASK 24 4416 #define M_FW_PFVF_CMD_CMASK 0xf 4417 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 4418 #define G_FW_PFVF_CMD_CMASK(x) \ 4419 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 4420 4421 #define S_FW_PFVF_CMD_PMASK 20 4422 #define M_FW_PFVF_CMD_PMASK 0xf 4423 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 4424 #define G_FW_PFVF_CMD_PMASK(x) \ 4425 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 4426 4427 #define S_FW_PFVF_CMD_NEQ 0 4428 #define M_FW_PFVF_CMD_NEQ 0xfffff 4429 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 4430 #define G_FW_PFVF_CMD_NEQ(x) \ 4431 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 4432 4433 #define S_FW_PFVF_CMD_TC 24 4434 #define M_FW_PFVF_CMD_TC 0xff 4435 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 4436 #define G_FW_PFVF_CMD_TC(x) \ 4437 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 4438 4439 #define S_FW_PFVF_CMD_NVI 16 4440 #define M_FW_PFVF_CMD_NVI 0xff 4441 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 4442 #define G_FW_PFVF_CMD_NVI(x) \ 4443 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 4444 4445 #define S_FW_PFVF_CMD_NEXACTF 0 4446 #define M_FW_PFVF_CMD_NEXACTF 0xffff 4447 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 4448 #define G_FW_PFVF_CMD_NEXACTF(x) \ 4449 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 4450 4451 #define S_FW_PFVF_CMD_R_CAPS 24 4452 #define M_FW_PFVF_CMD_R_CAPS 0xff 4453 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 4454 #define G_FW_PFVF_CMD_R_CAPS(x) \ 4455 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 4456 4457 #define S_FW_PFVF_CMD_WX_CAPS 16 4458 #define M_FW_PFVF_CMD_WX_CAPS 0xff 4459 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 4460 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 4461 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 4462 4463 #define S_FW_PFVF_CMD_NETHCTRL 0 4464 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 4465 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 4466 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 4467 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 4468 4469 /* 4470 * ingress queue type; the first 1K ingress queues can have associated 0, 4471 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 4472 * capabilities 4473 */ 4474 enum fw_iq_type { 4475 FW_IQ_TYPE_FL_INT_CAP, 4476 FW_IQ_TYPE_NO_FL_INT_CAP 4477 }; 4478 4479 struct fw_iq_cmd { 4480 __be32 op_to_vfn; 4481 __be32 alloc_to_len16; 4482 __be16 physiqid; 4483 __be16 iqid; 4484 __be16 fl0id; 4485 __be16 fl1id; 4486 __be32 type_to_iqandstindex; 4487 __be16 iqdroprss_to_iqesize; 4488 __be16 iqsize; 4489 __be64 iqaddr; 4490 __be32 iqns_to_fl0congen; 4491 __be16 fl0dcaen_to_fl0cidxfthresh; 4492 __be16 fl0size; 4493 __be64 fl0addr; 4494 __be32 fl1cngchmap_to_fl1congen; 4495 __be16 fl1dcaen_to_fl1cidxfthresh; 4496 __be16 fl1size; 4497 __be64 fl1addr; 4498 }; 4499 4500 #define S_FW_IQ_CMD_PFN 8 4501 #define M_FW_IQ_CMD_PFN 0x7 4502 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 4503 #define G_FW_IQ_CMD_PFN(x) \ 4504 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 4505 4506 #define S_FW_IQ_CMD_VFN 0 4507 #define M_FW_IQ_CMD_VFN 0xff 4508 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 4509 #define G_FW_IQ_CMD_VFN(x) \ 4510 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 4511 4512 #define S_FW_IQ_CMD_ALLOC 31 4513 #define M_FW_IQ_CMD_ALLOC 0x1 4514 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 4515 #define G_FW_IQ_CMD_ALLOC(x) \ 4516 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 4517 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 4518 4519 #define S_FW_IQ_CMD_FREE 30 4520 #define M_FW_IQ_CMD_FREE 0x1 4521 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 4522 #define G_FW_IQ_CMD_FREE(x) \ 4523 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 4524 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 4525 4526 #define S_FW_IQ_CMD_MODIFY 29 4527 #define M_FW_IQ_CMD_MODIFY 0x1 4528 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 4529 #define G_FW_IQ_CMD_MODIFY(x) \ 4530 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 4531 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 4532 4533 #define S_FW_IQ_CMD_IQSTART 28 4534 #define M_FW_IQ_CMD_IQSTART 0x1 4535 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 4536 #define G_FW_IQ_CMD_IQSTART(x) \ 4537 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 4538 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 4539 4540 #define S_FW_IQ_CMD_IQSTOP 27 4541 #define M_FW_IQ_CMD_IQSTOP 0x1 4542 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 4543 #define G_FW_IQ_CMD_IQSTOP(x) \ 4544 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 4545 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 4546 4547 #define S_FW_IQ_CMD_TYPE 29 4548 #define M_FW_IQ_CMD_TYPE 0x7 4549 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 4550 #define G_FW_IQ_CMD_TYPE(x) \ 4551 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 4552 4553 #define S_FW_IQ_CMD_IQASYNCH 28 4554 #define M_FW_IQ_CMD_IQASYNCH 0x1 4555 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 4556 #define G_FW_IQ_CMD_IQASYNCH(x) \ 4557 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 4558 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 4559 4560 #define S_FW_IQ_CMD_VIID 16 4561 #define M_FW_IQ_CMD_VIID 0xfff 4562 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 4563 #define G_FW_IQ_CMD_VIID(x) \ 4564 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 4565 4566 #define S_FW_IQ_CMD_IQANDST 15 4567 #define M_FW_IQ_CMD_IQANDST 0x1 4568 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 4569 #define G_FW_IQ_CMD_IQANDST(x) \ 4570 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 4571 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 4572 4573 #define S_FW_IQ_CMD_IQANUS 14 4574 #define M_FW_IQ_CMD_IQANUS 0x1 4575 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 4576 #define G_FW_IQ_CMD_IQANUS(x) \ 4577 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 4578 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 4579 4580 #define S_FW_IQ_CMD_IQANUD 12 4581 #define M_FW_IQ_CMD_IQANUD 0x3 4582 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 4583 #define G_FW_IQ_CMD_IQANUD(x) \ 4584 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 4585 4586 #define S_FW_IQ_CMD_IQANDSTINDEX 0 4587 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 4588 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 4589 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 4590 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 4591 4592 #define S_FW_IQ_CMD_IQDROPRSS 15 4593 #define M_FW_IQ_CMD_IQDROPRSS 0x1 4594 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 4595 #define G_FW_IQ_CMD_IQDROPRSS(x) \ 4596 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 4597 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 4598 4599 #define S_FW_IQ_CMD_IQGTSMODE 14 4600 #define M_FW_IQ_CMD_IQGTSMODE 0x1 4601 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 4602 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 4603 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 4604 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 4605 4606 #define S_FW_IQ_CMD_IQPCIECH 12 4607 #define M_FW_IQ_CMD_IQPCIECH 0x3 4608 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 4609 #define G_FW_IQ_CMD_IQPCIECH(x) \ 4610 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 4611 4612 #define S_FW_IQ_CMD_IQDCAEN 11 4613 #define M_FW_IQ_CMD_IQDCAEN 0x1 4614 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 4615 #define G_FW_IQ_CMD_IQDCAEN(x) \ 4616 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 4617 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 4618 4619 #define S_FW_IQ_CMD_IQDCACPU 6 4620 #define M_FW_IQ_CMD_IQDCACPU 0x1f 4621 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 4622 #define G_FW_IQ_CMD_IQDCACPU(x) \ 4623 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 4624 4625 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 4626 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 4627 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 4628 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 4629 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 4630 4631 #define S_FW_IQ_CMD_IQO 3 4632 #define M_FW_IQ_CMD_IQO 0x1 4633 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 4634 #define G_FW_IQ_CMD_IQO(x) \ 4635 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 4636 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 4637 4638 #define S_FW_IQ_CMD_IQCPRIO 2 4639 #define M_FW_IQ_CMD_IQCPRIO 0x1 4640 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 4641 #define G_FW_IQ_CMD_IQCPRIO(x) \ 4642 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 4643 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 4644 4645 #define S_FW_IQ_CMD_IQESIZE 0 4646 #define M_FW_IQ_CMD_IQESIZE 0x3 4647 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 4648 #define G_FW_IQ_CMD_IQESIZE(x) \ 4649 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 4650 4651 #define S_FW_IQ_CMD_IQNS 31 4652 #define M_FW_IQ_CMD_IQNS 0x1 4653 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 4654 #define G_FW_IQ_CMD_IQNS(x) \ 4655 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 4656 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 4657 4658 #define S_FW_IQ_CMD_IQRO 30 4659 #define M_FW_IQ_CMD_IQRO 0x1 4660 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 4661 #define G_FW_IQ_CMD_IQRO(x) \ 4662 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 4663 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 4664 4665 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 4666 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 4667 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 4668 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 4669 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 4670 4671 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 4672 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 4673 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 4674 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 4675 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 4676 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 4677 4678 #define S_FW_IQ_CMD_IQFLINTISCSIC 26 4679 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 4680 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 4681 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 4682 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 4683 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 4684 4685 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 4686 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 4687 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 4688 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 4689 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 4690 4691 #define S_FW_IQ_CMD_FL0CONGDROP 16 4692 #define M_FW_IQ_CMD_FL0CONGDROP 0x1 4693 #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) 4694 #define G_FW_IQ_CMD_FL0CONGDROP(x) \ 4695 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) 4696 #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) 4697 4698 #define S_FW_IQ_CMD_FL0CACHELOCK 15 4699 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 4700 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 4701 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 4702 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 4703 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 4704 4705 #define S_FW_IQ_CMD_FL0DBP 14 4706 #define M_FW_IQ_CMD_FL0DBP 0x1 4707 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 4708 #define G_FW_IQ_CMD_FL0DBP(x) \ 4709 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 4710 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 4711 4712 #define S_FW_IQ_CMD_FL0DATANS 13 4713 #define M_FW_IQ_CMD_FL0DATANS 0x1 4714 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 4715 #define G_FW_IQ_CMD_FL0DATANS(x) \ 4716 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 4717 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 4718 4719 #define S_FW_IQ_CMD_FL0DATARO 12 4720 #define M_FW_IQ_CMD_FL0DATARO 0x1 4721 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 4722 #define G_FW_IQ_CMD_FL0DATARO(x) \ 4723 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 4724 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 4725 4726 #define S_FW_IQ_CMD_FL0CONGCIF 11 4727 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 4728 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 4729 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 4730 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 4731 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 4732 4733 #define S_FW_IQ_CMD_FL0ONCHIP 10 4734 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 4735 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 4736 #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 4737 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 4738 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 4739 4740 #define S_FW_IQ_CMD_FL0STATUSPGNS 9 4741 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 4742 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 4743 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 4744 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 4745 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 4746 4747 #define S_FW_IQ_CMD_FL0STATUSPGRO 8 4748 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 4749 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 4750 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 4751 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 4752 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 4753 4754 #define S_FW_IQ_CMD_FL0FETCHNS 7 4755 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 4756 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 4757 #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 4758 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 4759 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 4760 4761 #define S_FW_IQ_CMD_FL0FETCHRO 6 4762 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 4763 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 4764 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 4765 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 4766 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 4767 4768 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 4769 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 4770 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 4771 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 4772 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 4773 4774 #define S_FW_IQ_CMD_FL0CPRIO 3 4775 #define M_FW_IQ_CMD_FL0CPRIO 0x1 4776 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 4777 #define G_FW_IQ_CMD_FL0CPRIO(x) \ 4778 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 4779 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 4780 4781 #define S_FW_IQ_CMD_FL0PADEN 2 4782 #define M_FW_IQ_CMD_FL0PADEN 0x1 4783 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 4784 #define G_FW_IQ_CMD_FL0PADEN(x) \ 4785 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 4786 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 4787 4788 #define S_FW_IQ_CMD_FL0PACKEN 1 4789 #define M_FW_IQ_CMD_FL0PACKEN 0x1 4790 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 4791 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 4792 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 4793 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 4794 4795 #define S_FW_IQ_CMD_FL0CONGEN 0 4796 #define M_FW_IQ_CMD_FL0CONGEN 0x1 4797 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 4798 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 4799 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 4800 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 4801 4802 #define S_FW_IQ_CMD_FL0DCAEN 15 4803 #define M_FW_IQ_CMD_FL0DCAEN 0x1 4804 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 4805 #define G_FW_IQ_CMD_FL0DCAEN(x) \ 4806 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 4807 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 4808 4809 #define S_FW_IQ_CMD_FL0DCACPU 10 4810 #define M_FW_IQ_CMD_FL0DCACPU 0x1f 4811 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 4812 #define G_FW_IQ_CMD_FL0DCACPU(x) \ 4813 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 4814 4815 #define S_FW_IQ_CMD_FL0FBMIN 7 4816 #define M_FW_IQ_CMD_FL0FBMIN 0x7 4817 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 4818 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 4819 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 4820 4821 #define S_FW_IQ_CMD_FL0FBMAX 4 4822 #define M_FW_IQ_CMD_FL0FBMAX 0x7 4823 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 4824 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 4825 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 4826 4827 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 4828 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 4829 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 4830 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 4831 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 4832 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 4833 4834 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 4835 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 4836 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 4837 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 4838 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 4839 4840 #define S_FW_IQ_CMD_FL1CNGCHMAP 20 4841 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 4842 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 4843 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 4844 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 4845 4846 #define S_FW_IQ_CMD_FL1CONGDROP 16 4847 #define M_FW_IQ_CMD_FL1CONGDROP 0x1 4848 #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) 4849 #define G_FW_IQ_CMD_FL1CONGDROP(x) \ 4850 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) 4851 #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) 4852 4853 #define S_FW_IQ_CMD_FL1CACHELOCK 15 4854 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 4855 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 4856 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 4857 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 4858 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 4859 4860 #define S_FW_IQ_CMD_FL1DBP 14 4861 #define M_FW_IQ_CMD_FL1DBP 0x1 4862 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 4863 #define G_FW_IQ_CMD_FL1DBP(x) \ 4864 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 4865 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 4866 4867 #define S_FW_IQ_CMD_FL1DATANS 13 4868 #define M_FW_IQ_CMD_FL1DATANS 0x1 4869 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 4870 #define G_FW_IQ_CMD_FL1DATANS(x) \ 4871 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 4872 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 4873 4874 #define S_FW_IQ_CMD_FL1DATARO 12 4875 #define M_FW_IQ_CMD_FL1DATARO 0x1 4876 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 4877 #define G_FW_IQ_CMD_FL1DATARO(x) \ 4878 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 4879 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 4880 4881 #define S_FW_IQ_CMD_FL1CONGCIF 11 4882 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 4883 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 4884 #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 4885 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 4886 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 4887 4888 #define S_FW_IQ_CMD_FL1ONCHIP 10 4889 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 4890 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 4891 #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 4892 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 4893 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 4894 4895 #define S_FW_IQ_CMD_FL1STATUSPGNS 9 4896 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 4897 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 4898 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 4899 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 4900 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 4901 4902 #define S_FW_IQ_CMD_FL1STATUSPGRO 8 4903 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 4904 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 4905 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 4906 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 4907 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 4908 4909 #define S_FW_IQ_CMD_FL1FETCHNS 7 4910 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 4911 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 4912 #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 4913 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 4914 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 4915 4916 #define S_FW_IQ_CMD_FL1FETCHRO 6 4917 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 4918 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 4919 #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 4920 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 4921 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 4922 4923 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 4924 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 4925 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 4926 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 4927 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 4928 4929 #define S_FW_IQ_CMD_FL1CPRIO 3 4930 #define M_FW_IQ_CMD_FL1CPRIO 0x1 4931 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 4932 #define G_FW_IQ_CMD_FL1CPRIO(x) \ 4933 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 4934 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 4935 4936 #define S_FW_IQ_CMD_FL1PADEN 2 4937 #define M_FW_IQ_CMD_FL1PADEN 0x1 4938 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 4939 #define G_FW_IQ_CMD_FL1PADEN(x) \ 4940 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 4941 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 4942 4943 #define S_FW_IQ_CMD_FL1PACKEN 1 4944 #define M_FW_IQ_CMD_FL1PACKEN 0x1 4945 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 4946 #define G_FW_IQ_CMD_FL1PACKEN(x) \ 4947 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 4948 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 4949 4950 #define S_FW_IQ_CMD_FL1CONGEN 0 4951 #define M_FW_IQ_CMD_FL1CONGEN 0x1 4952 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 4953 #define G_FW_IQ_CMD_FL1CONGEN(x) \ 4954 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 4955 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 4956 4957 #define S_FW_IQ_CMD_FL1DCAEN 15 4958 #define M_FW_IQ_CMD_FL1DCAEN 0x1 4959 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 4960 #define G_FW_IQ_CMD_FL1DCAEN(x) \ 4961 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 4962 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 4963 4964 #define S_FW_IQ_CMD_FL1DCACPU 10 4965 #define M_FW_IQ_CMD_FL1DCACPU 0x1f 4966 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 4967 #define G_FW_IQ_CMD_FL1DCACPU(x) \ 4968 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 4969 4970 #define S_FW_IQ_CMD_FL1FBMIN 7 4971 #define M_FW_IQ_CMD_FL1FBMIN 0x7 4972 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 4973 #define G_FW_IQ_CMD_FL1FBMIN(x) \ 4974 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 4975 4976 #define S_FW_IQ_CMD_FL1FBMAX 4 4977 #define M_FW_IQ_CMD_FL1FBMAX 0x7 4978 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 4979 #define G_FW_IQ_CMD_FL1FBMAX(x) \ 4980 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 4981 4982 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 4983 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 4984 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 4985 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 4986 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 4987 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 4988 4989 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 4990 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 4991 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 4992 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 4993 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 4994 4995 struct fw_eq_mngt_cmd { 4996 __be32 op_to_vfn; 4997 __be32 alloc_to_len16; 4998 __be32 cmpliqid_eqid; 4999 __be32 physeqid_pkd; 5000 __be32 fetchszm_to_iqid; 5001 __be32 dcaen_to_eqsize; 5002 __be64 eqaddr; 5003 }; 5004 5005 #define S_FW_EQ_MNGT_CMD_PFN 8 5006 #define M_FW_EQ_MNGT_CMD_PFN 0x7 5007 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 5008 #define G_FW_EQ_MNGT_CMD_PFN(x) \ 5009 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 5010 5011 #define S_FW_EQ_MNGT_CMD_VFN 0 5012 #define M_FW_EQ_MNGT_CMD_VFN 0xff 5013 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 5014 #define G_FW_EQ_MNGT_CMD_VFN(x) \ 5015 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 5016 5017 #define S_FW_EQ_MNGT_CMD_ALLOC 31 5018 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 5019 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 5020 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 5021 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 5022 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 5023 5024 #define S_FW_EQ_MNGT_CMD_FREE 30 5025 #define M_FW_EQ_MNGT_CMD_FREE 0x1 5026 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 5027 #define G_FW_EQ_MNGT_CMD_FREE(x) \ 5028 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 5029 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 5030 5031 #define S_FW_EQ_MNGT_CMD_MODIFY 29 5032 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 5033 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 5034 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 5035 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 5036 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 5037 5038 #define S_FW_EQ_MNGT_CMD_EQSTART 28 5039 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 5040 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 5041 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 5042 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 5043 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 5044 5045 #define S_FW_EQ_MNGT_CMD_EQSTOP 27 5046 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 5047 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 5048 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 5049 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 5050 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 5051 5052 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 5053 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 5054 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 5055 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 5056 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 5057 5058 #define S_FW_EQ_MNGT_CMD_EQID 0 5059 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 5060 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 5061 #define G_FW_EQ_MNGT_CMD_EQID(x) \ 5062 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 5063 5064 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 5065 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 5066 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 5067 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 5068 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 5069 5070 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 5071 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 5072 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 5073 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 5074 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 5075 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 5076 5077 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 5078 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 5079 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 5080 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 5081 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 5082 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 5083 5084 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 5085 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 5086 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 5087 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 5088 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 5089 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 5090 5091 #define S_FW_EQ_MNGT_CMD_FETCHNS 23 5092 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 5093 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 5094 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 5095 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 5096 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 5097 5098 #define S_FW_EQ_MNGT_CMD_FETCHRO 22 5099 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 5100 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 5101 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 5102 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 5103 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 5104 5105 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 5106 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 5107 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 5108 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 5109 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 5110 5111 #define S_FW_EQ_MNGT_CMD_CPRIO 19 5112 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 5113 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 5114 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 5115 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 5116 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 5117 5118 #define S_FW_EQ_MNGT_CMD_ONCHIP 18 5119 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 5120 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 5121 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 5122 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 5123 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 5124 5125 #define S_FW_EQ_MNGT_CMD_PCIECHN 16 5126 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 5127 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 5128 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 5129 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 5130 5131 #define S_FW_EQ_MNGT_CMD_IQID 0 5132 #define M_FW_EQ_MNGT_CMD_IQID 0xffff 5133 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 5134 #define G_FW_EQ_MNGT_CMD_IQID(x) \ 5135 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 5136 5137 #define S_FW_EQ_MNGT_CMD_DCAEN 31 5138 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 5139 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 5140 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 5141 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 5142 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 5143 5144 #define S_FW_EQ_MNGT_CMD_DCACPU 26 5145 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 5146 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 5147 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 5148 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 5149 5150 #define S_FW_EQ_MNGT_CMD_FBMIN 23 5151 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 5152 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 5153 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 5154 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 5155 5156 #define S_FW_EQ_MNGT_CMD_FBMAX 20 5157 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 5158 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 5159 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 5160 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 5161 5162 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 5163 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 5164 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5165 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5166 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5167 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5168 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 5169 5170 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 5171 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 5172 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5173 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 5174 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5175 5176 #define S_FW_EQ_MNGT_CMD_EQSIZE 0 5177 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 5178 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 5179 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 5180 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 5181 5182 struct fw_eq_eth_cmd { 5183 __be32 op_to_vfn; 5184 __be32 alloc_to_len16; 5185 __be32 eqid_pkd; 5186 __be32 physeqid_pkd; 5187 __be32 fetchszm_to_iqid; 5188 __be32 dcaen_to_eqsize; 5189 __be64 eqaddr; 5190 __be32 autoequiqe_to_viid; 5191 __be32 r8_lo; 5192 __be64 r9; 5193 }; 5194 5195 #define S_FW_EQ_ETH_CMD_PFN 8 5196 #define M_FW_EQ_ETH_CMD_PFN 0x7 5197 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 5198 #define G_FW_EQ_ETH_CMD_PFN(x) \ 5199 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 5200 5201 #define S_FW_EQ_ETH_CMD_VFN 0 5202 #define M_FW_EQ_ETH_CMD_VFN 0xff 5203 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 5204 #define G_FW_EQ_ETH_CMD_VFN(x) \ 5205 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 5206 5207 #define S_FW_EQ_ETH_CMD_ALLOC 31 5208 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 5209 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 5210 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 5211 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 5212 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 5213 5214 #define S_FW_EQ_ETH_CMD_FREE 30 5215 #define M_FW_EQ_ETH_CMD_FREE 0x1 5216 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 5217 #define G_FW_EQ_ETH_CMD_FREE(x) \ 5218 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 5219 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 5220 5221 #define S_FW_EQ_ETH_CMD_MODIFY 29 5222 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 5223 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 5224 #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 5225 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 5226 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 5227 5228 #define S_FW_EQ_ETH_CMD_EQSTART 28 5229 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 5230 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 5231 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 5232 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 5233 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 5234 5235 #define S_FW_EQ_ETH_CMD_EQSTOP 27 5236 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 5237 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 5238 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 5239 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 5240 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 5241 5242 #define S_FW_EQ_ETH_CMD_EQID 0 5243 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 5244 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 5245 #define G_FW_EQ_ETH_CMD_EQID(x) \ 5246 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 5247 5248 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 5249 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 5250 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 5251 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 5252 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 5253 5254 #define S_FW_EQ_ETH_CMD_FETCHSZM 26 5255 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 5256 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 5257 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 5258 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 5259 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 5260 5261 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 5262 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 5263 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 5264 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 5265 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 5266 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 5267 5268 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 5269 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 5270 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 5271 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 5272 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 5273 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 5274 5275 #define S_FW_EQ_ETH_CMD_FETCHNS 23 5276 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 5277 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 5278 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 5279 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 5280 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 5281 5282 #define S_FW_EQ_ETH_CMD_FETCHRO 22 5283 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 5284 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 5285 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 5286 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 5287 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 5288 5289 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 5290 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 5291 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 5292 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 5293 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 5294 5295 #define S_FW_EQ_ETH_CMD_CPRIO 19 5296 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 5297 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 5298 #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 5299 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 5300 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 5301 5302 #define S_FW_EQ_ETH_CMD_ONCHIP 18 5303 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 5304 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 5305 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 5306 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 5307 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 5308 5309 #define S_FW_EQ_ETH_CMD_PCIECHN 16 5310 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 5311 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 5312 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 5313 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 5314 5315 #define S_FW_EQ_ETH_CMD_IQID 0 5316 #define M_FW_EQ_ETH_CMD_IQID 0xffff 5317 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 5318 #define G_FW_EQ_ETH_CMD_IQID(x) \ 5319 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 5320 5321 #define S_FW_EQ_ETH_CMD_DCAEN 31 5322 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 5323 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 5324 #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 5325 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 5326 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 5327 5328 #define S_FW_EQ_ETH_CMD_DCACPU 26 5329 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 5330 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 5331 #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 5332 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 5333 5334 #define S_FW_EQ_ETH_CMD_FBMIN 23 5335 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 5336 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 5337 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 5338 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 5339 5340 #define S_FW_EQ_ETH_CMD_FBMAX 20 5341 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 5342 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 5343 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 5344 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 5345 5346 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 5347 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 5348 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 5349 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 5350 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 5351 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 5352 5353 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 5354 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 5355 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 5356 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 5357 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 5358 5359 #define S_FW_EQ_ETH_CMD_EQSIZE 0 5360 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 5361 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 5362 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 5363 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 5364 5365 #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 5366 #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 5367 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 5368 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 5369 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 5370 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 5371 5372 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 5373 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 5374 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 5375 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 5376 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 5377 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 5378 5379 #define S_FW_EQ_ETH_CMD_VIID 16 5380 #define M_FW_EQ_ETH_CMD_VIID 0xfff 5381 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 5382 #define G_FW_EQ_ETH_CMD_VIID(x) \ 5383 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 5384 5385 struct fw_eq_ctrl_cmd { 5386 __be32 op_to_vfn; 5387 __be32 alloc_to_len16; 5388 __be32 cmpliqid_eqid; 5389 __be32 physeqid_pkd; 5390 __be32 fetchszm_to_iqid; 5391 __be32 dcaen_to_eqsize; 5392 __be64 eqaddr; 5393 }; 5394 5395 #define S_FW_EQ_CTRL_CMD_PFN 8 5396 #define M_FW_EQ_CTRL_CMD_PFN 0x7 5397 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 5398 #define G_FW_EQ_CTRL_CMD_PFN(x) \ 5399 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 5400 5401 #define S_FW_EQ_CTRL_CMD_VFN 0 5402 #define M_FW_EQ_CTRL_CMD_VFN 0xff 5403 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 5404 #define G_FW_EQ_CTRL_CMD_VFN(x) \ 5405 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 5406 5407 #define S_FW_EQ_CTRL_CMD_ALLOC 31 5408 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 5409 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 5410 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 5411 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 5412 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 5413 5414 #define S_FW_EQ_CTRL_CMD_FREE 30 5415 #define M_FW_EQ_CTRL_CMD_FREE 0x1 5416 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 5417 #define G_FW_EQ_CTRL_CMD_FREE(x) \ 5418 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 5419 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 5420 5421 #define S_FW_EQ_CTRL_CMD_MODIFY 29 5422 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 5423 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 5424 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 5425 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 5426 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 5427 5428 #define S_FW_EQ_CTRL_CMD_EQSTART 28 5429 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 5430 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 5431 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 5432 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 5433 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 5434 5435 #define S_FW_EQ_CTRL_CMD_EQSTOP 27 5436 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 5437 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 5438 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 5439 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 5440 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 5441 5442 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 5443 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 5444 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 5445 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 5446 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 5447 5448 #define S_FW_EQ_CTRL_CMD_EQID 0 5449 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 5450 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 5451 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 5452 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 5453 5454 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 5455 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 5456 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 5457 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 5458 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 5459 5460 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 5461 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 5462 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 5463 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 5464 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 5465 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 5466 5467 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 5468 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 5469 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 5470 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 5471 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 5472 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 5473 5474 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 5475 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 5476 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 5477 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 5478 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 5479 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 5480 5481 #define S_FW_EQ_CTRL_CMD_FETCHNS 23 5482 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 5483 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 5484 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 5485 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 5486 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 5487 5488 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 5489 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 5490 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 5491 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 5492 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 5493 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 5494 5495 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 5496 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 5497 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 5498 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 5499 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 5500 5501 #define S_FW_EQ_CTRL_CMD_CPRIO 19 5502 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 5503 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 5504 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 5505 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 5506 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 5507 5508 #define S_FW_EQ_CTRL_CMD_ONCHIP 18 5509 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 5510 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 5511 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 5512 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 5513 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 5514 5515 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 5516 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 5517 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 5518 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 5519 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 5520 5521 #define S_FW_EQ_CTRL_CMD_IQID 0 5522 #define M_FW_EQ_CTRL_CMD_IQID 0xffff 5523 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 5524 #define G_FW_EQ_CTRL_CMD_IQID(x) \ 5525 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 5526 5527 #define S_FW_EQ_CTRL_CMD_DCAEN 31 5528 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 5529 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 5530 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 5531 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 5532 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 5533 5534 #define S_FW_EQ_CTRL_CMD_DCACPU 26 5535 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 5536 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 5537 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 5538 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 5539 5540 #define S_FW_EQ_CTRL_CMD_FBMIN 23 5541 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 5542 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 5543 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 5544 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 5545 5546 #define S_FW_EQ_CTRL_CMD_FBMAX 20 5547 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 5548 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 5549 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 5550 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 5551 5552 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 5553 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 5554 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 5555 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 5556 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 5557 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 5558 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 5559 5560 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 5561 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 5562 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 5563 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 5564 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 5565 5566 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 5567 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 5568 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 5569 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 5570 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 5571 5572 struct fw_eq_ofld_cmd { 5573 __be32 op_to_vfn; 5574 __be32 alloc_to_len16; 5575 __be32 eqid_pkd; 5576 __be32 physeqid_pkd; 5577 __be32 fetchszm_to_iqid; 5578 __be32 dcaen_to_eqsize; 5579 __be64 eqaddr; 5580 }; 5581 5582 #define S_FW_EQ_OFLD_CMD_PFN 8 5583 #define M_FW_EQ_OFLD_CMD_PFN 0x7 5584 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 5585 #define G_FW_EQ_OFLD_CMD_PFN(x) \ 5586 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 5587 5588 #define S_FW_EQ_OFLD_CMD_VFN 0 5589 #define M_FW_EQ_OFLD_CMD_VFN 0xff 5590 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 5591 #define G_FW_EQ_OFLD_CMD_VFN(x) \ 5592 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 5593 5594 #define S_FW_EQ_OFLD_CMD_ALLOC 31 5595 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 5596 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 5597 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 5598 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 5599 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 5600 5601 #define S_FW_EQ_OFLD_CMD_FREE 30 5602 #define M_FW_EQ_OFLD_CMD_FREE 0x1 5603 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 5604 #define G_FW_EQ_OFLD_CMD_FREE(x) \ 5605 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 5606 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 5607 5608 #define S_FW_EQ_OFLD_CMD_MODIFY 29 5609 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 5610 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 5611 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 5612 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 5613 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 5614 5615 #define S_FW_EQ_OFLD_CMD_EQSTART 28 5616 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 5617 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 5618 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 5619 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 5620 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 5621 5622 #define S_FW_EQ_OFLD_CMD_EQSTOP 27 5623 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 5624 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 5625 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 5626 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 5627 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 5628 5629 #define S_FW_EQ_OFLD_CMD_EQID 0 5630 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 5631 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 5632 #define G_FW_EQ_OFLD_CMD_EQID(x) \ 5633 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 5634 5635 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 5636 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 5637 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 5638 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 5639 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 5640 5641 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 5642 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 5643 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 5644 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 5645 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 5646 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 5647 5648 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 5649 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 5650 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 5651 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 5652 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 5653 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 5654 5655 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 5656 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 5657 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 5658 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 5659 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 5660 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 5661 5662 #define S_FW_EQ_OFLD_CMD_FETCHNS 23 5663 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 5664 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 5665 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 5666 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 5667 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 5668 5669 #define S_FW_EQ_OFLD_CMD_FETCHRO 22 5670 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 5671 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 5672 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 5673 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 5674 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 5675 5676 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 5677 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 5678 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 5679 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 5680 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 5681 5682 #define S_FW_EQ_OFLD_CMD_CPRIO 19 5683 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 5684 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 5685 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 5686 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 5687 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 5688 5689 #define S_FW_EQ_OFLD_CMD_ONCHIP 18 5690 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 5691 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 5692 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 5693 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 5694 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 5695 5696 #define S_FW_EQ_OFLD_CMD_PCIECHN 16 5697 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 5698 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 5699 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 5700 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 5701 5702 #define S_FW_EQ_OFLD_CMD_IQID 0 5703 #define M_FW_EQ_OFLD_CMD_IQID 0xffff 5704 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 5705 #define G_FW_EQ_OFLD_CMD_IQID(x) \ 5706 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 5707 5708 #define S_FW_EQ_OFLD_CMD_DCAEN 31 5709 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 5710 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 5711 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 5712 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 5713 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 5714 5715 #define S_FW_EQ_OFLD_CMD_DCACPU 26 5716 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 5717 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 5718 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 5719 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 5720 5721 #define S_FW_EQ_OFLD_CMD_FBMIN 23 5722 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 5723 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 5724 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 5725 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 5726 5727 #define S_FW_EQ_OFLD_CMD_FBMAX 20 5728 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 5729 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 5730 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 5731 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 5732 5733 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 5734 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 5735 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 5736 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 5737 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 5738 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 5739 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 5740 5741 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 5742 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 5743 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 5744 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 5745 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 5746 5747 #define S_FW_EQ_OFLD_CMD_EQSIZE 0 5748 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 5749 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 5750 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 5751 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 5752 5753 /* Macros for VIID parsing: 5754 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 5755 #define S_FW_VIID_PFN 8 5756 #define M_FW_VIID_PFN 0x7 5757 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 5758 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 5759 5760 #define S_FW_VIID_VIVLD 7 5761 #define M_FW_VIID_VIVLD 0x1 5762 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 5763 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 5764 5765 #define S_FW_VIID_VIN 0 5766 #define M_FW_VIID_VIN 0x7F 5767 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 5768 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 5769 5770 enum fw_vi_func { 5771 FW_VI_FUNC_ETH, 5772 FW_VI_FUNC_OFLD, 5773 FW_VI_FUNC_IWARP, 5774 FW_VI_FUNC_OPENISCSI, 5775 FW_VI_FUNC_OPENFCOE, 5776 FW_VI_FUNC_FOISCSI, 5777 FW_VI_FUNC_FOFCOE, 5778 FW_VI_FUNC_FW, 5779 }; 5780 5781 struct fw_vi_cmd { 5782 __be32 op_to_vfn; 5783 __be32 alloc_to_len16; 5784 __be16 type_to_viid; 5785 __u8 mac[6]; 5786 __u8 portid_pkd; 5787 __u8 nmac; 5788 __u8 nmac0[6]; 5789 __be16 norss_rsssize; 5790 __u8 nmac1[6]; 5791 __be16 idsiiq_pkd; 5792 __u8 nmac2[6]; 5793 __be16 idseiq_pkd; 5794 __u8 nmac3[6]; 5795 __be64 r9; 5796 __be64 r10; 5797 }; 5798 5799 #define S_FW_VI_CMD_PFN 8 5800 #define M_FW_VI_CMD_PFN 0x7 5801 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 5802 #define G_FW_VI_CMD_PFN(x) \ 5803 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 5804 5805 #define S_FW_VI_CMD_VFN 0 5806 #define M_FW_VI_CMD_VFN 0xff 5807 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 5808 #define G_FW_VI_CMD_VFN(x) \ 5809 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 5810 5811 #define S_FW_VI_CMD_ALLOC 31 5812 #define M_FW_VI_CMD_ALLOC 0x1 5813 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 5814 #define G_FW_VI_CMD_ALLOC(x) \ 5815 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 5816 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 5817 5818 #define S_FW_VI_CMD_FREE 30 5819 #define M_FW_VI_CMD_FREE 0x1 5820 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 5821 #define G_FW_VI_CMD_FREE(x) \ 5822 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 5823 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 5824 5825 #define S_FW_VI_CMD_TYPE 15 5826 #define M_FW_VI_CMD_TYPE 0x1 5827 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 5828 #define G_FW_VI_CMD_TYPE(x) \ 5829 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 5830 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 5831 5832 #define S_FW_VI_CMD_FUNC 12 5833 #define M_FW_VI_CMD_FUNC 0x7 5834 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 5835 #define G_FW_VI_CMD_FUNC(x) \ 5836 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 5837 5838 #define S_FW_VI_CMD_VIID 0 5839 #define M_FW_VI_CMD_VIID 0xfff 5840 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 5841 #define G_FW_VI_CMD_VIID(x) \ 5842 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 5843 5844 #define S_FW_VI_CMD_PORTID 4 5845 #define M_FW_VI_CMD_PORTID 0xf 5846 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 5847 #define G_FW_VI_CMD_PORTID(x) \ 5848 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 5849 5850 #define S_FW_VI_CMD_NORSS 11 5851 #define M_FW_VI_CMD_NORSS 0x1 5852 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 5853 #define G_FW_VI_CMD_NORSS(x) \ 5854 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 5855 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 5856 5857 #define S_FW_VI_CMD_RSSSIZE 0 5858 #define M_FW_VI_CMD_RSSSIZE 0x7ff 5859 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 5860 #define G_FW_VI_CMD_RSSSIZE(x) \ 5861 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 5862 5863 #define S_FW_VI_CMD_IDSIIQ 0 5864 #define M_FW_VI_CMD_IDSIIQ 0x3ff 5865 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 5866 #define G_FW_VI_CMD_IDSIIQ(x) \ 5867 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 5868 5869 #define S_FW_VI_CMD_IDSEIQ 0 5870 #define M_FW_VI_CMD_IDSEIQ 0x3ff 5871 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 5872 #define G_FW_VI_CMD_IDSEIQ(x) \ 5873 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 5874 5875 /* Special VI_MAC command index ids */ 5876 #define FW_VI_MAC_ADD_MAC 0x3FF 5877 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 5878 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 5879 5880 enum fw_vi_mac_smac { 5881 FW_VI_MAC_MPS_TCAM_ENTRY, 5882 FW_VI_MAC_MPS_TCAM_ONLY, 5883 FW_VI_MAC_SMT_ONLY, 5884 FW_VI_MAC_SMT_AND_MPSTCAM 5885 }; 5886 5887 enum fw_vi_mac_result { 5888 FW_VI_MAC_R_SUCCESS, 5889 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 5890 FW_VI_MAC_R_SMAC_FAIL, 5891 FW_VI_MAC_R_F_ACL_CHECK 5892 }; 5893 5894 enum fw_vi_mac_entry_types { 5895 FW_VI_MAC_TYPE_EXACTMAC, 5896 FW_VI_MAC_TYPE_HASHVEC, 5897 FW_VI_MAC_TYPE_RAW, 5898 }; 5899 5900 struct fw_vi_mac_cmd { 5901 __be32 op_to_viid; 5902 __be32 freemacs_to_len16; 5903 union fw_vi_mac { 5904 struct fw_vi_mac_exact { 5905 __be16 valid_to_idx; 5906 __u8 macaddr[6]; 5907 } exact[7]; 5908 struct fw_vi_mac_hash { 5909 __be64 hashvec; 5910 } hash; 5911 struct fw_vi_mac_raw { 5912 __be32 raw_idx_pkd; 5913 __be32 data0_pkd; 5914 __be32 data1[2]; 5915 __be64 data0m_pkd; 5916 __be32 data1m[2]; 5917 } raw; 5918 } u; 5919 }; 5920 5921 #define S_FW_VI_MAC_CMD_VIID 0 5922 #define M_FW_VI_MAC_CMD_VIID 0xfff 5923 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 5924 #define G_FW_VI_MAC_CMD_VIID(x) \ 5925 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 5926 5927 #define S_FW_VI_MAC_CMD_FREEMACS 31 5928 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 5929 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 5930 #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 5931 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 5932 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 5933 5934 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 5935 #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7 5936 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 5937 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \ 5938 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE) 5939 5940 #define S_FW_VI_MAC_CMD_HASHUNIEN 22 5941 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 5942 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 5943 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 5944 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 5945 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 5946 5947 #define S_FW_VI_MAC_CMD_VALID 15 5948 #define M_FW_VI_MAC_CMD_VALID 0x1 5949 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 5950 #define G_FW_VI_MAC_CMD_VALID(x) \ 5951 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 5952 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 5953 5954 #define S_FW_VI_MAC_CMD_PRIO 12 5955 #define M_FW_VI_MAC_CMD_PRIO 0x7 5956 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 5957 #define G_FW_VI_MAC_CMD_PRIO(x) \ 5958 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 5959 5960 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 5961 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 5962 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 5963 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 5964 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 5965 5966 #define S_FW_VI_MAC_CMD_IDX 0 5967 #define M_FW_VI_MAC_CMD_IDX 0x3ff 5968 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 5969 #define G_FW_VI_MAC_CMD_IDX(x) \ 5970 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 5971 5972 #define S_FW_VI_MAC_CMD_RAW_IDX 16 5973 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 5974 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 5975 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 5976 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 5977 5978 #define S_FW_VI_MAC_CMD_DATA0 0 5979 #define M_FW_VI_MAC_CMD_DATA0 0xffff 5980 #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0) 5981 #define G_FW_VI_MAC_CMD_DATA0(x) \ 5982 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0) 5983 5984 /* T4 max MTU supported */ 5985 #define T4_MAX_MTU_SUPPORTED 9600 5986 #define FW_RXMODE_MTU_NO_CHG 65535 5987 5988 struct fw_vi_rxmode_cmd { 5989 __be32 op_to_viid; 5990 __be32 retval_len16; 5991 __be32 mtu_to_vlanexen; 5992 __be32 r4_lo; 5993 }; 5994 5995 #define S_FW_VI_RXMODE_CMD_VIID 0 5996 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 5997 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 5998 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 5999 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 6000 6001 #define S_FW_VI_RXMODE_CMD_MTU 16 6002 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 6003 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 6004 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 6005 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 6006 6007 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 6008 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 6009 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 6010 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 6011 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 6012 6013 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 6014 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 6015 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6016 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 6017 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6018 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 6019 6020 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 6021 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 6022 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6023 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 6024 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6025 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 6026 6027 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 6028 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 6029 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 6030 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 6031 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 6032 6033 struct fw_vi_enable_cmd { 6034 __be32 op_to_viid; 6035 __be32 ien_to_len16; 6036 __be16 blinkdur; 6037 __be16 r3; 6038 __be32 r4; 6039 }; 6040 6041 #define S_FW_VI_ENABLE_CMD_VIID 0 6042 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 6043 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 6044 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 6045 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 6046 6047 #define S_FW_VI_ENABLE_CMD_IEN 31 6048 #define M_FW_VI_ENABLE_CMD_IEN 0x1 6049 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 6050 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 6051 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 6052 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 6053 6054 #define S_FW_VI_ENABLE_CMD_EEN 30 6055 #define M_FW_VI_ENABLE_CMD_EEN 0x1 6056 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 6057 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 6058 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 6059 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 6060 6061 #define S_FW_VI_ENABLE_CMD_LED 29 6062 #define M_FW_VI_ENABLE_CMD_LED 0x1 6063 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 6064 #define G_FW_VI_ENABLE_CMD_LED(x) \ 6065 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 6066 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 6067 6068 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 6069 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 6070 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 6071 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 6072 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 6073 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 6074 6075 /* VI VF stats offset definitions */ 6076 #define VI_VF_NUM_STATS 16 6077 enum fw_vi_stats_vf_index { 6078 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 6079 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 6080 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 6081 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 6082 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 6083 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 6084 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 6085 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 6086 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 6087 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 6088 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 6089 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 6090 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 6091 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 6092 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 6093 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 6094 }; 6095 6096 /* VI PF stats offset definitions */ 6097 #define VI_PF_NUM_STATS 17 6098 enum fw_vi_stats_pf_index { 6099 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 6100 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 6101 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 6102 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 6103 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 6104 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 6105 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 6106 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 6107 FW_VI_PF_STAT_RX_BYTES_IX, 6108 FW_VI_PF_STAT_RX_FRAMES_IX, 6109 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 6110 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 6111 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 6112 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 6113 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 6114 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 6115 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 6116 }; 6117 6118 struct fw_vi_stats_cmd { 6119 __be32 op_to_viid; 6120 __be32 retval_len16; 6121 union fw_vi_stats { 6122 struct fw_vi_stats_ctl { 6123 __be16 nstats_ix; 6124 __be16 r6; 6125 __be32 r7; 6126 __be64 stat0; 6127 __be64 stat1; 6128 __be64 stat2; 6129 __be64 stat3; 6130 __be64 stat4; 6131 __be64 stat5; 6132 } ctl; 6133 struct fw_vi_stats_pf { 6134 __be64 tx_bcast_bytes; 6135 __be64 tx_bcast_frames; 6136 __be64 tx_mcast_bytes; 6137 __be64 tx_mcast_frames; 6138 __be64 tx_ucast_bytes; 6139 __be64 tx_ucast_frames; 6140 __be64 tx_offload_bytes; 6141 __be64 tx_offload_frames; 6142 __be64 rx_pf_bytes; 6143 __be64 rx_pf_frames; 6144 __be64 rx_bcast_bytes; 6145 __be64 rx_bcast_frames; 6146 __be64 rx_mcast_bytes; 6147 __be64 rx_mcast_frames; 6148 __be64 rx_ucast_bytes; 6149 __be64 rx_ucast_frames; 6150 __be64 rx_err_frames; 6151 } pf; 6152 struct fw_vi_stats_vf { 6153 __be64 tx_bcast_bytes; 6154 __be64 tx_bcast_frames; 6155 __be64 tx_mcast_bytes; 6156 __be64 tx_mcast_frames; 6157 __be64 tx_ucast_bytes; 6158 __be64 tx_ucast_frames; 6159 __be64 tx_drop_frames; 6160 __be64 tx_offload_bytes; 6161 __be64 tx_offload_frames; 6162 __be64 rx_bcast_bytes; 6163 __be64 rx_bcast_frames; 6164 __be64 rx_mcast_bytes; 6165 __be64 rx_mcast_frames; 6166 __be64 rx_ucast_bytes; 6167 __be64 rx_ucast_frames; 6168 __be64 rx_err_frames; 6169 } vf; 6170 } u; 6171 }; 6172 6173 #define S_FW_VI_STATS_CMD_VIID 0 6174 #define M_FW_VI_STATS_CMD_VIID 0xfff 6175 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 6176 #define G_FW_VI_STATS_CMD_VIID(x) \ 6177 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 6178 6179 #define S_FW_VI_STATS_CMD_NSTATS 12 6180 #define M_FW_VI_STATS_CMD_NSTATS 0x7 6181 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 6182 #define G_FW_VI_STATS_CMD_NSTATS(x) \ 6183 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 6184 6185 #define S_FW_VI_STATS_CMD_IX 0 6186 #define M_FW_VI_STATS_CMD_IX 0x1f 6187 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 6188 #define G_FW_VI_STATS_CMD_IX(x) \ 6189 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 6190 6191 struct fw_acl_mac_cmd { 6192 __be32 op_to_vfn; 6193 __be32 en_to_len16; 6194 __u8 nmac; 6195 __u8 r3[7]; 6196 __be16 r4; 6197 __u8 macaddr0[6]; 6198 __be16 r5; 6199 __u8 macaddr1[6]; 6200 __be16 r6; 6201 __u8 macaddr2[6]; 6202 __be16 r7; 6203 __u8 macaddr3[6]; 6204 }; 6205 6206 #define S_FW_ACL_MAC_CMD_PFN 8 6207 #define M_FW_ACL_MAC_CMD_PFN 0x7 6208 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 6209 #define G_FW_ACL_MAC_CMD_PFN(x) \ 6210 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 6211 6212 #define S_FW_ACL_MAC_CMD_VFN 0 6213 #define M_FW_ACL_MAC_CMD_VFN 0xff 6214 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 6215 #define G_FW_ACL_MAC_CMD_VFN(x) \ 6216 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 6217 6218 #define S_FW_ACL_MAC_CMD_EN 31 6219 #define M_FW_ACL_MAC_CMD_EN 0x1 6220 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 6221 #define G_FW_ACL_MAC_CMD_EN(x) \ 6222 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 6223 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 6224 6225 struct fw_acl_vlan_cmd { 6226 __be32 op_to_vfn; 6227 __be32 en_to_len16; 6228 __u8 nvlan; 6229 __u8 dropnovlan_fm; 6230 __u8 r3_lo[6]; 6231 __be16 vlanid[16]; 6232 }; 6233 6234 #define S_FW_ACL_VLAN_CMD_PFN 8 6235 #define M_FW_ACL_VLAN_CMD_PFN 0x7 6236 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 6237 #define G_FW_ACL_VLAN_CMD_PFN(x) \ 6238 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 6239 6240 #define S_FW_ACL_VLAN_CMD_VFN 0 6241 #define M_FW_ACL_VLAN_CMD_VFN 0xff 6242 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 6243 #define G_FW_ACL_VLAN_CMD_VFN(x) \ 6244 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 6245 6246 #define S_FW_ACL_VLAN_CMD_EN 31 6247 #define M_FW_ACL_VLAN_CMD_EN 0x1 6248 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 6249 #define G_FW_ACL_VLAN_CMD_EN(x) \ 6250 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 6251 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 6252 6253 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 6254 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 6255 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 6256 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 6257 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 6258 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 6259 6260 #define S_FW_ACL_VLAN_CMD_FM 6 6261 #define M_FW_ACL_VLAN_CMD_FM 0x1 6262 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 6263 #define G_FW_ACL_VLAN_CMD_FM(x) \ 6264 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 6265 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 6266 6267 /* port capabilities bitmap */ 6268 enum fw_port_cap { 6269 FW_PORT_CAP_SPEED_100M = 0x0001, 6270 FW_PORT_CAP_SPEED_1G = 0x0002, 6271 FW_PORT_CAP_SPEED_2_5G = 0x0004, 6272 FW_PORT_CAP_SPEED_10G = 0x0008, 6273 FW_PORT_CAP_SPEED_40G = 0x0010, 6274 FW_PORT_CAP_SPEED_100G = 0x0020, 6275 FW_PORT_CAP_FC_RX = 0x0040, 6276 FW_PORT_CAP_FC_TX = 0x0080, 6277 FW_PORT_CAP_ANEG = 0x0100, 6278 FW_PORT_CAP_MDIX = 0x0200, 6279 FW_PORT_CAP_MDIAUTO = 0x0400, 6280 FW_PORT_CAP_FEC = 0x0800, 6281 FW_PORT_CAP_TECHKR = 0x1000, 6282 FW_PORT_CAP_TECHKX4 = 0x2000, 6283 FW_PORT_CAP_802_3_PAUSE = 0x4000, 6284 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 6285 }; 6286 6287 #define S_FW_PORT_AUXLINFO_MDI 3 6288 #define M_FW_PORT_AUXLINFO_MDI 0x3 6289 #define V_FW_PORT_AUXLINFO_MDI(x) ((x) << S_FW_PORT_AUXLINFO_MDI) 6290 #define G_FW_PORT_AUXLINFO_MDI(x) \ 6291 (((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI) 6292 6293 #define S_FW_PORT_AUXLINFO_KX4 2 6294 #define M_FW_PORT_AUXLINFO_KX4 0x1 6295 #define V_FW_PORT_AUXLINFO_KX4(x) ((x) << S_FW_PORT_AUXLINFO_KX4) 6296 #define G_FW_PORT_AUXLINFO_KX4(x) \ 6297 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 6298 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 6299 6300 #define S_FW_PORT_AUXLINFO_KR 1 6301 #define M_FW_PORT_AUXLINFO_KR 0x1 6302 #define V_FW_PORT_AUXLINFO_KR(x) ((x) << S_FW_PORT_AUXLINFO_KR) 6303 #define G_FW_PORT_AUXLINFO_KR(x) \ 6304 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 6305 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 6306 6307 #define S_FW_PORT_AUXLINFO_FEC 0 6308 #define M_FW_PORT_AUXLINFO_FEC 0x1 6309 #define V_FW_PORT_AUXLINFO_FEC(x) ((x) << S_FW_PORT_AUXLINFO_FEC) 6310 #define G_FW_PORT_AUXLINFO_FEC(x) \ 6311 (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) 6312 #define F_FW_PORT_AUXLINFO_FEC V_FW_PORT_AUXLINFO_FEC(1U) 6313 6314 #define S_FW_PORT_RCAP_AUX 11 6315 #define M_FW_PORT_RCAP_AUX 0x7 6316 #define V_FW_PORT_RCAP_AUX(x) ((x) << S_FW_PORT_RCAP_AUX) 6317 #define G_FW_PORT_RCAP_AUX(x) \ 6318 (((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX) 6319 6320 #define S_FW_PORT_CAP_SPEED 0 6321 #define M_FW_PORT_CAP_SPEED 0x3f 6322 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 6323 #define G_FW_PORT_CAP_SPEED(x) \ 6324 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 6325 6326 #define S_FW_PORT_CAP_FC 6 6327 #define M_FW_PORT_CAP_FC 0x3 6328 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 6329 #define G_FW_PORT_CAP_FC(x) \ 6330 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 6331 6332 #define S_FW_PORT_CAP_ANEG 8 6333 #define M_FW_PORT_CAP_ANEG 0x1 6334 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 6335 #define G_FW_PORT_CAP_ANEG(x) \ 6336 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 6337 6338 #define S_FW_PORT_CAP_802_3 14 6339 #define M_FW_PORT_CAP_802_3 0x3 6340 #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) 6341 #define G_FW_PORT_CAP_802_3(x) \ 6342 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) 6343 6344 enum fw_port_mdi { 6345 FW_PORT_CAP_MDI_UNCHANGED, 6346 FW_PORT_CAP_MDI_AUTO, 6347 FW_PORT_CAP_MDI_F_STRAIGHT, 6348 FW_PORT_CAP_MDI_F_CROSSOVER 6349 }; 6350 6351 #define S_FW_PORT_CAP_MDI 9 6352 #define M_FW_PORT_CAP_MDI 3 6353 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 6354 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 6355 6356 enum fw_port_action { 6357 FW_PORT_ACTION_L1_CFG = 0x0001, 6358 FW_PORT_ACTION_L2_CFG = 0x0002, 6359 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 6360 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 6361 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 6362 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 6363 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 6364 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 6365 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 6366 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 6367 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 6368 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 6369 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 6370 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 6371 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 6372 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 6373 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 6374 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 6375 FW_PORT_ACTION_PHY_RESET = 0x0040, 6376 FW_PORT_ACTION_PMA_RESET = 0x0041, 6377 FW_PORT_ACTION_PCS_RESET = 0x0042, 6378 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 6379 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 6380 FW_PORT_ACTION_AN_RESET = 0x0045, 6381 6382 }; 6383 6384 enum fw_port_l2cfg_ctlbf { 6385 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 6386 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 6387 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 6388 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 6389 FW_PORT_L2_CTLBF_IVLAN = 0x10, 6390 FW_PORT_L2_CTLBF_TXIPG = 0x20, 6391 FW_PORT_L2_CTLBF_MTU = 0x40 6392 }; 6393 6394 enum fw_dcb_app_tlv_sf { 6395 FW_DCB_APP_SF_ETHERTYPE, 6396 FW_DCB_APP_SF_SOCKET_TCP, 6397 FW_DCB_APP_SF_SOCKET_UDP, 6398 FW_DCB_APP_SF_SOCKET_ALL, 6399 }; 6400 6401 enum fw_port_dcb_versions { 6402 FW_PORT_DCB_VER_UNKNOWN, 6403 FW_PORT_DCB_VER_CEE1D0, 6404 FW_PORT_DCB_VER_CEE1D01, 6405 FW_PORT_DCB_VER_IEEE, 6406 FW_PORT_DCB_VER_AUTO=7 6407 }; 6408 6409 enum fw_port_dcb_cfg { 6410 FW_PORT_DCB_CFG_PG = 0x01, 6411 FW_PORT_DCB_CFG_PFC = 0x02, 6412 FW_PORT_DCB_CFG_APPL = 0x04 6413 }; 6414 6415 enum fw_port_dcb_cfg_rc { 6416 FW_PORT_DCB_CFG_SUCCESS = 0x0, 6417 FW_PORT_DCB_CFG_ERROR = 0x1 6418 }; 6419 6420 enum fw_port_dcb_type { 6421 FW_PORT_DCB_TYPE_PGID = 0x00, 6422 FW_PORT_DCB_TYPE_PGRATE = 0x01, 6423 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 6424 FW_PORT_DCB_TYPE_PFC = 0x03, 6425 FW_PORT_DCB_TYPE_APP_ID = 0x04, 6426 FW_PORT_DCB_TYPE_CONTROL = 0x05, 6427 }; 6428 6429 enum fw_port_dcb_feature_state { 6430 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 6431 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 6432 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 6433 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 6434 }; 6435 6436 enum fw_port_diag_ops { 6437 FW_PORT_DIAGS_TEMP = 0x00, 6438 FW_PORT_DIAGS_TX_POWER = 0x01, 6439 FW_PORT_DIAGS_RX_POWER = 0x02, 6440 FW_PORT_DIAGS_TX_DIS = 0x03, 6441 }; 6442 6443 struct fw_port_cmd { 6444 __be32 op_to_portid; 6445 __be32 action_to_len16; 6446 union fw_port { 6447 struct fw_port_l1cfg { 6448 __be32 rcap; 6449 __be32 r; 6450 } l1cfg; 6451 struct fw_port_l2cfg { 6452 __u8 ctlbf; 6453 __u8 ovlan3_to_ivlan0; 6454 __be16 ivlantype; 6455 __be16 txipg_force_pinfo; 6456 __be16 mtu; 6457 __be16 ovlan0mask; 6458 __be16 ovlan0type; 6459 __be16 ovlan1mask; 6460 __be16 ovlan1type; 6461 __be16 ovlan2mask; 6462 __be16 ovlan2type; 6463 __be16 ovlan3mask; 6464 __be16 ovlan3type; 6465 } l2cfg; 6466 struct fw_port_info { 6467 __be32 lstatus_to_modtype; 6468 __be16 pcap; 6469 __be16 acap; 6470 __be16 mtu; 6471 __u8 cbllen; 6472 __u8 auxlinfo; 6473 __u8 dcbxdis_pkd; 6474 __u8 r8_lo; 6475 __be16 lpacap; 6476 __be64 r9; 6477 } info; 6478 struct fw_port_diags { 6479 __u8 diagop; 6480 __u8 r[3]; 6481 __be32 diagval; 6482 } diags; 6483 union fw_port_dcb { 6484 struct fw_port_dcb_pgid { 6485 __u8 type; 6486 __u8 apply_pkd; 6487 __u8 r10_lo[2]; 6488 __be32 pgid; 6489 __be64 r11; 6490 } pgid; 6491 struct fw_port_dcb_pgrate { 6492 __u8 type; 6493 __u8 apply_pkd; 6494 __u8 r10_lo[5]; 6495 __u8 num_tcs_supported; 6496 __u8 pgrate[8]; 6497 __u8 tsa[8]; 6498 } pgrate; 6499 struct fw_port_dcb_priorate { 6500 __u8 type; 6501 __u8 apply_pkd; 6502 __u8 r10_lo[6]; 6503 __u8 strict_priorate[8]; 6504 } priorate; 6505 struct fw_port_dcb_pfc { 6506 __u8 type; 6507 __u8 pfcen; 6508 __u8 r10[5]; 6509 __u8 max_pfc_tcs; 6510 __be64 r11; 6511 } pfc; 6512 struct fw_port_app_priority { 6513 __u8 type; 6514 __u8 r10[2]; 6515 __u8 idx; 6516 __u8 user_prio_map; 6517 __u8 sel_field; 6518 __be16 protocolid; 6519 __be64 r12; 6520 } app_priority; 6521 struct fw_port_dcb_control { 6522 __u8 type; 6523 __u8 all_syncd_pkd; 6524 __be16 dcb_version_to_app_state; 6525 __be32 r11; 6526 __be64 r12; 6527 } control; 6528 } dcb; 6529 } u; 6530 }; 6531 6532 #define S_FW_PORT_CMD_READ 22 6533 #define M_FW_PORT_CMD_READ 0x1 6534 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 6535 #define G_FW_PORT_CMD_READ(x) \ 6536 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 6537 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 6538 6539 #define S_FW_PORT_CMD_PORTID 0 6540 #define M_FW_PORT_CMD_PORTID 0xf 6541 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 6542 #define G_FW_PORT_CMD_PORTID(x) \ 6543 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 6544 6545 #define S_FW_PORT_CMD_ACTION 16 6546 #define M_FW_PORT_CMD_ACTION 0xffff 6547 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 6548 #define G_FW_PORT_CMD_ACTION(x) \ 6549 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 6550 6551 #define S_FW_PORT_CMD_OVLAN3 7 6552 #define M_FW_PORT_CMD_OVLAN3 0x1 6553 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 6554 #define G_FW_PORT_CMD_OVLAN3(x) \ 6555 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 6556 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 6557 6558 #define S_FW_PORT_CMD_OVLAN2 6 6559 #define M_FW_PORT_CMD_OVLAN2 0x1 6560 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 6561 #define G_FW_PORT_CMD_OVLAN2(x) \ 6562 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 6563 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 6564 6565 #define S_FW_PORT_CMD_OVLAN1 5 6566 #define M_FW_PORT_CMD_OVLAN1 0x1 6567 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 6568 #define G_FW_PORT_CMD_OVLAN1(x) \ 6569 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 6570 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 6571 6572 #define S_FW_PORT_CMD_OVLAN0 4 6573 #define M_FW_PORT_CMD_OVLAN0 0x1 6574 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 6575 #define G_FW_PORT_CMD_OVLAN0(x) \ 6576 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 6577 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 6578 6579 #define S_FW_PORT_CMD_IVLAN0 3 6580 #define M_FW_PORT_CMD_IVLAN0 0x1 6581 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 6582 #define G_FW_PORT_CMD_IVLAN0(x) \ 6583 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 6584 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 6585 6586 #define S_FW_PORT_CMD_TXIPG 3 6587 #define M_FW_PORT_CMD_TXIPG 0x1fff 6588 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 6589 #define G_FW_PORT_CMD_TXIPG(x) \ 6590 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 6591 6592 #define S_FW_PORT_CMD_FORCE_PINFO 0 6593 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 6594 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 6595 #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 6596 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 6597 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 6598 6599 #define S_FW_PORT_CMD_LSTATUS 31 6600 #define M_FW_PORT_CMD_LSTATUS 0x1 6601 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 6602 #define G_FW_PORT_CMD_LSTATUS(x) \ 6603 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 6604 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 6605 6606 #define S_FW_PORT_CMD_LSPEED 24 6607 #define M_FW_PORT_CMD_LSPEED 0x3f 6608 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 6609 #define G_FW_PORT_CMD_LSPEED(x) \ 6610 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 6611 6612 #define S_FW_PORT_CMD_TXPAUSE 23 6613 #define M_FW_PORT_CMD_TXPAUSE 0x1 6614 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 6615 #define G_FW_PORT_CMD_TXPAUSE(x) \ 6616 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 6617 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 6618 6619 #define S_FW_PORT_CMD_RXPAUSE 22 6620 #define M_FW_PORT_CMD_RXPAUSE 0x1 6621 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 6622 #define G_FW_PORT_CMD_RXPAUSE(x) \ 6623 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 6624 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 6625 6626 #define S_FW_PORT_CMD_MDIOCAP 21 6627 #define M_FW_PORT_CMD_MDIOCAP 0x1 6628 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 6629 #define G_FW_PORT_CMD_MDIOCAP(x) \ 6630 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 6631 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 6632 6633 #define S_FW_PORT_CMD_MDIOADDR 16 6634 #define M_FW_PORT_CMD_MDIOADDR 0x1f 6635 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 6636 #define G_FW_PORT_CMD_MDIOADDR(x) \ 6637 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 6638 6639 #define S_FW_PORT_CMD_LPTXPAUSE 15 6640 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 6641 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 6642 #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 6643 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 6644 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 6645 6646 #define S_FW_PORT_CMD_LPRXPAUSE 14 6647 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 6648 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 6649 #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 6650 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 6651 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 6652 6653 #define S_FW_PORT_CMD_PTYPE 8 6654 #define M_FW_PORT_CMD_PTYPE 0x1f 6655 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 6656 #define G_FW_PORT_CMD_PTYPE(x) \ 6657 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 6658 6659 #define S_FW_PORT_CMD_LINKDNRC 5 6660 #define M_FW_PORT_CMD_LINKDNRC 0x7 6661 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 6662 #define G_FW_PORT_CMD_LINKDNRC(x) \ 6663 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 6664 6665 #define S_FW_PORT_CMD_MODTYPE 0 6666 #define M_FW_PORT_CMD_MODTYPE 0x1f 6667 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 6668 #define G_FW_PORT_CMD_MODTYPE(x) \ 6669 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 6670 6671 #define S_FW_PORT_CMD_DCBXDIS 7 6672 #define M_FW_PORT_CMD_DCBXDIS 0x1 6673 #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 6674 #define G_FW_PORT_CMD_DCBXDIS(x) \ 6675 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 6676 #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 6677 6678 #define S_FW_PORT_CMD_APPLY 7 6679 #define M_FW_PORT_CMD_APPLY 0x1 6680 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 6681 #define G_FW_PORT_CMD_APPLY(x) \ 6682 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 6683 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 6684 6685 #define S_FW_PORT_CMD_ALL_SYNCD 7 6686 #define M_FW_PORT_CMD_ALL_SYNCD 0x1 6687 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 6688 #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 6689 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 6690 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 6691 6692 #define S_FW_PORT_CMD_DCB_VERSION 12 6693 #define M_FW_PORT_CMD_DCB_VERSION 0x7 6694 #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) 6695 #define G_FW_PORT_CMD_DCB_VERSION(x) \ 6696 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) 6697 6698 #define S_FW_PORT_CMD_PFC_STATE 8 6699 #define M_FW_PORT_CMD_PFC_STATE 0xf 6700 #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 6701 #define G_FW_PORT_CMD_PFC_STATE(x) \ 6702 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 6703 6704 #define S_FW_PORT_CMD_ETS_STATE 4 6705 #define M_FW_PORT_CMD_ETS_STATE 0xf 6706 #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 6707 #define G_FW_PORT_CMD_ETS_STATE(x) \ 6708 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 6709 6710 #define S_FW_PORT_CMD_APP_STATE 0 6711 #define M_FW_PORT_CMD_APP_STATE 0xf 6712 #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 6713 #define G_FW_PORT_CMD_APP_STATE(x) \ 6714 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 6715 6716 /* 6717 * These are configured into the VPD and hence tools that generate 6718 * VPD may use this enumeration. 6719 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 6720 * 6721 * REMEMBER: 6722 * Update the Common Code t4_hw.c:t4_get_port_type_description() 6723 * with any new Firmware Port Technology Types! 6724 */ 6725 enum fw_port_type { 6726 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 6727 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 6728 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 6729 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ 6730 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ 6731 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 6732 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 6733 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 6734 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 6735 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 6736 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 6737 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 6738 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 6739 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 6740 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 6741 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 6742 6743 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 6744 }; 6745 6746 /* These are read from module's EEPROM and determined once the 6747 module is inserted. */ 6748 enum fw_port_module_type { 6749 FW_PORT_MOD_TYPE_NA = 0x0, 6750 FW_PORT_MOD_TYPE_LR = 0x1, 6751 FW_PORT_MOD_TYPE_SR = 0x2, 6752 FW_PORT_MOD_TYPE_ER = 0x3, 6753 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 6754 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 6755 FW_PORT_MOD_TYPE_LRM = 0x6, 6756 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 6757 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 6758 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 6759 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 6760 }; 6761 6762 /* used by FW and tools may use this to generate VPD */ 6763 enum fw_port_mod_sub_type { 6764 FW_PORT_MOD_SUB_TYPE_NA, 6765 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 6766 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 6767 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 6768 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 6769 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 6770 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 6771 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, 6772 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 6773 6774 /* 6775 * The following will never been in the VPD. They are TWINAX cable 6776 * lengths decoded from SFP+ module i2c PROMs. These should almost 6777 * certainly go somewhere else ... 6778 */ 6779 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 6780 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 6781 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 6782 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 6783 }; 6784 6785 /* link down reason codes (3b) */ 6786 enum fw_port_link_dn_rc { 6787 FW_PORT_LINK_DN_RC_NONE, 6788 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 6789 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 6790 FW_PORT_LINK_DN_RESERVED3, 6791 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 6792 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 6793 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 6794 FW_PORT_LINK_DN_RESERVED7 6795 }; 6796 enum fw_port_stats_tx_index { 6797 FW_STAT_TX_PORT_BYTES_IX = 0, 6798 FW_STAT_TX_PORT_FRAMES_IX, 6799 FW_STAT_TX_PORT_BCAST_IX, 6800 FW_STAT_TX_PORT_MCAST_IX, 6801 FW_STAT_TX_PORT_UCAST_IX, 6802 FW_STAT_TX_PORT_ERROR_IX, 6803 FW_STAT_TX_PORT_64B_IX, 6804 FW_STAT_TX_PORT_65B_127B_IX, 6805 FW_STAT_TX_PORT_128B_255B_IX, 6806 FW_STAT_TX_PORT_256B_511B_IX, 6807 FW_STAT_TX_PORT_512B_1023B_IX, 6808 FW_STAT_TX_PORT_1024B_1518B_IX, 6809 FW_STAT_TX_PORT_1519B_MAX_IX, 6810 FW_STAT_TX_PORT_DROP_IX, 6811 FW_STAT_TX_PORT_PAUSE_IX, 6812 FW_STAT_TX_PORT_PPP0_IX, 6813 FW_STAT_TX_PORT_PPP1_IX, 6814 FW_STAT_TX_PORT_PPP2_IX, 6815 FW_STAT_TX_PORT_PPP3_IX, 6816 FW_STAT_TX_PORT_PPP4_IX, 6817 FW_STAT_TX_PORT_PPP5_IX, 6818 FW_STAT_TX_PORT_PPP6_IX, 6819 FW_STAT_TX_PORT_PPP7_IX, 6820 FW_NUM_PORT_TX_STATS 6821 }; 6822 6823 enum fw_port_stat_rx_index { 6824 FW_STAT_RX_PORT_BYTES_IX = 0, 6825 FW_STAT_RX_PORT_FRAMES_IX, 6826 FW_STAT_RX_PORT_BCAST_IX, 6827 FW_STAT_RX_PORT_MCAST_IX, 6828 FW_STAT_RX_PORT_UCAST_IX, 6829 FW_STAT_RX_PORT_MTU_ERROR_IX, 6830 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 6831 FW_STAT_RX_PORT_CRC_ERROR_IX, 6832 FW_STAT_RX_PORT_LEN_ERROR_IX, 6833 FW_STAT_RX_PORT_SYM_ERROR_IX, 6834 FW_STAT_RX_PORT_64B_IX, 6835 FW_STAT_RX_PORT_65B_127B_IX, 6836 FW_STAT_RX_PORT_128B_255B_IX, 6837 FW_STAT_RX_PORT_256B_511B_IX, 6838 FW_STAT_RX_PORT_512B_1023B_IX, 6839 FW_STAT_RX_PORT_1024B_1518B_IX, 6840 FW_STAT_RX_PORT_1519B_MAX_IX, 6841 FW_STAT_RX_PORT_PAUSE_IX, 6842 FW_STAT_RX_PORT_PPP0_IX, 6843 FW_STAT_RX_PORT_PPP1_IX, 6844 FW_STAT_RX_PORT_PPP2_IX, 6845 FW_STAT_RX_PORT_PPP3_IX, 6846 FW_STAT_RX_PORT_PPP4_IX, 6847 FW_STAT_RX_PORT_PPP5_IX, 6848 FW_STAT_RX_PORT_PPP6_IX, 6849 FW_STAT_RX_PORT_PPP7_IX, 6850 FW_STAT_RX_PORT_LESS_64B_IX, 6851 FW_STAT_RX_PORT_MAC_ERROR_IX, 6852 FW_NUM_PORT_RX_STATS 6853 }; 6854 /* port stats */ 6855 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ 6856 FW_NUM_PORT_RX_STATS) 6857 6858 6859 struct fw_port_stats_cmd { 6860 __be32 op_to_portid; 6861 __be32 retval_len16; 6862 union fw_port_stats { 6863 struct fw_port_stats_ctl { 6864 __u8 nstats_bg_bm; 6865 __u8 tx_ix; 6866 __be16 r6; 6867 __be32 r7; 6868 __be64 stat0; 6869 __be64 stat1; 6870 __be64 stat2; 6871 __be64 stat3; 6872 __be64 stat4; 6873 __be64 stat5; 6874 } ctl; 6875 struct fw_port_stats_all { 6876 __be64 tx_bytes; 6877 __be64 tx_frames; 6878 __be64 tx_bcast; 6879 __be64 tx_mcast; 6880 __be64 tx_ucast; 6881 __be64 tx_error; 6882 __be64 tx_64b; 6883 __be64 tx_65b_127b; 6884 __be64 tx_128b_255b; 6885 __be64 tx_256b_511b; 6886 __be64 tx_512b_1023b; 6887 __be64 tx_1024b_1518b; 6888 __be64 tx_1519b_max; 6889 __be64 tx_drop; 6890 __be64 tx_pause; 6891 __be64 tx_ppp0; 6892 __be64 tx_ppp1; 6893 __be64 tx_ppp2; 6894 __be64 tx_ppp3; 6895 __be64 tx_ppp4; 6896 __be64 tx_ppp5; 6897 __be64 tx_ppp6; 6898 __be64 tx_ppp7; 6899 __be64 rx_bytes; 6900 __be64 rx_frames; 6901 __be64 rx_bcast; 6902 __be64 rx_mcast; 6903 __be64 rx_ucast; 6904 __be64 rx_mtu_error; 6905 __be64 rx_mtu_crc_error; 6906 __be64 rx_crc_error; 6907 __be64 rx_len_error; 6908 __be64 rx_sym_error; 6909 __be64 rx_64b; 6910 __be64 rx_65b_127b; 6911 __be64 rx_128b_255b; 6912 __be64 rx_256b_511b; 6913 __be64 rx_512b_1023b; 6914 __be64 rx_1024b_1518b; 6915 __be64 rx_1519b_max; 6916 __be64 rx_pause; 6917 __be64 rx_ppp0; 6918 __be64 rx_ppp1; 6919 __be64 rx_ppp2; 6920 __be64 rx_ppp3; 6921 __be64 rx_ppp4; 6922 __be64 rx_ppp5; 6923 __be64 rx_ppp6; 6924 __be64 rx_ppp7; 6925 __be64 rx_less_64b; 6926 __be64 rx_bg_drop; 6927 __be64 rx_bg_trunc; 6928 } all; 6929 } u; 6930 }; 6931 6932 #define S_FW_PORT_STATS_CMD_NSTATS 4 6933 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 6934 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 6935 #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 6936 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 6937 6938 #define S_FW_PORT_STATS_CMD_BG_BM 0 6939 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 6940 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 6941 #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 6942 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 6943 6944 #define S_FW_PORT_STATS_CMD_TX 7 6945 #define M_FW_PORT_STATS_CMD_TX 0x1 6946 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 6947 #define G_FW_PORT_STATS_CMD_TX(x) \ 6948 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 6949 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 6950 6951 #define S_FW_PORT_STATS_CMD_IX 0 6952 #define M_FW_PORT_STATS_CMD_IX 0x3f 6953 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 6954 #define G_FW_PORT_STATS_CMD_IX(x) \ 6955 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 6956 6957 /* port loopback stats */ 6958 #define FW_NUM_LB_STATS 14 6959 enum fw_port_lb_stats_index { 6960 FW_STAT_LB_PORT_BYTES_IX, 6961 FW_STAT_LB_PORT_FRAMES_IX, 6962 FW_STAT_LB_PORT_BCAST_IX, 6963 FW_STAT_LB_PORT_MCAST_IX, 6964 FW_STAT_LB_PORT_UCAST_IX, 6965 FW_STAT_LB_PORT_ERROR_IX, 6966 FW_STAT_LB_PORT_64B_IX, 6967 FW_STAT_LB_PORT_65B_127B_IX, 6968 FW_STAT_LB_PORT_128B_255B_IX, 6969 FW_STAT_LB_PORT_256B_511B_IX, 6970 FW_STAT_LB_PORT_512B_1023B_IX, 6971 FW_STAT_LB_PORT_1024B_1518B_IX, 6972 FW_STAT_LB_PORT_1519B_MAX_IX, 6973 FW_STAT_LB_PORT_DROP_FRAMES_IX 6974 }; 6975 6976 struct fw_port_lb_stats_cmd { 6977 __be32 op_to_lbport; 6978 __be32 retval_len16; 6979 union fw_port_lb_stats { 6980 struct fw_port_lb_stats_ctl { 6981 __u8 nstats_bg_bm; 6982 __u8 ix_pkd; 6983 __be16 r6; 6984 __be32 r7; 6985 __be64 stat0; 6986 __be64 stat1; 6987 __be64 stat2; 6988 __be64 stat3; 6989 __be64 stat4; 6990 __be64 stat5; 6991 } ctl; 6992 struct fw_port_lb_stats_all { 6993 __be64 tx_bytes; 6994 __be64 tx_frames; 6995 __be64 tx_bcast; 6996 __be64 tx_mcast; 6997 __be64 tx_ucast; 6998 __be64 tx_error; 6999 __be64 tx_64b; 7000 __be64 tx_65b_127b; 7001 __be64 tx_128b_255b; 7002 __be64 tx_256b_511b; 7003 __be64 tx_512b_1023b; 7004 __be64 tx_1024b_1518b; 7005 __be64 tx_1519b_max; 7006 __be64 rx_lb_drop; 7007 __be64 rx_lb_trunc; 7008 } all; 7009 } u; 7010 }; 7011 7012 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 7013 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 7014 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7015 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 7016 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7017 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 7018 7019 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 7020 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 7021 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7022 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 7023 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7024 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 7025 7026 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 7027 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 7028 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 7029 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 7030 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 7031 7032 #define S_FW_PORT_LB_STATS_CMD_IX 0 7033 #define M_FW_PORT_LB_STATS_CMD_IX 0xf 7034 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 7035 #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 7036 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 7037 7038 /* Trace related defines */ 7039 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 7040 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 7041 7042 struct fw_port_trace_cmd { 7043 __be32 op_to_portid; 7044 __be32 retval_len16; 7045 __be16 traceen_to_pciech; 7046 __be16 qnum; 7047 __be32 r5; 7048 }; 7049 7050 #define S_FW_PORT_TRACE_CMD_PORTID 0 7051 #define M_FW_PORT_TRACE_CMD_PORTID 0xf 7052 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 7053 #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 7054 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 7055 7056 #define S_FW_PORT_TRACE_CMD_TRACEEN 15 7057 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 7058 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 7059 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 7060 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 7061 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 7062 7063 #define S_FW_PORT_TRACE_CMD_FLTMODE 14 7064 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 7065 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 7066 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 7067 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 7068 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 7069 7070 #define S_FW_PORT_TRACE_CMD_DUPLEN 13 7071 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 7072 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 7073 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 7074 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 7075 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 7076 7077 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 7078 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 7079 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 7080 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 7081 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 7082 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 7083 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 7084 7085 #define S_FW_PORT_TRACE_CMD_PCIECH 6 7086 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 7087 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 7088 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 7089 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 7090 7091 struct fw_port_trace_mmap_cmd { 7092 __be32 op_to_portid; 7093 __be32 retval_len16; 7094 __be32 fid_to_skipoffset; 7095 __be32 minpktsize_capturemax; 7096 __u8 map[224]; 7097 }; 7098 7099 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 7100 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 7101 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 7102 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 7103 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 7104 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 7105 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 7106 7107 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 7108 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 7109 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 7110 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 7111 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 7112 7113 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 7114 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 7115 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 7116 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 7117 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 7118 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 7119 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 7120 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 7121 7122 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 7123 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 7124 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 7125 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 7126 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 7127 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 7128 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 7129 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 7130 7131 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 7132 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 7133 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 7134 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 7135 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 7136 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 7137 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 7138 7139 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 7140 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 7141 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 7142 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 7143 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 7144 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 7145 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 7146 7147 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 7148 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 7149 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 7150 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 7151 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 7152 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 7153 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 7154 7155 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 7156 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 7157 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 7158 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 7159 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 7160 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 7161 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 7162 7163 enum fw_ptp_subop { 7164 7165 /* none */ 7166 FW_PTP_SC_INIT_TIMER = 0x00, 7167 FW_PTP_SC_TX_TYPE = 0x01, 7168 7169 /* init */ 7170 FW_PTP_SC_RXTIME_STAMP = 0x08, 7171 FW_PTP_SC_RDRX_TYPE = 0x09, 7172 7173 /* ts */ 7174 FW_PTP_SC_ADJ_FREQ = 0x10, 7175 FW_PTP_SC_ADJ_TIME = 0x11, 7176 FW_PTP_SC_ADJ_FTIME = 0x12, 7177 FW_PTP_SC_WALL_CLOCK = 0x13, 7178 FW_PTP_SC_GET_TIME = 0x14, 7179 FW_PTP_SC_SET_TIME = 0x15, 7180 }; 7181 7182 struct fw_ptp_cmd { 7183 __be32 op_to_portid; 7184 __be32 retval_len16; 7185 union fw_ptp { 7186 struct fw_ptp_sc { 7187 __u8 sc; 7188 __u8 r3[7]; 7189 } scmd; 7190 struct fw_ptp_init { 7191 __u8 sc; 7192 __u8 txchan; 7193 __be16 absid; 7194 __be16 mode; 7195 __be16 r3; 7196 } init; 7197 struct fw_ptp_ts { 7198 __u8 sc; 7199 __u8 sign; 7200 __be16 r3; 7201 __be32 ppb; 7202 __be64 tm; 7203 } ts; 7204 } u; 7205 __be64 r3; 7206 }; 7207 7208 #define S_FW_PTP_CMD_PORTID 0 7209 #define M_FW_PTP_CMD_PORTID 0xf 7210 #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) 7211 #define G_FW_PTP_CMD_PORTID(x) \ 7212 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) 7213 7214 struct fw_rss_ind_tbl_cmd { 7215 __be32 op_to_viid; 7216 __be32 retval_len16; 7217 __be16 niqid; 7218 __be16 startidx; 7219 __be32 r3; 7220 __be32 iq0_to_iq2; 7221 __be32 iq3_to_iq5; 7222 __be32 iq6_to_iq8; 7223 __be32 iq9_to_iq11; 7224 __be32 iq12_to_iq14; 7225 __be32 iq15_to_iq17; 7226 __be32 iq18_to_iq20; 7227 __be32 iq21_to_iq23; 7228 __be32 iq24_to_iq26; 7229 __be32 iq27_to_iq29; 7230 __be32 iq30_iq31; 7231 __be32 r15_lo; 7232 }; 7233 7234 #define S_FW_RSS_IND_TBL_CMD_VIID 0 7235 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 7236 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 7237 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 7238 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 7239 7240 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 7241 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 7242 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 7243 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 7244 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 7245 7246 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 7247 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 7248 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 7249 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 7250 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 7251 7252 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 7253 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 7254 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 7255 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 7256 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 7257 7258 #define S_FW_RSS_IND_TBL_CMD_IQ3 20 7259 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 7260 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 7261 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 7262 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 7263 7264 #define S_FW_RSS_IND_TBL_CMD_IQ4 10 7265 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 7266 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 7267 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 7268 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 7269 7270 #define S_FW_RSS_IND_TBL_CMD_IQ5 0 7271 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 7272 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 7273 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 7274 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 7275 7276 #define S_FW_RSS_IND_TBL_CMD_IQ6 20 7277 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 7278 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 7279 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 7280 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 7281 7282 #define S_FW_RSS_IND_TBL_CMD_IQ7 10 7283 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 7284 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 7285 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 7286 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 7287 7288 #define S_FW_RSS_IND_TBL_CMD_IQ8 0 7289 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 7290 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 7291 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 7292 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 7293 7294 #define S_FW_RSS_IND_TBL_CMD_IQ9 20 7295 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 7296 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 7297 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 7298 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 7299 7300 #define S_FW_RSS_IND_TBL_CMD_IQ10 10 7301 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 7302 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 7303 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 7304 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 7305 7306 #define S_FW_RSS_IND_TBL_CMD_IQ11 0 7307 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 7308 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 7309 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 7310 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 7311 7312 #define S_FW_RSS_IND_TBL_CMD_IQ12 20 7313 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 7314 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 7315 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 7316 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 7317 7318 #define S_FW_RSS_IND_TBL_CMD_IQ13 10 7319 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 7320 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 7321 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 7322 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 7323 7324 #define S_FW_RSS_IND_TBL_CMD_IQ14 0 7325 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 7326 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 7327 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 7328 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 7329 7330 #define S_FW_RSS_IND_TBL_CMD_IQ15 20 7331 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 7332 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 7333 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 7334 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 7335 7336 #define S_FW_RSS_IND_TBL_CMD_IQ16 10 7337 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 7338 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 7339 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 7340 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 7341 7342 #define S_FW_RSS_IND_TBL_CMD_IQ17 0 7343 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 7344 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 7345 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 7346 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 7347 7348 #define S_FW_RSS_IND_TBL_CMD_IQ18 20 7349 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 7350 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 7351 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 7352 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 7353 7354 #define S_FW_RSS_IND_TBL_CMD_IQ19 10 7355 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 7356 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 7357 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 7358 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 7359 7360 #define S_FW_RSS_IND_TBL_CMD_IQ20 0 7361 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 7362 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 7363 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 7364 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 7365 7366 #define S_FW_RSS_IND_TBL_CMD_IQ21 20 7367 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 7368 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 7369 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 7370 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 7371 7372 #define S_FW_RSS_IND_TBL_CMD_IQ22 10 7373 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 7374 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 7375 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 7376 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 7377 7378 #define S_FW_RSS_IND_TBL_CMD_IQ23 0 7379 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 7380 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 7381 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 7382 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 7383 7384 #define S_FW_RSS_IND_TBL_CMD_IQ24 20 7385 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 7386 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 7387 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 7388 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 7389 7390 #define S_FW_RSS_IND_TBL_CMD_IQ25 10 7391 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 7392 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 7393 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 7394 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 7395 7396 #define S_FW_RSS_IND_TBL_CMD_IQ26 0 7397 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 7398 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 7399 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 7400 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 7401 7402 #define S_FW_RSS_IND_TBL_CMD_IQ27 20 7403 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 7404 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 7405 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 7406 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 7407 7408 #define S_FW_RSS_IND_TBL_CMD_IQ28 10 7409 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 7410 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 7411 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 7412 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 7413 7414 #define S_FW_RSS_IND_TBL_CMD_IQ29 0 7415 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 7416 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 7417 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 7418 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 7419 7420 #define S_FW_RSS_IND_TBL_CMD_IQ30 20 7421 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 7422 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 7423 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 7424 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 7425 7426 #define S_FW_RSS_IND_TBL_CMD_IQ31 10 7427 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 7428 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 7429 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 7430 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 7431 7432 struct fw_rss_glb_config_cmd { 7433 __be32 op_to_write; 7434 __be32 retval_len16; 7435 union fw_rss_glb_config { 7436 struct fw_rss_glb_config_manual { 7437 __be32 mode_pkd; 7438 __be32 r3; 7439 __be64 r4; 7440 __be64 r5; 7441 } manual; 7442 struct fw_rss_glb_config_basicvirtual { 7443 __be32 mode_pkd; 7444 __be32 synmapen_to_hashtoeplitz; 7445 __be64 r8; 7446 __be64 r9; 7447 } basicvirtual; 7448 } u; 7449 }; 7450 7451 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 7452 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 7453 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 7454 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 7455 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 7456 7457 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 7458 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 7459 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 7460 7461 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 7462 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 7463 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 7464 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 7465 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 7466 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 7467 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 7468 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 7469 7470 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 7471 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 7472 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 7473 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 7474 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 7475 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 7476 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 7477 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 7478 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 7479 7480 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 7481 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 7482 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 7483 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 7484 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 7485 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 7486 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 7487 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 7488 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 7489 7490 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 7491 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 7492 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 7493 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 7494 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 7495 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 7496 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 7497 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 7498 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 7499 7500 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 7501 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 7502 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 7503 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 7504 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 7505 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 7506 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 7507 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 7508 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 7509 7510 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 7511 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 7512 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 7513 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 7514 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 7515 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 7516 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 7517 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 7518 7519 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 7520 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 7521 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 7522 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 7523 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 7524 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 7525 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 7526 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 7527 7528 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 7529 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 7530 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 7531 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 7532 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 7533 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 7534 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 7535 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 7536 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 7537 7538 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 7539 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 7540 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 7541 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 7542 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 7543 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 7544 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 7545 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 7546 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 7547 7548 struct fw_rss_vi_config_cmd { 7549 __be32 op_to_viid; 7550 __be32 retval_len16; 7551 union fw_rss_vi_config { 7552 struct fw_rss_vi_config_manual { 7553 __be64 r3; 7554 __be64 r4; 7555 __be64 r5; 7556 } manual; 7557 struct fw_rss_vi_config_basicvirtual { 7558 __be32 r6; 7559 __be32 defaultq_to_udpen; 7560 __be64 r9; 7561 __be64 r10; 7562 } basicvirtual; 7563 } u; 7564 }; 7565 7566 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 7567 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 7568 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 7569 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 7570 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 7571 7572 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 7573 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 7574 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 7575 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 7576 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 7577 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 7578 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 7579 7580 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 7581 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 7582 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 7583 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 7584 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 7585 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 7586 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 7587 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 7588 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 7589 7590 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 7591 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 7592 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 7593 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 7594 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 7595 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 7596 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 7597 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 7598 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 7599 7600 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 7601 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 7602 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 7603 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 7604 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 7605 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 7606 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 7607 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 7608 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 7609 7610 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 7611 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 7612 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 7613 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 7614 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 7615 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 7616 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 7617 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 7618 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 7619 7620 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 7621 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 7622 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 7623 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 7624 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 7625 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 7626 7627 enum fw_sched_sc { 7628 FW_SCHED_SC_CONFIG = 0, 7629 FW_SCHED_SC_PARAMS = 1, 7630 }; 7631 7632 enum fw_sched_type { 7633 FW_SCHED_TYPE_PKTSCHED = 0, 7634 FW_SCHED_TYPE_STREAMSCHED = 1, 7635 }; 7636 7637 enum fw_sched_params_level { 7638 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 7639 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 7640 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 7641 }; 7642 7643 enum fw_sched_params_mode { 7644 FW_SCHED_PARAMS_MODE_CLASS = 0, 7645 FW_SCHED_PARAMS_MODE_FLOW = 1, 7646 }; 7647 7648 enum fw_sched_params_unit { 7649 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 7650 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 7651 }; 7652 7653 enum fw_sched_params_rate { 7654 FW_SCHED_PARAMS_RATE_REL = 0, 7655 FW_SCHED_PARAMS_RATE_ABS = 1, 7656 }; 7657 7658 struct fw_sched_cmd { 7659 __be32 op_to_write; 7660 __be32 retval_len16; 7661 union fw_sched { 7662 struct fw_sched_config { 7663 __u8 sc; 7664 __u8 type; 7665 __u8 minmaxen; 7666 __u8 r3[5]; 7667 __u8 nclasses[4]; 7668 __be32 r4; 7669 } config; 7670 struct fw_sched_params { 7671 __u8 sc; 7672 __u8 type; 7673 __u8 level; 7674 __u8 mode; 7675 __u8 unit; 7676 __u8 rate; 7677 __u8 ch; 7678 __u8 cl; 7679 __be32 min; 7680 __be32 max; 7681 __be16 weight; 7682 __be16 pktsize; 7683 __be16 burstsize; 7684 __be16 r4; 7685 } params; 7686 } u; 7687 }; 7688 7689 /* 7690 * length of the formatting string 7691 */ 7692 #define FW_DEVLOG_FMT_LEN 192 7693 7694 /* 7695 * maximum number of the formatting string parameters 7696 */ 7697 #define FW_DEVLOG_FMT_PARAMS_NUM 8 7698 7699 /* 7700 * priority levels 7701 */ 7702 enum fw_devlog_level { 7703 FW_DEVLOG_LEVEL_EMERG = 0x0, 7704 FW_DEVLOG_LEVEL_CRIT = 0x1, 7705 FW_DEVLOG_LEVEL_ERR = 0x2, 7706 FW_DEVLOG_LEVEL_NOTICE = 0x3, 7707 FW_DEVLOG_LEVEL_INFO = 0x4, 7708 FW_DEVLOG_LEVEL_DEBUG = 0x5, 7709 FW_DEVLOG_LEVEL_MAX = 0x5, 7710 }; 7711 7712 /* 7713 * facilities that may send a log message 7714 */ 7715 enum fw_devlog_facility { 7716 FW_DEVLOG_FACILITY_CORE = 0x00, 7717 FW_DEVLOG_FACILITY_CF = 0x01, 7718 FW_DEVLOG_FACILITY_SCHED = 0x02, 7719 FW_DEVLOG_FACILITY_TIMER = 0x04, 7720 FW_DEVLOG_FACILITY_RES = 0x06, 7721 FW_DEVLOG_FACILITY_HW = 0x08, 7722 FW_DEVLOG_FACILITY_FLR = 0x10, 7723 FW_DEVLOG_FACILITY_DMAQ = 0x12, 7724 FW_DEVLOG_FACILITY_PHY = 0x14, 7725 FW_DEVLOG_FACILITY_MAC = 0x16, 7726 FW_DEVLOG_FACILITY_PORT = 0x18, 7727 FW_DEVLOG_FACILITY_VI = 0x1A, 7728 FW_DEVLOG_FACILITY_FILTER = 0x1C, 7729 FW_DEVLOG_FACILITY_ACL = 0x1E, 7730 FW_DEVLOG_FACILITY_TM = 0x20, 7731 FW_DEVLOG_FACILITY_QFC = 0x22, 7732 FW_DEVLOG_FACILITY_DCB = 0x24, 7733 FW_DEVLOG_FACILITY_ETH = 0x26, 7734 FW_DEVLOG_FACILITY_OFLD = 0x28, 7735 FW_DEVLOG_FACILITY_RI = 0x2A, 7736 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 7737 FW_DEVLOG_FACILITY_FCOE = 0x2E, 7738 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 7739 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 7740 FW_DEVLOG_FACILITY_CHNET = 0x34, 7741 FW_DEVLOG_FACILITY_COiSCSI = 0x36, 7742 FW_DEVLOG_FACILITY_MAX = 0x38, 7743 }; 7744 7745 /* 7746 * log message format 7747 */ 7748 struct fw_devlog_e { 7749 __be64 timestamp; 7750 __be32 seqno; 7751 __be16 reserved1; 7752 __u8 level; 7753 __u8 facility; 7754 __u8 fmt[FW_DEVLOG_FMT_LEN]; 7755 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 7756 __be32 reserved3[4]; 7757 }; 7758 7759 struct fw_devlog_cmd { 7760 __be32 op_to_write; 7761 __be32 retval_len16; 7762 __u8 level; 7763 __u8 r2[7]; 7764 __be32 memtype_devlog_memaddr16_devlog; 7765 __be32 memsize_devlog; 7766 __be32 r3[2]; 7767 }; 7768 7769 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 7770 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 7771 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 7772 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 7773 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 7774 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 7775 7776 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 7777 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 7778 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 7779 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 7780 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 7781 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 7782 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 7783 7784 enum fw_watchdog_actions { 7785 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 7786 FW_WATCHDOG_ACTION_FLR = 1, 7787 FW_WATCHDOG_ACTION_BYPASS = 2, 7788 FW_WATCHDOG_ACTION_TMPCHK = 3, 7789 FW_WATCHDOG_ACTION_PAUSEOFF = 4, 7790 7791 FW_WATCHDOG_ACTION_MAX = 5, 7792 }; 7793 7794 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 7795 7796 struct fw_watchdog_cmd { 7797 __be32 op_to_vfn; 7798 __be32 retval_len16; 7799 __be32 timeout; 7800 __be32 action; 7801 }; 7802 7803 #define S_FW_WATCHDOG_CMD_PFN 8 7804 #define M_FW_WATCHDOG_CMD_PFN 0x7 7805 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 7806 #define G_FW_WATCHDOG_CMD_PFN(x) \ 7807 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 7808 7809 #define S_FW_WATCHDOG_CMD_VFN 0 7810 #define M_FW_WATCHDOG_CMD_VFN 0xff 7811 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 7812 #define G_FW_WATCHDOG_CMD_VFN(x) \ 7813 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 7814 7815 struct fw_clip_cmd { 7816 __be32 op_to_write; 7817 __be32 alloc_to_len16; 7818 __be64 ip_hi; 7819 __be64 ip_lo; 7820 __be32 r4[2]; 7821 }; 7822 7823 #define S_FW_CLIP_CMD_ALLOC 31 7824 #define M_FW_CLIP_CMD_ALLOC 0x1 7825 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 7826 #define G_FW_CLIP_CMD_ALLOC(x) \ 7827 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 7828 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 7829 7830 #define S_FW_CLIP_CMD_FREE 30 7831 #define M_FW_CLIP_CMD_FREE 0x1 7832 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 7833 #define G_FW_CLIP_CMD_FREE(x) \ 7834 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 7835 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 7836 7837 /****************************************************************************** 7838 * F O i S C S I C O M M A N D s 7839 **************************************/ 7840 7841 #define FW_CHNET_IFACE_ADDR_MAX 3 7842 7843 enum fw_chnet_iface_cmd_subop { 7844 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 7845 7846 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 7847 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 7848 7849 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 7850 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 7851 7852 FW_CHNET_IFACE_CMD_SUBOP_MAX, 7853 }; 7854 7855 struct fw_chnet_iface_cmd { 7856 __be32 op_to_portid; 7857 __be32 retval_len16; 7858 __u8 subop; 7859 __u8 r2[3]; 7860 __be32 ifid_ifstate; 7861 __be16 mtu; 7862 __be16 vlanid; 7863 __be32 r3; 7864 __be16 r4; 7865 __u8 mac[6]; 7866 }; 7867 7868 #define S_FW_CHNET_IFACE_CMD_PORTID 0 7869 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 7870 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 7871 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 7872 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 7873 7874 #define S_FW_CHNET_IFACE_CMD_IFID 8 7875 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 7876 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 7877 #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 7878 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 7879 7880 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 7881 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 7882 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 7883 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 7884 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 7885 7886 struct fw_fcoe_res_info_cmd { 7887 __be32 op_to_read; 7888 __be32 retval_len16; 7889 __be16 e_d_tov; 7890 __be16 r_a_tov_seq; 7891 __be16 r_a_tov_els; 7892 __be16 r_r_tov; 7893 __be32 max_xchgs; 7894 __be32 max_ssns; 7895 __be32 used_xchgs; 7896 __be32 used_ssns; 7897 __be32 max_fcfs; 7898 __be32 max_vnps; 7899 __be32 used_fcfs; 7900 __be32 used_vnps; 7901 }; 7902 7903 struct fw_fcoe_link_cmd { 7904 __be32 op_to_portid; 7905 __be32 retval_len16; 7906 __be32 sub_opcode_fcfi; 7907 __u8 r3; 7908 __u8 lstatus; 7909 __be16 flags; 7910 __u8 r4; 7911 __u8 set_vlan; 7912 __be16 vlan_id; 7913 __be32 vnpi_pkd; 7914 __be16 r6; 7915 __u8 phy_mac[6]; 7916 __u8 vnport_wwnn[8]; 7917 __u8 vnport_wwpn[8]; 7918 }; 7919 7920 #define S_FW_FCOE_LINK_CMD_PORTID 0 7921 #define M_FW_FCOE_LINK_CMD_PORTID 0xf 7922 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 7923 #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 7924 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 7925 7926 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 7927 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 7928 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 7929 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 7930 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 7931 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 7932 7933 #define S_FW_FCOE_LINK_CMD_FCFI 0 7934 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 7935 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 7936 #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 7937 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 7938 7939 #define S_FW_FCOE_LINK_CMD_VNPI 0 7940 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 7941 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 7942 #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 7943 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 7944 7945 struct fw_fcoe_vnp_cmd { 7946 __be32 op_to_fcfi; 7947 __be32 alloc_to_len16; 7948 __be32 gen_wwn_to_vnpi; 7949 __be32 vf_id; 7950 __be16 iqid; 7951 __u8 vnport_mac[6]; 7952 __u8 vnport_wwnn[8]; 7953 __u8 vnport_wwpn[8]; 7954 __u8 cmn_srv_parms[16]; 7955 __u8 clsp_word_0_1[8]; 7956 }; 7957 7958 #define S_FW_FCOE_VNP_CMD_FCFI 0 7959 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 7960 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 7961 #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 7962 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 7963 7964 #define S_FW_FCOE_VNP_CMD_ALLOC 31 7965 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 7966 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 7967 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 7968 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 7969 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 7970 7971 #define S_FW_FCOE_VNP_CMD_FREE 30 7972 #define M_FW_FCOE_VNP_CMD_FREE 0x1 7973 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 7974 #define G_FW_FCOE_VNP_CMD_FREE(x) \ 7975 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 7976 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 7977 7978 #define S_FW_FCOE_VNP_CMD_MODIFY 29 7979 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 7980 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 7981 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 7982 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 7983 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 7984 7985 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 7986 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 7987 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 7988 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 7989 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 7990 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 7991 7992 #define S_FW_FCOE_VNP_CMD_PERSIST 21 7993 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 7994 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 7995 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 7996 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 7997 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 7998 7999 #define S_FW_FCOE_VNP_CMD_VFID_EN 20 8000 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 8001 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 8002 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 8003 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 8004 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 8005 8006 #define S_FW_FCOE_VNP_CMD_VNPI 0 8007 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 8008 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 8009 #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 8010 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 8011 8012 struct fw_fcoe_sparams_cmd { 8013 __be32 op_to_portid; 8014 __be32 retval_len16; 8015 __u8 r3[7]; 8016 __u8 cos; 8017 __u8 lport_wwnn[8]; 8018 __u8 lport_wwpn[8]; 8019 __u8 cmn_srv_parms[16]; 8020 __u8 cls_srv_parms[16]; 8021 }; 8022 8023 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 8024 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 8025 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 8026 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 8027 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 8028 8029 struct fw_fcoe_stats_cmd { 8030 __be32 op_to_flowid; 8031 __be32 free_to_len16; 8032 union fw_fcoe_stats { 8033 struct fw_fcoe_stats_ctl { 8034 __u8 nstats_port; 8035 __u8 port_valid_ix; 8036 __be16 r6; 8037 __be32 r7; 8038 __be64 stat0; 8039 __be64 stat1; 8040 __be64 stat2; 8041 __be64 stat3; 8042 __be64 stat4; 8043 __be64 stat5; 8044 } ctl; 8045 struct fw_fcoe_port_stats { 8046 __be64 tx_bcast_bytes; 8047 __be64 tx_bcast_frames; 8048 __be64 tx_mcast_bytes; 8049 __be64 tx_mcast_frames; 8050 __be64 tx_ucast_bytes; 8051 __be64 tx_ucast_frames; 8052 __be64 tx_drop_frames; 8053 __be64 tx_offload_bytes; 8054 __be64 tx_offload_frames; 8055 __be64 rx_bcast_bytes; 8056 __be64 rx_bcast_frames; 8057 __be64 rx_mcast_bytes; 8058 __be64 rx_mcast_frames; 8059 __be64 rx_ucast_bytes; 8060 __be64 rx_ucast_frames; 8061 __be64 rx_err_frames; 8062 } port_stats; 8063 struct fw_fcoe_fcf_stats { 8064 __be32 fip_tx_bytes; 8065 __be32 fip_tx_fr; 8066 __be64 fcf_ka; 8067 __be64 mcast_adv_rcvd; 8068 __be16 ucast_adv_rcvd; 8069 __be16 sol_sent; 8070 __be16 vlan_req; 8071 __be16 vlan_rpl; 8072 __be16 clr_vlink; 8073 __be16 link_down; 8074 __be16 link_up; 8075 __be16 logo; 8076 __be16 flogi_req; 8077 __be16 flogi_rpl; 8078 __be16 fdisc_req; 8079 __be16 fdisc_rpl; 8080 __be16 fka_prd_chg; 8081 __be16 fc_map_chg; 8082 __be16 vfid_chg; 8083 __u8 no_fka_req; 8084 __u8 no_vnp; 8085 } fcf_stats; 8086 struct fw_fcoe_pcb_stats { 8087 __be64 tx_bytes; 8088 __be64 tx_frames; 8089 __be64 rx_bytes; 8090 __be64 rx_frames; 8091 __be32 vnp_ka; 8092 __be32 unsol_els_rcvd; 8093 __be64 unsol_cmd_rcvd; 8094 __be16 implicit_logo; 8095 __be16 flogi_inv_sparm; 8096 __be16 fdisc_inv_sparm; 8097 __be16 flogi_rjt; 8098 __be16 fdisc_rjt; 8099 __be16 no_ssn; 8100 __be16 mac_flt_fail; 8101 __be16 inv_fr_rcvd; 8102 } pcb_stats; 8103 struct fw_fcoe_scb_stats { 8104 __be64 tx_bytes; 8105 __be64 tx_frames; 8106 __be64 rx_bytes; 8107 __be64 rx_frames; 8108 __be32 host_abrt_req; 8109 __be32 adap_auto_abrt; 8110 __be32 adap_abrt_rsp; 8111 __be32 host_ios_req; 8112 __be16 ssn_offl_ios; 8113 __be16 ssn_not_rdy_ios; 8114 __u8 rx_data_ddp_err; 8115 __u8 ddp_flt_set_err; 8116 __be16 rx_data_fr_err; 8117 __u8 bad_st_abrt_req; 8118 __u8 no_io_abrt_req; 8119 __u8 abort_tmo; 8120 __u8 abort_tmo_2; 8121 __be32 abort_req; 8122 __u8 no_ppod_res_tmo; 8123 __u8 bp_tmo; 8124 __u8 adap_auto_cls; 8125 __u8 no_io_cls_req; 8126 __be32 host_cls_req; 8127 __be64 unsol_cmd_rcvd; 8128 __be32 plogi_req_rcvd; 8129 __be32 prli_req_rcvd; 8130 __be16 logo_req_rcvd; 8131 __be16 prlo_req_rcvd; 8132 __be16 plogi_rjt_rcvd; 8133 __be16 prli_rjt_rcvd; 8134 __be32 adisc_req_rcvd; 8135 __be32 rscn_rcvd; 8136 __be32 rrq_req_rcvd; 8137 __be32 unsol_els_rcvd; 8138 __u8 adisc_rjt_rcvd; 8139 __u8 scr_rjt; 8140 __u8 ct_rjt; 8141 __u8 inval_bls_rcvd; 8142 __be32 ba_rjt_rcvd; 8143 } scb_stats; 8144 } u; 8145 }; 8146 8147 #define S_FW_FCOE_STATS_CMD_FLOWID 0 8148 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 8149 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 8150 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 8151 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 8152 8153 #define S_FW_FCOE_STATS_CMD_FREE 30 8154 #define M_FW_FCOE_STATS_CMD_FREE 0x1 8155 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 8156 #define G_FW_FCOE_STATS_CMD_FREE(x) \ 8157 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 8158 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 8159 8160 #define S_FW_FCOE_STATS_CMD_NSTATS 4 8161 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 8162 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 8163 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 8164 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 8165 8166 #define S_FW_FCOE_STATS_CMD_PORT 0 8167 #define M_FW_FCOE_STATS_CMD_PORT 0x3 8168 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 8169 #define G_FW_FCOE_STATS_CMD_PORT(x) \ 8170 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 8171 8172 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 8173 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 8174 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 8175 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 8176 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 8177 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 8178 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 8179 8180 #define S_FW_FCOE_STATS_CMD_IX 0 8181 #define M_FW_FCOE_STATS_CMD_IX 0x3f 8182 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 8183 #define G_FW_FCOE_STATS_CMD_IX(x) \ 8184 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 8185 8186 struct fw_fcoe_fcf_cmd { 8187 __be32 op_to_fcfi; 8188 __be32 retval_len16; 8189 __be16 priority_pkd; 8190 __u8 mac[6]; 8191 __u8 name_id[8]; 8192 __u8 fabric[8]; 8193 __be16 vf_id; 8194 __be16 max_fcoe_size; 8195 __u8 vlan_id; 8196 __u8 fc_map[3]; 8197 __be32 fka_adv; 8198 __be32 r6; 8199 __u8 r7_hi; 8200 __u8 fpma_to_portid; 8201 __u8 spma_mac[6]; 8202 __be64 r8; 8203 }; 8204 8205 #define S_FW_FCOE_FCF_CMD_FCFI 0 8206 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 8207 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 8208 #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 8209 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 8210 8211 #define S_FW_FCOE_FCF_CMD_PRIORITY 0 8212 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 8213 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 8214 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 8215 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 8216 8217 #define S_FW_FCOE_FCF_CMD_FPMA 6 8218 #define M_FW_FCOE_FCF_CMD_FPMA 0x1 8219 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 8220 #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 8221 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 8222 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 8223 8224 #define S_FW_FCOE_FCF_CMD_SPMA 5 8225 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 8226 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 8227 #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 8228 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 8229 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 8230 8231 #define S_FW_FCOE_FCF_CMD_LOGIN 4 8232 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 8233 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 8234 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 8235 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 8236 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 8237 8238 #define S_FW_FCOE_FCF_CMD_PORTID 0 8239 #define M_FW_FCOE_FCF_CMD_PORTID 0xf 8240 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 8241 #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 8242 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 8243 8244 /****************************************************************************** 8245 * E R R O R a n d D E B U G C O M M A N D s 8246 ******************************************************/ 8247 8248 enum fw_error_type { 8249 FW_ERROR_TYPE_EXCEPTION = 0x0, 8250 FW_ERROR_TYPE_HWMODULE = 0x1, 8251 FW_ERROR_TYPE_WR = 0x2, 8252 FW_ERROR_TYPE_ACL = 0x3, 8253 }; 8254 8255 enum fw_dcb_ieee_locations { 8256 FW_IEEE_LOC_LOCAL, 8257 FW_IEEE_LOC_PEER, 8258 FW_IEEE_LOC_OPERATIONAL, 8259 }; 8260 8261 struct fw_dcb_ieee_cmd { 8262 __be32 op_to_location; 8263 __be32 changed_to_len16; 8264 union fw_dcbx_stats { 8265 struct fw_dcbx_pfc_stats_ieee { 8266 __be32 pfc_mbc_pkd; 8267 __be32 pfc_willing_to_pfc_en; 8268 } dcbx_pfc_stats; 8269 struct fw_dcbx_ets_stats_ieee { 8270 __be32 cbs_to_ets_max_tc; 8271 __be32 pg_table; 8272 __u8 pg_percent[8]; 8273 __u8 tsa[8]; 8274 } dcbx_ets_stats; 8275 struct fw_dcbx_app_stats_ieee { 8276 __be32 num_apps_pkd; 8277 __be32 r6; 8278 __be32 app[4]; 8279 } dcbx_app_stats; 8280 struct fw_dcbx_control { 8281 __be32 multi_peer_invalidated; 8282 __be32 r5_lo; 8283 } dcbx_control; 8284 } u; 8285 }; 8286 8287 #define S_FW_DCB_IEEE_CMD_PORT 8 8288 #define M_FW_DCB_IEEE_CMD_PORT 0x7 8289 #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT) 8290 #define G_FW_DCB_IEEE_CMD_PORT(x) \ 8291 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT) 8292 8293 #define S_FW_DCB_IEEE_CMD_FEATURE 2 8294 #define M_FW_DCB_IEEE_CMD_FEATURE 0x7 8295 #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE) 8296 #define G_FW_DCB_IEEE_CMD_FEATURE(x) \ 8297 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE) 8298 8299 #define S_FW_DCB_IEEE_CMD_LOCATION 0 8300 #define M_FW_DCB_IEEE_CMD_LOCATION 0x3 8301 #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION) 8302 #define G_FW_DCB_IEEE_CMD_LOCATION(x) \ 8303 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION) 8304 8305 #define S_FW_DCB_IEEE_CMD_CHANGED 20 8306 #define M_FW_DCB_IEEE_CMD_CHANGED 0x1 8307 #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED) 8308 #define G_FW_DCB_IEEE_CMD_CHANGED(x) \ 8309 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED) 8310 #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U) 8311 8312 #define S_FW_DCB_IEEE_CMD_RECEIVED 19 8313 #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1 8314 #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED) 8315 #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \ 8316 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED) 8317 #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U) 8318 8319 #define S_FW_DCB_IEEE_CMD_APPLY 18 8320 #define M_FW_DCB_IEEE_CMD_APPLY 0x1 8321 #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY) 8322 #define G_FW_DCB_IEEE_CMD_APPLY(x) \ 8323 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY) 8324 #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U) 8325 8326 #define S_FW_DCB_IEEE_CMD_DISABLED 17 8327 #define M_FW_DCB_IEEE_CMD_DISABLED 0x1 8328 #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED) 8329 #define G_FW_DCB_IEEE_CMD_DISABLED(x) \ 8330 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED) 8331 #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U) 8332 8333 #define S_FW_DCB_IEEE_CMD_MORE 16 8334 #define M_FW_DCB_IEEE_CMD_MORE 0x1 8335 #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE) 8336 #define G_FW_DCB_IEEE_CMD_MORE(x) \ 8337 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE) 8338 #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U) 8339 8340 #define S_FW_DCB_IEEE_CMD_PFC_MBC 0 8341 #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1 8342 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC) 8343 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \ 8344 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC) 8345 #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U) 8346 8347 #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16 8348 #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1 8349 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 8350 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING) 8351 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 8352 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING) 8353 #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U) 8354 8355 #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8 8356 #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff 8357 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC) 8358 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \ 8359 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC) 8360 8361 #define S_FW_DCB_IEEE_CMD_PFC_EN 0 8362 #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff 8363 #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN) 8364 #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \ 8365 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN) 8366 8367 #define S_FW_DCB_IEEE_CMD_CBS 16 8368 #define M_FW_DCB_IEEE_CMD_CBS 0x1 8369 #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS) 8370 #define G_FW_DCB_IEEE_CMD_CBS(x) \ 8371 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS) 8372 #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U) 8373 8374 #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8 8375 #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1 8376 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 8377 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING) 8378 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 8379 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING) 8380 #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U) 8381 8382 #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0 8383 #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff 8384 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC) 8385 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \ 8386 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC) 8387 8388 #define S_FW_DCB_IEEE_CMD_NUM_APPS 0 8389 #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7 8390 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS) 8391 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \ 8392 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS) 8393 8394 #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31 8395 #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1 8396 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER) 8397 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \ 8398 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER) 8399 #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U) 8400 8401 #define S_FW_DCB_IEEE_CMD_INVALIDATED 30 8402 #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1 8403 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 8404 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED) 8405 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 8406 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED) 8407 #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U) 8408 8409 /* Hand-written */ 8410 #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16 8411 #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff 8412 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL) 8413 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \ 8414 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL) 8415 8416 #define S_FW_DCB_IEEE_CMD_APP_SELECT 3 8417 #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7 8418 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT) 8419 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \ 8420 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT) 8421 8422 #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0 8423 #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7 8424 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY) 8425 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \ 8426 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY) 8427 8428 8429 struct fw_error_cmd { 8430 __be32 op_to_type; 8431 __be32 len16_pkd; 8432 union fw_error { 8433 struct fw_error_exception { 8434 __be32 info[6]; 8435 } exception; 8436 struct fw_error_hwmodule { 8437 __be32 regaddr; 8438 __be32 regval; 8439 } hwmodule; 8440 struct fw_error_wr { 8441 __be16 cidx; 8442 __be16 pfn_vfn; 8443 __be32 eqid; 8444 __u8 wrhdr[16]; 8445 } wr; 8446 struct fw_error_acl { 8447 __be16 cidx; 8448 __be16 pfn_vfn; 8449 __be32 eqid; 8450 __be16 mv_pkd; 8451 __u8 val[6]; 8452 __be64 r4; 8453 } acl; 8454 } u; 8455 }; 8456 8457 #define S_FW_ERROR_CMD_FATAL 4 8458 #define M_FW_ERROR_CMD_FATAL 0x1 8459 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 8460 #define G_FW_ERROR_CMD_FATAL(x) \ 8461 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 8462 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 8463 8464 #define S_FW_ERROR_CMD_TYPE 0 8465 #define M_FW_ERROR_CMD_TYPE 0xf 8466 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 8467 #define G_FW_ERROR_CMD_TYPE(x) \ 8468 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 8469 8470 #define S_FW_ERROR_CMD_PFN 8 8471 #define M_FW_ERROR_CMD_PFN 0x7 8472 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 8473 #define G_FW_ERROR_CMD_PFN(x) \ 8474 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 8475 8476 #define S_FW_ERROR_CMD_VFN 0 8477 #define M_FW_ERROR_CMD_VFN 0xff 8478 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 8479 #define G_FW_ERROR_CMD_VFN(x) \ 8480 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 8481 8482 #define S_FW_ERROR_CMD_PFN 8 8483 #define M_FW_ERROR_CMD_PFN 0x7 8484 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 8485 #define G_FW_ERROR_CMD_PFN(x) \ 8486 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 8487 8488 #define S_FW_ERROR_CMD_VFN 0 8489 #define M_FW_ERROR_CMD_VFN 0xff 8490 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 8491 #define G_FW_ERROR_CMD_VFN(x) \ 8492 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 8493 8494 #define S_FW_ERROR_CMD_MV 15 8495 #define M_FW_ERROR_CMD_MV 0x1 8496 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 8497 #define G_FW_ERROR_CMD_MV(x) \ 8498 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 8499 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 8500 8501 struct fw_debug_cmd { 8502 __be32 op_type; 8503 __be32 len16_pkd; 8504 union fw_debug { 8505 struct fw_debug_assert { 8506 __be32 fcid; 8507 __be32 line; 8508 __be32 x; 8509 __be32 y; 8510 __u8 filename_0_7[8]; 8511 __u8 filename_8_15[8]; 8512 __be64 r3; 8513 } assert; 8514 struct fw_debug_prt { 8515 __be16 dprtstridx; 8516 __be16 r3[3]; 8517 __be32 dprtstrparam0; 8518 __be32 dprtstrparam1; 8519 __be32 dprtstrparam2; 8520 __be32 dprtstrparam3; 8521 } prt; 8522 } u; 8523 }; 8524 8525 #define S_FW_DEBUG_CMD_TYPE 0 8526 #define M_FW_DEBUG_CMD_TYPE 0xff 8527 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 8528 #define G_FW_DEBUG_CMD_TYPE(x) \ 8529 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 8530 8531 /****************************************************************************** 8532 * P C I E F W R E G I S T E R 8533 **************************************/ 8534 8535 enum pcie_fw_eval { 8536 PCIE_FW_EVAL_CRASH = 0, 8537 PCIE_FW_EVAL_PREP = 1, 8538 PCIE_FW_EVAL_CONF = 2, 8539 PCIE_FW_EVAL_INIT = 3, 8540 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 8541 PCIE_FW_EVAL_OVERHEAT = 5, 8542 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 8543 }; 8544 8545 /** 8546 * Register definitions for the PCIE_FW register which the firmware uses 8547 * to retain status across RESETs. This register should be considered 8548 * as a READ-ONLY register for Host Software and only to be used to 8549 * track firmware initialization/error state, etc. 8550 */ 8551 #define S_PCIE_FW_ERR 31 8552 #define M_PCIE_FW_ERR 0x1 8553 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 8554 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 8555 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 8556 8557 #define S_PCIE_FW_INIT 30 8558 #define M_PCIE_FW_INIT 0x1 8559 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 8560 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 8561 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 8562 8563 #define S_PCIE_FW_HALT 29 8564 #define M_PCIE_FW_HALT 0x1 8565 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 8566 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 8567 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 8568 8569 #define S_PCIE_FW_EVAL 24 8570 #define M_PCIE_FW_EVAL 0x7 8571 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 8572 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 8573 8574 #define S_PCIE_FW_STAGE 21 8575 #define M_PCIE_FW_STAGE 0x7 8576 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 8577 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 8578 8579 #define S_PCIE_FW_ASYNCNOT_VLD 20 8580 #define M_PCIE_FW_ASYNCNOT_VLD 0x1 8581 #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 8582 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 8583 #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 8584 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 8585 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 8586 8587 #define S_PCIE_FW_ASYNCNOTINT 19 8588 #define M_PCIE_FW_ASYNCNOTINT 0x1 8589 #define V_PCIE_FW_ASYNCNOTINT(x) \ 8590 ((x) << S_PCIE_FW_ASYNCNOTINT) 8591 #define G_PCIE_FW_ASYNCNOTINT(x) \ 8592 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 8593 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 8594 8595 #define S_PCIE_FW_ASYNCNOT 16 8596 #define M_PCIE_FW_ASYNCNOT 0x7 8597 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 8598 #define G_PCIE_FW_ASYNCNOT(x) \ 8599 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 8600 8601 #define S_PCIE_FW_MASTER_VLD 15 8602 #define M_PCIE_FW_MASTER_VLD 0x1 8603 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 8604 #define G_PCIE_FW_MASTER_VLD(x) \ 8605 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 8606 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 8607 8608 #define S_PCIE_FW_MASTER 12 8609 #define M_PCIE_FW_MASTER 0x7 8610 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 8611 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 8612 8613 #define S_PCIE_FW_RESET_VLD 11 8614 #define M_PCIE_FW_RESET_VLD 0x1 8615 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 8616 #define G_PCIE_FW_RESET_VLD(x) \ 8617 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 8618 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 8619 8620 #define S_PCIE_FW_RESET 8 8621 #define M_PCIE_FW_RESET 0x7 8622 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 8623 #define G_PCIE_FW_RESET(x) \ 8624 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 8625 8626 #define S_PCIE_FW_REGISTERED 0 8627 #define M_PCIE_FW_REGISTERED 0xff 8628 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 8629 #define G_PCIE_FW_REGISTERED(x) \ 8630 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 8631 8632 8633 /****************************************************************************** 8634 * P C I E F W P F 0 R E G I S T E R 8635 **********************************************/ 8636 8637 /* 8638 * this register is available as 32-bit of persistent storage (accross 8639 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 8640 * will not write it) 8641 */ 8642 8643 8644 /****************************************************************************** 8645 * P C I E F W P F 7 R E G I S T E R 8646 **********************************************/ 8647 8648 /* 8649 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to 8650 * access the "devlog" which needing to contact firmware. The encoding is 8651 * mostly the same as that returned by the DEVLOG command except for the size 8652 * which is encoded as the number of entries in multiples-1 of 128 here rather 8653 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 8654 * and 15 means 2048. This of course in turn constrains the allowed values 8655 * for the devlog size ... 8656 */ 8657 #define PCIE_FW_PF_DEVLOG 7 8658 8659 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 8660 #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf 8661 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 8662 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) 8663 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 8664 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ 8665 M_PCIE_FW_PF_DEVLOG_NENTRIES128) 8666 8667 #define S_PCIE_FW_PF_DEVLOG_ADDR16 4 8668 #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff 8669 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) 8670 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ 8671 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) 8672 8673 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 8674 #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf 8675 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) 8676 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ 8677 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) 8678 8679 8680 /****************************************************************************** 8681 * B I N A R Y H E A D E R F O R M A T 8682 **********************************************/ 8683 8684 /* 8685 * firmware binary header format 8686 */ 8687 struct fw_hdr { 8688 __u8 ver; 8689 __u8 chip; /* terminator chip family */ 8690 __be16 len512; /* bin length in units of 512-bytes */ 8691 __be32 fw_ver; /* firmware version */ 8692 __be32 tp_microcode_ver; /* tcp processor microcode version */ 8693 __u8 intfver_nic; 8694 __u8 intfver_vnic; 8695 __u8 intfver_ofld; 8696 __u8 intfver_ri; 8697 __u8 intfver_iscsipdu; 8698 __u8 intfver_iscsi; 8699 __u8 intfver_fcoepdu; 8700 __u8 intfver_fcoe; 8701 __u32 reserved2; 8702 __u32 reserved3; 8703 __be32 magic; /* runtime or bootstrap fw */ 8704 __be32 flags; 8705 __be32 reserved6[23]; 8706 }; 8707 8708 enum fw_hdr_chip { 8709 FW_HDR_CHIP_T4, 8710 FW_HDR_CHIP_T5, 8711 FW_HDR_CHIP_T6 8712 }; 8713 8714 #define S_FW_HDR_FW_VER_MAJOR 24 8715 #define M_FW_HDR_FW_VER_MAJOR 0xff 8716 #define V_FW_HDR_FW_VER_MAJOR(x) \ 8717 ((x) << S_FW_HDR_FW_VER_MAJOR) 8718 #define G_FW_HDR_FW_VER_MAJOR(x) \ 8719 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 8720 8721 #define S_FW_HDR_FW_VER_MINOR 16 8722 #define M_FW_HDR_FW_VER_MINOR 0xff 8723 #define V_FW_HDR_FW_VER_MINOR(x) \ 8724 ((x) << S_FW_HDR_FW_VER_MINOR) 8725 #define G_FW_HDR_FW_VER_MINOR(x) \ 8726 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 8727 8728 #define S_FW_HDR_FW_VER_MICRO 8 8729 #define M_FW_HDR_FW_VER_MICRO 0xff 8730 #define V_FW_HDR_FW_VER_MICRO(x) \ 8731 ((x) << S_FW_HDR_FW_VER_MICRO) 8732 #define G_FW_HDR_FW_VER_MICRO(x) \ 8733 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 8734 8735 #define S_FW_HDR_FW_VER_BUILD 0 8736 #define M_FW_HDR_FW_VER_BUILD 0xff 8737 #define V_FW_HDR_FW_VER_BUILD(x) \ 8738 ((x) << S_FW_HDR_FW_VER_BUILD) 8739 #define G_FW_HDR_FW_VER_BUILD(x) \ 8740 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 8741 8742 enum { 8743 T4FW_VERSION_MAJOR = 0x01, 8744 T4FW_VERSION_MINOR = 0x05, 8745 T4FW_VERSION_MICRO = 0x1c, 8746 T4FW_VERSION_BUILD = 0x00, 8747 8748 T5FW_VERSION_MAJOR = 0x01, 8749 T5FW_VERSION_MINOR = 0x05, 8750 T5FW_VERSION_MICRO = 0x1c, 8751 T5FW_VERSION_BUILD = 0x00, 8752 }; 8753 8754 enum { 8755 /* T4 8756 */ 8757 T4FW_HDR_INTFVER_NIC = 0x00, 8758 T4FW_HDR_INTFVER_VNIC = 0x00, 8759 T4FW_HDR_INTFVER_OFLD = 0x00, 8760 T4FW_HDR_INTFVER_RI = 0x00, 8761 T4FW_HDR_INTFVER_ISCSIPDU= 0x00, 8762 T4FW_HDR_INTFVER_ISCSI = 0x00, 8763 T4FW_HDR_INTFVER_FCOEPDU = 0x00, 8764 T4FW_HDR_INTFVER_FCOE = 0x00, 8765 8766 /* T5 8767 */ 8768 T5FW_HDR_INTFVER_NIC = 0x00, 8769 T5FW_HDR_INTFVER_VNIC = 0x00, 8770 T5FW_HDR_INTFVER_OFLD = 0x00, 8771 T5FW_HDR_INTFVER_RI = 0x00, 8772 T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 8773 T5FW_HDR_INTFVER_ISCSI = 0x00, 8774 T5FW_HDR_INTFVER_FCOEPDU= 0x00, 8775 T5FW_HDR_INTFVER_FCOE = 0x00, 8776 8777 /* T6 8778 */ 8779 T6FW_HDR_INTFVER_NIC = 0x00, 8780 T6FW_HDR_INTFVER_VNIC = 0x00, 8781 T6FW_HDR_INTFVER_OFLD = 0x00, 8782 T6FW_HDR_INTFVER_RI = 0x00, 8783 T6FW_HDR_INTFVER_ISCSIPDU= 0x00, 8784 T6FW_HDR_INTFVER_ISCSI = 0x00, 8785 T6FW_HDR_INTFVER_FCOEPDU= 0x00, 8786 T6FW_HDR_INTFVER_FCOE = 0x00, 8787 }; 8788 8789 enum { 8790 FW_HDR_MAGIC_RUNTIME = 0x00000000, 8791 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 8792 }; 8793 8794 enum fw_hdr_flags { 8795 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 8796 }; 8797 8798 /* 8799 * External PHY firmware binary header format 8800 */ 8801 struct fw_ephy_hdr { 8802 __u8 ver; 8803 __u8 reserved; 8804 __be16 len512; /* bin length in units of 512-bytes */ 8805 __be32 magic; 8806 8807 __be16 vendor_id; 8808 __be16 device_id; 8809 __be32 version; 8810 8811 __be32 reserved1[4]; 8812 }; 8813 8814 enum { 8815 FW_EPHY_HDR_MAGIC = 0x65706879, 8816 }; 8817 8818 #endif /* _T4FW_INTERFACE_H_ */ 8819