1 /*- 2 * Copyright (c) 2012-2017 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _T4FW_INTERFACE_H_ 31 #define _T4FW_INTERFACE_H_ 32 33 /****************************************************************************** 34 * R E T U R N V A L U E S 35 ********************************/ 36 37 enum fw_retval { 38 FW_SUCCESS = 0, /* completed successfully */ 39 FW_EPERM = 1, /* operation not permitted */ 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ 48 FW_ENODEV = 19, /* no such device */ 49 FW_EINVAL = 22, /* invalid argument */ 50 FW_ENOSPC = 28, /* no space left on device */ 51 FW_ENOSYS = 38, /* functionality not implemented */ 52 FW_ENODATA = 61, /* no data available */ 53 FW_EPROTO = 71, /* protocol error */ 54 FW_EADDRINUSE = 98, /* address already in use */ 55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 56 FW_ENETDOWN = 100, /* network is down */ 57 FW_ENETUNREACH = 101, /* network is unreachable */ 58 FW_ENOBUFS = 105, /* no buffer space available */ 59 FW_ETIMEDOUT = 110, /* timeout */ 60 FW_EINPROGRESS = 115, /* fw internal */ 61 FW_SCSI_ABORT_REQUESTED = 128, /* */ 62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 63 FW_SCSI_ABORTED = 130, /* */ 64 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 65 FW_ERR_LINK_DOWN = 132, /* */ 66 FW_RDEV_NOT_READY = 133, /* */ 67 FW_ERR_RDEV_LOST = 134, /* */ 68 FW_ERR_RDEV_LOGO = 135, /* */ 69 FW_FCOE_NO_XCHG = 136, /* */ 70 FW_SCSI_RSP_ERR = 137, /* */ 71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 73 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 74 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 76 }; 77 78 /****************************************************************************** 79 * M E M O R Y T Y P E s 80 ******************************/ 81 82 enum fw_memtype { 83 FW_MEMTYPE_EDC0 = 0x0, 84 FW_MEMTYPE_EDC1 = 0x1, 85 FW_MEMTYPE_EXTMEM = 0x2, 86 FW_MEMTYPE_FLASH = 0x4, 87 FW_MEMTYPE_INTERNAL = 0x5, 88 FW_MEMTYPE_EXTMEM1 = 0x6, 89 }; 90 91 /****************************************************************************** 92 * W O R K R E Q U E S T s 93 ********************************/ 94 95 enum fw_wr_opcodes { 96 FW_FRAG_WR = 0x1d, 97 FW_FILTER_WR = 0x02, 98 FW_ULPTX_WR = 0x04, 99 FW_TP_WR = 0x05, 100 FW_ETH_TX_PKT_WR = 0x08, 101 FW_ETH_TX_PKT2_WR = 0x44, 102 FW_ETH_TX_PKTS_WR = 0x09, 103 FW_ETH_TX_PKTS2_WR = 0x78, 104 FW_ETH_TX_EO_WR = 0x1c, 105 FW_EQ_FLUSH_WR = 0x1b, 106 FW_OFLD_CONNECTION_WR = 0x2f, 107 FW_FLOWC_WR = 0x0a, 108 FW_OFLD_TX_DATA_WR = 0x0b, 109 FW_CMD_WR = 0x10, 110 FW_ETH_TX_PKT_VM_WR = 0x11, 111 FW_RI_RES_WR = 0x0c, 112 FW_RI_RDMA_WRITE_WR = 0x14, 113 FW_RI_SEND_WR = 0x15, 114 FW_RI_RDMA_READ_WR = 0x16, 115 FW_RI_RECV_WR = 0x17, 116 FW_RI_BIND_MW_WR = 0x18, 117 FW_RI_FR_NSMR_WR = 0x19, 118 FW_RI_FR_NSMR_TPTE_WR = 0x20, 119 FW_RI_INV_LSTAG_WR = 0x1a, 120 FW_RI_SEND_IMMEDIATE_WR = 0x15, 121 FW_RI_ATOMIC_WR = 0x16, 122 FW_RI_WR = 0x0d, 123 FW_CHNET_IFCONF_WR = 0x6b, 124 FW_RDEV_WR = 0x38, 125 FW_FOISCSI_NODE_WR = 0x60, 126 FW_FOISCSI_CTRL_WR = 0x6a, 127 FW_FOISCSI_CHAP_WR = 0x6c, 128 FW_FCOE_ELS_CT_WR = 0x30, 129 FW_SCSI_WRITE_WR = 0x31, 130 FW_SCSI_READ_WR = 0x32, 131 FW_SCSI_CMD_WR = 0x33, 132 FW_SCSI_ABRT_CLS_WR = 0x34, 133 FW_SCSI_TGT_ACC_WR = 0x35, 134 FW_SCSI_TGT_XMIT_WR = 0x36, 135 FW_SCSI_TGT_RSP_WR = 0x37, 136 FW_POFCOE_TCB_WR = 0x42, 137 FW_POFCOE_ULPTX_WR = 0x43, 138 FW_ISCSI_TX_DATA_WR = 0x45, 139 FW_PTP_TX_PKT_WR = 0x46, 140 FW_TLSTX_DATA_WR = 0x68, 141 FW_TLS_KEYCTX_TX_WR = 0x69, 142 FW_CRYPTO_LOOKASIDE_WR = 0x6d, 143 FW_COiSCSI_TGT_WR = 0x70, 144 FW_COiSCSI_TGT_CONN_WR = 0x71, 145 FW_COiSCSI_TGT_XMIT_WR = 0x72, 146 FW_ISNS_WR = 0x75, 147 FW_ISNS_XMIT_WR = 0x76, 148 FW_FILTER2_WR = 0x77, 149 FW_LASTC2E_WR = 0x80 150 }; 151 152 /* 153 * Generic work request header flit0 154 */ 155 struct fw_wr_hdr { 156 __be32 hi; 157 __be32 lo; 158 }; 159 160 /* work request opcode (hi) 161 */ 162 #define S_FW_WR_OP 24 163 #define M_FW_WR_OP 0xff 164 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 165 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 166 167 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 168 */ 169 #define S_FW_WR_ATOMIC 23 170 #define M_FW_WR_ATOMIC 0x1 171 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 172 #define G_FW_WR_ATOMIC(x) \ 173 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 174 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 175 176 /* flush flag (hi) - firmware flushes flushable work request buffered 177 * in the flow context. 178 */ 179 #define S_FW_WR_FLUSH 22 180 #define M_FW_WR_FLUSH 0x1 181 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 182 #define G_FW_WR_FLUSH(x) \ 183 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 184 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 185 186 /* completion flag (hi) - firmware generates a cpl_fw6_ack 187 */ 188 #define S_FW_WR_COMPL 21 189 #define M_FW_WR_COMPL 0x1 190 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 191 #define G_FW_WR_COMPL(x) \ 192 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 193 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 194 195 196 /* work request immediate data lengh (hi) 197 */ 198 #define S_FW_WR_IMMDLEN 0 199 #define M_FW_WR_IMMDLEN 0xff 200 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 201 #define G_FW_WR_IMMDLEN(x) \ 202 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 203 204 /* egress queue status update to associated ingress queue entry (lo) 205 */ 206 #define S_FW_WR_EQUIQ 31 207 #define M_FW_WR_EQUIQ 0x1 208 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 209 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 210 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 211 212 /* egress queue status update to egress queue status entry (lo) 213 */ 214 #define S_FW_WR_EQUEQ 30 215 #define M_FW_WR_EQUEQ 0x1 216 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 217 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 218 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 219 220 /* flow context identifier (lo) 221 */ 222 #define S_FW_WR_FLOWID 8 223 #define M_FW_WR_FLOWID 0xfffff 224 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 225 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 226 227 /* length in units of 16-bytes (lo) 228 */ 229 #define S_FW_WR_LEN16 0 230 #define M_FW_WR_LEN16 0xff 231 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 232 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 233 234 struct fw_frag_wr { 235 __be32 op_to_fragoff16; 236 __be32 flowid_len16; 237 __be64 r4; 238 }; 239 240 #define S_FW_FRAG_WR_EOF 15 241 #define M_FW_FRAG_WR_EOF 0x1 242 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 243 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 244 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 245 246 #define S_FW_FRAG_WR_FRAGOFF16 8 247 #define M_FW_FRAG_WR_FRAGOFF16 0x7f 248 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 249 #define G_FW_FRAG_WR_FRAGOFF16(x) \ 250 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 251 252 /* valid filter configurations for compressed tuple 253 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 254 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 255 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 256 * OV - Outer VLAN/VNIC_ID, 257 */ 258 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 259 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 260 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 261 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 262 #define HW_TPL_FR_MT_E_PR_T 0x370 263 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 264 #define HW_TPL_FR_MT_E_T_P_FC 0X353 265 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 266 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 267 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 268 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 269 #define HW_TPL_FR_M_E_PR_FC 0X2E1 270 #define HW_TPL_FR_M_E_T_FC 0X2D1 271 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 272 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 273 #define HW_TPL_FR_M_T_IV_FC 0X299 274 #define HW_TPL_FR_M_T_OV_FC 0X295 275 #define HW_TPL_FR_E_PR_T_P 0X272 276 #define HW_TPL_FR_E_PR_T_FC 0X271 277 #define HW_TPL_FR_E_IV_FC 0X249 278 #define HW_TPL_FR_E_OV_FC 0X245 279 #define HW_TPL_FR_PR_T_IV_FC 0X239 280 #define HW_TPL_FR_PR_T_OV_FC 0X235 281 #define HW_TPL_FR_IV_OV_FC 0X20D 282 #define HW_TPL_MT_M_E_PR 0X1E0 283 #define HW_TPL_MT_M_E_T 0X1D0 284 #define HW_TPL_MT_E_PR_T_FC 0X171 285 #define HW_TPL_MT_E_IV 0X148 286 #define HW_TPL_MT_E_OV 0X144 287 #define HW_TPL_MT_PR_T_IV 0X138 288 #define HW_TPL_MT_PR_T_OV 0X134 289 #define HW_TPL_M_E_PR_P 0X0E2 290 #define HW_TPL_M_E_T_P 0X0D2 291 #define HW_TPL_E_PR_T_P_FC 0X073 292 #define HW_TPL_E_IV_P 0X04A 293 #define HW_TPL_E_OV_P 0X046 294 #define HW_TPL_PR_T_IV_P 0X03A 295 #define HW_TPL_PR_T_OV_P 0X036 296 297 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 298 enum fw_filter_wr_cookie { 299 FW_FILTER_WR_SUCCESS, 300 FW_FILTER_WR_FLT_ADDED, 301 FW_FILTER_WR_FLT_DELETED, 302 FW_FILTER_WR_SMT_TBL_FULL, 303 FW_FILTER_WR_EINVAL, 304 }; 305 306 enum fw_filter_wr_nat_mode { 307 FW_FILTER_WR_NATMODE_NONE = 0, 308 FW_FILTER_WR_NATMODE_DIP , 309 FW_FILTER_WR_NATMODE_DIPDP, 310 FW_FILTER_WR_NATMODE_DIPDPSIP, 311 FW_FILTER_WR_NATMODE_DIPDPSP, 312 FW_FILTER_WR_NATMODE_SIPSP, 313 FW_FILTER_WR_NATMODE_DIPSIPSP, 314 FW_FILTER_WR_NATMODE_FOURTUPLE, 315 }; 316 317 struct fw_filter_wr { 318 __be32 op_pkd; 319 __be32 len16_pkd; 320 __be64 r3; 321 __be32 tid_to_iq; 322 __be32 del_filter_to_l2tix; 323 __be16 ethtype; 324 __be16 ethtypem; 325 __u8 frag_to_ovlan_vldm; 326 __u8 smac_sel; 327 __be16 rx_chan_rx_rpl_iq; 328 __be32 maci_to_matchtypem; 329 __u8 ptcl; 330 __u8 ptclm; 331 __u8 ttyp; 332 __u8 ttypm; 333 __be16 ivlan; 334 __be16 ivlanm; 335 __be16 ovlan; 336 __be16 ovlanm; 337 __u8 lip[16]; 338 __u8 lipm[16]; 339 __u8 fip[16]; 340 __u8 fipm[16]; 341 __be16 lp; 342 __be16 lpm; 343 __be16 fp; 344 __be16 fpm; 345 __be16 r7; 346 __u8 sma[6]; 347 }; 348 349 struct fw_filter2_wr { 350 __be32 op_pkd; 351 __be32 len16_pkd; 352 __be64 r3; 353 __be32 tid_to_iq; 354 __be32 del_filter_to_l2tix; 355 __be16 ethtype; 356 __be16 ethtypem; 357 __u8 frag_to_ovlan_vldm; 358 __u8 smac_sel; 359 __be16 rx_chan_rx_rpl_iq; 360 __be32 maci_to_matchtypem; 361 __u8 ptcl; 362 __u8 ptclm; 363 __u8 ttyp; 364 __u8 ttypm; 365 __be16 ivlan; 366 __be16 ivlanm; 367 __be16 ovlan; 368 __be16 ovlanm; 369 __u8 lip[16]; 370 __u8 lipm[16]; 371 __u8 fip[16]; 372 __u8 fipm[16]; 373 __be16 lp; 374 __be16 lpm; 375 __be16 fp; 376 __be16 fpm; 377 __be16 r7; 378 __u8 sma[6]; 379 __u8 r8_hi[2]; 380 __u8 filter_type_swapmac; 381 __u8 natmode_to_ulp_type; 382 __be16 newlport; 383 __be16 newfport; 384 __u8 newlip[16]; 385 __u8 newfip[16]; 386 __be32 natseqcheck; 387 __be32 dip_hit_vni; 388 __be64 r10; 389 __be64 r11; 390 __be64 r12; 391 __be64 r13; 392 }; 393 394 #define S_FW_FILTER_WR_TID 12 395 #define M_FW_FILTER_WR_TID 0xfffff 396 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 397 #define G_FW_FILTER_WR_TID(x) \ 398 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 399 400 #define S_FW_FILTER_WR_RQTYPE 11 401 #define M_FW_FILTER_WR_RQTYPE 0x1 402 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 403 #define G_FW_FILTER_WR_RQTYPE(x) \ 404 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 405 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 406 407 #define S_FW_FILTER_WR_NOREPLY 10 408 #define M_FW_FILTER_WR_NOREPLY 0x1 409 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 410 #define G_FW_FILTER_WR_NOREPLY(x) \ 411 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 412 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 413 414 #define S_FW_FILTER_WR_IQ 0 415 #define M_FW_FILTER_WR_IQ 0x3ff 416 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 417 #define G_FW_FILTER_WR_IQ(x) \ 418 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 419 420 #define S_FW_FILTER_WR_DEL_FILTER 31 421 #define M_FW_FILTER_WR_DEL_FILTER 0x1 422 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 423 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 424 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 425 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 426 427 #define S_FW_FILTER_WR_RPTTID 25 428 #define M_FW_FILTER_WR_RPTTID 0x1 429 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 430 #define G_FW_FILTER_WR_RPTTID(x) \ 431 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 432 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 433 434 #define S_FW_FILTER_WR_DROP 24 435 #define M_FW_FILTER_WR_DROP 0x1 436 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 437 #define G_FW_FILTER_WR_DROP(x) \ 438 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 439 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 440 441 #define S_FW_FILTER_WR_DIRSTEER 23 442 #define M_FW_FILTER_WR_DIRSTEER 0x1 443 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 444 #define G_FW_FILTER_WR_DIRSTEER(x) \ 445 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 446 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 447 448 #define S_FW_FILTER_WR_MASKHASH 22 449 #define M_FW_FILTER_WR_MASKHASH 0x1 450 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 451 #define G_FW_FILTER_WR_MASKHASH(x) \ 452 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 453 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 454 455 #define S_FW_FILTER_WR_DIRSTEERHASH 21 456 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 457 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 458 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 459 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 460 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 461 462 #define S_FW_FILTER_WR_LPBK 20 463 #define M_FW_FILTER_WR_LPBK 0x1 464 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 465 #define G_FW_FILTER_WR_LPBK(x) \ 466 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 467 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 468 469 #define S_FW_FILTER_WR_DMAC 19 470 #define M_FW_FILTER_WR_DMAC 0x1 471 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 472 #define G_FW_FILTER_WR_DMAC(x) \ 473 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 474 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 475 476 #define S_FW_FILTER_WR_SMAC 18 477 #define M_FW_FILTER_WR_SMAC 0x1 478 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 479 #define G_FW_FILTER_WR_SMAC(x) \ 480 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 481 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 482 483 #define S_FW_FILTER_WR_INSVLAN 17 484 #define M_FW_FILTER_WR_INSVLAN 0x1 485 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 486 #define G_FW_FILTER_WR_INSVLAN(x) \ 487 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 488 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 489 490 #define S_FW_FILTER_WR_RMVLAN 16 491 #define M_FW_FILTER_WR_RMVLAN 0x1 492 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 493 #define G_FW_FILTER_WR_RMVLAN(x) \ 494 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 495 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 496 497 #define S_FW_FILTER_WR_HITCNTS 15 498 #define M_FW_FILTER_WR_HITCNTS 0x1 499 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 500 #define G_FW_FILTER_WR_HITCNTS(x) \ 501 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 502 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 503 504 #define S_FW_FILTER_WR_TXCHAN 13 505 #define M_FW_FILTER_WR_TXCHAN 0x3 506 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 507 #define G_FW_FILTER_WR_TXCHAN(x) \ 508 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 509 510 #define S_FW_FILTER_WR_PRIO 12 511 #define M_FW_FILTER_WR_PRIO 0x1 512 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 513 #define G_FW_FILTER_WR_PRIO(x) \ 514 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 515 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 516 517 #define S_FW_FILTER_WR_L2TIX 0 518 #define M_FW_FILTER_WR_L2TIX 0xfff 519 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 520 #define G_FW_FILTER_WR_L2TIX(x) \ 521 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 522 523 #define S_FW_FILTER_WR_FRAG 7 524 #define M_FW_FILTER_WR_FRAG 0x1 525 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 526 #define G_FW_FILTER_WR_FRAG(x) \ 527 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 528 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 529 530 #define S_FW_FILTER_WR_FRAGM 6 531 #define M_FW_FILTER_WR_FRAGM 0x1 532 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 533 #define G_FW_FILTER_WR_FRAGM(x) \ 534 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 535 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 536 537 #define S_FW_FILTER_WR_IVLAN_VLD 5 538 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 539 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 540 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 541 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 542 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 543 544 #define S_FW_FILTER_WR_OVLAN_VLD 4 545 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 546 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 547 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 548 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 549 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 550 551 #define S_FW_FILTER_WR_IVLAN_VLDM 3 552 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 553 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 554 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 555 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 556 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 557 558 #define S_FW_FILTER_WR_OVLAN_VLDM 2 559 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 560 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 561 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 562 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 563 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 564 565 #define S_FW_FILTER_WR_RX_CHAN 15 566 #define M_FW_FILTER_WR_RX_CHAN 0x1 567 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 568 #define G_FW_FILTER_WR_RX_CHAN(x) \ 569 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 570 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 571 572 #define S_FW_FILTER_WR_RX_RPL_IQ 0 573 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 574 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 575 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 576 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 577 578 #define S_FW_FILTER2_WR_FILTER_TYPE 1 579 #define M_FW_FILTER2_WR_FILTER_TYPE 0x1 580 #define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE) 581 #define G_FW_FILTER2_WR_FILTER_TYPE(x) \ 582 (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE) 583 #define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U) 584 585 #define S_FW_FILTER2_WR_SWAPMAC 0 586 #define M_FW_FILTER2_WR_SWAPMAC 0x1 587 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) 588 #define G_FW_FILTER2_WR_SWAPMAC(x) \ 589 (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC) 590 #define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U) 591 592 #define S_FW_FILTER2_WR_NATMODE 5 593 #define M_FW_FILTER2_WR_NATMODE 0x7 594 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 595 #define G_FW_FILTER2_WR_NATMODE(x) \ 596 (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE) 597 598 #define S_FW_FILTER2_WR_NATFLAGCHECK 4 599 #define M_FW_FILTER2_WR_NATFLAGCHECK 0x1 600 #define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK) 601 #define G_FW_FILTER2_WR_NATFLAGCHECK(x) \ 602 (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK) 603 #define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U) 604 605 #define S_FW_FILTER2_WR_ULP_TYPE 0 606 #define M_FW_FILTER2_WR_ULP_TYPE 0xf 607 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 608 #define G_FW_FILTER2_WR_ULP_TYPE(x) \ 609 (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE) 610 611 #define S_FW_FILTER2_WR_DIP_HIT 24 612 #define M_FW_FILTER2_WR_DIP_HIT 0x1 613 #define V_FW_FILTER2_WR_DIP_HIT(x) ((x) << S_FW_FILTER2_WR_DIP_HIT) 614 #define G_FW_FILTER2_WR_DIP_HIT(x) \ 615 (((x) >> S_FW_FILTER2_WR_DIP_HIT) & M_FW_FILTER2_WR_DIP_HIT) 616 #define F_FW_FILTER2_WR_DIP_HIT V_FW_FILTER2_WR_DIP_HIT(1U) 617 618 #define S_FW_FILTER2_WR_VNI 0 619 #define M_FW_FILTER2_WR_VNI 0xffffff 620 #define V_FW_FILTER2_WR_VNI(x) ((x) << S_FW_FILTER2_WR_VNI) 621 #define G_FW_FILTER2_WR_VNI(x) \ 622 (((x) >> S_FW_FILTER2_WR_VNI) & M_FW_FILTER2_WR_VNI) 623 624 #define S_FW_FILTER_WR_MACI 23 625 #define M_FW_FILTER_WR_MACI 0x1ff 626 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 627 #define G_FW_FILTER_WR_MACI(x) \ 628 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 629 630 #define S_FW_FILTER_WR_MACIM 14 631 #define M_FW_FILTER_WR_MACIM 0x1ff 632 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 633 #define G_FW_FILTER_WR_MACIM(x) \ 634 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 635 636 #define S_FW_FILTER_WR_FCOE 13 637 #define M_FW_FILTER_WR_FCOE 0x1 638 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 639 #define G_FW_FILTER_WR_FCOE(x) \ 640 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 641 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 642 643 #define S_FW_FILTER_WR_FCOEM 12 644 #define M_FW_FILTER_WR_FCOEM 0x1 645 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 646 #define G_FW_FILTER_WR_FCOEM(x) \ 647 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 648 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 649 650 #define S_FW_FILTER_WR_PORT 9 651 #define M_FW_FILTER_WR_PORT 0x7 652 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 653 #define G_FW_FILTER_WR_PORT(x) \ 654 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 655 656 #define S_FW_FILTER_WR_PORTM 6 657 #define M_FW_FILTER_WR_PORTM 0x7 658 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 659 #define G_FW_FILTER_WR_PORTM(x) \ 660 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 661 662 #define S_FW_FILTER_WR_MATCHTYPE 3 663 #define M_FW_FILTER_WR_MATCHTYPE 0x7 664 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 665 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 666 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 667 668 #define S_FW_FILTER_WR_MATCHTYPEM 0 669 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 670 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 671 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 672 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 673 674 struct fw_ulptx_wr { 675 __be32 op_to_compl; 676 __be32 flowid_len16; 677 __u64 cookie; 678 }; 679 680 struct fw_tp_wr { 681 __be32 op_to_immdlen; 682 __be32 flowid_len16; 683 __u64 cookie; 684 }; 685 686 struct fw_eth_tx_pkt_wr { 687 __be32 op_immdlen; 688 __be32 equiq_to_len16; 689 __be64 r3; 690 }; 691 692 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 693 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 694 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 695 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 696 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 697 698 struct fw_eth_tx_pkt2_wr { 699 __be32 op_immdlen; 700 __be32 equiq_to_len16; 701 __be32 r3; 702 __be32 L4ChkDisable_to_IpHdrLen; 703 }; 704 705 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 706 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 707 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 708 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 709 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 710 711 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 712 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 713 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 714 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 715 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 716 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 717 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 718 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 719 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 720 721 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 722 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 723 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 724 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 725 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 726 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 727 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 728 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 729 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 730 731 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 732 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 733 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 734 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 735 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 736 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 737 738 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 739 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 740 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 741 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 742 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 743 744 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 745 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 746 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 747 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 748 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 749 750 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 751 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 752 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 753 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 754 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 755 756 struct fw_eth_tx_pkts_wr { 757 __be32 op_pkd; 758 __be32 equiq_to_len16; 759 __be32 r3; 760 __be16 plen; 761 __u8 npkt; 762 __u8 type; 763 }; 764 765 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 766 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 767 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 768 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 769 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 770 771 struct fw_eth_tx_pkt_ptp_wr { 772 __be32 op_immdlen; 773 __be32 equiq_to_len16; 774 __be64 r3; 775 }; 776 777 enum fw_eth_tx_eo_type { 778 FW_ETH_TX_EO_TYPE_UDPSEG, 779 FW_ETH_TX_EO_TYPE_TCPSEG, 780 FW_ETH_TX_EO_TYPE_NVGRESEG, 781 FW_ETH_TX_EO_TYPE_VXLANSEG, 782 FW_ETH_TX_EO_TYPE_GENEVESEG, 783 }; 784 785 struct fw_eth_tx_eo_wr { 786 __be32 op_immdlen; 787 __be32 equiq_to_len16; 788 __be64 r3; 789 union fw_eth_tx_eo { 790 struct fw_eth_tx_eo_udpseg { 791 __u8 type; 792 __u8 ethlen; 793 __be16 iplen; 794 __u8 udplen; 795 __u8 rtplen; 796 __be16 r4; 797 __be16 mss; 798 __be16 schedpktsize; 799 __be32 plen; 800 } udpseg; 801 struct fw_eth_tx_eo_tcpseg { 802 __u8 type; 803 __u8 ethlen; 804 __be16 iplen; 805 __u8 tcplen; 806 __u8 tsclk_tsoff; 807 __be16 r4; 808 __be16 mss; 809 __be16 r5; 810 __be32 plen; 811 } tcpseg; 812 struct fw_eth_tx_eo_nvgreseg { 813 __u8 type; 814 __u8 iphdroffout; 815 __be16 grehdroff; 816 __be16 iphdroffin; 817 __be16 tcphdroffin; 818 __be16 mss; 819 __be16 r4; 820 __be32 plen; 821 } nvgreseg; 822 struct fw_eth_tx_eo_vxlanseg { 823 __u8 type; 824 __u8 iphdroffout; 825 __be16 vxlanhdroff; 826 __be16 iphdroffin; 827 __be16 tcphdroffin; 828 __be16 mss; 829 __be16 r4; 830 __be32 plen; 831 832 } vxlanseg; 833 struct fw_eth_tx_eo_geneveseg { 834 __u8 type; 835 __u8 iphdroffout; 836 __be16 genevehdroff; 837 __be16 iphdroffin; 838 __be16 tcphdroffin; 839 __be16 mss; 840 __be16 r4; 841 __be32 plen; 842 } geneveseg; 843 } u; 844 }; 845 846 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0 847 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 848 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 849 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 850 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 851 852 #define S_FW_ETH_TX_EO_WR_TSCLK 6 853 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3 854 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 855 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 856 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 857 858 #define S_FW_ETH_TX_EO_WR_TSOFF 0 859 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 860 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 861 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 862 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 863 864 struct fw_eq_flush_wr { 865 __u8 opcode; 866 __u8 r1[3]; 867 __be32 equiq_to_len16; 868 __be64 r3; 869 }; 870 871 struct fw_ofld_connection_wr { 872 __be32 op_compl; 873 __be32 len16_pkd; 874 __u64 cookie; 875 __be64 r2; 876 __be64 r3; 877 struct fw_ofld_connection_le { 878 __be32 version_cpl; 879 __be32 filter; 880 __be32 r1; 881 __be16 lport; 882 __be16 pport; 883 union fw_ofld_connection_leip { 884 struct fw_ofld_connection_le_ipv4 { 885 __be32 pip; 886 __be32 lip; 887 __be64 r0; 888 __be64 r1; 889 __be64 r2; 890 } ipv4; 891 struct fw_ofld_connection_le_ipv6 { 892 __be64 pip_hi; 893 __be64 pip_lo; 894 __be64 lip_hi; 895 __be64 lip_lo; 896 } ipv6; 897 } u; 898 } le; 899 struct fw_ofld_connection_tcb { 900 __be32 t_state_to_astid; 901 __be16 cplrxdataack_cplpassacceptrpl; 902 __be16 rcv_adv; 903 __be32 rcv_nxt; 904 __be32 tx_max; 905 __be64 opt0; 906 __be32 opt2; 907 __be32 r1; 908 __be64 r2; 909 __be64 r3; 910 } tcb; 911 }; 912 913 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 914 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 915 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 916 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 917 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 918 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 919 M_FW_OFLD_CONNECTION_WR_VERSION) 920 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 921 922 #define S_FW_OFLD_CONNECTION_WR_CPL 30 923 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 924 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 925 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 926 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 927 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 928 929 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 930 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 931 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 932 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 933 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 934 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 935 M_FW_OFLD_CONNECTION_WR_T_STATE) 936 937 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 938 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 939 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 940 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 941 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 942 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 943 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 944 945 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 946 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 947 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 948 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 949 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 950 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 951 952 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 953 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 954 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 955 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 956 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 957 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 958 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 959 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 960 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 961 962 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 963 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 964 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 965 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 966 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 967 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 968 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 969 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 970 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 971 972 enum fw_flowc_mnem_tcpstate { 973 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 974 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 975 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 976 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 977 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 978 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 979 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 980 * will resend FIN - equiv ESTAB 981 */ 982 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 983 * will resend FIN but have 984 * received FIN 985 */ 986 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 987 * will resend FIN but have 988 * received FIN 989 */ 990 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 991 * waiting for FIN 992 */ 993 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 994 }; 995 996 enum fw_flowc_mnem_eostate { 997 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 998 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 999 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 1000 * outstanding payload 1001 */ 1002 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 1003 * discarding outstanding payload 1004 */ 1005 }; 1006 1007 enum fw_flowc_mnem { 1008 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 1009 FW_FLOWC_MNEM_CH = 1, 1010 FW_FLOWC_MNEM_PORT = 2, 1011 FW_FLOWC_MNEM_IQID = 3, 1012 FW_FLOWC_MNEM_SNDNXT = 4, 1013 FW_FLOWC_MNEM_RCVNXT = 5, 1014 FW_FLOWC_MNEM_SNDBUF = 6, 1015 FW_FLOWC_MNEM_MSS = 7, 1016 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 1017 FW_FLOWC_MNEM_TCPSTATE = 9, 1018 FW_FLOWC_MNEM_EOSTATE = 10, 1019 FW_FLOWC_MNEM_SCHEDCLASS = 11, 1020 FW_FLOWC_MNEM_DCBPRIO = 12, 1021 FW_FLOWC_MNEM_SND_SCALE = 13, 1022 FW_FLOWC_MNEM_RCV_SCALE = 14, 1023 FW_FLOWC_MNEM_ULP_MODE = 15, 1024 FW_FLOWC_MNEM_MAX = 16, 1025 }; 1026 1027 struct fw_flowc_mnemval { 1028 __u8 mnemonic; 1029 __u8 r4[3]; 1030 __be32 val; 1031 }; 1032 1033 struct fw_flowc_wr { 1034 __be32 op_to_nparams; 1035 __be32 flowid_len16; 1036 #ifndef C99_NOT_SUPPORTED 1037 struct fw_flowc_mnemval mnemval[0]; 1038 #endif 1039 }; 1040 1041 #define S_FW_FLOWC_WR_NPARAMS 0 1042 #define M_FW_FLOWC_WR_NPARAMS 0xff 1043 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 1044 #define G_FW_FLOWC_WR_NPARAMS(x) \ 1045 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 1046 1047 struct fw_ofld_tx_data_wr { 1048 __be32 op_to_immdlen; 1049 __be32 flowid_len16; 1050 __be32 plen; 1051 __be32 lsodisable_to_flags; 1052 }; 1053 1054 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 1055 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 1056 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1057 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 1058 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1059 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 1060 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 1061 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 1062 1063 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 1064 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 1065 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1066 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1067 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1068 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1069 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 1070 1071 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 1072 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 1073 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1074 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1075 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1076 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 1077 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1078 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 1079 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 1080 1081 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0 1082 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 1083 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 1084 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 1085 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 1086 1087 1088 /* Use fw_ofld_tx_data_wr structure */ 1089 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 1090 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 1091 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1092 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1093 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1094 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1095 1096 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 1097 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 1098 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1099 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1100 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1101 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 1102 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1103 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 1104 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 1105 1106 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 1107 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 1108 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1109 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1110 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1111 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 1112 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1113 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 1114 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1115 1116 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1117 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1118 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1119 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1120 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1121 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1122 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1123 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1124 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1125 1126 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1127 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1128 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1129 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1130 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1131 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1132 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1133 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1134 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1135 1136 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1137 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1138 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1139 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1140 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1141 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1142 1143 struct fw_cmd_wr { 1144 __be32 op_dma; 1145 __be32 len16_pkd; 1146 __be64 cookie_daddr; 1147 }; 1148 1149 #define S_FW_CMD_WR_DMA 17 1150 #define M_FW_CMD_WR_DMA 0x1 1151 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1152 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1153 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1154 1155 struct fw_eth_tx_pkt_vm_wr { 1156 __be32 op_immdlen; 1157 __be32 equiq_to_len16; 1158 __be32 r3[2]; 1159 __u8 ethmacdst[6]; 1160 __u8 ethmacsrc[6]; 1161 __be16 ethtype; 1162 __be16 vlantci; 1163 }; 1164 1165 /****************************************************************************** 1166 * R I W O R K R E Q U E S T s 1167 **************************************/ 1168 1169 enum fw_ri_wr_opcode { 1170 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1171 FW_RI_READ_REQ = 0x1, 1172 FW_RI_READ_RESP = 0x2, 1173 FW_RI_SEND = 0x3, 1174 FW_RI_SEND_WITH_INV = 0x4, 1175 FW_RI_SEND_WITH_SE = 0x5, 1176 FW_RI_SEND_WITH_SE_INV = 0x6, 1177 FW_RI_TERMINATE = 0x7, 1178 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1179 FW_RI_BIND_MW = 0x9, 1180 FW_RI_FAST_REGISTER = 0xa, 1181 FW_RI_LOCAL_INV = 0xb, 1182 FW_RI_QP_MODIFY = 0xc, 1183 FW_RI_BYPASS = 0xd, 1184 FW_RI_RECEIVE = 0xe, 1185 #if 0 1186 FW_RI_SEND_IMMEDIATE = 0x8, 1187 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1188 FW_RI_ATOMIC_REQUEST = 0xa, 1189 FW_RI_ATOMIC_RESPONSE = 0xb, 1190 1191 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1192 FW_RI_FAST_REGISTER = 0xd, 1193 FW_RI_LOCAL_INV = 0xe, 1194 #endif 1195 FW_RI_SGE_EC_CR_RETURN = 0xf 1196 }; 1197 1198 enum fw_ri_wr_flags { 1199 FW_RI_COMPLETION_FLAG = 0x01, 1200 FW_RI_NOTIFICATION_FLAG = 0x02, 1201 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1202 FW_RI_READ_FENCE_FLAG = 0x08, 1203 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1204 FW_RI_RDMA_READ_INVALIDATE = 0x20 1205 }; 1206 1207 enum fw_ri_mpa_attrs { 1208 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1209 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1210 FW_RI_MPA_CRC_ENABLE = 0x04, 1211 FW_RI_MPA_IETF_ENABLE = 0x08 1212 }; 1213 1214 enum fw_ri_qp_caps { 1215 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1216 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1217 FW_RI_QP_BIND_ENABLE = 0x04, 1218 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1219 FW_RI_QP_STAG0_ENABLE = 0x10, 1220 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1221 }; 1222 1223 enum fw_ri_addr_type { 1224 FW_RI_ZERO_BASED_TO = 0x00, 1225 FW_RI_VA_BASED_TO = 0x01 1226 }; 1227 1228 enum fw_ri_mem_perms { 1229 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1230 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1231 FW_RI_MEM_ACCESS_REM = 0x03, 1232 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1233 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1234 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1235 }; 1236 1237 enum fw_ri_stag_type { 1238 FW_RI_STAG_NSMR = 0x00, 1239 FW_RI_STAG_SMR = 0x01, 1240 FW_RI_STAG_MW = 0x02, 1241 FW_RI_STAG_MW_RELAXED = 0x03 1242 }; 1243 1244 enum fw_ri_data_op { 1245 FW_RI_DATA_IMMD = 0x81, 1246 FW_RI_DATA_DSGL = 0x82, 1247 FW_RI_DATA_ISGL = 0x83 1248 }; 1249 1250 enum fw_ri_sgl_depth { 1251 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1252 FW_RI_SGL_DEPTH_MAX_RQ = 4 1253 }; 1254 1255 enum fw_ri_cqe_err { 1256 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1257 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1258 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1259 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1260 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1261 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1262 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1263 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1264 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1265 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1266 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1267 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1268 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1269 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1270 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1271 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1272 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1273 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1274 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1275 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1276 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1277 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1278 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1279 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1280 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1281 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1282 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1283 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1284 1285 }; 1286 1287 struct fw_ri_dsge_pair { 1288 __be32 len[2]; 1289 __be64 addr[2]; 1290 }; 1291 1292 struct fw_ri_dsgl { 1293 __u8 op; 1294 __u8 r1; 1295 __be16 nsge; 1296 __be32 len0; 1297 __be64 addr0; 1298 #ifndef C99_NOT_SUPPORTED 1299 struct fw_ri_dsge_pair sge[0]; 1300 #endif 1301 }; 1302 1303 struct fw_ri_sge { 1304 __be32 stag; 1305 __be32 len; 1306 __be64 to; 1307 }; 1308 1309 struct fw_ri_isgl { 1310 __u8 op; 1311 __u8 r1; 1312 __be16 nsge; 1313 __be32 r2; 1314 #ifndef C99_NOT_SUPPORTED 1315 struct fw_ri_sge sge[0]; 1316 #endif 1317 }; 1318 1319 struct fw_ri_immd { 1320 __u8 op; 1321 __u8 r1; 1322 __be16 r2; 1323 __be32 immdlen; 1324 #ifndef C99_NOT_SUPPORTED 1325 __u8 data[0]; 1326 #endif 1327 }; 1328 1329 struct fw_ri_tpte { 1330 __be32 valid_to_pdid; 1331 __be32 locread_to_qpid; 1332 __be32 nosnoop_pbladdr; 1333 __be32 len_lo; 1334 __be32 va_hi; 1335 __be32 va_lo_fbo; 1336 __be32 dca_mwbcnt_pstag; 1337 __be32 len_hi; 1338 }; 1339 1340 #define S_FW_RI_TPTE_VALID 31 1341 #define M_FW_RI_TPTE_VALID 0x1 1342 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1343 #define G_FW_RI_TPTE_VALID(x) \ 1344 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1345 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1346 1347 #define S_FW_RI_TPTE_STAGKEY 23 1348 #define M_FW_RI_TPTE_STAGKEY 0xff 1349 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1350 #define G_FW_RI_TPTE_STAGKEY(x) \ 1351 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1352 1353 #define S_FW_RI_TPTE_STAGSTATE 22 1354 #define M_FW_RI_TPTE_STAGSTATE 0x1 1355 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1356 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1357 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1358 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1359 1360 #define S_FW_RI_TPTE_STAGTYPE 20 1361 #define M_FW_RI_TPTE_STAGTYPE 0x3 1362 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1363 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1364 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1365 1366 #define S_FW_RI_TPTE_PDID 0 1367 #define M_FW_RI_TPTE_PDID 0xfffff 1368 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1369 #define G_FW_RI_TPTE_PDID(x) \ 1370 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1371 1372 #define S_FW_RI_TPTE_PERM 28 1373 #define M_FW_RI_TPTE_PERM 0xf 1374 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1375 #define G_FW_RI_TPTE_PERM(x) \ 1376 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1377 1378 #define S_FW_RI_TPTE_REMINVDIS 27 1379 #define M_FW_RI_TPTE_REMINVDIS 0x1 1380 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1381 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1382 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1383 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1384 1385 #define S_FW_RI_TPTE_ADDRTYPE 26 1386 #define M_FW_RI_TPTE_ADDRTYPE 1 1387 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1388 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1389 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1390 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1391 1392 #define S_FW_RI_TPTE_MWBINDEN 25 1393 #define M_FW_RI_TPTE_MWBINDEN 0x1 1394 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1395 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1396 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1397 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1398 1399 #define S_FW_RI_TPTE_PS 20 1400 #define M_FW_RI_TPTE_PS 0x1f 1401 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1402 #define G_FW_RI_TPTE_PS(x) \ 1403 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1404 1405 #define S_FW_RI_TPTE_QPID 0 1406 #define M_FW_RI_TPTE_QPID 0xfffff 1407 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1408 #define G_FW_RI_TPTE_QPID(x) \ 1409 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1410 1411 #define S_FW_RI_TPTE_NOSNOOP 31 1412 #define M_FW_RI_TPTE_NOSNOOP 0x1 1413 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1414 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1415 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1416 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1417 1418 #define S_FW_RI_TPTE_PBLADDR 0 1419 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1420 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1421 #define G_FW_RI_TPTE_PBLADDR(x) \ 1422 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1423 1424 #define S_FW_RI_TPTE_DCA 24 1425 #define M_FW_RI_TPTE_DCA 0x1f 1426 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1427 #define G_FW_RI_TPTE_DCA(x) \ 1428 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1429 1430 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1431 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1432 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1433 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1434 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1435 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1436 1437 enum fw_ri_cqe_rxtx { 1438 FW_RI_CQE_RXTX_RX = 0x0, 1439 FW_RI_CQE_RXTX_TX = 0x1, 1440 }; 1441 1442 struct fw_ri_cqe { 1443 union fw_ri_rxtx { 1444 struct fw_ri_scqe { 1445 __be32 qpid_n_stat_rxtx_type; 1446 __be32 plen; 1447 __be32 stag; 1448 __be32 wrid; 1449 } scqe; 1450 struct fw_ri_rcqe { 1451 __be32 qpid_n_stat_rxtx_type; 1452 __be32 plen; 1453 __be32 stag; 1454 __be32 msn; 1455 } rcqe; 1456 } u; 1457 }; 1458 1459 #define S_FW_RI_CQE_QPID 12 1460 #define M_FW_RI_CQE_QPID 0xfffff 1461 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1462 #define G_FW_RI_CQE_QPID(x) \ 1463 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1464 1465 #define S_FW_RI_CQE_NOTIFY 10 1466 #define M_FW_RI_CQE_NOTIFY 0x1 1467 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1468 #define G_FW_RI_CQE_NOTIFY(x) \ 1469 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1470 1471 #define S_FW_RI_CQE_STATUS 5 1472 #define M_FW_RI_CQE_STATUS 0x1f 1473 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1474 #define G_FW_RI_CQE_STATUS(x) \ 1475 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1476 1477 1478 #define S_FW_RI_CQE_RXTX 4 1479 #define M_FW_RI_CQE_RXTX 0x1 1480 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1481 #define G_FW_RI_CQE_RXTX(x) \ 1482 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1483 1484 #define S_FW_RI_CQE_TYPE 0 1485 #define M_FW_RI_CQE_TYPE 0xf 1486 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1487 #define G_FW_RI_CQE_TYPE(x) \ 1488 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1489 1490 enum fw_ri_res_type { 1491 FW_RI_RES_TYPE_SQ, 1492 FW_RI_RES_TYPE_RQ, 1493 FW_RI_RES_TYPE_CQ, 1494 FW_RI_RES_TYPE_SRQ, 1495 }; 1496 1497 enum fw_ri_res_op { 1498 FW_RI_RES_OP_WRITE, 1499 FW_RI_RES_OP_RESET, 1500 }; 1501 1502 struct fw_ri_res { 1503 union fw_ri_restype { 1504 struct fw_ri_res_sqrq { 1505 __u8 restype; 1506 __u8 op; 1507 __be16 r3; 1508 __be32 eqid; 1509 __be32 r4[2]; 1510 __be32 fetchszm_to_iqid; 1511 __be32 dcaen_to_eqsize; 1512 __be64 eqaddr; 1513 } sqrq; 1514 struct fw_ri_res_cq { 1515 __u8 restype; 1516 __u8 op; 1517 __be16 r3; 1518 __be32 iqid; 1519 __be32 r4[2]; 1520 __be32 iqandst_to_iqandstindex; 1521 __be16 iqdroprss_to_iqesize; 1522 __be16 iqsize; 1523 __be64 iqaddr; 1524 __be32 iqns_iqro; 1525 __be32 r6_lo; 1526 __be64 r7; 1527 } cq; 1528 struct fw_ri_res_srq { 1529 __u8 restype; 1530 __u8 op; 1531 __be16 r3; 1532 __be32 eqid; 1533 __be32 r4[2]; 1534 __be32 fetchszm_to_iqid; 1535 __be32 dcaen_to_eqsize; 1536 __be64 eqaddr; 1537 __be32 srqid; 1538 __be32 pdid; 1539 __be32 hwsrqsize; 1540 __be32 hwsrqaddr; 1541 } srq; 1542 } u; 1543 }; 1544 1545 struct fw_ri_res_wr { 1546 __be32 op_nres; 1547 __be32 len16_pkd; 1548 __u64 cookie; 1549 #ifndef C99_NOT_SUPPORTED 1550 struct fw_ri_res res[0]; 1551 #endif 1552 }; 1553 1554 #define S_FW_RI_RES_WR_VFN 8 1555 #define M_FW_RI_RES_WR_VFN 0xff 1556 #define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN) 1557 #define G_FW_RI_RES_WR_VFN(x) \ 1558 (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN) 1559 1560 #define S_FW_RI_RES_WR_NRES 0 1561 #define M_FW_RI_RES_WR_NRES 0xff 1562 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1563 #define G_FW_RI_RES_WR_NRES(x) \ 1564 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1565 1566 #define S_FW_RI_RES_WR_FETCHSZM 26 1567 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1568 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1569 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1570 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1571 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1572 1573 #define S_FW_RI_RES_WR_STATUSPGNS 25 1574 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1575 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1576 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1577 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1578 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1579 1580 #define S_FW_RI_RES_WR_STATUSPGRO 24 1581 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1582 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1583 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1584 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1585 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1586 1587 #define S_FW_RI_RES_WR_FETCHNS 23 1588 #define M_FW_RI_RES_WR_FETCHNS 0x1 1589 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1590 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1591 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1592 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1593 1594 #define S_FW_RI_RES_WR_FETCHRO 22 1595 #define M_FW_RI_RES_WR_FETCHRO 0x1 1596 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1597 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1598 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1599 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1600 1601 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1602 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1603 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1604 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1605 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1606 1607 #define S_FW_RI_RES_WR_CPRIO 19 1608 #define M_FW_RI_RES_WR_CPRIO 0x1 1609 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1610 #define G_FW_RI_RES_WR_CPRIO(x) \ 1611 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1612 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1613 1614 #define S_FW_RI_RES_WR_ONCHIP 18 1615 #define M_FW_RI_RES_WR_ONCHIP 0x1 1616 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1617 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1618 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1619 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1620 1621 #define S_FW_RI_RES_WR_PCIECHN 16 1622 #define M_FW_RI_RES_WR_PCIECHN 0x3 1623 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1624 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1625 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1626 1627 #define S_FW_RI_RES_WR_IQID 0 1628 #define M_FW_RI_RES_WR_IQID 0xffff 1629 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1630 #define G_FW_RI_RES_WR_IQID(x) \ 1631 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1632 1633 #define S_FW_RI_RES_WR_DCAEN 31 1634 #define M_FW_RI_RES_WR_DCAEN 0x1 1635 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1636 #define G_FW_RI_RES_WR_DCAEN(x) \ 1637 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1638 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1639 1640 #define S_FW_RI_RES_WR_DCACPU 26 1641 #define M_FW_RI_RES_WR_DCACPU 0x1f 1642 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1643 #define G_FW_RI_RES_WR_DCACPU(x) \ 1644 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1645 1646 #define S_FW_RI_RES_WR_FBMIN 23 1647 #define M_FW_RI_RES_WR_FBMIN 0x7 1648 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1649 #define G_FW_RI_RES_WR_FBMIN(x) \ 1650 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1651 1652 #define S_FW_RI_RES_WR_FBMAX 20 1653 #define M_FW_RI_RES_WR_FBMAX 0x7 1654 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1655 #define G_FW_RI_RES_WR_FBMAX(x) \ 1656 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1657 1658 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1659 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1660 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1661 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1662 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1663 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1664 1665 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1666 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1667 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1668 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1669 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1670 1671 #define S_FW_RI_RES_WR_EQSIZE 0 1672 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1673 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1674 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1675 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1676 1677 #define S_FW_RI_RES_WR_IQANDST 15 1678 #define M_FW_RI_RES_WR_IQANDST 0x1 1679 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1680 #define G_FW_RI_RES_WR_IQANDST(x) \ 1681 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1682 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1683 1684 #define S_FW_RI_RES_WR_IQANUS 14 1685 #define M_FW_RI_RES_WR_IQANUS 0x1 1686 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1687 #define G_FW_RI_RES_WR_IQANUS(x) \ 1688 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1689 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1690 1691 #define S_FW_RI_RES_WR_IQANUD 12 1692 #define M_FW_RI_RES_WR_IQANUD 0x3 1693 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1694 #define G_FW_RI_RES_WR_IQANUD(x) \ 1695 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1696 1697 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1698 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1699 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1700 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1701 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1702 1703 #define S_FW_RI_RES_WR_IQDROPRSS 15 1704 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1705 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1706 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1707 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1708 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1709 1710 #define S_FW_RI_RES_WR_IQGTSMODE 14 1711 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1712 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1713 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1714 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1715 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1716 1717 #define S_FW_RI_RES_WR_IQPCIECH 12 1718 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1719 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1720 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1721 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1722 1723 #define S_FW_RI_RES_WR_IQDCAEN 11 1724 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1725 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1726 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1727 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1728 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1729 1730 #define S_FW_RI_RES_WR_IQDCACPU 6 1731 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1732 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1733 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1734 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1735 1736 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1737 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1738 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1739 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1740 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1741 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1742 1743 #define S_FW_RI_RES_WR_IQO 3 1744 #define M_FW_RI_RES_WR_IQO 0x1 1745 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1746 #define G_FW_RI_RES_WR_IQO(x) \ 1747 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1748 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1749 1750 #define S_FW_RI_RES_WR_IQCPRIO 2 1751 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1752 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1753 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1754 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1755 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1756 1757 #define S_FW_RI_RES_WR_IQESIZE 0 1758 #define M_FW_RI_RES_WR_IQESIZE 0x3 1759 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1760 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1761 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1762 1763 #define S_FW_RI_RES_WR_IQNS 31 1764 #define M_FW_RI_RES_WR_IQNS 0x1 1765 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1766 #define G_FW_RI_RES_WR_IQNS(x) \ 1767 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1768 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1769 1770 #define S_FW_RI_RES_WR_IQRO 30 1771 #define M_FW_RI_RES_WR_IQRO 0x1 1772 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1773 #define G_FW_RI_RES_WR_IQRO(x) \ 1774 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1775 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1776 1777 struct fw_ri_rdma_write_wr { 1778 __u8 opcode; 1779 __u8 flags; 1780 __u16 wrid; 1781 __u8 r1[3]; 1782 __u8 len16; 1783 __be64 r2; 1784 __be32 plen; 1785 __be32 stag_sink; 1786 __be64 to_sink; 1787 #ifndef C99_NOT_SUPPORTED 1788 union { 1789 struct fw_ri_immd immd_src[0]; 1790 struct fw_ri_isgl isgl_src[0]; 1791 } u; 1792 #endif 1793 }; 1794 1795 struct fw_ri_send_wr { 1796 __u8 opcode; 1797 __u8 flags; 1798 __u16 wrid; 1799 __u8 r1[3]; 1800 __u8 len16; 1801 __be32 sendop_pkd; 1802 __be32 stag_inv; 1803 __be32 plen; 1804 __be32 r3; 1805 __be64 r4; 1806 #ifndef C99_NOT_SUPPORTED 1807 union { 1808 struct fw_ri_immd immd_src[0]; 1809 struct fw_ri_isgl isgl_src[0]; 1810 } u; 1811 #endif 1812 }; 1813 1814 #define S_FW_RI_SEND_WR_SENDOP 0 1815 #define M_FW_RI_SEND_WR_SENDOP 0xf 1816 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1817 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1818 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1819 1820 struct fw_ri_rdma_read_wr { 1821 __u8 opcode; 1822 __u8 flags; 1823 __u16 wrid; 1824 __u8 r1[3]; 1825 __u8 len16; 1826 __be64 r2; 1827 __be32 stag_sink; 1828 __be32 to_sink_hi; 1829 __be32 to_sink_lo; 1830 __be32 plen; 1831 __be32 stag_src; 1832 __be32 to_src_hi; 1833 __be32 to_src_lo; 1834 __be32 r5; 1835 }; 1836 1837 struct fw_ri_recv_wr { 1838 __u8 opcode; 1839 __u8 r1; 1840 __u16 wrid; 1841 __u8 r2[3]; 1842 __u8 len16; 1843 struct fw_ri_isgl isgl; 1844 }; 1845 1846 struct fw_ri_bind_mw_wr { 1847 __u8 opcode; 1848 __u8 flags; 1849 __u16 wrid; 1850 __u8 r1[3]; 1851 __u8 len16; 1852 __u8 qpbinde_to_dcacpu; 1853 __u8 pgsz_shift; 1854 __u8 addr_type; 1855 __u8 mem_perms; 1856 __be32 stag_mr; 1857 __be32 stag_mw; 1858 __be32 r3; 1859 __be64 len_mw; 1860 __be64 va_fbo; 1861 __be64 r4; 1862 }; 1863 1864 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1865 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1866 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1867 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1868 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1869 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1870 1871 #define S_FW_RI_BIND_MW_WR_NS 5 1872 #define M_FW_RI_BIND_MW_WR_NS 0x1 1873 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1874 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1875 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1876 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1877 1878 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1879 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1880 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1881 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1882 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1883 1884 struct fw_ri_fr_nsmr_wr { 1885 __u8 opcode; 1886 __u8 flags; 1887 __u16 wrid; 1888 __u8 r1[3]; 1889 __u8 len16; 1890 __u8 qpbinde_to_dcacpu; 1891 __u8 pgsz_shift; 1892 __u8 addr_type; 1893 __u8 mem_perms; 1894 __be32 stag; 1895 __be32 len_hi; 1896 __be32 len_lo; 1897 __be32 va_hi; 1898 __be32 va_lo_fbo; 1899 }; 1900 1901 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1902 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1903 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1904 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1905 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1906 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1907 1908 #define S_FW_RI_FR_NSMR_WR_NS 5 1909 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1910 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1911 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1912 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1913 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1914 1915 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1916 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1917 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1918 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1919 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1920 1921 struct fw_ri_fr_nsmr_tpte_wr { 1922 __u8 opcode; 1923 __u8 flags; 1924 __u16 wrid; 1925 __u8 r1[3]; 1926 __u8 len16; 1927 __be32 r2; 1928 __be32 stag; 1929 struct fw_ri_tpte tpte; 1930 __be64 pbl[2]; 1931 }; 1932 1933 struct fw_ri_inv_lstag_wr { 1934 __u8 opcode; 1935 __u8 flags; 1936 __u16 wrid; 1937 __u8 r1[3]; 1938 __u8 len16; 1939 __be32 r2; 1940 __be32 stag_inv; 1941 }; 1942 1943 struct fw_ri_send_immediate_wr { 1944 __u8 opcode; 1945 __u8 flags; 1946 __u16 wrid; 1947 __u8 r1[3]; 1948 __u8 len16; 1949 __be32 sendimmop_pkd; 1950 __be32 r3; 1951 __be32 plen; 1952 __be32 r4; 1953 __be64 r5; 1954 #ifndef C99_NOT_SUPPORTED 1955 struct fw_ri_immd immd_src[0]; 1956 #endif 1957 }; 1958 1959 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1960 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1961 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1962 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1963 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1964 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1965 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1966 1967 enum fw_ri_atomic_op { 1968 FW_RI_ATOMIC_OP_FETCHADD, 1969 FW_RI_ATOMIC_OP_SWAP, 1970 FW_RI_ATOMIC_OP_CMDSWAP, 1971 }; 1972 1973 struct fw_ri_atomic_wr { 1974 __u8 opcode; 1975 __u8 flags; 1976 __u16 wrid; 1977 __u8 r1[3]; 1978 __u8 len16; 1979 __be32 atomicop_pkd; 1980 __be64 r3; 1981 __be32 aopcode_pkd; 1982 __be32 reqid; 1983 __be32 stag; 1984 __be32 to_hi; 1985 __be32 to_lo; 1986 __be32 addswap_data_hi; 1987 __be32 addswap_data_lo; 1988 __be32 addswap_mask_hi; 1989 __be32 addswap_mask_lo; 1990 __be32 compare_data_hi; 1991 __be32 compare_data_lo; 1992 __be32 compare_mask_hi; 1993 __be32 compare_mask_lo; 1994 __be32 r5; 1995 }; 1996 1997 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1998 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1999 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 2000 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 2001 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 2002 2003 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 2004 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 2005 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 2006 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 2007 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 2008 2009 enum fw_ri_type { 2010 FW_RI_TYPE_INIT, 2011 FW_RI_TYPE_FINI, 2012 FW_RI_TYPE_TERMINATE 2013 }; 2014 2015 enum fw_ri_init_p2ptype { 2016 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 2017 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 2018 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 2019 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 2020 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 2021 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 2022 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 2023 }; 2024 2025 enum fw_ri_init_rqeqid_srq { 2026 FW_RI_INIT_RQEQID_SRQ = 1 << 31, 2027 }; 2028 2029 struct fw_ri_wr { 2030 __be32 op_compl; 2031 __be32 flowid_len16; 2032 __u64 cookie; 2033 union fw_ri { 2034 struct fw_ri_init { 2035 __u8 type; 2036 __u8 mpareqbit_p2ptype; 2037 __u8 r4[2]; 2038 __u8 mpa_attrs; 2039 __u8 qp_caps; 2040 __be16 nrqe; 2041 __be32 pdid; 2042 __be32 qpid; 2043 __be32 sq_eqid; 2044 __be32 rq_eqid; 2045 __be32 scqid; 2046 __be32 rcqid; 2047 __be32 ord_max; 2048 __be32 ird_max; 2049 __be32 iss; 2050 __be32 irs; 2051 __be32 hwrqsize; 2052 __be32 hwrqaddr; 2053 __be64 r5; 2054 union fw_ri_init_p2p { 2055 struct fw_ri_rdma_write_wr write; 2056 struct fw_ri_rdma_read_wr read; 2057 struct fw_ri_send_wr send; 2058 } u; 2059 } init; 2060 struct fw_ri_fini { 2061 __u8 type; 2062 __u8 r3[7]; 2063 __be64 r4; 2064 } fini; 2065 struct fw_ri_terminate { 2066 __u8 type; 2067 __u8 r3[3]; 2068 __be32 immdlen; 2069 __u8 termmsg[40]; 2070 } terminate; 2071 } u; 2072 }; 2073 2074 #define S_FW_RI_WR_MPAREQBIT 7 2075 #define M_FW_RI_WR_MPAREQBIT 0x1 2076 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 2077 #define G_FW_RI_WR_MPAREQBIT(x) \ 2078 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 2079 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 2080 2081 #define S_FW_RI_WR_0BRRBIT 6 2082 #define M_FW_RI_WR_0BRRBIT 0x1 2083 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 2084 #define G_FW_RI_WR_0BRRBIT(x) \ 2085 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 2086 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 2087 2088 #define S_FW_RI_WR_P2PTYPE 0 2089 #define M_FW_RI_WR_P2PTYPE 0xf 2090 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 2091 #define G_FW_RI_WR_P2PTYPE(x) \ 2092 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 2093 2094 /****************************************************************************** 2095 * F O i S C S I W O R K R E Q U E S T s 2096 *********************************************/ 2097 2098 #define FW_FOISCSI_NAME_MAX_LEN 224 2099 #define FW_FOISCSI_ALIAS_MAX_LEN 224 2100 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 2101 #define FW_FOISCSI_INIT_NODE_MAX 8 2102 2103 enum fw_chnet_ifconf_wr_subop { 2104 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 2105 2106 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 2107 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 2108 2109 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 2110 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 2111 2112 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 2113 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 2114 2115 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 2116 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 2117 2118 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 2119 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 2120 2121 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 2122 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 2123 2124 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 2125 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 2126 2127 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 2128 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 2129 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 2130 2131 FW_CHNET_IFCONF_WR_SUBOP_MAX, 2132 }; 2133 2134 struct fw_chnet_ifconf_wr { 2135 __be32 op_compl; 2136 __be32 flowid_len16; 2137 __be64 cookie; 2138 __be32 if_flowid; 2139 __u8 idx; 2140 __u8 subop; 2141 __u8 retval; 2142 __u8 r2; 2143 __be64 r3; 2144 struct fw_chnet_ifconf_params { 2145 __be32 r0; 2146 __be16 vlanid; 2147 __be16 mtu; 2148 union fw_chnet_ifconf_addr_type { 2149 struct fw_chnet_ifconf_ipv4 { 2150 __be32 addr; 2151 __be32 mask; 2152 __be32 router; 2153 __be32 r0; 2154 __be64 r1; 2155 } ipv4; 2156 struct fw_chnet_ifconf_ipv6 { 2157 __u8 prefix_len; 2158 __u8 r0; 2159 __be16 r1; 2160 __be32 r2; 2161 __be64 addr_hi; 2162 __be64 addr_lo; 2163 __be64 router_hi; 2164 __be64 router_lo; 2165 } ipv6; 2166 } in_attr; 2167 } param; 2168 }; 2169 2170 enum fw_foiscsi_node_type { 2171 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 2172 FW_FOISCSI_NODE_TYPE_TARGET, 2173 }; 2174 2175 enum fw_foiscsi_session_type { 2176 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 2177 FW_FOISCSI_SESSION_TYPE_NORMAL, 2178 }; 2179 2180 enum fw_foiscsi_auth_policy { 2181 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 2182 FW_FOISCSI_AUTH_POLICY_MUTUAL, 2183 }; 2184 2185 enum fw_foiscsi_auth_method { 2186 FW_FOISCSI_AUTH_METHOD_NONE = 0, 2187 FW_FOISCSI_AUTH_METHOD_CHAP, 2188 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 2189 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 2190 }; 2191 2192 enum fw_foiscsi_digest_type { 2193 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 2194 FW_FOISCSI_DIGEST_TYPE_CRC32, 2195 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 2196 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 2197 }; 2198 2199 enum fw_foiscsi_wr_subop { 2200 FW_FOISCSI_WR_SUBOP_ADD = 1, 2201 FW_FOISCSI_WR_SUBOP_DEL = 2, 2202 FW_FOISCSI_WR_SUBOP_MOD = 4, 2203 }; 2204 2205 enum fw_foiscsi_ctrl_state { 2206 FW_FOISCSI_CTRL_STATE_FREE = 0, 2207 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 2208 FW_FOISCSI_CTRL_STATE_FAILED, 2209 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 2210 FW_FOISCSI_CTRL_STATE_REDIRECT, 2211 }; 2212 2213 struct fw_rdev_wr { 2214 __be32 op_to_immdlen; 2215 __be32 alloc_to_len16; 2216 __be64 cookie; 2217 __u8 protocol; 2218 __u8 event_cause; 2219 __u8 cur_state; 2220 __u8 prev_state; 2221 __be32 flags_to_assoc_flowid; 2222 union rdev_entry { 2223 struct fcoe_rdev_entry { 2224 __be32 flowid; 2225 __u8 protocol; 2226 __u8 event_cause; 2227 __u8 flags; 2228 __u8 rjt_reason; 2229 __u8 cur_login_st; 2230 __u8 prev_login_st; 2231 __be16 rcv_fr_sz; 2232 __u8 rd_xfer_rdy_to_rport_type; 2233 __u8 vft_to_qos; 2234 __u8 org_proc_assoc_to_acc_rsp_code; 2235 __u8 enh_disc_to_tgt; 2236 __u8 wwnn[8]; 2237 __u8 wwpn[8]; 2238 __be16 iqid; 2239 __u8 fc_oui[3]; 2240 __u8 r_id[3]; 2241 } fcoe_rdev; 2242 struct iscsi_rdev_entry { 2243 __be32 flowid; 2244 __u8 protocol; 2245 __u8 event_cause; 2246 __u8 flags; 2247 __u8 r3; 2248 __be16 iscsi_opts; 2249 __be16 tcp_opts; 2250 __be16 ip_opts; 2251 __be16 max_rcv_len; 2252 __be16 max_snd_len; 2253 __be16 first_brst_len; 2254 __be16 max_brst_len; 2255 __be16 r4; 2256 __be16 def_time2wait; 2257 __be16 def_time2ret; 2258 __be16 nop_out_intrvl; 2259 __be16 non_scsi_to; 2260 __be16 isid; 2261 __be16 tsid; 2262 __be16 port; 2263 __be16 tpgt; 2264 __u8 r5[6]; 2265 __be16 iqid; 2266 } iscsi_rdev; 2267 } u; 2268 }; 2269 2270 #define S_FW_RDEV_WR_IMMDLEN 0 2271 #define M_FW_RDEV_WR_IMMDLEN 0xff 2272 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2273 #define G_FW_RDEV_WR_IMMDLEN(x) \ 2274 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2275 2276 #define S_FW_RDEV_WR_ALLOC 31 2277 #define M_FW_RDEV_WR_ALLOC 0x1 2278 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2279 #define G_FW_RDEV_WR_ALLOC(x) \ 2280 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2281 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2282 2283 #define S_FW_RDEV_WR_FREE 30 2284 #define M_FW_RDEV_WR_FREE 0x1 2285 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2286 #define G_FW_RDEV_WR_FREE(x) \ 2287 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2288 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2289 2290 #define S_FW_RDEV_WR_MODIFY 29 2291 #define M_FW_RDEV_WR_MODIFY 0x1 2292 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2293 #define G_FW_RDEV_WR_MODIFY(x) \ 2294 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2295 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2296 2297 #define S_FW_RDEV_WR_FLOWID 8 2298 #define M_FW_RDEV_WR_FLOWID 0xfffff 2299 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2300 #define G_FW_RDEV_WR_FLOWID(x) \ 2301 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2302 2303 #define S_FW_RDEV_WR_LEN16 0 2304 #define M_FW_RDEV_WR_LEN16 0xff 2305 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2306 #define G_FW_RDEV_WR_LEN16(x) \ 2307 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2308 2309 #define S_FW_RDEV_WR_FLAGS 24 2310 #define M_FW_RDEV_WR_FLAGS 0xff 2311 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2312 #define G_FW_RDEV_WR_FLAGS(x) \ 2313 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2314 2315 #define S_FW_RDEV_WR_GET_NEXT 20 2316 #define M_FW_RDEV_WR_GET_NEXT 0xf 2317 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2318 #define G_FW_RDEV_WR_GET_NEXT(x) \ 2319 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2320 2321 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 2322 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2323 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2324 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2325 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2326 2327 #define S_FW_RDEV_WR_RJT 7 2328 #define M_FW_RDEV_WR_RJT 0x1 2329 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2330 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2331 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2332 2333 #define S_FW_RDEV_WR_REASON 0 2334 #define M_FW_RDEV_WR_REASON 0x7f 2335 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2336 #define G_FW_RDEV_WR_REASON(x) \ 2337 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2338 2339 #define S_FW_RDEV_WR_RD_XFER_RDY 7 2340 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2341 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2342 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2343 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2344 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2345 2346 #define S_FW_RDEV_WR_WR_XFER_RDY 6 2347 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2348 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2349 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2350 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2351 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2352 2353 #define S_FW_RDEV_WR_FC_SP 5 2354 #define M_FW_RDEV_WR_FC_SP 0x1 2355 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2356 #define G_FW_RDEV_WR_FC_SP(x) \ 2357 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2358 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2359 2360 #define S_FW_RDEV_WR_RPORT_TYPE 0 2361 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2362 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2363 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2364 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2365 2366 #define S_FW_RDEV_WR_VFT 7 2367 #define M_FW_RDEV_WR_VFT 0x1 2368 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2369 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2370 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2371 2372 #define S_FW_RDEV_WR_NPIV 6 2373 #define M_FW_RDEV_WR_NPIV 0x1 2374 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2375 #define G_FW_RDEV_WR_NPIV(x) \ 2376 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2377 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2378 2379 #define S_FW_RDEV_WR_CLASS 4 2380 #define M_FW_RDEV_WR_CLASS 0x3 2381 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2382 #define G_FW_RDEV_WR_CLASS(x) \ 2383 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2384 2385 #define S_FW_RDEV_WR_SEQ_DEL 3 2386 #define M_FW_RDEV_WR_SEQ_DEL 0x1 2387 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2388 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2389 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2390 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2391 2392 #define S_FW_RDEV_WR_PRIO_PREEMP 2 2393 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2394 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2395 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2396 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2397 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2398 2399 #define S_FW_RDEV_WR_PREF 1 2400 #define M_FW_RDEV_WR_PREF 0x1 2401 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2402 #define G_FW_RDEV_WR_PREF(x) \ 2403 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2404 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2405 2406 #define S_FW_RDEV_WR_QOS 0 2407 #define M_FW_RDEV_WR_QOS 0x1 2408 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2409 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2410 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2411 2412 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2413 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2414 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2415 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2416 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2417 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2418 2419 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2420 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2421 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2422 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2423 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2424 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2425 2426 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2427 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2428 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2429 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2430 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2431 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2432 2433 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2434 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2435 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2436 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2437 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2438 2439 #define S_FW_RDEV_WR_ENH_DISC 7 2440 #define M_FW_RDEV_WR_ENH_DISC 0x1 2441 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2442 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2443 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2444 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2445 2446 #define S_FW_RDEV_WR_REC 6 2447 #define M_FW_RDEV_WR_REC 0x1 2448 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2449 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2450 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2451 2452 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2453 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2454 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2455 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2456 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2457 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2458 2459 #define S_FW_RDEV_WR_RETRY 4 2460 #define M_FW_RDEV_WR_RETRY 0x1 2461 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2462 #define G_FW_RDEV_WR_RETRY(x) \ 2463 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2464 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2465 2466 #define S_FW_RDEV_WR_CONF_CMPL 3 2467 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2468 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2469 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2470 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2471 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2472 2473 #define S_FW_RDEV_WR_DATA_OVLY 2 2474 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2475 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2476 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2477 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2478 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2479 2480 #define S_FW_RDEV_WR_INI 1 2481 #define M_FW_RDEV_WR_INI 0x1 2482 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2483 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2484 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2485 2486 #define S_FW_RDEV_WR_TGT 0 2487 #define M_FW_RDEV_WR_TGT 0x1 2488 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2489 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2490 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2491 2492 struct fw_foiscsi_node_wr { 2493 __be32 op_to_immdlen; 2494 __be32 flowid_len16; 2495 __u64 cookie; 2496 __u8 subop; 2497 __u8 status; 2498 __u8 alias_len; 2499 __u8 iqn_len; 2500 __be32 node_flowid; 2501 __be16 nodeid; 2502 __be16 login_retry; 2503 __be16 retry_timeout; 2504 __be16 r3; 2505 __u8 iqn[224]; 2506 __u8 alias[224]; 2507 }; 2508 2509 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2510 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2511 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2512 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2513 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2514 2515 struct fw_foiscsi_ctrl_wr { 2516 __be32 op_compl; 2517 __be32 flowid_len16; 2518 __u64 cookie; 2519 __u8 subop; 2520 __u8 status; 2521 __u8 ctrl_state; 2522 __u8 io_state; 2523 __be32 node_id; 2524 __be32 ctrl_id; 2525 __be32 io_id; 2526 struct fw_foiscsi_sess_attr { 2527 __be32 sess_type_to_erl; 2528 __be16 max_conn; 2529 __be16 max_r2t; 2530 __be16 time2wait; 2531 __be16 time2retain; 2532 __be32 max_burst; 2533 __be32 first_burst; 2534 __be32 r1; 2535 } sess_attr; 2536 struct fw_foiscsi_conn_attr { 2537 __be32 hdigest_to_ddp_pgsz; 2538 __be32 max_rcv_dsl; 2539 __be32 ping_tmo; 2540 __be16 dst_port; 2541 __be16 src_port; 2542 union fw_foiscsi_conn_attr_addr { 2543 struct fw_foiscsi_conn_attr_ipv6 { 2544 __be64 dst_addr[2]; 2545 __be64 src_addr[2]; 2546 } ipv6_addr; 2547 struct fw_foiscsi_conn_attr_ipv4 { 2548 __be32 dst_addr; 2549 __be32 src_addr; 2550 } ipv4_addr; 2551 } u; 2552 } conn_attr; 2553 __u8 tgt_name_len; 2554 __u8 r3[7]; 2555 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2556 }; 2557 2558 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2559 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2560 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2561 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2562 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2563 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2564 2565 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2566 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2567 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2568 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2569 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2570 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2571 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2572 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2573 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2574 2575 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2576 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2577 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2578 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2579 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2580 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2581 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2582 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2583 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2584 2585 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2586 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2587 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2588 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2589 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2590 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2591 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2592 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2593 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2594 2595 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2596 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2597 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2598 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2599 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2600 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2601 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2602 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2603 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2604 2605 #define S_FW_FOISCSI_CTRL_WR_ERL 24 2606 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2607 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2608 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2609 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2610 2611 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2612 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2613 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2614 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2615 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2616 2617 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2618 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2619 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2620 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2621 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2622 2623 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2624 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2625 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2626 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2627 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2628 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2629 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2630 2631 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2632 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2633 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2634 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2635 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2636 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2637 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2638 2639 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2640 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2641 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2642 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2643 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2644 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2645 2646 #define S_FW_FOISCSI_CTRL_WR_IPV6 20 2647 #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 2648 #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 2649 #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 2650 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 2651 #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 2652 2653 struct fw_foiscsi_chap_wr { 2654 __be32 op_compl; 2655 __be32 flowid_len16; 2656 __u64 cookie; 2657 __u8 status; 2658 __u8 id_len; 2659 __u8 sec_len; 2660 __u8 node_type; 2661 __be16 node_id; 2662 __u8 r3[2]; 2663 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2664 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 2665 }; 2666 2667 /****************************************************************************** 2668 * C O i S C S I W O R K R E Q U E S T S 2669 ********************************************/ 2670 2671 enum fw_chnet_addr_type { 2672 FW_CHNET_ADDD_TYPE_NONE = 0, 2673 FW_CHNET_ADDR_TYPE_IPV4, 2674 FW_CHNET_ADDR_TYPE_IPV6, 2675 }; 2676 2677 enum fw_msg_wr_type { 2678 FW_MSG_WR_TYPE_RPL = 0, 2679 FW_MSG_WR_TYPE_ERR, 2680 FW_MSG_WR_TYPE_PLD, 2681 }; 2682 2683 struct fw_coiscsi_tgt_wr { 2684 __be32 op_compl; 2685 __be32 flowid_len16; 2686 __u64 cookie; 2687 __u8 subop; 2688 __u8 status; 2689 __be16 r4; 2690 __be32 flags; 2691 struct fw_coiscsi_tgt_conn_attr { 2692 __be32 in_tid; 2693 __be16 in_port; 2694 __u8 in_type; 2695 __u8 r6; 2696 union fw_coiscsi_tgt_conn_attr_addr { 2697 struct fw_coiscsi_tgt_conn_attr_in_addr { 2698 __be32 addr; 2699 __be32 r7; 2700 __be32 r8[2]; 2701 } in_addr; 2702 struct fw_coiscsi_tgt_conn_attr_in_addr6 { 2703 __be64 addr[2]; 2704 } in_addr6; 2705 } u; 2706 } conn_attr; 2707 }; 2708 2709 struct fw_coiscsi_tgt_conn_wr { 2710 __be32 op_compl; 2711 __be32 flowid_len16; 2712 __u64 cookie; 2713 __u8 subop; 2714 __u8 status; 2715 __be16 iq_id; 2716 __be32 in_stid; 2717 __be32 io_id; 2718 __be32 flags; 2719 struct fw_coiscsi_tgt_conn_tcp { 2720 __be16 in_sport; 2721 __be16 in_dport; 2722 __be32 r4; 2723 union fw_coiscsi_tgt_conn_tcp_addr { 2724 struct fw_coiscsi_tgt_conn_tcp_in_addr { 2725 __be32 saddr; 2726 __be32 daddr; 2727 } in_addr; 2728 struct fw_coiscsi_tgt_conn_tcp_in_addr6 { 2729 __be64 saddr[2]; 2730 __be64 daddr[2]; 2731 } in_addr6; 2732 } u; 2733 } conn_tcp; 2734 struct fw_coiscsi_tgt_conn_iscsi { 2735 __be32 hdigest_to_ddp_pgsz; 2736 __be32 tgt_id; 2737 __be16 max_r2t; 2738 __be16 r5; 2739 __be32 max_burst; 2740 __be32 max_rdsl; 2741 __be32 max_tdsl; 2742 __be32 nxt_sn; 2743 __be32 r6; 2744 } conn_iscsi; 2745 }; 2746 2747 struct fw_coiscsi_tgt_xmit_wr { 2748 __be32 op_to_immdlen; 2749 __be32 flowid_len16; 2750 __be64 cookie; 2751 __be16 iq_id; 2752 __be16 r4; 2753 __be32 datasn; 2754 __be32 t_xfer_len; 2755 __be32 flags; 2756 __be32 tag; 2757 __be32 tidx; 2758 __be32 r5[2]; 2759 }; 2760 2761 #define S_FW_COiSCSI_TGT_XMIT_WR_DDGST 23 2762 #define M_FW_COiSCSI_TGT_XMIT_WR_DDGST 0x1 2763 #define V_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 2764 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDGST) 2765 #define G_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 2766 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDGST) & M_FW_COiSCSI_TGT_XMIT_WR_DDGST) 2767 #define F_FW_COiSCSI_TGT_XMIT_WR_DDGST V_FW_COiSCSI_TGT_XMIT_WR_DDGST(1U) 2768 2769 #define S_FW_COiSCSI_TGT_XMIT_WR_HDGST 22 2770 #define M_FW_COiSCSI_TGT_XMIT_WR_HDGST 0x1 2771 #define V_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 2772 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_HDGST) 2773 #define G_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 2774 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_HDGST) & M_FW_COiSCSI_TGT_XMIT_WR_HDGST) 2775 #define F_FW_COiSCSI_TGT_XMIT_WR_HDGST V_FW_COiSCSI_TGT_XMIT_WR_HDGST(1U) 2776 2777 #define S_FW_COiSCSI_TGT_XMIT_WR_DDP 20 2778 #define M_FW_COiSCSI_TGT_XMIT_WR_DDP 0x1 2779 #define V_FW_COiSCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDP) 2780 #define G_FW_COiSCSI_TGT_XMIT_WR_DDP(x) \ 2781 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDP) & M_FW_COiSCSI_TGT_XMIT_WR_DDP) 2782 #define F_FW_COiSCSI_TGT_XMIT_WR_DDP V_FW_COiSCSI_TGT_XMIT_WR_DDP(1U) 2783 2784 #define S_FW_COiSCSI_TGT_XMIT_WR_ABORT 19 2785 #define M_FW_COiSCSI_TGT_XMIT_WR_ABORT 0x1 2786 #define V_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \ 2787 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_ABORT) 2788 #define G_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \ 2789 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_ABORT) & M_FW_COiSCSI_TGT_XMIT_WR_ABORT) 2790 #define F_FW_COiSCSI_TGT_XMIT_WR_ABORT V_FW_COiSCSI_TGT_XMIT_WR_ABORT(1U) 2791 2792 #define S_FW_COiSCSI_TGT_XMIT_WR_FINAL 18 2793 #define M_FW_COiSCSI_TGT_XMIT_WR_FINAL 0x1 2794 #define V_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \ 2795 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_FINAL) 2796 #define G_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \ 2797 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_FINAL) & M_FW_COiSCSI_TGT_XMIT_WR_FINAL) 2798 #define F_FW_COiSCSI_TGT_XMIT_WR_FINAL V_FW_COiSCSI_TGT_XMIT_WR_FINAL(1U) 2799 2800 #define S_FW_COiSCSI_TGT_XMIT_WR_PADLEN 16 2801 #define M_FW_COiSCSI_TGT_XMIT_WR_PADLEN 0x3 2802 #define V_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \ 2803 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) 2804 #define G_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \ 2805 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) & \ 2806 M_FW_COiSCSI_TGT_XMIT_WR_PADLEN) 2807 2808 #define S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0 2809 #define M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0xff 2810 #define V_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2811 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 2812 #define G_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2813 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) & \ 2814 M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 2815 2816 struct fw_isns_wr { 2817 __be32 op_compl; 2818 __be32 flowid_len16; 2819 __u64 cookie; 2820 __u8 subop; 2821 __u8 status; 2822 __be16 iq_id; 2823 __be32 r4; 2824 struct fw_tcp_conn_attr { 2825 __be32 in_tid; 2826 __be16 in_port; 2827 __u8 in_type; 2828 __u8 r6; 2829 union fw_tcp_conn_attr_addr { 2830 struct fw_tcp_conn_attr_in_addr { 2831 __be32 addr; 2832 __be32 r7; 2833 __be32 r8[2]; 2834 } in_addr; 2835 struct fw_tcp_conn_attr_in_addr6 { 2836 __be64 addr[2]; 2837 } in_addr6; 2838 } u; 2839 } conn_attr; 2840 }; 2841 2842 struct fw_isns_xmit_wr { 2843 __be32 op_to_immdlen; 2844 __be32 flowid_len16; 2845 __be64 cookie; 2846 __be16 iq_id; 2847 __be16 r4; 2848 __be32 xfer_len; 2849 __be64 r5; 2850 }; 2851 2852 #define S_FW_ISNS_XMIT_WR_IMMDLEN 0 2853 #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff 2854 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) 2855 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ 2856 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN) 2857 2858 /****************************************************************************** 2859 * F O F C O E W O R K R E Q U E S T s 2860 *******************************************/ 2861 2862 struct fw_fcoe_els_ct_wr { 2863 __be32 op_immdlen; 2864 __be32 flowid_len16; 2865 __be64 cookie; 2866 __be16 iqid; 2867 __u8 tmo_val; 2868 __u8 els_ct_type; 2869 __u8 ctl_pri; 2870 __u8 cp_en_class; 2871 __be16 xfer_cnt; 2872 __u8 fl_to_sp; 2873 __u8 l_id[3]; 2874 __u8 r5; 2875 __u8 r_id[3]; 2876 __be64 rsp_dmaaddr; 2877 __be32 rsp_dmalen; 2878 __be32 r6; 2879 }; 2880 2881 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2882 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2883 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2884 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2885 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2886 2887 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2888 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2889 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2890 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2891 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2892 2893 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2894 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2895 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2896 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2897 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2898 2899 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 2900 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2901 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2902 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2903 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2904 2905 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2906 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2907 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2908 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2909 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2910 2911 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 2912 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2913 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2914 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2915 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2916 2917 #define S_FW_FCOE_ELS_CT_WR_FL 2 2918 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 2919 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2920 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2921 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2922 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2923 2924 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 2925 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2926 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2927 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2928 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2929 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2930 2931 #define S_FW_FCOE_ELS_CT_WR_SP 0 2932 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 2933 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2934 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2935 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2936 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2937 2938 /****************************************************************************** 2939 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 2940 *****************************************************************************/ 2941 2942 struct fw_scsi_write_wr { 2943 __be32 op_immdlen; 2944 __be32 flowid_len16; 2945 __be64 cookie; 2946 __be16 iqid; 2947 __u8 tmo_val; 2948 __u8 use_xfer_cnt; 2949 union fw_scsi_write_priv { 2950 struct fcoe_write_priv { 2951 __u8 ctl_pri; 2952 __u8 cp_en_class; 2953 __u8 r3_lo[2]; 2954 } fcoe; 2955 struct iscsi_write_priv { 2956 __u8 r3[4]; 2957 } iscsi; 2958 } u; 2959 __be32 xfer_cnt; 2960 __be32 ini_xfer_cnt; 2961 __be64 rsp_dmaaddr; 2962 __be32 rsp_dmalen; 2963 __be32 r4; 2964 }; 2965 2966 #define S_FW_SCSI_WRITE_WR_OPCODE 24 2967 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2968 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2969 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2970 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2971 2972 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2973 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2974 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2975 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2976 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2977 2978 #define S_FW_SCSI_WRITE_WR_FLOWID 8 2979 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2980 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2981 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2982 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2983 2984 #define S_FW_SCSI_WRITE_WR_LEN16 0 2985 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 2986 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2987 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 2988 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 2989 2990 #define S_FW_SCSI_WRITE_WR_CP_EN 6 2991 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 2992 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 2993 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 2994 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 2995 2996 #define S_FW_SCSI_WRITE_WR_CLASS 4 2997 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 2998 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 2999 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 3000 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 3001 3002 struct fw_scsi_read_wr { 3003 __be32 op_immdlen; 3004 __be32 flowid_len16; 3005 __be64 cookie; 3006 __be16 iqid; 3007 __u8 tmo_val; 3008 __u8 use_xfer_cnt; 3009 union fw_scsi_read_priv { 3010 struct fcoe_read_priv { 3011 __u8 ctl_pri; 3012 __u8 cp_en_class; 3013 __u8 r3_lo[2]; 3014 } fcoe; 3015 struct iscsi_read_priv { 3016 __u8 r3[4]; 3017 } iscsi; 3018 } u; 3019 __be32 xfer_cnt; 3020 __be32 ini_xfer_cnt; 3021 __be64 rsp_dmaaddr; 3022 __be32 rsp_dmalen; 3023 __be32 r4; 3024 }; 3025 3026 #define S_FW_SCSI_READ_WR_OPCODE 24 3027 #define M_FW_SCSI_READ_WR_OPCODE 0xff 3028 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 3029 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 3030 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 3031 3032 #define S_FW_SCSI_READ_WR_IMMDLEN 0 3033 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 3034 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 3035 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 3036 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 3037 3038 #define S_FW_SCSI_READ_WR_FLOWID 8 3039 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 3040 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 3041 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 3042 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 3043 3044 #define S_FW_SCSI_READ_WR_LEN16 0 3045 #define M_FW_SCSI_READ_WR_LEN16 0xff 3046 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 3047 #define G_FW_SCSI_READ_WR_LEN16(x) \ 3048 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 3049 3050 #define S_FW_SCSI_READ_WR_CP_EN 6 3051 #define M_FW_SCSI_READ_WR_CP_EN 0x3 3052 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 3053 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 3054 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 3055 3056 #define S_FW_SCSI_READ_WR_CLASS 4 3057 #define M_FW_SCSI_READ_WR_CLASS 0x3 3058 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 3059 #define G_FW_SCSI_READ_WR_CLASS(x) \ 3060 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 3061 3062 struct fw_scsi_cmd_wr { 3063 __be32 op_immdlen; 3064 __be32 flowid_len16; 3065 __be64 cookie; 3066 __be16 iqid; 3067 __u8 tmo_val; 3068 __u8 r3; 3069 union fw_scsi_cmd_priv { 3070 struct fcoe_cmd_priv { 3071 __u8 ctl_pri; 3072 __u8 cp_en_class; 3073 __u8 r4_lo[2]; 3074 } fcoe; 3075 struct iscsi_cmd_priv { 3076 __u8 r4[4]; 3077 } iscsi; 3078 } u; 3079 __u8 r5[8]; 3080 __be64 rsp_dmaaddr; 3081 __be32 rsp_dmalen; 3082 __be32 r6; 3083 }; 3084 3085 #define S_FW_SCSI_CMD_WR_OPCODE 24 3086 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 3087 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 3088 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 3089 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 3090 3091 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 3092 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 3093 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 3094 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 3095 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 3096 3097 #define S_FW_SCSI_CMD_WR_FLOWID 8 3098 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 3099 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 3100 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 3101 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 3102 3103 #define S_FW_SCSI_CMD_WR_LEN16 0 3104 #define M_FW_SCSI_CMD_WR_LEN16 0xff 3105 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 3106 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 3107 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 3108 3109 #define S_FW_SCSI_CMD_WR_CP_EN 6 3110 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 3111 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 3112 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 3113 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 3114 3115 #define S_FW_SCSI_CMD_WR_CLASS 4 3116 #define M_FW_SCSI_CMD_WR_CLASS 0x3 3117 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 3118 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 3119 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 3120 3121 struct fw_scsi_abrt_cls_wr { 3122 __be32 op_immdlen; 3123 __be32 flowid_len16; 3124 __be64 cookie; 3125 __be16 iqid; 3126 __u8 tmo_val; 3127 __u8 sub_opcode_to_chk_all_io; 3128 __u8 r3[4]; 3129 __be64 t_cookie; 3130 }; 3131 3132 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 3133 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 3134 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 3135 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 3136 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 3137 3138 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 3139 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 3140 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3141 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3142 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3143 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3144 3145 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 3146 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 3147 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 3148 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 3149 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 3150 3151 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 3152 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 3153 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 3154 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 3155 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 3156 3157 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 3158 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 3159 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3160 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3161 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3162 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 3163 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3164 3165 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 3166 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 3167 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 3168 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 3169 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 3170 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 3171 3172 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 3173 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 3174 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3175 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3176 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3177 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 3178 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3179 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 3180 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 3181 3182 struct fw_scsi_tgt_acc_wr { 3183 __be32 op_immdlen; 3184 __be32 flowid_len16; 3185 __be64 cookie; 3186 __be16 iqid; 3187 __u8 r3; 3188 __u8 use_burst_len; 3189 union fw_scsi_tgt_acc_priv { 3190 struct fcoe_tgt_acc_priv { 3191 __u8 ctl_pri; 3192 __u8 cp_en_class; 3193 __u8 r4_lo[2]; 3194 } fcoe; 3195 struct iscsi_tgt_acc_priv { 3196 __u8 r4[4]; 3197 } iscsi; 3198 } u; 3199 __be32 burst_len; 3200 __be32 rel_off; 3201 __be64 r5; 3202 __be32 r6; 3203 __be32 tot_xfer_len; 3204 }; 3205 3206 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 3207 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 3208 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 3209 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 3210 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 3211 3212 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 3213 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 3214 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3215 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 3216 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3217 3218 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 3219 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 3220 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 3221 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 3222 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 3223 3224 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 3225 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 3226 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 3227 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 3228 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 3229 3230 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 3231 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 3232 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 3233 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 3234 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 3235 3236 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 3237 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 3238 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 3239 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 3240 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 3241 3242 struct fw_scsi_tgt_xmit_wr { 3243 __be32 op_immdlen; 3244 __be32 flowid_len16; 3245 __be64 cookie; 3246 __be16 iqid; 3247 __u8 auto_rsp; 3248 __u8 use_xfer_cnt; 3249 union fw_scsi_tgt_xmit_priv { 3250 struct fcoe_tgt_xmit_priv { 3251 __u8 ctl_pri; 3252 __u8 cp_en_class; 3253 __u8 r3_lo[2]; 3254 } fcoe; 3255 struct iscsi_tgt_xmit_priv { 3256 __u8 r3[4]; 3257 } iscsi; 3258 } u; 3259 __be32 xfer_cnt; 3260 __be32 r4; 3261 __be64 r5; 3262 __be32 r6; 3263 __be32 tot_xfer_len; 3264 }; 3265 3266 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 3267 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 3268 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 3269 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 3270 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 3271 3272 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 3273 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 3274 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3275 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3276 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3277 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3278 3279 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 3280 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 3281 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 3282 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 3283 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 3284 3285 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 3286 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 3287 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 3288 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 3289 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 3290 3291 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 3292 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 3293 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 3294 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 3295 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 3296 3297 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 3298 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 3299 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 3300 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 3301 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 3302 3303 struct fw_scsi_tgt_rsp_wr { 3304 __be32 op_immdlen; 3305 __be32 flowid_len16; 3306 __be64 cookie; 3307 __be16 iqid; 3308 __u8 r3[2]; 3309 union fw_scsi_tgt_rsp_priv { 3310 struct fcoe_tgt_rsp_priv { 3311 __u8 ctl_pri; 3312 __u8 cp_en_class; 3313 __u8 r4_lo[2]; 3314 } fcoe; 3315 struct iscsi_tgt_rsp_priv { 3316 __u8 r4[4]; 3317 } iscsi; 3318 } u; 3319 __u8 r5[8]; 3320 }; 3321 3322 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 3323 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 3324 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 3325 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 3326 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 3327 3328 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 3329 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 3330 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3331 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 3332 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3333 3334 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 3335 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 3336 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 3337 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 3338 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 3339 3340 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 3341 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 3342 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 3343 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 3344 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 3345 3346 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 3347 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 3348 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 3349 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 3350 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 3351 3352 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 3353 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 3354 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 3355 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 3356 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 3357 3358 struct fw_pofcoe_tcb_wr { 3359 __be32 op_compl; 3360 __be32 equiq_to_len16; 3361 __be32 r4; 3362 __be32 xfer_len; 3363 __be32 tid_to_port; 3364 __be16 x_id; 3365 __be16 vlan_id; 3366 __be64 cookie; 3367 __be32 s_id; 3368 __be32 d_id; 3369 __be32 tag; 3370 __be16 r6; 3371 __be16 iqid; 3372 }; 3373 3374 #define S_FW_POFCOE_TCB_WR_TID 12 3375 #define M_FW_POFCOE_TCB_WR_TID 0xfffff 3376 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 3377 #define G_FW_POFCOE_TCB_WR_TID(x) \ 3378 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 3379 3380 #define S_FW_POFCOE_TCB_WR_ALLOC 4 3381 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 3382 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 3383 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 3384 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 3385 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 3386 3387 #define S_FW_POFCOE_TCB_WR_FREE 3 3388 #define M_FW_POFCOE_TCB_WR_FREE 0x1 3389 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 3390 #define G_FW_POFCOE_TCB_WR_FREE(x) \ 3391 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 3392 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 3393 3394 #define S_FW_POFCOE_TCB_WR_PORT 0 3395 #define M_FW_POFCOE_TCB_WR_PORT 0x7 3396 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 3397 #define G_FW_POFCOE_TCB_WR_PORT(x) \ 3398 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 3399 3400 struct fw_pofcoe_ulptx_wr { 3401 __be32 op_pkd; 3402 __be32 equiq_to_len16; 3403 __u64 cookie; 3404 }; 3405 3406 /******************************************************************* 3407 * T10 DIF related definition 3408 *******************************************************************/ 3409 struct fw_tx_pi_header { 3410 __be16 op_to_inline; 3411 __u8 pi_interval_tag_type; 3412 __u8 num_pi; 3413 __be32 pi_start4_pi_end4; 3414 __u8 tag_gen_enabled_pkd; 3415 __u8 num_pi_dsg; 3416 __be16 app_tag; 3417 __be32 ref_tag; 3418 }; 3419 3420 #define S_FW_TX_PI_HEADER_OP 8 3421 #define M_FW_TX_PI_HEADER_OP 0xff 3422 #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) 3423 #define G_FW_TX_PI_HEADER_OP(x) \ 3424 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) 3425 3426 #define S_FW_TX_PI_HEADER_ULPTXMORE 7 3427 #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 3428 #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) 3429 #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ 3430 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) 3431 #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) 3432 3433 #define S_FW_TX_PI_HEADER_PI_CONTROL 4 3434 #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 3435 #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) 3436 #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ 3437 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) 3438 3439 #define S_FW_TX_PI_HEADER_GUARD_TYPE 2 3440 #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 3441 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) 3442 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ 3443 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) 3444 #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) 3445 3446 #define S_FW_TX_PI_HEADER_VALIDATE 1 3447 #define M_FW_TX_PI_HEADER_VALIDATE 0x1 3448 #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) 3449 #define G_FW_TX_PI_HEADER_VALIDATE(x) \ 3450 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) 3451 #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) 3452 3453 #define S_FW_TX_PI_HEADER_INLINE 0 3454 #define M_FW_TX_PI_HEADER_INLINE 0x1 3455 #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) 3456 #define G_FW_TX_PI_HEADER_INLINE(x) \ 3457 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) 3458 #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) 3459 3460 #define S_FW_TX_PI_HEADER_PI_INTERVAL 7 3461 #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 3462 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3463 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) 3464 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3465 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) 3466 #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) 3467 3468 #define S_FW_TX_PI_HEADER_TAG_TYPE 5 3469 #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 3470 #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) 3471 #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ 3472 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) 3473 3474 #define S_FW_TX_PI_HEADER_PI_START4 22 3475 #define M_FW_TX_PI_HEADER_PI_START4 0x3ff 3476 #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) 3477 #define G_FW_TX_PI_HEADER_PI_START4(x) \ 3478 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) 3479 3480 #define S_FW_TX_PI_HEADER_PI_END4 0 3481 #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff 3482 #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) 3483 #define G_FW_TX_PI_HEADER_PI_END4(x) \ 3484 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) 3485 3486 #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 3487 #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 3488 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3489 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3490 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3491 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ 3492 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3493 3494 enum fw_pi_error_type { 3495 FW_PI_ERROR_GUARD_CHECK_FAILED = 0, 3496 }; 3497 3498 struct fw_pi_error { 3499 __be32 err_type_pkd; 3500 __be32 flowid_len16; 3501 __be16 r2; 3502 __be16 app_tag; 3503 __be32 ref_tag; 3504 __be32 pisc[4]; 3505 }; 3506 3507 #define S_FW_PI_ERROR_ERR_TYPE 24 3508 #define M_FW_PI_ERROR_ERR_TYPE 0xff 3509 #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) 3510 #define G_FW_PI_ERROR_ERR_TYPE(x) \ 3511 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) 3512 3513 struct fw_tlstx_data_wr { 3514 __be32 op_to_immdlen; 3515 __be32 flowid_len16; 3516 __be32 plen; 3517 __be32 lsodisable_to_flags; 3518 __be32 r5; 3519 __be32 ctxloc_to_exp; 3520 __be16 mfs; 3521 __be16 adjustedplen_pkd; 3522 __be16 expinplenmax_pkd; 3523 __u8 pdusinplenmax_pkd; 3524 __u8 r10; 3525 }; 3526 3527 #define S_FW_TLSTX_DATA_WR_OPCODE 24 3528 #define M_FW_TLSTX_DATA_WR_OPCODE 0xff 3529 #define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE) 3530 #define G_FW_TLSTX_DATA_WR_OPCODE(x) \ 3531 (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE) 3532 3533 #define S_FW_TLSTX_DATA_WR_COMPL 21 3534 #define M_FW_TLSTX_DATA_WR_COMPL 0x1 3535 #define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL) 3536 #define G_FW_TLSTX_DATA_WR_COMPL(x) \ 3537 (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL) 3538 #define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U) 3539 3540 #define S_FW_TLSTX_DATA_WR_IMMDLEN 0 3541 #define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff 3542 #define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN) 3543 #define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \ 3544 (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN) 3545 3546 #define S_FW_TLSTX_DATA_WR_FLOWID 8 3547 #define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff 3548 #define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID) 3549 #define G_FW_TLSTX_DATA_WR_FLOWID(x) \ 3550 (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID) 3551 3552 #define S_FW_TLSTX_DATA_WR_LEN16 0 3553 #define M_FW_TLSTX_DATA_WR_LEN16 0xff 3554 #define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16) 3555 #define G_FW_TLSTX_DATA_WR_LEN16(x) \ 3556 (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16) 3557 3558 #define S_FW_TLSTX_DATA_WR_LSODISABLE 31 3559 #define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1 3560 #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3561 ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE) 3562 #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3563 (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE) 3564 #define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U) 3565 3566 #define S_FW_TLSTX_DATA_WR_ALIGNPLD 30 3567 #define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1 3568 #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD) 3569 #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \ 3570 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD) 3571 #define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U) 3572 3573 #define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29 3574 #define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1 3575 #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3576 ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3577 #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3578 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \ 3579 M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3580 #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U) 3581 3582 #define S_FW_TLSTX_DATA_WR_FLAGS 0 3583 #define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff 3584 #define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS) 3585 #define G_FW_TLSTX_DATA_WR_FLAGS(x) \ 3586 (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS) 3587 3588 #define S_FW_TLSTX_DATA_WR_CTXLOC 30 3589 #define M_FW_TLSTX_DATA_WR_CTXLOC 0x3 3590 #define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC) 3591 #define G_FW_TLSTX_DATA_WR_CTXLOC(x) \ 3592 (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC) 3593 3594 #define S_FW_TLSTX_DATA_WR_IVDSGL 29 3595 #define M_FW_TLSTX_DATA_WR_IVDSGL 0x1 3596 #define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL) 3597 #define G_FW_TLSTX_DATA_WR_IVDSGL(x) \ 3598 (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL) 3599 #define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U) 3600 3601 #define S_FW_TLSTX_DATA_WR_KEYSIZE 24 3602 #define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f 3603 #define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE) 3604 #define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \ 3605 (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE) 3606 3607 #define S_FW_TLSTX_DATA_WR_NUMIVS 14 3608 #define M_FW_TLSTX_DATA_WR_NUMIVS 0xff 3609 #define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS) 3610 #define G_FW_TLSTX_DATA_WR_NUMIVS(x) \ 3611 (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS) 3612 3613 #define S_FW_TLSTX_DATA_WR_EXP 0 3614 #define M_FW_TLSTX_DATA_WR_EXP 0x3fff 3615 #define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP) 3616 #define G_FW_TLSTX_DATA_WR_EXP(x) \ 3617 (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP) 3618 3619 #define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1 3620 #define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff 3621 #define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3622 ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3623 #define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3624 (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \ 3625 M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3626 3627 #define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4 3628 #define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff 3629 #define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3630 ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3631 #define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3632 (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \ 3633 M_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3634 3635 #define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2 3636 #define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f 3637 #define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3638 ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3639 #define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3640 (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \ 3641 M_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3642 3643 struct fw_tls_keyctx_tx_wr { 3644 __be32 op_to_compl; 3645 __be32 flowid_len16; 3646 union fw_key_ctx { 3647 struct fw_tx_keyctx_hdr { 3648 __u8 ctxlen; 3649 __u8 r2; 3650 __be16 dualck_to_txvalid; 3651 __u8 txsalt[4]; 3652 __be64 r5; 3653 } txhdr; 3654 struct fw_rx_keyctx_hdr { 3655 __u8 flitcnt_hmacctrl; 3656 __u8 protover_ciphmode; 3657 __u8 authmode_to_rxvalid; 3658 __u8 ivpresent_to_rxmk_size; 3659 __u8 rxsalt[4]; 3660 __be64 ivinsert_to_authinsrt; 3661 } rxhdr; 3662 struct fw_keyctx_clear { 3663 __be32 tx_key; 3664 __be32 rx_key; 3665 } kctx_clr; 3666 } u; 3667 struct keys { 3668 __u8 edkey[32]; 3669 __u8 ipad[64]; 3670 __u8 opad[64]; 3671 } keys; 3672 __u8 reneg_to_write_rx; 3673 __u8 protocol; 3674 __be16 mfs; 3675 __be32 ftid; 3676 }; 3677 3678 #define S_FW_TLS_KEYCTX_TX_WR_OPCODE 24 3679 #define M_FW_TLS_KEYCTX_TX_WR_OPCODE 0xff 3680 #define V_FW_TLS_KEYCTX_TX_WR_OPCODE(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_OPCODE) 3681 #define G_FW_TLS_KEYCTX_TX_WR_OPCODE(x) \ 3682 (((x) >> S_FW_TLS_KEYCTX_TX_WR_OPCODE) & M_FW_TLS_KEYCTX_TX_WR_OPCODE) 3683 3684 #define S_FW_TLS_KEYCTX_TX_WR_ATOMIC 23 3685 #define M_FW_TLS_KEYCTX_TX_WR_ATOMIC 0x1 3686 #define V_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_ATOMIC) 3687 #define G_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) \ 3688 (((x) >> S_FW_TLS_KEYCTX_TX_WR_ATOMIC) & M_FW_TLS_KEYCTX_TX_WR_ATOMIC) 3689 #define F_FW_TLS_KEYCTX_TX_WR_ATOMIC V_FW_TLS_KEYCTX_TX_WR_ATOMIC(1U) 3690 3691 #define S_FW_TLS_KEYCTX_TX_WR_FLUSH 22 3692 #define M_FW_TLS_KEYCTX_TX_WR_FLUSH 0x1 3693 #define V_FW_TLS_KEYCTX_TX_WR_FLUSH(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLUSH) 3694 #define G_FW_TLS_KEYCTX_TX_WR_FLUSH(x) \ 3695 (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLUSH) & M_FW_TLS_KEYCTX_TX_WR_FLUSH) 3696 #define F_FW_TLS_KEYCTX_TX_WR_FLUSH V_FW_TLS_KEYCTX_TX_WR_FLUSH(1U) 3697 3698 #define S_FW_TLS_KEYCTX_TX_WR_COMPL 21 3699 #define M_FW_TLS_KEYCTX_TX_WR_COMPL 0x1 3700 #define V_FW_TLS_KEYCTX_TX_WR_COMPL(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_COMPL) 3701 #define G_FW_TLS_KEYCTX_TX_WR_COMPL(x) \ 3702 (((x) >> S_FW_TLS_KEYCTX_TX_WR_COMPL) & M_FW_TLS_KEYCTX_TX_WR_COMPL) 3703 #define F_FW_TLS_KEYCTX_TX_WR_COMPL V_FW_TLS_KEYCTX_TX_WR_COMPL(1U) 3704 3705 #define S_FW_TLS_KEYCTX_TX_WR_FLOWID 8 3706 #define M_FW_TLS_KEYCTX_TX_WR_FLOWID 0xfffff 3707 #define V_FW_TLS_KEYCTX_TX_WR_FLOWID(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLOWID) 3708 #define G_FW_TLS_KEYCTX_TX_WR_FLOWID(x) \ 3709 (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLOWID) & M_FW_TLS_KEYCTX_TX_WR_FLOWID) 3710 3711 #define S_FW_TLS_KEYCTX_TX_WR_LEN16 0 3712 #define M_FW_TLS_KEYCTX_TX_WR_LEN16 0xff 3713 #define V_FW_TLS_KEYCTX_TX_WR_LEN16(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_LEN16) 3714 #define G_FW_TLS_KEYCTX_TX_WR_LEN16(x) \ 3715 (((x) >> S_FW_TLS_KEYCTX_TX_WR_LEN16) & M_FW_TLS_KEYCTX_TX_WR_LEN16) 3716 3717 #define S_FW_TLS_KEYCTX_TX_WR_DUALCK 12 3718 #define M_FW_TLS_KEYCTX_TX_WR_DUALCK 0x1 3719 #define V_FW_TLS_KEYCTX_TX_WR_DUALCK(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_DUALCK) 3720 #define G_FW_TLS_KEYCTX_TX_WR_DUALCK(x) \ 3721 (((x) >> S_FW_TLS_KEYCTX_TX_WR_DUALCK) & M_FW_TLS_KEYCTX_TX_WR_DUALCK) 3722 #define F_FW_TLS_KEYCTX_TX_WR_DUALCK V_FW_TLS_KEYCTX_TX_WR_DUALCK(1U) 3723 3724 #define S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 11 3725 #define M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 0x1 3726 #define V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \ 3727 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) 3728 #define G_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \ 3729 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) & \ 3730 M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) 3731 #define F_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT \ 3732 V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(1U) 3733 3734 #define S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 10 3735 #define M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 0x1 3736 #define V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \ 3737 ((x) << S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) 3738 #define G_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \ 3739 (((x) >> S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) & \ 3740 M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) 3741 #define F_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT \ 3742 V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(1U) 3743 3744 #define S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 6 3745 #define M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 0xf 3746 #define V_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \ 3747 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) 3748 #define G_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \ 3749 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) & \ 3750 M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) 3751 3752 #define S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 2 3753 #define M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 0xf 3754 #define V_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \ 3755 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) 3756 #define G_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \ 3757 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) & \ 3758 M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) 3759 3760 #define S_FW_TLS_KEYCTX_TX_WR_TXVALID 0 3761 #define M_FW_TLS_KEYCTX_TX_WR_TXVALID 0x1 3762 #define V_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \ 3763 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXVALID) 3764 #define G_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \ 3765 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXVALID) & M_FW_TLS_KEYCTX_TX_WR_TXVALID) 3766 #define F_FW_TLS_KEYCTX_TX_WR_TXVALID V_FW_TLS_KEYCTX_TX_WR_TXVALID(1U) 3767 3768 #define S_FW_TLS_KEYCTX_TX_WR_FLITCNT 3 3769 #define M_FW_TLS_KEYCTX_TX_WR_FLITCNT 0x1f 3770 #define V_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \ 3771 ((x) << S_FW_TLS_KEYCTX_TX_WR_FLITCNT) 3772 #define G_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \ 3773 (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLITCNT) & M_FW_TLS_KEYCTX_TX_WR_FLITCNT) 3774 3775 #define S_FW_TLS_KEYCTX_TX_WR_HMACCTRL 0 3776 #define M_FW_TLS_KEYCTX_TX_WR_HMACCTRL 0x7 3777 #define V_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \ 3778 ((x) << S_FW_TLS_KEYCTX_TX_WR_HMACCTRL) 3779 #define G_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \ 3780 (((x) >> S_FW_TLS_KEYCTX_TX_WR_HMACCTRL) & M_FW_TLS_KEYCTX_TX_WR_HMACCTRL) 3781 3782 #define S_FW_TLS_KEYCTX_TX_WR_PROTOVER 4 3783 #define M_FW_TLS_KEYCTX_TX_WR_PROTOVER 0xf 3784 #define V_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \ 3785 ((x) << S_FW_TLS_KEYCTX_TX_WR_PROTOVER) 3786 #define G_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \ 3787 (((x) >> S_FW_TLS_KEYCTX_TX_WR_PROTOVER) & M_FW_TLS_KEYCTX_TX_WR_PROTOVER) 3788 3789 #define S_FW_TLS_KEYCTX_TX_WR_CIPHMODE 0 3790 #define M_FW_TLS_KEYCTX_TX_WR_CIPHMODE 0xf 3791 #define V_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \ 3792 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHMODE) 3793 #define G_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \ 3794 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHMODE) & M_FW_TLS_KEYCTX_TX_WR_CIPHMODE) 3795 3796 #define S_FW_TLS_KEYCTX_TX_WR_AUTHMODE 4 3797 #define M_FW_TLS_KEYCTX_TX_WR_AUTHMODE 0xf 3798 #define V_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \ 3799 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHMODE) 3800 #define G_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \ 3801 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHMODE) & M_FW_TLS_KEYCTX_TX_WR_AUTHMODE) 3802 3803 #define S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 3 3804 #define M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 0x1 3805 #define V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \ 3806 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) 3807 #define G_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \ 3808 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) & \ 3809 M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) 3810 #define F_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL \ 3811 V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(1U) 3812 3813 #define S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 1 3814 #define M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 0x3 3815 #define V_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \ 3816 ((x) << S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) 3817 #define G_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \ 3818 (((x) >> S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) & \ 3819 M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) 3820 3821 #define S_FW_TLS_KEYCTX_TX_WR_RXVALID 0 3822 #define M_FW_TLS_KEYCTX_TX_WR_RXVALID 0x1 3823 #define V_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \ 3824 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXVALID) 3825 #define G_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \ 3826 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXVALID) & M_FW_TLS_KEYCTX_TX_WR_RXVALID) 3827 #define F_FW_TLS_KEYCTX_TX_WR_RXVALID V_FW_TLS_KEYCTX_TX_WR_RXVALID(1U) 3828 3829 #define S_FW_TLS_KEYCTX_TX_WR_IVPRESENT 7 3830 #define M_FW_TLS_KEYCTX_TX_WR_IVPRESENT 0x1 3831 #define V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \ 3832 ((x) << S_FW_TLS_KEYCTX_TX_WR_IVPRESENT) 3833 #define G_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \ 3834 (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVPRESENT) & \ 3835 M_FW_TLS_KEYCTX_TX_WR_IVPRESENT) 3836 #define F_FW_TLS_KEYCTX_TX_WR_IVPRESENT V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(1U) 3837 3838 #define S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 6 3839 #define M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 0x1 3840 #define V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \ 3841 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) 3842 #define G_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \ 3843 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) & \ 3844 M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) 3845 #define F_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT \ 3846 V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(1U) 3847 3848 #define S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 3 3849 #define M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 0x7 3850 #define V_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \ 3851 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) 3852 #define G_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \ 3853 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) & \ 3854 M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) 3855 3856 #define S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0 3857 #define M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0x7 3858 #define V_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \ 3859 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) 3860 #define G_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \ 3861 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) & \ 3862 M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) 3863 3864 #define S_FW_TLS_KEYCTX_TX_WR_IVINSERT 55 3865 #define M_FW_TLS_KEYCTX_TX_WR_IVINSERT 0x1ffULL 3866 #define V_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \ 3867 ((x) << S_FW_TLS_KEYCTX_TX_WR_IVINSERT) 3868 #define G_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \ 3869 (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVINSERT) & M_FW_TLS_KEYCTX_TX_WR_IVINSERT) 3870 3871 #define S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 47 3872 #define M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 0xffULL 3873 #define V_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \ 3874 ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) 3875 #define G_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \ 3876 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) & \ 3877 M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) 3878 3879 #define S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 39 3880 #define M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 0xffULL 3881 #define V_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \ 3882 ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) 3883 #define G_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \ 3884 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) & \ 3885 M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) 3886 3887 #define S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 30 3888 #define M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 0x1ffULL 3889 #define V_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \ 3890 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) 3891 #define G_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \ 3892 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) & \ 3893 M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) 3894 3895 #define S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 23 3896 #define M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 0x7f 3897 #define V_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \ 3898 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) 3899 #define G_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \ 3900 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) & \ 3901 M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) 3902 3903 #define S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 14 3904 #define M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 0x1ff 3905 #define V_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \ 3906 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) 3907 #define G_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \ 3908 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) & \ 3909 M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) 3910 3911 #define S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 7 3912 #define M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 0x7f 3913 #define V_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \ 3914 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) 3915 #define G_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \ 3916 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) & \ 3917 M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) 3918 3919 #define S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0 3920 #define M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0x7f 3921 #define V_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \ 3922 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) 3923 #define G_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \ 3924 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) & \ 3925 M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) 3926 3927 #define S_FW_TLS_KEYCTX_TX_WR_RENEG 4 3928 #define M_FW_TLS_KEYCTX_TX_WR_RENEG 0x1 3929 #define V_FW_TLS_KEYCTX_TX_WR_RENEG(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_RENEG) 3930 #define G_FW_TLS_KEYCTX_TX_WR_RENEG(x) \ 3931 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RENEG) & M_FW_TLS_KEYCTX_TX_WR_RENEG) 3932 #define F_FW_TLS_KEYCTX_TX_WR_RENEG V_FW_TLS_KEYCTX_TX_WR_RENEG(1U) 3933 3934 #define S_FW_TLS_KEYCTX_TX_WR_DELETE_TX 3 3935 #define M_FW_TLS_KEYCTX_TX_WR_DELETE_TX 0x1 3936 #define V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \ 3937 ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_TX) 3938 #define G_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \ 3939 (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_TX) & \ 3940 M_FW_TLS_KEYCTX_TX_WR_DELETE_TX) 3941 #define F_FW_TLS_KEYCTX_TX_WR_DELETE_TX V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(1U) 3942 3943 #define S_FW_TLS_KEYCTX_TX_WR_DELETE_RX 2 3944 #define M_FW_TLS_KEYCTX_TX_WR_DELETE_RX 0x1 3945 #define V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \ 3946 ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_RX) 3947 #define G_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \ 3948 (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_RX) & \ 3949 M_FW_TLS_KEYCTX_TX_WR_DELETE_RX) 3950 #define F_FW_TLS_KEYCTX_TX_WR_DELETE_RX V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(1U) 3951 3952 #define S_FW_TLS_KEYCTX_TX_WR_WRITE_TX 1 3953 #define M_FW_TLS_KEYCTX_TX_WR_WRITE_TX 0x1 3954 #define V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \ 3955 ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_TX) 3956 #define G_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \ 3957 (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_TX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_TX) 3958 #define F_FW_TLS_KEYCTX_TX_WR_WRITE_TX V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(1U) 3959 3960 #define S_FW_TLS_KEYCTX_TX_WR_WRITE_RX 0 3961 #define M_FW_TLS_KEYCTX_TX_WR_WRITE_RX 0x1 3962 #define V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \ 3963 ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_RX) 3964 #define G_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \ 3965 (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_RX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_RX) 3966 #define F_FW_TLS_KEYCTX_TX_WR_WRITE_RX V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(1U) 3967 3968 struct fw_crypto_lookaside_wr { 3969 __be32 op_to_cctx_size; 3970 __be32 len16_pkd; 3971 __be32 session_id; 3972 __be32 rx_chid_to_rx_q_id; 3973 __be32 key_addr; 3974 __be32 pld_size_hash_size; 3975 __be64 cookie; 3976 }; 3977 3978 #define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24 3979 #define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff 3980 #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3981 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3982 #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3983 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \ 3984 M_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3985 3986 #define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23 3987 #define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1 3988 #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3989 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3990 #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3991 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \ 3992 M_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3993 #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U) 3994 3995 #define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15 3996 #define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff 3997 #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 3998 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 3999 #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 4000 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \ 4001 M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 4002 4003 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5 4004 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3 4005 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 4006 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 4007 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 4008 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \ 4009 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 4010 4011 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0 4012 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f 4013 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 4014 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 4015 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 4016 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \ 4017 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 4018 4019 #define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0 4020 #define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff 4021 #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 4022 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16) 4023 #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 4024 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \ 4025 M_FW_CRYPTO_LOOKASIDE_WR_LEN16) 4026 4027 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29 4028 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3 4029 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 4030 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 4031 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 4032 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \ 4033 M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 4034 4035 #define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27 4036 #define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3 4037 #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 4038 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB) 4039 #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 4040 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB) 4041 4042 #define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25 4043 #define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3 4044 #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4045 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4046 #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4047 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \ 4048 M_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4049 4050 #define S_FW_CRYPTO_LOOKASIDE_WR_IV 23 4051 #define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3 4052 #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4053 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV) 4054 #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4055 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV) 4056 4057 #define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15 4058 #define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff 4059 #define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4060 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4061 #define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4062 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\ 4063 M_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4064 4065 #define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10 4066 #define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3 4067 #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4068 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4069 #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4070 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \ 4071 M_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4072 4073 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0 4074 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff 4075 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4076 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4077 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4078 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \ 4079 M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4080 4081 #define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24 4082 #define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff 4083 #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4084 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4085 #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4086 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \ 4087 M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4088 4089 #define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17 4090 #define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f 4091 #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4092 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4093 #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4094 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \ 4095 M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4096 4097 /****************************************************************************** 4098 * C O M M A N D s 4099 *********************/ 4100 4101 /* 4102 * The maximum length of time, in miliseconds, that we expect any firmware 4103 * command to take to execute and return a reply to the host. The RESET 4104 * and INITIALIZE commands can take a fair amount of time to execute but 4105 * most execute in far less time than this maximum. This constant is used 4106 * by host software to determine how long to wait for a firmware command 4107 * reply before declaring the firmware as dead/unreachable ... 4108 */ 4109 #define FW_CMD_MAX_TIMEOUT 10000 4110 4111 /* 4112 * If a host driver does a HELLO and discovers that there's already a MASTER 4113 * selected, we may have to wait for that MASTER to finish issuing RESET, 4114 * configuration and INITIALIZE commands. Also, there's a possibility that 4115 * our own HELLO may get lost if it happens right as the MASTER is issuign a 4116 * RESET command, so we need to be willing to make a few retries of our HELLO. 4117 */ 4118 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 4119 #define FW_CMD_HELLO_RETRIES 3 4120 4121 enum fw_cmd_opcodes { 4122 FW_LDST_CMD = 0x01, 4123 FW_RESET_CMD = 0x03, 4124 FW_HELLO_CMD = 0x04, 4125 FW_BYE_CMD = 0x05, 4126 FW_INITIALIZE_CMD = 0x06, 4127 FW_CAPS_CONFIG_CMD = 0x07, 4128 FW_PARAMS_CMD = 0x08, 4129 FW_PFVF_CMD = 0x09, 4130 FW_IQ_CMD = 0x10, 4131 FW_EQ_MNGT_CMD = 0x11, 4132 FW_EQ_ETH_CMD = 0x12, 4133 FW_EQ_CTRL_CMD = 0x13, 4134 FW_EQ_OFLD_CMD = 0x21, 4135 FW_VI_CMD = 0x14, 4136 FW_VI_MAC_CMD = 0x15, 4137 FW_VI_RXMODE_CMD = 0x16, 4138 FW_VI_ENABLE_CMD = 0x17, 4139 FW_VI_STATS_CMD = 0x1a, 4140 FW_ACL_MAC_CMD = 0x18, 4141 FW_ACL_VLAN_CMD = 0x19, 4142 FW_PORT_CMD = 0x1b, 4143 FW_PORT_STATS_CMD = 0x1c, 4144 FW_PORT_LB_STATS_CMD = 0x1d, 4145 FW_PORT_TRACE_CMD = 0x1e, 4146 FW_PORT_TRACE_MMAP_CMD = 0x1f, 4147 FW_RSS_IND_TBL_CMD = 0x20, 4148 FW_RSS_GLB_CONFIG_CMD = 0x22, 4149 FW_RSS_VI_CONFIG_CMD = 0x23, 4150 FW_SCHED_CMD = 0x24, 4151 FW_DEVLOG_CMD = 0x25, 4152 FW_WATCHDOG_CMD = 0x27, 4153 FW_CLIP_CMD = 0x28, 4154 FW_CHNET_IFACE_CMD = 0x26, 4155 FW_FCOE_RES_INFO_CMD = 0x31, 4156 FW_FCOE_LINK_CMD = 0x32, 4157 FW_FCOE_VNP_CMD = 0x33, 4158 FW_FCOE_SPARAMS_CMD = 0x35, 4159 FW_FCOE_STATS_CMD = 0x37, 4160 FW_FCOE_FCF_CMD = 0x38, 4161 FW_DCB_IEEE_CMD = 0x3a, 4162 FW_DIAG_CMD = 0x3d, 4163 FW_PTP_CMD = 0x3e, 4164 FW_LASTC2E_CMD = 0x40, 4165 FW_ERROR_CMD = 0x80, 4166 FW_DEBUG_CMD = 0x81, 4167 }; 4168 4169 enum fw_cmd_cap { 4170 FW_CMD_CAP_PF = 0x01, 4171 FW_CMD_CAP_DMAQ = 0x02, 4172 FW_CMD_CAP_PORT = 0x04, 4173 FW_CMD_CAP_PORTPROMISC = 0x08, 4174 FW_CMD_CAP_PORTSTATS = 0x10, 4175 FW_CMD_CAP_VF = 0x80, 4176 }; 4177 4178 /* 4179 * Generic command header flit0 4180 */ 4181 struct fw_cmd_hdr { 4182 __be32 hi; 4183 __be32 lo; 4184 }; 4185 4186 #define S_FW_CMD_OP 24 4187 #define M_FW_CMD_OP 0xff 4188 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 4189 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 4190 4191 #define S_FW_CMD_REQUEST 23 4192 #define M_FW_CMD_REQUEST 0x1 4193 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 4194 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 4195 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 4196 4197 #define S_FW_CMD_READ 22 4198 #define M_FW_CMD_READ 0x1 4199 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 4200 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 4201 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 4202 4203 #define S_FW_CMD_WRITE 21 4204 #define M_FW_CMD_WRITE 0x1 4205 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 4206 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 4207 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 4208 4209 #define S_FW_CMD_EXEC 20 4210 #define M_FW_CMD_EXEC 0x1 4211 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 4212 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 4213 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 4214 4215 #define S_FW_CMD_RAMASK 20 4216 #define M_FW_CMD_RAMASK 0xf 4217 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 4218 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 4219 4220 #define S_FW_CMD_RETVAL 8 4221 #define M_FW_CMD_RETVAL 0xff 4222 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 4223 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 4224 4225 #define S_FW_CMD_LEN16 0 4226 #define M_FW_CMD_LEN16 0xff 4227 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 4228 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 4229 4230 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 4231 4232 /* 4233 * address spaces 4234 */ 4235 enum fw_ldst_addrspc { 4236 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 4237 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 4238 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 4239 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 4240 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 4241 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 4242 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 4243 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 4244 FW_LDST_ADDRSPC_MDIO = 0x0018, 4245 FW_LDST_ADDRSPC_MPS = 0x0020, 4246 FW_LDST_ADDRSPC_FUNC = 0x0028, 4247 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 4248 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 4249 FW_LDST_ADDRSPC_LE = 0x0030, 4250 FW_LDST_ADDRSPC_I2C = 0x0038, 4251 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 4252 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 4253 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 4254 FW_LDST_ADDRSPC_CIM_Q = 0x0048, 4255 }; 4256 4257 /* 4258 * MDIO VSC8634 register access control field 4259 */ 4260 enum fw_ldst_mdio_vsc8634_aid { 4261 FW_LDST_MDIO_VS_STANDARD, 4262 FW_LDST_MDIO_VS_EXTENDED, 4263 FW_LDST_MDIO_VS_GPIO 4264 }; 4265 4266 enum fw_ldst_mps_fid { 4267 FW_LDST_MPS_ATRB, 4268 FW_LDST_MPS_RPLC 4269 }; 4270 4271 enum fw_ldst_func_access_ctl { 4272 FW_LDST_FUNC_ACC_CTL_VIID, 4273 FW_LDST_FUNC_ACC_CTL_FID 4274 }; 4275 4276 enum fw_ldst_func_mod_index { 4277 FW_LDST_FUNC_MPS 4278 }; 4279 4280 struct fw_ldst_cmd { 4281 __be32 op_to_addrspace; 4282 __be32 cycles_to_len16; 4283 union fw_ldst { 4284 struct fw_ldst_addrval { 4285 __be32 addr; 4286 __be32 val; 4287 } addrval; 4288 struct fw_ldst_idctxt { 4289 __be32 physid; 4290 __be32 msg_ctxtflush; 4291 __be32 ctxt_data7; 4292 __be32 ctxt_data6; 4293 __be32 ctxt_data5; 4294 __be32 ctxt_data4; 4295 __be32 ctxt_data3; 4296 __be32 ctxt_data2; 4297 __be32 ctxt_data1; 4298 __be32 ctxt_data0; 4299 } idctxt; 4300 struct fw_ldst_mdio { 4301 __be16 paddr_mmd; 4302 __be16 raddr; 4303 __be16 vctl; 4304 __be16 rval; 4305 } mdio; 4306 struct fw_ldst_cim_rq { 4307 __u8 req_first64[8]; 4308 __u8 req_second64[8]; 4309 __u8 resp_first64[8]; 4310 __u8 resp_second64[8]; 4311 __be32 r3[2]; 4312 } cim_rq; 4313 union fw_ldst_mps { 4314 struct fw_ldst_mps_rplc { 4315 __be16 fid_idx; 4316 __be16 rplcpf_pkd; 4317 __be32 rplc255_224; 4318 __be32 rplc223_192; 4319 __be32 rplc191_160; 4320 __be32 rplc159_128; 4321 __be32 rplc127_96; 4322 __be32 rplc95_64; 4323 __be32 rplc63_32; 4324 __be32 rplc31_0; 4325 } rplc; 4326 struct fw_ldst_mps_atrb { 4327 __be16 fid_mpsid; 4328 __be16 r2[3]; 4329 __be32 r3[2]; 4330 __be32 r4; 4331 __be32 atrb; 4332 __be16 vlan[16]; 4333 } atrb; 4334 } mps; 4335 struct fw_ldst_func { 4336 __u8 access_ctl; 4337 __u8 mod_index; 4338 __be16 ctl_id; 4339 __be32 offset; 4340 __be64 data0; 4341 __be64 data1; 4342 } func; 4343 struct fw_ldst_pcie { 4344 __u8 ctrl_to_fn; 4345 __u8 bnum; 4346 __u8 r; 4347 __u8 ext_r; 4348 __u8 select_naccess; 4349 __u8 pcie_fn; 4350 __be16 nset_pkd; 4351 __be32 data[12]; 4352 } pcie; 4353 struct fw_ldst_i2c_deprecated { 4354 __u8 pid_pkd; 4355 __u8 base; 4356 __u8 boffset; 4357 __u8 data; 4358 __be32 r9; 4359 } i2c_deprecated; 4360 struct fw_ldst_i2c { 4361 __u8 pid; 4362 __u8 did; 4363 __u8 boffset; 4364 __u8 blen; 4365 __be32 r9; 4366 __u8 data[48]; 4367 } i2c; 4368 struct fw_ldst_le { 4369 __be32 index; 4370 __be32 r9; 4371 __u8 val[33]; 4372 __u8 r11[7]; 4373 } le; 4374 } u; 4375 }; 4376 4377 #define S_FW_LDST_CMD_ADDRSPACE 0 4378 #define M_FW_LDST_CMD_ADDRSPACE 0xff 4379 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 4380 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 4381 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 4382 4383 #define S_FW_LDST_CMD_CYCLES 16 4384 #define M_FW_LDST_CMD_CYCLES 0xffff 4385 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 4386 #define G_FW_LDST_CMD_CYCLES(x) \ 4387 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 4388 4389 #define S_FW_LDST_CMD_MSG 31 4390 #define M_FW_LDST_CMD_MSG 0x1 4391 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 4392 #define G_FW_LDST_CMD_MSG(x) \ 4393 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 4394 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 4395 4396 #define S_FW_LDST_CMD_CTXTFLUSH 30 4397 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 4398 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 4399 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 4400 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 4401 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 4402 4403 #define S_FW_LDST_CMD_PADDR 8 4404 #define M_FW_LDST_CMD_PADDR 0x1f 4405 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 4406 #define G_FW_LDST_CMD_PADDR(x) \ 4407 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 4408 4409 #define S_FW_LDST_CMD_MMD 0 4410 #define M_FW_LDST_CMD_MMD 0x1f 4411 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 4412 #define G_FW_LDST_CMD_MMD(x) \ 4413 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 4414 4415 #define S_FW_LDST_CMD_FID 15 4416 #define M_FW_LDST_CMD_FID 0x1 4417 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 4418 #define G_FW_LDST_CMD_FID(x) \ 4419 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 4420 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 4421 4422 #define S_FW_LDST_CMD_IDX 0 4423 #define M_FW_LDST_CMD_IDX 0x7fff 4424 #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) 4425 #define G_FW_LDST_CMD_IDX(x) \ 4426 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) 4427 4428 #define S_FW_LDST_CMD_RPLCPF 0 4429 #define M_FW_LDST_CMD_RPLCPF 0xff 4430 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 4431 #define G_FW_LDST_CMD_RPLCPF(x) \ 4432 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 4433 4434 #define S_FW_LDST_CMD_MPSID 0 4435 #define M_FW_LDST_CMD_MPSID 0x7fff 4436 #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) 4437 #define G_FW_LDST_CMD_MPSID(x) \ 4438 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) 4439 4440 #define S_FW_LDST_CMD_CTRL 7 4441 #define M_FW_LDST_CMD_CTRL 0x1 4442 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 4443 #define G_FW_LDST_CMD_CTRL(x) \ 4444 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 4445 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 4446 4447 #define S_FW_LDST_CMD_LC 4 4448 #define M_FW_LDST_CMD_LC 0x1 4449 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 4450 #define G_FW_LDST_CMD_LC(x) \ 4451 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 4452 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 4453 4454 #define S_FW_LDST_CMD_AI 3 4455 #define M_FW_LDST_CMD_AI 0x1 4456 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 4457 #define G_FW_LDST_CMD_AI(x) \ 4458 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 4459 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 4460 4461 #define S_FW_LDST_CMD_FN 0 4462 #define M_FW_LDST_CMD_FN 0x7 4463 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 4464 #define G_FW_LDST_CMD_FN(x) \ 4465 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 4466 4467 #define S_FW_LDST_CMD_SELECT 4 4468 #define M_FW_LDST_CMD_SELECT 0xf 4469 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 4470 #define G_FW_LDST_CMD_SELECT(x) \ 4471 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 4472 4473 #define S_FW_LDST_CMD_NACCESS 0 4474 #define M_FW_LDST_CMD_NACCESS 0xf 4475 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 4476 #define G_FW_LDST_CMD_NACCESS(x) \ 4477 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 4478 4479 #define S_FW_LDST_CMD_NSET 14 4480 #define M_FW_LDST_CMD_NSET 0x3 4481 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 4482 #define G_FW_LDST_CMD_NSET(x) \ 4483 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 4484 4485 #define S_FW_LDST_CMD_PID 6 4486 #define M_FW_LDST_CMD_PID 0x3 4487 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 4488 #define G_FW_LDST_CMD_PID(x) \ 4489 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 4490 4491 struct fw_reset_cmd { 4492 __be32 op_to_write; 4493 __be32 retval_len16; 4494 __be32 val; 4495 __be32 halt_pkd; 4496 }; 4497 4498 #define S_FW_RESET_CMD_HALT 31 4499 #define M_FW_RESET_CMD_HALT 0x1 4500 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 4501 #define G_FW_RESET_CMD_HALT(x) \ 4502 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 4503 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 4504 4505 enum { 4506 FW_HELLO_CMD_STAGE_OS = 0, 4507 FW_HELLO_CMD_STAGE_PREOS0 = 1, 4508 FW_HELLO_CMD_STAGE_PREOS1 = 2, 4509 FW_HELLO_CMD_STAGE_POSTOS = 3, 4510 }; 4511 4512 struct fw_hello_cmd { 4513 __be32 op_to_write; 4514 __be32 retval_len16; 4515 __be32 err_to_clearinit; 4516 __be32 fwrev; 4517 }; 4518 4519 #define S_FW_HELLO_CMD_ERR 31 4520 #define M_FW_HELLO_CMD_ERR 0x1 4521 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 4522 #define G_FW_HELLO_CMD_ERR(x) \ 4523 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 4524 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 4525 4526 #define S_FW_HELLO_CMD_INIT 30 4527 #define M_FW_HELLO_CMD_INIT 0x1 4528 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 4529 #define G_FW_HELLO_CMD_INIT(x) \ 4530 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 4531 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 4532 4533 #define S_FW_HELLO_CMD_MASTERDIS 29 4534 #define M_FW_HELLO_CMD_MASTERDIS 0x1 4535 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 4536 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 4537 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 4538 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 4539 4540 #define S_FW_HELLO_CMD_MASTERFORCE 28 4541 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 4542 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 4543 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 4544 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 4545 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 4546 4547 #define S_FW_HELLO_CMD_MBMASTER 24 4548 #define M_FW_HELLO_CMD_MBMASTER 0xf 4549 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 4550 #define G_FW_HELLO_CMD_MBMASTER(x) \ 4551 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 4552 4553 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 4554 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 4555 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 4556 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 4557 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 4558 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 4559 4560 #define S_FW_HELLO_CMD_MBASYNCNOT 20 4561 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 4562 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 4563 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 4564 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 4565 4566 #define S_FW_HELLO_CMD_STAGE 17 4567 #define M_FW_HELLO_CMD_STAGE 0x7 4568 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 4569 #define G_FW_HELLO_CMD_STAGE(x) \ 4570 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 4571 4572 #define S_FW_HELLO_CMD_CLEARINIT 16 4573 #define M_FW_HELLO_CMD_CLEARINIT 0x1 4574 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 4575 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 4576 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 4577 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 4578 4579 struct fw_bye_cmd { 4580 __be32 op_to_write; 4581 __be32 retval_len16; 4582 __be64 r3; 4583 }; 4584 4585 struct fw_initialize_cmd { 4586 __be32 op_to_write; 4587 __be32 retval_len16; 4588 __be64 r3; 4589 }; 4590 4591 enum fw_caps_config_hm { 4592 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 4593 FW_CAPS_CONFIG_HM_PL = 0x00000002, 4594 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 4595 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 4596 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 4597 FW_CAPS_CONFIG_HM_TP = 0x00000020, 4598 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 4599 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 4600 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 4601 FW_CAPS_CONFIG_HM_MC = 0x00000200, 4602 FW_CAPS_CONFIG_HM_LE = 0x00000400, 4603 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 4604 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 4605 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 4606 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 4607 FW_CAPS_CONFIG_HM_MI = 0x00008000, 4608 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 4609 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 4610 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 4611 FW_CAPS_CONFIG_HM_MA = 0x00080000, 4612 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 4613 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 4614 FW_CAPS_CONFIG_HM_UART = 0x00400000, 4615 FW_CAPS_CONFIG_HM_SF = 0x00800000, 4616 }; 4617 4618 /* 4619 * The VF Register Map. 4620 * 4621 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 4622 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 4623 * the Slice to Module Map Table (see below) in the Physical Function Register 4624 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 4625 * and Offset registers in the PF Register Map. The MBDATA base address is 4626 * quite constrained as it determines the Mailbox Data addresses for both PFs 4627 * and VFs, and therefore must fit in both the VF and PF Register Maps without 4628 * overlapping other registers. 4629 */ 4630 #define FW_T4VF_SGE_BASE_ADDR 0x0000 4631 #define FW_T4VF_MPS_BASE_ADDR 0x0100 4632 #define FW_T4VF_PL_BASE_ADDR 0x0200 4633 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 4634 #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */ 4635 #define FW_T4VF_CIM_BASE_ADDR 0x0300 4636 4637 #define FW_T4VF_REGMAP_START 0x0000 4638 #define FW_T4VF_REGMAP_SIZE 0x0400 4639 4640 enum fw_caps_config_nbm { 4641 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 4642 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 4643 }; 4644 4645 enum fw_caps_config_link { 4646 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 4647 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 4648 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 4649 }; 4650 4651 enum fw_caps_config_switch { 4652 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 4653 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 4654 }; 4655 4656 enum fw_caps_config_nic { 4657 FW_CAPS_CONFIG_NIC = 0x00000001, 4658 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 4659 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 4660 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 4661 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 4662 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 4663 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 4664 }; 4665 4666 enum fw_caps_config_toe { 4667 FW_CAPS_CONFIG_TOE = 0x00000001, 4668 }; 4669 4670 enum fw_caps_config_rdma { 4671 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 4672 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 4673 }; 4674 4675 enum fw_caps_config_iscsi { 4676 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 4677 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 4678 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 4679 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 4680 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 4681 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 4682 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, 4683 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080, 4684 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100, 4685 }; 4686 4687 enum fw_caps_config_crypto { 4688 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001, 4689 FW_CAPS_CONFIG_TLSKEYS = 0x00000002, 4690 }; 4691 4692 enum fw_caps_config_fcoe { 4693 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 4694 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 4695 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 4696 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 4697 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 4698 }; 4699 4700 enum fw_memtype_cf { 4701 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 4702 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 4703 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 4704 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 4705 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 4706 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 4707 }; 4708 4709 struct fw_caps_config_cmd { 4710 __be32 op_to_write; 4711 __be32 cfvalid_to_len16; 4712 __be32 r2; 4713 __be32 hwmbitmap; 4714 __be16 nbmcaps; 4715 __be16 linkcaps; 4716 __be16 switchcaps; 4717 __be16 r3; 4718 __be16 niccaps; 4719 __be16 toecaps; 4720 __be16 rdmacaps; 4721 __be16 cryptocaps; 4722 __be16 iscsicaps; 4723 __be16 fcoecaps; 4724 __be32 cfcsum; 4725 __be32 finiver; 4726 __be32 finicsum; 4727 }; 4728 4729 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 4730 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 4731 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 4732 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 4733 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 4734 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 4735 4736 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 4737 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 4738 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4739 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4740 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4741 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 4742 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4743 4744 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 4745 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 4746 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4747 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4748 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4749 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 4750 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4751 4752 /* 4753 * params command mnemonics 4754 */ 4755 enum fw_params_mnem { 4756 FW_PARAMS_MNEM_DEV = 1, /* device params */ 4757 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 4758 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 4759 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 4760 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 4761 FW_PARAMS_MNEM_LAST 4762 }; 4763 4764 /* 4765 * device parameters 4766 */ 4767 enum fw_params_param_dev { 4768 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 4769 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 4770 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 4771 * allocated by the device's 4772 * Lookup Engine 4773 */ 4774 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 4775 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 4776 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 4777 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 4778 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 4779 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 4780 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 4781 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 4782 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 4783 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 4784 FW_PARAMS_PARAM_DEV_CF = 0x0D, 4785 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 4786 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 4787 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 4788 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 4789 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 4790 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 4791 */ 4792 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 4793 */ 4794 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 4795 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 4796 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 4797 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 4798 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, 4799 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 4800 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 4801 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 4802 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 4803 4804 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 4805 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F, 4806 }; 4807 4808 /* 4809 * dev bypass parameters; actions and modes 4810 */ 4811 enum fw_params_param_dev_bypass { 4812 4813 /* actions 4814 */ 4815 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 4816 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 4817 4818 /* modes 4819 */ 4820 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 4821 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 4822 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 4823 }; 4824 4825 enum fw_params_param_dev_phyfw { 4826 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 4827 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 4828 }; 4829 4830 enum fw_params_param_dev_diag { 4831 FW_PARAM_DEV_DIAG_TMP = 0x00, 4832 FW_PARAM_DEV_DIAG_VDD = 0x01, 4833 }; 4834 4835 enum fw_params_param_dev_fwcache { 4836 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 4837 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 4838 }; 4839 4840 /* 4841 * physical and virtual function parameters 4842 */ 4843 enum fw_params_param_pfvf { 4844 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 4845 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 4846 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 4847 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 4848 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 4849 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 4850 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 4851 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 4852 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 4853 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 4854 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 4855 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 4856 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 4857 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 4858 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 4859 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 4860 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 4861 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 4862 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 4863 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 4864 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 4865 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 4866 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 4867 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 4868 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 4869 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 4870 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 4871 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 4872 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 4873 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 4874 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 4875 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 4876 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 4877 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 4878 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 4879 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 4880 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 4881 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 4882 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 4883 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 4884 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 4885 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 4886 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 4887 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 4888 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 4889 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 4890 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 4891 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 4892 FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38, 4893 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 4894 }; 4895 4896 /* 4897 * dma queue parameters 4898 */ 4899 enum fw_params_param_dmaq { 4900 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 4901 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 4902 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 4903 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03, 4904 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 4905 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 4906 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 4907 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 4908 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14, 4909 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 4910 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30 4911 }; 4912 4913 /* 4914 * chnet parameters 4915 */ 4916 enum fw_params_param_chnet { 4917 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, 4918 }; 4919 4920 enum fw_params_param_chnet_flags { 4921 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, 4922 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, 4923 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, 4924 }; 4925 4926 #define S_FW_PARAMS_MNEM 24 4927 #define M_FW_PARAMS_MNEM 0xff 4928 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 4929 #define G_FW_PARAMS_MNEM(x) \ 4930 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 4931 4932 #define S_FW_PARAMS_PARAM_X 16 4933 #define M_FW_PARAMS_PARAM_X 0xff 4934 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 4935 #define G_FW_PARAMS_PARAM_X(x) \ 4936 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 4937 4938 #define S_FW_PARAMS_PARAM_Y 8 4939 #define M_FW_PARAMS_PARAM_Y 0xff 4940 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 4941 #define G_FW_PARAMS_PARAM_Y(x) \ 4942 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 4943 4944 #define S_FW_PARAMS_PARAM_Z 0 4945 #define M_FW_PARAMS_PARAM_Z 0xff 4946 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 4947 #define G_FW_PARAMS_PARAM_Z(x) \ 4948 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 4949 4950 #define S_FW_PARAMS_PARAM_XYZ 0 4951 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 4952 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 4953 #define G_FW_PARAMS_PARAM_XYZ(x) \ 4954 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 4955 4956 #define S_FW_PARAMS_PARAM_YZ 0 4957 #define M_FW_PARAMS_PARAM_YZ 0xffff 4958 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 4959 #define G_FW_PARAMS_PARAM_YZ(x) \ 4960 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 4961 4962 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31 4963 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1 4964 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4965 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4966 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4967 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \ 4968 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4969 4970 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24 4971 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3 4972 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4973 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4974 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4975 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \ 4976 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4977 4978 #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0 4979 #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff 4980 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4981 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4982 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4983 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4984 4985 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29 4986 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7 4987 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 4988 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 4989 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 4990 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \ 4991 M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 4992 4993 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0 4994 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff 4995 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 4996 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 4997 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 4998 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \ 4999 M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 5000 5001 struct fw_params_cmd { 5002 __be32 op_to_vfn; 5003 __be32 retval_len16; 5004 struct fw_params_param { 5005 __be32 mnem; 5006 __be32 val; 5007 } param[7]; 5008 }; 5009 5010 #define S_FW_PARAMS_CMD_PFN 8 5011 #define M_FW_PARAMS_CMD_PFN 0x7 5012 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 5013 #define G_FW_PARAMS_CMD_PFN(x) \ 5014 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 5015 5016 #define S_FW_PARAMS_CMD_VFN 0 5017 #define M_FW_PARAMS_CMD_VFN 0xff 5018 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 5019 #define G_FW_PARAMS_CMD_VFN(x) \ 5020 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 5021 5022 struct fw_pfvf_cmd { 5023 __be32 op_to_vfn; 5024 __be32 retval_len16; 5025 __be32 niqflint_niq; 5026 __be32 type_to_neq; 5027 __be32 tc_to_nexactf; 5028 __be32 r_caps_to_nethctrl; 5029 __be16 nricq; 5030 __be16 nriqp; 5031 __be32 r4; 5032 }; 5033 5034 #define S_FW_PFVF_CMD_PFN 8 5035 #define M_FW_PFVF_CMD_PFN 0x7 5036 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 5037 #define G_FW_PFVF_CMD_PFN(x) \ 5038 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 5039 5040 #define S_FW_PFVF_CMD_VFN 0 5041 #define M_FW_PFVF_CMD_VFN 0xff 5042 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 5043 #define G_FW_PFVF_CMD_VFN(x) \ 5044 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 5045 5046 #define S_FW_PFVF_CMD_NIQFLINT 20 5047 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 5048 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 5049 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 5050 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 5051 5052 #define S_FW_PFVF_CMD_NIQ 0 5053 #define M_FW_PFVF_CMD_NIQ 0xfffff 5054 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 5055 #define G_FW_PFVF_CMD_NIQ(x) \ 5056 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 5057 5058 #define S_FW_PFVF_CMD_TYPE 31 5059 #define M_FW_PFVF_CMD_TYPE 0x1 5060 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 5061 #define G_FW_PFVF_CMD_TYPE(x) \ 5062 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 5063 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 5064 5065 #define S_FW_PFVF_CMD_CMASK 24 5066 #define M_FW_PFVF_CMD_CMASK 0xf 5067 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 5068 #define G_FW_PFVF_CMD_CMASK(x) \ 5069 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 5070 5071 #define S_FW_PFVF_CMD_PMASK 20 5072 #define M_FW_PFVF_CMD_PMASK 0xf 5073 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 5074 #define G_FW_PFVF_CMD_PMASK(x) \ 5075 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 5076 5077 #define S_FW_PFVF_CMD_NEQ 0 5078 #define M_FW_PFVF_CMD_NEQ 0xfffff 5079 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 5080 #define G_FW_PFVF_CMD_NEQ(x) \ 5081 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 5082 5083 #define S_FW_PFVF_CMD_TC 24 5084 #define M_FW_PFVF_CMD_TC 0xff 5085 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 5086 #define G_FW_PFVF_CMD_TC(x) \ 5087 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 5088 5089 #define S_FW_PFVF_CMD_NVI 16 5090 #define M_FW_PFVF_CMD_NVI 0xff 5091 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 5092 #define G_FW_PFVF_CMD_NVI(x) \ 5093 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 5094 5095 #define S_FW_PFVF_CMD_NEXACTF 0 5096 #define M_FW_PFVF_CMD_NEXACTF 0xffff 5097 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 5098 #define G_FW_PFVF_CMD_NEXACTF(x) \ 5099 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 5100 5101 #define S_FW_PFVF_CMD_R_CAPS 24 5102 #define M_FW_PFVF_CMD_R_CAPS 0xff 5103 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 5104 #define G_FW_PFVF_CMD_R_CAPS(x) \ 5105 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 5106 5107 #define S_FW_PFVF_CMD_WX_CAPS 16 5108 #define M_FW_PFVF_CMD_WX_CAPS 0xff 5109 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 5110 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 5111 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 5112 5113 #define S_FW_PFVF_CMD_NETHCTRL 0 5114 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 5115 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 5116 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 5117 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 5118 5119 /* 5120 * ingress queue type; the first 1K ingress queues can have associated 0, 5121 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 5122 * capabilities 5123 */ 5124 enum fw_iq_type { 5125 FW_IQ_TYPE_FL_INT_CAP, 5126 FW_IQ_TYPE_NO_FL_INT_CAP, 5127 FW_IQ_TYPE_VF_CQ 5128 }; 5129 5130 struct fw_iq_cmd { 5131 __be32 op_to_vfn; 5132 __be32 alloc_to_len16; 5133 __be16 physiqid; 5134 __be16 iqid; 5135 __be16 fl0id; 5136 __be16 fl1id; 5137 __be32 type_to_iqandstindex; 5138 __be16 iqdroprss_to_iqesize; 5139 __be16 iqsize; 5140 __be64 iqaddr; 5141 __be32 iqns_to_fl0congen; 5142 __be16 fl0dcaen_to_fl0cidxfthresh; 5143 __be16 fl0size; 5144 __be64 fl0addr; 5145 __be32 fl1cngchmap_to_fl1congen; 5146 __be16 fl1dcaen_to_fl1cidxfthresh; 5147 __be16 fl1size; 5148 __be64 fl1addr; 5149 }; 5150 5151 #define S_FW_IQ_CMD_PFN 8 5152 #define M_FW_IQ_CMD_PFN 0x7 5153 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 5154 #define G_FW_IQ_CMD_PFN(x) \ 5155 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 5156 5157 #define S_FW_IQ_CMD_VFN 0 5158 #define M_FW_IQ_CMD_VFN 0xff 5159 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 5160 #define G_FW_IQ_CMD_VFN(x) \ 5161 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 5162 5163 #define S_FW_IQ_CMD_ALLOC 31 5164 #define M_FW_IQ_CMD_ALLOC 0x1 5165 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 5166 #define G_FW_IQ_CMD_ALLOC(x) \ 5167 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 5168 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 5169 5170 #define S_FW_IQ_CMD_FREE 30 5171 #define M_FW_IQ_CMD_FREE 0x1 5172 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 5173 #define G_FW_IQ_CMD_FREE(x) \ 5174 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 5175 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 5176 5177 #define S_FW_IQ_CMD_MODIFY 29 5178 #define M_FW_IQ_CMD_MODIFY 0x1 5179 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 5180 #define G_FW_IQ_CMD_MODIFY(x) \ 5181 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 5182 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 5183 5184 #define S_FW_IQ_CMD_IQSTART 28 5185 #define M_FW_IQ_CMD_IQSTART 0x1 5186 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 5187 #define G_FW_IQ_CMD_IQSTART(x) \ 5188 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 5189 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 5190 5191 #define S_FW_IQ_CMD_IQSTOP 27 5192 #define M_FW_IQ_CMD_IQSTOP 0x1 5193 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 5194 #define G_FW_IQ_CMD_IQSTOP(x) \ 5195 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 5196 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 5197 5198 #define S_FW_IQ_CMD_TYPE 29 5199 #define M_FW_IQ_CMD_TYPE 0x7 5200 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 5201 #define G_FW_IQ_CMD_TYPE(x) \ 5202 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 5203 5204 #define S_FW_IQ_CMD_IQASYNCH 28 5205 #define M_FW_IQ_CMD_IQASYNCH 0x1 5206 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 5207 #define G_FW_IQ_CMD_IQASYNCH(x) \ 5208 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 5209 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 5210 5211 #define S_FW_IQ_CMD_VIID 16 5212 #define M_FW_IQ_CMD_VIID 0xfff 5213 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 5214 #define G_FW_IQ_CMD_VIID(x) \ 5215 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 5216 5217 #define S_FW_IQ_CMD_IQANDST 15 5218 #define M_FW_IQ_CMD_IQANDST 0x1 5219 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 5220 #define G_FW_IQ_CMD_IQANDST(x) \ 5221 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 5222 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 5223 5224 #define S_FW_IQ_CMD_IQANUS 14 5225 #define M_FW_IQ_CMD_IQANUS 0x1 5226 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 5227 #define G_FW_IQ_CMD_IQANUS(x) \ 5228 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 5229 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 5230 5231 #define S_FW_IQ_CMD_IQANUD 12 5232 #define M_FW_IQ_CMD_IQANUD 0x3 5233 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 5234 #define G_FW_IQ_CMD_IQANUD(x) \ 5235 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 5236 5237 #define S_FW_IQ_CMD_IQANDSTINDEX 0 5238 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 5239 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 5240 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 5241 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 5242 5243 #define S_FW_IQ_CMD_IQDROPRSS 15 5244 #define M_FW_IQ_CMD_IQDROPRSS 0x1 5245 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 5246 #define G_FW_IQ_CMD_IQDROPRSS(x) \ 5247 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 5248 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 5249 5250 #define S_FW_IQ_CMD_IQGTSMODE 14 5251 #define M_FW_IQ_CMD_IQGTSMODE 0x1 5252 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 5253 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 5254 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 5255 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 5256 5257 #define S_FW_IQ_CMD_IQPCIECH 12 5258 #define M_FW_IQ_CMD_IQPCIECH 0x3 5259 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 5260 #define G_FW_IQ_CMD_IQPCIECH(x) \ 5261 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 5262 5263 #define S_FW_IQ_CMD_IQDCAEN 11 5264 #define M_FW_IQ_CMD_IQDCAEN 0x1 5265 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 5266 #define G_FW_IQ_CMD_IQDCAEN(x) \ 5267 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 5268 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 5269 5270 #define S_FW_IQ_CMD_IQDCACPU 6 5271 #define M_FW_IQ_CMD_IQDCACPU 0x1f 5272 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 5273 #define G_FW_IQ_CMD_IQDCACPU(x) \ 5274 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 5275 5276 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 5277 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 5278 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 5279 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 5280 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 5281 5282 #define S_FW_IQ_CMD_IQO 3 5283 #define M_FW_IQ_CMD_IQO 0x1 5284 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 5285 #define G_FW_IQ_CMD_IQO(x) \ 5286 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 5287 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 5288 5289 #define S_FW_IQ_CMD_IQCPRIO 2 5290 #define M_FW_IQ_CMD_IQCPRIO 0x1 5291 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 5292 #define G_FW_IQ_CMD_IQCPRIO(x) \ 5293 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 5294 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 5295 5296 #define S_FW_IQ_CMD_IQESIZE 0 5297 #define M_FW_IQ_CMD_IQESIZE 0x3 5298 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 5299 #define G_FW_IQ_CMD_IQESIZE(x) \ 5300 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 5301 5302 #define S_FW_IQ_CMD_IQNS 31 5303 #define M_FW_IQ_CMD_IQNS 0x1 5304 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 5305 #define G_FW_IQ_CMD_IQNS(x) \ 5306 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 5307 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 5308 5309 #define S_FW_IQ_CMD_IQRO 30 5310 #define M_FW_IQ_CMD_IQRO 0x1 5311 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 5312 #define G_FW_IQ_CMD_IQRO(x) \ 5313 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 5314 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 5315 5316 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 5317 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 5318 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 5319 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 5320 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 5321 5322 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 5323 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 5324 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 5325 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 5326 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 5327 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 5328 5329 #define S_FW_IQ_CMD_IQFLINTISCSIC 26 5330 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 5331 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 5332 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 5333 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 5334 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 5335 5336 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 5337 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 5338 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 5339 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 5340 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 5341 5342 #define S_FW_IQ_CMD_FL0CONGDROP 16 5343 #define M_FW_IQ_CMD_FL0CONGDROP 0x1 5344 #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) 5345 #define G_FW_IQ_CMD_FL0CONGDROP(x) \ 5346 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) 5347 #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) 5348 5349 #define S_FW_IQ_CMD_FL0CACHELOCK 15 5350 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 5351 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 5352 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 5353 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 5354 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 5355 5356 #define S_FW_IQ_CMD_FL0DBP 14 5357 #define M_FW_IQ_CMD_FL0DBP 0x1 5358 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 5359 #define G_FW_IQ_CMD_FL0DBP(x) \ 5360 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 5361 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 5362 5363 #define S_FW_IQ_CMD_FL0DATANS 13 5364 #define M_FW_IQ_CMD_FL0DATANS 0x1 5365 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 5366 #define G_FW_IQ_CMD_FL0DATANS(x) \ 5367 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 5368 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 5369 5370 #define S_FW_IQ_CMD_FL0DATARO 12 5371 #define M_FW_IQ_CMD_FL0DATARO 0x1 5372 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 5373 #define G_FW_IQ_CMD_FL0DATARO(x) \ 5374 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 5375 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 5376 5377 #define S_FW_IQ_CMD_FL0CONGCIF 11 5378 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 5379 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 5380 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 5381 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 5382 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 5383 5384 #define S_FW_IQ_CMD_FL0ONCHIP 10 5385 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 5386 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 5387 #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 5388 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 5389 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 5390 5391 #define S_FW_IQ_CMD_FL0STATUSPGNS 9 5392 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 5393 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 5394 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 5395 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 5396 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 5397 5398 #define S_FW_IQ_CMD_FL0STATUSPGRO 8 5399 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 5400 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 5401 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 5402 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 5403 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 5404 5405 #define S_FW_IQ_CMD_FL0FETCHNS 7 5406 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 5407 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 5408 #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 5409 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 5410 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 5411 5412 #define S_FW_IQ_CMD_FL0FETCHRO 6 5413 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 5414 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 5415 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 5416 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 5417 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 5418 5419 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 5420 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 5421 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 5422 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 5423 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 5424 5425 #define S_FW_IQ_CMD_FL0CPRIO 3 5426 #define M_FW_IQ_CMD_FL0CPRIO 0x1 5427 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 5428 #define G_FW_IQ_CMD_FL0CPRIO(x) \ 5429 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 5430 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 5431 5432 #define S_FW_IQ_CMD_FL0PADEN 2 5433 #define M_FW_IQ_CMD_FL0PADEN 0x1 5434 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 5435 #define G_FW_IQ_CMD_FL0PADEN(x) \ 5436 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 5437 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 5438 5439 #define S_FW_IQ_CMD_FL0PACKEN 1 5440 #define M_FW_IQ_CMD_FL0PACKEN 0x1 5441 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 5442 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 5443 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 5444 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 5445 5446 #define S_FW_IQ_CMD_FL0CONGEN 0 5447 #define M_FW_IQ_CMD_FL0CONGEN 0x1 5448 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 5449 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 5450 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 5451 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 5452 5453 #define S_FW_IQ_CMD_FL0DCAEN 15 5454 #define M_FW_IQ_CMD_FL0DCAEN 0x1 5455 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 5456 #define G_FW_IQ_CMD_FL0DCAEN(x) \ 5457 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 5458 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 5459 5460 #define S_FW_IQ_CMD_FL0DCACPU 10 5461 #define M_FW_IQ_CMD_FL0DCACPU 0x1f 5462 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 5463 #define G_FW_IQ_CMD_FL0DCACPU(x) \ 5464 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 5465 5466 #define S_FW_IQ_CMD_FL0FBMIN 7 5467 #define M_FW_IQ_CMD_FL0FBMIN 0x7 5468 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 5469 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 5470 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 5471 5472 #define S_FW_IQ_CMD_FL0FBMAX 4 5473 #define M_FW_IQ_CMD_FL0FBMAX 0x7 5474 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 5475 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 5476 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 5477 5478 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 5479 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 5480 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 5481 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 5482 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 5483 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 5484 5485 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 5486 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 5487 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 5488 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 5489 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 5490 5491 #define S_FW_IQ_CMD_FL1CNGCHMAP 20 5492 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 5493 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 5494 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 5495 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 5496 5497 #define S_FW_IQ_CMD_FL1CONGDROP 16 5498 #define M_FW_IQ_CMD_FL1CONGDROP 0x1 5499 #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) 5500 #define G_FW_IQ_CMD_FL1CONGDROP(x) \ 5501 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) 5502 #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) 5503 5504 #define S_FW_IQ_CMD_FL1CACHELOCK 15 5505 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 5506 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 5507 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 5508 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 5509 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 5510 5511 #define S_FW_IQ_CMD_FL1DBP 14 5512 #define M_FW_IQ_CMD_FL1DBP 0x1 5513 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 5514 #define G_FW_IQ_CMD_FL1DBP(x) \ 5515 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 5516 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 5517 5518 #define S_FW_IQ_CMD_FL1DATANS 13 5519 #define M_FW_IQ_CMD_FL1DATANS 0x1 5520 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 5521 #define G_FW_IQ_CMD_FL1DATANS(x) \ 5522 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 5523 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 5524 5525 #define S_FW_IQ_CMD_FL1DATARO 12 5526 #define M_FW_IQ_CMD_FL1DATARO 0x1 5527 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 5528 #define G_FW_IQ_CMD_FL1DATARO(x) \ 5529 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 5530 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 5531 5532 #define S_FW_IQ_CMD_FL1CONGCIF 11 5533 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 5534 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 5535 #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 5536 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 5537 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 5538 5539 #define S_FW_IQ_CMD_FL1ONCHIP 10 5540 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 5541 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 5542 #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 5543 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 5544 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 5545 5546 #define S_FW_IQ_CMD_FL1STATUSPGNS 9 5547 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 5548 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 5549 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 5550 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 5551 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 5552 5553 #define S_FW_IQ_CMD_FL1STATUSPGRO 8 5554 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 5555 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 5556 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 5557 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 5558 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 5559 5560 #define S_FW_IQ_CMD_FL1FETCHNS 7 5561 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 5562 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 5563 #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 5564 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 5565 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 5566 5567 #define S_FW_IQ_CMD_FL1FETCHRO 6 5568 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 5569 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 5570 #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 5571 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 5572 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 5573 5574 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 5575 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 5576 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 5577 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 5578 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 5579 5580 #define S_FW_IQ_CMD_FL1CPRIO 3 5581 #define M_FW_IQ_CMD_FL1CPRIO 0x1 5582 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 5583 #define G_FW_IQ_CMD_FL1CPRIO(x) \ 5584 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 5585 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 5586 5587 #define S_FW_IQ_CMD_FL1PADEN 2 5588 #define M_FW_IQ_CMD_FL1PADEN 0x1 5589 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 5590 #define G_FW_IQ_CMD_FL1PADEN(x) \ 5591 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 5592 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 5593 5594 #define S_FW_IQ_CMD_FL1PACKEN 1 5595 #define M_FW_IQ_CMD_FL1PACKEN 0x1 5596 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 5597 #define G_FW_IQ_CMD_FL1PACKEN(x) \ 5598 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 5599 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 5600 5601 #define S_FW_IQ_CMD_FL1CONGEN 0 5602 #define M_FW_IQ_CMD_FL1CONGEN 0x1 5603 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 5604 #define G_FW_IQ_CMD_FL1CONGEN(x) \ 5605 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 5606 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 5607 5608 #define S_FW_IQ_CMD_FL1DCAEN 15 5609 #define M_FW_IQ_CMD_FL1DCAEN 0x1 5610 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 5611 #define G_FW_IQ_CMD_FL1DCAEN(x) \ 5612 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 5613 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 5614 5615 #define S_FW_IQ_CMD_FL1DCACPU 10 5616 #define M_FW_IQ_CMD_FL1DCACPU 0x1f 5617 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 5618 #define G_FW_IQ_CMD_FL1DCACPU(x) \ 5619 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 5620 5621 #define S_FW_IQ_CMD_FL1FBMIN 7 5622 #define M_FW_IQ_CMD_FL1FBMIN 0x7 5623 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 5624 #define G_FW_IQ_CMD_FL1FBMIN(x) \ 5625 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 5626 5627 #define S_FW_IQ_CMD_FL1FBMAX 4 5628 #define M_FW_IQ_CMD_FL1FBMAX 0x7 5629 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 5630 #define G_FW_IQ_CMD_FL1FBMAX(x) \ 5631 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 5632 5633 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 5634 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 5635 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 5636 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 5637 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 5638 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 5639 5640 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 5641 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 5642 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 5643 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 5644 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 5645 5646 struct fw_eq_mngt_cmd { 5647 __be32 op_to_vfn; 5648 __be32 alloc_to_len16; 5649 __be32 cmpliqid_eqid; 5650 __be32 physeqid_pkd; 5651 __be32 fetchszm_to_iqid; 5652 __be32 dcaen_to_eqsize; 5653 __be64 eqaddr; 5654 }; 5655 5656 #define S_FW_EQ_MNGT_CMD_PFN 8 5657 #define M_FW_EQ_MNGT_CMD_PFN 0x7 5658 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 5659 #define G_FW_EQ_MNGT_CMD_PFN(x) \ 5660 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 5661 5662 #define S_FW_EQ_MNGT_CMD_VFN 0 5663 #define M_FW_EQ_MNGT_CMD_VFN 0xff 5664 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 5665 #define G_FW_EQ_MNGT_CMD_VFN(x) \ 5666 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 5667 5668 #define S_FW_EQ_MNGT_CMD_ALLOC 31 5669 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 5670 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 5671 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 5672 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 5673 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 5674 5675 #define S_FW_EQ_MNGT_CMD_FREE 30 5676 #define M_FW_EQ_MNGT_CMD_FREE 0x1 5677 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 5678 #define G_FW_EQ_MNGT_CMD_FREE(x) \ 5679 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 5680 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 5681 5682 #define S_FW_EQ_MNGT_CMD_MODIFY 29 5683 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 5684 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 5685 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 5686 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 5687 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 5688 5689 #define S_FW_EQ_MNGT_CMD_EQSTART 28 5690 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 5691 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 5692 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 5693 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 5694 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 5695 5696 #define S_FW_EQ_MNGT_CMD_EQSTOP 27 5697 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 5698 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 5699 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 5700 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 5701 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 5702 5703 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 5704 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 5705 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 5706 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 5707 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 5708 5709 #define S_FW_EQ_MNGT_CMD_EQID 0 5710 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 5711 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 5712 #define G_FW_EQ_MNGT_CMD_EQID(x) \ 5713 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 5714 5715 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 5716 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 5717 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 5718 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 5719 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 5720 5721 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 5722 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 5723 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 5724 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 5725 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 5726 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 5727 5728 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 5729 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 5730 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 5731 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 5732 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 5733 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 5734 5735 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 5736 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 5737 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 5738 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 5739 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 5740 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 5741 5742 #define S_FW_EQ_MNGT_CMD_FETCHNS 23 5743 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 5744 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 5745 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 5746 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 5747 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 5748 5749 #define S_FW_EQ_MNGT_CMD_FETCHRO 22 5750 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 5751 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 5752 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 5753 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 5754 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 5755 5756 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 5757 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 5758 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 5759 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 5760 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 5761 5762 #define S_FW_EQ_MNGT_CMD_CPRIO 19 5763 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 5764 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 5765 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 5766 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 5767 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 5768 5769 #define S_FW_EQ_MNGT_CMD_ONCHIP 18 5770 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 5771 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 5772 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 5773 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 5774 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 5775 5776 #define S_FW_EQ_MNGT_CMD_PCIECHN 16 5777 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 5778 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 5779 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 5780 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 5781 5782 #define S_FW_EQ_MNGT_CMD_IQID 0 5783 #define M_FW_EQ_MNGT_CMD_IQID 0xffff 5784 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 5785 #define G_FW_EQ_MNGT_CMD_IQID(x) \ 5786 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 5787 5788 #define S_FW_EQ_MNGT_CMD_DCAEN 31 5789 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 5790 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 5791 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 5792 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 5793 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 5794 5795 #define S_FW_EQ_MNGT_CMD_DCACPU 26 5796 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 5797 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 5798 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 5799 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 5800 5801 #define S_FW_EQ_MNGT_CMD_FBMIN 23 5802 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 5803 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 5804 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 5805 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 5806 5807 #define S_FW_EQ_MNGT_CMD_FBMAX 20 5808 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 5809 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 5810 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 5811 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 5812 5813 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 5814 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 5815 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5816 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5817 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5818 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5819 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 5820 5821 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 5822 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 5823 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5824 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 5825 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5826 5827 #define S_FW_EQ_MNGT_CMD_EQSIZE 0 5828 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 5829 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 5830 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 5831 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 5832 5833 struct fw_eq_eth_cmd { 5834 __be32 op_to_vfn; 5835 __be32 alloc_to_len16; 5836 __be32 eqid_pkd; 5837 __be32 physeqid_pkd; 5838 __be32 fetchszm_to_iqid; 5839 __be32 dcaen_to_eqsize; 5840 __be64 eqaddr; 5841 __be32 autoequiqe_to_viid; 5842 __be32 r8_lo; 5843 __be64 r9; 5844 }; 5845 5846 #define S_FW_EQ_ETH_CMD_PFN 8 5847 #define M_FW_EQ_ETH_CMD_PFN 0x7 5848 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 5849 #define G_FW_EQ_ETH_CMD_PFN(x) \ 5850 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 5851 5852 #define S_FW_EQ_ETH_CMD_VFN 0 5853 #define M_FW_EQ_ETH_CMD_VFN 0xff 5854 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 5855 #define G_FW_EQ_ETH_CMD_VFN(x) \ 5856 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 5857 5858 #define S_FW_EQ_ETH_CMD_ALLOC 31 5859 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 5860 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 5861 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 5862 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 5863 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 5864 5865 #define S_FW_EQ_ETH_CMD_FREE 30 5866 #define M_FW_EQ_ETH_CMD_FREE 0x1 5867 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 5868 #define G_FW_EQ_ETH_CMD_FREE(x) \ 5869 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 5870 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 5871 5872 #define S_FW_EQ_ETH_CMD_MODIFY 29 5873 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 5874 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 5875 #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 5876 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 5877 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 5878 5879 #define S_FW_EQ_ETH_CMD_EQSTART 28 5880 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 5881 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 5882 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 5883 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 5884 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 5885 5886 #define S_FW_EQ_ETH_CMD_EQSTOP 27 5887 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 5888 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 5889 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 5890 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 5891 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 5892 5893 #define S_FW_EQ_ETH_CMD_EQID 0 5894 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 5895 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 5896 #define G_FW_EQ_ETH_CMD_EQID(x) \ 5897 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 5898 5899 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 5900 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 5901 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 5902 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 5903 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 5904 5905 #define S_FW_EQ_ETH_CMD_FETCHSZM 26 5906 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 5907 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 5908 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 5909 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 5910 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 5911 5912 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 5913 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 5914 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 5915 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 5916 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 5917 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 5918 5919 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 5920 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 5921 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 5922 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 5923 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 5924 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 5925 5926 #define S_FW_EQ_ETH_CMD_FETCHNS 23 5927 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 5928 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 5929 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 5930 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 5931 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 5932 5933 #define S_FW_EQ_ETH_CMD_FETCHRO 22 5934 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 5935 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 5936 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 5937 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 5938 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 5939 5940 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 5941 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 5942 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 5943 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 5944 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 5945 5946 #define S_FW_EQ_ETH_CMD_CPRIO 19 5947 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 5948 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 5949 #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 5950 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 5951 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 5952 5953 #define S_FW_EQ_ETH_CMD_ONCHIP 18 5954 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 5955 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 5956 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 5957 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 5958 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 5959 5960 #define S_FW_EQ_ETH_CMD_PCIECHN 16 5961 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 5962 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 5963 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 5964 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 5965 5966 #define S_FW_EQ_ETH_CMD_IQID 0 5967 #define M_FW_EQ_ETH_CMD_IQID 0xffff 5968 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 5969 #define G_FW_EQ_ETH_CMD_IQID(x) \ 5970 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 5971 5972 #define S_FW_EQ_ETH_CMD_DCAEN 31 5973 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 5974 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 5975 #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 5976 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 5977 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 5978 5979 #define S_FW_EQ_ETH_CMD_DCACPU 26 5980 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 5981 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 5982 #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 5983 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 5984 5985 #define S_FW_EQ_ETH_CMD_FBMIN 23 5986 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 5987 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 5988 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 5989 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 5990 5991 #define S_FW_EQ_ETH_CMD_FBMAX 20 5992 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 5993 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 5994 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 5995 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 5996 5997 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 5998 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 5999 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 6000 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 6001 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 6002 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 6003 6004 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 6005 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 6006 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 6007 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 6008 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 6009 6010 #define S_FW_EQ_ETH_CMD_EQSIZE 0 6011 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 6012 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 6013 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 6014 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 6015 6016 #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 6017 #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 6018 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 6019 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 6020 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 6021 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 6022 6023 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 6024 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 6025 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 6026 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 6027 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 6028 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 6029 6030 #define S_FW_EQ_ETH_CMD_VIID 16 6031 #define M_FW_EQ_ETH_CMD_VIID 0xfff 6032 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 6033 #define G_FW_EQ_ETH_CMD_VIID(x) \ 6034 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 6035 6036 struct fw_eq_ctrl_cmd { 6037 __be32 op_to_vfn; 6038 __be32 alloc_to_len16; 6039 __be32 cmpliqid_eqid; 6040 __be32 physeqid_pkd; 6041 __be32 fetchszm_to_iqid; 6042 __be32 dcaen_to_eqsize; 6043 __be64 eqaddr; 6044 }; 6045 6046 #define S_FW_EQ_CTRL_CMD_PFN 8 6047 #define M_FW_EQ_CTRL_CMD_PFN 0x7 6048 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 6049 #define G_FW_EQ_CTRL_CMD_PFN(x) \ 6050 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 6051 6052 #define S_FW_EQ_CTRL_CMD_VFN 0 6053 #define M_FW_EQ_CTRL_CMD_VFN 0xff 6054 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 6055 #define G_FW_EQ_CTRL_CMD_VFN(x) \ 6056 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 6057 6058 #define S_FW_EQ_CTRL_CMD_ALLOC 31 6059 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 6060 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 6061 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 6062 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 6063 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 6064 6065 #define S_FW_EQ_CTRL_CMD_FREE 30 6066 #define M_FW_EQ_CTRL_CMD_FREE 0x1 6067 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 6068 #define G_FW_EQ_CTRL_CMD_FREE(x) \ 6069 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 6070 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 6071 6072 #define S_FW_EQ_CTRL_CMD_MODIFY 29 6073 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 6074 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 6075 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 6076 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 6077 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 6078 6079 #define S_FW_EQ_CTRL_CMD_EQSTART 28 6080 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 6081 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 6082 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 6083 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 6084 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 6085 6086 #define S_FW_EQ_CTRL_CMD_EQSTOP 27 6087 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 6088 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 6089 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 6090 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 6091 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 6092 6093 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 6094 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 6095 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 6096 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 6097 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 6098 6099 #define S_FW_EQ_CTRL_CMD_EQID 0 6100 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 6101 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 6102 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 6103 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 6104 6105 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 6106 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 6107 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 6108 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 6109 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 6110 6111 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 6112 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 6113 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 6114 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 6115 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 6116 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 6117 6118 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 6119 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 6120 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 6121 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 6122 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 6123 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 6124 6125 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 6126 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 6127 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 6128 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 6129 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 6130 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 6131 6132 #define S_FW_EQ_CTRL_CMD_FETCHNS 23 6133 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 6134 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 6135 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 6136 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 6137 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 6138 6139 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 6140 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 6141 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 6142 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 6143 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 6144 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 6145 6146 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 6147 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 6148 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 6149 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 6150 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 6151 6152 #define S_FW_EQ_CTRL_CMD_CPRIO 19 6153 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 6154 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 6155 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 6156 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 6157 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 6158 6159 #define S_FW_EQ_CTRL_CMD_ONCHIP 18 6160 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 6161 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 6162 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 6163 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 6164 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 6165 6166 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 6167 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 6168 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 6169 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 6170 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 6171 6172 #define S_FW_EQ_CTRL_CMD_IQID 0 6173 #define M_FW_EQ_CTRL_CMD_IQID 0xffff 6174 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 6175 #define G_FW_EQ_CTRL_CMD_IQID(x) \ 6176 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 6177 6178 #define S_FW_EQ_CTRL_CMD_DCAEN 31 6179 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 6180 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 6181 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 6182 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 6183 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 6184 6185 #define S_FW_EQ_CTRL_CMD_DCACPU 26 6186 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 6187 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 6188 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 6189 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 6190 6191 #define S_FW_EQ_CTRL_CMD_FBMIN 23 6192 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 6193 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 6194 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 6195 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 6196 6197 #define S_FW_EQ_CTRL_CMD_FBMAX 20 6198 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 6199 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 6200 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 6201 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 6202 6203 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 6204 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 6205 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6206 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6207 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6208 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6209 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 6210 6211 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 6212 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 6213 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6214 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 6215 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6216 6217 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 6218 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 6219 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 6220 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 6221 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 6222 6223 struct fw_eq_ofld_cmd { 6224 __be32 op_to_vfn; 6225 __be32 alloc_to_len16; 6226 __be32 eqid_pkd; 6227 __be32 physeqid_pkd; 6228 __be32 fetchszm_to_iqid; 6229 __be32 dcaen_to_eqsize; 6230 __be64 eqaddr; 6231 }; 6232 6233 #define S_FW_EQ_OFLD_CMD_PFN 8 6234 #define M_FW_EQ_OFLD_CMD_PFN 0x7 6235 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 6236 #define G_FW_EQ_OFLD_CMD_PFN(x) \ 6237 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 6238 6239 #define S_FW_EQ_OFLD_CMD_VFN 0 6240 #define M_FW_EQ_OFLD_CMD_VFN 0xff 6241 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 6242 #define G_FW_EQ_OFLD_CMD_VFN(x) \ 6243 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 6244 6245 #define S_FW_EQ_OFLD_CMD_ALLOC 31 6246 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 6247 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 6248 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 6249 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 6250 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 6251 6252 #define S_FW_EQ_OFLD_CMD_FREE 30 6253 #define M_FW_EQ_OFLD_CMD_FREE 0x1 6254 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 6255 #define G_FW_EQ_OFLD_CMD_FREE(x) \ 6256 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 6257 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 6258 6259 #define S_FW_EQ_OFLD_CMD_MODIFY 29 6260 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 6261 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 6262 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 6263 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 6264 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 6265 6266 #define S_FW_EQ_OFLD_CMD_EQSTART 28 6267 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 6268 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 6269 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 6270 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 6271 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 6272 6273 #define S_FW_EQ_OFLD_CMD_EQSTOP 27 6274 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 6275 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 6276 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 6277 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 6278 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 6279 6280 #define S_FW_EQ_OFLD_CMD_EQID 0 6281 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 6282 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 6283 #define G_FW_EQ_OFLD_CMD_EQID(x) \ 6284 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 6285 6286 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 6287 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 6288 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 6289 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 6290 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 6291 6292 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 6293 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 6294 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 6295 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 6296 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 6297 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 6298 6299 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 6300 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 6301 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 6302 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 6303 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 6304 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 6305 6306 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 6307 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 6308 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 6309 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 6310 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 6311 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 6312 6313 #define S_FW_EQ_OFLD_CMD_FETCHNS 23 6314 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 6315 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 6316 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 6317 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 6318 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 6319 6320 #define S_FW_EQ_OFLD_CMD_FETCHRO 22 6321 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 6322 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 6323 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 6324 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 6325 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 6326 6327 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 6328 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 6329 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 6330 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 6331 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 6332 6333 #define S_FW_EQ_OFLD_CMD_CPRIO 19 6334 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 6335 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 6336 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 6337 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 6338 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 6339 6340 #define S_FW_EQ_OFLD_CMD_ONCHIP 18 6341 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 6342 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 6343 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 6344 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 6345 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 6346 6347 #define S_FW_EQ_OFLD_CMD_PCIECHN 16 6348 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 6349 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 6350 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 6351 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 6352 6353 #define S_FW_EQ_OFLD_CMD_IQID 0 6354 #define M_FW_EQ_OFLD_CMD_IQID 0xffff 6355 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 6356 #define G_FW_EQ_OFLD_CMD_IQID(x) \ 6357 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 6358 6359 #define S_FW_EQ_OFLD_CMD_DCAEN 31 6360 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 6361 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 6362 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 6363 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 6364 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 6365 6366 #define S_FW_EQ_OFLD_CMD_DCACPU 26 6367 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 6368 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 6369 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 6370 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 6371 6372 #define S_FW_EQ_OFLD_CMD_FBMIN 23 6373 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 6374 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 6375 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 6376 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 6377 6378 #define S_FW_EQ_OFLD_CMD_FBMAX 20 6379 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 6380 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 6381 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 6382 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 6383 6384 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 6385 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 6386 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6387 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6388 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6389 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6390 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 6391 6392 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 6393 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 6394 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6395 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 6396 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6397 6398 #define S_FW_EQ_OFLD_CMD_EQSIZE 0 6399 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 6400 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 6401 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 6402 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 6403 6404 /* Macros for VIID parsing: 6405 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 6406 #define S_FW_VIID_PFN 8 6407 #define M_FW_VIID_PFN 0x7 6408 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 6409 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 6410 6411 #define S_FW_VIID_VIVLD 7 6412 #define M_FW_VIID_VIVLD 0x1 6413 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 6414 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 6415 6416 #define S_FW_VIID_VIN 0 6417 #define M_FW_VIID_VIN 0x7F 6418 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 6419 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 6420 6421 enum fw_vi_func { 6422 FW_VI_FUNC_ETH, 6423 FW_VI_FUNC_OFLD, 6424 FW_VI_FUNC_IWARP, 6425 FW_VI_FUNC_OPENISCSI, 6426 FW_VI_FUNC_OPENFCOE, 6427 FW_VI_FUNC_FOISCSI, 6428 FW_VI_FUNC_FOFCOE, 6429 FW_VI_FUNC_FW, 6430 }; 6431 6432 struct fw_vi_cmd { 6433 __be32 op_to_vfn; 6434 __be32 alloc_to_len16; 6435 __be16 type_to_viid; 6436 __u8 mac[6]; 6437 __u8 portid_pkd; 6438 __u8 nmac; 6439 __u8 nmac0[6]; 6440 __be16 norss_rsssize; 6441 __u8 nmac1[6]; 6442 __be16 idsiiq_pkd; 6443 __u8 nmac2[6]; 6444 __be16 idseiq_pkd; 6445 __u8 nmac3[6]; 6446 __be64 r9; 6447 __be64 r10; 6448 }; 6449 6450 #define S_FW_VI_CMD_PFN 8 6451 #define M_FW_VI_CMD_PFN 0x7 6452 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 6453 #define G_FW_VI_CMD_PFN(x) \ 6454 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 6455 6456 #define S_FW_VI_CMD_VFN 0 6457 #define M_FW_VI_CMD_VFN 0xff 6458 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 6459 #define G_FW_VI_CMD_VFN(x) \ 6460 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 6461 6462 #define S_FW_VI_CMD_ALLOC 31 6463 #define M_FW_VI_CMD_ALLOC 0x1 6464 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 6465 #define G_FW_VI_CMD_ALLOC(x) \ 6466 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 6467 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 6468 6469 #define S_FW_VI_CMD_FREE 30 6470 #define M_FW_VI_CMD_FREE 0x1 6471 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 6472 #define G_FW_VI_CMD_FREE(x) \ 6473 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 6474 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 6475 6476 #define S_FW_VI_CMD_TYPE 15 6477 #define M_FW_VI_CMD_TYPE 0x1 6478 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 6479 #define G_FW_VI_CMD_TYPE(x) \ 6480 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 6481 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 6482 6483 #define S_FW_VI_CMD_FUNC 12 6484 #define M_FW_VI_CMD_FUNC 0x7 6485 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 6486 #define G_FW_VI_CMD_FUNC(x) \ 6487 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 6488 6489 #define S_FW_VI_CMD_VIID 0 6490 #define M_FW_VI_CMD_VIID 0xfff 6491 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 6492 #define G_FW_VI_CMD_VIID(x) \ 6493 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 6494 6495 #define S_FW_VI_CMD_PORTID 4 6496 #define M_FW_VI_CMD_PORTID 0xf 6497 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 6498 #define G_FW_VI_CMD_PORTID(x) \ 6499 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 6500 6501 #define S_FW_VI_CMD_NORSS 11 6502 #define M_FW_VI_CMD_NORSS 0x1 6503 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 6504 #define G_FW_VI_CMD_NORSS(x) \ 6505 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 6506 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 6507 6508 #define S_FW_VI_CMD_RSSSIZE 0 6509 #define M_FW_VI_CMD_RSSSIZE 0x7ff 6510 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 6511 #define G_FW_VI_CMD_RSSSIZE(x) \ 6512 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 6513 6514 #define S_FW_VI_CMD_IDSIIQ 0 6515 #define M_FW_VI_CMD_IDSIIQ 0x3ff 6516 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 6517 #define G_FW_VI_CMD_IDSIIQ(x) \ 6518 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 6519 6520 #define S_FW_VI_CMD_IDSEIQ 0 6521 #define M_FW_VI_CMD_IDSEIQ 0x3ff 6522 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 6523 #define G_FW_VI_CMD_IDSEIQ(x) \ 6524 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 6525 6526 /* Special VI_MAC command index ids */ 6527 #define FW_VI_MAC_ADD_MAC 0x3FF 6528 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 6529 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 6530 6531 enum fw_vi_mac_smac { 6532 FW_VI_MAC_MPS_TCAM_ENTRY, 6533 FW_VI_MAC_MPS_TCAM_ONLY, 6534 FW_VI_MAC_SMT_ONLY, 6535 FW_VI_MAC_SMT_AND_MPSTCAM 6536 }; 6537 6538 enum fw_vi_mac_result { 6539 FW_VI_MAC_R_SUCCESS, 6540 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 6541 FW_VI_MAC_R_SMAC_FAIL, 6542 FW_VI_MAC_R_F_ACL_CHECK 6543 }; 6544 6545 enum fw_vi_mac_entry_types { 6546 FW_VI_MAC_TYPE_EXACTMAC, 6547 FW_VI_MAC_TYPE_HASHVEC, 6548 FW_VI_MAC_TYPE_RAW, 6549 }; 6550 6551 struct fw_vi_mac_cmd { 6552 __be32 op_to_viid; 6553 __be32 freemacs_to_len16; 6554 union fw_vi_mac { 6555 struct fw_vi_mac_exact { 6556 __be16 valid_to_idx; 6557 __u8 macaddr[6]; 6558 } exact[7]; 6559 struct fw_vi_mac_hash { 6560 __be64 hashvec; 6561 } hash; 6562 struct fw_vi_mac_raw { 6563 __be32 raw_idx_pkd; 6564 __be32 data0_pkd; 6565 __be32 data1[2]; 6566 __be64 data0m_pkd; 6567 __be32 data1m[2]; 6568 } raw; 6569 } u; 6570 }; 6571 6572 #define S_FW_VI_MAC_CMD_VIID 0 6573 #define M_FW_VI_MAC_CMD_VIID 0xfff 6574 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 6575 #define G_FW_VI_MAC_CMD_VIID(x) \ 6576 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 6577 6578 #define S_FW_VI_MAC_CMD_FREEMACS 31 6579 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 6580 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 6581 #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 6582 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 6583 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 6584 6585 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 6586 #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7 6587 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 6588 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \ 6589 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE) 6590 6591 #define S_FW_VI_MAC_CMD_HASHUNIEN 22 6592 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 6593 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 6594 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 6595 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 6596 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 6597 6598 #define S_FW_VI_MAC_CMD_VALID 15 6599 #define M_FW_VI_MAC_CMD_VALID 0x1 6600 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 6601 #define G_FW_VI_MAC_CMD_VALID(x) \ 6602 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 6603 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 6604 6605 #define S_FW_VI_MAC_CMD_PRIO 12 6606 #define M_FW_VI_MAC_CMD_PRIO 0x7 6607 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 6608 #define G_FW_VI_MAC_CMD_PRIO(x) \ 6609 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 6610 6611 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 6612 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 6613 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 6614 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 6615 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 6616 6617 #define S_FW_VI_MAC_CMD_IDX 0 6618 #define M_FW_VI_MAC_CMD_IDX 0x3ff 6619 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 6620 #define G_FW_VI_MAC_CMD_IDX(x) \ 6621 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 6622 6623 #define S_FW_VI_MAC_CMD_RAW_IDX 16 6624 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 6625 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 6626 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 6627 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 6628 6629 #define S_FW_VI_MAC_CMD_DATA0 0 6630 #define M_FW_VI_MAC_CMD_DATA0 0xffff 6631 #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0) 6632 #define G_FW_VI_MAC_CMD_DATA0(x) \ 6633 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0) 6634 6635 /* T4 max MTU supported */ 6636 #define T4_MAX_MTU_SUPPORTED 9600 6637 #define FW_RXMODE_MTU_NO_CHG 65535 6638 6639 struct fw_vi_rxmode_cmd { 6640 __be32 op_to_viid; 6641 __be32 retval_len16; 6642 __be32 mtu_to_vlanexen; 6643 __be32 r4_lo; 6644 }; 6645 6646 #define S_FW_VI_RXMODE_CMD_VIID 0 6647 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 6648 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 6649 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 6650 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 6651 6652 #define S_FW_VI_RXMODE_CMD_MTU 16 6653 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 6654 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 6655 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 6656 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 6657 6658 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 6659 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 6660 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 6661 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 6662 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 6663 6664 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 6665 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 6666 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6667 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 6668 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6669 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 6670 6671 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 6672 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 6673 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6674 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 6675 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6676 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 6677 6678 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 6679 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 6680 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 6681 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 6682 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 6683 6684 struct fw_vi_enable_cmd { 6685 __be32 op_to_viid; 6686 __be32 ien_to_len16; 6687 __be16 blinkdur; 6688 __be16 r3; 6689 __be32 r4; 6690 }; 6691 6692 #define S_FW_VI_ENABLE_CMD_VIID 0 6693 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 6694 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 6695 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 6696 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 6697 6698 #define S_FW_VI_ENABLE_CMD_IEN 31 6699 #define M_FW_VI_ENABLE_CMD_IEN 0x1 6700 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 6701 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 6702 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 6703 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 6704 6705 #define S_FW_VI_ENABLE_CMD_EEN 30 6706 #define M_FW_VI_ENABLE_CMD_EEN 0x1 6707 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 6708 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 6709 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 6710 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 6711 6712 #define S_FW_VI_ENABLE_CMD_LED 29 6713 #define M_FW_VI_ENABLE_CMD_LED 0x1 6714 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 6715 #define G_FW_VI_ENABLE_CMD_LED(x) \ 6716 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 6717 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 6718 6719 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 6720 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 6721 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 6722 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 6723 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 6724 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 6725 6726 /* VI VF stats offset definitions */ 6727 #define VI_VF_NUM_STATS 16 6728 enum fw_vi_stats_vf_index { 6729 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 6730 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 6731 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 6732 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 6733 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 6734 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 6735 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 6736 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 6737 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 6738 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 6739 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 6740 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 6741 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 6742 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 6743 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 6744 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 6745 }; 6746 6747 /* VI PF stats offset definitions */ 6748 #define VI_PF_NUM_STATS 17 6749 enum fw_vi_stats_pf_index { 6750 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 6751 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 6752 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 6753 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 6754 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 6755 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 6756 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 6757 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 6758 FW_VI_PF_STAT_RX_BYTES_IX, 6759 FW_VI_PF_STAT_RX_FRAMES_IX, 6760 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 6761 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 6762 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 6763 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 6764 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 6765 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 6766 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 6767 }; 6768 6769 struct fw_vi_stats_cmd { 6770 __be32 op_to_viid; 6771 __be32 retval_len16; 6772 union fw_vi_stats { 6773 struct fw_vi_stats_ctl { 6774 __be16 nstats_ix; 6775 __be16 r6; 6776 __be32 r7; 6777 __be64 stat0; 6778 __be64 stat1; 6779 __be64 stat2; 6780 __be64 stat3; 6781 __be64 stat4; 6782 __be64 stat5; 6783 } ctl; 6784 struct fw_vi_stats_pf { 6785 __be64 tx_bcast_bytes; 6786 __be64 tx_bcast_frames; 6787 __be64 tx_mcast_bytes; 6788 __be64 tx_mcast_frames; 6789 __be64 tx_ucast_bytes; 6790 __be64 tx_ucast_frames; 6791 __be64 tx_offload_bytes; 6792 __be64 tx_offload_frames; 6793 __be64 rx_pf_bytes; 6794 __be64 rx_pf_frames; 6795 __be64 rx_bcast_bytes; 6796 __be64 rx_bcast_frames; 6797 __be64 rx_mcast_bytes; 6798 __be64 rx_mcast_frames; 6799 __be64 rx_ucast_bytes; 6800 __be64 rx_ucast_frames; 6801 __be64 rx_err_frames; 6802 } pf; 6803 struct fw_vi_stats_vf { 6804 __be64 tx_bcast_bytes; 6805 __be64 tx_bcast_frames; 6806 __be64 tx_mcast_bytes; 6807 __be64 tx_mcast_frames; 6808 __be64 tx_ucast_bytes; 6809 __be64 tx_ucast_frames; 6810 __be64 tx_drop_frames; 6811 __be64 tx_offload_bytes; 6812 __be64 tx_offload_frames; 6813 __be64 rx_bcast_bytes; 6814 __be64 rx_bcast_frames; 6815 __be64 rx_mcast_bytes; 6816 __be64 rx_mcast_frames; 6817 __be64 rx_ucast_bytes; 6818 __be64 rx_ucast_frames; 6819 __be64 rx_err_frames; 6820 } vf; 6821 } u; 6822 }; 6823 6824 #define S_FW_VI_STATS_CMD_VIID 0 6825 #define M_FW_VI_STATS_CMD_VIID 0xfff 6826 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 6827 #define G_FW_VI_STATS_CMD_VIID(x) \ 6828 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 6829 6830 #define S_FW_VI_STATS_CMD_NSTATS 12 6831 #define M_FW_VI_STATS_CMD_NSTATS 0x7 6832 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 6833 #define G_FW_VI_STATS_CMD_NSTATS(x) \ 6834 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 6835 6836 #define S_FW_VI_STATS_CMD_IX 0 6837 #define M_FW_VI_STATS_CMD_IX 0x1f 6838 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 6839 #define G_FW_VI_STATS_CMD_IX(x) \ 6840 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 6841 6842 struct fw_acl_mac_cmd { 6843 __be32 op_to_vfn; 6844 __be32 en_to_len16; 6845 __u8 nmac; 6846 __u8 r3[7]; 6847 __be16 r4; 6848 __u8 macaddr0[6]; 6849 __be16 r5; 6850 __u8 macaddr1[6]; 6851 __be16 r6; 6852 __u8 macaddr2[6]; 6853 __be16 r7; 6854 __u8 macaddr3[6]; 6855 }; 6856 6857 #define S_FW_ACL_MAC_CMD_PFN 8 6858 #define M_FW_ACL_MAC_CMD_PFN 0x7 6859 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 6860 #define G_FW_ACL_MAC_CMD_PFN(x) \ 6861 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 6862 6863 #define S_FW_ACL_MAC_CMD_VFN 0 6864 #define M_FW_ACL_MAC_CMD_VFN 0xff 6865 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 6866 #define G_FW_ACL_MAC_CMD_VFN(x) \ 6867 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 6868 6869 #define S_FW_ACL_MAC_CMD_EN 31 6870 #define M_FW_ACL_MAC_CMD_EN 0x1 6871 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 6872 #define G_FW_ACL_MAC_CMD_EN(x) \ 6873 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 6874 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 6875 6876 struct fw_acl_vlan_cmd { 6877 __be32 op_to_vfn; 6878 __be32 en_to_len16; 6879 __u8 nvlan; 6880 __u8 dropnovlan_fm; 6881 __u8 r3_lo[6]; 6882 __be16 vlanid[16]; 6883 }; 6884 6885 #define S_FW_ACL_VLAN_CMD_PFN 8 6886 #define M_FW_ACL_VLAN_CMD_PFN 0x7 6887 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 6888 #define G_FW_ACL_VLAN_CMD_PFN(x) \ 6889 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 6890 6891 #define S_FW_ACL_VLAN_CMD_VFN 0 6892 #define M_FW_ACL_VLAN_CMD_VFN 0xff 6893 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 6894 #define G_FW_ACL_VLAN_CMD_VFN(x) \ 6895 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 6896 6897 #define S_FW_ACL_VLAN_CMD_EN 31 6898 #define M_FW_ACL_VLAN_CMD_EN 0x1 6899 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 6900 #define G_FW_ACL_VLAN_CMD_EN(x) \ 6901 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 6902 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 6903 6904 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 6905 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 6906 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 6907 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 6908 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 6909 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 6910 6911 #define S_FW_ACL_VLAN_CMD_FM 6 6912 #define M_FW_ACL_VLAN_CMD_FM 0x1 6913 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 6914 #define G_FW_ACL_VLAN_CMD_FM(x) \ 6915 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 6916 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 6917 6918 /* port capabilities bitmap */ 6919 enum fw_port_cap { 6920 FW_PORT_CAP_SPEED_100M = 0x0001, 6921 FW_PORT_CAP_SPEED_1G = 0x0002, 6922 FW_PORT_CAP_SPEED_25G = 0x0004, 6923 FW_PORT_CAP_SPEED_10G = 0x0008, 6924 FW_PORT_CAP_SPEED_40G = 0x0010, 6925 FW_PORT_CAP_SPEED_100G = 0x0020, 6926 FW_PORT_CAP_FC_RX = 0x0040, 6927 FW_PORT_CAP_FC_TX = 0x0080, 6928 FW_PORT_CAP_ANEG = 0x0100, 6929 FW_PORT_CAP_MDIX = 0x0200, 6930 FW_PORT_CAP_MDIAUTO = 0x0400, 6931 FW_PORT_CAP_FEC_RS = 0x0800, 6932 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 6933 FW_PORT_CAP_FEC_RESERVED = 0x2000, 6934 FW_PORT_CAP_802_3_PAUSE = 0x4000, 6935 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 6936 }; 6937 6938 #define S_FW_PORT_CAP_SPEED 0 6939 #define M_FW_PORT_CAP_SPEED 0x3f 6940 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 6941 #define G_FW_PORT_CAP_SPEED(x) \ 6942 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 6943 6944 #define S_FW_PORT_CAP_FC 6 6945 #define M_FW_PORT_CAP_FC 0x3 6946 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 6947 #define G_FW_PORT_CAP_FC(x) \ 6948 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 6949 6950 #define S_FW_PORT_CAP_ANEG 8 6951 #define M_FW_PORT_CAP_ANEG 0x1 6952 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 6953 #define G_FW_PORT_CAP_ANEG(x) \ 6954 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 6955 6956 #define S_FW_PORT_CAP_FEC 11 6957 #define M_FW_PORT_CAP_FEC 0x7 6958 #define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC) 6959 #define G_FW_PORT_CAP_FEC(x) \ 6960 (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC) 6961 6962 #define S_FW_PORT_CAP_802_3 14 6963 #define M_FW_PORT_CAP_802_3 0x3 6964 #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) 6965 #define G_FW_PORT_CAP_802_3(x) \ 6966 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) 6967 6968 enum fw_port_mdi { 6969 FW_PORT_CAP_MDI_UNCHANGED, 6970 FW_PORT_CAP_MDI_AUTO, 6971 FW_PORT_CAP_MDI_F_STRAIGHT, 6972 FW_PORT_CAP_MDI_F_CROSSOVER 6973 }; 6974 6975 #define S_FW_PORT_CAP_MDI 9 6976 #define M_FW_PORT_CAP_MDI 3 6977 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 6978 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 6979 6980 #define S_FW_PORT_AUXLINFO_KX4 2 6981 #define M_FW_PORT_AUXLINFO_KX4 0x1 6982 #define V_FW_PORT_AUXLINFO_KX4(x) \ 6983 ((x) << S_FW_PORT_AUXLINFO_KX4) 6984 #define G_FW_PORT_AUXLINFO_KX4(x) \ 6985 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 6986 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 6987 6988 #define S_FW_PORT_AUXLINFO_KR 1 6989 #define M_FW_PORT_AUXLINFO_KR 0x1 6990 #define V_FW_PORT_AUXLINFO_KR(x) \ 6991 ((x) << S_FW_PORT_AUXLINFO_KR) 6992 #define G_FW_PORT_AUXLINFO_KR(x) \ 6993 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 6994 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 6995 6996 enum fw_port_action { 6997 FW_PORT_ACTION_L1_CFG = 0x0001, 6998 FW_PORT_ACTION_L2_CFG = 0x0002, 6999 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 7000 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 7001 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 7002 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 7003 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 7004 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 7005 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 7006 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 7007 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 7008 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 7009 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 7010 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 7011 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 7012 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 7013 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 7014 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 7015 FW_PORT_ACTION_PHY_RESET = 0x0040, 7016 FW_PORT_ACTION_PMA_RESET = 0x0041, 7017 FW_PORT_ACTION_PCS_RESET = 0x0042, 7018 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 7019 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 7020 FW_PORT_ACTION_AN_RESET = 0x0045, 7021 7022 }; 7023 7024 enum fw_port_l2cfg_ctlbf { 7025 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 7026 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 7027 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 7028 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 7029 FW_PORT_L2_CTLBF_IVLAN = 0x10, 7030 FW_PORT_L2_CTLBF_TXIPG = 0x20, 7031 FW_PORT_L2_CTLBF_MTU = 0x40 7032 }; 7033 7034 enum fw_dcb_app_tlv_sf { 7035 FW_DCB_APP_SF_ETHERTYPE, 7036 FW_DCB_APP_SF_SOCKET_TCP, 7037 FW_DCB_APP_SF_SOCKET_UDP, 7038 FW_DCB_APP_SF_SOCKET_ALL, 7039 }; 7040 7041 enum fw_port_dcb_versions { 7042 FW_PORT_DCB_VER_UNKNOWN, 7043 FW_PORT_DCB_VER_CEE1D0, 7044 FW_PORT_DCB_VER_CEE1D01, 7045 FW_PORT_DCB_VER_IEEE, 7046 FW_PORT_DCB_VER_AUTO=7 7047 }; 7048 7049 enum fw_port_dcb_cfg { 7050 FW_PORT_DCB_CFG_PG = 0x01, 7051 FW_PORT_DCB_CFG_PFC = 0x02, 7052 FW_PORT_DCB_CFG_APPL = 0x04 7053 }; 7054 7055 enum fw_port_dcb_cfg_rc { 7056 FW_PORT_DCB_CFG_SUCCESS = 0x0, 7057 FW_PORT_DCB_CFG_ERROR = 0x1 7058 }; 7059 7060 enum fw_port_dcb_type { 7061 FW_PORT_DCB_TYPE_PGID = 0x00, 7062 FW_PORT_DCB_TYPE_PGRATE = 0x01, 7063 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 7064 FW_PORT_DCB_TYPE_PFC = 0x03, 7065 FW_PORT_DCB_TYPE_APP_ID = 0x04, 7066 FW_PORT_DCB_TYPE_CONTROL = 0x05, 7067 }; 7068 7069 enum fw_port_dcb_feature_state { 7070 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 7071 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 7072 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 7073 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 7074 }; 7075 7076 enum fw_port_diag_ops { 7077 FW_PORT_DIAGS_TEMP = 0x00, 7078 FW_PORT_DIAGS_TX_POWER = 0x01, 7079 FW_PORT_DIAGS_RX_POWER = 0x02, 7080 FW_PORT_DIAGS_TX_DIS = 0x03, 7081 }; 7082 7083 struct fw_port_cmd { 7084 __be32 op_to_portid; 7085 __be32 action_to_len16; 7086 union fw_port { 7087 struct fw_port_l1cfg { 7088 __be32 rcap; 7089 __be32 r; 7090 } l1cfg; 7091 struct fw_port_l2cfg { 7092 __u8 ctlbf; 7093 __u8 ovlan3_to_ivlan0; 7094 __be16 ivlantype; 7095 __be16 txipg_force_pinfo; 7096 __be16 mtu; 7097 __be16 ovlan0mask; 7098 __be16 ovlan0type; 7099 __be16 ovlan1mask; 7100 __be16 ovlan1type; 7101 __be16 ovlan2mask; 7102 __be16 ovlan2type; 7103 __be16 ovlan3mask; 7104 __be16 ovlan3type; 7105 } l2cfg; 7106 struct fw_port_info { 7107 __be32 lstatus_to_modtype; 7108 __be16 pcap; 7109 __be16 acap; 7110 __be16 mtu; 7111 __u8 cbllen; 7112 __u8 auxlinfo; 7113 __u8 dcbxdis_pkd; 7114 __u8 r8_lo; 7115 __be16 lpacap; 7116 __be64 r9; 7117 } info; 7118 struct fw_port_diags { 7119 __u8 diagop; 7120 __u8 r[3]; 7121 __be32 diagval; 7122 } diags; 7123 union fw_port_dcb { 7124 struct fw_port_dcb_pgid { 7125 __u8 type; 7126 __u8 apply_pkd; 7127 __u8 r10_lo[2]; 7128 __be32 pgid; 7129 __be64 r11; 7130 } pgid; 7131 struct fw_port_dcb_pgrate { 7132 __u8 type; 7133 __u8 apply_pkd; 7134 __u8 r10_lo[5]; 7135 __u8 num_tcs_supported; 7136 __u8 pgrate[8]; 7137 __u8 tsa[8]; 7138 } pgrate; 7139 struct fw_port_dcb_priorate { 7140 __u8 type; 7141 __u8 apply_pkd; 7142 __u8 r10_lo[6]; 7143 __u8 strict_priorate[8]; 7144 } priorate; 7145 struct fw_port_dcb_pfc { 7146 __u8 type; 7147 __u8 pfcen; 7148 __u8 r10[5]; 7149 __u8 max_pfc_tcs; 7150 __be64 r11; 7151 } pfc; 7152 struct fw_port_app_priority { 7153 __u8 type; 7154 __u8 r10[2]; 7155 __u8 idx; 7156 __u8 user_prio_map; 7157 __u8 sel_field; 7158 __be16 protocolid; 7159 __be64 r12; 7160 } app_priority; 7161 struct fw_port_dcb_control { 7162 __u8 type; 7163 __u8 all_syncd_pkd; 7164 __be16 dcb_version_to_app_state; 7165 __be32 r11; 7166 __be64 r12; 7167 } control; 7168 } dcb; 7169 } u; 7170 }; 7171 7172 #define S_FW_PORT_CMD_READ 22 7173 #define M_FW_PORT_CMD_READ 0x1 7174 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 7175 #define G_FW_PORT_CMD_READ(x) \ 7176 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 7177 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 7178 7179 #define S_FW_PORT_CMD_PORTID 0 7180 #define M_FW_PORT_CMD_PORTID 0xf 7181 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 7182 #define G_FW_PORT_CMD_PORTID(x) \ 7183 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 7184 7185 #define S_FW_PORT_CMD_ACTION 16 7186 #define M_FW_PORT_CMD_ACTION 0xffff 7187 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 7188 #define G_FW_PORT_CMD_ACTION(x) \ 7189 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 7190 7191 #define S_FW_PORT_CMD_OVLAN3 7 7192 #define M_FW_PORT_CMD_OVLAN3 0x1 7193 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 7194 #define G_FW_PORT_CMD_OVLAN3(x) \ 7195 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 7196 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 7197 7198 #define S_FW_PORT_CMD_OVLAN2 6 7199 #define M_FW_PORT_CMD_OVLAN2 0x1 7200 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 7201 #define G_FW_PORT_CMD_OVLAN2(x) \ 7202 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 7203 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 7204 7205 #define S_FW_PORT_CMD_OVLAN1 5 7206 #define M_FW_PORT_CMD_OVLAN1 0x1 7207 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 7208 #define G_FW_PORT_CMD_OVLAN1(x) \ 7209 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 7210 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 7211 7212 #define S_FW_PORT_CMD_OVLAN0 4 7213 #define M_FW_PORT_CMD_OVLAN0 0x1 7214 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 7215 #define G_FW_PORT_CMD_OVLAN0(x) \ 7216 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 7217 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 7218 7219 #define S_FW_PORT_CMD_IVLAN0 3 7220 #define M_FW_PORT_CMD_IVLAN0 0x1 7221 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 7222 #define G_FW_PORT_CMD_IVLAN0(x) \ 7223 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 7224 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 7225 7226 #define S_FW_PORT_CMD_TXIPG 3 7227 #define M_FW_PORT_CMD_TXIPG 0x1fff 7228 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 7229 #define G_FW_PORT_CMD_TXIPG(x) \ 7230 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 7231 7232 #define S_FW_PORT_CMD_FORCE_PINFO 0 7233 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 7234 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 7235 #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 7236 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 7237 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 7238 7239 #define S_FW_PORT_CMD_LSTATUS 31 7240 #define M_FW_PORT_CMD_LSTATUS 0x1 7241 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 7242 #define G_FW_PORT_CMD_LSTATUS(x) \ 7243 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 7244 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 7245 7246 #define S_FW_PORT_CMD_LSPEED 24 7247 #define M_FW_PORT_CMD_LSPEED 0x3f 7248 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 7249 #define G_FW_PORT_CMD_LSPEED(x) \ 7250 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 7251 7252 #define S_FW_PORT_CMD_TXPAUSE 23 7253 #define M_FW_PORT_CMD_TXPAUSE 0x1 7254 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 7255 #define G_FW_PORT_CMD_TXPAUSE(x) \ 7256 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 7257 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 7258 7259 #define S_FW_PORT_CMD_RXPAUSE 22 7260 #define M_FW_PORT_CMD_RXPAUSE 0x1 7261 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 7262 #define G_FW_PORT_CMD_RXPAUSE(x) \ 7263 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 7264 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 7265 7266 #define S_FW_PORT_CMD_MDIOCAP 21 7267 #define M_FW_PORT_CMD_MDIOCAP 0x1 7268 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 7269 #define G_FW_PORT_CMD_MDIOCAP(x) \ 7270 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 7271 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 7272 7273 #define S_FW_PORT_CMD_MDIOADDR 16 7274 #define M_FW_PORT_CMD_MDIOADDR 0x1f 7275 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 7276 #define G_FW_PORT_CMD_MDIOADDR(x) \ 7277 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 7278 7279 #define S_FW_PORT_CMD_LPTXPAUSE 15 7280 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 7281 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 7282 #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 7283 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 7284 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 7285 7286 #define S_FW_PORT_CMD_LPRXPAUSE 14 7287 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 7288 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 7289 #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 7290 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 7291 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 7292 7293 #define S_FW_PORT_CMD_PTYPE 8 7294 #define M_FW_PORT_CMD_PTYPE 0x1f 7295 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 7296 #define G_FW_PORT_CMD_PTYPE(x) \ 7297 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 7298 7299 #define S_FW_PORT_CMD_LINKDNRC 5 7300 #define M_FW_PORT_CMD_LINKDNRC 0x7 7301 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 7302 #define G_FW_PORT_CMD_LINKDNRC(x) \ 7303 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 7304 7305 #define S_FW_PORT_CMD_MODTYPE 0 7306 #define M_FW_PORT_CMD_MODTYPE 0x1f 7307 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 7308 #define G_FW_PORT_CMD_MODTYPE(x) \ 7309 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 7310 7311 #define S_FW_PORT_CMD_DCBXDIS 7 7312 #define M_FW_PORT_CMD_DCBXDIS 0x1 7313 #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 7314 #define G_FW_PORT_CMD_DCBXDIS(x) \ 7315 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 7316 #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 7317 7318 #define S_FW_PORT_CMD_APPLY 7 7319 #define M_FW_PORT_CMD_APPLY 0x1 7320 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 7321 #define G_FW_PORT_CMD_APPLY(x) \ 7322 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 7323 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 7324 7325 #define S_FW_PORT_CMD_ALL_SYNCD 7 7326 #define M_FW_PORT_CMD_ALL_SYNCD 0x1 7327 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 7328 #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 7329 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 7330 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 7331 7332 #define S_FW_PORT_CMD_DCB_VERSION 12 7333 #define M_FW_PORT_CMD_DCB_VERSION 0x7 7334 #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) 7335 #define G_FW_PORT_CMD_DCB_VERSION(x) \ 7336 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) 7337 7338 #define S_FW_PORT_CMD_PFC_STATE 8 7339 #define M_FW_PORT_CMD_PFC_STATE 0xf 7340 #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 7341 #define G_FW_PORT_CMD_PFC_STATE(x) \ 7342 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 7343 7344 #define S_FW_PORT_CMD_ETS_STATE 4 7345 #define M_FW_PORT_CMD_ETS_STATE 0xf 7346 #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 7347 #define G_FW_PORT_CMD_ETS_STATE(x) \ 7348 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 7349 7350 #define S_FW_PORT_CMD_APP_STATE 0 7351 #define M_FW_PORT_CMD_APP_STATE 0xf 7352 #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 7353 #define G_FW_PORT_CMD_APP_STATE(x) \ 7354 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 7355 7356 /* 7357 * These are configured into the VPD and hence tools that generate 7358 * VPD may use this enumeration. 7359 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 7360 * 7361 * REMEMBER: 7362 * Update the Common Code t4_hw.c:t4_get_port_type_description() 7363 * with any new Firmware Port Technology Types! 7364 */ 7365 enum fw_port_type { 7366 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 7367 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 7368 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 7369 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ 7370 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ 7371 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 7372 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 7373 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 7374 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 7375 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 7376 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 7377 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 7378 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 7379 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 7380 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 7381 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 7382 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */ 7383 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ 7384 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */ 7385 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ 7386 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ 7387 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ 7388 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 7389 }; 7390 7391 /* These are read from module's EEPROM and determined once the 7392 module is inserted. */ 7393 enum fw_port_module_type { 7394 FW_PORT_MOD_TYPE_NA = 0x0, 7395 FW_PORT_MOD_TYPE_LR = 0x1, 7396 FW_PORT_MOD_TYPE_SR = 0x2, 7397 FW_PORT_MOD_TYPE_ER = 0x3, 7398 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 7399 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 7400 FW_PORT_MOD_TYPE_LRM = 0x6, 7401 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 7402 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 7403 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 7404 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 7405 }; 7406 7407 /* used by FW and tools may use this to generate VPD */ 7408 enum fw_port_mod_sub_type { 7409 FW_PORT_MOD_SUB_TYPE_NA, 7410 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 7411 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 7412 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 7413 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 7414 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 7415 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 7416 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, 7417 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 7418 7419 /* 7420 * The following will never been in the VPD. They are TWINAX cable 7421 * lengths decoded from SFP+ module i2c PROMs. These should almost 7422 * certainly go somewhere else ... 7423 */ 7424 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 7425 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 7426 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 7427 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 7428 }; 7429 7430 /* link down reason codes (3b) */ 7431 enum fw_port_link_dn_rc { 7432 FW_PORT_LINK_DN_RC_NONE, 7433 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 7434 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 7435 FW_PORT_LINK_DN_RESERVED3, 7436 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 7437 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 7438 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 7439 FW_PORT_LINK_DN_RESERVED7 7440 }; 7441 enum fw_port_stats_tx_index { 7442 FW_STAT_TX_PORT_BYTES_IX = 0, 7443 FW_STAT_TX_PORT_FRAMES_IX, 7444 FW_STAT_TX_PORT_BCAST_IX, 7445 FW_STAT_TX_PORT_MCAST_IX, 7446 FW_STAT_TX_PORT_UCAST_IX, 7447 FW_STAT_TX_PORT_ERROR_IX, 7448 FW_STAT_TX_PORT_64B_IX, 7449 FW_STAT_TX_PORT_65B_127B_IX, 7450 FW_STAT_TX_PORT_128B_255B_IX, 7451 FW_STAT_TX_PORT_256B_511B_IX, 7452 FW_STAT_TX_PORT_512B_1023B_IX, 7453 FW_STAT_TX_PORT_1024B_1518B_IX, 7454 FW_STAT_TX_PORT_1519B_MAX_IX, 7455 FW_STAT_TX_PORT_DROP_IX, 7456 FW_STAT_TX_PORT_PAUSE_IX, 7457 FW_STAT_TX_PORT_PPP0_IX, 7458 FW_STAT_TX_PORT_PPP1_IX, 7459 FW_STAT_TX_PORT_PPP2_IX, 7460 FW_STAT_TX_PORT_PPP3_IX, 7461 FW_STAT_TX_PORT_PPP4_IX, 7462 FW_STAT_TX_PORT_PPP5_IX, 7463 FW_STAT_TX_PORT_PPP6_IX, 7464 FW_STAT_TX_PORT_PPP7_IX, 7465 FW_NUM_PORT_TX_STATS 7466 }; 7467 7468 enum fw_port_stat_rx_index { 7469 FW_STAT_RX_PORT_BYTES_IX = 0, 7470 FW_STAT_RX_PORT_FRAMES_IX, 7471 FW_STAT_RX_PORT_BCAST_IX, 7472 FW_STAT_RX_PORT_MCAST_IX, 7473 FW_STAT_RX_PORT_UCAST_IX, 7474 FW_STAT_RX_PORT_MTU_ERROR_IX, 7475 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 7476 FW_STAT_RX_PORT_CRC_ERROR_IX, 7477 FW_STAT_RX_PORT_LEN_ERROR_IX, 7478 FW_STAT_RX_PORT_SYM_ERROR_IX, 7479 FW_STAT_RX_PORT_64B_IX, 7480 FW_STAT_RX_PORT_65B_127B_IX, 7481 FW_STAT_RX_PORT_128B_255B_IX, 7482 FW_STAT_RX_PORT_256B_511B_IX, 7483 FW_STAT_RX_PORT_512B_1023B_IX, 7484 FW_STAT_RX_PORT_1024B_1518B_IX, 7485 FW_STAT_RX_PORT_1519B_MAX_IX, 7486 FW_STAT_RX_PORT_PAUSE_IX, 7487 FW_STAT_RX_PORT_PPP0_IX, 7488 FW_STAT_RX_PORT_PPP1_IX, 7489 FW_STAT_RX_PORT_PPP2_IX, 7490 FW_STAT_RX_PORT_PPP3_IX, 7491 FW_STAT_RX_PORT_PPP4_IX, 7492 FW_STAT_RX_PORT_PPP5_IX, 7493 FW_STAT_RX_PORT_PPP6_IX, 7494 FW_STAT_RX_PORT_PPP7_IX, 7495 FW_STAT_RX_PORT_LESS_64B_IX, 7496 FW_STAT_RX_PORT_MAC_ERROR_IX, 7497 FW_NUM_PORT_RX_STATS 7498 }; 7499 /* port stats */ 7500 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ 7501 FW_NUM_PORT_RX_STATS) 7502 7503 7504 struct fw_port_stats_cmd { 7505 __be32 op_to_portid; 7506 __be32 retval_len16; 7507 union fw_port_stats { 7508 struct fw_port_stats_ctl { 7509 __u8 nstats_bg_bm; 7510 __u8 tx_ix; 7511 __be16 r6; 7512 __be32 r7; 7513 __be64 stat0; 7514 __be64 stat1; 7515 __be64 stat2; 7516 __be64 stat3; 7517 __be64 stat4; 7518 __be64 stat5; 7519 } ctl; 7520 struct fw_port_stats_all { 7521 __be64 tx_bytes; 7522 __be64 tx_frames; 7523 __be64 tx_bcast; 7524 __be64 tx_mcast; 7525 __be64 tx_ucast; 7526 __be64 tx_error; 7527 __be64 tx_64b; 7528 __be64 tx_65b_127b; 7529 __be64 tx_128b_255b; 7530 __be64 tx_256b_511b; 7531 __be64 tx_512b_1023b; 7532 __be64 tx_1024b_1518b; 7533 __be64 tx_1519b_max; 7534 __be64 tx_drop; 7535 __be64 tx_pause; 7536 __be64 tx_ppp0; 7537 __be64 tx_ppp1; 7538 __be64 tx_ppp2; 7539 __be64 tx_ppp3; 7540 __be64 tx_ppp4; 7541 __be64 tx_ppp5; 7542 __be64 tx_ppp6; 7543 __be64 tx_ppp7; 7544 __be64 rx_bytes; 7545 __be64 rx_frames; 7546 __be64 rx_bcast; 7547 __be64 rx_mcast; 7548 __be64 rx_ucast; 7549 __be64 rx_mtu_error; 7550 __be64 rx_mtu_crc_error; 7551 __be64 rx_crc_error; 7552 __be64 rx_len_error; 7553 __be64 rx_sym_error; 7554 __be64 rx_64b; 7555 __be64 rx_65b_127b; 7556 __be64 rx_128b_255b; 7557 __be64 rx_256b_511b; 7558 __be64 rx_512b_1023b; 7559 __be64 rx_1024b_1518b; 7560 __be64 rx_1519b_max; 7561 __be64 rx_pause; 7562 __be64 rx_ppp0; 7563 __be64 rx_ppp1; 7564 __be64 rx_ppp2; 7565 __be64 rx_ppp3; 7566 __be64 rx_ppp4; 7567 __be64 rx_ppp5; 7568 __be64 rx_ppp6; 7569 __be64 rx_ppp7; 7570 __be64 rx_less_64b; 7571 __be64 rx_bg_drop; 7572 __be64 rx_bg_trunc; 7573 } all; 7574 } u; 7575 }; 7576 7577 #define S_FW_PORT_STATS_CMD_NSTATS 4 7578 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 7579 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 7580 #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 7581 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 7582 7583 #define S_FW_PORT_STATS_CMD_BG_BM 0 7584 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 7585 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 7586 #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 7587 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 7588 7589 #define S_FW_PORT_STATS_CMD_TX 7 7590 #define M_FW_PORT_STATS_CMD_TX 0x1 7591 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 7592 #define G_FW_PORT_STATS_CMD_TX(x) \ 7593 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 7594 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 7595 7596 #define S_FW_PORT_STATS_CMD_IX 0 7597 #define M_FW_PORT_STATS_CMD_IX 0x3f 7598 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 7599 #define G_FW_PORT_STATS_CMD_IX(x) \ 7600 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 7601 7602 /* port loopback stats */ 7603 #define FW_NUM_LB_STATS 14 7604 enum fw_port_lb_stats_index { 7605 FW_STAT_LB_PORT_BYTES_IX, 7606 FW_STAT_LB_PORT_FRAMES_IX, 7607 FW_STAT_LB_PORT_BCAST_IX, 7608 FW_STAT_LB_PORT_MCAST_IX, 7609 FW_STAT_LB_PORT_UCAST_IX, 7610 FW_STAT_LB_PORT_ERROR_IX, 7611 FW_STAT_LB_PORT_64B_IX, 7612 FW_STAT_LB_PORT_65B_127B_IX, 7613 FW_STAT_LB_PORT_128B_255B_IX, 7614 FW_STAT_LB_PORT_256B_511B_IX, 7615 FW_STAT_LB_PORT_512B_1023B_IX, 7616 FW_STAT_LB_PORT_1024B_1518B_IX, 7617 FW_STAT_LB_PORT_1519B_MAX_IX, 7618 FW_STAT_LB_PORT_DROP_FRAMES_IX 7619 }; 7620 7621 struct fw_port_lb_stats_cmd { 7622 __be32 op_to_lbport; 7623 __be32 retval_len16; 7624 union fw_port_lb_stats { 7625 struct fw_port_lb_stats_ctl { 7626 __u8 nstats_bg_bm; 7627 __u8 ix_pkd; 7628 __be16 r6; 7629 __be32 r7; 7630 __be64 stat0; 7631 __be64 stat1; 7632 __be64 stat2; 7633 __be64 stat3; 7634 __be64 stat4; 7635 __be64 stat5; 7636 } ctl; 7637 struct fw_port_lb_stats_all { 7638 __be64 tx_bytes; 7639 __be64 tx_frames; 7640 __be64 tx_bcast; 7641 __be64 tx_mcast; 7642 __be64 tx_ucast; 7643 __be64 tx_error; 7644 __be64 tx_64b; 7645 __be64 tx_65b_127b; 7646 __be64 tx_128b_255b; 7647 __be64 tx_256b_511b; 7648 __be64 tx_512b_1023b; 7649 __be64 tx_1024b_1518b; 7650 __be64 tx_1519b_max; 7651 __be64 rx_lb_drop; 7652 __be64 rx_lb_trunc; 7653 } all; 7654 } u; 7655 }; 7656 7657 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 7658 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 7659 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7660 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 7661 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7662 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 7663 7664 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 7665 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 7666 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7667 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 7668 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7669 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 7670 7671 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 7672 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 7673 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 7674 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 7675 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 7676 7677 #define S_FW_PORT_LB_STATS_CMD_IX 0 7678 #define M_FW_PORT_LB_STATS_CMD_IX 0xf 7679 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 7680 #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 7681 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 7682 7683 /* Trace related defines */ 7684 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 7685 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 7686 7687 struct fw_port_trace_cmd { 7688 __be32 op_to_portid; 7689 __be32 retval_len16; 7690 __be16 traceen_to_pciech; 7691 __be16 qnum; 7692 __be32 r5; 7693 }; 7694 7695 #define S_FW_PORT_TRACE_CMD_PORTID 0 7696 #define M_FW_PORT_TRACE_CMD_PORTID 0xf 7697 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 7698 #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 7699 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 7700 7701 #define S_FW_PORT_TRACE_CMD_TRACEEN 15 7702 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 7703 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 7704 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 7705 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 7706 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 7707 7708 #define S_FW_PORT_TRACE_CMD_FLTMODE 14 7709 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 7710 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 7711 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 7712 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 7713 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 7714 7715 #define S_FW_PORT_TRACE_CMD_DUPLEN 13 7716 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 7717 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 7718 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 7719 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 7720 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 7721 7722 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 7723 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 7724 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 7725 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 7726 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 7727 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 7728 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 7729 7730 #define S_FW_PORT_TRACE_CMD_PCIECH 6 7731 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 7732 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 7733 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 7734 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 7735 7736 struct fw_port_trace_mmap_cmd { 7737 __be32 op_to_portid; 7738 __be32 retval_len16; 7739 __be32 fid_to_skipoffset; 7740 __be32 minpktsize_capturemax; 7741 __u8 map[224]; 7742 }; 7743 7744 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 7745 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 7746 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 7747 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 7748 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 7749 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 7750 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 7751 7752 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 7753 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 7754 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 7755 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 7756 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 7757 7758 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 7759 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 7760 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 7761 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 7762 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 7763 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 7764 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 7765 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 7766 7767 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 7768 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 7769 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 7770 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 7771 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 7772 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 7773 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 7774 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 7775 7776 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 7777 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 7778 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 7779 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 7780 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 7781 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 7782 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 7783 7784 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 7785 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 7786 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 7787 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 7788 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 7789 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 7790 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 7791 7792 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 7793 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 7794 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 7795 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 7796 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 7797 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 7798 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 7799 7800 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 7801 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 7802 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 7803 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 7804 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 7805 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 7806 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 7807 7808 enum fw_ptp_subop { 7809 7810 /* none */ 7811 FW_PTP_SC_INIT_TIMER = 0x00, 7812 FW_PTP_SC_TX_TYPE = 0x01, 7813 7814 /* init */ 7815 FW_PTP_SC_RXTIME_STAMP = 0x08, 7816 FW_PTP_SC_RDRX_TYPE = 0x09, 7817 7818 /* ts */ 7819 FW_PTP_SC_ADJ_FREQ = 0x10, 7820 FW_PTP_SC_ADJ_TIME = 0x11, 7821 FW_PTP_SC_ADJ_FTIME = 0x12, 7822 FW_PTP_SC_WALL_CLOCK = 0x13, 7823 FW_PTP_SC_GET_TIME = 0x14, 7824 FW_PTP_SC_SET_TIME = 0x15, 7825 }; 7826 7827 struct fw_ptp_cmd { 7828 __be32 op_to_portid; 7829 __be32 retval_len16; 7830 union fw_ptp { 7831 struct fw_ptp_sc { 7832 __u8 sc; 7833 __u8 r3[7]; 7834 } scmd; 7835 struct fw_ptp_init { 7836 __u8 sc; 7837 __u8 txchan; 7838 __be16 absid; 7839 __be16 mode; 7840 __be16 r3; 7841 } init; 7842 struct fw_ptp_ts { 7843 __u8 sc; 7844 __u8 sign; 7845 __be16 r3; 7846 __be32 ppb; 7847 __be64 tm; 7848 } ts; 7849 } u; 7850 __be64 r3; 7851 }; 7852 7853 #define S_FW_PTP_CMD_PORTID 0 7854 #define M_FW_PTP_CMD_PORTID 0xf 7855 #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) 7856 #define G_FW_PTP_CMD_PORTID(x) \ 7857 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) 7858 7859 struct fw_rss_ind_tbl_cmd { 7860 __be32 op_to_viid; 7861 __be32 retval_len16; 7862 __be16 niqid; 7863 __be16 startidx; 7864 __be32 r3; 7865 __be32 iq0_to_iq2; 7866 __be32 iq3_to_iq5; 7867 __be32 iq6_to_iq8; 7868 __be32 iq9_to_iq11; 7869 __be32 iq12_to_iq14; 7870 __be32 iq15_to_iq17; 7871 __be32 iq18_to_iq20; 7872 __be32 iq21_to_iq23; 7873 __be32 iq24_to_iq26; 7874 __be32 iq27_to_iq29; 7875 __be32 iq30_iq31; 7876 __be32 r15_lo; 7877 }; 7878 7879 #define S_FW_RSS_IND_TBL_CMD_VIID 0 7880 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 7881 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 7882 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 7883 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 7884 7885 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 7886 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 7887 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 7888 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 7889 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 7890 7891 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 7892 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 7893 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 7894 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 7895 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 7896 7897 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 7898 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 7899 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 7900 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 7901 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 7902 7903 #define S_FW_RSS_IND_TBL_CMD_IQ3 20 7904 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 7905 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 7906 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 7907 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 7908 7909 #define S_FW_RSS_IND_TBL_CMD_IQ4 10 7910 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 7911 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 7912 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 7913 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 7914 7915 #define S_FW_RSS_IND_TBL_CMD_IQ5 0 7916 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 7917 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 7918 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 7919 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 7920 7921 #define S_FW_RSS_IND_TBL_CMD_IQ6 20 7922 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 7923 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 7924 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 7925 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 7926 7927 #define S_FW_RSS_IND_TBL_CMD_IQ7 10 7928 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 7929 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 7930 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 7931 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 7932 7933 #define S_FW_RSS_IND_TBL_CMD_IQ8 0 7934 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 7935 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 7936 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 7937 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 7938 7939 #define S_FW_RSS_IND_TBL_CMD_IQ9 20 7940 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 7941 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 7942 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 7943 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 7944 7945 #define S_FW_RSS_IND_TBL_CMD_IQ10 10 7946 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 7947 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 7948 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 7949 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 7950 7951 #define S_FW_RSS_IND_TBL_CMD_IQ11 0 7952 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 7953 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 7954 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 7955 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 7956 7957 #define S_FW_RSS_IND_TBL_CMD_IQ12 20 7958 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 7959 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 7960 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 7961 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 7962 7963 #define S_FW_RSS_IND_TBL_CMD_IQ13 10 7964 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 7965 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 7966 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 7967 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 7968 7969 #define S_FW_RSS_IND_TBL_CMD_IQ14 0 7970 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 7971 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 7972 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 7973 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 7974 7975 #define S_FW_RSS_IND_TBL_CMD_IQ15 20 7976 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 7977 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 7978 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 7979 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 7980 7981 #define S_FW_RSS_IND_TBL_CMD_IQ16 10 7982 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 7983 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 7984 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 7985 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 7986 7987 #define S_FW_RSS_IND_TBL_CMD_IQ17 0 7988 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 7989 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 7990 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 7991 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 7992 7993 #define S_FW_RSS_IND_TBL_CMD_IQ18 20 7994 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 7995 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 7996 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 7997 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 7998 7999 #define S_FW_RSS_IND_TBL_CMD_IQ19 10 8000 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 8001 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 8002 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 8003 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 8004 8005 #define S_FW_RSS_IND_TBL_CMD_IQ20 0 8006 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 8007 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 8008 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 8009 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 8010 8011 #define S_FW_RSS_IND_TBL_CMD_IQ21 20 8012 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 8013 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 8014 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 8015 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 8016 8017 #define S_FW_RSS_IND_TBL_CMD_IQ22 10 8018 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 8019 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 8020 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 8021 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 8022 8023 #define S_FW_RSS_IND_TBL_CMD_IQ23 0 8024 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 8025 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 8026 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 8027 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 8028 8029 #define S_FW_RSS_IND_TBL_CMD_IQ24 20 8030 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 8031 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 8032 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 8033 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 8034 8035 #define S_FW_RSS_IND_TBL_CMD_IQ25 10 8036 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 8037 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 8038 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 8039 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 8040 8041 #define S_FW_RSS_IND_TBL_CMD_IQ26 0 8042 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 8043 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 8044 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 8045 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 8046 8047 #define S_FW_RSS_IND_TBL_CMD_IQ27 20 8048 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 8049 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 8050 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 8051 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 8052 8053 #define S_FW_RSS_IND_TBL_CMD_IQ28 10 8054 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 8055 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 8056 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 8057 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 8058 8059 #define S_FW_RSS_IND_TBL_CMD_IQ29 0 8060 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 8061 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 8062 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 8063 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 8064 8065 #define S_FW_RSS_IND_TBL_CMD_IQ30 20 8066 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 8067 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 8068 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 8069 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 8070 8071 #define S_FW_RSS_IND_TBL_CMD_IQ31 10 8072 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 8073 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 8074 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 8075 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 8076 8077 struct fw_rss_glb_config_cmd { 8078 __be32 op_to_write; 8079 __be32 retval_len16; 8080 union fw_rss_glb_config { 8081 struct fw_rss_glb_config_manual { 8082 __be32 mode_pkd; 8083 __be32 r3; 8084 __be64 r4; 8085 __be64 r5; 8086 } manual; 8087 struct fw_rss_glb_config_basicvirtual { 8088 __be32 mode_keymode; 8089 __be32 synmapen_to_hashtoeplitz; 8090 __be64 r8; 8091 __be64 r9; 8092 } basicvirtual; 8093 } u; 8094 }; 8095 8096 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 8097 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 8098 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 8099 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 8100 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 8101 8102 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 8103 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 8104 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 8105 8106 #define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26 8107 #define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3 8108 #define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8109 ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8110 #define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8111 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \ 8112 M_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8113 8114 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0 8115 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1 8116 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2 8117 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3 8118 8119 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 8120 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 8121 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8122 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8123 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8124 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 8125 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8126 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 8127 8128 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 8129 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 8130 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8131 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8132 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8133 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 8134 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8135 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 8136 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 8137 8138 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 8139 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 8140 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8141 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8142 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8143 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 8144 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8145 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 8146 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 8147 8148 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 8149 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 8150 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8151 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8152 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8153 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 8154 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8155 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 8156 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 8157 8158 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 8159 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 8160 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8161 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8162 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8163 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 8164 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8165 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 8166 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 8167 8168 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 8169 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 8170 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8171 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8172 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8173 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 8174 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8175 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 8176 8177 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 8178 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 8179 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8180 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8181 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8182 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 8183 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8184 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 8185 8186 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 8187 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 8188 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8189 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8190 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8191 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 8192 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8193 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 8194 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 8195 8196 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 8197 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 8198 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8199 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8200 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8201 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 8202 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8203 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 8204 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 8205 8206 struct fw_rss_vi_config_cmd { 8207 __be32 op_to_viid; 8208 __be32 retval_len16; 8209 union fw_rss_vi_config { 8210 struct fw_rss_vi_config_manual { 8211 __be64 r3; 8212 __be64 r4; 8213 __be64 r5; 8214 } manual; 8215 struct fw_rss_vi_config_basicvirtual { 8216 __be32 r6; 8217 __be32 defaultq_to_udpen; 8218 __be32 secretkeyidx_pkd; 8219 __be32 secretkeyxor; 8220 __be64 r10; 8221 } basicvirtual; 8222 } u; 8223 }; 8224 8225 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 8226 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 8227 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 8228 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 8229 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 8230 8231 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 8232 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 8233 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8234 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8235 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8236 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 8237 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8238 8239 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 8240 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 8241 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8242 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8243 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8244 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 8245 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8246 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 8247 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 8248 8249 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 8250 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 8251 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8252 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8253 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8254 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 8255 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8256 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 8257 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 8258 8259 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 8260 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 8261 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8262 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8263 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8264 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 8265 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8266 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 8267 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 8268 8269 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 8270 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 8271 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8272 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8273 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8274 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 8275 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8276 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 8277 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 8278 8279 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 8280 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 8281 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 8282 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 8283 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 8284 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 8285 8286 #define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0 8287 #define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf 8288 #define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8289 ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 8290 #define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8291 (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \ 8292 M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 8293 8294 enum fw_sched_sc { 8295 FW_SCHED_SC_CONFIG = 0, 8296 FW_SCHED_SC_PARAMS = 1, 8297 }; 8298 8299 enum fw_sched_type { 8300 FW_SCHED_TYPE_PKTSCHED = 0, 8301 FW_SCHED_TYPE_STREAMSCHED = 1, 8302 }; 8303 8304 enum fw_sched_params_level { 8305 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 8306 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 8307 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 8308 }; 8309 8310 enum fw_sched_params_mode { 8311 FW_SCHED_PARAMS_MODE_CLASS = 0, 8312 FW_SCHED_PARAMS_MODE_FLOW = 1, 8313 }; 8314 8315 enum fw_sched_params_unit { 8316 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 8317 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 8318 }; 8319 8320 enum fw_sched_params_rate { 8321 FW_SCHED_PARAMS_RATE_REL = 0, 8322 FW_SCHED_PARAMS_RATE_ABS = 1, 8323 }; 8324 8325 struct fw_sched_cmd { 8326 __be32 op_to_write; 8327 __be32 retval_len16; 8328 union fw_sched { 8329 struct fw_sched_config { 8330 __u8 sc; 8331 __u8 type; 8332 __u8 minmaxen; 8333 __u8 r3[5]; 8334 __u8 nclasses[4]; 8335 __be32 r4; 8336 } config; 8337 struct fw_sched_params { 8338 __u8 sc; 8339 __u8 type; 8340 __u8 level; 8341 __u8 mode; 8342 __u8 unit; 8343 __u8 rate; 8344 __u8 ch; 8345 __u8 cl; 8346 __be32 min; 8347 __be32 max; 8348 __be16 weight; 8349 __be16 pktsize; 8350 __be16 burstsize; 8351 __be16 r4; 8352 } params; 8353 } u; 8354 }; 8355 8356 /* 8357 * length of the formatting string 8358 */ 8359 #define FW_DEVLOG_FMT_LEN 192 8360 8361 /* 8362 * maximum number of the formatting string parameters 8363 */ 8364 #define FW_DEVLOG_FMT_PARAMS_NUM 8 8365 8366 /* 8367 * priority levels 8368 */ 8369 enum fw_devlog_level { 8370 FW_DEVLOG_LEVEL_EMERG = 0x0, 8371 FW_DEVLOG_LEVEL_CRIT = 0x1, 8372 FW_DEVLOG_LEVEL_ERR = 0x2, 8373 FW_DEVLOG_LEVEL_NOTICE = 0x3, 8374 FW_DEVLOG_LEVEL_INFO = 0x4, 8375 FW_DEVLOG_LEVEL_DEBUG = 0x5, 8376 FW_DEVLOG_LEVEL_MAX = 0x5, 8377 }; 8378 8379 /* 8380 * facilities that may send a log message 8381 */ 8382 enum fw_devlog_facility { 8383 FW_DEVLOG_FACILITY_CORE = 0x00, 8384 FW_DEVLOG_FACILITY_CF = 0x01, 8385 FW_DEVLOG_FACILITY_SCHED = 0x02, 8386 FW_DEVLOG_FACILITY_TIMER = 0x04, 8387 FW_DEVLOG_FACILITY_RES = 0x06, 8388 FW_DEVLOG_FACILITY_HW = 0x08, 8389 FW_DEVLOG_FACILITY_FLR = 0x10, 8390 FW_DEVLOG_FACILITY_DMAQ = 0x12, 8391 FW_DEVLOG_FACILITY_PHY = 0x14, 8392 FW_DEVLOG_FACILITY_MAC = 0x16, 8393 FW_DEVLOG_FACILITY_PORT = 0x18, 8394 FW_DEVLOG_FACILITY_VI = 0x1A, 8395 FW_DEVLOG_FACILITY_FILTER = 0x1C, 8396 FW_DEVLOG_FACILITY_ACL = 0x1E, 8397 FW_DEVLOG_FACILITY_TM = 0x20, 8398 FW_DEVLOG_FACILITY_QFC = 0x22, 8399 FW_DEVLOG_FACILITY_DCB = 0x24, 8400 FW_DEVLOG_FACILITY_ETH = 0x26, 8401 FW_DEVLOG_FACILITY_OFLD = 0x28, 8402 FW_DEVLOG_FACILITY_RI = 0x2A, 8403 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 8404 FW_DEVLOG_FACILITY_FCOE = 0x2E, 8405 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 8406 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 8407 FW_DEVLOG_FACILITY_CHNET = 0x34, 8408 FW_DEVLOG_FACILITY_COiSCSI = 0x36, 8409 FW_DEVLOG_FACILITY_MAX = 0x38, 8410 }; 8411 8412 /* 8413 * log message format 8414 */ 8415 struct fw_devlog_e { 8416 __be64 timestamp; 8417 __be32 seqno; 8418 __be16 reserved1; 8419 __u8 level; 8420 __u8 facility; 8421 __u8 fmt[FW_DEVLOG_FMT_LEN]; 8422 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 8423 __be32 reserved3[4]; 8424 }; 8425 8426 struct fw_devlog_cmd { 8427 __be32 op_to_write; 8428 __be32 retval_len16; 8429 __u8 level; 8430 __u8 r2[7]; 8431 __be32 memtype_devlog_memaddr16_devlog; 8432 __be32 memsize_devlog; 8433 __be32 r3[2]; 8434 }; 8435 8436 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 8437 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 8438 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8439 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8440 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8441 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8442 8443 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 8444 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 8445 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8446 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8447 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8448 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 8449 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8450 8451 enum fw_watchdog_actions { 8452 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 8453 FW_WATCHDOG_ACTION_FLR = 1, 8454 FW_WATCHDOG_ACTION_BYPASS = 2, 8455 FW_WATCHDOG_ACTION_TMPCHK = 3, 8456 FW_WATCHDOG_ACTION_PAUSEOFF = 4, 8457 8458 FW_WATCHDOG_ACTION_MAX = 5, 8459 }; 8460 8461 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 8462 8463 struct fw_watchdog_cmd { 8464 __be32 op_to_vfn; 8465 __be32 retval_len16; 8466 __be32 timeout; 8467 __be32 action; 8468 }; 8469 8470 #define S_FW_WATCHDOG_CMD_PFN 8 8471 #define M_FW_WATCHDOG_CMD_PFN 0x7 8472 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 8473 #define G_FW_WATCHDOG_CMD_PFN(x) \ 8474 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 8475 8476 #define S_FW_WATCHDOG_CMD_VFN 0 8477 #define M_FW_WATCHDOG_CMD_VFN 0xff 8478 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 8479 #define G_FW_WATCHDOG_CMD_VFN(x) \ 8480 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 8481 8482 struct fw_clip_cmd { 8483 __be32 op_to_write; 8484 __be32 alloc_to_len16; 8485 __be64 ip_hi; 8486 __be64 ip_lo; 8487 __be32 r4[2]; 8488 }; 8489 8490 #define S_FW_CLIP_CMD_ALLOC 31 8491 #define M_FW_CLIP_CMD_ALLOC 0x1 8492 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 8493 #define G_FW_CLIP_CMD_ALLOC(x) \ 8494 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 8495 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 8496 8497 #define S_FW_CLIP_CMD_FREE 30 8498 #define M_FW_CLIP_CMD_FREE 0x1 8499 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 8500 #define G_FW_CLIP_CMD_FREE(x) \ 8501 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 8502 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 8503 8504 /****************************************************************************** 8505 * F O i S C S I C O M M A N D s 8506 **************************************/ 8507 8508 #define FW_CHNET_IFACE_ADDR_MAX 3 8509 8510 enum fw_chnet_iface_cmd_subop { 8511 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 8512 8513 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 8514 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 8515 8516 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 8517 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 8518 8519 FW_CHNET_IFACE_CMD_SUBOP_MAX, 8520 }; 8521 8522 struct fw_chnet_iface_cmd { 8523 __be32 op_to_portid; 8524 __be32 retval_len16; 8525 __u8 subop; 8526 __u8 r2[3]; 8527 __be32 ifid_ifstate; 8528 __be16 mtu; 8529 __be16 vlanid; 8530 __be32 r3; 8531 __be16 r4; 8532 __u8 mac[6]; 8533 }; 8534 8535 #define S_FW_CHNET_IFACE_CMD_PORTID 0 8536 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 8537 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 8538 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 8539 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 8540 8541 #define S_FW_CHNET_IFACE_CMD_IFID 8 8542 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 8543 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 8544 #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 8545 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 8546 8547 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 8548 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 8549 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 8550 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 8551 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 8552 8553 struct fw_fcoe_res_info_cmd { 8554 __be32 op_to_read; 8555 __be32 retval_len16; 8556 __be16 e_d_tov; 8557 __be16 r_a_tov_seq; 8558 __be16 r_a_tov_els; 8559 __be16 r_r_tov; 8560 __be32 max_xchgs; 8561 __be32 max_ssns; 8562 __be32 used_xchgs; 8563 __be32 used_ssns; 8564 __be32 max_fcfs; 8565 __be32 max_vnps; 8566 __be32 used_fcfs; 8567 __be32 used_vnps; 8568 }; 8569 8570 struct fw_fcoe_link_cmd { 8571 __be32 op_to_portid; 8572 __be32 retval_len16; 8573 __be32 sub_opcode_fcfi; 8574 __u8 r3; 8575 __u8 lstatus; 8576 __be16 flags; 8577 __u8 r4; 8578 __u8 set_vlan; 8579 __be16 vlan_id; 8580 __be32 vnpi_pkd; 8581 __be16 r6; 8582 __u8 phy_mac[6]; 8583 __u8 vnport_wwnn[8]; 8584 __u8 vnport_wwpn[8]; 8585 }; 8586 8587 #define S_FW_FCOE_LINK_CMD_PORTID 0 8588 #define M_FW_FCOE_LINK_CMD_PORTID 0xf 8589 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 8590 #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 8591 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 8592 8593 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 8594 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 8595 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 8596 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 8597 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 8598 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 8599 8600 #define S_FW_FCOE_LINK_CMD_FCFI 0 8601 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 8602 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 8603 #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 8604 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 8605 8606 #define S_FW_FCOE_LINK_CMD_VNPI 0 8607 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 8608 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 8609 #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 8610 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 8611 8612 struct fw_fcoe_vnp_cmd { 8613 __be32 op_to_fcfi; 8614 __be32 alloc_to_len16; 8615 __be32 gen_wwn_to_vnpi; 8616 __be32 vf_id; 8617 __be16 iqid; 8618 __u8 vnport_mac[6]; 8619 __u8 vnport_wwnn[8]; 8620 __u8 vnport_wwpn[8]; 8621 __u8 cmn_srv_parms[16]; 8622 __u8 clsp_word_0_1[8]; 8623 }; 8624 8625 #define S_FW_FCOE_VNP_CMD_FCFI 0 8626 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 8627 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 8628 #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 8629 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 8630 8631 #define S_FW_FCOE_VNP_CMD_ALLOC 31 8632 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 8633 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 8634 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 8635 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 8636 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 8637 8638 #define S_FW_FCOE_VNP_CMD_FREE 30 8639 #define M_FW_FCOE_VNP_CMD_FREE 0x1 8640 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 8641 #define G_FW_FCOE_VNP_CMD_FREE(x) \ 8642 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 8643 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 8644 8645 #define S_FW_FCOE_VNP_CMD_MODIFY 29 8646 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 8647 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 8648 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 8649 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 8650 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 8651 8652 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 8653 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 8654 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 8655 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 8656 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 8657 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 8658 8659 #define S_FW_FCOE_VNP_CMD_PERSIST 21 8660 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 8661 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 8662 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 8663 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 8664 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 8665 8666 #define S_FW_FCOE_VNP_CMD_VFID_EN 20 8667 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 8668 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 8669 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 8670 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 8671 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 8672 8673 #define S_FW_FCOE_VNP_CMD_VNPI 0 8674 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 8675 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 8676 #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 8677 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 8678 8679 struct fw_fcoe_sparams_cmd { 8680 __be32 op_to_portid; 8681 __be32 retval_len16; 8682 __u8 r3[7]; 8683 __u8 cos; 8684 __u8 lport_wwnn[8]; 8685 __u8 lport_wwpn[8]; 8686 __u8 cmn_srv_parms[16]; 8687 __u8 cls_srv_parms[16]; 8688 }; 8689 8690 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 8691 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 8692 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 8693 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 8694 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 8695 8696 struct fw_fcoe_stats_cmd { 8697 __be32 op_to_flowid; 8698 __be32 free_to_len16; 8699 union fw_fcoe_stats { 8700 struct fw_fcoe_stats_ctl { 8701 __u8 nstats_port; 8702 __u8 port_valid_ix; 8703 __be16 r6; 8704 __be32 r7; 8705 __be64 stat0; 8706 __be64 stat1; 8707 __be64 stat2; 8708 __be64 stat3; 8709 __be64 stat4; 8710 __be64 stat5; 8711 } ctl; 8712 struct fw_fcoe_port_stats { 8713 __be64 tx_bcast_bytes; 8714 __be64 tx_bcast_frames; 8715 __be64 tx_mcast_bytes; 8716 __be64 tx_mcast_frames; 8717 __be64 tx_ucast_bytes; 8718 __be64 tx_ucast_frames; 8719 __be64 tx_drop_frames; 8720 __be64 tx_offload_bytes; 8721 __be64 tx_offload_frames; 8722 __be64 rx_bcast_bytes; 8723 __be64 rx_bcast_frames; 8724 __be64 rx_mcast_bytes; 8725 __be64 rx_mcast_frames; 8726 __be64 rx_ucast_bytes; 8727 __be64 rx_ucast_frames; 8728 __be64 rx_err_frames; 8729 } port_stats; 8730 struct fw_fcoe_fcf_stats { 8731 __be32 fip_tx_bytes; 8732 __be32 fip_tx_fr; 8733 __be64 fcf_ka; 8734 __be64 mcast_adv_rcvd; 8735 __be16 ucast_adv_rcvd; 8736 __be16 sol_sent; 8737 __be16 vlan_req; 8738 __be16 vlan_rpl; 8739 __be16 clr_vlink; 8740 __be16 link_down; 8741 __be16 link_up; 8742 __be16 logo; 8743 __be16 flogi_req; 8744 __be16 flogi_rpl; 8745 __be16 fdisc_req; 8746 __be16 fdisc_rpl; 8747 __be16 fka_prd_chg; 8748 __be16 fc_map_chg; 8749 __be16 vfid_chg; 8750 __u8 no_fka_req; 8751 __u8 no_vnp; 8752 } fcf_stats; 8753 struct fw_fcoe_pcb_stats { 8754 __be64 tx_bytes; 8755 __be64 tx_frames; 8756 __be64 rx_bytes; 8757 __be64 rx_frames; 8758 __be32 vnp_ka; 8759 __be32 unsol_els_rcvd; 8760 __be64 unsol_cmd_rcvd; 8761 __be16 implicit_logo; 8762 __be16 flogi_inv_sparm; 8763 __be16 fdisc_inv_sparm; 8764 __be16 flogi_rjt; 8765 __be16 fdisc_rjt; 8766 __be16 no_ssn; 8767 __be16 mac_flt_fail; 8768 __be16 inv_fr_rcvd; 8769 } pcb_stats; 8770 struct fw_fcoe_scb_stats { 8771 __be64 tx_bytes; 8772 __be64 tx_frames; 8773 __be64 rx_bytes; 8774 __be64 rx_frames; 8775 __be32 host_abrt_req; 8776 __be32 adap_auto_abrt; 8777 __be32 adap_abrt_rsp; 8778 __be32 host_ios_req; 8779 __be16 ssn_offl_ios; 8780 __be16 ssn_not_rdy_ios; 8781 __u8 rx_data_ddp_err; 8782 __u8 ddp_flt_set_err; 8783 __be16 rx_data_fr_err; 8784 __u8 bad_st_abrt_req; 8785 __u8 no_io_abrt_req; 8786 __u8 abort_tmo; 8787 __u8 abort_tmo_2; 8788 __be32 abort_req; 8789 __u8 no_ppod_res_tmo; 8790 __u8 bp_tmo; 8791 __u8 adap_auto_cls; 8792 __u8 no_io_cls_req; 8793 __be32 host_cls_req; 8794 __be64 unsol_cmd_rcvd; 8795 __be32 plogi_req_rcvd; 8796 __be32 prli_req_rcvd; 8797 __be16 logo_req_rcvd; 8798 __be16 prlo_req_rcvd; 8799 __be16 plogi_rjt_rcvd; 8800 __be16 prli_rjt_rcvd; 8801 __be32 adisc_req_rcvd; 8802 __be32 rscn_rcvd; 8803 __be32 rrq_req_rcvd; 8804 __be32 unsol_els_rcvd; 8805 __u8 adisc_rjt_rcvd; 8806 __u8 scr_rjt; 8807 __u8 ct_rjt; 8808 __u8 inval_bls_rcvd; 8809 __be32 ba_rjt_rcvd; 8810 } scb_stats; 8811 } u; 8812 }; 8813 8814 #define S_FW_FCOE_STATS_CMD_FLOWID 0 8815 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 8816 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 8817 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 8818 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 8819 8820 #define S_FW_FCOE_STATS_CMD_FREE 30 8821 #define M_FW_FCOE_STATS_CMD_FREE 0x1 8822 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 8823 #define G_FW_FCOE_STATS_CMD_FREE(x) \ 8824 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 8825 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 8826 8827 #define S_FW_FCOE_STATS_CMD_NSTATS 4 8828 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 8829 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 8830 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 8831 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 8832 8833 #define S_FW_FCOE_STATS_CMD_PORT 0 8834 #define M_FW_FCOE_STATS_CMD_PORT 0x3 8835 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 8836 #define G_FW_FCOE_STATS_CMD_PORT(x) \ 8837 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 8838 8839 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 8840 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 8841 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 8842 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 8843 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 8844 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 8845 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 8846 8847 #define S_FW_FCOE_STATS_CMD_IX 0 8848 #define M_FW_FCOE_STATS_CMD_IX 0x3f 8849 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 8850 #define G_FW_FCOE_STATS_CMD_IX(x) \ 8851 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 8852 8853 struct fw_fcoe_fcf_cmd { 8854 __be32 op_to_fcfi; 8855 __be32 retval_len16; 8856 __be16 priority_pkd; 8857 __u8 mac[6]; 8858 __u8 name_id[8]; 8859 __u8 fabric[8]; 8860 __be16 vf_id; 8861 __be16 max_fcoe_size; 8862 __u8 vlan_id; 8863 __u8 fc_map[3]; 8864 __be32 fka_adv; 8865 __be32 r6; 8866 __u8 r7_hi; 8867 __u8 fpma_to_portid; 8868 __u8 spma_mac[6]; 8869 __be64 r8; 8870 }; 8871 8872 #define S_FW_FCOE_FCF_CMD_FCFI 0 8873 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 8874 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 8875 #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 8876 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 8877 8878 #define S_FW_FCOE_FCF_CMD_PRIORITY 0 8879 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 8880 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 8881 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 8882 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 8883 8884 #define S_FW_FCOE_FCF_CMD_FPMA 6 8885 #define M_FW_FCOE_FCF_CMD_FPMA 0x1 8886 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 8887 #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 8888 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 8889 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 8890 8891 #define S_FW_FCOE_FCF_CMD_SPMA 5 8892 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 8893 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 8894 #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 8895 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 8896 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 8897 8898 #define S_FW_FCOE_FCF_CMD_LOGIN 4 8899 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 8900 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 8901 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 8902 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 8903 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 8904 8905 #define S_FW_FCOE_FCF_CMD_PORTID 0 8906 #define M_FW_FCOE_FCF_CMD_PORTID 0xf 8907 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 8908 #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 8909 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 8910 8911 /****************************************************************************** 8912 * E R R O R a n d D E B U G C O M M A N D s 8913 ******************************************************/ 8914 8915 enum fw_error_type { 8916 FW_ERROR_TYPE_EXCEPTION = 0x0, 8917 FW_ERROR_TYPE_HWMODULE = 0x1, 8918 FW_ERROR_TYPE_WR = 0x2, 8919 FW_ERROR_TYPE_ACL = 0x3, 8920 }; 8921 8922 enum fw_dcb_ieee_locations { 8923 FW_IEEE_LOC_LOCAL, 8924 FW_IEEE_LOC_PEER, 8925 FW_IEEE_LOC_OPERATIONAL, 8926 }; 8927 8928 struct fw_dcb_ieee_cmd { 8929 __be32 op_to_location; 8930 __be32 changed_to_len16; 8931 union fw_dcbx_stats { 8932 struct fw_dcbx_pfc_stats_ieee { 8933 __be32 pfc_mbc_pkd; 8934 __be32 pfc_willing_to_pfc_en; 8935 } dcbx_pfc_stats; 8936 struct fw_dcbx_ets_stats_ieee { 8937 __be32 cbs_to_ets_max_tc; 8938 __be32 pg_table; 8939 __u8 pg_percent[8]; 8940 __u8 tsa[8]; 8941 } dcbx_ets_stats; 8942 struct fw_dcbx_app_stats_ieee { 8943 __be32 num_apps_pkd; 8944 __be32 r6; 8945 __be32 app[4]; 8946 } dcbx_app_stats; 8947 struct fw_dcbx_control { 8948 __be32 multi_peer_invalidated; 8949 __be32 r5_lo; 8950 } dcbx_control; 8951 } u; 8952 }; 8953 8954 #define S_FW_DCB_IEEE_CMD_PORT 8 8955 #define M_FW_DCB_IEEE_CMD_PORT 0x7 8956 #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT) 8957 #define G_FW_DCB_IEEE_CMD_PORT(x) \ 8958 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT) 8959 8960 #define S_FW_DCB_IEEE_CMD_FEATURE 2 8961 #define M_FW_DCB_IEEE_CMD_FEATURE 0x7 8962 #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE) 8963 #define G_FW_DCB_IEEE_CMD_FEATURE(x) \ 8964 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE) 8965 8966 #define S_FW_DCB_IEEE_CMD_LOCATION 0 8967 #define M_FW_DCB_IEEE_CMD_LOCATION 0x3 8968 #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION) 8969 #define G_FW_DCB_IEEE_CMD_LOCATION(x) \ 8970 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION) 8971 8972 #define S_FW_DCB_IEEE_CMD_CHANGED 20 8973 #define M_FW_DCB_IEEE_CMD_CHANGED 0x1 8974 #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED) 8975 #define G_FW_DCB_IEEE_CMD_CHANGED(x) \ 8976 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED) 8977 #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U) 8978 8979 #define S_FW_DCB_IEEE_CMD_RECEIVED 19 8980 #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1 8981 #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED) 8982 #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \ 8983 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED) 8984 #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U) 8985 8986 #define S_FW_DCB_IEEE_CMD_APPLY 18 8987 #define M_FW_DCB_IEEE_CMD_APPLY 0x1 8988 #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY) 8989 #define G_FW_DCB_IEEE_CMD_APPLY(x) \ 8990 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY) 8991 #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U) 8992 8993 #define S_FW_DCB_IEEE_CMD_DISABLED 17 8994 #define M_FW_DCB_IEEE_CMD_DISABLED 0x1 8995 #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED) 8996 #define G_FW_DCB_IEEE_CMD_DISABLED(x) \ 8997 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED) 8998 #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U) 8999 9000 #define S_FW_DCB_IEEE_CMD_MORE 16 9001 #define M_FW_DCB_IEEE_CMD_MORE 0x1 9002 #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE) 9003 #define G_FW_DCB_IEEE_CMD_MORE(x) \ 9004 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE) 9005 #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U) 9006 9007 #define S_FW_DCB_IEEE_CMD_PFC_MBC 0 9008 #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1 9009 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC) 9010 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \ 9011 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC) 9012 #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U) 9013 9014 #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16 9015 #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1 9016 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 9017 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING) 9018 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 9019 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING) 9020 #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U) 9021 9022 #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8 9023 #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff 9024 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC) 9025 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \ 9026 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC) 9027 9028 #define S_FW_DCB_IEEE_CMD_PFC_EN 0 9029 #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff 9030 #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN) 9031 #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \ 9032 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN) 9033 9034 #define S_FW_DCB_IEEE_CMD_CBS 16 9035 #define M_FW_DCB_IEEE_CMD_CBS 0x1 9036 #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS) 9037 #define G_FW_DCB_IEEE_CMD_CBS(x) \ 9038 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS) 9039 #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U) 9040 9041 #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8 9042 #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1 9043 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 9044 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING) 9045 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 9046 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING) 9047 #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U) 9048 9049 #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0 9050 #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff 9051 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC) 9052 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \ 9053 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC) 9054 9055 #define S_FW_DCB_IEEE_CMD_NUM_APPS 0 9056 #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7 9057 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS) 9058 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \ 9059 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS) 9060 9061 #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31 9062 #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1 9063 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER) 9064 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \ 9065 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER) 9066 #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U) 9067 9068 #define S_FW_DCB_IEEE_CMD_INVALIDATED 30 9069 #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1 9070 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9071 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED) 9072 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9073 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED) 9074 #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U) 9075 9076 /* Hand-written */ 9077 #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16 9078 #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff 9079 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9080 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \ 9081 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9082 9083 #define S_FW_DCB_IEEE_CMD_APP_SELECT 3 9084 #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7 9085 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT) 9086 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \ 9087 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT) 9088 9089 #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0 9090 #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7 9091 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY) 9092 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \ 9093 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY) 9094 9095 9096 struct fw_error_cmd { 9097 __be32 op_to_type; 9098 __be32 len16_pkd; 9099 union fw_error { 9100 struct fw_error_exception { 9101 __be32 info[6]; 9102 } exception; 9103 struct fw_error_hwmodule { 9104 __be32 regaddr; 9105 __be32 regval; 9106 } hwmodule; 9107 struct fw_error_wr { 9108 __be16 cidx; 9109 __be16 pfn_vfn; 9110 __be32 eqid; 9111 __u8 wrhdr[16]; 9112 } wr; 9113 struct fw_error_acl { 9114 __be16 cidx; 9115 __be16 pfn_vfn; 9116 __be32 eqid; 9117 __be16 mv_pkd; 9118 __u8 val[6]; 9119 __be64 r4; 9120 } acl; 9121 } u; 9122 }; 9123 9124 #define S_FW_ERROR_CMD_FATAL 4 9125 #define M_FW_ERROR_CMD_FATAL 0x1 9126 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 9127 #define G_FW_ERROR_CMD_FATAL(x) \ 9128 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 9129 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 9130 9131 #define S_FW_ERROR_CMD_TYPE 0 9132 #define M_FW_ERROR_CMD_TYPE 0xf 9133 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 9134 #define G_FW_ERROR_CMD_TYPE(x) \ 9135 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 9136 9137 #define S_FW_ERROR_CMD_PFN 8 9138 #define M_FW_ERROR_CMD_PFN 0x7 9139 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9140 #define G_FW_ERROR_CMD_PFN(x) \ 9141 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9142 9143 #define S_FW_ERROR_CMD_VFN 0 9144 #define M_FW_ERROR_CMD_VFN 0xff 9145 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9146 #define G_FW_ERROR_CMD_VFN(x) \ 9147 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9148 9149 #define S_FW_ERROR_CMD_PFN 8 9150 #define M_FW_ERROR_CMD_PFN 0x7 9151 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9152 #define G_FW_ERROR_CMD_PFN(x) \ 9153 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9154 9155 #define S_FW_ERROR_CMD_VFN 0 9156 #define M_FW_ERROR_CMD_VFN 0xff 9157 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9158 #define G_FW_ERROR_CMD_VFN(x) \ 9159 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9160 9161 #define S_FW_ERROR_CMD_MV 15 9162 #define M_FW_ERROR_CMD_MV 0x1 9163 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 9164 #define G_FW_ERROR_CMD_MV(x) \ 9165 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 9166 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 9167 9168 struct fw_debug_cmd { 9169 __be32 op_type; 9170 __be32 len16_pkd; 9171 union fw_debug { 9172 struct fw_debug_assert { 9173 __be32 fcid; 9174 __be32 line; 9175 __be32 x; 9176 __be32 y; 9177 __u8 filename_0_7[8]; 9178 __u8 filename_8_15[8]; 9179 __be64 r3; 9180 } assert; 9181 struct fw_debug_prt { 9182 __be16 dprtstridx; 9183 __be16 r3[3]; 9184 __be32 dprtstrparam0; 9185 __be32 dprtstrparam1; 9186 __be32 dprtstrparam2; 9187 __be32 dprtstrparam3; 9188 } prt; 9189 } u; 9190 }; 9191 9192 #define S_FW_DEBUG_CMD_TYPE 0 9193 #define M_FW_DEBUG_CMD_TYPE 0xff 9194 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 9195 #define G_FW_DEBUG_CMD_TYPE(x) \ 9196 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 9197 9198 enum fw_diag_cmd_type { 9199 FW_DIAG_CMD_TYPE_OFLDIAG = 0, 9200 }; 9201 9202 enum fw_diag_cmd_ofldiag_op { 9203 FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0, 9204 FW_DIAG_CMD_OFLDIAG_TEST_START, 9205 FW_DIAG_CMD_OFLDIAG_TEST_STOP, 9206 FW_DIAG_CMD_OFLDIAG_TEST_STATUS, 9207 }; 9208 9209 enum fw_diag_cmd_ofldiag_status { 9210 FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0, 9211 FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING, 9212 FW_DIAG_CMD_OFLDIAG_STATUS_FAILED, 9213 FW_DIAG_CMD_OFLDIAG_STATUS_PASSED, 9214 }; 9215 9216 struct fw_diag_cmd { 9217 __be32 op_type; 9218 __be32 len16_pkd; 9219 union fw_diag_test { 9220 struct fw_diag_test_ofldiag { 9221 __u8 test_op; 9222 __u8 r3; 9223 __be16 test_status; 9224 __be32 duration; 9225 } ofldiag; 9226 } u; 9227 }; 9228 9229 #define S_FW_DIAG_CMD_TYPE 0 9230 #define M_FW_DIAG_CMD_TYPE 0xff 9231 #define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE) 9232 #define G_FW_DIAG_CMD_TYPE(x) \ 9233 (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE) 9234 9235 /****************************************************************************** 9236 * P C I E F W R E G I S T E R 9237 **************************************/ 9238 9239 enum pcie_fw_eval { 9240 PCIE_FW_EVAL_CRASH = 0, 9241 PCIE_FW_EVAL_PREP = 1, 9242 PCIE_FW_EVAL_CONF = 2, 9243 PCIE_FW_EVAL_INIT = 3, 9244 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 9245 PCIE_FW_EVAL_OVERHEAT = 5, 9246 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 9247 }; 9248 9249 /** 9250 * Register definitions for the PCIE_FW register which the firmware uses 9251 * to retain status across RESETs. This register should be considered 9252 * as a READ-ONLY register for Host Software and only to be used to 9253 * track firmware initialization/error state, etc. 9254 */ 9255 #define S_PCIE_FW_ERR 31 9256 #define M_PCIE_FW_ERR 0x1 9257 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 9258 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 9259 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 9260 9261 #define S_PCIE_FW_INIT 30 9262 #define M_PCIE_FW_INIT 0x1 9263 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 9264 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 9265 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 9266 9267 #define S_PCIE_FW_HALT 29 9268 #define M_PCIE_FW_HALT 0x1 9269 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 9270 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 9271 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 9272 9273 #define S_PCIE_FW_EVAL 24 9274 #define M_PCIE_FW_EVAL 0x7 9275 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 9276 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 9277 9278 #define S_PCIE_FW_STAGE 21 9279 #define M_PCIE_FW_STAGE 0x7 9280 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 9281 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 9282 9283 #define S_PCIE_FW_ASYNCNOT_VLD 20 9284 #define M_PCIE_FW_ASYNCNOT_VLD 0x1 9285 #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 9286 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 9287 #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 9288 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 9289 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 9290 9291 #define S_PCIE_FW_ASYNCNOTINT 19 9292 #define M_PCIE_FW_ASYNCNOTINT 0x1 9293 #define V_PCIE_FW_ASYNCNOTINT(x) \ 9294 ((x) << S_PCIE_FW_ASYNCNOTINT) 9295 #define G_PCIE_FW_ASYNCNOTINT(x) \ 9296 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 9297 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 9298 9299 #define S_PCIE_FW_ASYNCNOT 16 9300 #define M_PCIE_FW_ASYNCNOT 0x7 9301 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 9302 #define G_PCIE_FW_ASYNCNOT(x) \ 9303 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 9304 9305 #define S_PCIE_FW_MASTER_VLD 15 9306 #define M_PCIE_FW_MASTER_VLD 0x1 9307 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 9308 #define G_PCIE_FW_MASTER_VLD(x) \ 9309 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 9310 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 9311 9312 #define S_PCIE_FW_MASTER 12 9313 #define M_PCIE_FW_MASTER 0x7 9314 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 9315 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 9316 9317 #define S_PCIE_FW_RESET_VLD 11 9318 #define M_PCIE_FW_RESET_VLD 0x1 9319 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 9320 #define G_PCIE_FW_RESET_VLD(x) \ 9321 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 9322 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 9323 9324 #define S_PCIE_FW_RESET 8 9325 #define M_PCIE_FW_RESET 0x7 9326 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 9327 #define G_PCIE_FW_RESET(x) \ 9328 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 9329 9330 #define S_PCIE_FW_REGISTERED 0 9331 #define M_PCIE_FW_REGISTERED 0xff 9332 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 9333 #define G_PCIE_FW_REGISTERED(x) \ 9334 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 9335 9336 9337 /****************************************************************************** 9338 * P C I E F W P F 0 R E G I S T E R 9339 **********************************************/ 9340 9341 /* 9342 * this register is available as 32-bit of persistent storage (across 9343 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 9344 * will not write it) 9345 */ 9346 9347 9348 /****************************************************************************** 9349 * P C I E F W P F 7 R E G I S T E R 9350 **********************************************/ 9351 9352 /* 9353 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to 9354 * access the "devlog" which needing to contact firmware. The encoding is 9355 * mostly the same as that returned by the DEVLOG command except for the size 9356 * which is encoded as the number of entries in multiples-1 of 128 here rather 9357 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 9358 * and 15 means 2048. This of course in turn constrains the allowed values 9359 * for the devlog size ... 9360 */ 9361 #define PCIE_FW_PF_DEVLOG 7 9362 9363 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 9364 #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf 9365 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9366 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) 9367 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9368 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ 9369 M_PCIE_FW_PF_DEVLOG_NENTRIES128) 9370 9371 #define S_PCIE_FW_PF_DEVLOG_ADDR16 4 9372 #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff 9373 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) 9374 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ 9375 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) 9376 9377 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 9378 #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf 9379 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) 9380 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ 9381 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) 9382 9383 9384 /****************************************************************************** 9385 * B I N A R Y H E A D E R F O R M A T 9386 **********************************************/ 9387 9388 /* 9389 * firmware binary header format 9390 */ 9391 struct fw_hdr { 9392 __u8 ver; 9393 __u8 chip; /* terminator chip family */ 9394 __be16 len512; /* bin length in units of 512-bytes */ 9395 __be32 fw_ver; /* firmware version */ 9396 __be32 tp_microcode_ver; /* tcp processor microcode version */ 9397 __u8 intfver_nic; 9398 __u8 intfver_vnic; 9399 __u8 intfver_ofld; 9400 __u8 intfver_ri; 9401 __u8 intfver_iscsipdu; 9402 __u8 intfver_iscsi; 9403 __u8 intfver_fcoepdu; 9404 __u8 intfver_fcoe; 9405 __u32 reserved2; 9406 __u32 reserved3; 9407 __be32 magic; /* runtime or bootstrap fw */ 9408 __be32 flags; 9409 __be32 reserved6[23]; 9410 }; 9411 9412 enum fw_hdr_chip { 9413 FW_HDR_CHIP_T4, 9414 FW_HDR_CHIP_T5, 9415 FW_HDR_CHIP_T6 9416 }; 9417 9418 #define S_FW_HDR_FW_VER_MAJOR 24 9419 #define M_FW_HDR_FW_VER_MAJOR 0xff 9420 #define V_FW_HDR_FW_VER_MAJOR(x) \ 9421 ((x) << S_FW_HDR_FW_VER_MAJOR) 9422 #define G_FW_HDR_FW_VER_MAJOR(x) \ 9423 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 9424 9425 #define S_FW_HDR_FW_VER_MINOR 16 9426 #define M_FW_HDR_FW_VER_MINOR 0xff 9427 #define V_FW_HDR_FW_VER_MINOR(x) \ 9428 ((x) << S_FW_HDR_FW_VER_MINOR) 9429 #define G_FW_HDR_FW_VER_MINOR(x) \ 9430 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 9431 9432 #define S_FW_HDR_FW_VER_MICRO 8 9433 #define M_FW_HDR_FW_VER_MICRO 0xff 9434 #define V_FW_HDR_FW_VER_MICRO(x) \ 9435 ((x) << S_FW_HDR_FW_VER_MICRO) 9436 #define G_FW_HDR_FW_VER_MICRO(x) \ 9437 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 9438 9439 #define S_FW_HDR_FW_VER_BUILD 0 9440 #define M_FW_HDR_FW_VER_BUILD 0xff 9441 #define V_FW_HDR_FW_VER_BUILD(x) \ 9442 ((x) << S_FW_HDR_FW_VER_BUILD) 9443 #define G_FW_HDR_FW_VER_BUILD(x) \ 9444 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 9445 9446 enum { 9447 T4FW_VERSION_MAJOR = 0x01, 9448 T4FW_VERSION_MINOR = 0x10, 9449 T4FW_VERSION_MICRO = 0x2d, 9450 T4FW_VERSION_BUILD = 0x00, 9451 9452 T5FW_VERSION_MAJOR = 0x01, 9453 T5FW_VERSION_MINOR = 0x10, 9454 T5FW_VERSION_MICRO = 0x2d, 9455 T5FW_VERSION_BUILD = 0x00, 9456 9457 T6FW_VERSION_MAJOR = 0x01, 9458 T6FW_VERSION_MINOR = 0x10, 9459 T6FW_VERSION_MICRO = 0x2d, 9460 T6FW_VERSION_BUILD = 0x00, 9461 }; 9462 9463 enum { 9464 /* T4 9465 */ 9466 T4FW_HDR_INTFVER_NIC = 0x00, 9467 T4FW_HDR_INTFVER_VNIC = 0x00, 9468 T4FW_HDR_INTFVER_OFLD = 0x00, 9469 T4FW_HDR_INTFVER_RI = 0x00, 9470 T4FW_HDR_INTFVER_ISCSIPDU= 0x00, 9471 T4FW_HDR_INTFVER_ISCSI = 0x00, 9472 T4FW_HDR_INTFVER_FCOEPDU = 0x00, 9473 T4FW_HDR_INTFVER_FCOE = 0x00, 9474 9475 /* T5 9476 */ 9477 T5FW_HDR_INTFVER_NIC = 0x00, 9478 T5FW_HDR_INTFVER_VNIC = 0x00, 9479 T5FW_HDR_INTFVER_OFLD = 0x00, 9480 T5FW_HDR_INTFVER_RI = 0x00, 9481 T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 9482 T5FW_HDR_INTFVER_ISCSI = 0x00, 9483 T5FW_HDR_INTFVER_FCOEPDU= 0x00, 9484 T5FW_HDR_INTFVER_FCOE = 0x00, 9485 9486 /* T6 9487 */ 9488 T6FW_HDR_INTFVER_NIC = 0x00, 9489 T6FW_HDR_INTFVER_VNIC = 0x00, 9490 T6FW_HDR_INTFVER_OFLD = 0x00, 9491 T6FW_HDR_INTFVER_RI = 0x00, 9492 T6FW_HDR_INTFVER_ISCSIPDU= 0x00, 9493 T6FW_HDR_INTFVER_ISCSI = 0x00, 9494 T6FW_HDR_INTFVER_FCOEPDU= 0x00, 9495 T6FW_HDR_INTFVER_FCOE = 0x00, 9496 }; 9497 9498 enum { 9499 FW_HDR_MAGIC_RUNTIME = 0x00000000, 9500 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 9501 }; 9502 9503 enum fw_hdr_flags { 9504 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 9505 }; 9506 9507 /* 9508 * External PHY firmware binary header format 9509 */ 9510 struct fw_ephy_hdr { 9511 __u8 ver; 9512 __u8 reserved; 9513 __be16 len512; /* bin length in units of 512-bytes */ 9514 __be32 magic; 9515 9516 __be16 vendor_id; 9517 __be16 device_id; 9518 __be32 version; 9519 9520 __be32 reserved1[4]; 9521 }; 9522 9523 enum { 9524 FW_EPHY_HDR_MAGIC = 0x65706879, 9525 }; 9526 9527 #endif /* _T4FW_INTERFACE_H_ */ 9528