1 /*- 2 * Copyright (c) 2012 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _T4FW_INTERFACE_H_ 31 #define _T4FW_INTERFACE_H_ 32 33 /****************************************************************************** 34 * R E T U R N V A L U E S 35 ********************************/ 36 37 enum fw_retval { 38 FW_SUCCESS = 0, /* completed sucessfully */ 39 FW_EPERM = 1, /* operation not permitted */ 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ 48 FW_ENODEV = 19, /* no such device */ 49 FW_EINVAL = 22, /* invalid argument */ 50 FW_ENOSPC = 28, /* no space left on device */ 51 FW_ENOSYS = 38, /* functionality not implemented */ 52 FW_ENODATA = 61, /* no data available */ 53 FW_EPROTO = 71, /* protocol error */ 54 FW_EADDRINUSE = 98, /* address already in use */ 55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 56 FW_ENETDOWN = 100, /* network is down */ 57 FW_ENETUNREACH = 101, /* network is unreachable */ 58 FW_ENOBUFS = 105, /* no buffer space available */ 59 FW_ETIMEDOUT = 110, /* timeout */ 60 FW_EINPROGRESS = 115, /* fw internal */ 61 FW_SCSI_ABORT_REQUESTED = 128, /* */ 62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 63 FW_SCSI_ABORTED = 130, /* */ 64 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 65 FW_ERR_LINK_DOWN = 132, /* */ 66 FW_RDEV_NOT_READY = 133, /* */ 67 FW_ERR_RDEV_LOST = 134, /* */ 68 FW_ERR_RDEV_LOGO = 135, /* */ 69 FW_FCOE_NO_XCHG = 136, /* */ 70 FW_SCSI_RSP_ERR = 137, /* */ 71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 73 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 74 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 76 }; 77 78 /****************************************************************************** 79 * W O R K R E Q U E S T s 80 ********************************/ 81 82 enum fw_wr_opcodes { 83 FW_FRAG_WR = 0x1d, 84 FW_FILTER_WR = 0x02, 85 FW_ULPTX_WR = 0x04, 86 FW_TP_WR = 0x05, 87 FW_ETH_TX_PKT_WR = 0x08, 88 FW_ETH_TX_PKTS_WR = 0x09, 89 FW_ETH_TX_UO_WR = 0x1c, 90 FW_EQ_FLUSH_WR = 0x1b, 91 FW_OFLD_CONNECTION_WR = 0x2f, 92 FW_FLOWC_WR = 0x0a, 93 FW_OFLD_TX_DATA_WR = 0x0b, 94 FW_CMD_WR = 0x10, 95 FW_ETH_TX_PKT_VM_WR = 0x11, 96 FW_RI_RES_WR = 0x0c, 97 FW_RI_RDMA_WRITE_WR = 0x14, 98 FW_RI_SEND_WR = 0x15, 99 FW_RI_RDMA_READ_WR = 0x16, 100 FW_RI_RECV_WR = 0x17, 101 FW_RI_BIND_MW_WR = 0x18, 102 FW_RI_FR_NSMR_WR = 0x19, 103 FW_RI_INV_LSTAG_WR = 0x1a, 104 FW_RI_SEND_IMMEDIATE_WR = 0x15, 105 FW_RI_ATOMIC_WR = 0x16, 106 FW_RI_WR = 0x0d, 107 FW_CHNET_IFCONF_WR = 0x6b, 108 FW_RDEV_WR = 0x38, 109 FW_FOISCSI_NODE_WR = 0x60, 110 FW_FOISCSI_CTRL_WR = 0x6a, 111 FW_FOISCSI_CHAP_WR = 0x6c, 112 FW_FCOE_ELS_CT_WR = 0x30, 113 FW_SCSI_WRITE_WR = 0x31, 114 FW_SCSI_READ_WR = 0x32, 115 FW_SCSI_CMD_WR = 0x33, 116 FW_SCSI_ABRT_CLS_WR = 0x34, 117 FW_SCSI_TGT_ACC_WR = 0x35, 118 FW_SCSI_TGT_XMIT_WR = 0x36, 119 FW_SCSI_TGT_RSP_WR = 0x37, 120 FW_POFCOE_TCB_WR = 0x42, 121 FW_POFCOE_ULPTX_WR = 0x43, 122 FW_LASTC2E_WR = 0x70 123 }; 124 125 /* 126 * Generic work request header flit0 127 */ 128 struct fw_wr_hdr { 129 __be32 hi; 130 __be32 lo; 131 }; 132 133 /* work request opcode (hi) 134 */ 135 #define S_FW_WR_OP 24 136 #define M_FW_WR_OP 0xff 137 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 138 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 139 140 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 141 */ 142 #define S_FW_WR_ATOMIC 23 143 #define M_FW_WR_ATOMIC 0x1 144 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 145 #define G_FW_WR_ATOMIC(x) \ 146 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 147 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 148 149 /* flush flag (hi) - firmware flushes flushable work request buffered 150 * in the flow context. 151 */ 152 #define S_FW_WR_FLUSH 22 153 #define M_FW_WR_FLUSH 0x1 154 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 155 #define G_FW_WR_FLUSH(x) \ 156 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 157 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 158 159 /* completion flag (hi) - firmware generates a cpl_fw6_ack 160 */ 161 #define S_FW_WR_COMPL 21 162 #define M_FW_WR_COMPL 0x1 163 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 164 #define G_FW_WR_COMPL(x) \ 165 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 166 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 167 168 169 /* work request immediate data lengh (hi) 170 */ 171 #define S_FW_WR_IMMDLEN 0 172 #define M_FW_WR_IMMDLEN 0xff 173 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 174 #define G_FW_WR_IMMDLEN(x) \ 175 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 176 177 /* egress queue status update to associated ingress queue entry (lo) 178 */ 179 #define S_FW_WR_EQUIQ 31 180 #define M_FW_WR_EQUIQ 0x1 181 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 182 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 183 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 184 185 /* egress queue status update to egress queue status entry (lo) 186 */ 187 #define S_FW_WR_EQUEQ 30 188 #define M_FW_WR_EQUEQ 0x1 189 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 190 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 191 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 192 193 /* flow context identifier (lo) 194 */ 195 #define S_FW_WR_FLOWID 8 196 #define M_FW_WR_FLOWID 0xfffff 197 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 198 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 199 200 /* length in units of 16-bytes (lo) 201 */ 202 #define S_FW_WR_LEN16 0 203 #define M_FW_WR_LEN16 0xff 204 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 205 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 206 207 struct fw_frag_wr { 208 __be32 op_to_fragoff16; 209 __be32 flowid_len16; 210 __be64 r4; 211 }; 212 213 #define S_FW_FRAG_WR_EOF 15 214 #define M_FW_FRAG_WR_EOF 0x1 215 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 216 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 217 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 218 219 #define S_FW_FRAG_WR_FRAGOFF16 8 220 #define M_FW_FRAG_WR_FRAGOFF16 0x7f 221 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 222 #define G_FW_FRAG_WR_FRAGOFF16(x) \ 223 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 224 225 /* valid filter configurations for compressed tuple 226 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 227 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 228 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 229 * OV - Outer VLAN/VNIC_ID, 230 */ 231 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 232 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 233 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 234 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 235 #define HW_TPL_FR_MT_E_PR_T 0x370 236 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 237 #define HW_TPL_FR_MT_E_T_P_FC 0X353 238 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 239 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 240 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 241 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 242 #define HW_TPL_FR_M_E_PR_FC 0X2E1 243 #define HW_TPL_FR_M_E_T_FC 0X2D1 244 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 245 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 246 #define HW_TPL_FR_M_T_IV_FC 0X299 247 #define HW_TPL_FR_M_T_OV_FC 0X295 248 #define HW_TPL_FR_E_PR_T_P 0X272 249 #define HW_TPL_FR_E_PR_T_FC 0X271 250 #define HW_TPL_FR_E_IV_FC 0X249 251 #define HW_TPL_FR_E_OV_FC 0X245 252 #define HW_TPL_FR_PR_T_IV_FC 0X239 253 #define HW_TPL_FR_PR_T_OV_FC 0X235 254 #define HW_TPL_FR_IV_OV_FC 0X20D 255 #define HW_TPL_MT_M_E_PR 0X1E0 256 #define HW_TPL_MT_M_E_T 0X1D0 257 #define HW_TPL_MT_E_PR_T_FC 0X171 258 #define HW_TPL_MT_E_IV 0X148 259 #define HW_TPL_MT_E_OV 0X144 260 #define HW_TPL_MT_PR_T_IV 0X138 261 #define HW_TPL_MT_PR_T_OV 0X134 262 #define HW_TPL_M_E_PR_P 0X0E2 263 #define HW_TPL_M_E_T_P 0X0D2 264 #define HW_TPL_E_PR_T_P_FC 0X073 265 #define HW_TPL_E_IV_P 0X04A 266 #define HW_TPL_E_OV_P 0X046 267 #define HW_TPL_PR_T_IV_P 0X03A 268 #define HW_TPL_PR_T_OV_P 0X036 269 270 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 271 enum fw_filter_wr_cookie { 272 FW_FILTER_WR_SUCCESS, 273 FW_FILTER_WR_FLT_ADDED, 274 FW_FILTER_WR_FLT_DELETED, 275 FW_FILTER_WR_SMT_TBL_FULL, 276 FW_FILTER_WR_EINVAL, 277 }; 278 279 struct fw_filter_wr { 280 __be32 op_pkd; 281 __be32 len16_pkd; 282 __be64 r3; 283 __be32 tid_to_iq; 284 __be32 del_filter_to_l2tix; 285 __be16 ethtype; 286 __be16 ethtypem; 287 __u8 frag_to_ovlan_vldm; 288 __u8 smac_sel; 289 __be16 rx_chan_rx_rpl_iq; 290 __be32 maci_to_matchtypem; 291 __u8 ptcl; 292 __u8 ptclm; 293 __u8 ttyp; 294 __u8 ttypm; 295 __be16 ivlan; 296 __be16 ivlanm; 297 __be16 ovlan; 298 __be16 ovlanm; 299 __u8 lip[16]; 300 __u8 lipm[16]; 301 __u8 fip[16]; 302 __u8 fipm[16]; 303 __be16 lp; 304 __be16 lpm; 305 __be16 fp; 306 __be16 fpm; 307 __be16 r7; 308 __u8 sma[6]; 309 }; 310 311 #define S_FW_FILTER_WR_TID 12 312 #define M_FW_FILTER_WR_TID 0xfffff 313 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 314 #define G_FW_FILTER_WR_TID(x) \ 315 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 316 317 #define S_FW_FILTER_WR_RQTYPE 11 318 #define M_FW_FILTER_WR_RQTYPE 0x1 319 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 320 #define G_FW_FILTER_WR_RQTYPE(x) \ 321 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 322 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 323 324 #define S_FW_FILTER_WR_NOREPLY 10 325 #define M_FW_FILTER_WR_NOREPLY 0x1 326 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 327 #define G_FW_FILTER_WR_NOREPLY(x) \ 328 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 329 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 330 331 #define S_FW_FILTER_WR_IQ 0 332 #define M_FW_FILTER_WR_IQ 0x3ff 333 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 334 #define G_FW_FILTER_WR_IQ(x) \ 335 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 336 337 #define S_FW_FILTER_WR_DEL_FILTER 31 338 #define M_FW_FILTER_WR_DEL_FILTER 0x1 339 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 340 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 341 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 342 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 343 344 #define S_FW_FILTER_WR_RPTTID 25 345 #define M_FW_FILTER_WR_RPTTID 0x1 346 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 347 #define G_FW_FILTER_WR_RPTTID(x) \ 348 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 349 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 350 351 #define S_FW_FILTER_WR_DROP 24 352 #define M_FW_FILTER_WR_DROP 0x1 353 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 354 #define G_FW_FILTER_WR_DROP(x) \ 355 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 356 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 357 358 #define S_FW_FILTER_WR_DIRSTEER 23 359 #define M_FW_FILTER_WR_DIRSTEER 0x1 360 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 361 #define G_FW_FILTER_WR_DIRSTEER(x) \ 362 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 363 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 364 365 #define S_FW_FILTER_WR_MASKHASH 22 366 #define M_FW_FILTER_WR_MASKHASH 0x1 367 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 368 #define G_FW_FILTER_WR_MASKHASH(x) \ 369 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 370 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 371 372 #define S_FW_FILTER_WR_DIRSTEERHASH 21 373 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 374 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 375 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 376 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 377 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 378 379 #define S_FW_FILTER_WR_LPBK 20 380 #define M_FW_FILTER_WR_LPBK 0x1 381 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 382 #define G_FW_FILTER_WR_LPBK(x) \ 383 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 384 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 385 386 #define S_FW_FILTER_WR_DMAC 19 387 #define M_FW_FILTER_WR_DMAC 0x1 388 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 389 #define G_FW_FILTER_WR_DMAC(x) \ 390 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 391 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 392 393 #define S_FW_FILTER_WR_SMAC 18 394 #define M_FW_FILTER_WR_SMAC 0x1 395 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 396 #define G_FW_FILTER_WR_SMAC(x) \ 397 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 398 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 399 400 #define S_FW_FILTER_WR_INSVLAN 17 401 #define M_FW_FILTER_WR_INSVLAN 0x1 402 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 403 #define G_FW_FILTER_WR_INSVLAN(x) \ 404 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 405 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 406 407 #define S_FW_FILTER_WR_RMVLAN 16 408 #define M_FW_FILTER_WR_RMVLAN 0x1 409 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 410 #define G_FW_FILTER_WR_RMVLAN(x) \ 411 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 412 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 413 414 #define S_FW_FILTER_WR_HITCNTS 15 415 #define M_FW_FILTER_WR_HITCNTS 0x1 416 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 417 #define G_FW_FILTER_WR_HITCNTS(x) \ 418 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 419 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 420 421 #define S_FW_FILTER_WR_TXCHAN 13 422 #define M_FW_FILTER_WR_TXCHAN 0x3 423 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 424 #define G_FW_FILTER_WR_TXCHAN(x) \ 425 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 426 427 #define S_FW_FILTER_WR_PRIO 12 428 #define M_FW_FILTER_WR_PRIO 0x1 429 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 430 #define G_FW_FILTER_WR_PRIO(x) \ 431 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 432 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 433 434 #define S_FW_FILTER_WR_L2TIX 0 435 #define M_FW_FILTER_WR_L2TIX 0xfff 436 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 437 #define G_FW_FILTER_WR_L2TIX(x) \ 438 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 439 440 #define S_FW_FILTER_WR_FRAG 7 441 #define M_FW_FILTER_WR_FRAG 0x1 442 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 443 #define G_FW_FILTER_WR_FRAG(x) \ 444 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 445 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 446 447 #define S_FW_FILTER_WR_FRAGM 6 448 #define M_FW_FILTER_WR_FRAGM 0x1 449 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 450 #define G_FW_FILTER_WR_FRAGM(x) \ 451 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 452 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 453 454 #define S_FW_FILTER_WR_IVLAN_VLD 5 455 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 456 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 457 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 458 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 459 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 460 461 #define S_FW_FILTER_WR_OVLAN_VLD 4 462 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 463 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 464 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 465 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 466 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 467 468 #define S_FW_FILTER_WR_IVLAN_VLDM 3 469 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 470 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 471 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 472 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 473 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 474 475 #define S_FW_FILTER_WR_OVLAN_VLDM 2 476 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 477 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 478 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 479 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 480 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 481 482 #define S_FW_FILTER_WR_RX_CHAN 15 483 #define M_FW_FILTER_WR_RX_CHAN 0x1 484 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 485 #define G_FW_FILTER_WR_RX_CHAN(x) \ 486 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 487 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 488 489 #define S_FW_FILTER_WR_RX_RPL_IQ 0 490 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 491 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 492 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 493 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 494 495 #define S_FW_FILTER_WR_MACI 23 496 #define M_FW_FILTER_WR_MACI 0x1ff 497 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 498 #define G_FW_FILTER_WR_MACI(x) \ 499 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 500 501 #define S_FW_FILTER_WR_MACIM 14 502 #define M_FW_FILTER_WR_MACIM 0x1ff 503 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 504 #define G_FW_FILTER_WR_MACIM(x) \ 505 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 506 507 #define S_FW_FILTER_WR_FCOE 13 508 #define M_FW_FILTER_WR_FCOE 0x1 509 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 510 #define G_FW_FILTER_WR_FCOE(x) \ 511 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 512 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 513 514 #define S_FW_FILTER_WR_FCOEM 12 515 #define M_FW_FILTER_WR_FCOEM 0x1 516 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 517 #define G_FW_FILTER_WR_FCOEM(x) \ 518 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 519 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 520 521 #define S_FW_FILTER_WR_PORT 9 522 #define M_FW_FILTER_WR_PORT 0x7 523 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 524 #define G_FW_FILTER_WR_PORT(x) \ 525 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 526 527 #define S_FW_FILTER_WR_PORTM 6 528 #define M_FW_FILTER_WR_PORTM 0x7 529 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 530 #define G_FW_FILTER_WR_PORTM(x) \ 531 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 532 533 #define S_FW_FILTER_WR_MATCHTYPE 3 534 #define M_FW_FILTER_WR_MATCHTYPE 0x7 535 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 536 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 537 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 538 539 #define S_FW_FILTER_WR_MATCHTYPEM 0 540 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 541 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 542 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 543 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 544 545 struct fw_ulptx_wr { 546 __be32 op_to_compl; 547 __be32 flowid_len16; 548 __u64 cookie; 549 }; 550 551 struct fw_tp_wr { 552 __be32 op_to_immdlen; 553 __be32 flowid_len16; 554 __u64 cookie; 555 }; 556 557 struct fw_eth_tx_pkt_wr { 558 __be32 op_immdlen; 559 __be32 equiq_to_len16; 560 __be64 r3; 561 }; 562 563 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 564 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 565 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 566 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 567 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 568 569 struct fw_eth_tx_pkts_wr { 570 __be32 op_pkd; 571 __be32 equiq_to_len16; 572 __be32 r3; 573 __be16 plen; 574 __u8 npkt; 575 __u8 type; 576 }; 577 578 struct fw_eth_tx_uo_wr { 579 __be32 op_immdlen; 580 __be32 equiq_to_len16; 581 __be64 r3; 582 __u8 r4; 583 __u8 ethlen; 584 __be16 iplen; 585 __u8 udplen; 586 __u8 rtplen; 587 __be16 r5; 588 __be16 mss; 589 __be16 schedpktsize; 590 __be32 length; 591 }; 592 593 struct fw_eq_flush_wr { 594 __u8 opcode; 595 __u8 r1[3]; 596 __be32 equiq_to_len16; 597 __be64 r3; 598 }; 599 600 struct fw_ofld_connection_wr { 601 __be32 op_compl; 602 __be32 len16_pkd; 603 __u64 cookie; 604 __be64 r2; 605 __be64 r3; 606 struct fw_ofld_connection_le { 607 __be32 version_cpl; 608 __be32 filter; 609 __be32 r1; 610 __be16 lport; 611 __be16 pport; 612 union fw_ofld_connection_leip { 613 struct fw_ofld_connection_le_ipv4 { 614 __be32 pip; 615 __be32 lip; 616 __be64 r0; 617 __be64 r1; 618 __be64 r2; 619 } ipv4; 620 struct fw_ofld_connection_le_ipv6 { 621 __be64 pip_hi; 622 __be64 pip_lo; 623 __be64 lip_hi; 624 __be64 lip_lo; 625 } ipv6; 626 } u; 627 } le; 628 struct fw_ofld_connection_tcb { 629 __be32 t_state_to_astid; 630 __be16 cplrxdataack_cplpassacceptrpl; 631 __be16 rcv_adv; 632 __be32 rcv_nxt; 633 __be32 tx_max; 634 __be64 opt0; 635 __be32 opt2; 636 __be32 r1; 637 __be64 r2; 638 __be64 r3; 639 } tcb; 640 }; 641 642 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 643 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 644 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 645 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 646 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 647 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 648 M_FW_OFLD_CONNECTION_WR_VERSION) 649 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 650 651 #define S_FW_OFLD_CONNECTION_WR_CPL 30 652 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 653 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 654 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 655 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 656 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 657 658 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 659 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 660 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 661 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 662 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 663 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 664 M_FW_OFLD_CONNECTION_WR_T_STATE) 665 666 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 667 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 668 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 669 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 670 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 671 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 672 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 673 674 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 675 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 676 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 677 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 678 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 679 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 680 681 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 682 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 683 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 684 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 685 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 686 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 687 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 688 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 689 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 690 691 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 692 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 693 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 694 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 695 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 696 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 697 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 698 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 699 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 700 701 enum fw_flowc_mnem_tcpstate { 702 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 703 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 704 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 705 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 706 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 707 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 708 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 709 * will resend FIN - equiv ESTAB 710 */ 711 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 712 * will resend FIN but have 713 * received FIN 714 */ 715 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 716 * will resend FIN but have 717 * received FIN 718 */ 719 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 720 * waiting for FIN 721 */ 722 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 723 }; 724 725 enum fw_flowc_mnem_uostate { 726 FW_FLOWC_MNEM_UOSTATE_CLOSED = 0, /* illegal */ 727 FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1, /* default */ 728 FW_FLOWC_MNEM_UOSTATE_CLOSING = 2, /* graceful close, after sending 729 * outstanding payload 730 */ 731 FW_FLOWC_MNEM_UOSTATE_ABORTING = 3, /* immediate close, after 732 * discarding outstanding payload 733 */ 734 }; 735 736 enum fw_flowc_mnem { 737 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 738 FW_FLOWC_MNEM_CH = 1, 739 FW_FLOWC_MNEM_PORT = 2, 740 FW_FLOWC_MNEM_IQID = 3, 741 FW_FLOWC_MNEM_SNDNXT = 4, 742 FW_FLOWC_MNEM_RCVNXT = 5, 743 FW_FLOWC_MNEM_SNDBUF = 6, 744 FW_FLOWC_MNEM_MSS = 7, 745 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 746 FW_FLOWC_MNEM_TCPSTATE = 9, 747 FW_FLOWC_MNEM_UOSTATE = 10, 748 FW_FLOWC_MNEM_SCHEDCLASS = 11, 749 FW_FLOWC_MNEM_DCBPRIO = 12, 750 }; 751 752 struct fw_flowc_mnemval { 753 __u8 mnemonic; 754 __u8 r4[3]; 755 __be32 val; 756 }; 757 758 struct fw_flowc_wr { 759 __be32 op_to_nparams; 760 __be32 flowid_len16; 761 #ifndef C99_NOT_SUPPORTED 762 struct fw_flowc_mnemval mnemval[0]; 763 #endif 764 }; 765 766 #define S_FW_FLOWC_WR_NPARAMS 0 767 #define M_FW_FLOWC_WR_NPARAMS 0xff 768 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 769 #define G_FW_FLOWC_WR_NPARAMS(x) \ 770 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 771 772 struct fw_ofld_tx_data_wr { 773 __be32 op_to_immdlen; 774 __be32 flowid_len16; 775 __be32 plen; 776 __be32 tunnel_to_proxy; 777 }; 778 779 #define S_FW_OFLD_TX_DATA_WR_TUNNEL 19 780 #define M_FW_OFLD_TX_DATA_WR_TUNNEL 0x1 781 #define V_FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL) 782 #define G_FW_OFLD_TX_DATA_WR_TUNNEL(x) \ 783 (((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL) 784 #define F_FW_OFLD_TX_DATA_WR_TUNNEL V_FW_OFLD_TX_DATA_WR_TUNNEL(1U) 785 786 #define S_FW_OFLD_TX_DATA_WR_SAVE 18 787 #define M_FW_OFLD_TX_DATA_WR_SAVE 0x1 788 #define V_FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SAVE) 789 #define G_FW_OFLD_TX_DATA_WR_SAVE(x) \ 790 (((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE) 791 #define F_FW_OFLD_TX_DATA_WR_SAVE V_FW_OFLD_TX_DATA_WR_SAVE(1U) 792 793 #define S_FW_OFLD_TX_DATA_WR_FLUSH 17 794 #define M_FW_OFLD_TX_DATA_WR_FLUSH 0x1 795 #define V_FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLUSH) 796 #define G_FW_OFLD_TX_DATA_WR_FLUSH(x) \ 797 (((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH) 798 #define F_FW_OFLD_TX_DATA_WR_FLUSH V_FW_OFLD_TX_DATA_WR_FLUSH(1U) 799 800 #define S_FW_OFLD_TX_DATA_WR_URGENT 16 801 #define M_FW_OFLD_TX_DATA_WR_URGENT 0x1 802 #define V_FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << S_FW_OFLD_TX_DATA_WR_URGENT) 803 #define G_FW_OFLD_TX_DATA_WR_URGENT(x) \ 804 (((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT) 805 #define F_FW_OFLD_TX_DATA_WR_URGENT V_FW_OFLD_TX_DATA_WR_URGENT(1U) 806 807 #define S_FW_OFLD_TX_DATA_WR_MORE 15 808 #define M_FW_OFLD_TX_DATA_WR_MORE 0x1 809 #define V_FW_OFLD_TX_DATA_WR_MORE(x) ((x) << S_FW_OFLD_TX_DATA_WR_MORE) 810 #define G_FW_OFLD_TX_DATA_WR_MORE(x) \ 811 (((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE) 812 #define F_FW_OFLD_TX_DATA_WR_MORE V_FW_OFLD_TX_DATA_WR_MORE(1U) 813 814 #define S_FW_OFLD_TX_DATA_WR_SHOVE 14 815 #define M_FW_OFLD_TX_DATA_WR_SHOVE 0x1 816 #define V_FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SHOVE) 817 #define G_FW_OFLD_TX_DATA_WR_SHOVE(x) \ 818 (((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE) 819 #define F_FW_OFLD_TX_DATA_WR_SHOVE V_FW_OFLD_TX_DATA_WR_SHOVE(1U) 820 821 #define S_FW_OFLD_TX_DATA_WR_ULPMODE 10 822 #define M_FW_OFLD_TX_DATA_WR_ULPMODE 0xf 823 #define V_FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE) 824 #define G_FW_OFLD_TX_DATA_WR_ULPMODE(x) \ 825 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE) 826 827 #define S_FW_OFLD_TX_DATA_WR_ULPSUBMODE 6 828 #define M_FW_OFLD_TX_DATA_WR_ULPSUBMODE 0xf 829 #define V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 830 ((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 831 #define G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 832 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \ 833 M_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 834 835 #define S_FW_OFLD_TX_DATA_WR_PROXY 5 836 #define M_FW_OFLD_TX_DATA_WR_PROXY 0x1 837 #define V_FW_OFLD_TX_DATA_WR_PROXY(x) ((x) << S_FW_OFLD_TX_DATA_WR_PROXY) 838 #define G_FW_OFLD_TX_DATA_WR_PROXY(x) \ 839 (((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY) 840 #define F_FW_OFLD_TX_DATA_WR_PROXY V_FW_OFLD_TX_DATA_WR_PROXY(1U) 841 842 struct fw_cmd_wr { 843 __be32 op_dma; 844 __be32 len16_pkd; 845 __be64 cookie_daddr; 846 }; 847 848 #define S_FW_CMD_WR_DMA 17 849 #define M_FW_CMD_WR_DMA 0x1 850 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 851 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 852 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 853 854 struct fw_eth_tx_pkt_vm_wr { 855 __be32 op_immdlen; 856 __be32 equiq_to_len16; 857 __be32 r3[2]; 858 __u8 ethmacdst[6]; 859 __u8 ethmacsrc[6]; 860 __be16 ethtype; 861 __be16 vlantci; 862 }; 863 864 /****************************************************************************** 865 * R I W O R K R E Q U E S T s 866 **************************************/ 867 868 enum fw_ri_wr_opcode { 869 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 870 FW_RI_READ_REQ = 0x1, 871 FW_RI_READ_RESP = 0x2, 872 FW_RI_SEND = 0x3, 873 FW_RI_SEND_WITH_INV = 0x4, 874 FW_RI_SEND_WITH_SE = 0x5, 875 FW_RI_SEND_WITH_SE_INV = 0x6, 876 FW_RI_TERMINATE = 0x7, 877 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 878 FW_RI_BIND_MW = 0x9, 879 FW_RI_FAST_REGISTER = 0xa, 880 FW_RI_LOCAL_INV = 0xb, 881 FW_RI_QP_MODIFY = 0xc, 882 FW_RI_BYPASS = 0xd, 883 FW_RI_RECEIVE = 0xe, 884 #if 0 885 FW_RI_SEND_IMMEDIATE = 0x8, 886 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 887 FW_RI_ATOMIC_REQUEST = 0xa, 888 FW_RI_ATOMIC_RESPONSE = 0xb, 889 890 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 891 FW_RI_FAST_REGISTER = 0xd, 892 FW_RI_LOCAL_INV = 0xe, 893 #endif 894 FW_RI_SGE_EC_CR_RETURN = 0xf 895 }; 896 897 enum fw_ri_wr_flags { 898 FW_RI_COMPLETION_FLAG = 0x01, 899 FW_RI_NOTIFICATION_FLAG = 0x02, 900 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 901 FW_RI_READ_FENCE_FLAG = 0x08, 902 FW_RI_LOCAL_FENCE_FLAG = 0x10, 903 FW_RI_RDMA_READ_INVALIDATE = 0x20 904 }; 905 906 enum fw_ri_mpa_attrs { 907 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 908 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 909 FW_RI_MPA_CRC_ENABLE = 0x04, 910 FW_RI_MPA_IETF_ENABLE = 0x08 911 }; 912 913 enum fw_ri_qp_caps { 914 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 915 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 916 FW_RI_QP_BIND_ENABLE = 0x04, 917 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 918 FW_RI_QP_STAG0_ENABLE = 0x10, 919 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 920 }; 921 922 enum fw_ri_addr_type { 923 FW_RI_ZERO_BASED_TO = 0x00, 924 FW_RI_VA_BASED_TO = 0x01 925 }; 926 927 enum fw_ri_mem_perms { 928 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 929 FW_RI_MEM_ACCESS_REM_READ = 0x02, 930 FW_RI_MEM_ACCESS_REM = 0x03, 931 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 932 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 933 FW_RI_MEM_ACCESS_LOCAL = 0x0C 934 }; 935 936 enum fw_ri_stag_type { 937 FW_RI_STAG_NSMR = 0x00, 938 FW_RI_STAG_SMR = 0x01, 939 FW_RI_STAG_MW = 0x02, 940 FW_RI_STAG_MW_RELAXED = 0x03 941 }; 942 943 enum fw_ri_data_op { 944 FW_RI_DATA_IMMD = 0x81, 945 FW_RI_DATA_DSGL = 0x82, 946 FW_RI_DATA_ISGL = 0x83 947 }; 948 949 enum fw_ri_sgl_depth { 950 FW_RI_SGL_DEPTH_MAX_SQ = 16, 951 FW_RI_SGL_DEPTH_MAX_RQ = 4 952 }; 953 954 enum fw_ri_cqe_err { 955 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 956 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 957 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 958 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 959 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 960 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 961 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 962 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 963 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 964 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 965 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 966 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 967 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 968 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 969 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 970 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 971 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 972 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 973 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 974 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 975 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 976 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 977 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 978 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 979 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 980 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 981 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 982 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 983 984 }; 985 986 struct fw_ri_dsge_pair { 987 __be32 len[2]; 988 __be64 addr[2]; 989 }; 990 991 struct fw_ri_dsgl { 992 __u8 op; 993 __u8 r1; 994 __be16 nsge; 995 __be32 len0; 996 __be64 addr0; 997 #ifndef C99_NOT_SUPPORTED 998 struct fw_ri_dsge_pair sge[0]; 999 #endif 1000 }; 1001 1002 struct fw_ri_sge { 1003 __be32 stag; 1004 __be32 len; 1005 __be64 to; 1006 }; 1007 1008 struct fw_ri_isgl { 1009 __u8 op; 1010 __u8 r1; 1011 __be16 nsge; 1012 __be32 r2; 1013 #ifndef C99_NOT_SUPPORTED 1014 struct fw_ri_sge sge[0]; 1015 #endif 1016 }; 1017 1018 struct fw_ri_immd { 1019 __u8 op; 1020 __u8 r1; 1021 __be16 r2; 1022 __be32 immdlen; 1023 #ifndef C99_NOT_SUPPORTED 1024 __u8 data[0]; 1025 #endif 1026 }; 1027 1028 struct fw_ri_tpte { 1029 __be32 valid_to_pdid; 1030 __be32 locread_to_qpid; 1031 __be32 nosnoop_pbladdr; 1032 __be32 len_lo; 1033 __be32 va_hi; 1034 __be32 va_lo_fbo; 1035 __be32 dca_mwbcnt_pstag; 1036 __be32 len_hi; 1037 }; 1038 1039 #define S_FW_RI_TPTE_VALID 31 1040 #define M_FW_RI_TPTE_VALID 0x1 1041 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1042 #define G_FW_RI_TPTE_VALID(x) \ 1043 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1044 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1045 1046 #define S_FW_RI_TPTE_STAGKEY 23 1047 #define M_FW_RI_TPTE_STAGKEY 0xff 1048 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1049 #define G_FW_RI_TPTE_STAGKEY(x) \ 1050 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1051 1052 #define S_FW_RI_TPTE_STAGSTATE 22 1053 #define M_FW_RI_TPTE_STAGSTATE 0x1 1054 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1055 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1056 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1057 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1058 1059 #define S_FW_RI_TPTE_STAGTYPE 20 1060 #define M_FW_RI_TPTE_STAGTYPE 0x3 1061 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1062 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1063 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1064 1065 #define S_FW_RI_TPTE_PDID 0 1066 #define M_FW_RI_TPTE_PDID 0xfffff 1067 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1068 #define G_FW_RI_TPTE_PDID(x) \ 1069 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1070 1071 #define S_FW_RI_TPTE_PERM 28 1072 #define M_FW_RI_TPTE_PERM 0xf 1073 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1074 #define G_FW_RI_TPTE_PERM(x) \ 1075 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1076 1077 #define S_FW_RI_TPTE_REMINVDIS 27 1078 #define M_FW_RI_TPTE_REMINVDIS 0x1 1079 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1080 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1081 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1082 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1083 1084 #define S_FW_RI_TPTE_ADDRTYPE 26 1085 #define M_FW_RI_TPTE_ADDRTYPE 1 1086 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1087 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1088 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1089 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1090 1091 #define S_FW_RI_TPTE_MWBINDEN 25 1092 #define M_FW_RI_TPTE_MWBINDEN 0x1 1093 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1094 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1095 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1096 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1097 1098 #define S_FW_RI_TPTE_PS 20 1099 #define M_FW_RI_TPTE_PS 0x1f 1100 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1101 #define G_FW_RI_TPTE_PS(x) \ 1102 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1103 1104 #define S_FW_RI_TPTE_QPID 0 1105 #define M_FW_RI_TPTE_QPID 0xfffff 1106 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1107 #define G_FW_RI_TPTE_QPID(x) \ 1108 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1109 1110 #define S_FW_RI_TPTE_NOSNOOP 31 1111 #define M_FW_RI_TPTE_NOSNOOP 0x1 1112 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1113 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1114 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1115 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1116 1117 #define S_FW_RI_TPTE_PBLADDR 0 1118 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1119 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1120 #define G_FW_RI_TPTE_PBLADDR(x) \ 1121 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1122 1123 #define S_FW_RI_TPTE_DCA 24 1124 #define M_FW_RI_TPTE_DCA 0x1f 1125 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1126 #define G_FW_RI_TPTE_DCA(x) \ 1127 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1128 1129 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1130 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1131 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1132 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1133 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1134 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1135 1136 enum fw_ri_cqe_rxtx { 1137 FW_RI_CQE_RXTX_RX = 0x0, 1138 FW_RI_CQE_RXTX_TX = 0x1, 1139 }; 1140 1141 struct fw_ri_cqe { 1142 union fw_ri_rxtx { 1143 struct fw_ri_scqe { 1144 __be32 qpid_n_stat_rxtx_type; 1145 __be32 plen; 1146 __be32 reserved; 1147 __be32 wrid; 1148 } scqe; 1149 struct fw_ri_rcqe { 1150 __be32 qpid_n_stat_rxtx_type; 1151 __be32 plen; 1152 __be32 stag; 1153 __be32 msn; 1154 } rcqe; 1155 } u; 1156 }; 1157 1158 #define S_FW_RI_CQE_QPID 12 1159 #define M_FW_RI_CQE_QPID 0xfffff 1160 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1161 #define G_FW_RI_CQE_QPID(x) \ 1162 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1163 1164 #define S_FW_RI_CQE_NOTIFY 10 1165 #define M_FW_RI_CQE_NOTIFY 0x1 1166 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1167 #define G_FW_RI_CQE_NOTIFY(x) \ 1168 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1169 1170 #define S_FW_RI_CQE_STATUS 5 1171 #define M_FW_RI_CQE_STATUS 0x1f 1172 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1173 #define G_FW_RI_CQE_STATUS(x) \ 1174 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1175 1176 1177 #define S_FW_RI_CQE_RXTX 4 1178 #define M_FW_RI_CQE_RXTX 0x1 1179 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1180 #define G_FW_RI_CQE_RXTX(x) \ 1181 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1182 1183 #define S_FW_RI_CQE_TYPE 0 1184 #define M_FW_RI_CQE_TYPE 0xf 1185 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1186 #define G_FW_RI_CQE_TYPE(x) \ 1187 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1188 1189 enum fw_ri_res_type { 1190 FW_RI_RES_TYPE_SQ, 1191 FW_RI_RES_TYPE_RQ, 1192 FW_RI_RES_TYPE_CQ, 1193 }; 1194 1195 enum fw_ri_res_op { 1196 FW_RI_RES_OP_WRITE, 1197 FW_RI_RES_OP_RESET, 1198 }; 1199 1200 struct fw_ri_res { 1201 union fw_ri_restype { 1202 struct fw_ri_res_sqrq { 1203 __u8 restype; 1204 __u8 op; 1205 __be16 r3; 1206 __be32 eqid; 1207 __be32 r4[2]; 1208 __be32 fetchszm_to_iqid; 1209 __be32 dcaen_to_eqsize; 1210 __be64 eqaddr; 1211 } sqrq; 1212 struct fw_ri_res_cq { 1213 __u8 restype; 1214 __u8 op; 1215 __be16 r3; 1216 __be32 iqid; 1217 __be32 r4[2]; 1218 __be32 iqandst_to_iqandstindex; 1219 __be16 iqdroprss_to_iqesize; 1220 __be16 iqsize; 1221 __be64 iqaddr; 1222 __be32 iqns_iqro; 1223 __be32 r6_lo; 1224 __be64 r7; 1225 } cq; 1226 } u; 1227 }; 1228 1229 struct fw_ri_res_wr { 1230 __be32 op_nres; 1231 __be32 len16_pkd; 1232 __u64 cookie; 1233 #ifndef C99_NOT_SUPPORTED 1234 struct fw_ri_res res[0]; 1235 #endif 1236 }; 1237 1238 #define S_FW_RI_RES_WR_NRES 0 1239 #define M_FW_RI_RES_WR_NRES 0xff 1240 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1241 #define G_FW_RI_RES_WR_NRES(x) \ 1242 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1243 1244 #define S_FW_RI_RES_WR_FETCHSZM 26 1245 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1246 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1247 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1248 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1249 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1250 1251 #define S_FW_RI_RES_WR_STATUSPGNS 25 1252 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1253 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1254 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1255 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1256 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1257 1258 #define S_FW_RI_RES_WR_STATUSPGRO 24 1259 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1260 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1261 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1262 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1263 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1264 1265 #define S_FW_RI_RES_WR_FETCHNS 23 1266 #define M_FW_RI_RES_WR_FETCHNS 0x1 1267 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1268 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1269 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1270 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1271 1272 #define S_FW_RI_RES_WR_FETCHRO 22 1273 #define M_FW_RI_RES_WR_FETCHRO 0x1 1274 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1275 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1276 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1277 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1278 1279 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1280 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1281 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1282 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1283 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1284 1285 #define S_FW_RI_RES_WR_CPRIO 19 1286 #define M_FW_RI_RES_WR_CPRIO 0x1 1287 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1288 #define G_FW_RI_RES_WR_CPRIO(x) \ 1289 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1290 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1291 1292 #define S_FW_RI_RES_WR_ONCHIP 18 1293 #define M_FW_RI_RES_WR_ONCHIP 0x1 1294 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1295 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1296 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1297 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1298 1299 #define S_FW_RI_RES_WR_PCIECHN 16 1300 #define M_FW_RI_RES_WR_PCIECHN 0x3 1301 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1302 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1303 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1304 1305 #define S_FW_RI_RES_WR_IQID 0 1306 #define M_FW_RI_RES_WR_IQID 0xffff 1307 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1308 #define G_FW_RI_RES_WR_IQID(x) \ 1309 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1310 1311 #define S_FW_RI_RES_WR_DCAEN 31 1312 #define M_FW_RI_RES_WR_DCAEN 0x1 1313 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1314 #define G_FW_RI_RES_WR_DCAEN(x) \ 1315 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1316 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1317 1318 #define S_FW_RI_RES_WR_DCACPU 26 1319 #define M_FW_RI_RES_WR_DCACPU 0x1f 1320 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1321 #define G_FW_RI_RES_WR_DCACPU(x) \ 1322 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1323 1324 #define S_FW_RI_RES_WR_FBMIN 23 1325 #define M_FW_RI_RES_WR_FBMIN 0x7 1326 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1327 #define G_FW_RI_RES_WR_FBMIN(x) \ 1328 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1329 1330 #define S_FW_RI_RES_WR_FBMAX 20 1331 #define M_FW_RI_RES_WR_FBMAX 0x7 1332 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1333 #define G_FW_RI_RES_WR_FBMAX(x) \ 1334 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1335 1336 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1337 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1338 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1339 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1340 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1341 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1342 1343 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1344 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1345 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1346 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1347 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1348 1349 #define S_FW_RI_RES_WR_EQSIZE 0 1350 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1351 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1352 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1353 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1354 1355 #define S_FW_RI_RES_WR_IQANDST 15 1356 #define M_FW_RI_RES_WR_IQANDST 0x1 1357 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1358 #define G_FW_RI_RES_WR_IQANDST(x) \ 1359 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1360 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1361 1362 #define S_FW_RI_RES_WR_IQANUS 14 1363 #define M_FW_RI_RES_WR_IQANUS 0x1 1364 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1365 #define G_FW_RI_RES_WR_IQANUS(x) \ 1366 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1367 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1368 1369 #define S_FW_RI_RES_WR_IQANUD 12 1370 #define M_FW_RI_RES_WR_IQANUD 0x3 1371 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1372 #define G_FW_RI_RES_WR_IQANUD(x) \ 1373 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1374 1375 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1376 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1377 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1378 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1379 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1380 1381 #define S_FW_RI_RES_WR_IQDROPRSS 15 1382 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1383 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1384 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1385 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1386 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1387 1388 #define S_FW_RI_RES_WR_IQGTSMODE 14 1389 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1390 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1391 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1392 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1393 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1394 1395 #define S_FW_RI_RES_WR_IQPCIECH 12 1396 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1397 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1398 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1399 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1400 1401 #define S_FW_RI_RES_WR_IQDCAEN 11 1402 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1403 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1404 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1405 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1406 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1407 1408 #define S_FW_RI_RES_WR_IQDCACPU 6 1409 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1410 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1411 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1412 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1413 1414 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1415 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1416 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1417 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1418 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1419 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1420 1421 #define S_FW_RI_RES_WR_IQO 3 1422 #define M_FW_RI_RES_WR_IQO 0x1 1423 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1424 #define G_FW_RI_RES_WR_IQO(x) \ 1425 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1426 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1427 1428 #define S_FW_RI_RES_WR_IQCPRIO 2 1429 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1430 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1431 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1432 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1433 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1434 1435 #define S_FW_RI_RES_WR_IQESIZE 0 1436 #define M_FW_RI_RES_WR_IQESIZE 0x3 1437 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1438 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1439 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1440 1441 #define S_FW_RI_RES_WR_IQNS 31 1442 #define M_FW_RI_RES_WR_IQNS 0x1 1443 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1444 #define G_FW_RI_RES_WR_IQNS(x) \ 1445 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1446 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1447 1448 #define S_FW_RI_RES_WR_IQRO 30 1449 #define M_FW_RI_RES_WR_IQRO 0x1 1450 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1451 #define G_FW_RI_RES_WR_IQRO(x) \ 1452 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1453 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1454 1455 struct fw_ri_rdma_write_wr { 1456 __u8 opcode; 1457 __u8 flags; 1458 __u16 wrid; 1459 __u8 r1[3]; 1460 __u8 len16; 1461 __be64 r2; 1462 __be32 plen; 1463 __be32 stag_sink; 1464 __be64 to_sink; 1465 #ifndef C99_NOT_SUPPORTED 1466 union { 1467 struct fw_ri_immd immd_src[0]; 1468 struct fw_ri_isgl isgl_src[0]; 1469 } u; 1470 #endif 1471 }; 1472 1473 struct fw_ri_send_wr { 1474 __u8 opcode; 1475 __u8 flags; 1476 __u16 wrid; 1477 __u8 r1[3]; 1478 __u8 len16; 1479 __be32 sendop_pkd; 1480 __be32 stag_inv; 1481 __be32 plen; 1482 __be32 r3; 1483 __be64 r4; 1484 #ifndef C99_NOT_SUPPORTED 1485 union { 1486 struct fw_ri_immd immd_src[0]; 1487 struct fw_ri_isgl isgl_src[0]; 1488 } u; 1489 #endif 1490 }; 1491 1492 #define S_FW_RI_SEND_WR_SENDOP 0 1493 #define M_FW_RI_SEND_WR_SENDOP 0xf 1494 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1495 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1496 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1497 1498 struct fw_ri_rdma_read_wr { 1499 __u8 opcode; 1500 __u8 flags; 1501 __u16 wrid; 1502 __u8 r1[3]; 1503 __u8 len16; 1504 __be64 r2; 1505 __be32 stag_sink; 1506 __be32 to_sink_hi; 1507 __be32 to_sink_lo; 1508 __be32 plen; 1509 __be32 stag_src; 1510 __be32 to_src_hi; 1511 __be32 to_src_lo; 1512 __be32 r5; 1513 }; 1514 1515 struct fw_ri_recv_wr { 1516 __u8 opcode; 1517 __u8 r1; 1518 __u16 wrid; 1519 __u8 r2[3]; 1520 __u8 len16; 1521 struct fw_ri_isgl isgl; 1522 }; 1523 1524 struct fw_ri_bind_mw_wr { 1525 __u8 opcode; 1526 __u8 flags; 1527 __u16 wrid; 1528 __u8 r1[3]; 1529 __u8 len16; 1530 __u8 qpbinde_to_dcacpu; 1531 __u8 pgsz_shift; 1532 __u8 addr_type; 1533 __u8 mem_perms; 1534 __be32 stag_mr; 1535 __be32 stag_mw; 1536 __be32 r3; 1537 __be64 len_mw; 1538 __be64 va_fbo; 1539 __be64 r4; 1540 }; 1541 1542 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1543 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1544 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1545 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1546 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1547 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1548 1549 #define S_FW_RI_BIND_MW_WR_NS 5 1550 #define M_FW_RI_BIND_MW_WR_NS 0x1 1551 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1552 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1553 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1554 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1555 1556 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1557 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1558 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1559 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1560 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1561 1562 struct fw_ri_fr_nsmr_wr { 1563 __u8 opcode; 1564 __u8 flags; 1565 __u16 wrid; 1566 __u8 r1[3]; 1567 __u8 len16; 1568 __u8 qpbinde_to_dcacpu; 1569 __u8 pgsz_shift; 1570 __u8 addr_type; 1571 __u8 mem_perms; 1572 __be32 stag; 1573 __be32 len_hi; 1574 __be32 len_lo; 1575 __be32 va_hi; 1576 __be32 va_lo_fbo; 1577 }; 1578 1579 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1580 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1581 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1582 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1583 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1584 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1585 1586 #define S_FW_RI_FR_NSMR_WR_NS 5 1587 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1588 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1589 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1590 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1591 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1592 1593 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1594 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1595 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1596 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1597 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1598 1599 struct fw_ri_inv_lstag_wr { 1600 __u8 opcode; 1601 __u8 flags; 1602 __u16 wrid; 1603 __u8 r1[3]; 1604 __u8 len16; 1605 __be32 r2; 1606 __be32 stag_inv; 1607 }; 1608 1609 struct fw_ri_send_immediate_wr { 1610 __u8 opcode; 1611 __u8 flags; 1612 __u16 wrid; 1613 __u8 r1[3]; 1614 __u8 len16; 1615 __be32 sendimmop_pkd; 1616 __be32 r3; 1617 __be32 plen; 1618 __be32 r4; 1619 __be64 r5; 1620 #ifndef C99_NOT_SUPPORTED 1621 struct fw_ri_immd immd_src[0]; 1622 #endif 1623 }; 1624 1625 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1626 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1627 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1628 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1629 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1630 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1631 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1632 1633 enum fw_ri_atomic_op { 1634 FW_RI_ATOMIC_OP_FETCHADD, 1635 FW_RI_ATOMIC_OP_SWAP, 1636 FW_RI_ATOMIC_OP_CMDSWAP, 1637 }; 1638 1639 struct fw_ri_atomic_wr { 1640 __u8 opcode; 1641 __u8 flags; 1642 __u16 wrid; 1643 __u8 r1[3]; 1644 __u8 len16; 1645 __be32 atomicop_pkd; 1646 __be64 r3; 1647 __be32 aopcode_pkd; 1648 __be32 reqid; 1649 __be32 stag; 1650 __be32 to_hi; 1651 __be32 to_lo; 1652 __be32 addswap_data_hi; 1653 __be32 addswap_data_lo; 1654 __be32 addswap_mask_hi; 1655 __be32 addswap_mask_lo; 1656 __be32 compare_data_hi; 1657 __be32 compare_data_lo; 1658 __be32 compare_mask_hi; 1659 __be32 compare_mask_lo; 1660 __be32 r5; 1661 }; 1662 1663 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1664 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1665 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 1666 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 1667 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 1668 1669 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 1670 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 1671 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 1672 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 1673 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 1674 1675 enum fw_ri_type { 1676 FW_RI_TYPE_INIT, 1677 FW_RI_TYPE_FINI, 1678 FW_RI_TYPE_TERMINATE 1679 }; 1680 1681 enum fw_ri_init_p2ptype { 1682 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 1683 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 1684 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 1685 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 1686 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 1687 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 1688 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 1689 }; 1690 1691 struct fw_ri_wr { 1692 __be32 op_compl; 1693 __be32 flowid_len16; 1694 __u64 cookie; 1695 union fw_ri { 1696 struct fw_ri_init { 1697 __u8 type; 1698 __u8 mpareqbit_p2ptype; 1699 __u8 r4[2]; 1700 __u8 mpa_attrs; 1701 __u8 qp_caps; 1702 __be16 nrqe; 1703 __be32 pdid; 1704 __be32 qpid; 1705 __be32 sq_eqid; 1706 __be32 rq_eqid; 1707 __be32 scqid; 1708 __be32 rcqid; 1709 __be32 ord_max; 1710 __be32 ird_max; 1711 __be32 iss; 1712 __be32 irs; 1713 __be32 hwrqsize; 1714 __be32 hwrqaddr; 1715 __be64 r5; 1716 union fw_ri_init_p2p { 1717 struct fw_ri_rdma_write_wr write; 1718 struct fw_ri_rdma_read_wr read; 1719 struct fw_ri_send_wr send; 1720 } u; 1721 } init; 1722 struct fw_ri_fini { 1723 __u8 type; 1724 __u8 r3[7]; 1725 __be64 r4; 1726 } fini; 1727 struct fw_ri_terminate { 1728 __u8 type; 1729 __u8 r3[3]; 1730 __be32 immdlen; 1731 __u8 termmsg[40]; 1732 } terminate; 1733 } u; 1734 }; 1735 1736 #define S_FW_RI_WR_MPAREQBIT 7 1737 #define M_FW_RI_WR_MPAREQBIT 0x1 1738 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 1739 #define G_FW_RI_WR_MPAREQBIT(x) \ 1740 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 1741 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 1742 1743 #define S_FW_RI_WR_0BRRBIT 6 1744 #define M_FW_RI_WR_0BRRBIT 0x1 1745 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 1746 #define G_FW_RI_WR_0BRRBIT(x) \ 1747 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 1748 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 1749 1750 #define S_FW_RI_WR_P2PTYPE 0 1751 #define M_FW_RI_WR_P2PTYPE 0xf 1752 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 1753 #define G_FW_RI_WR_P2PTYPE(x) \ 1754 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 1755 1756 /****************************************************************************** 1757 * F O i S C S I W O R K R E Q U E S T s 1758 *********************************************/ 1759 1760 #define FW_FOISCSI_NAME_MAX_LEN 224 1761 #define FW_FOISCSI_ALIAS_MAX_LEN 224 1762 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 1763 #define FW_FOISCSI_INIT_NODE_MAX 8 1764 1765 enum fw_chnet_ifconf_wr_subop { 1766 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 1767 1768 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 1769 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 1770 1771 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 1772 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 1773 1774 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 1775 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 1776 1777 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 1778 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 1779 1780 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 1781 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 1782 1783 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 1784 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 1785 1786 FW_CHNET_IFCONF_WR_SUBOP_MAX, 1787 }; 1788 1789 struct fw_chnet_ifconf_wr { 1790 __be32 op_compl; 1791 __be32 flowid_len16; 1792 __be64 cookie; 1793 __be32 if_flowid; 1794 __u8 idx; 1795 __u8 subop; 1796 __u8 retval; 1797 __u8 r2; 1798 __be64 r3; 1799 struct fw_chnet_ifconf_params { 1800 __be32 r0; 1801 __be16 vlanid; 1802 __be16 mtu; 1803 union fw_chnet_ifconf_addr_type { 1804 struct fw_chnet_ifconf_ipv4 { 1805 __be32 addr; 1806 __be32 mask; 1807 __be32 router; 1808 __be32 r0; 1809 __be64 r1; 1810 } ipv4; 1811 struct fw_chnet_ifconf_ipv6 { 1812 __be64 linklocal_lo; 1813 __be64 linklocal_hi; 1814 __be64 router_hi; 1815 __be64 router_lo; 1816 __be64 aconf_hi; 1817 __be64 aconf_lo; 1818 __be64 linklocal_aconf_hi; 1819 __be64 linklocal_aconf_lo; 1820 __be64 router_aconf_hi; 1821 __be64 router_aconf_lo; 1822 __be64 r0; 1823 } ipv6; 1824 } in_attr; 1825 } param; 1826 }; 1827 1828 enum fw_foiscsi_node_type { 1829 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 1830 FW_FOISCSI_NODE_TYPE_TARGET, 1831 }; 1832 1833 enum fw_foiscsi_session_type { 1834 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 1835 FW_FOISCSI_SESSION_TYPE_NORMAL, 1836 }; 1837 1838 enum fw_foiscsi_auth_policy { 1839 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 1840 FW_FOISCSI_AUTH_POLICY_MUTUAL, 1841 }; 1842 1843 enum fw_foiscsi_auth_method { 1844 FW_FOISCSI_AUTH_METHOD_NONE = 0, 1845 FW_FOISCSI_AUTH_METHOD_CHAP, 1846 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 1847 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 1848 }; 1849 1850 enum fw_foiscsi_digest_type { 1851 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 1852 FW_FOISCSI_DIGEST_TYPE_CRC32, 1853 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 1854 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 1855 }; 1856 1857 enum fw_foiscsi_wr_subop { 1858 FW_FOISCSI_WR_SUBOP_ADD = 1, 1859 FW_FOISCSI_WR_SUBOP_DEL = 2, 1860 FW_FOISCSI_WR_SUBOP_MOD = 4, 1861 }; 1862 1863 enum fw_foiscsi_ctrl_state { 1864 FW_FOISCSI_CTRL_STATE_FREE = 0, 1865 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 1866 FW_FOISCSI_CTRL_STATE_FAILED, 1867 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 1868 FW_FOISCSI_CTRL_STATE_REDIRECT, 1869 }; 1870 1871 struct fw_rdev_wr { 1872 __be32 op_to_immdlen; 1873 __be32 alloc_to_len16; 1874 __be64 cookie; 1875 __u8 protocol; 1876 __u8 event_cause; 1877 __u8 cur_state; 1878 __u8 prev_state; 1879 __be32 flags_to_assoc_flowid; 1880 union rdev_entry { 1881 struct fcoe_rdev_entry { 1882 __be32 flowid; 1883 __u8 protocol; 1884 __u8 event_cause; 1885 __u8 flags; 1886 __u8 rjt_reason; 1887 __u8 cur_login_st; 1888 __u8 prev_login_st; 1889 __be16 rcv_fr_sz; 1890 __u8 rd_xfer_rdy_to_rport_type; 1891 __u8 vft_to_qos; 1892 __u8 org_proc_assoc_to_acc_rsp_code; 1893 __u8 enh_disc_to_tgt; 1894 __u8 wwnn[8]; 1895 __u8 wwpn[8]; 1896 __be16 iqid; 1897 __u8 fc_oui[3]; 1898 __u8 r_id[3]; 1899 } fcoe_rdev; 1900 struct iscsi_rdev_entry { 1901 __be32 flowid; 1902 __u8 protocol; 1903 __u8 event_cause; 1904 __u8 flags; 1905 __u8 r3; 1906 __be16 iscsi_opts; 1907 __be16 tcp_opts; 1908 __be16 ip_opts; 1909 __be16 max_rcv_len; 1910 __be16 max_snd_len; 1911 __be16 first_brst_len; 1912 __be16 max_brst_len; 1913 __be16 r4; 1914 __be16 def_time2wait; 1915 __be16 def_time2ret; 1916 __be16 nop_out_intrvl; 1917 __be16 non_scsi_to; 1918 __be16 isid; 1919 __be16 tsid; 1920 __be16 port; 1921 __be16 tpgt; 1922 __u8 r5[6]; 1923 __be16 iqid; 1924 } iscsi_rdev; 1925 } u; 1926 }; 1927 1928 #define S_FW_RDEV_WR_IMMDLEN 0 1929 #define M_FW_RDEV_WR_IMMDLEN 0xff 1930 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 1931 #define G_FW_RDEV_WR_IMMDLEN(x) \ 1932 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 1933 1934 #define S_FW_RDEV_WR_ALLOC 31 1935 #define M_FW_RDEV_WR_ALLOC 0x1 1936 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 1937 #define G_FW_RDEV_WR_ALLOC(x) \ 1938 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 1939 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 1940 1941 #define S_FW_RDEV_WR_FREE 30 1942 #define M_FW_RDEV_WR_FREE 0x1 1943 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 1944 #define G_FW_RDEV_WR_FREE(x) \ 1945 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 1946 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 1947 1948 #define S_FW_RDEV_WR_MODIFY 29 1949 #define M_FW_RDEV_WR_MODIFY 0x1 1950 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 1951 #define G_FW_RDEV_WR_MODIFY(x) \ 1952 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 1953 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 1954 1955 #define S_FW_RDEV_WR_FLOWID 8 1956 #define M_FW_RDEV_WR_FLOWID 0xfffff 1957 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 1958 #define G_FW_RDEV_WR_FLOWID(x) \ 1959 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 1960 1961 #define S_FW_RDEV_WR_LEN16 0 1962 #define M_FW_RDEV_WR_LEN16 0xff 1963 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 1964 #define G_FW_RDEV_WR_LEN16(x) \ 1965 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 1966 1967 #define S_FW_RDEV_WR_FLAGS 24 1968 #define M_FW_RDEV_WR_FLAGS 0xff 1969 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 1970 #define G_FW_RDEV_WR_FLAGS(x) \ 1971 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 1972 1973 #define S_FW_RDEV_WR_GET_NEXT 20 1974 #define M_FW_RDEV_WR_GET_NEXT 0xf 1975 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 1976 #define G_FW_RDEV_WR_GET_NEXT(x) \ 1977 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 1978 1979 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 1980 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 1981 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 1982 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 1983 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 1984 1985 #define S_FW_RDEV_WR_RJT 7 1986 #define M_FW_RDEV_WR_RJT 0x1 1987 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 1988 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 1989 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 1990 1991 #define S_FW_RDEV_WR_REASON 0 1992 #define M_FW_RDEV_WR_REASON 0x7f 1993 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 1994 #define G_FW_RDEV_WR_REASON(x) \ 1995 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 1996 1997 #define S_FW_RDEV_WR_RD_XFER_RDY 7 1998 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 1999 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2000 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2001 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2002 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2003 2004 #define S_FW_RDEV_WR_WR_XFER_RDY 6 2005 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2006 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2007 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2008 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2009 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2010 2011 #define S_FW_RDEV_WR_FC_SP 5 2012 #define M_FW_RDEV_WR_FC_SP 0x1 2013 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2014 #define G_FW_RDEV_WR_FC_SP(x) \ 2015 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2016 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2017 2018 #define S_FW_RDEV_WR_RPORT_TYPE 0 2019 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2020 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2021 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2022 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2023 2024 #define S_FW_RDEV_WR_VFT 7 2025 #define M_FW_RDEV_WR_VFT 0x1 2026 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2027 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2028 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2029 2030 #define S_FW_RDEV_WR_NPIV 6 2031 #define M_FW_RDEV_WR_NPIV 0x1 2032 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2033 #define G_FW_RDEV_WR_NPIV(x) \ 2034 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2035 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2036 2037 #define S_FW_RDEV_WR_CLASS 4 2038 #define M_FW_RDEV_WR_CLASS 0x3 2039 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2040 #define G_FW_RDEV_WR_CLASS(x) \ 2041 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2042 2043 #define S_FW_RDEV_WR_SEQ_DEL 3 2044 #define M_FW_RDEV_WR_SEQ_DEL 0x1 2045 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2046 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2047 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2048 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2049 2050 #define S_FW_RDEV_WR_PRIO_PREEMP 2 2051 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2052 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2053 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2054 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2055 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2056 2057 #define S_FW_RDEV_WR_PREF 1 2058 #define M_FW_RDEV_WR_PREF 0x1 2059 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2060 #define G_FW_RDEV_WR_PREF(x) \ 2061 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2062 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2063 2064 #define S_FW_RDEV_WR_QOS 0 2065 #define M_FW_RDEV_WR_QOS 0x1 2066 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2067 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2068 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2069 2070 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2071 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2072 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2073 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2074 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2075 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2076 2077 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2078 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2079 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2080 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2081 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2082 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2083 2084 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2085 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2086 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2087 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2088 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2089 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2090 2091 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2092 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2093 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2094 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2095 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2096 2097 #define S_FW_RDEV_WR_ENH_DISC 7 2098 #define M_FW_RDEV_WR_ENH_DISC 0x1 2099 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2100 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2101 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2102 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2103 2104 #define S_FW_RDEV_WR_REC 6 2105 #define M_FW_RDEV_WR_REC 0x1 2106 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2107 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2108 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2109 2110 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2111 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2112 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2113 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2114 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2115 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2116 2117 #define S_FW_RDEV_WR_RETRY 4 2118 #define M_FW_RDEV_WR_RETRY 0x1 2119 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2120 #define G_FW_RDEV_WR_RETRY(x) \ 2121 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2122 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2123 2124 #define S_FW_RDEV_WR_CONF_CMPL 3 2125 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2126 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2127 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2128 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2129 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2130 2131 #define S_FW_RDEV_WR_DATA_OVLY 2 2132 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2133 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2134 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2135 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2136 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2137 2138 #define S_FW_RDEV_WR_INI 1 2139 #define M_FW_RDEV_WR_INI 0x1 2140 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2141 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2142 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2143 2144 #define S_FW_RDEV_WR_TGT 0 2145 #define M_FW_RDEV_WR_TGT 0x1 2146 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2147 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2148 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2149 2150 struct fw_foiscsi_node_wr { 2151 __be32 op_to_immdlen; 2152 __be32 flowid_len16; 2153 __u64 cookie; 2154 __u8 subop; 2155 __u8 status; 2156 __u8 alias_len; 2157 __u8 iqn_len; 2158 __be32 node_flowid; 2159 __be16 nodeid; 2160 __be16 login_retry; 2161 __be16 retry_timeout; 2162 __be16 r3; 2163 __u8 iqn[224]; 2164 __u8 alias[224]; 2165 }; 2166 2167 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2168 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2169 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2170 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2171 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2172 2173 struct fw_foiscsi_ctrl_wr { 2174 __be32 op_compl; 2175 __be32 flowid_len16; 2176 __u64 cookie; 2177 __u8 subop; 2178 __u8 status; 2179 __u8 ctrl_state; 2180 __u8 io_state; 2181 __be32 node_id; 2182 __be32 ctrl_id; 2183 __be32 io_id; 2184 struct fw_foiscsi_sess_attr { 2185 __be32 sess_type_to_erl; 2186 __be16 max_conn; 2187 __be16 max_r2t; 2188 __be16 time2wait; 2189 __be16 time2retain; 2190 __be32 max_burst; 2191 __be32 first_burst; 2192 __be32 r1; 2193 } sess_attr; 2194 struct fw_foiscsi_conn_attr { 2195 __be32 hdigest_to_ddp_pgsz; 2196 __be32 max_rcv_dsl; 2197 __be32 ping_tmo; 2198 __be16 dst_port; 2199 __be16 src_port; 2200 union fw_foiscsi_conn_attr_addr { 2201 struct fw_foiscsi_conn_attr_ipv6 { 2202 __be64 dst_addr[2]; 2203 __be64 src_addr[2]; 2204 } ipv6_addr; 2205 struct fw_foiscsi_conn_attr_ipv4 { 2206 __be32 dst_addr; 2207 __be32 src_addr; 2208 } ipv4_addr; 2209 } u; 2210 } conn_attr; 2211 __u8 tgt_name_len; 2212 __u8 r3[7]; 2213 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2214 }; 2215 2216 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2217 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2218 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2219 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2220 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2221 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2222 2223 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2224 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2225 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2226 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2227 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2228 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2229 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2230 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2231 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2232 2233 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2234 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2235 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2236 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2237 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2238 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2239 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2240 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2241 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2242 2243 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2244 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2245 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2246 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2247 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2248 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2249 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2250 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2251 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2252 2253 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2254 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2255 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2256 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2257 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2258 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2259 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2260 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2261 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2262 2263 #define S_FW_FOISCSI_CTRL_WR_ERL 24 2264 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2265 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2266 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2267 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2268 2269 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2270 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2271 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2272 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2273 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2274 2275 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2276 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2277 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2278 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2279 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2280 2281 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2282 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2283 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2284 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2285 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2286 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2287 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2288 2289 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2290 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2291 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2292 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2293 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2294 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2295 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2296 2297 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2298 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2299 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2300 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2301 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2302 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2303 2304 struct fw_foiscsi_chap_wr { 2305 __be32 op_compl; 2306 __be32 flowid_len16; 2307 __u64 cookie; 2308 __u8 status; 2309 __u8 id_len; 2310 __u8 sec_len; 2311 __u8 node_type; 2312 __be16 node_id; 2313 __u8 r3[2]; 2314 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2315 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 2316 }; 2317 2318 /****************************************************************************** 2319 * F O F C O E W O R K R E Q U E S T s 2320 *******************************************/ 2321 2322 struct fw_fcoe_els_ct_wr { 2323 __be32 op_immdlen; 2324 __be32 flowid_len16; 2325 __be64 cookie; 2326 __be16 iqid; 2327 __u8 tmo_val; 2328 __u8 els_ct_type; 2329 __u8 ctl_pri; 2330 __u8 cp_en_class; 2331 __be16 xfer_cnt; 2332 __u8 fl_to_sp; 2333 __u8 l_id[3]; 2334 __u8 r5; 2335 __u8 r_id[3]; 2336 __be64 rsp_dmaaddr; 2337 __be32 rsp_dmalen; 2338 __be32 r6; 2339 }; 2340 2341 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2342 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2343 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2344 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2345 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2346 2347 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2348 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2349 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2350 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2351 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2352 2353 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2354 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2355 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2356 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2357 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2358 2359 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 2360 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2361 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2362 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2363 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2364 2365 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2366 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2367 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2368 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2369 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2370 2371 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 2372 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2373 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2374 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2375 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2376 2377 #define S_FW_FCOE_ELS_CT_WR_FL 2 2378 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 2379 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2380 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2381 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2382 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2383 2384 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 2385 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2386 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2387 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2388 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2389 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2390 2391 #define S_FW_FCOE_ELS_CT_WR_SP 0 2392 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 2393 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2394 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2395 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2396 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2397 2398 /****************************************************************************** 2399 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 2400 *****************************************************************************/ 2401 2402 struct fw_scsi_write_wr { 2403 __be32 op_immdlen; 2404 __be32 flowid_len16; 2405 __be64 cookie; 2406 __be16 iqid; 2407 __u8 tmo_val; 2408 __u8 use_xfer_cnt; 2409 union fw_scsi_write_priv { 2410 struct fcoe_write_priv { 2411 __u8 ctl_pri; 2412 __u8 cp_en_class; 2413 __u8 r3_lo[2]; 2414 } fcoe; 2415 struct iscsi_write_priv { 2416 __u8 r3[4]; 2417 } iscsi; 2418 } u; 2419 __be32 xfer_cnt; 2420 __be32 ini_xfer_cnt; 2421 __be64 rsp_dmaaddr; 2422 __be32 rsp_dmalen; 2423 __be32 r4; 2424 }; 2425 2426 #define S_FW_SCSI_WRITE_WR_OPCODE 24 2427 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2428 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2429 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2430 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2431 2432 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2433 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2434 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2435 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2436 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2437 2438 #define S_FW_SCSI_WRITE_WR_FLOWID 8 2439 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2440 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2441 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2442 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2443 2444 #define S_FW_SCSI_WRITE_WR_LEN16 0 2445 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 2446 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2447 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 2448 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 2449 2450 #define S_FW_SCSI_WRITE_WR_CP_EN 6 2451 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 2452 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 2453 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 2454 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 2455 2456 #define S_FW_SCSI_WRITE_WR_CLASS 4 2457 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 2458 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 2459 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 2460 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 2461 2462 struct fw_scsi_read_wr { 2463 __be32 op_immdlen; 2464 __be32 flowid_len16; 2465 __be64 cookie; 2466 __be16 iqid; 2467 __u8 tmo_val; 2468 __u8 use_xfer_cnt; 2469 union fw_scsi_read_priv { 2470 struct fcoe_read_priv { 2471 __u8 ctl_pri; 2472 __u8 cp_en_class; 2473 __u8 r3_lo[2]; 2474 } fcoe; 2475 struct iscsi_read_priv { 2476 __u8 r3[4]; 2477 } iscsi; 2478 } u; 2479 __be32 xfer_cnt; 2480 __be32 ini_xfer_cnt; 2481 __be64 rsp_dmaaddr; 2482 __be32 rsp_dmalen; 2483 __be32 r4; 2484 }; 2485 2486 #define S_FW_SCSI_READ_WR_OPCODE 24 2487 #define M_FW_SCSI_READ_WR_OPCODE 0xff 2488 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 2489 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 2490 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 2491 2492 #define S_FW_SCSI_READ_WR_IMMDLEN 0 2493 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 2494 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 2495 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 2496 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 2497 2498 #define S_FW_SCSI_READ_WR_FLOWID 8 2499 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 2500 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 2501 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 2502 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 2503 2504 #define S_FW_SCSI_READ_WR_LEN16 0 2505 #define M_FW_SCSI_READ_WR_LEN16 0xff 2506 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 2507 #define G_FW_SCSI_READ_WR_LEN16(x) \ 2508 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 2509 2510 #define S_FW_SCSI_READ_WR_CP_EN 6 2511 #define M_FW_SCSI_READ_WR_CP_EN 0x3 2512 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 2513 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 2514 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 2515 2516 #define S_FW_SCSI_READ_WR_CLASS 4 2517 #define M_FW_SCSI_READ_WR_CLASS 0x3 2518 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 2519 #define G_FW_SCSI_READ_WR_CLASS(x) \ 2520 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 2521 2522 struct fw_scsi_cmd_wr { 2523 __be32 op_immdlen; 2524 __be32 flowid_len16; 2525 __be64 cookie; 2526 __be16 iqid; 2527 __u8 tmo_val; 2528 __u8 r3; 2529 union fw_scsi_cmd_priv { 2530 struct fcoe_cmd_priv { 2531 __u8 ctl_pri; 2532 __u8 cp_en_class; 2533 __u8 r4_lo[2]; 2534 } fcoe; 2535 struct iscsi_cmd_priv { 2536 __u8 r4[4]; 2537 } iscsi; 2538 } u; 2539 __u8 r5[8]; 2540 __be64 rsp_dmaaddr; 2541 __be32 rsp_dmalen; 2542 __be32 r6; 2543 }; 2544 2545 #define S_FW_SCSI_CMD_WR_OPCODE 24 2546 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 2547 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 2548 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 2549 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 2550 2551 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 2552 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 2553 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 2554 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 2555 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 2556 2557 #define S_FW_SCSI_CMD_WR_FLOWID 8 2558 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 2559 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 2560 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 2561 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 2562 2563 #define S_FW_SCSI_CMD_WR_LEN16 0 2564 #define M_FW_SCSI_CMD_WR_LEN16 0xff 2565 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 2566 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 2567 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 2568 2569 #define S_FW_SCSI_CMD_WR_CP_EN 6 2570 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 2571 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 2572 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 2573 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 2574 2575 #define S_FW_SCSI_CMD_WR_CLASS 4 2576 #define M_FW_SCSI_CMD_WR_CLASS 0x3 2577 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 2578 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 2579 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 2580 2581 struct fw_scsi_abrt_cls_wr { 2582 __be32 op_immdlen; 2583 __be32 flowid_len16; 2584 __be64 cookie; 2585 __be16 iqid; 2586 __u8 tmo_val; 2587 __u8 sub_opcode_to_chk_all_io; 2588 __u8 r3[4]; 2589 __be64 t_cookie; 2590 }; 2591 2592 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 2593 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 2594 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 2595 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 2596 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 2597 2598 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 2599 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 2600 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2601 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2602 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2603 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2604 2605 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 2606 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 2607 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 2608 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 2609 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 2610 2611 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 2612 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 2613 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 2614 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 2615 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 2616 2617 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 2618 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 2619 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2620 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2621 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2622 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 2623 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2624 2625 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 2626 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 2627 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 2628 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 2629 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 2630 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 2631 2632 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 2633 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 2634 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2635 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2636 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2637 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 2638 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2639 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 2640 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 2641 2642 struct fw_scsi_tgt_acc_wr { 2643 __be32 op_immdlen; 2644 __be32 flowid_len16; 2645 __be64 cookie; 2646 __be16 iqid; 2647 __u8 r3; 2648 __u8 use_burst_len; 2649 union fw_scsi_tgt_acc_priv { 2650 struct fcoe_tgt_acc_priv { 2651 __u8 ctl_pri; 2652 __u8 cp_en_class; 2653 __u8 r4_lo[2]; 2654 } fcoe; 2655 struct iscsi_tgt_acc_priv { 2656 __u8 r4[4]; 2657 } iscsi; 2658 } u; 2659 __be32 burst_len; 2660 __be32 rel_off; 2661 __be64 r5; 2662 __be32 r6; 2663 __be32 tot_xfer_len; 2664 }; 2665 2666 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 2667 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 2668 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 2669 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 2670 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 2671 2672 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 2673 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 2674 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2675 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 2676 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2677 2678 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 2679 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 2680 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 2681 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 2682 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 2683 2684 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 2685 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 2686 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 2687 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 2688 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 2689 2690 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 2691 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 2692 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 2693 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 2694 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 2695 2696 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 2697 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 2698 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 2699 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 2700 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 2701 2702 struct fw_scsi_tgt_xmit_wr { 2703 __be32 op_immdlen; 2704 __be32 flowid_len16; 2705 __be64 cookie; 2706 __be16 iqid; 2707 __u8 auto_rsp; 2708 __u8 use_xfer_cnt; 2709 union fw_scsi_tgt_xmit_priv { 2710 struct fcoe_tgt_xmit_priv { 2711 __u8 ctl_pri; 2712 __u8 cp_en_class; 2713 __u8 r3_lo[2]; 2714 } fcoe; 2715 struct iscsi_tgt_xmit_priv { 2716 __u8 r3[4]; 2717 } iscsi; 2718 } u; 2719 __be32 xfer_cnt; 2720 __be32 r4; 2721 __be64 r5; 2722 __be32 r6; 2723 __be32 tot_xfer_len; 2724 }; 2725 2726 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 2727 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 2728 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 2729 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 2730 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 2731 2732 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 2733 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 2734 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2735 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2736 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2737 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2738 2739 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 2740 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 2741 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 2742 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 2743 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 2744 2745 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 2746 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 2747 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 2748 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 2749 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 2750 2751 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 2752 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 2753 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 2754 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 2755 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 2756 2757 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 2758 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 2759 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 2760 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 2761 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 2762 2763 struct fw_scsi_tgt_rsp_wr { 2764 __be32 op_immdlen; 2765 __be32 flowid_len16; 2766 __be64 cookie; 2767 __be16 iqid; 2768 __u8 r3[2]; 2769 union fw_scsi_tgt_rsp_priv { 2770 struct fcoe_tgt_rsp_priv { 2771 __u8 ctl_pri; 2772 __u8 cp_en_class; 2773 __u8 r4_lo[2]; 2774 } fcoe; 2775 struct iscsi_tgt_rsp_priv { 2776 __u8 r4[4]; 2777 } iscsi; 2778 } u; 2779 __u8 r5[8]; 2780 }; 2781 2782 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 2783 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 2784 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 2785 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 2786 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 2787 2788 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 2789 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 2790 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2791 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 2792 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2793 2794 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 2795 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 2796 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 2797 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 2798 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 2799 2800 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 2801 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 2802 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 2803 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 2804 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 2805 2806 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 2807 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 2808 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 2809 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 2810 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 2811 2812 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 2813 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 2814 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 2815 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 2816 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 2817 2818 struct fw_pofcoe_tcb_wr { 2819 __be32 op_compl; 2820 __be32 equiq_to_len16; 2821 __be64 cookie; 2822 __be32 tid_to_port; 2823 __be16 x_id; 2824 __be16 vlan_id; 2825 __be32 s_id; 2826 __be32 d_id; 2827 __be32 tag; 2828 __be32 xfer_len; 2829 __be32 r4; 2830 __be16 r5; 2831 __be16 iqid; 2832 }; 2833 2834 #define S_FW_POFCOE_TCB_WR_TID 12 2835 #define M_FW_POFCOE_TCB_WR_TID 0xfffff 2836 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 2837 #define G_FW_POFCOE_TCB_WR_TID(x) \ 2838 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 2839 2840 #define S_FW_POFCOE_TCB_WR_ALLOC 4 2841 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 2842 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 2843 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 2844 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 2845 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 2846 2847 #define S_FW_POFCOE_TCB_WR_FREE 3 2848 #define M_FW_POFCOE_TCB_WR_FREE 0x1 2849 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 2850 #define G_FW_POFCOE_TCB_WR_FREE(x) \ 2851 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 2852 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 2853 2854 #define S_FW_POFCOE_TCB_WR_PORT 0 2855 #define M_FW_POFCOE_TCB_WR_PORT 0x7 2856 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 2857 #define G_FW_POFCOE_TCB_WR_PORT(x) \ 2858 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 2859 2860 struct fw_pofcoe_ulptx_wr { 2861 __be32 op_pkd; 2862 __be32 equiq_to_len16; 2863 __u64 cookie; 2864 }; 2865 2866 2867 /****************************************************************************** 2868 * C O M M A N D s 2869 *********************/ 2870 2871 /* 2872 * The maximum length of time, in miliseconds, that we expect any firmware 2873 * command to take to execute and return a reply to the host. The RESET 2874 * and INITIALIZE commands can take a fair amount of time to execute but 2875 * most execute in far less time than this maximum. This constant is used 2876 * by host software to determine how long to wait for a firmware command 2877 * reply before declaring the firmware as dead/unreachable ... 2878 */ 2879 #define FW_CMD_MAX_TIMEOUT 10000 2880 2881 /* 2882 * If a host driver does a HELLO and discovers that there's already a MASTER 2883 * selected, we may have to wait for that MASTER to finish issuing RESET, 2884 * configuration and INITIALIZE commands. Also, there's a possibility that 2885 * our own HELLO may get lost if it happens right as the MASTER is issuign a 2886 * RESET command, so we need to be willing to make a few retries of our HELLO. 2887 */ 2888 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 2889 #define FW_CMD_HELLO_RETRIES 3 2890 2891 enum fw_cmd_opcodes { 2892 FW_LDST_CMD = 0x01, 2893 FW_RESET_CMD = 0x03, 2894 FW_HELLO_CMD = 0x04, 2895 FW_BYE_CMD = 0x05, 2896 FW_INITIALIZE_CMD = 0x06, 2897 FW_CAPS_CONFIG_CMD = 0x07, 2898 FW_PARAMS_CMD = 0x08, 2899 FW_PFVF_CMD = 0x09, 2900 FW_IQ_CMD = 0x10, 2901 FW_EQ_MNGT_CMD = 0x11, 2902 FW_EQ_ETH_CMD = 0x12, 2903 FW_EQ_CTRL_CMD = 0x13, 2904 FW_EQ_OFLD_CMD = 0x21, 2905 FW_VI_CMD = 0x14, 2906 FW_VI_MAC_CMD = 0x15, 2907 FW_VI_RXMODE_CMD = 0x16, 2908 FW_VI_ENABLE_CMD = 0x17, 2909 FW_VI_STATS_CMD = 0x1a, 2910 FW_ACL_MAC_CMD = 0x18, 2911 FW_ACL_VLAN_CMD = 0x19, 2912 FW_PORT_CMD = 0x1b, 2913 FW_PORT_STATS_CMD = 0x1c, 2914 FW_PORT_LB_STATS_CMD = 0x1d, 2915 FW_PORT_TRACE_CMD = 0x1e, 2916 FW_PORT_TRACE_MMAP_CMD = 0x1f, 2917 FW_RSS_IND_TBL_CMD = 0x20, 2918 FW_RSS_GLB_CONFIG_CMD = 0x22, 2919 FW_RSS_VI_CONFIG_CMD = 0x23, 2920 FW_SCHED_CMD = 0x24, 2921 FW_DEVLOG_CMD = 0x25, 2922 FW_WATCHDOG_CMD = 0x27, 2923 FW_CLIP_CMD = 0x28, 2924 FW_CHNET_IFACE_CMD = 0x26, 2925 FW_FCOE_RES_INFO_CMD = 0x31, 2926 FW_FCOE_LINK_CMD = 0x32, 2927 FW_FCOE_VNP_CMD = 0x33, 2928 FW_FCOE_SPARAMS_CMD = 0x35, 2929 FW_FCOE_STATS_CMD = 0x37, 2930 FW_FCOE_FCF_CMD = 0x38, 2931 FW_LASTC2E_CMD = 0x40, 2932 FW_ERROR_CMD = 0x80, 2933 FW_DEBUG_CMD = 0x81, 2934 }; 2935 2936 enum fw_cmd_cap { 2937 FW_CMD_CAP_PF = 0x01, 2938 FW_CMD_CAP_DMAQ = 0x02, 2939 FW_CMD_CAP_PORT = 0x04, 2940 FW_CMD_CAP_PORTPROMISC = 0x08, 2941 FW_CMD_CAP_PORTSTATS = 0x10, 2942 FW_CMD_CAP_VF = 0x80, 2943 }; 2944 2945 /* 2946 * Generic command header flit0 2947 */ 2948 struct fw_cmd_hdr { 2949 __be32 hi; 2950 __be32 lo; 2951 }; 2952 2953 #define S_FW_CMD_OP 24 2954 #define M_FW_CMD_OP 0xff 2955 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 2956 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 2957 2958 #define S_FW_CMD_REQUEST 23 2959 #define M_FW_CMD_REQUEST 0x1 2960 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 2961 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 2962 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 2963 2964 #define S_FW_CMD_READ 22 2965 #define M_FW_CMD_READ 0x1 2966 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 2967 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 2968 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 2969 2970 #define S_FW_CMD_WRITE 21 2971 #define M_FW_CMD_WRITE 0x1 2972 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 2973 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 2974 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 2975 2976 #define S_FW_CMD_EXEC 20 2977 #define M_FW_CMD_EXEC 0x1 2978 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 2979 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 2980 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 2981 2982 #define S_FW_CMD_RAMASK 20 2983 #define M_FW_CMD_RAMASK 0xf 2984 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 2985 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 2986 2987 #define S_FW_CMD_RETVAL 8 2988 #define M_FW_CMD_RETVAL 0xff 2989 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 2990 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 2991 2992 #define S_FW_CMD_LEN16 0 2993 #define M_FW_CMD_LEN16 0xff 2994 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 2995 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 2996 2997 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 2998 2999 /* 3000 * address spaces 3001 */ 3002 enum fw_ldst_addrspc { 3003 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 3004 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 3005 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 3006 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 3007 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 3008 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 3009 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 3010 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 3011 FW_LDST_ADDRSPC_MDIO = 0x0018, 3012 FW_LDST_ADDRSPC_MPS = 0x0020, 3013 FW_LDST_ADDRSPC_FUNC = 0x0028, 3014 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 3015 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 3016 FW_LDST_ADDRSPC_LE = 0x0030, 3017 FW_LDST_ADDRSPC_I2C = 0x0038, 3018 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 3019 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 3020 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 3021 }; 3022 3023 /* 3024 * MDIO VSC8634 register access control field 3025 */ 3026 enum fw_ldst_mdio_vsc8634_aid { 3027 FW_LDST_MDIO_VS_STANDARD, 3028 FW_LDST_MDIO_VS_EXTENDED, 3029 FW_LDST_MDIO_VS_GPIO 3030 }; 3031 3032 enum fw_ldst_mps_fid { 3033 FW_LDST_MPS_ATRB, 3034 FW_LDST_MPS_RPLC 3035 }; 3036 3037 enum fw_ldst_func_access_ctl { 3038 FW_LDST_FUNC_ACC_CTL_VIID, 3039 FW_LDST_FUNC_ACC_CTL_FID 3040 }; 3041 3042 enum fw_ldst_func_mod_index { 3043 FW_LDST_FUNC_MPS 3044 }; 3045 3046 struct fw_ldst_cmd { 3047 __be32 op_to_addrspace; 3048 __be32 cycles_to_len16; 3049 union fw_ldst { 3050 struct fw_ldst_addrval { 3051 __be32 addr; 3052 __be32 val; 3053 } addrval; 3054 struct fw_ldst_idctxt { 3055 __be32 physid; 3056 __be32 msg_ctxtflush; 3057 __be32 ctxt_data7; 3058 __be32 ctxt_data6; 3059 __be32 ctxt_data5; 3060 __be32 ctxt_data4; 3061 __be32 ctxt_data3; 3062 __be32 ctxt_data2; 3063 __be32 ctxt_data1; 3064 __be32 ctxt_data0; 3065 } idctxt; 3066 struct fw_ldst_mdio { 3067 __be16 paddr_mmd; 3068 __be16 raddr; 3069 __be16 vctl; 3070 __be16 rval; 3071 } mdio; 3072 struct fw_ldst_mps { 3073 __be16 fid_ctl; 3074 __be16 rplcpf_pkd; 3075 __be32 rplc127_96; 3076 __be32 rplc95_64; 3077 __be32 rplc63_32; 3078 __be32 rplc31_0; 3079 __be32 atrb; 3080 __be16 vlan[16]; 3081 } mps; 3082 struct fw_ldst_func { 3083 __u8 access_ctl; 3084 __u8 mod_index; 3085 __be16 ctl_id; 3086 __be32 offset; 3087 __be64 data0; 3088 __be64 data1; 3089 } func; 3090 struct fw_ldst_pcie { 3091 __u8 ctrl_to_fn; 3092 __u8 bnum; 3093 __u8 r; 3094 __u8 ext_r; 3095 __u8 select_naccess; 3096 __u8 pcie_fn; 3097 __be16 nset_pkd; 3098 __be32 data[12]; 3099 } pcie; 3100 struct fw_ldst_i2c_deprecated { 3101 __u8 pid_pkd; 3102 __u8 base; 3103 __u8 boffset; 3104 __u8 data; 3105 __be32 r9; 3106 } i2c_deprecated; 3107 struct fw_ldst_i2c { 3108 __u8 pid; 3109 __u8 did; 3110 __u8 boffset; 3111 __u8 blen; 3112 __be32 r9; 3113 __u8 data[48]; 3114 } i2c; 3115 struct fw_ldst_le { 3116 __be32 index; 3117 __be32 r9; 3118 __u8 val[33]; 3119 __u8 r11[7]; 3120 } le; 3121 } u; 3122 }; 3123 3124 #define S_FW_LDST_CMD_ADDRSPACE 0 3125 #define M_FW_LDST_CMD_ADDRSPACE 0xff 3126 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 3127 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 3128 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 3129 3130 #define S_FW_LDST_CMD_CYCLES 16 3131 #define M_FW_LDST_CMD_CYCLES 0xffff 3132 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 3133 #define G_FW_LDST_CMD_CYCLES(x) \ 3134 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 3135 3136 #define S_FW_LDST_CMD_MSG 31 3137 #define M_FW_LDST_CMD_MSG 0x1 3138 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 3139 #define G_FW_LDST_CMD_MSG(x) \ 3140 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 3141 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 3142 3143 #define S_FW_LDST_CMD_CTXTFLUSH 30 3144 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 3145 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 3146 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 3147 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 3148 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 3149 3150 #define S_FW_LDST_CMD_PADDR 8 3151 #define M_FW_LDST_CMD_PADDR 0x1f 3152 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 3153 #define G_FW_LDST_CMD_PADDR(x) \ 3154 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 3155 3156 #define S_FW_LDST_CMD_MMD 0 3157 #define M_FW_LDST_CMD_MMD 0x1f 3158 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 3159 #define G_FW_LDST_CMD_MMD(x) \ 3160 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 3161 3162 #define S_FW_LDST_CMD_FID 15 3163 #define M_FW_LDST_CMD_FID 0x1 3164 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 3165 #define G_FW_LDST_CMD_FID(x) \ 3166 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 3167 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 3168 3169 #define S_FW_LDST_CMD_CTL 0 3170 #define M_FW_LDST_CMD_CTL 0x7fff 3171 #define V_FW_LDST_CMD_CTL(x) ((x) << S_FW_LDST_CMD_CTL) 3172 #define G_FW_LDST_CMD_CTL(x) \ 3173 (((x) >> S_FW_LDST_CMD_CTL) & M_FW_LDST_CMD_CTL) 3174 3175 #define S_FW_LDST_CMD_RPLCPF 0 3176 #define M_FW_LDST_CMD_RPLCPF 0xff 3177 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 3178 #define G_FW_LDST_CMD_RPLCPF(x) \ 3179 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 3180 3181 #define S_FW_LDST_CMD_CTRL 7 3182 #define M_FW_LDST_CMD_CTRL 0x1 3183 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 3184 #define G_FW_LDST_CMD_CTRL(x) \ 3185 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 3186 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 3187 3188 #define S_FW_LDST_CMD_LC 4 3189 #define M_FW_LDST_CMD_LC 0x1 3190 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 3191 #define G_FW_LDST_CMD_LC(x) (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 3192 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 3193 3194 #define S_FW_LDST_CMD_AI 3 3195 #define M_FW_LDST_CMD_AI 0x1 3196 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 3197 #define G_FW_LDST_CMD_AI(x) (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 3198 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 3199 3200 #define S_FW_LDST_CMD_FN 0 3201 #define M_FW_LDST_CMD_FN 0x7 3202 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 3203 #define G_FW_LDST_CMD_FN(x) (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 3204 3205 #define S_FW_LDST_CMD_SELECT 4 3206 #define M_FW_LDST_CMD_SELECT 0xf 3207 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 3208 #define G_FW_LDST_CMD_SELECT(x) \ 3209 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 3210 3211 #define S_FW_LDST_CMD_NACCESS 0 3212 #define M_FW_LDST_CMD_NACCESS 0xf 3213 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 3214 #define G_FW_LDST_CMD_NACCESS(x) \ 3215 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 3216 3217 #define S_FW_LDST_CMD_NSET 14 3218 #define M_FW_LDST_CMD_NSET 0x3 3219 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 3220 #define G_FW_LDST_CMD_NSET(x) \ 3221 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 3222 3223 #define S_FW_LDST_CMD_PID 6 3224 #define M_FW_LDST_CMD_PID 0x3 3225 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 3226 #define G_FW_LDST_CMD_PID(x) \ 3227 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 3228 3229 struct fw_reset_cmd { 3230 __be32 op_to_write; 3231 __be32 retval_len16; 3232 __be32 val; 3233 __be32 halt_pkd; 3234 }; 3235 3236 #define S_FW_RESET_CMD_HALT 31 3237 #define M_FW_RESET_CMD_HALT 0x1 3238 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 3239 #define G_FW_RESET_CMD_HALT(x) \ 3240 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 3241 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 3242 3243 enum { 3244 FW_HELLO_CMD_STAGE_OS = 0, 3245 FW_HELLO_CMD_STAGE_PREOS0 = 1, 3246 FW_HELLO_CMD_STAGE_PREOS1 = 2, 3247 FW_HELLO_CMD_STAGE_POSTOS = 3, 3248 }; 3249 3250 struct fw_hello_cmd { 3251 __be32 op_to_write; 3252 __be32 retval_len16; 3253 __be32 err_to_clearinit; 3254 __be32 fwrev; 3255 }; 3256 3257 #define S_FW_HELLO_CMD_ERR 31 3258 #define M_FW_HELLO_CMD_ERR 0x1 3259 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 3260 #define G_FW_HELLO_CMD_ERR(x) \ 3261 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 3262 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 3263 3264 #define S_FW_HELLO_CMD_INIT 30 3265 #define M_FW_HELLO_CMD_INIT 0x1 3266 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 3267 #define G_FW_HELLO_CMD_INIT(x) \ 3268 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 3269 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 3270 3271 #define S_FW_HELLO_CMD_MASTERDIS 29 3272 #define M_FW_HELLO_CMD_MASTERDIS 0x1 3273 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 3274 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 3275 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 3276 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 3277 3278 #define S_FW_HELLO_CMD_MASTERFORCE 28 3279 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 3280 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 3281 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 3282 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 3283 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 3284 3285 #define S_FW_HELLO_CMD_MBMASTER 24 3286 #define M_FW_HELLO_CMD_MBMASTER 0xf 3287 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 3288 #define G_FW_HELLO_CMD_MBMASTER(x) \ 3289 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 3290 3291 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 3292 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 3293 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 3294 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 3295 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 3296 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 3297 3298 #define S_FW_HELLO_CMD_MBASYNCNOT 20 3299 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 3300 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 3301 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 3302 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 3303 3304 #define S_FW_HELLO_CMD_STAGE 17 3305 #define M_FW_HELLO_CMD_STAGE 0x7 3306 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 3307 #define G_FW_HELLO_CMD_STAGE(x) \ 3308 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 3309 3310 #define S_FW_HELLO_CMD_CLEARINIT 16 3311 #define M_FW_HELLO_CMD_CLEARINIT 0x1 3312 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 3313 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 3314 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 3315 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 3316 3317 struct fw_bye_cmd { 3318 __be32 op_to_write; 3319 __be32 retval_len16; 3320 __be64 r3; 3321 }; 3322 3323 struct fw_initialize_cmd { 3324 __be32 op_to_write; 3325 __be32 retval_len16; 3326 __be64 r3; 3327 }; 3328 3329 enum fw_caps_config_hm { 3330 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 3331 FW_CAPS_CONFIG_HM_PL = 0x00000002, 3332 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 3333 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 3334 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 3335 FW_CAPS_CONFIG_HM_TP = 0x00000020, 3336 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 3337 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 3338 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 3339 FW_CAPS_CONFIG_HM_MC = 0x00000200, 3340 FW_CAPS_CONFIG_HM_LE = 0x00000400, 3341 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 3342 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 3343 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 3344 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 3345 FW_CAPS_CONFIG_HM_MI = 0x00008000, 3346 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 3347 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 3348 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 3349 FW_CAPS_CONFIG_HM_MA = 0x00080000, 3350 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 3351 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 3352 FW_CAPS_CONFIG_HM_UART = 0x00400000, 3353 FW_CAPS_CONFIG_HM_SF = 0x00800000, 3354 }; 3355 3356 /* 3357 * The VF Register Map. 3358 * 3359 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 3360 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 3361 * the Slice to Module Map Table (see below) in the Physical Function Register 3362 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 3363 * and Offset registers in the PF Register Map. The MBDATA base address is 3364 * quite constrained as it determines the Mailbox Data addresses for both PFs 3365 * and VFs, and therefore must fit in both the VF and PF Register Maps without 3366 * overlapping other registers. 3367 */ 3368 #define FW_T4VF_SGE_BASE_ADDR 0x0000 3369 #define FW_T4VF_MPS_BASE_ADDR 0x0100 3370 #define FW_T4VF_PL_BASE_ADDR 0x0200 3371 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 3372 #define FW_T4VF_CIM_BASE_ADDR 0x0300 3373 3374 #define FW_T4VF_REGMAP_START 0x0000 3375 #define FW_T4VF_REGMAP_SIZE 0x0400 3376 3377 enum fw_caps_config_nbm { 3378 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 3379 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 3380 }; 3381 3382 enum fw_caps_config_link { 3383 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 3384 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 3385 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 3386 }; 3387 3388 enum fw_caps_config_switch { 3389 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 3390 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 3391 }; 3392 3393 enum fw_caps_config_nic { 3394 FW_CAPS_CONFIG_NIC = 0x00000001, 3395 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 3396 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 3397 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 3398 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 3399 }; 3400 3401 enum fw_caps_config_toe { 3402 FW_CAPS_CONFIG_TOE = 0x00000001, 3403 }; 3404 3405 enum fw_caps_config_rdma { 3406 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 3407 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 3408 }; 3409 3410 enum fw_caps_config_iscsi { 3411 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 3412 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 3413 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 3414 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 3415 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 3416 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 3417 }; 3418 3419 enum fw_caps_config_fcoe { 3420 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 3421 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 3422 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 3423 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 3424 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 3425 }; 3426 3427 enum fw_memtype_cf { 3428 FW_MEMTYPE_CF_EDC0 = 0x0, 3429 FW_MEMTYPE_CF_EDC1 = 0x1, 3430 FW_MEMTYPE_CF_EXTMEM = 0x2, 3431 FW_MEMTYPE_CF_FLASH = 0x4, 3432 FW_MEMTYPE_CF_INTERNAL = 0x5, 3433 }; 3434 3435 struct fw_caps_config_cmd { 3436 __be32 op_to_write; 3437 __be32 cfvalid_to_len16; 3438 __be32 r2; 3439 __be32 hwmbitmap; 3440 __be16 nbmcaps; 3441 __be16 linkcaps; 3442 __be16 switchcaps; 3443 __be16 r3; 3444 __be16 niccaps; 3445 __be16 toecaps; 3446 __be16 rdmacaps; 3447 __be16 r4; 3448 __be16 iscsicaps; 3449 __be16 fcoecaps; 3450 __be32 cfcsum; 3451 __be32 finiver; 3452 __be32 finicsum; 3453 }; 3454 3455 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 3456 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 3457 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 3458 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 3459 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 3460 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 3461 3462 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 3463 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 3464 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3465 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3466 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3467 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 3468 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3469 3470 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 3471 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 3472 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3473 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3474 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3475 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 3476 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3477 3478 /* 3479 * params command mnemonics 3480 */ 3481 enum fw_params_mnem { 3482 FW_PARAMS_MNEM_DEV = 1, /* device params */ 3483 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 3484 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 3485 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 3486 FW_PARAMS_MNEM_LAST 3487 }; 3488 3489 /* 3490 * device parameters 3491 */ 3492 enum fw_params_param_dev { 3493 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 3494 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 3495 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 3496 * allocated by the device's 3497 * Lookup Engine 3498 */ 3499 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 3500 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 3501 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 3502 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 3503 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 3504 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 3505 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 3506 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 3507 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 3508 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 3509 FW_PARAMS_PARAM_DEV_CF = 0x0D, 3510 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 3511 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 3512 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 3513 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 3514 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 3515 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 3516 */ 3517 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 3518 */ 3519 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 3520 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 3521 }; 3522 3523 /* 3524 * physical and virtual function parameters 3525 */ 3526 enum fw_params_param_pfvf { 3527 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 3528 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 3529 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 3530 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 3531 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 3532 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 3533 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 3534 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 3535 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 3536 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 3537 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 3538 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 3539 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 3540 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 3541 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 3542 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 3543 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 3544 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 3545 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 3546 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 3547 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 3548 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 3549 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 3550 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 3551 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 3552 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 3553 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 3554 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 3555 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 3556 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 3557 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 3558 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 3559 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 3560 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 3561 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 3562 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 3563 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 3564 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 3565 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 3566 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31 3567 }; 3568 3569 /* 3570 * dma queue parameters 3571 */ 3572 enum fw_params_param_dmaq { 3573 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 3574 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 3575 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 3576 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 3577 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 3578 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 3579 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13 3580 }; 3581 3582 /* 3583 * dev bypass parameters; actions and modes 3584 */ 3585 enum fw_params_param_dev_bypass { 3586 3587 /* actions 3588 */ 3589 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 3590 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 3591 3592 /* modes 3593 */ 3594 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 3595 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 3596 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 3597 }; 3598 3599 enum fw_params_phyfw_actions { 3600 FW_PARAMS_PARAM_PHYFW_DOWNLOAD = 0x00, 3601 FW_PARAMS_PARAM_PHYFW_VERSION = 0x01, 3602 }; 3603 3604 enum fw_params_param_dev_diag { 3605 FW_PARAM_DEV_DIAG_TMP = 0x00, 3606 }; 3607 3608 #define S_FW_PARAMS_MNEM 24 3609 #define M_FW_PARAMS_MNEM 0xff 3610 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 3611 #define G_FW_PARAMS_MNEM(x) \ 3612 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 3613 3614 #define S_FW_PARAMS_PARAM_X 16 3615 #define M_FW_PARAMS_PARAM_X 0xff 3616 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 3617 #define G_FW_PARAMS_PARAM_X(x) \ 3618 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 3619 3620 #define S_FW_PARAMS_PARAM_Y 8 3621 #define M_FW_PARAMS_PARAM_Y 0xff 3622 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 3623 #define G_FW_PARAMS_PARAM_Y(x) \ 3624 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 3625 3626 #define S_FW_PARAMS_PARAM_Z 0 3627 #define M_FW_PARAMS_PARAM_Z 0xff 3628 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 3629 #define G_FW_PARAMS_PARAM_Z(x) \ 3630 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 3631 3632 #define S_FW_PARAMS_PARAM_XYZ 0 3633 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 3634 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 3635 #define G_FW_PARAMS_PARAM_XYZ(x) \ 3636 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 3637 3638 #define S_FW_PARAMS_PARAM_YZ 0 3639 #define M_FW_PARAMS_PARAM_YZ 0xffff 3640 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 3641 #define G_FW_PARAMS_PARAM_YZ(x) \ 3642 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 3643 3644 struct fw_params_cmd { 3645 __be32 op_to_vfn; 3646 __be32 retval_len16; 3647 struct fw_params_param { 3648 __be32 mnem; 3649 __be32 val; 3650 } param[7]; 3651 }; 3652 3653 #define S_FW_PARAMS_CMD_PFN 8 3654 #define M_FW_PARAMS_CMD_PFN 0x7 3655 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 3656 #define G_FW_PARAMS_CMD_PFN(x) \ 3657 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 3658 3659 #define S_FW_PARAMS_CMD_VFN 0 3660 #define M_FW_PARAMS_CMD_VFN 0xff 3661 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 3662 #define G_FW_PARAMS_CMD_VFN(x) \ 3663 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 3664 3665 struct fw_pfvf_cmd { 3666 __be32 op_to_vfn; 3667 __be32 retval_len16; 3668 __be32 niqflint_niq; 3669 __be32 type_to_neq; 3670 __be32 tc_to_nexactf; 3671 __be32 r_caps_to_nethctrl; 3672 __be16 nricq; 3673 __be16 nriqp; 3674 __be32 r4; 3675 }; 3676 3677 #define S_FW_PFVF_CMD_PFN 8 3678 #define M_FW_PFVF_CMD_PFN 0x7 3679 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 3680 #define G_FW_PFVF_CMD_PFN(x) \ 3681 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 3682 3683 #define S_FW_PFVF_CMD_VFN 0 3684 #define M_FW_PFVF_CMD_VFN 0xff 3685 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 3686 #define G_FW_PFVF_CMD_VFN(x) \ 3687 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 3688 3689 #define S_FW_PFVF_CMD_NIQFLINT 20 3690 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 3691 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 3692 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 3693 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 3694 3695 #define S_FW_PFVF_CMD_NIQ 0 3696 #define M_FW_PFVF_CMD_NIQ 0xfffff 3697 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 3698 #define G_FW_PFVF_CMD_NIQ(x) \ 3699 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 3700 3701 #define S_FW_PFVF_CMD_TYPE 31 3702 #define M_FW_PFVF_CMD_TYPE 0x1 3703 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 3704 #define G_FW_PFVF_CMD_TYPE(x) \ 3705 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 3706 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 3707 3708 #define S_FW_PFVF_CMD_CMASK 24 3709 #define M_FW_PFVF_CMD_CMASK 0xf 3710 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 3711 #define G_FW_PFVF_CMD_CMASK(x) \ 3712 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 3713 3714 #define S_FW_PFVF_CMD_PMASK 20 3715 #define M_FW_PFVF_CMD_PMASK 0xf 3716 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 3717 #define G_FW_PFVF_CMD_PMASK(x) \ 3718 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 3719 3720 #define S_FW_PFVF_CMD_NEQ 0 3721 #define M_FW_PFVF_CMD_NEQ 0xfffff 3722 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 3723 #define G_FW_PFVF_CMD_NEQ(x) \ 3724 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 3725 3726 #define S_FW_PFVF_CMD_TC 24 3727 #define M_FW_PFVF_CMD_TC 0xff 3728 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 3729 #define G_FW_PFVF_CMD_TC(x) (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 3730 3731 #define S_FW_PFVF_CMD_NVI 16 3732 #define M_FW_PFVF_CMD_NVI 0xff 3733 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 3734 #define G_FW_PFVF_CMD_NVI(x) \ 3735 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 3736 3737 #define S_FW_PFVF_CMD_NEXACTF 0 3738 #define M_FW_PFVF_CMD_NEXACTF 0xffff 3739 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 3740 #define G_FW_PFVF_CMD_NEXACTF(x) \ 3741 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 3742 3743 #define S_FW_PFVF_CMD_R_CAPS 24 3744 #define M_FW_PFVF_CMD_R_CAPS 0xff 3745 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 3746 #define G_FW_PFVF_CMD_R_CAPS(x) \ 3747 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 3748 3749 #define S_FW_PFVF_CMD_WX_CAPS 16 3750 #define M_FW_PFVF_CMD_WX_CAPS 0xff 3751 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 3752 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 3753 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 3754 3755 #define S_FW_PFVF_CMD_NETHCTRL 0 3756 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 3757 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 3758 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 3759 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 3760 3761 /* 3762 * ingress queue type; the first 1K ingress queues can have associated 0, 3763 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 3764 * capabilities 3765 */ 3766 enum fw_iq_type { 3767 FW_IQ_TYPE_FL_INT_CAP, 3768 FW_IQ_TYPE_NO_FL_INT_CAP 3769 }; 3770 3771 struct fw_iq_cmd { 3772 __be32 op_to_vfn; 3773 __be32 alloc_to_len16; 3774 __be16 physiqid; 3775 __be16 iqid; 3776 __be16 fl0id; 3777 __be16 fl1id; 3778 __be32 type_to_iqandstindex; 3779 __be16 iqdroprss_to_iqesize; 3780 __be16 iqsize; 3781 __be64 iqaddr; 3782 __be32 iqns_to_fl0congen; 3783 __be16 fl0dcaen_to_fl0cidxfthresh; 3784 __be16 fl0size; 3785 __be64 fl0addr; 3786 __be32 fl1cngchmap_to_fl1congen; 3787 __be16 fl1dcaen_to_fl1cidxfthresh; 3788 __be16 fl1size; 3789 __be64 fl1addr; 3790 }; 3791 3792 #define S_FW_IQ_CMD_PFN 8 3793 #define M_FW_IQ_CMD_PFN 0x7 3794 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 3795 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 3796 3797 #define S_FW_IQ_CMD_VFN 0 3798 #define M_FW_IQ_CMD_VFN 0xff 3799 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 3800 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 3801 3802 #define S_FW_IQ_CMD_ALLOC 31 3803 #define M_FW_IQ_CMD_ALLOC 0x1 3804 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 3805 #define G_FW_IQ_CMD_ALLOC(x) \ 3806 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 3807 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 3808 3809 #define S_FW_IQ_CMD_FREE 30 3810 #define M_FW_IQ_CMD_FREE 0x1 3811 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 3812 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 3813 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 3814 3815 #define S_FW_IQ_CMD_MODIFY 29 3816 #define M_FW_IQ_CMD_MODIFY 0x1 3817 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 3818 #define G_FW_IQ_CMD_MODIFY(x) \ 3819 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 3820 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 3821 3822 #define S_FW_IQ_CMD_IQSTART 28 3823 #define M_FW_IQ_CMD_IQSTART 0x1 3824 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 3825 #define G_FW_IQ_CMD_IQSTART(x) \ 3826 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 3827 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 3828 3829 #define S_FW_IQ_CMD_IQSTOP 27 3830 #define M_FW_IQ_CMD_IQSTOP 0x1 3831 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 3832 #define G_FW_IQ_CMD_IQSTOP(x) \ 3833 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 3834 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 3835 3836 #define S_FW_IQ_CMD_TYPE 29 3837 #define M_FW_IQ_CMD_TYPE 0x7 3838 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 3839 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 3840 3841 #define S_FW_IQ_CMD_IQASYNCH 28 3842 #define M_FW_IQ_CMD_IQASYNCH 0x1 3843 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 3844 #define G_FW_IQ_CMD_IQASYNCH(x) \ 3845 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 3846 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 3847 3848 #define S_FW_IQ_CMD_VIID 16 3849 #define M_FW_IQ_CMD_VIID 0xfff 3850 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 3851 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 3852 3853 #define S_FW_IQ_CMD_IQANDST 15 3854 #define M_FW_IQ_CMD_IQANDST 0x1 3855 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 3856 #define G_FW_IQ_CMD_IQANDST(x) \ 3857 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 3858 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 3859 3860 #define S_FW_IQ_CMD_IQANUS 14 3861 #define M_FW_IQ_CMD_IQANUS 0x1 3862 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 3863 #define G_FW_IQ_CMD_IQANUS(x) \ 3864 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 3865 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 3866 3867 #define S_FW_IQ_CMD_IQANUD 12 3868 #define M_FW_IQ_CMD_IQANUD 0x3 3869 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 3870 #define G_FW_IQ_CMD_IQANUD(x) \ 3871 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 3872 3873 #define S_FW_IQ_CMD_IQANDSTINDEX 0 3874 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 3875 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 3876 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 3877 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 3878 3879 #define S_FW_IQ_CMD_IQDROPRSS 15 3880 #define M_FW_IQ_CMD_IQDROPRSS 0x1 3881 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 3882 #define G_FW_IQ_CMD_IQDROPRSS(x) \ 3883 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 3884 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 3885 3886 #define S_FW_IQ_CMD_IQGTSMODE 14 3887 #define M_FW_IQ_CMD_IQGTSMODE 0x1 3888 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 3889 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 3890 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 3891 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 3892 3893 #define S_FW_IQ_CMD_IQPCIECH 12 3894 #define M_FW_IQ_CMD_IQPCIECH 0x3 3895 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 3896 #define G_FW_IQ_CMD_IQPCIECH(x) \ 3897 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 3898 3899 #define S_FW_IQ_CMD_IQDCAEN 11 3900 #define M_FW_IQ_CMD_IQDCAEN 0x1 3901 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 3902 #define G_FW_IQ_CMD_IQDCAEN(x) \ 3903 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 3904 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 3905 3906 #define S_FW_IQ_CMD_IQDCACPU 6 3907 #define M_FW_IQ_CMD_IQDCACPU 0x1f 3908 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 3909 #define G_FW_IQ_CMD_IQDCACPU(x) \ 3910 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 3911 3912 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 3913 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 3914 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 3915 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 3916 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 3917 3918 #define S_FW_IQ_CMD_IQO 3 3919 #define M_FW_IQ_CMD_IQO 0x1 3920 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 3921 #define G_FW_IQ_CMD_IQO(x) (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 3922 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 3923 3924 #define S_FW_IQ_CMD_IQCPRIO 2 3925 #define M_FW_IQ_CMD_IQCPRIO 0x1 3926 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 3927 #define G_FW_IQ_CMD_IQCPRIO(x) \ 3928 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 3929 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 3930 3931 #define S_FW_IQ_CMD_IQESIZE 0 3932 #define M_FW_IQ_CMD_IQESIZE 0x3 3933 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 3934 #define G_FW_IQ_CMD_IQESIZE(x) \ 3935 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 3936 3937 #define S_FW_IQ_CMD_IQNS 31 3938 #define M_FW_IQ_CMD_IQNS 0x1 3939 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 3940 #define G_FW_IQ_CMD_IQNS(x) (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 3941 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 3942 3943 #define S_FW_IQ_CMD_IQRO 30 3944 #define M_FW_IQ_CMD_IQRO 0x1 3945 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 3946 #define G_FW_IQ_CMD_IQRO(x) (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 3947 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 3948 3949 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 3950 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 3951 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 3952 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 3953 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 3954 3955 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 3956 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 3957 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 3958 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 3959 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 3960 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 3961 3962 #define S_FW_IQ_CMD_IQFLINTISCSIC 26 3963 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 3964 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 3965 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 3966 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 3967 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 3968 3969 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 3970 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 3971 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 3972 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 3973 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 3974 3975 #define S_FW_IQ_CMD_FL0CACHELOCK 15 3976 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 3977 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 3978 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 3979 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 3980 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 3981 3982 #define S_FW_IQ_CMD_FL0DBP 14 3983 #define M_FW_IQ_CMD_FL0DBP 0x1 3984 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 3985 #define G_FW_IQ_CMD_FL0DBP(x) \ 3986 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 3987 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 3988 3989 #define S_FW_IQ_CMD_FL0DATANS 13 3990 #define M_FW_IQ_CMD_FL0DATANS 0x1 3991 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 3992 #define G_FW_IQ_CMD_FL0DATANS(x) \ 3993 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 3994 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 3995 3996 #define S_FW_IQ_CMD_FL0DATARO 12 3997 #define M_FW_IQ_CMD_FL0DATARO 0x1 3998 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 3999 #define G_FW_IQ_CMD_FL0DATARO(x) \ 4000 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 4001 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 4002 4003 #define S_FW_IQ_CMD_FL0CONGCIF 11 4004 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 4005 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 4006 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 4007 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 4008 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 4009 4010 #define S_FW_IQ_CMD_FL0ONCHIP 10 4011 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 4012 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 4013 #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 4014 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 4015 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 4016 4017 #define S_FW_IQ_CMD_FL0STATUSPGNS 9 4018 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 4019 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 4020 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 4021 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 4022 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 4023 4024 #define S_FW_IQ_CMD_FL0STATUSPGRO 8 4025 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 4026 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 4027 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 4028 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 4029 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 4030 4031 #define S_FW_IQ_CMD_FL0FETCHNS 7 4032 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 4033 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 4034 #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 4035 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 4036 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 4037 4038 #define S_FW_IQ_CMD_FL0FETCHRO 6 4039 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 4040 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 4041 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 4042 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 4043 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 4044 4045 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 4046 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 4047 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 4048 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 4049 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 4050 4051 #define S_FW_IQ_CMD_FL0CPRIO 3 4052 #define M_FW_IQ_CMD_FL0CPRIO 0x1 4053 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 4054 #define G_FW_IQ_CMD_FL0CPRIO(x) \ 4055 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 4056 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 4057 4058 #define S_FW_IQ_CMD_FL0PADEN 2 4059 #define M_FW_IQ_CMD_FL0PADEN 0x1 4060 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 4061 #define G_FW_IQ_CMD_FL0PADEN(x) \ 4062 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 4063 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 4064 4065 #define S_FW_IQ_CMD_FL0PACKEN 1 4066 #define M_FW_IQ_CMD_FL0PACKEN 0x1 4067 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 4068 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 4069 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 4070 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 4071 4072 #define S_FW_IQ_CMD_FL0CONGEN 0 4073 #define M_FW_IQ_CMD_FL0CONGEN 0x1 4074 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 4075 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 4076 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 4077 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 4078 4079 #define S_FW_IQ_CMD_FL0DCAEN 15 4080 #define M_FW_IQ_CMD_FL0DCAEN 0x1 4081 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 4082 #define G_FW_IQ_CMD_FL0DCAEN(x) \ 4083 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 4084 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 4085 4086 #define S_FW_IQ_CMD_FL0DCACPU 10 4087 #define M_FW_IQ_CMD_FL0DCACPU 0x1f 4088 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 4089 #define G_FW_IQ_CMD_FL0DCACPU(x) \ 4090 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 4091 4092 #define S_FW_IQ_CMD_FL0FBMIN 7 4093 #define M_FW_IQ_CMD_FL0FBMIN 0x7 4094 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 4095 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 4096 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 4097 4098 #define S_FW_IQ_CMD_FL0FBMAX 4 4099 #define M_FW_IQ_CMD_FL0FBMAX 0x7 4100 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 4101 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 4102 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 4103 4104 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 4105 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 4106 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 4107 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 4108 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 4109 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 4110 4111 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 4112 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 4113 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 4114 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 4115 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 4116 4117 #define S_FW_IQ_CMD_FL1CNGCHMAP 20 4118 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 4119 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 4120 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 4121 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 4122 4123 #define S_FW_IQ_CMD_FL1CACHELOCK 15 4124 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 4125 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 4126 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 4127 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 4128 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 4129 4130 #define S_FW_IQ_CMD_FL1DBP 14 4131 #define M_FW_IQ_CMD_FL1DBP 0x1 4132 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 4133 #define G_FW_IQ_CMD_FL1DBP(x) \ 4134 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 4135 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 4136 4137 #define S_FW_IQ_CMD_FL1DATANS 13 4138 #define M_FW_IQ_CMD_FL1DATANS 0x1 4139 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 4140 #define G_FW_IQ_CMD_FL1DATANS(x) \ 4141 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 4142 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 4143 4144 #define S_FW_IQ_CMD_FL1DATARO 12 4145 #define M_FW_IQ_CMD_FL1DATARO 0x1 4146 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 4147 #define G_FW_IQ_CMD_FL1DATARO(x) \ 4148 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 4149 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 4150 4151 #define S_FW_IQ_CMD_FL1CONGCIF 11 4152 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 4153 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 4154 #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 4155 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 4156 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 4157 4158 #define S_FW_IQ_CMD_FL1ONCHIP 10 4159 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 4160 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 4161 #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 4162 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 4163 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 4164 4165 #define S_FW_IQ_CMD_FL1STATUSPGNS 9 4166 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 4167 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 4168 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 4169 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 4170 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 4171 4172 #define S_FW_IQ_CMD_FL1STATUSPGRO 8 4173 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 4174 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 4175 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 4176 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 4177 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 4178 4179 #define S_FW_IQ_CMD_FL1FETCHNS 7 4180 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 4181 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 4182 #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 4183 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 4184 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 4185 4186 #define S_FW_IQ_CMD_FL1FETCHRO 6 4187 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 4188 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 4189 #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 4190 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 4191 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 4192 4193 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 4194 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 4195 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 4196 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 4197 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 4198 4199 #define S_FW_IQ_CMD_FL1CPRIO 3 4200 #define M_FW_IQ_CMD_FL1CPRIO 0x1 4201 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 4202 #define G_FW_IQ_CMD_FL1CPRIO(x) \ 4203 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 4204 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 4205 4206 #define S_FW_IQ_CMD_FL1PADEN 2 4207 #define M_FW_IQ_CMD_FL1PADEN 0x1 4208 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 4209 #define G_FW_IQ_CMD_FL1PADEN(x) \ 4210 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 4211 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 4212 4213 #define S_FW_IQ_CMD_FL1PACKEN 1 4214 #define M_FW_IQ_CMD_FL1PACKEN 0x1 4215 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 4216 #define G_FW_IQ_CMD_FL1PACKEN(x) \ 4217 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 4218 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 4219 4220 #define S_FW_IQ_CMD_FL1CONGEN 0 4221 #define M_FW_IQ_CMD_FL1CONGEN 0x1 4222 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 4223 #define G_FW_IQ_CMD_FL1CONGEN(x) \ 4224 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 4225 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 4226 4227 #define S_FW_IQ_CMD_FL1DCAEN 15 4228 #define M_FW_IQ_CMD_FL1DCAEN 0x1 4229 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 4230 #define G_FW_IQ_CMD_FL1DCAEN(x) \ 4231 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 4232 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 4233 4234 #define S_FW_IQ_CMD_FL1DCACPU 10 4235 #define M_FW_IQ_CMD_FL1DCACPU 0x1f 4236 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 4237 #define G_FW_IQ_CMD_FL1DCACPU(x) \ 4238 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 4239 4240 #define S_FW_IQ_CMD_FL1FBMIN 7 4241 #define M_FW_IQ_CMD_FL1FBMIN 0x7 4242 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 4243 #define G_FW_IQ_CMD_FL1FBMIN(x) \ 4244 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 4245 4246 #define S_FW_IQ_CMD_FL1FBMAX 4 4247 #define M_FW_IQ_CMD_FL1FBMAX 0x7 4248 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 4249 #define G_FW_IQ_CMD_FL1FBMAX(x) \ 4250 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 4251 4252 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 4253 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 4254 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 4255 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 4256 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 4257 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 4258 4259 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 4260 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 4261 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 4262 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 4263 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 4264 4265 struct fw_eq_mngt_cmd { 4266 __be32 op_to_vfn; 4267 __be32 alloc_to_len16; 4268 __be32 cmpliqid_eqid; 4269 __be32 physeqid_pkd; 4270 __be32 fetchszm_to_iqid; 4271 __be32 dcaen_to_eqsize; 4272 __be64 eqaddr; 4273 }; 4274 4275 #define S_FW_EQ_MNGT_CMD_PFN 8 4276 #define M_FW_EQ_MNGT_CMD_PFN 0x7 4277 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 4278 #define G_FW_EQ_MNGT_CMD_PFN(x) \ 4279 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 4280 4281 #define S_FW_EQ_MNGT_CMD_VFN 0 4282 #define M_FW_EQ_MNGT_CMD_VFN 0xff 4283 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 4284 #define G_FW_EQ_MNGT_CMD_VFN(x) \ 4285 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 4286 4287 #define S_FW_EQ_MNGT_CMD_ALLOC 31 4288 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 4289 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 4290 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 4291 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 4292 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 4293 4294 #define S_FW_EQ_MNGT_CMD_FREE 30 4295 #define M_FW_EQ_MNGT_CMD_FREE 0x1 4296 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 4297 #define G_FW_EQ_MNGT_CMD_FREE(x) \ 4298 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 4299 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 4300 4301 #define S_FW_EQ_MNGT_CMD_MODIFY 29 4302 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 4303 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 4304 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 4305 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 4306 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 4307 4308 #define S_FW_EQ_MNGT_CMD_EQSTART 28 4309 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 4310 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 4311 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 4312 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 4313 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 4314 4315 #define S_FW_EQ_MNGT_CMD_EQSTOP 27 4316 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 4317 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 4318 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 4319 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 4320 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 4321 4322 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 4323 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 4324 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 4325 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 4326 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 4327 4328 #define S_FW_EQ_MNGT_CMD_EQID 0 4329 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 4330 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 4331 #define G_FW_EQ_MNGT_CMD_EQID(x) \ 4332 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 4333 4334 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 4335 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 4336 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 4337 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 4338 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 4339 4340 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 4341 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 4342 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 4343 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 4344 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 4345 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 4346 4347 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 4348 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 4349 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 4350 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 4351 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 4352 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 4353 4354 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 4355 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 4356 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 4357 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 4358 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 4359 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 4360 4361 #define S_FW_EQ_MNGT_CMD_FETCHNS 23 4362 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 4363 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 4364 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 4365 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 4366 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 4367 4368 #define S_FW_EQ_MNGT_CMD_FETCHRO 22 4369 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 4370 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 4371 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 4372 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 4373 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 4374 4375 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 4376 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 4377 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 4378 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 4379 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 4380 4381 #define S_FW_EQ_MNGT_CMD_CPRIO 19 4382 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 4383 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 4384 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 4385 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 4386 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 4387 4388 #define S_FW_EQ_MNGT_CMD_ONCHIP 18 4389 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 4390 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 4391 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 4392 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 4393 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 4394 4395 #define S_FW_EQ_MNGT_CMD_PCIECHN 16 4396 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 4397 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 4398 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 4399 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 4400 4401 #define S_FW_EQ_MNGT_CMD_IQID 0 4402 #define M_FW_EQ_MNGT_CMD_IQID 0xffff 4403 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 4404 #define G_FW_EQ_MNGT_CMD_IQID(x) \ 4405 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 4406 4407 #define S_FW_EQ_MNGT_CMD_DCAEN 31 4408 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 4409 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 4410 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 4411 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 4412 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 4413 4414 #define S_FW_EQ_MNGT_CMD_DCACPU 26 4415 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 4416 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 4417 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 4418 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 4419 4420 #define S_FW_EQ_MNGT_CMD_FBMIN 23 4421 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 4422 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 4423 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 4424 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 4425 4426 #define S_FW_EQ_MNGT_CMD_FBMAX 20 4427 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 4428 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 4429 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 4430 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 4431 4432 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 4433 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 4434 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4435 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4436 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4437 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4438 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 4439 4440 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 4441 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 4442 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4443 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 4444 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4445 4446 #define S_FW_EQ_MNGT_CMD_EQSIZE 0 4447 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 4448 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 4449 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 4450 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 4451 4452 struct fw_eq_eth_cmd { 4453 __be32 op_to_vfn; 4454 __be32 alloc_to_len16; 4455 __be32 eqid_pkd; 4456 __be32 physeqid_pkd; 4457 __be32 fetchszm_to_iqid; 4458 __be32 dcaen_to_eqsize; 4459 __be64 eqaddr; 4460 __be32 viid_pkd; 4461 __be32 r8_lo; 4462 __be64 r9; 4463 }; 4464 4465 #define S_FW_EQ_ETH_CMD_PFN 8 4466 #define M_FW_EQ_ETH_CMD_PFN 0x7 4467 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 4468 #define G_FW_EQ_ETH_CMD_PFN(x) \ 4469 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 4470 4471 #define S_FW_EQ_ETH_CMD_VFN 0 4472 #define M_FW_EQ_ETH_CMD_VFN 0xff 4473 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 4474 #define G_FW_EQ_ETH_CMD_VFN(x) \ 4475 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 4476 4477 #define S_FW_EQ_ETH_CMD_ALLOC 31 4478 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 4479 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 4480 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 4481 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 4482 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 4483 4484 #define S_FW_EQ_ETH_CMD_FREE 30 4485 #define M_FW_EQ_ETH_CMD_FREE 0x1 4486 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 4487 #define G_FW_EQ_ETH_CMD_FREE(x) \ 4488 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 4489 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 4490 4491 #define S_FW_EQ_ETH_CMD_MODIFY 29 4492 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 4493 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 4494 #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 4495 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 4496 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 4497 4498 #define S_FW_EQ_ETH_CMD_EQSTART 28 4499 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 4500 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 4501 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 4502 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 4503 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 4504 4505 #define S_FW_EQ_ETH_CMD_EQSTOP 27 4506 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 4507 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 4508 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 4509 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 4510 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 4511 4512 #define S_FW_EQ_ETH_CMD_EQID 0 4513 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 4514 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 4515 #define G_FW_EQ_ETH_CMD_EQID(x) \ 4516 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 4517 4518 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 4519 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 4520 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 4521 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 4522 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 4523 4524 #define S_FW_EQ_ETH_CMD_FETCHSZM 26 4525 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 4526 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 4527 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 4528 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 4529 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 4530 4531 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 4532 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 4533 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 4534 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 4535 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 4536 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 4537 4538 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 4539 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 4540 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 4541 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 4542 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 4543 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 4544 4545 #define S_FW_EQ_ETH_CMD_FETCHNS 23 4546 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 4547 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 4548 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 4549 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 4550 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 4551 4552 #define S_FW_EQ_ETH_CMD_FETCHRO 22 4553 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 4554 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 4555 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 4556 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 4557 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 4558 4559 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 4560 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 4561 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 4562 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 4563 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 4564 4565 #define S_FW_EQ_ETH_CMD_CPRIO 19 4566 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 4567 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 4568 #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 4569 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 4570 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 4571 4572 #define S_FW_EQ_ETH_CMD_ONCHIP 18 4573 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 4574 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 4575 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 4576 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 4577 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 4578 4579 #define S_FW_EQ_ETH_CMD_PCIECHN 16 4580 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 4581 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 4582 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 4583 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 4584 4585 #define S_FW_EQ_ETH_CMD_IQID 0 4586 #define M_FW_EQ_ETH_CMD_IQID 0xffff 4587 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 4588 #define G_FW_EQ_ETH_CMD_IQID(x) \ 4589 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 4590 4591 #define S_FW_EQ_ETH_CMD_DCAEN 31 4592 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 4593 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 4594 #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 4595 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 4596 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 4597 4598 #define S_FW_EQ_ETH_CMD_DCACPU 26 4599 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 4600 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 4601 #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 4602 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 4603 4604 #define S_FW_EQ_ETH_CMD_FBMIN 23 4605 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 4606 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 4607 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 4608 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 4609 4610 #define S_FW_EQ_ETH_CMD_FBMAX 20 4611 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 4612 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 4613 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 4614 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 4615 4616 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 4617 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 4618 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 4619 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 4620 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 4621 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 4622 4623 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 4624 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 4625 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 4626 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 4627 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 4628 4629 #define S_FW_EQ_ETH_CMD_EQSIZE 0 4630 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 4631 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 4632 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 4633 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 4634 4635 #define S_FW_EQ_ETH_CMD_VIID 16 4636 #define M_FW_EQ_ETH_CMD_VIID 0xfff 4637 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 4638 #define G_FW_EQ_ETH_CMD_VIID(x) \ 4639 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 4640 4641 struct fw_eq_ctrl_cmd { 4642 __be32 op_to_vfn; 4643 __be32 alloc_to_len16; 4644 __be32 cmpliqid_eqid; 4645 __be32 physeqid_pkd; 4646 __be32 fetchszm_to_iqid; 4647 __be32 dcaen_to_eqsize; 4648 __be64 eqaddr; 4649 }; 4650 4651 #define S_FW_EQ_CTRL_CMD_PFN 8 4652 #define M_FW_EQ_CTRL_CMD_PFN 0x7 4653 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 4654 #define G_FW_EQ_CTRL_CMD_PFN(x) \ 4655 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 4656 4657 #define S_FW_EQ_CTRL_CMD_VFN 0 4658 #define M_FW_EQ_CTRL_CMD_VFN 0xff 4659 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 4660 #define G_FW_EQ_CTRL_CMD_VFN(x) \ 4661 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 4662 4663 #define S_FW_EQ_CTRL_CMD_ALLOC 31 4664 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 4665 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 4666 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 4667 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 4668 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 4669 4670 #define S_FW_EQ_CTRL_CMD_FREE 30 4671 #define M_FW_EQ_CTRL_CMD_FREE 0x1 4672 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 4673 #define G_FW_EQ_CTRL_CMD_FREE(x) \ 4674 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 4675 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 4676 4677 #define S_FW_EQ_CTRL_CMD_MODIFY 29 4678 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 4679 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 4680 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 4681 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 4682 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 4683 4684 #define S_FW_EQ_CTRL_CMD_EQSTART 28 4685 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 4686 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 4687 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 4688 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 4689 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 4690 4691 #define S_FW_EQ_CTRL_CMD_EQSTOP 27 4692 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 4693 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 4694 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 4695 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 4696 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 4697 4698 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 4699 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 4700 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 4701 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 4702 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 4703 4704 #define S_FW_EQ_CTRL_CMD_EQID 0 4705 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 4706 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 4707 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 4708 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 4709 4710 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 4711 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 4712 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 4713 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 4714 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 4715 4716 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 4717 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 4718 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 4719 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 4720 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 4721 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 4722 4723 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 4724 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 4725 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 4726 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 4727 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 4728 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 4729 4730 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 4731 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 4732 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 4733 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 4734 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 4735 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 4736 4737 #define S_FW_EQ_CTRL_CMD_FETCHNS 23 4738 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 4739 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 4740 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 4741 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 4742 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 4743 4744 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 4745 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 4746 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 4747 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 4748 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 4749 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 4750 4751 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 4752 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 4753 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 4754 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 4755 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 4756 4757 #define S_FW_EQ_CTRL_CMD_CPRIO 19 4758 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 4759 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 4760 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 4761 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 4762 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 4763 4764 #define S_FW_EQ_CTRL_CMD_ONCHIP 18 4765 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 4766 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 4767 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 4768 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 4769 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 4770 4771 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 4772 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 4773 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 4774 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 4775 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 4776 4777 #define S_FW_EQ_CTRL_CMD_IQID 0 4778 #define M_FW_EQ_CTRL_CMD_IQID 0xffff 4779 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 4780 #define G_FW_EQ_CTRL_CMD_IQID(x) \ 4781 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 4782 4783 #define S_FW_EQ_CTRL_CMD_DCAEN 31 4784 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 4785 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 4786 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 4787 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 4788 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 4789 4790 #define S_FW_EQ_CTRL_CMD_DCACPU 26 4791 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 4792 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 4793 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 4794 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 4795 4796 #define S_FW_EQ_CTRL_CMD_FBMIN 23 4797 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 4798 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 4799 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 4800 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 4801 4802 #define S_FW_EQ_CTRL_CMD_FBMAX 20 4803 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 4804 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 4805 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 4806 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 4807 4808 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 4809 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 4810 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 4811 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 4812 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 4813 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 4814 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 4815 4816 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 4817 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 4818 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 4819 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 4820 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 4821 4822 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 4823 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 4824 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 4825 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 4826 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 4827 4828 struct fw_eq_ofld_cmd { 4829 __be32 op_to_vfn; 4830 __be32 alloc_to_len16; 4831 __be32 eqid_pkd; 4832 __be32 physeqid_pkd; 4833 __be32 fetchszm_to_iqid; 4834 __be32 dcaen_to_eqsize; 4835 __be64 eqaddr; 4836 }; 4837 4838 #define S_FW_EQ_OFLD_CMD_PFN 8 4839 #define M_FW_EQ_OFLD_CMD_PFN 0x7 4840 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 4841 #define G_FW_EQ_OFLD_CMD_PFN(x) \ 4842 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 4843 4844 #define S_FW_EQ_OFLD_CMD_VFN 0 4845 #define M_FW_EQ_OFLD_CMD_VFN 0xff 4846 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 4847 #define G_FW_EQ_OFLD_CMD_VFN(x) \ 4848 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 4849 4850 #define S_FW_EQ_OFLD_CMD_ALLOC 31 4851 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 4852 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 4853 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 4854 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 4855 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 4856 4857 #define S_FW_EQ_OFLD_CMD_FREE 30 4858 #define M_FW_EQ_OFLD_CMD_FREE 0x1 4859 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 4860 #define G_FW_EQ_OFLD_CMD_FREE(x) \ 4861 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 4862 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 4863 4864 #define S_FW_EQ_OFLD_CMD_MODIFY 29 4865 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 4866 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 4867 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 4868 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 4869 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 4870 4871 #define S_FW_EQ_OFLD_CMD_EQSTART 28 4872 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 4873 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 4874 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 4875 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 4876 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 4877 4878 #define S_FW_EQ_OFLD_CMD_EQSTOP 27 4879 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 4880 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 4881 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 4882 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 4883 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 4884 4885 #define S_FW_EQ_OFLD_CMD_EQID 0 4886 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 4887 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 4888 #define G_FW_EQ_OFLD_CMD_EQID(x) \ 4889 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 4890 4891 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 4892 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 4893 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 4894 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 4895 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 4896 4897 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 4898 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 4899 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 4900 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 4901 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 4902 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 4903 4904 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 4905 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 4906 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 4907 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 4908 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 4909 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 4910 4911 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 4912 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 4913 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 4914 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 4915 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 4916 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 4917 4918 #define S_FW_EQ_OFLD_CMD_FETCHNS 23 4919 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 4920 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 4921 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 4922 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 4923 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 4924 4925 #define S_FW_EQ_OFLD_CMD_FETCHRO 22 4926 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 4927 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 4928 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 4929 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 4930 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 4931 4932 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 4933 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 4934 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 4935 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 4936 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 4937 4938 #define S_FW_EQ_OFLD_CMD_CPRIO 19 4939 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 4940 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 4941 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 4942 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 4943 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 4944 4945 #define S_FW_EQ_OFLD_CMD_ONCHIP 18 4946 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 4947 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 4948 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 4949 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 4950 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 4951 4952 #define S_FW_EQ_OFLD_CMD_PCIECHN 16 4953 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 4954 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 4955 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 4956 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 4957 4958 #define S_FW_EQ_OFLD_CMD_IQID 0 4959 #define M_FW_EQ_OFLD_CMD_IQID 0xffff 4960 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 4961 #define G_FW_EQ_OFLD_CMD_IQID(x) \ 4962 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 4963 4964 #define S_FW_EQ_OFLD_CMD_DCAEN 31 4965 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 4966 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 4967 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 4968 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 4969 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 4970 4971 #define S_FW_EQ_OFLD_CMD_DCACPU 26 4972 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 4973 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 4974 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 4975 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 4976 4977 #define S_FW_EQ_OFLD_CMD_FBMIN 23 4978 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 4979 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 4980 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 4981 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 4982 4983 #define S_FW_EQ_OFLD_CMD_FBMAX 20 4984 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 4985 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 4986 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 4987 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 4988 4989 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 4990 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 4991 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 4992 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 4993 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 4994 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 4995 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 4996 4997 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 4998 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 4999 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 5000 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 5001 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 5002 5003 #define S_FW_EQ_OFLD_CMD_EQSIZE 0 5004 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 5005 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 5006 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 5007 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 5008 5009 /* Macros for VIID parsing: 5010 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 5011 #define S_FW_VIID_PFN 8 5012 #define M_FW_VIID_PFN 0x7 5013 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 5014 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 5015 5016 #define S_FW_VIID_VIVLD 7 5017 #define M_FW_VIID_VIVLD 0x1 5018 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 5019 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 5020 5021 #define S_FW_VIID_VIN 0 5022 #define M_FW_VIID_VIN 0x7F 5023 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 5024 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 5025 5026 enum fw_vi_func { 5027 FW_VI_FUNC_ETH, 5028 FW_VI_FUNC_OFLD, 5029 FW_VI_FUNC_IWARP, 5030 FW_VI_FUNC_OPENISCSI, 5031 FW_VI_FUNC_OPENFCOE, 5032 FW_VI_FUNC_FOISCSI, 5033 FW_VI_FUNC_FOFCOE, 5034 FW_VI_FUNC_FW, 5035 }; 5036 5037 struct fw_vi_cmd { 5038 __be32 op_to_vfn; 5039 __be32 alloc_to_len16; 5040 __be16 type_to_viid; 5041 __u8 mac[6]; 5042 __u8 portid_pkd; 5043 __u8 nmac; 5044 __u8 nmac0[6]; 5045 __be16 norss_rsssize; 5046 __u8 nmac1[6]; 5047 __be16 idsiiq_pkd; 5048 __u8 nmac2[6]; 5049 __be16 idseiq_pkd; 5050 __u8 nmac3[6]; 5051 __be64 r9; 5052 __be64 r10; 5053 }; 5054 5055 #define S_FW_VI_CMD_PFN 8 5056 #define M_FW_VI_CMD_PFN 0x7 5057 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 5058 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 5059 5060 #define S_FW_VI_CMD_VFN 0 5061 #define M_FW_VI_CMD_VFN 0xff 5062 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 5063 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 5064 5065 #define S_FW_VI_CMD_ALLOC 31 5066 #define M_FW_VI_CMD_ALLOC 0x1 5067 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 5068 #define G_FW_VI_CMD_ALLOC(x) \ 5069 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 5070 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 5071 5072 #define S_FW_VI_CMD_FREE 30 5073 #define M_FW_VI_CMD_FREE 0x1 5074 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 5075 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 5076 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 5077 5078 #define S_FW_VI_CMD_TYPE 15 5079 #define M_FW_VI_CMD_TYPE 0x1 5080 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 5081 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 5082 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 5083 5084 #define S_FW_VI_CMD_FUNC 12 5085 #define M_FW_VI_CMD_FUNC 0x7 5086 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 5087 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 5088 5089 #define S_FW_VI_CMD_VIID 0 5090 #define M_FW_VI_CMD_VIID 0xfff 5091 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 5092 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 5093 5094 #define S_FW_VI_CMD_PORTID 4 5095 #define M_FW_VI_CMD_PORTID 0xf 5096 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 5097 #define G_FW_VI_CMD_PORTID(x) \ 5098 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 5099 5100 #define S_FW_VI_CMD_NORSS 11 5101 #define M_FW_VI_CMD_NORSS 0x1 5102 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 5103 #define G_FW_VI_CMD_NORSS(x) \ 5104 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 5105 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 5106 5107 #define S_FW_VI_CMD_RSSSIZE 0 5108 #define M_FW_VI_CMD_RSSSIZE 0x7ff 5109 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 5110 #define G_FW_VI_CMD_RSSSIZE(x) \ 5111 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 5112 5113 #define S_FW_VI_CMD_IDSIIQ 0 5114 #define M_FW_VI_CMD_IDSIIQ 0x3ff 5115 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 5116 #define G_FW_VI_CMD_IDSIIQ(x) \ 5117 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 5118 5119 #define S_FW_VI_CMD_IDSEIQ 0 5120 #define M_FW_VI_CMD_IDSEIQ 0x3ff 5121 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 5122 #define G_FW_VI_CMD_IDSEIQ(x) \ 5123 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 5124 5125 /* Special VI_MAC command index ids */ 5126 #define FW_VI_MAC_ADD_MAC 0x3FF 5127 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 5128 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 5129 5130 enum fw_vi_mac_smac { 5131 FW_VI_MAC_MPS_TCAM_ENTRY, 5132 FW_VI_MAC_MPS_TCAM_ONLY, 5133 FW_VI_MAC_SMT_ONLY, 5134 FW_VI_MAC_SMT_AND_MPSTCAM 5135 }; 5136 5137 enum fw_vi_mac_result { 5138 FW_VI_MAC_R_SUCCESS, 5139 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 5140 FW_VI_MAC_R_SMAC_FAIL, 5141 FW_VI_MAC_R_F_ACL_CHECK 5142 }; 5143 5144 struct fw_vi_mac_cmd { 5145 __be32 op_to_viid; 5146 __be32 freemacs_to_len16; 5147 union fw_vi_mac { 5148 struct fw_vi_mac_exact { 5149 __be16 valid_to_idx; 5150 __u8 macaddr[6]; 5151 } exact[7]; 5152 struct fw_vi_mac_hash { 5153 __be64 hashvec; 5154 } hash; 5155 } u; 5156 }; 5157 5158 #define S_FW_VI_MAC_CMD_VIID 0 5159 #define M_FW_VI_MAC_CMD_VIID 0xfff 5160 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 5161 #define G_FW_VI_MAC_CMD_VIID(x) \ 5162 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 5163 5164 #define S_FW_VI_MAC_CMD_FREEMACS 31 5165 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 5166 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 5167 #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 5168 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 5169 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 5170 5171 #define S_FW_VI_MAC_CMD_HASHVECEN 23 5172 #define M_FW_VI_MAC_CMD_HASHVECEN 0x1 5173 #define V_FW_VI_MAC_CMD_HASHVECEN(x) ((x) << S_FW_VI_MAC_CMD_HASHVECEN) 5174 #define G_FW_VI_MAC_CMD_HASHVECEN(x) \ 5175 (((x) >> S_FW_VI_MAC_CMD_HASHVECEN) & M_FW_VI_MAC_CMD_HASHVECEN) 5176 #define F_FW_VI_MAC_CMD_HASHVECEN V_FW_VI_MAC_CMD_HASHVECEN(1U) 5177 5178 #define S_FW_VI_MAC_CMD_HASHUNIEN 22 5179 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 5180 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 5181 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 5182 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 5183 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 5184 5185 #define S_FW_VI_MAC_CMD_VALID 15 5186 #define M_FW_VI_MAC_CMD_VALID 0x1 5187 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 5188 #define G_FW_VI_MAC_CMD_VALID(x) \ 5189 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 5190 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 5191 5192 #define S_FW_VI_MAC_CMD_PRIO 12 5193 #define M_FW_VI_MAC_CMD_PRIO 0x7 5194 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 5195 #define G_FW_VI_MAC_CMD_PRIO(x) \ 5196 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 5197 5198 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 5199 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 5200 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 5201 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 5202 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 5203 5204 #define S_FW_VI_MAC_CMD_IDX 0 5205 #define M_FW_VI_MAC_CMD_IDX 0x3ff 5206 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 5207 #define G_FW_VI_MAC_CMD_IDX(x) \ 5208 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 5209 5210 /* T4 max MTU supported */ 5211 #define T4_MAX_MTU_SUPPORTED 9600 5212 #define FW_RXMODE_MTU_NO_CHG 65535 5213 5214 struct fw_vi_rxmode_cmd { 5215 __be32 op_to_viid; 5216 __be32 retval_len16; 5217 __be32 mtu_to_vlanexen; 5218 __be32 r4_lo; 5219 }; 5220 5221 #define S_FW_VI_RXMODE_CMD_VIID 0 5222 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 5223 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 5224 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 5225 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 5226 5227 #define S_FW_VI_RXMODE_CMD_MTU 16 5228 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 5229 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 5230 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 5231 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 5232 5233 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 5234 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 5235 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 5236 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 5237 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 5238 5239 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 5240 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 5241 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5242 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 5243 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5244 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 5245 5246 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 5247 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 5248 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5249 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 5250 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5251 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 5252 5253 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 5254 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 5255 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 5256 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 5257 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 5258 5259 struct fw_vi_enable_cmd { 5260 __be32 op_to_viid; 5261 __be32 ien_to_len16; 5262 __be16 blinkdur; 5263 __be16 r3; 5264 __be32 r4; 5265 }; 5266 5267 #define S_FW_VI_ENABLE_CMD_VIID 0 5268 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 5269 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 5270 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 5271 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 5272 5273 #define S_FW_VI_ENABLE_CMD_IEN 31 5274 #define M_FW_VI_ENABLE_CMD_IEN 0x1 5275 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 5276 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 5277 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 5278 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 5279 5280 #define S_FW_VI_ENABLE_CMD_EEN 30 5281 #define M_FW_VI_ENABLE_CMD_EEN 0x1 5282 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 5283 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 5284 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 5285 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 5286 5287 #define S_FW_VI_ENABLE_CMD_LED 29 5288 #define M_FW_VI_ENABLE_CMD_LED 0x1 5289 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 5290 #define G_FW_VI_ENABLE_CMD_LED(x) \ 5291 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 5292 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 5293 5294 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 5295 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 5296 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 5297 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 5298 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 5299 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 5300 5301 /* VI VF stats offset definitions */ 5302 #define VI_VF_NUM_STATS 16 5303 enum fw_vi_stats_vf_index { 5304 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 5305 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 5306 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 5307 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 5308 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 5309 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 5310 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 5311 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 5312 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 5313 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 5314 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 5315 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 5316 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 5317 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 5318 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 5319 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 5320 }; 5321 5322 /* VI PF stats offset definitions */ 5323 #define VI_PF_NUM_STATS 17 5324 enum fw_vi_stats_pf_index { 5325 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 5326 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 5327 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 5328 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 5329 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 5330 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 5331 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 5332 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 5333 FW_VI_PF_STAT_RX_BYTES_IX, 5334 FW_VI_PF_STAT_RX_FRAMES_IX, 5335 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 5336 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 5337 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 5338 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 5339 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 5340 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 5341 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 5342 }; 5343 5344 struct fw_vi_stats_cmd { 5345 __be32 op_to_viid; 5346 __be32 retval_len16; 5347 union fw_vi_stats { 5348 struct fw_vi_stats_ctl { 5349 __be16 nstats_ix; 5350 __be16 r6; 5351 __be32 r7; 5352 __be64 stat0; 5353 __be64 stat1; 5354 __be64 stat2; 5355 __be64 stat3; 5356 __be64 stat4; 5357 __be64 stat5; 5358 } ctl; 5359 struct fw_vi_stats_pf { 5360 __be64 tx_bcast_bytes; 5361 __be64 tx_bcast_frames; 5362 __be64 tx_mcast_bytes; 5363 __be64 tx_mcast_frames; 5364 __be64 tx_ucast_bytes; 5365 __be64 tx_ucast_frames; 5366 __be64 tx_offload_bytes; 5367 __be64 tx_offload_frames; 5368 __be64 rx_pf_bytes; 5369 __be64 rx_pf_frames; 5370 __be64 rx_bcast_bytes; 5371 __be64 rx_bcast_frames; 5372 __be64 rx_mcast_bytes; 5373 __be64 rx_mcast_frames; 5374 __be64 rx_ucast_bytes; 5375 __be64 rx_ucast_frames; 5376 __be64 rx_err_frames; 5377 } pf; 5378 struct fw_vi_stats_vf { 5379 __be64 tx_bcast_bytes; 5380 __be64 tx_bcast_frames; 5381 __be64 tx_mcast_bytes; 5382 __be64 tx_mcast_frames; 5383 __be64 tx_ucast_bytes; 5384 __be64 tx_ucast_frames; 5385 __be64 tx_drop_frames; 5386 __be64 tx_offload_bytes; 5387 __be64 tx_offload_frames; 5388 __be64 rx_bcast_bytes; 5389 __be64 rx_bcast_frames; 5390 __be64 rx_mcast_bytes; 5391 __be64 rx_mcast_frames; 5392 __be64 rx_ucast_bytes; 5393 __be64 rx_ucast_frames; 5394 __be64 rx_err_frames; 5395 } vf; 5396 } u; 5397 }; 5398 5399 #define S_FW_VI_STATS_CMD_VIID 0 5400 #define M_FW_VI_STATS_CMD_VIID 0xfff 5401 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 5402 #define G_FW_VI_STATS_CMD_VIID(x) \ 5403 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 5404 5405 #define S_FW_VI_STATS_CMD_NSTATS 12 5406 #define M_FW_VI_STATS_CMD_NSTATS 0x7 5407 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 5408 #define G_FW_VI_STATS_CMD_NSTATS(x) \ 5409 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 5410 5411 #define S_FW_VI_STATS_CMD_IX 0 5412 #define M_FW_VI_STATS_CMD_IX 0x1f 5413 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 5414 #define G_FW_VI_STATS_CMD_IX(x) \ 5415 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 5416 5417 struct fw_acl_mac_cmd { 5418 __be32 op_to_vfn; 5419 __be32 en_to_len16; 5420 __u8 nmac; 5421 __u8 r3[7]; 5422 __be16 r4; 5423 __u8 macaddr0[6]; 5424 __be16 r5; 5425 __u8 macaddr1[6]; 5426 __be16 r6; 5427 __u8 macaddr2[6]; 5428 __be16 r7; 5429 __u8 macaddr3[6]; 5430 }; 5431 5432 #define S_FW_ACL_MAC_CMD_PFN 8 5433 #define M_FW_ACL_MAC_CMD_PFN 0x7 5434 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 5435 #define G_FW_ACL_MAC_CMD_PFN(x) \ 5436 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 5437 5438 #define S_FW_ACL_MAC_CMD_VFN 0 5439 #define M_FW_ACL_MAC_CMD_VFN 0xff 5440 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 5441 #define G_FW_ACL_MAC_CMD_VFN(x) \ 5442 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 5443 5444 #define S_FW_ACL_MAC_CMD_EN 31 5445 #define M_FW_ACL_MAC_CMD_EN 0x1 5446 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 5447 #define G_FW_ACL_MAC_CMD_EN(x) \ 5448 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 5449 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 5450 5451 struct fw_acl_vlan_cmd { 5452 __be32 op_to_vfn; 5453 __be32 en_to_len16; 5454 __u8 nvlan; 5455 __u8 dropnovlan_fm; 5456 __u8 r3_lo[6]; 5457 __be16 vlanid[16]; 5458 }; 5459 5460 #define S_FW_ACL_VLAN_CMD_PFN 8 5461 #define M_FW_ACL_VLAN_CMD_PFN 0x7 5462 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 5463 #define G_FW_ACL_VLAN_CMD_PFN(x) \ 5464 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 5465 5466 #define S_FW_ACL_VLAN_CMD_VFN 0 5467 #define M_FW_ACL_VLAN_CMD_VFN 0xff 5468 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 5469 #define G_FW_ACL_VLAN_CMD_VFN(x) \ 5470 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 5471 5472 #define S_FW_ACL_VLAN_CMD_EN 31 5473 #define M_FW_ACL_VLAN_CMD_EN 0x1 5474 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 5475 #define G_FW_ACL_VLAN_CMD_EN(x) \ 5476 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 5477 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 5478 5479 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 5480 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 5481 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 5482 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 5483 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 5484 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 5485 5486 #define S_FW_ACL_VLAN_CMD_FM 6 5487 #define M_FW_ACL_VLAN_CMD_FM 0x1 5488 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 5489 #define G_FW_ACL_VLAN_CMD_FM(x) \ 5490 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 5491 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 5492 5493 /* port capabilities bitmap */ 5494 enum fw_port_cap { 5495 FW_PORT_CAP_SPEED_100M = 0x0001, 5496 FW_PORT_CAP_SPEED_1G = 0x0002, 5497 FW_PORT_CAP_SPEED_2_5G = 0x0004, 5498 FW_PORT_CAP_SPEED_10G = 0x0008, 5499 FW_PORT_CAP_SPEED_40G = 0x0010, 5500 FW_PORT_CAP_SPEED_100G = 0x0020, 5501 FW_PORT_CAP_FC_RX = 0x0040, 5502 FW_PORT_CAP_FC_TX = 0x0080, 5503 FW_PORT_CAP_ANEG = 0x0100, 5504 FW_PORT_CAP_MDIX = 0x0200, 5505 FW_PORT_CAP_MDIAUTO = 0x0400, 5506 FW_PORT_CAP_FEC = 0x0800, 5507 FW_PORT_CAP_TECHKR = 0x1000, 5508 FW_PORT_CAP_TECHKX4 = 0x2000, 5509 }; 5510 5511 #define S_FW_PORT_AUXLINFO_MDI 3 5512 #define M_FW_PORT_AUXLINFO_MDI 0x3 5513 #define V_FW_PORT_AUXLINFO_MDI(x) ((x) << S_FW_PORT_AUXLINFO_MDI) 5514 #define G_FW_PORT_AUXLINFO_MDI(x) \ 5515 (((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI) 5516 5517 #define S_FW_PORT_AUXLINFO_KX4 2 5518 #define M_FW_PORT_AUXLINFO_KX4 0x1 5519 #define V_FW_PORT_AUXLINFO_KX4(x) ((x) << S_FW_PORT_AUXLINFO_KX4) 5520 #define G_FW_PORT_AUXLINFO_KX4(x) \ 5521 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 5522 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 5523 5524 #define S_FW_PORT_AUXLINFO_KR 1 5525 #define M_FW_PORT_AUXLINFO_KR 0x1 5526 #define V_FW_PORT_AUXLINFO_KR(x) ((x) << S_FW_PORT_AUXLINFO_KR) 5527 #define G_FW_PORT_AUXLINFO_KR(x) \ 5528 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 5529 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 5530 5531 #define S_FW_PORT_AUXLINFO_FEC 0 5532 #define M_FW_PORT_AUXLINFO_FEC 0x1 5533 #define V_FW_PORT_AUXLINFO_FEC(x) ((x) << S_FW_PORT_AUXLINFO_FEC) 5534 #define G_FW_PORT_AUXLINFO_FEC(x) \ 5535 (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) 5536 #define F_FW_PORT_AUXLINFO_FEC V_FW_PORT_AUXLINFO_FEC(1U) 5537 5538 #define S_FW_PORT_RCAP_AUX 11 5539 #define M_FW_PORT_RCAP_AUX 0x7 5540 #define V_FW_PORT_RCAP_AUX(x) ((x) << S_FW_PORT_RCAP_AUX) 5541 #define G_FW_PORT_RCAP_AUX(x) \ 5542 (((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX) 5543 5544 #define S_FW_PORT_CAP_SPEED 0 5545 #define M_FW_PORT_CAP_SPEED 0x3f 5546 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 5547 #define G_FW_PORT_CAP_SPEED(x) \ 5548 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 5549 5550 #define S_FW_PORT_CAP_FC 6 5551 #define M_FW_PORT_CAP_FC 0x3 5552 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 5553 #define G_FW_PORT_CAP_FC(x) \ 5554 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 5555 5556 #define S_FW_PORT_CAP_ANEG 8 5557 #define M_FW_PORT_CAP_ANEG 0x1 5558 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 5559 #define G_FW_PORT_CAP_ANEG(x) \ 5560 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 5561 5562 enum fw_port_mdi { 5563 FW_PORT_CAP_MDI_UNCHANGED, 5564 FW_PORT_CAP_MDI_AUTO, 5565 FW_PORT_CAP_MDI_F_STRAIGHT, 5566 FW_PORT_CAP_MDI_F_CROSSOVER 5567 }; 5568 5569 #define S_FW_PORT_CAP_MDI 9 5570 #define M_FW_PORT_CAP_MDI 3 5571 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 5572 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 5573 5574 enum fw_port_action { 5575 FW_PORT_ACTION_L1_CFG = 0x0001, 5576 FW_PORT_ACTION_L2_CFG = 0x0002, 5577 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 5578 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 5579 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 5580 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 5581 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 5582 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 5583 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 5584 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 5585 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 5586 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 5587 FW_PORT_ACTION_L1_SS_LPBK_ASIC = 0x0021, 5588 FW_PORT_ACTION_MAC_LPBK = 0x0022, 5589 FW_PORT_ACTION_L1_WS_LPBK_ASIC = 0x0023, 5590 FW_PORT_ACTION_L1_EXT_LPBK = 0x0026, 5591 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 5592 FW_PORT_ACTION_PCS_LPBK = 0x0028, 5593 FW_PORT_ACTION_PHY_RESET = 0x0040, 5594 FW_PORT_ACTION_PMA_RESET = 0x0041, 5595 FW_PORT_ACTION_PCS_RESET = 0x0042, 5596 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 5597 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 5598 FW_PORT_ACTION_AN_RESET = 0x0045, 5599 }; 5600 5601 enum fw_port_l2cfg_ctlbf { 5602 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 5603 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 5604 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 5605 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 5606 FW_PORT_L2_CTLBF_IVLAN = 0x10, 5607 FW_PORT_L2_CTLBF_TXIPG = 0x20, 5608 FW_PORT_L2_CTLBF_MTU = 0x40 5609 }; 5610 5611 enum fw_port_dcb_cfg { 5612 FW_PORT_DCB_CFG_PG = 0x01, 5613 FW_PORT_DCB_CFG_PFC = 0x02, 5614 FW_PORT_DCB_CFG_APPL = 0x04 5615 }; 5616 5617 enum fw_port_dcb_cfg_rc { 5618 FW_PORT_DCB_CFG_SUCCESS = 0x0, 5619 FW_PORT_DCB_CFG_ERROR = 0x1 5620 }; 5621 5622 enum fw_port_dcb_type { 5623 FW_PORT_DCB_TYPE_PGID = 0x00, 5624 FW_PORT_DCB_TYPE_PGRATE = 0x01, 5625 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 5626 FW_PORT_DCB_TYPE_PFC = 0x03, 5627 FW_PORT_DCB_TYPE_APP_ID = 0x04, 5628 FW_PORT_DCB_TYPE_CONTROL = 0x05, 5629 }; 5630 5631 enum fw_port_diag_ops { 5632 FW_PORT_DIAGS_TEMP = 0x00, 5633 FW_PORT_DIAGS_TX_POWER = 0x01, 5634 FW_PORT_DIAGS_RX_POWER = 0x02, 5635 }; 5636 5637 struct fw_port_cmd { 5638 __be32 op_to_portid; 5639 __be32 action_to_len16; 5640 union fw_port { 5641 struct fw_port_l1cfg { 5642 __be32 rcap; 5643 __be32 r; 5644 } l1cfg; 5645 struct fw_port_l2cfg { 5646 __u8 ctlbf; 5647 __u8 ovlan3_to_ivlan0; 5648 __be16 ivlantype; 5649 __be16 txipg_force_pinfo; 5650 __be16 mtu; 5651 __be16 ovlan0mask; 5652 __be16 ovlan0type; 5653 __be16 ovlan1mask; 5654 __be16 ovlan1type; 5655 __be16 ovlan2mask; 5656 __be16 ovlan2type; 5657 __be16 ovlan3mask; 5658 __be16 ovlan3type; 5659 } l2cfg; 5660 struct fw_port_info { 5661 __be32 lstatus_to_modtype; 5662 __be16 pcap; 5663 __be16 acap; 5664 __be16 mtu; 5665 __u8 cbllen; 5666 __u8 auxlinfo; 5667 __be32 r8; 5668 __be64 r9; 5669 } info; 5670 struct fw_port_diags { 5671 __u8 diagop; 5672 __u8 r[3]; 5673 __be32 diagval; 5674 } diags; 5675 union fw_port_dcb { 5676 struct fw_port_dcb_pgid { 5677 __u8 type; 5678 __u8 apply_pkd; 5679 __u8 r10_lo[2]; 5680 __be32 pgid; 5681 __be64 r11; 5682 } pgid; 5683 struct fw_port_dcb_pgrate { 5684 __u8 type; 5685 __u8 apply_pkd; 5686 __u8 r10_lo[5]; 5687 __u8 num_tcs_supported; 5688 __u8 pgrate[8]; 5689 } pgrate; 5690 struct fw_port_dcb_priorate { 5691 __u8 type; 5692 __u8 apply_pkd; 5693 __u8 r10_lo[6]; 5694 __u8 strict_priorate[8]; 5695 } priorate; 5696 struct fw_port_dcb_pfc { 5697 __u8 type; 5698 __u8 pfcen; 5699 __be16 r10[3]; 5700 __be64 r11; 5701 } pfc; 5702 struct fw_port_app_priority { 5703 __u8 type; 5704 __u8 r10[2]; 5705 __u8 idx; 5706 __u8 user_prio_map; 5707 __u8 sel_field; 5708 __be16 protocolid; 5709 __be64 r12; 5710 } app_priority; 5711 struct fw_port_dcb_control { 5712 __u8 type; 5713 __u8 all_syncd_pkd; 5714 __be16 r10_lo[3]; 5715 __be64 r11; 5716 } control; 5717 } dcb; 5718 } u; 5719 }; 5720 5721 #define S_FW_PORT_CMD_READ 22 5722 #define M_FW_PORT_CMD_READ 0x1 5723 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 5724 #define G_FW_PORT_CMD_READ(x) \ 5725 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 5726 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 5727 5728 #define S_FW_PORT_CMD_PORTID 0 5729 #define M_FW_PORT_CMD_PORTID 0xf 5730 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 5731 #define G_FW_PORT_CMD_PORTID(x) \ 5732 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 5733 5734 #define S_FW_PORT_CMD_ACTION 16 5735 #define M_FW_PORT_CMD_ACTION 0xffff 5736 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 5737 #define G_FW_PORT_CMD_ACTION(x) \ 5738 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 5739 5740 #define S_FW_PORT_CMD_OVLAN3 7 5741 #define M_FW_PORT_CMD_OVLAN3 0x1 5742 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 5743 #define G_FW_PORT_CMD_OVLAN3(x) \ 5744 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 5745 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 5746 5747 #define S_FW_PORT_CMD_OVLAN2 6 5748 #define M_FW_PORT_CMD_OVLAN2 0x1 5749 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 5750 #define G_FW_PORT_CMD_OVLAN2(x) \ 5751 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 5752 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 5753 5754 #define S_FW_PORT_CMD_OVLAN1 5 5755 #define M_FW_PORT_CMD_OVLAN1 0x1 5756 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 5757 #define G_FW_PORT_CMD_OVLAN1(x) \ 5758 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 5759 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 5760 5761 #define S_FW_PORT_CMD_OVLAN0 4 5762 #define M_FW_PORT_CMD_OVLAN0 0x1 5763 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 5764 #define G_FW_PORT_CMD_OVLAN0(x) \ 5765 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 5766 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 5767 5768 #define S_FW_PORT_CMD_IVLAN0 3 5769 #define M_FW_PORT_CMD_IVLAN0 0x1 5770 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 5771 #define G_FW_PORT_CMD_IVLAN0(x) \ 5772 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 5773 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 5774 5775 #define S_FW_PORT_CMD_TXIPG 3 5776 #define M_FW_PORT_CMD_TXIPG 0x1fff 5777 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 5778 #define G_FW_PORT_CMD_TXIPG(x) \ 5779 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 5780 5781 #define S_FW_PORT_CMD_FORCE_PINFO 0 5782 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 5783 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 5784 #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 5785 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 5786 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 5787 5788 #define S_FW_PORT_CMD_LSTATUS 31 5789 #define M_FW_PORT_CMD_LSTATUS 0x1 5790 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 5791 #define G_FW_PORT_CMD_LSTATUS(x) \ 5792 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 5793 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 5794 5795 #define S_FW_PORT_CMD_LSPEED 24 5796 #define M_FW_PORT_CMD_LSPEED 0x3f 5797 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 5798 #define G_FW_PORT_CMD_LSPEED(x) \ 5799 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 5800 5801 #define S_FW_PORT_CMD_TXPAUSE 23 5802 #define M_FW_PORT_CMD_TXPAUSE 0x1 5803 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 5804 #define G_FW_PORT_CMD_TXPAUSE(x) \ 5805 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 5806 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 5807 5808 #define S_FW_PORT_CMD_RXPAUSE 22 5809 #define M_FW_PORT_CMD_RXPAUSE 0x1 5810 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 5811 #define G_FW_PORT_CMD_RXPAUSE(x) \ 5812 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 5813 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 5814 5815 #define S_FW_PORT_CMD_MDIOCAP 21 5816 #define M_FW_PORT_CMD_MDIOCAP 0x1 5817 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 5818 #define G_FW_PORT_CMD_MDIOCAP(x) \ 5819 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 5820 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 5821 5822 #define S_FW_PORT_CMD_MDIOADDR 16 5823 #define M_FW_PORT_CMD_MDIOADDR 0x1f 5824 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 5825 #define G_FW_PORT_CMD_MDIOADDR(x) \ 5826 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 5827 5828 #define S_FW_PORT_CMD_LPTXPAUSE 15 5829 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 5830 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 5831 #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 5832 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 5833 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 5834 5835 #define S_FW_PORT_CMD_LPRXPAUSE 14 5836 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 5837 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 5838 #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 5839 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 5840 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 5841 5842 #define S_FW_PORT_CMD_PTYPE 8 5843 #define M_FW_PORT_CMD_PTYPE 0x1f 5844 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 5845 #define G_FW_PORT_CMD_PTYPE(x) \ 5846 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 5847 5848 #define S_FW_PORT_CMD_LINKDNRC 5 5849 #define M_FW_PORT_CMD_LINKDNRC 0x7 5850 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 5851 #define G_FW_PORT_CMD_LINKDNRC(x) \ 5852 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 5853 5854 #define S_FW_PORT_CMD_MODTYPE 0 5855 #define M_FW_PORT_CMD_MODTYPE 0x1f 5856 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 5857 #define G_FW_PORT_CMD_MODTYPE(x) \ 5858 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 5859 5860 #define S_FW_PORT_CMD_APPLY 7 5861 #define M_FW_PORT_CMD_APPLY 0x1 5862 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 5863 #define G_FW_PORT_CMD_APPLY(x) \ 5864 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 5865 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 5866 5867 #define S_FW_PORT_CMD_ALL_SYNCD 7 5868 #define M_FW_PORT_CMD_ALL_SYNCD 0x1 5869 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 5870 #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 5871 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 5872 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 5873 5874 /* 5875 * These are configured into the VPD and hence tools that generate 5876 * VPD may use this enumeration. 5877 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 5878 */ 5879 enum fw_port_type { 5880 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 5881 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 5882 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 5883 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */ 5884 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */ 5885 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 5886 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 5887 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 5888 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 5889 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 5890 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 5891 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 5892 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 5893 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 5894 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 5895 5896 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 5897 }; 5898 5899 /* These are read from module's EEPROM and determined once the 5900 module is inserted. */ 5901 enum fw_port_module_type { 5902 FW_PORT_MOD_TYPE_NA = 0x0, 5903 FW_PORT_MOD_TYPE_LR = 0x1, 5904 FW_PORT_MOD_TYPE_SR = 0x2, 5905 FW_PORT_MOD_TYPE_ER = 0x3, 5906 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 5907 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 5908 FW_PORT_MOD_TYPE_LRM = 0x6, 5909 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 5910 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 5911 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 5912 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 5913 }; 5914 5915 /* used by FW and tools may use this to generate VPD */ 5916 enum fw_port_mod_sub_type { 5917 FW_PORT_MOD_SUB_TYPE_NA, 5918 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 5919 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 5920 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 5921 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 5922 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 5923 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 5924 5925 /* 5926 * The following will never been in the VPD. They are TWINAX cable 5927 * lengths decoded from SFP+ module i2c PROMs. These should almost 5928 * certainly go somewhere else ... 5929 */ 5930 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 5931 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 5932 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 5933 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 5934 }; 5935 5936 /* link down reason codes (3b) */ 5937 enum fw_port_link_dn_rc { 5938 FW_PORT_LINK_DN_RC_NONE, 5939 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 5940 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 5941 FW_PORT_LINK_DN_RESERVED3, 5942 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 5943 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 5944 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 5945 FW_PORT_LINK_DN_RESERVED7 5946 }; 5947 5948 /* port stats */ 5949 #define FW_NUM_PORT_STATS 50 5950 #define FW_NUM_PORT_TX_STATS 23 5951 #define FW_NUM_PORT_RX_STATS 27 5952 5953 enum fw_port_stats_tx_index { 5954 FW_STAT_TX_PORT_BYTES_IX, 5955 FW_STAT_TX_PORT_FRAMES_IX, 5956 FW_STAT_TX_PORT_BCAST_IX, 5957 FW_STAT_TX_PORT_MCAST_IX, 5958 FW_STAT_TX_PORT_UCAST_IX, 5959 FW_STAT_TX_PORT_ERROR_IX, 5960 FW_STAT_TX_PORT_64B_IX, 5961 FW_STAT_TX_PORT_65B_127B_IX, 5962 FW_STAT_TX_PORT_128B_255B_IX, 5963 FW_STAT_TX_PORT_256B_511B_IX, 5964 FW_STAT_TX_PORT_512B_1023B_IX, 5965 FW_STAT_TX_PORT_1024B_1518B_IX, 5966 FW_STAT_TX_PORT_1519B_MAX_IX, 5967 FW_STAT_TX_PORT_DROP_IX, 5968 FW_STAT_TX_PORT_PAUSE_IX, 5969 FW_STAT_TX_PORT_PPP0_IX, 5970 FW_STAT_TX_PORT_PPP1_IX, 5971 FW_STAT_TX_PORT_PPP2_IX, 5972 FW_STAT_TX_PORT_PPP3_IX, 5973 FW_STAT_TX_PORT_PPP4_IX, 5974 FW_STAT_TX_PORT_PPP5_IX, 5975 FW_STAT_TX_PORT_PPP6_IX, 5976 FW_STAT_TX_PORT_PPP7_IX 5977 }; 5978 5979 enum fw_port_stat_rx_index { 5980 FW_STAT_RX_PORT_BYTES_IX, 5981 FW_STAT_RX_PORT_FRAMES_IX, 5982 FW_STAT_RX_PORT_BCAST_IX, 5983 FW_STAT_RX_PORT_MCAST_IX, 5984 FW_STAT_RX_PORT_UCAST_IX, 5985 FW_STAT_RX_PORT_MTU_ERROR_IX, 5986 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 5987 FW_STAT_RX_PORT_CRC_ERROR_IX, 5988 FW_STAT_RX_PORT_LEN_ERROR_IX, 5989 FW_STAT_RX_PORT_SYM_ERROR_IX, 5990 FW_STAT_RX_PORT_64B_IX, 5991 FW_STAT_RX_PORT_65B_127B_IX, 5992 FW_STAT_RX_PORT_128B_255B_IX, 5993 FW_STAT_RX_PORT_256B_511B_IX, 5994 FW_STAT_RX_PORT_512B_1023B_IX, 5995 FW_STAT_RX_PORT_1024B_1518B_IX, 5996 FW_STAT_RX_PORT_1519B_MAX_IX, 5997 FW_STAT_RX_PORT_PAUSE_IX, 5998 FW_STAT_RX_PORT_PPP0_IX, 5999 FW_STAT_RX_PORT_PPP1_IX, 6000 FW_STAT_RX_PORT_PPP2_IX, 6001 FW_STAT_RX_PORT_PPP3_IX, 6002 FW_STAT_RX_PORT_PPP4_IX, 6003 FW_STAT_RX_PORT_PPP5_IX, 6004 FW_STAT_RX_PORT_PPP6_IX, 6005 FW_STAT_RX_PORT_PPP7_IX, 6006 FW_STAT_RX_PORT_LESS_64B_IX 6007 }; 6008 6009 struct fw_port_stats_cmd { 6010 __be32 op_to_portid; 6011 __be32 retval_len16; 6012 union fw_port_stats { 6013 struct fw_port_stats_ctl { 6014 __u8 nstats_bg_bm; 6015 __u8 tx_ix; 6016 __be16 r6; 6017 __be32 r7; 6018 __be64 stat0; 6019 __be64 stat1; 6020 __be64 stat2; 6021 __be64 stat3; 6022 __be64 stat4; 6023 __be64 stat5; 6024 } ctl; 6025 struct fw_port_stats_all { 6026 __be64 tx_bytes; 6027 __be64 tx_frames; 6028 __be64 tx_bcast; 6029 __be64 tx_mcast; 6030 __be64 tx_ucast; 6031 __be64 tx_error; 6032 __be64 tx_64b; 6033 __be64 tx_65b_127b; 6034 __be64 tx_128b_255b; 6035 __be64 tx_256b_511b; 6036 __be64 tx_512b_1023b; 6037 __be64 tx_1024b_1518b; 6038 __be64 tx_1519b_max; 6039 __be64 tx_drop; 6040 __be64 tx_pause; 6041 __be64 tx_ppp0; 6042 __be64 tx_ppp1; 6043 __be64 tx_ppp2; 6044 __be64 tx_ppp3; 6045 __be64 tx_ppp4; 6046 __be64 tx_ppp5; 6047 __be64 tx_ppp6; 6048 __be64 tx_ppp7; 6049 __be64 rx_bytes; 6050 __be64 rx_frames; 6051 __be64 rx_bcast; 6052 __be64 rx_mcast; 6053 __be64 rx_ucast; 6054 __be64 rx_mtu_error; 6055 __be64 rx_mtu_crc_error; 6056 __be64 rx_crc_error; 6057 __be64 rx_len_error; 6058 __be64 rx_sym_error; 6059 __be64 rx_64b; 6060 __be64 rx_65b_127b; 6061 __be64 rx_128b_255b; 6062 __be64 rx_256b_511b; 6063 __be64 rx_512b_1023b; 6064 __be64 rx_1024b_1518b; 6065 __be64 rx_1519b_max; 6066 __be64 rx_pause; 6067 __be64 rx_ppp0; 6068 __be64 rx_ppp1; 6069 __be64 rx_ppp2; 6070 __be64 rx_ppp3; 6071 __be64 rx_ppp4; 6072 __be64 rx_ppp5; 6073 __be64 rx_ppp6; 6074 __be64 rx_ppp7; 6075 __be64 rx_less_64b; 6076 __be64 rx_bg_drop; 6077 __be64 rx_bg_trunc; 6078 } all; 6079 } u; 6080 }; 6081 6082 #define S_FW_PORT_STATS_CMD_NSTATS 4 6083 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 6084 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 6085 #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 6086 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 6087 6088 #define S_FW_PORT_STATS_CMD_BG_BM 0 6089 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 6090 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 6091 #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 6092 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 6093 6094 #define S_FW_PORT_STATS_CMD_TX 7 6095 #define M_FW_PORT_STATS_CMD_TX 0x1 6096 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 6097 #define G_FW_PORT_STATS_CMD_TX(x) \ 6098 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 6099 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 6100 6101 #define S_FW_PORT_STATS_CMD_IX 0 6102 #define M_FW_PORT_STATS_CMD_IX 0x3f 6103 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 6104 #define G_FW_PORT_STATS_CMD_IX(x) \ 6105 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 6106 6107 /* port loopback stats */ 6108 #define FW_NUM_LB_STATS 14 6109 enum fw_port_lb_stats_index { 6110 FW_STAT_LB_PORT_BYTES_IX, 6111 FW_STAT_LB_PORT_FRAMES_IX, 6112 FW_STAT_LB_PORT_BCAST_IX, 6113 FW_STAT_LB_PORT_MCAST_IX, 6114 FW_STAT_LB_PORT_UCAST_IX, 6115 FW_STAT_LB_PORT_ERROR_IX, 6116 FW_STAT_LB_PORT_64B_IX, 6117 FW_STAT_LB_PORT_65B_127B_IX, 6118 FW_STAT_LB_PORT_128B_255B_IX, 6119 FW_STAT_LB_PORT_256B_511B_IX, 6120 FW_STAT_LB_PORT_512B_1023B_IX, 6121 FW_STAT_LB_PORT_1024B_1518B_IX, 6122 FW_STAT_LB_PORT_1519B_MAX_IX, 6123 FW_STAT_LB_PORT_DROP_FRAMES_IX 6124 }; 6125 6126 struct fw_port_lb_stats_cmd { 6127 __be32 op_to_lbport; 6128 __be32 retval_len16; 6129 union fw_port_lb_stats { 6130 struct fw_port_lb_stats_ctl { 6131 __u8 nstats_bg_bm; 6132 __u8 ix_pkd; 6133 __be16 r6; 6134 __be32 r7; 6135 __be64 stat0; 6136 __be64 stat1; 6137 __be64 stat2; 6138 __be64 stat3; 6139 __be64 stat4; 6140 __be64 stat5; 6141 } ctl; 6142 struct fw_port_lb_stats_all { 6143 __be64 tx_bytes; 6144 __be64 tx_frames; 6145 __be64 tx_bcast; 6146 __be64 tx_mcast; 6147 __be64 tx_ucast; 6148 __be64 tx_error; 6149 __be64 tx_64b; 6150 __be64 tx_65b_127b; 6151 __be64 tx_128b_255b; 6152 __be64 tx_256b_511b; 6153 __be64 tx_512b_1023b; 6154 __be64 tx_1024b_1518b; 6155 __be64 tx_1519b_max; 6156 __be64 rx_lb_drop; 6157 __be64 rx_lb_trunc; 6158 } all; 6159 } u; 6160 }; 6161 6162 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 6163 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 6164 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 6165 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 6166 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 6167 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 6168 6169 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 6170 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 6171 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 6172 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 6173 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 6174 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 6175 6176 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 6177 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 6178 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 6179 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 6180 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 6181 6182 #define S_FW_PORT_LB_STATS_CMD_IX 0 6183 #define M_FW_PORT_LB_STATS_CMD_IX 0xf 6184 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 6185 #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 6186 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 6187 6188 /* Trace related defines */ 6189 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 6190 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 6191 6192 struct fw_port_trace_cmd { 6193 __be32 op_to_portid; 6194 __be32 retval_len16; 6195 __be16 traceen_to_pciech; 6196 __be16 qnum; 6197 __be32 r5; 6198 }; 6199 6200 #define S_FW_PORT_TRACE_CMD_PORTID 0 6201 #define M_FW_PORT_TRACE_CMD_PORTID 0xf 6202 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 6203 #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 6204 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 6205 6206 #define S_FW_PORT_TRACE_CMD_TRACEEN 15 6207 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 6208 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 6209 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 6210 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 6211 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 6212 6213 #define S_FW_PORT_TRACE_CMD_FLTMODE 14 6214 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 6215 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 6216 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 6217 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 6218 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 6219 6220 #define S_FW_PORT_TRACE_CMD_DUPLEN 13 6221 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 6222 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 6223 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 6224 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 6225 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 6226 6227 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 6228 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 6229 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6230 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6231 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6232 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 6233 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6234 6235 #define S_FW_PORT_TRACE_CMD_PCIECH 6 6236 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 6237 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 6238 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 6239 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 6240 6241 struct fw_port_trace_mmap_cmd { 6242 __be32 op_to_portid; 6243 __be32 retval_len16; 6244 __be32 fid_to_skipoffset; 6245 __be32 minpktsize_capturemax; 6246 __u8 map[224]; 6247 }; 6248 6249 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 6250 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 6251 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6252 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 6253 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6254 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 6255 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 6256 6257 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 6258 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 6259 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 6260 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 6261 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 6262 6263 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 6264 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 6265 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6266 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6267 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6268 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 6269 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6270 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 6271 6272 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 6273 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 6274 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6275 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6276 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6277 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 6278 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6279 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN \ 6280 V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 6281 6282 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 6283 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 6284 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6285 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6286 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6287 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 6288 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6289 6290 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 6291 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 6292 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6293 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6294 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6295 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 6296 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6297 6298 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 6299 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 6300 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6301 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6302 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6303 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 6304 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6305 6306 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 6307 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 6308 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6309 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6310 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6311 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 6312 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6313 6314 struct fw_rss_ind_tbl_cmd { 6315 __be32 op_to_viid; 6316 __be32 retval_len16; 6317 __be16 niqid; 6318 __be16 startidx; 6319 __be32 r3; 6320 __be32 iq0_to_iq2; 6321 __be32 iq3_to_iq5; 6322 __be32 iq6_to_iq8; 6323 __be32 iq9_to_iq11; 6324 __be32 iq12_to_iq14; 6325 __be32 iq15_to_iq17; 6326 __be32 iq18_to_iq20; 6327 __be32 iq21_to_iq23; 6328 __be32 iq24_to_iq26; 6329 __be32 iq27_to_iq29; 6330 __be32 iq30_iq31; 6331 __be32 r15_lo; 6332 }; 6333 6334 #define S_FW_RSS_IND_TBL_CMD_VIID 0 6335 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 6336 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 6337 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 6338 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 6339 6340 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 6341 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 6342 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 6343 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 6344 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 6345 6346 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 6347 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 6348 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 6349 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 6350 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 6351 6352 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 6353 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 6354 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 6355 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 6356 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 6357 6358 #define S_FW_RSS_IND_TBL_CMD_IQ3 20 6359 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 6360 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 6361 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 6362 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 6363 6364 #define S_FW_RSS_IND_TBL_CMD_IQ4 10 6365 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 6366 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 6367 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 6368 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 6369 6370 #define S_FW_RSS_IND_TBL_CMD_IQ5 0 6371 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 6372 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 6373 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 6374 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 6375 6376 #define S_FW_RSS_IND_TBL_CMD_IQ6 20 6377 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 6378 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 6379 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 6380 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 6381 6382 #define S_FW_RSS_IND_TBL_CMD_IQ7 10 6383 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 6384 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 6385 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 6386 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 6387 6388 #define S_FW_RSS_IND_TBL_CMD_IQ8 0 6389 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 6390 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 6391 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 6392 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 6393 6394 #define S_FW_RSS_IND_TBL_CMD_IQ9 20 6395 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 6396 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 6397 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 6398 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 6399 6400 #define S_FW_RSS_IND_TBL_CMD_IQ10 10 6401 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 6402 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 6403 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 6404 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 6405 6406 #define S_FW_RSS_IND_TBL_CMD_IQ11 0 6407 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 6408 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 6409 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 6410 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 6411 6412 #define S_FW_RSS_IND_TBL_CMD_IQ12 20 6413 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 6414 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 6415 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 6416 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 6417 6418 #define S_FW_RSS_IND_TBL_CMD_IQ13 10 6419 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 6420 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 6421 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 6422 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 6423 6424 #define S_FW_RSS_IND_TBL_CMD_IQ14 0 6425 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 6426 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 6427 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 6428 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 6429 6430 #define S_FW_RSS_IND_TBL_CMD_IQ15 20 6431 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 6432 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 6433 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 6434 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 6435 6436 #define S_FW_RSS_IND_TBL_CMD_IQ16 10 6437 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 6438 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 6439 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 6440 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 6441 6442 #define S_FW_RSS_IND_TBL_CMD_IQ17 0 6443 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 6444 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 6445 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 6446 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 6447 6448 #define S_FW_RSS_IND_TBL_CMD_IQ18 20 6449 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 6450 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 6451 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 6452 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 6453 6454 #define S_FW_RSS_IND_TBL_CMD_IQ19 10 6455 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 6456 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 6457 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 6458 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 6459 6460 #define S_FW_RSS_IND_TBL_CMD_IQ20 0 6461 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 6462 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 6463 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 6464 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 6465 6466 #define S_FW_RSS_IND_TBL_CMD_IQ21 20 6467 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 6468 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 6469 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 6470 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 6471 6472 #define S_FW_RSS_IND_TBL_CMD_IQ22 10 6473 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 6474 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 6475 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 6476 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 6477 6478 #define S_FW_RSS_IND_TBL_CMD_IQ23 0 6479 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 6480 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 6481 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 6482 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 6483 6484 #define S_FW_RSS_IND_TBL_CMD_IQ24 20 6485 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 6486 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 6487 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 6488 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 6489 6490 #define S_FW_RSS_IND_TBL_CMD_IQ25 10 6491 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 6492 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 6493 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 6494 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 6495 6496 #define S_FW_RSS_IND_TBL_CMD_IQ26 0 6497 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 6498 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 6499 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 6500 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 6501 6502 #define S_FW_RSS_IND_TBL_CMD_IQ27 20 6503 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 6504 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 6505 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 6506 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 6507 6508 #define S_FW_RSS_IND_TBL_CMD_IQ28 10 6509 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 6510 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 6511 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 6512 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 6513 6514 #define S_FW_RSS_IND_TBL_CMD_IQ29 0 6515 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 6516 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 6517 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 6518 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 6519 6520 #define S_FW_RSS_IND_TBL_CMD_IQ30 20 6521 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 6522 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 6523 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 6524 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 6525 6526 #define S_FW_RSS_IND_TBL_CMD_IQ31 10 6527 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 6528 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 6529 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 6530 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 6531 6532 struct fw_rss_glb_config_cmd { 6533 __be32 op_to_write; 6534 __be32 retval_len16; 6535 union fw_rss_glb_config { 6536 struct fw_rss_glb_config_manual { 6537 __be32 mode_pkd; 6538 __be32 r3; 6539 __be64 r4; 6540 __be64 r5; 6541 } manual; 6542 struct fw_rss_glb_config_basicvirtual { 6543 __be32 mode_pkd; 6544 __be32 synmapen_to_hashtoeplitz; 6545 __be64 r8; 6546 __be64 r9; 6547 } basicvirtual; 6548 } u; 6549 }; 6550 6551 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 6552 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 6553 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 6554 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 6555 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 6556 6557 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 6558 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 6559 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 6560 6561 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 6562 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 6563 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 6564 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 6565 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 6566 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 6567 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 6568 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN \ 6569 V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 6570 6571 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 6572 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 6573 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 6574 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 6575 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 6576 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 6577 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 6578 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 6579 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 6580 6581 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 6582 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 6583 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 6584 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 6585 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 6586 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 6587 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 6588 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 6589 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 6590 6591 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 6592 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 6593 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 6594 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 6595 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 6596 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 6597 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 6598 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 6599 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 6600 6601 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 6602 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 6603 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 6604 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 6605 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 6606 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 6607 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 6608 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 6609 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 6610 6611 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 6612 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 6613 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 6614 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 6615 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 6616 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 6617 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 6618 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN \ 6619 V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 6620 6621 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 6622 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 6623 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 6624 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 6625 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 6626 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 6627 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 6628 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN \ 6629 V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 6630 6631 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 6632 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 6633 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 6634 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 6635 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 6636 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 6637 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 6638 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 6639 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 6640 6641 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 6642 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 6643 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 6644 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 6645 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 6646 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 6647 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 6648 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 6649 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 6650 6651 struct fw_rss_vi_config_cmd { 6652 __be32 op_to_viid; 6653 __be32 retval_len16; 6654 union fw_rss_vi_config { 6655 struct fw_rss_vi_config_manual { 6656 __be64 r3; 6657 __be64 r4; 6658 __be64 r5; 6659 } manual; 6660 struct fw_rss_vi_config_basicvirtual { 6661 __be32 r6; 6662 __be32 defaultq_to_udpen; 6663 __be64 r9; 6664 __be64 r10; 6665 } basicvirtual; 6666 } u; 6667 }; 6668 6669 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 6670 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 6671 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 6672 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 6673 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 6674 6675 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 6676 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 6677 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 6678 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 6679 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 6680 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 6681 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 6682 6683 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 6684 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 6685 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 6686 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6687 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 6688 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 6689 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6690 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 6691 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 6692 6693 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 6694 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 6695 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 6696 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6697 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 6698 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 6699 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6700 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 6701 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 6702 6703 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 6704 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 6705 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 6706 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6707 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 6708 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 6709 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6710 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 6711 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 6712 6713 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 6714 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 6715 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 6716 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6717 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 6718 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 6719 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6720 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 6721 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 6722 6723 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 6724 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 6725 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 6726 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 6727 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 6728 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 6729 6730 enum fw_sched_sc { 6731 FW_SCHED_SC_CONFIG = 0, 6732 FW_SCHED_SC_PARAMS = 1, 6733 }; 6734 6735 enum fw_sched_type { 6736 FW_SCHED_TYPE_PKTSCHED = 0, 6737 FW_SCHED_TYPE_STREAMSCHED = 1, 6738 }; 6739 6740 enum fw_sched_params_level { 6741 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 6742 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 6743 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 6744 }; 6745 6746 enum fw_sched_params_mode { 6747 FW_SCHED_PARAMS_MODE_CLASS = 0, 6748 FW_SCHED_PARAMS_MODE_FLOW = 1, 6749 }; 6750 6751 enum fw_sched_params_unit { 6752 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 6753 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 6754 }; 6755 6756 enum fw_sched_params_rate { 6757 FW_SCHED_PARAMS_RATE_REL = 0, 6758 FW_SCHED_PARAMS_RATE_ABS = 1, 6759 }; 6760 6761 struct fw_sched_cmd { 6762 __be32 op_to_write; 6763 __be32 retval_len16; 6764 union fw_sched { 6765 struct fw_sched_config { 6766 __u8 sc; 6767 __u8 type; 6768 __u8 minmaxen; 6769 __u8 r3[5]; 6770 } config; 6771 struct fw_sched_params { 6772 __u8 sc; 6773 __u8 type; 6774 __u8 level; 6775 __u8 mode; 6776 __u8 unit; 6777 __u8 rate; 6778 __u8 ch; 6779 __u8 cl; 6780 __be32 min; 6781 __be32 max; 6782 __be16 weight; 6783 __be16 pktsize; 6784 __be16 burstsize; 6785 __be16 r4; 6786 } params; 6787 } u; 6788 }; 6789 6790 /* 6791 * length of the formatting string 6792 */ 6793 #define FW_DEVLOG_FMT_LEN 192 6794 6795 /* 6796 * maximum number of the formatting string parameters 6797 */ 6798 #define FW_DEVLOG_FMT_PARAMS_NUM 8 6799 6800 /* 6801 * priority levels 6802 */ 6803 enum fw_devlog_level { 6804 FW_DEVLOG_LEVEL_EMERG = 0x0, 6805 FW_DEVLOG_LEVEL_CRIT = 0x1, 6806 FW_DEVLOG_LEVEL_ERR = 0x2, 6807 FW_DEVLOG_LEVEL_NOTICE = 0x3, 6808 FW_DEVLOG_LEVEL_INFO = 0x4, 6809 FW_DEVLOG_LEVEL_DEBUG = 0x5, 6810 FW_DEVLOG_LEVEL_MAX = 0x5, 6811 }; 6812 6813 /* 6814 * facilities that may send a log message 6815 */ 6816 enum fw_devlog_facility { 6817 FW_DEVLOG_FACILITY_CORE = 0x00, 6818 FW_DEVLOG_FACILITY_CF = 0x01, 6819 FW_DEVLOG_FACILITY_SCHED = 0x02, 6820 FW_DEVLOG_FACILITY_TIMER = 0x04, 6821 FW_DEVLOG_FACILITY_RES = 0x06, 6822 FW_DEVLOG_FACILITY_HW = 0x08, 6823 FW_DEVLOG_FACILITY_FLR = 0x10, 6824 FW_DEVLOG_FACILITY_DMAQ = 0x12, 6825 FW_DEVLOG_FACILITY_PHY = 0x14, 6826 FW_DEVLOG_FACILITY_MAC = 0x16, 6827 FW_DEVLOG_FACILITY_PORT = 0x18, 6828 FW_DEVLOG_FACILITY_VI = 0x1A, 6829 FW_DEVLOG_FACILITY_FILTER = 0x1C, 6830 FW_DEVLOG_FACILITY_ACL = 0x1E, 6831 FW_DEVLOG_FACILITY_TM = 0x20, 6832 FW_DEVLOG_FACILITY_QFC = 0x22, 6833 FW_DEVLOG_FACILITY_DCB = 0x24, 6834 FW_DEVLOG_FACILITY_ETH = 0x26, 6835 FW_DEVLOG_FACILITY_OFLD = 0x28, 6836 FW_DEVLOG_FACILITY_RI = 0x2A, 6837 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 6838 FW_DEVLOG_FACILITY_FCOE = 0x2E, 6839 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 6840 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 6841 FW_DEVLOG_FACILITY_MAX = 0x32, 6842 }; 6843 6844 /* 6845 * log message format 6846 */ 6847 struct fw_devlog_e { 6848 __be64 timestamp; 6849 __be32 seqno; 6850 __be16 reserved1; 6851 __u8 level; 6852 __u8 facility; 6853 __u8 fmt[FW_DEVLOG_FMT_LEN]; 6854 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 6855 __be32 reserved3[4]; 6856 }; 6857 6858 struct fw_devlog_cmd { 6859 __be32 op_to_write; 6860 __be32 retval_len16; 6861 __u8 level; 6862 __u8 r2[7]; 6863 __be32 memtype_devlog_memaddr16_devlog; 6864 __be32 memsize_devlog; 6865 __be32 r3[2]; 6866 }; 6867 6868 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 6869 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 6870 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 6871 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 6872 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 6873 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 6874 6875 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 6876 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 6877 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 6878 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 6879 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 6880 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 6881 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 6882 6883 enum fw_watchdog_actions { 6884 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 6885 FW_WATCHDOG_ACTION_FLR = 1, 6886 FW_WATCHDOG_ACTION_BYPASS = 2, 6887 FW_WATCHDOG_ACTION_TMPCHK = 3, 6888 6889 FW_WATCHDOG_ACTION_MAX = 4, 6890 }; 6891 6892 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 6893 6894 struct fw_watchdog_cmd { 6895 __be32 op_to_vfn; 6896 __be32 retval_len16; 6897 __be32 timeout; 6898 __be32 action; 6899 }; 6900 6901 #define S_FW_WATCHDOG_CMD_PFN 8 6902 #define M_FW_WATCHDOG_CMD_PFN 0x7 6903 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 6904 #define G_FW_WATCHDOG_CMD_PFN(x) \ 6905 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 6906 6907 #define S_FW_WATCHDOG_CMD_VFN 0 6908 #define M_FW_WATCHDOG_CMD_VFN 0xff 6909 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 6910 #define G_FW_WATCHDOG_CMD_VFN(x) \ 6911 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 6912 6913 struct fw_clip_cmd { 6914 __be32 op_to_write; 6915 __be32 alloc_to_len16; 6916 __be64 ip_hi; 6917 __be64 ip_lo; 6918 __be32 r4[2]; 6919 }; 6920 6921 #define S_FW_CLIP_CMD_ALLOC 31 6922 #define M_FW_CLIP_CMD_ALLOC 0x1 6923 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 6924 #define G_FW_CLIP_CMD_ALLOC(x) \ 6925 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 6926 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 6927 6928 #define S_FW_CLIP_CMD_FREE 30 6929 #define M_FW_CLIP_CMD_FREE 0x1 6930 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 6931 #define G_FW_CLIP_CMD_FREE(x) \ 6932 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 6933 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 6934 6935 /****************************************************************************** 6936 * F O i S C S I C O M M A N D s 6937 **************************************/ 6938 6939 #define FW_CHNET_IFACE_ADDR_MAX 3 6940 6941 enum fw_chnet_iface_cmd_subop { 6942 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 6943 6944 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 6945 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 6946 6947 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 6948 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 6949 6950 FW_CHNET_IFACE_CMD_SUBOP_MAX, 6951 }; 6952 6953 struct fw_chnet_iface_cmd { 6954 __be32 op_to_portid; 6955 __be32 retval_len16; 6956 __u8 subop; 6957 __u8 r2[3]; 6958 __be32 ifid_ifstate; 6959 __be16 mtu; 6960 __be16 vlanid; 6961 __be32 r3; 6962 __be16 r4; 6963 __u8 mac[6]; 6964 }; 6965 6966 #define S_FW_CHNET_IFACE_CMD_PORTID 0 6967 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 6968 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 6969 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 6970 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 6971 6972 #define S_FW_CHNET_IFACE_CMD_IFID 8 6973 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 6974 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 6975 #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 6976 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 6977 6978 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 6979 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 6980 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 6981 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 6982 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 6983 6984 /****************************************************************************** 6985 * F O F C O E C O M M A N D s 6986 ************************************/ 6987 6988 struct fw_fcoe_res_info_cmd { 6989 __be32 op_to_read; 6990 __be32 retval_len16; 6991 __be16 e_d_tov; 6992 __be16 r_a_tov_seq; 6993 __be16 r_a_tov_els; 6994 __be16 r_r_tov; 6995 __be32 max_xchgs; 6996 __be32 max_ssns; 6997 __be32 used_xchgs; 6998 __be32 used_ssns; 6999 __be32 max_fcfs; 7000 __be32 max_vnps; 7001 __be32 used_fcfs; 7002 __be32 used_vnps; 7003 }; 7004 7005 struct fw_fcoe_link_cmd { 7006 __be32 op_to_portid; 7007 __be32 retval_len16; 7008 __be32 sub_opcode_fcfi; 7009 __u8 r3; 7010 __u8 lstatus; 7011 __be16 flags; 7012 __u8 r4; 7013 __u8 set_vlan; 7014 __be16 vlan_id; 7015 __be32 vnpi_pkd; 7016 __be16 r6; 7017 __u8 phy_mac[6]; 7018 __u8 vnport_wwnn[8]; 7019 __u8 vnport_wwpn[8]; 7020 }; 7021 7022 #define S_FW_FCOE_LINK_CMD_PORTID 0 7023 #define M_FW_FCOE_LINK_CMD_PORTID 0xf 7024 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 7025 #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 7026 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 7027 7028 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 7029 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 7030 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 7031 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 7032 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 7033 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 7034 7035 #define S_FW_FCOE_LINK_CMD_FCFI 0 7036 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 7037 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 7038 #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 7039 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 7040 7041 #define S_FW_FCOE_LINK_CMD_VNPI 0 7042 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 7043 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 7044 #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 7045 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 7046 7047 struct fw_fcoe_vnp_cmd { 7048 __be32 op_to_fcfi; 7049 __be32 alloc_to_len16; 7050 __be32 gen_wwn_to_vnpi; 7051 __be32 vf_id; 7052 __be16 iqid; 7053 __u8 vnport_mac[6]; 7054 __u8 vnport_wwnn[8]; 7055 __u8 vnport_wwpn[8]; 7056 __u8 cmn_srv_parms[16]; 7057 __u8 clsp_word_0_1[8]; 7058 }; 7059 7060 #define S_FW_FCOE_VNP_CMD_FCFI 0 7061 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 7062 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 7063 #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 7064 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 7065 7066 #define S_FW_FCOE_VNP_CMD_ALLOC 31 7067 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 7068 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 7069 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 7070 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 7071 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 7072 7073 #define S_FW_FCOE_VNP_CMD_FREE 30 7074 #define M_FW_FCOE_VNP_CMD_FREE 0x1 7075 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 7076 #define G_FW_FCOE_VNP_CMD_FREE(x) \ 7077 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 7078 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 7079 7080 #define S_FW_FCOE_VNP_CMD_MODIFY 29 7081 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 7082 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 7083 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 7084 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 7085 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 7086 7087 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 7088 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 7089 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 7090 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 7091 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 7092 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 7093 7094 #define S_FW_FCOE_VNP_CMD_PERSIST 21 7095 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 7096 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 7097 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 7098 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 7099 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 7100 7101 #define S_FW_FCOE_VNP_CMD_VFID_EN 20 7102 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 7103 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 7104 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 7105 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 7106 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 7107 7108 #define S_FW_FCOE_VNP_CMD_VNPI 0 7109 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 7110 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 7111 #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 7112 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 7113 7114 struct fw_fcoe_sparams_cmd { 7115 __be32 op_to_portid; 7116 __be32 retval_len16; 7117 __u8 r3[7]; 7118 __u8 cos; 7119 __u8 lport_wwnn[8]; 7120 __u8 lport_wwpn[8]; 7121 __u8 cmn_srv_parms[16]; 7122 __u8 cls_srv_parms[16]; 7123 }; 7124 7125 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 7126 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 7127 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 7128 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 7129 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 7130 7131 struct fw_fcoe_stats_cmd { 7132 __be32 op_to_flowid; 7133 __be32 free_to_len16; 7134 union fw_fcoe_stats { 7135 struct fw_fcoe_stats_ctl { 7136 __u8 nstats_port; 7137 __u8 port_valid_ix; 7138 __be16 r6; 7139 __be32 r7; 7140 __be64 stat0; 7141 __be64 stat1; 7142 __be64 stat2; 7143 __be64 stat3; 7144 __be64 stat4; 7145 __be64 stat5; 7146 } ctl; 7147 struct fw_fcoe_port_stats { 7148 __be64 tx_bcast_bytes; 7149 __be64 tx_bcast_frames; 7150 __be64 tx_mcast_bytes; 7151 __be64 tx_mcast_frames; 7152 __be64 tx_ucast_bytes; 7153 __be64 tx_ucast_frames; 7154 __be64 tx_drop_frames; 7155 __be64 tx_offload_bytes; 7156 __be64 tx_offload_frames; 7157 __be64 rx_bcast_bytes; 7158 __be64 rx_bcast_frames; 7159 __be64 rx_mcast_bytes; 7160 __be64 rx_mcast_frames; 7161 __be64 rx_ucast_bytes; 7162 __be64 rx_ucast_frames; 7163 __be64 rx_err_frames; 7164 } port_stats; 7165 struct fw_fcoe_fcf_stats { 7166 __be32 fip_tx_bytes; 7167 __be32 fip_tx_fr; 7168 __be64 fcf_ka; 7169 __be64 mcast_adv_rcvd; 7170 __be16 ucast_adv_rcvd; 7171 __be16 sol_sent; 7172 __be16 vlan_req; 7173 __be16 vlan_rpl; 7174 __be16 clr_vlink; 7175 __be16 link_down; 7176 __be16 link_up; 7177 __be16 logo; 7178 __be16 flogi_req; 7179 __be16 flogi_rpl; 7180 __be16 fdisc_req; 7181 __be16 fdisc_rpl; 7182 __be16 fka_prd_chg; 7183 __be16 fc_map_chg; 7184 __be16 vfid_chg; 7185 __u8 no_fka_req; 7186 __u8 no_vnp; 7187 } fcf_stats; 7188 struct fw_fcoe_pcb_stats { 7189 __be64 tx_bytes; 7190 __be64 tx_frames; 7191 __be64 rx_bytes; 7192 __be64 rx_frames; 7193 __be32 vnp_ka; 7194 __be32 unsol_els_rcvd; 7195 __be64 unsol_cmd_rcvd; 7196 __be16 implicit_logo; 7197 __be16 flogi_inv_sparm; 7198 __be16 fdisc_inv_sparm; 7199 __be16 flogi_rjt; 7200 __be16 fdisc_rjt; 7201 __be16 no_ssn; 7202 __be16 mac_flt_fail; 7203 __be16 inv_fr_rcvd; 7204 } pcb_stats; 7205 struct fw_fcoe_scb_stats { 7206 __be64 tx_bytes; 7207 __be64 tx_frames; 7208 __be64 rx_bytes; 7209 __be64 rx_frames; 7210 __be32 host_abrt_req; 7211 __be32 adap_auto_abrt; 7212 __be32 adap_abrt_rsp; 7213 __be32 host_ios_req; 7214 __be16 ssn_offl_ios; 7215 __be16 ssn_not_rdy_ios; 7216 __u8 rx_data_ddp_err; 7217 __u8 ddp_flt_set_err; 7218 __be16 rx_data_fr_err; 7219 __u8 bad_st_abrt_req; 7220 __u8 no_io_abrt_req; 7221 __u8 abort_tmo; 7222 __u8 abort_tmo_2; 7223 __be32 abort_req; 7224 __u8 no_ppod_res_tmo; 7225 __u8 bp_tmo; 7226 __u8 adap_auto_cls; 7227 __u8 no_io_cls_req; 7228 __be32 host_cls_req; 7229 __be64 unsol_cmd_rcvd; 7230 __be32 plogi_req_rcvd; 7231 __be32 prli_req_rcvd; 7232 __be16 logo_req_rcvd; 7233 __be16 prlo_req_rcvd; 7234 __be16 plogi_rjt_rcvd; 7235 __be16 prli_rjt_rcvd; 7236 __be32 adisc_req_rcvd; 7237 __be32 rscn_rcvd; 7238 __be32 rrq_req_rcvd; 7239 __be32 unsol_els_rcvd; 7240 __u8 adisc_rjt_rcvd; 7241 __u8 scr_rjt; 7242 __u8 ct_rjt; 7243 __u8 inval_bls_rcvd; 7244 __be32 ba_rjt_rcvd; 7245 } scb_stats; 7246 } u; 7247 }; 7248 7249 #define S_FW_FCOE_STATS_CMD_FLOWID 0 7250 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 7251 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 7252 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 7253 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 7254 7255 #define S_FW_FCOE_STATS_CMD_FREE 30 7256 #define M_FW_FCOE_STATS_CMD_FREE 0x1 7257 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 7258 #define G_FW_FCOE_STATS_CMD_FREE(x) \ 7259 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 7260 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 7261 7262 #define S_FW_FCOE_STATS_CMD_NSTATS 4 7263 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 7264 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 7265 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 7266 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 7267 7268 #define S_FW_FCOE_STATS_CMD_PORT 0 7269 #define M_FW_FCOE_STATS_CMD_PORT 0x3 7270 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 7271 #define G_FW_FCOE_STATS_CMD_PORT(x) \ 7272 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 7273 7274 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 7275 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 7276 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7277 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 7278 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7279 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 7280 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 7281 7282 #define S_FW_FCOE_STATS_CMD_IX 0 7283 #define M_FW_FCOE_STATS_CMD_IX 0x3f 7284 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 7285 #define G_FW_FCOE_STATS_CMD_IX(x) \ 7286 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 7287 7288 struct fw_fcoe_fcf_cmd { 7289 __be32 op_to_fcfi; 7290 __be32 retval_len16; 7291 __be16 priority_pkd; 7292 __u8 mac[6]; 7293 __u8 name_id[8]; 7294 __u8 fabric[8]; 7295 __be16 vf_id; 7296 __be16 max_fcoe_size; 7297 __u8 vlan_id; 7298 __u8 fc_map[3]; 7299 __be32 fka_adv; 7300 __be32 r6; 7301 __u8 r7_hi; 7302 __u8 fpma_to_portid; 7303 __u8 spma_mac[6]; 7304 __be64 r8; 7305 }; 7306 7307 #define S_FW_FCOE_FCF_CMD_FCFI 0 7308 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 7309 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 7310 #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 7311 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 7312 7313 #define S_FW_FCOE_FCF_CMD_PRIORITY 0 7314 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 7315 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 7316 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 7317 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 7318 7319 #define S_FW_FCOE_FCF_CMD_FPMA 6 7320 #define M_FW_FCOE_FCF_CMD_FPMA 0x1 7321 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 7322 #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 7323 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 7324 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 7325 7326 #define S_FW_FCOE_FCF_CMD_SPMA 5 7327 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 7328 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 7329 #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 7330 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 7331 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 7332 7333 #define S_FW_FCOE_FCF_CMD_LOGIN 4 7334 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 7335 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 7336 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 7337 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 7338 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 7339 7340 #define S_FW_FCOE_FCF_CMD_PORTID 0 7341 #define M_FW_FCOE_FCF_CMD_PORTID 0xf 7342 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 7343 #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 7344 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 7345 7346 /****************************************************************************** 7347 * E R R O R a n d D E B U G C O M M A N D s 7348 ******************************************************/ 7349 7350 enum fw_error_type { 7351 FW_ERROR_TYPE_EXCEPTION = 0x0, 7352 FW_ERROR_TYPE_HWMODULE = 0x1, 7353 FW_ERROR_TYPE_WR = 0x2, 7354 FW_ERROR_TYPE_ACL = 0x3, 7355 }; 7356 7357 struct fw_error_cmd { 7358 __be32 op_to_type; 7359 __be32 len16_pkd; 7360 union fw_error { 7361 struct fw_error_exception { 7362 __be32 info[6]; 7363 } exception; 7364 struct fw_error_hwmodule { 7365 __be32 regaddr; 7366 __be32 regval; 7367 } hwmodule; 7368 struct fw_error_wr { 7369 __be16 cidx; 7370 __be16 pfn_vfn; 7371 __be32 eqid; 7372 __u8 wrhdr[16]; 7373 } wr; 7374 struct fw_error_acl { 7375 __be16 cidx; 7376 __be16 pfn_vfn; 7377 __be32 eqid; 7378 __be16 mv_pkd; 7379 __u8 val[6]; 7380 __be64 r4; 7381 } acl; 7382 } u; 7383 }; 7384 7385 #define S_FW_ERROR_CMD_FATAL 4 7386 #define M_FW_ERROR_CMD_FATAL 0x1 7387 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 7388 #define G_FW_ERROR_CMD_FATAL(x) \ 7389 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 7390 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 7391 7392 #define S_FW_ERROR_CMD_TYPE 0 7393 #define M_FW_ERROR_CMD_TYPE 0xf 7394 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 7395 #define G_FW_ERROR_CMD_TYPE(x) \ 7396 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 7397 7398 #define S_FW_ERROR_CMD_PFN 8 7399 #define M_FW_ERROR_CMD_PFN 0x7 7400 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7401 #define G_FW_ERROR_CMD_PFN(x) \ 7402 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7403 7404 #define S_FW_ERROR_CMD_VFN 0 7405 #define M_FW_ERROR_CMD_VFN 0xff 7406 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7407 #define G_FW_ERROR_CMD_VFN(x) \ 7408 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7409 7410 #define S_FW_ERROR_CMD_PFN 8 7411 #define M_FW_ERROR_CMD_PFN 0x7 7412 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7413 #define G_FW_ERROR_CMD_PFN(x) \ 7414 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7415 7416 #define S_FW_ERROR_CMD_VFN 0 7417 #define M_FW_ERROR_CMD_VFN 0xff 7418 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7419 #define G_FW_ERROR_CMD_VFN(x) \ 7420 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7421 7422 #define S_FW_ERROR_CMD_MV 15 7423 #define M_FW_ERROR_CMD_MV 0x1 7424 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 7425 #define G_FW_ERROR_CMD_MV(x) \ 7426 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 7427 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 7428 7429 struct fw_debug_cmd { 7430 __be32 op_type; 7431 __be32 len16_pkd; 7432 union fw_debug { 7433 struct fw_debug_assert { 7434 __be32 fcid; 7435 __be32 line; 7436 __be32 x; 7437 __be32 y; 7438 __u8 filename_0_7[8]; 7439 __u8 filename_8_15[8]; 7440 __be64 r3; 7441 } assert; 7442 struct fw_debug_prt { 7443 __be16 dprtstridx; 7444 __be16 r3[3]; 7445 __be32 dprtstrparam0; 7446 __be32 dprtstrparam1; 7447 __be32 dprtstrparam2; 7448 __be32 dprtstrparam3; 7449 } prt; 7450 } u; 7451 }; 7452 7453 #define S_FW_DEBUG_CMD_TYPE 0 7454 #define M_FW_DEBUG_CMD_TYPE 0xff 7455 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 7456 #define G_FW_DEBUG_CMD_TYPE(x) \ 7457 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 7458 7459 /****************************************************************************** 7460 * P C I E F W R E G I S T E R 7461 **************************************/ 7462 7463 enum pcie_fw_eval { 7464 PCIE_FW_EVAL_CRASH = 0, 7465 PCIE_FW_EVAL_PREP = 1, 7466 PCIE_FW_EVAL_CONF = 2, 7467 PCIE_FW_EVAL_INIT = 3, 7468 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 7469 PCIE_FW_EVAL_OVERHEAT = 5, 7470 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 7471 }; 7472 7473 /** 7474 * Register definitions for the PCIE_FW register which the firmware uses 7475 * to retain status across RESETs. This register should be considered 7476 * as a READ-ONLY register for Host Software and only to be used to 7477 * track firmware initialization/error state, etc. 7478 */ 7479 #define S_PCIE_FW_ERR 31 7480 #define M_PCIE_FW_ERR 0x1 7481 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 7482 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 7483 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 7484 7485 #define S_PCIE_FW_INIT 30 7486 #define M_PCIE_FW_INIT 0x1 7487 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 7488 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 7489 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 7490 7491 #define S_PCIE_FW_HALT 29 7492 #define M_PCIE_FW_HALT 0x1 7493 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 7494 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 7495 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 7496 7497 #define S_PCIE_FW_EVAL 24 7498 #define M_PCIE_FW_EVAL 0x7 7499 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 7500 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 7501 7502 #define S_PCIE_FW_STAGE 21 7503 #define M_PCIE_FW_STAGE 0x7 7504 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 7505 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 7506 7507 #define S_PCIE_FW_ASYNCNOT_VLD 20 7508 #define M_PCIE_FW_ASYNCNOT_VLD 0x1 7509 #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 7510 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 7511 #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 7512 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 7513 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 7514 7515 #define S_PCIE_FW_ASYNCNOTINT 19 7516 #define M_PCIE_FW_ASYNCNOTINT 0x1 7517 #define V_PCIE_FW_ASYNCNOTINT(x) \ 7518 ((x) << S_PCIE_FW_ASYNCNOTINT) 7519 #define G_PCIE_FW_ASYNCNOTINT(x) \ 7520 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 7521 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 7522 7523 #define S_PCIE_FW_ASYNCNOT 16 7524 #define M_PCIE_FW_ASYNCNOT 0x7 7525 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 7526 #define G_PCIE_FW_ASYNCNOT(x) \ 7527 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 7528 7529 #define S_PCIE_FW_MASTER_VLD 15 7530 #define M_PCIE_FW_MASTER_VLD 0x1 7531 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 7532 #define G_PCIE_FW_MASTER_VLD(x) \ 7533 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 7534 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 7535 7536 #define S_PCIE_FW_MASTER 12 7537 #define M_PCIE_FW_MASTER 0x7 7538 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 7539 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 7540 7541 #define S_PCIE_FW_RESET_VLD 11 7542 #define M_PCIE_FW_RESET_VLD 0x1 7543 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 7544 #define G_PCIE_FW_RESET_VLD(x) \ 7545 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 7546 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 7547 7548 #define S_PCIE_FW_RESET 8 7549 #define M_PCIE_FW_RESET 0x7 7550 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 7551 #define G_PCIE_FW_RESET(x) \ 7552 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 7553 7554 #define S_PCIE_FW_REGISTERED 0 7555 #define M_PCIE_FW_REGISTERED 0xff 7556 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 7557 #define G_PCIE_FW_REGISTERED(x) \ 7558 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 7559 7560 7561 /****************************************************************************** 7562 * B I N A R Y H E A D E R F O R M A T 7563 **********************************************/ 7564 7565 /* 7566 * firmware binary header format 7567 */ 7568 struct fw_hdr { 7569 __u8 ver; 7570 __u8 chip; /* terminator chip family */ 7571 __be16 len512; /* bin length in units of 512-bytes */ 7572 __be32 fw_ver; /* firmware version */ 7573 __be32 tp_microcode_ver; /* tcp processor microcode version */ 7574 __u8 intfver_nic; 7575 __u8 intfver_vnic; 7576 __u8 intfver_ofld; 7577 __u8 intfver_ri; 7578 __u8 intfver_iscsipdu; 7579 __u8 intfver_iscsi; 7580 __u8 intfver_fcoepdu; 7581 __u8 intfver_fcoe; 7582 __u32 reserved2; 7583 __u32 reserved3; 7584 __u32 reserved4; 7585 __be32 flags; 7586 __be32 reserved6[23]; 7587 }; 7588 7589 enum fw_hdr_chip { 7590 FW_HDR_CHIP_T4, 7591 FW_HDR_CHIP_T5 7592 }; 7593 7594 #define S_FW_HDR_FW_VER_MAJOR 24 7595 #define M_FW_HDR_FW_VER_MAJOR 0xff 7596 #define V_FW_HDR_FW_VER_MAJOR(x) \ 7597 ((x) << S_FW_HDR_FW_VER_MAJOR) 7598 #define G_FW_HDR_FW_VER_MAJOR(x) \ 7599 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 7600 7601 #define S_FW_HDR_FW_VER_MINOR 16 7602 #define M_FW_HDR_FW_VER_MINOR 0xff 7603 #define V_FW_HDR_FW_VER_MINOR(x) \ 7604 ((x) << S_FW_HDR_FW_VER_MINOR) 7605 #define G_FW_HDR_FW_VER_MINOR(x) \ 7606 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 7607 7608 #define S_FW_HDR_FW_VER_MICRO 8 7609 #define M_FW_HDR_FW_VER_MICRO 0xff 7610 #define V_FW_HDR_FW_VER_MICRO(x) \ 7611 ((x) << S_FW_HDR_FW_VER_MICRO) 7612 #define G_FW_HDR_FW_VER_MICRO(x) \ 7613 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 7614 7615 #define S_FW_HDR_FW_VER_BUILD 0 7616 #define M_FW_HDR_FW_VER_BUILD 0xff 7617 #define V_FW_HDR_FW_VER_BUILD(x) \ 7618 ((x) << S_FW_HDR_FW_VER_BUILD) 7619 #define G_FW_HDR_FW_VER_BUILD(x) \ 7620 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 7621 7622 enum { 7623 FW_HDR_INTFVER_NIC = 0x00, 7624 FW_HDR_INTFVER_VNIC = 0x00, 7625 FW_HDR_INTFVER_OFLD = 0x00, 7626 FW_HDR_INTFVER_RI = 0x00, 7627 FW_HDR_INTFVER_ISCSIPDU = 0x00, 7628 FW_HDR_INTFVER_ISCSI = 0x00, 7629 FW_HDR_INTFVER_FCOEPDU = 0x00, 7630 FW_HDR_INTFVER_FCOE = 0x00, 7631 }; 7632 7633 enum fw_hdr_flags { 7634 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 7635 }; 7636 7637 #endif /* _T4FW_INTERFACE_H_ */ 7638