1 /*- 2 * Copyright (c) 2012-2017 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _T4FW_INTERFACE_H_ 31 #define _T4FW_INTERFACE_H_ 32 33 /****************************************************************************** 34 * R E T U R N V A L U E S 35 ********************************/ 36 37 enum fw_retval { 38 FW_SUCCESS = 0, /* completed successfully */ 39 FW_EPERM = 1, /* operation not permitted */ 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ 48 FW_ENODEV = 19, /* no such device */ 49 FW_EINVAL = 22, /* invalid argument */ 50 FW_ENOSPC = 28, /* no space left on device */ 51 FW_ENOSYS = 38, /* functionality not implemented */ 52 FW_ENODATA = 61, /* no data available */ 53 FW_EPROTO = 71, /* protocol error */ 54 FW_EADDRINUSE = 98, /* address already in use */ 55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 56 FW_ENETDOWN = 100, /* network is down */ 57 FW_ENETUNREACH = 101, /* network is unreachable */ 58 FW_ENOBUFS = 105, /* no buffer space available */ 59 FW_ETIMEDOUT = 110, /* timeout */ 60 FW_EINPROGRESS = 115, /* fw internal */ 61 FW_SCSI_ABORT_REQUESTED = 128, /* */ 62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 63 FW_SCSI_ABORTED = 130, /* */ 64 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 65 FW_ERR_LINK_DOWN = 132, /* */ 66 FW_RDEV_NOT_READY = 133, /* */ 67 FW_ERR_RDEV_LOST = 134, /* */ 68 FW_ERR_RDEV_LOGO = 135, /* */ 69 FW_FCOE_NO_XCHG = 136, /* */ 70 FW_SCSI_RSP_ERR = 137, /* */ 71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 73 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 74 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 76 FW_SCSI_IO_BLOCK = 143, /* IO is going to be blocked due to resource failure */ 77 }; 78 79 /****************************************************************************** 80 * M E M O R Y T Y P E s 81 ******************************/ 82 83 enum fw_memtype { 84 FW_MEMTYPE_EDC0 = 0x0, 85 FW_MEMTYPE_EDC1 = 0x1, 86 FW_MEMTYPE_EXTMEM = 0x2, 87 FW_MEMTYPE_FLASH = 0x4, 88 FW_MEMTYPE_INTERNAL = 0x5, 89 FW_MEMTYPE_EXTMEM1 = 0x6, 90 FW_MEMTYPE_HMA = 0x7, 91 }; 92 93 /****************************************************************************** 94 * W O R K R E Q U E S T s 95 ********************************/ 96 97 enum fw_wr_opcodes { 98 FW_FRAG_WR = 0x1d, 99 FW_FILTER_WR = 0x02, 100 FW_ULPTX_WR = 0x04, 101 FW_TP_WR = 0x05, 102 FW_ETH_TX_PKT_WR = 0x08, 103 FW_ETH_TX_PKT2_WR = 0x44, 104 FW_ETH_TX_PKTS_WR = 0x09, 105 FW_ETH_TX_PKTS2_WR = 0x78, 106 FW_ETH_TX_EO_WR = 0x1c, 107 FW_EQ_FLUSH_WR = 0x1b, 108 FW_OFLD_CONNECTION_WR = 0x2f, 109 FW_FLOWC_WR = 0x0a, 110 FW_OFLD_TX_DATA_WR = 0x0b, 111 FW_CMD_WR = 0x10, 112 FW_ETH_TX_PKT_VM_WR = 0x11, 113 FW_RI_RES_WR = 0x0c, 114 FW_RI_RDMA_WRITE_WR = 0x14, 115 FW_RI_SEND_WR = 0x15, 116 FW_RI_RDMA_READ_WR = 0x16, 117 FW_RI_RECV_WR = 0x17, 118 FW_RI_BIND_MW_WR = 0x18, 119 FW_RI_FR_NSMR_WR = 0x19, 120 FW_RI_FR_NSMR_TPTE_WR = 0x20, 121 FW_RI_RDMA_WRITE_CMPL_WR = 0x21, 122 FW_RI_INV_LSTAG_WR = 0x1a, 123 FW_RI_SEND_IMMEDIATE_WR = 0x15, 124 FW_RI_ATOMIC_WR = 0x16, 125 FW_RI_WR = 0x0d, 126 FW_CHNET_IFCONF_WR = 0x6b, 127 FW_RDEV_WR = 0x38, 128 FW_FOISCSI_NODE_WR = 0x60, 129 FW_FOISCSI_CTRL_WR = 0x6a, 130 FW_FOISCSI_CHAP_WR = 0x6c, 131 FW_FCOE_ELS_CT_WR = 0x30, 132 FW_SCSI_WRITE_WR = 0x31, 133 FW_SCSI_READ_WR = 0x32, 134 FW_SCSI_CMD_WR = 0x33, 135 FW_SCSI_ABRT_CLS_WR = 0x34, 136 FW_SCSI_TGT_ACC_WR = 0x35, 137 FW_SCSI_TGT_XMIT_WR = 0x36, 138 FW_SCSI_TGT_RSP_WR = 0x37, 139 FW_POFCOE_TCB_WR = 0x42, 140 FW_POFCOE_ULPTX_WR = 0x43, 141 FW_ISCSI_TX_DATA_WR = 0x45, 142 FW_PTP_TX_PKT_WR = 0x46, 143 FW_TLSTX_DATA_WR = 0x68, 144 FW_CRYPTO_LOOKASIDE_WR = 0x6d, 145 FW_COISCSI_TGT_WR = 0x70, 146 FW_COISCSI_TGT_CONN_WR = 0x71, 147 FW_COISCSI_TGT_XMIT_WR = 0x72, 148 FW_COISCSI_STATS_WR = 0x73, 149 FW_ISNS_WR = 0x75, 150 FW_ISNS_XMIT_WR = 0x76, 151 FW_FILTER2_WR = 0x77, 152 FW_LASTC2E_WR = 0x80 153 }; 154 155 /* 156 * Generic work request header flit0 157 */ 158 struct fw_wr_hdr { 159 __be32 hi; 160 __be32 lo; 161 }; 162 163 /* work request opcode (hi) 164 */ 165 #define S_FW_WR_OP 24 166 #define M_FW_WR_OP 0xff 167 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 168 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 169 170 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 171 */ 172 #define S_FW_WR_ATOMIC 23 173 #define M_FW_WR_ATOMIC 0x1 174 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 175 #define G_FW_WR_ATOMIC(x) \ 176 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 177 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 178 179 /* flush flag (hi) - firmware flushes flushable work request buffered 180 * in the flow context. 181 */ 182 #define S_FW_WR_FLUSH 22 183 #define M_FW_WR_FLUSH 0x1 184 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 185 #define G_FW_WR_FLUSH(x) \ 186 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 187 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 188 189 /* completion flag (hi) - firmware generates a cpl_fw6_ack 190 */ 191 #define S_FW_WR_COMPL 21 192 #define M_FW_WR_COMPL 0x1 193 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 194 #define G_FW_WR_COMPL(x) \ 195 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 196 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 197 198 199 /* work request immediate data lengh (hi) 200 */ 201 #define S_FW_WR_IMMDLEN 0 202 #define M_FW_WR_IMMDLEN 0xff 203 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 204 #define G_FW_WR_IMMDLEN(x) \ 205 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 206 207 /* egress queue status update to associated ingress queue entry (lo) 208 */ 209 #define S_FW_WR_EQUIQ 31 210 #define M_FW_WR_EQUIQ 0x1 211 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 212 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 213 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 214 215 /* egress queue status update to egress queue status entry (lo) 216 */ 217 #define S_FW_WR_EQUEQ 30 218 #define M_FW_WR_EQUEQ 0x1 219 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 220 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 221 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 222 223 /* flow context identifier (lo) 224 */ 225 #define S_FW_WR_FLOWID 8 226 #define M_FW_WR_FLOWID 0xfffff 227 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 228 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 229 230 /* length in units of 16-bytes (lo) 231 */ 232 #define S_FW_WR_LEN16 0 233 #define M_FW_WR_LEN16 0xff 234 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 235 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 236 237 struct fw_frag_wr { 238 __be32 op_to_fragoff16; 239 __be32 flowid_len16; 240 __be64 r4; 241 }; 242 243 #define S_FW_FRAG_WR_EOF 15 244 #define M_FW_FRAG_WR_EOF 0x1 245 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 246 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 247 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 248 249 #define S_FW_FRAG_WR_FRAGOFF16 8 250 #define M_FW_FRAG_WR_FRAGOFF16 0x7f 251 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 252 #define G_FW_FRAG_WR_FRAGOFF16(x) \ 253 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 254 255 /* valid filter configurations for compressed tuple 256 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 257 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 258 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 259 * OV - Outer VLAN/VNIC_ID, 260 */ 261 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 262 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 263 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 264 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 265 #define HW_TPL_FR_MT_E_PR_T 0x370 266 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 267 #define HW_TPL_FR_MT_E_T_P_FC 0X353 268 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 269 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 270 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 271 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 272 #define HW_TPL_FR_M_E_PR_FC 0X2E1 273 #define HW_TPL_FR_M_E_T_FC 0X2D1 274 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 275 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 276 #define HW_TPL_FR_M_T_IV_FC 0X299 277 #define HW_TPL_FR_M_T_OV_FC 0X295 278 #define HW_TPL_FR_E_PR_T_P 0X272 279 #define HW_TPL_FR_E_PR_T_FC 0X271 280 #define HW_TPL_FR_E_IV_FC 0X249 281 #define HW_TPL_FR_E_OV_FC 0X245 282 #define HW_TPL_FR_PR_T_IV_FC 0X239 283 #define HW_TPL_FR_PR_T_OV_FC 0X235 284 #define HW_TPL_FR_IV_OV_FC 0X20D 285 #define HW_TPL_MT_M_E_PR 0X1E0 286 #define HW_TPL_MT_M_E_T 0X1D0 287 #define HW_TPL_MT_E_PR_T_FC 0X171 288 #define HW_TPL_MT_E_IV 0X148 289 #define HW_TPL_MT_E_OV 0X144 290 #define HW_TPL_MT_PR_T_IV 0X138 291 #define HW_TPL_MT_PR_T_OV 0X134 292 #define HW_TPL_M_E_PR_P 0X0E2 293 #define HW_TPL_M_E_T_P 0X0D2 294 #define HW_TPL_E_PR_T_P_FC 0X073 295 #define HW_TPL_E_IV_P 0X04A 296 #define HW_TPL_E_OV_P 0X046 297 #define HW_TPL_PR_T_IV_P 0X03A 298 #define HW_TPL_PR_T_OV_P 0X036 299 300 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 301 enum fw_filter_wr_cookie { 302 FW_FILTER_WR_SUCCESS, 303 FW_FILTER_WR_FLT_ADDED, 304 FW_FILTER_WR_FLT_DELETED, 305 FW_FILTER_WR_SMT_TBL_FULL, 306 FW_FILTER_WR_EINVAL, 307 }; 308 309 enum fw_filter_wr_nat_mode { 310 FW_FILTER_WR_NATMODE_NONE = 0, 311 FW_FILTER_WR_NATMODE_DIP , 312 FW_FILTER_WR_NATMODE_DIPDP, 313 FW_FILTER_WR_NATMODE_DIPDPSIP, 314 FW_FILTER_WR_NATMODE_DIPDPSP, 315 FW_FILTER_WR_NATMODE_SIPSP, 316 FW_FILTER_WR_NATMODE_DIPSIPSP, 317 FW_FILTER_WR_NATMODE_FOURTUPLE, 318 }; 319 320 struct fw_filter_wr { 321 __be32 op_pkd; 322 __be32 len16_pkd; 323 __be64 r3; 324 __be32 tid_to_iq; 325 __be32 del_filter_to_l2tix; 326 __be16 ethtype; 327 __be16 ethtypem; 328 __u8 frag_to_ovlan_vldm; 329 __u8 smac_sel; 330 __be16 rx_chan_rx_rpl_iq; 331 __be32 maci_to_matchtypem; 332 __u8 ptcl; 333 __u8 ptclm; 334 __u8 ttyp; 335 __u8 ttypm; 336 __be16 ivlan; 337 __be16 ivlanm; 338 __be16 ovlan; 339 __be16 ovlanm; 340 __u8 lip[16]; 341 __u8 lipm[16]; 342 __u8 fip[16]; 343 __u8 fipm[16]; 344 __be16 lp; 345 __be16 lpm; 346 __be16 fp; 347 __be16 fpm; 348 __be16 r7; 349 __u8 sma[6]; 350 }; 351 352 struct fw_filter2_wr { 353 __be32 op_pkd; 354 __be32 len16_pkd; 355 __be64 r3; 356 __be32 tid_to_iq; 357 __be32 del_filter_to_l2tix; 358 __be16 ethtype; 359 __be16 ethtypem; 360 __u8 frag_to_ovlan_vldm; 361 __u8 smac_sel; 362 __be16 rx_chan_rx_rpl_iq; 363 __be32 maci_to_matchtypem; 364 __u8 ptcl; 365 __u8 ptclm; 366 __u8 ttyp; 367 __u8 ttypm; 368 __be16 ivlan; 369 __be16 ivlanm; 370 __be16 ovlan; 371 __be16 ovlanm; 372 __u8 lip[16]; 373 __u8 lipm[16]; 374 __u8 fip[16]; 375 __u8 fipm[16]; 376 __be16 lp; 377 __be16 lpm; 378 __be16 fp; 379 __be16 fpm; 380 __be16 r7; 381 __u8 sma[6]; 382 __be16 r8; 383 __u8 filter_type_swapmac; 384 __u8 natmode_to_ulp_type; 385 __be16 newlport; 386 __be16 newfport; 387 __u8 newlip[16]; 388 __u8 newfip[16]; 389 __be32 natseqcheck; 390 __be32 r9; 391 __be64 r10; 392 __be64 r11; 393 __be64 r12; 394 __be64 r13; 395 }; 396 397 #define S_FW_FILTER_WR_TID 12 398 #define M_FW_FILTER_WR_TID 0xfffff 399 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 400 #define G_FW_FILTER_WR_TID(x) \ 401 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 402 403 #define S_FW_FILTER_WR_RQTYPE 11 404 #define M_FW_FILTER_WR_RQTYPE 0x1 405 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 406 #define G_FW_FILTER_WR_RQTYPE(x) \ 407 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 408 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 409 410 #define S_FW_FILTER_WR_NOREPLY 10 411 #define M_FW_FILTER_WR_NOREPLY 0x1 412 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 413 #define G_FW_FILTER_WR_NOREPLY(x) \ 414 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 415 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 416 417 #define S_FW_FILTER_WR_IQ 0 418 #define M_FW_FILTER_WR_IQ 0x3ff 419 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 420 #define G_FW_FILTER_WR_IQ(x) \ 421 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 422 423 #define S_FW_FILTER_WR_DEL_FILTER 31 424 #define M_FW_FILTER_WR_DEL_FILTER 0x1 425 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 426 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 427 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 428 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 429 430 #define S_FW_FILTER_WR_RPTTID 25 431 #define M_FW_FILTER_WR_RPTTID 0x1 432 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 433 #define G_FW_FILTER_WR_RPTTID(x) \ 434 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 435 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 436 437 #define S_FW_FILTER_WR_DROP 24 438 #define M_FW_FILTER_WR_DROP 0x1 439 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 440 #define G_FW_FILTER_WR_DROP(x) \ 441 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 442 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 443 444 #define S_FW_FILTER_WR_DIRSTEER 23 445 #define M_FW_FILTER_WR_DIRSTEER 0x1 446 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 447 #define G_FW_FILTER_WR_DIRSTEER(x) \ 448 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 449 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 450 451 #define S_FW_FILTER_WR_MASKHASH 22 452 #define M_FW_FILTER_WR_MASKHASH 0x1 453 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 454 #define G_FW_FILTER_WR_MASKHASH(x) \ 455 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 456 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 457 458 #define S_FW_FILTER_WR_DIRSTEERHASH 21 459 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 460 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 461 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 462 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 463 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 464 465 #define S_FW_FILTER_WR_LPBK 20 466 #define M_FW_FILTER_WR_LPBK 0x1 467 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 468 #define G_FW_FILTER_WR_LPBK(x) \ 469 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 470 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 471 472 #define S_FW_FILTER_WR_DMAC 19 473 #define M_FW_FILTER_WR_DMAC 0x1 474 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 475 #define G_FW_FILTER_WR_DMAC(x) \ 476 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 477 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 478 479 #define S_FW_FILTER_WR_SMAC 18 480 #define M_FW_FILTER_WR_SMAC 0x1 481 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 482 #define G_FW_FILTER_WR_SMAC(x) \ 483 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 484 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 485 486 #define S_FW_FILTER_WR_INSVLAN 17 487 #define M_FW_FILTER_WR_INSVLAN 0x1 488 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 489 #define G_FW_FILTER_WR_INSVLAN(x) \ 490 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 491 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 492 493 #define S_FW_FILTER_WR_RMVLAN 16 494 #define M_FW_FILTER_WR_RMVLAN 0x1 495 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 496 #define G_FW_FILTER_WR_RMVLAN(x) \ 497 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 498 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 499 500 #define S_FW_FILTER_WR_HITCNTS 15 501 #define M_FW_FILTER_WR_HITCNTS 0x1 502 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 503 #define G_FW_FILTER_WR_HITCNTS(x) \ 504 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 505 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 506 507 #define S_FW_FILTER_WR_TXCHAN 13 508 #define M_FW_FILTER_WR_TXCHAN 0x3 509 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 510 #define G_FW_FILTER_WR_TXCHAN(x) \ 511 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 512 513 #define S_FW_FILTER_WR_PRIO 12 514 #define M_FW_FILTER_WR_PRIO 0x1 515 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 516 #define G_FW_FILTER_WR_PRIO(x) \ 517 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 518 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 519 520 #define S_FW_FILTER_WR_L2TIX 0 521 #define M_FW_FILTER_WR_L2TIX 0xfff 522 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 523 #define G_FW_FILTER_WR_L2TIX(x) \ 524 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 525 526 #define S_FW_FILTER_WR_FRAG 7 527 #define M_FW_FILTER_WR_FRAG 0x1 528 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 529 #define G_FW_FILTER_WR_FRAG(x) \ 530 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 531 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 532 533 #define S_FW_FILTER_WR_FRAGM 6 534 #define M_FW_FILTER_WR_FRAGM 0x1 535 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 536 #define G_FW_FILTER_WR_FRAGM(x) \ 537 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 538 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 539 540 #define S_FW_FILTER_WR_IVLAN_VLD 5 541 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 542 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 543 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 544 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 545 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 546 547 #define S_FW_FILTER_WR_OVLAN_VLD 4 548 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 549 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 550 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 551 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 552 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 553 554 #define S_FW_FILTER_WR_IVLAN_VLDM 3 555 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 556 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 557 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 558 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 559 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 560 561 #define S_FW_FILTER_WR_OVLAN_VLDM 2 562 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 563 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 564 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 565 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 566 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 567 568 #define S_FW_FILTER_WR_RX_CHAN 15 569 #define M_FW_FILTER_WR_RX_CHAN 0x1 570 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 571 #define G_FW_FILTER_WR_RX_CHAN(x) \ 572 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 573 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 574 575 #define S_FW_FILTER_WR_RX_RPL_IQ 0 576 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 577 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 578 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 579 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 580 581 #define S_FW_FILTER2_WR_FILTER_TYPE 1 582 #define M_FW_FILTER2_WR_FILTER_TYPE 0x1 583 #define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE) 584 #define G_FW_FILTER2_WR_FILTER_TYPE(x) \ 585 (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE) 586 #define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U) 587 588 #define S_FW_FILTER2_WR_SWAPMAC 0 589 #define M_FW_FILTER2_WR_SWAPMAC 0x1 590 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) 591 #define G_FW_FILTER2_WR_SWAPMAC(x) \ 592 (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC) 593 #define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U) 594 595 #define S_FW_FILTER2_WR_NATMODE 5 596 #define M_FW_FILTER2_WR_NATMODE 0x7 597 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 598 #define G_FW_FILTER2_WR_NATMODE(x) \ 599 (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE) 600 601 #define S_FW_FILTER2_WR_NATFLAGCHECK 4 602 #define M_FW_FILTER2_WR_NATFLAGCHECK 0x1 603 #define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK) 604 #define G_FW_FILTER2_WR_NATFLAGCHECK(x) \ 605 (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK) 606 #define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U) 607 608 #define S_FW_FILTER2_WR_ULP_TYPE 0 609 #define M_FW_FILTER2_WR_ULP_TYPE 0xf 610 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 611 #define G_FW_FILTER2_WR_ULP_TYPE(x) \ 612 (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE) 613 614 #define S_FW_FILTER_WR_MACI 23 615 #define M_FW_FILTER_WR_MACI 0x1ff 616 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 617 #define G_FW_FILTER_WR_MACI(x) \ 618 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 619 620 #define S_FW_FILTER_WR_MACIM 14 621 #define M_FW_FILTER_WR_MACIM 0x1ff 622 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 623 #define G_FW_FILTER_WR_MACIM(x) \ 624 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 625 626 #define S_FW_FILTER_WR_FCOE 13 627 #define M_FW_FILTER_WR_FCOE 0x1 628 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 629 #define G_FW_FILTER_WR_FCOE(x) \ 630 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 631 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 632 633 #define S_FW_FILTER_WR_FCOEM 12 634 #define M_FW_FILTER_WR_FCOEM 0x1 635 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 636 #define G_FW_FILTER_WR_FCOEM(x) \ 637 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 638 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 639 640 #define S_FW_FILTER_WR_PORT 9 641 #define M_FW_FILTER_WR_PORT 0x7 642 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 643 #define G_FW_FILTER_WR_PORT(x) \ 644 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 645 646 #define S_FW_FILTER_WR_PORTM 6 647 #define M_FW_FILTER_WR_PORTM 0x7 648 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 649 #define G_FW_FILTER_WR_PORTM(x) \ 650 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 651 652 #define S_FW_FILTER_WR_MATCHTYPE 3 653 #define M_FW_FILTER_WR_MATCHTYPE 0x7 654 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 655 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 656 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 657 658 #define S_FW_FILTER_WR_MATCHTYPEM 0 659 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 660 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 661 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 662 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 663 664 struct fw_ulptx_wr { 665 __be32 op_to_compl; 666 __be32 flowid_len16; 667 __u64 cookie; 668 }; 669 670 /* flag for packet type - control packet (0), data packet (1) 671 */ 672 #define S_FW_ULPTX_WR_DATA 28 673 #define M_FW_ULPTX_WR_DATA 0x1 674 #define V_FW_ULPTX_WR_DATA(x) ((x) << S_FW_ULPTX_WR_DATA) 675 #define G_FW_ULPTX_WR_DATA(x) \ 676 (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA) 677 #define F_FW_ULPTX_WR_DATA V_FW_ULPTX_WR_DATA(1U) 678 679 struct fw_tp_wr { 680 __be32 op_to_immdlen; 681 __be32 flowid_len16; 682 __u64 cookie; 683 }; 684 685 struct fw_eth_tx_pkt_wr { 686 __be32 op_immdlen; 687 __be32 equiq_to_len16; 688 __be64 r3; 689 }; 690 691 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 692 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 693 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 694 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 695 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 696 697 struct fw_eth_tx_pkt2_wr { 698 __be32 op_immdlen; 699 __be32 equiq_to_len16; 700 __be32 r3; 701 __be32 L4ChkDisable_to_IpHdrLen; 702 }; 703 704 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 705 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 706 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 707 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 708 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 709 710 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 711 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 712 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 713 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 714 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 715 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 716 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 717 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 718 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 719 720 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 721 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 722 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 723 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 724 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 725 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 726 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 727 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 728 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 729 730 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 731 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 732 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 733 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 734 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 735 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 736 737 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 738 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 739 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 740 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 741 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 742 743 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 744 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 745 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 746 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 747 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 748 749 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 750 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 751 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 752 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 753 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 754 755 struct fw_eth_tx_pkts_wr { 756 __be32 op_pkd; 757 __be32 equiq_to_len16; 758 __be32 r3; 759 __be16 plen; 760 __u8 npkt; 761 __u8 type; 762 }; 763 764 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 765 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 766 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 767 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 768 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 769 770 struct fw_eth_tx_pkt_ptp_wr { 771 __be32 op_immdlen; 772 __be32 equiq_to_len16; 773 __be64 r3; 774 }; 775 776 enum fw_eth_tx_eo_type { 777 FW_ETH_TX_EO_TYPE_UDPSEG, 778 FW_ETH_TX_EO_TYPE_TCPSEG, 779 FW_ETH_TX_EO_TYPE_NVGRESEG, 780 FW_ETH_TX_EO_TYPE_VXLANSEG, 781 FW_ETH_TX_EO_TYPE_GENEVESEG, 782 }; 783 784 struct fw_eth_tx_eo_wr { 785 __be32 op_immdlen; 786 __be32 equiq_to_len16; 787 __be64 r3; 788 union fw_eth_tx_eo { 789 struct fw_eth_tx_eo_udpseg { 790 __u8 type; 791 __u8 ethlen; 792 __be16 iplen; 793 __u8 udplen; 794 __u8 rtplen; 795 __be16 r4; 796 __be16 mss; 797 __be16 schedpktsize; 798 __be32 plen; 799 } udpseg; 800 struct fw_eth_tx_eo_tcpseg { 801 __u8 type; 802 __u8 ethlen; 803 __be16 iplen; 804 __u8 tcplen; 805 __u8 tsclk_tsoff; 806 __be16 r4; 807 __be16 mss; 808 __be16 r5; 809 __be32 plen; 810 } tcpseg; 811 struct fw_eth_tx_eo_nvgreseg { 812 __u8 type; 813 __u8 iphdroffout; 814 __be16 grehdroff; 815 __be16 iphdroffin; 816 __be16 tcphdroffin; 817 __be16 mss; 818 __be16 r4; 819 __be32 plen; 820 } nvgreseg; 821 struct fw_eth_tx_eo_vxlanseg { 822 __u8 type; 823 __u8 iphdroffout; 824 __be16 vxlanhdroff; 825 __be16 iphdroffin; 826 __be16 tcphdroffin; 827 __be16 mss; 828 __be16 r4; 829 __be32 plen; 830 831 } vxlanseg; 832 struct fw_eth_tx_eo_geneveseg { 833 __u8 type; 834 __u8 iphdroffout; 835 __be16 genevehdroff; 836 __be16 iphdroffin; 837 __be16 tcphdroffin; 838 __be16 mss; 839 __be16 r4; 840 __be32 plen; 841 } geneveseg; 842 } u; 843 }; 844 845 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0 846 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 847 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 848 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 849 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 850 851 #define S_FW_ETH_TX_EO_WR_TSCLK 6 852 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3 853 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 854 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 855 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 856 857 #define S_FW_ETH_TX_EO_WR_TSOFF 0 858 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 859 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 860 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 861 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 862 863 struct fw_eq_flush_wr { 864 __u8 opcode; 865 __u8 r1[3]; 866 __be32 equiq_to_len16; 867 __be64 r3; 868 }; 869 870 struct fw_ofld_connection_wr { 871 __be32 op_compl; 872 __be32 len16_pkd; 873 __u64 cookie; 874 __be64 r2; 875 __be64 r3; 876 struct fw_ofld_connection_le { 877 __be32 version_cpl; 878 __be32 filter; 879 __be32 r1; 880 __be16 lport; 881 __be16 pport; 882 union fw_ofld_connection_leip { 883 struct fw_ofld_connection_le_ipv4 { 884 __be32 pip; 885 __be32 lip; 886 __be64 r0; 887 __be64 r1; 888 __be64 r2; 889 } ipv4; 890 struct fw_ofld_connection_le_ipv6 { 891 __be64 pip_hi; 892 __be64 pip_lo; 893 __be64 lip_hi; 894 __be64 lip_lo; 895 } ipv6; 896 } u; 897 } le; 898 struct fw_ofld_connection_tcb { 899 __be32 t_state_to_astid; 900 __be16 cplrxdataack_cplpassacceptrpl; 901 __be16 rcv_adv; 902 __be32 rcv_nxt; 903 __be32 tx_max; 904 __be64 opt0; 905 __be32 opt2; 906 __be32 r1; 907 __be64 r2; 908 __be64 r3; 909 } tcb; 910 }; 911 912 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 913 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 914 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 915 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 916 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 917 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 918 M_FW_OFLD_CONNECTION_WR_VERSION) 919 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 920 921 #define S_FW_OFLD_CONNECTION_WR_CPL 30 922 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 923 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 924 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 925 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 926 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 927 928 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 929 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 930 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 931 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 932 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 933 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 934 M_FW_OFLD_CONNECTION_WR_T_STATE) 935 936 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 937 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 938 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 939 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 940 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 941 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 942 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 943 944 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 945 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 946 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 947 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 948 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 949 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 950 951 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 952 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 953 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 954 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 955 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 956 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 957 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 958 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 959 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 960 961 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 962 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 963 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 964 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 965 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 966 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 967 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 968 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 969 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 970 971 enum fw_flowc_mnem_tcpstate { 972 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 973 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 974 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 975 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 976 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 977 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 978 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 979 * will resend FIN - equiv ESTAB 980 */ 981 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 982 * will resend FIN but have 983 * received FIN 984 */ 985 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 986 * will resend FIN but have 987 * received FIN 988 */ 989 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 990 * waiting for FIN 991 */ 992 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 993 }; 994 995 enum fw_flowc_mnem_eostate { 996 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 997 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 998 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 999 * outstanding payload 1000 */ 1001 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 1002 * discarding outstanding payload 1003 */ 1004 }; 1005 1006 enum fw_flowc_mnem { 1007 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 1008 FW_FLOWC_MNEM_CH = 1, 1009 FW_FLOWC_MNEM_PORT = 2, 1010 FW_FLOWC_MNEM_IQID = 3, 1011 FW_FLOWC_MNEM_SNDNXT = 4, 1012 FW_FLOWC_MNEM_RCVNXT = 5, 1013 FW_FLOWC_MNEM_SNDBUF = 6, 1014 FW_FLOWC_MNEM_MSS = 7, 1015 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 1016 FW_FLOWC_MNEM_TCPSTATE = 9, 1017 FW_FLOWC_MNEM_EOSTATE = 10, 1018 FW_FLOWC_MNEM_SCHEDCLASS = 11, 1019 FW_FLOWC_MNEM_DCBPRIO = 12, 1020 FW_FLOWC_MNEM_SND_SCALE = 13, 1021 FW_FLOWC_MNEM_RCV_SCALE = 14, 1022 FW_FLOWC_MNEM_ULP_MODE = 15, 1023 FW_FLOWC_MNEM_MAX = 16, 1024 }; 1025 1026 struct fw_flowc_mnemval { 1027 __u8 mnemonic; 1028 __u8 r4[3]; 1029 __be32 val; 1030 }; 1031 1032 struct fw_flowc_wr { 1033 __be32 op_to_nparams; 1034 __be32 flowid_len16; 1035 #ifndef C99_NOT_SUPPORTED 1036 struct fw_flowc_mnemval mnemval[0]; 1037 #endif 1038 }; 1039 1040 #define S_FW_FLOWC_WR_NPARAMS 0 1041 #define M_FW_FLOWC_WR_NPARAMS 0xff 1042 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 1043 #define G_FW_FLOWC_WR_NPARAMS(x) \ 1044 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 1045 1046 struct fw_ofld_tx_data_wr { 1047 __be32 op_to_immdlen; 1048 __be32 flowid_len16; 1049 __be32 plen; 1050 __be32 lsodisable_to_flags; 1051 }; 1052 1053 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 1054 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 1055 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1056 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 1057 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1058 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 1059 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 1060 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 1061 1062 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 1063 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 1064 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1065 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1066 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1067 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1068 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 1069 1070 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 1071 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 1072 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1073 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1074 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1075 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 1076 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1077 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 1078 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 1079 1080 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0 1081 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 1082 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 1083 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 1084 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 1085 1086 1087 /* Use fw_ofld_tx_data_wr structure */ 1088 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 1089 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 1090 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1091 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1092 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1093 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1094 1095 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 1096 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 1097 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1098 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1099 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1100 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 1101 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1102 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 1103 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 1104 1105 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 1106 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 1107 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1108 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1109 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1110 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 1111 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1112 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 1113 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1114 1115 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1116 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1117 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1118 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1119 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1120 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1121 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1122 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1123 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1124 1125 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1126 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1127 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1128 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1129 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1130 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1131 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1132 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1133 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1134 1135 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1136 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1137 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1138 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1139 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1140 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1141 1142 struct fw_cmd_wr { 1143 __be32 op_dma; 1144 __be32 len16_pkd; 1145 __be64 cookie_daddr; 1146 }; 1147 1148 #define S_FW_CMD_WR_DMA 17 1149 #define M_FW_CMD_WR_DMA 0x1 1150 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1151 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1152 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1153 1154 struct fw_eth_tx_pkt_vm_wr { 1155 __be32 op_immdlen; 1156 __be32 equiq_to_len16; 1157 __be32 r3[2]; 1158 __u8 ethmacdst[6]; 1159 __u8 ethmacsrc[6]; 1160 __be16 ethtype; 1161 __be16 vlantci; 1162 }; 1163 1164 /****************************************************************************** 1165 * R I W O R K R E Q U E S T s 1166 **************************************/ 1167 1168 enum fw_ri_wr_opcode { 1169 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1170 FW_RI_READ_REQ = 0x1, 1171 FW_RI_READ_RESP = 0x2, 1172 FW_RI_SEND = 0x3, 1173 FW_RI_SEND_WITH_INV = 0x4, 1174 FW_RI_SEND_WITH_SE = 0x5, 1175 FW_RI_SEND_WITH_SE_INV = 0x6, 1176 FW_RI_TERMINATE = 0x7, 1177 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1178 FW_RI_BIND_MW = 0x9, 1179 FW_RI_FAST_REGISTER = 0xa, 1180 FW_RI_LOCAL_INV = 0xb, 1181 FW_RI_QP_MODIFY = 0xc, 1182 FW_RI_BYPASS = 0xd, 1183 FW_RI_RECEIVE = 0xe, 1184 #if 0 1185 FW_RI_SEND_IMMEDIATE = 0x8, 1186 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1187 FW_RI_ATOMIC_REQUEST = 0xa, 1188 FW_RI_ATOMIC_RESPONSE = 0xb, 1189 1190 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1191 FW_RI_FAST_REGISTER = 0xd, 1192 FW_RI_LOCAL_INV = 0xe, 1193 #endif 1194 FW_RI_SGE_EC_CR_RETURN = 0xf, 1195 FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT, 1196 }; 1197 1198 enum fw_ri_wr_flags { 1199 FW_RI_COMPLETION_FLAG = 0x01, 1200 FW_RI_NOTIFICATION_FLAG = 0x02, 1201 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1202 FW_RI_READ_FENCE_FLAG = 0x08, 1203 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1204 FW_RI_RDMA_READ_INVALIDATE = 0x20, 1205 FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40 1206 }; 1207 1208 enum fw_ri_mpa_attrs { 1209 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1210 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1211 FW_RI_MPA_CRC_ENABLE = 0x04, 1212 FW_RI_MPA_IETF_ENABLE = 0x08 1213 }; 1214 1215 enum fw_ri_qp_caps { 1216 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1217 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1218 FW_RI_QP_BIND_ENABLE = 0x04, 1219 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1220 FW_RI_QP_STAG0_ENABLE = 0x10, 1221 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1222 }; 1223 1224 enum fw_ri_addr_type { 1225 FW_RI_ZERO_BASED_TO = 0x00, 1226 FW_RI_VA_BASED_TO = 0x01 1227 }; 1228 1229 enum fw_ri_mem_perms { 1230 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1231 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1232 FW_RI_MEM_ACCESS_REM = 0x03, 1233 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1234 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1235 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1236 }; 1237 1238 enum fw_ri_stag_type { 1239 FW_RI_STAG_NSMR = 0x00, 1240 FW_RI_STAG_SMR = 0x01, 1241 FW_RI_STAG_MW = 0x02, 1242 FW_RI_STAG_MW_RELAXED = 0x03 1243 }; 1244 1245 enum fw_ri_data_op { 1246 FW_RI_DATA_IMMD = 0x81, 1247 FW_RI_DATA_DSGL = 0x82, 1248 FW_RI_DATA_ISGL = 0x83 1249 }; 1250 1251 enum fw_ri_sgl_depth { 1252 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1253 FW_RI_SGL_DEPTH_MAX_RQ = 4 1254 }; 1255 1256 enum fw_ri_cqe_err { 1257 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1258 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1259 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1260 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1261 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1262 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1263 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1264 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1265 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1266 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1267 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1268 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1269 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1270 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1271 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1272 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1273 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1274 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1275 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1276 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1277 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1278 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1279 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1280 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1281 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1282 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1283 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1284 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1285 1286 }; 1287 1288 struct fw_ri_dsge_pair { 1289 __be32 len[2]; 1290 __be64 addr[2]; 1291 }; 1292 1293 struct fw_ri_dsgl { 1294 __u8 op; 1295 __u8 r1; 1296 __be16 nsge; 1297 __be32 len0; 1298 __be64 addr0; 1299 #ifndef C99_NOT_SUPPORTED 1300 struct fw_ri_dsge_pair sge[0]; 1301 #endif 1302 }; 1303 1304 struct fw_ri_sge { 1305 __be32 stag; 1306 __be32 len; 1307 __be64 to; 1308 }; 1309 1310 struct fw_ri_isgl { 1311 __u8 op; 1312 __u8 r1; 1313 __be16 nsge; 1314 __be32 r2; 1315 #ifndef C99_NOT_SUPPORTED 1316 struct fw_ri_sge sge[0]; 1317 #endif 1318 }; 1319 1320 struct fw_ri_immd { 1321 __u8 op; 1322 __u8 r1; 1323 __be16 r2; 1324 __be32 immdlen; 1325 #ifndef C99_NOT_SUPPORTED 1326 __u8 data[0]; 1327 #endif 1328 }; 1329 1330 struct fw_ri_tpte { 1331 __be32 valid_to_pdid; 1332 __be32 locread_to_qpid; 1333 __be32 nosnoop_pbladdr; 1334 __be32 len_lo; 1335 __be32 va_hi; 1336 __be32 va_lo_fbo; 1337 __be32 dca_mwbcnt_pstag; 1338 __be32 len_hi; 1339 }; 1340 1341 #define S_FW_RI_TPTE_VALID 31 1342 #define M_FW_RI_TPTE_VALID 0x1 1343 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1344 #define G_FW_RI_TPTE_VALID(x) \ 1345 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1346 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1347 1348 #define S_FW_RI_TPTE_STAGKEY 23 1349 #define M_FW_RI_TPTE_STAGKEY 0xff 1350 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1351 #define G_FW_RI_TPTE_STAGKEY(x) \ 1352 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1353 1354 #define S_FW_RI_TPTE_STAGSTATE 22 1355 #define M_FW_RI_TPTE_STAGSTATE 0x1 1356 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1357 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1358 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1359 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1360 1361 #define S_FW_RI_TPTE_STAGTYPE 20 1362 #define M_FW_RI_TPTE_STAGTYPE 0x3 1363 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1364 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1365 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1366 1367 #define S_FW_RI_TPTE_PDID 0 1368 #define M_FW_RI_TPTE_PDID 0xfffff 1369 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1370 #define G_FW_RI_TPTE_PDID(x) \ 1371 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1372 1373 #define S_FW_RI_TPTE_PERM 28 1374 #define M_FW_RI_TPTE_PERM 0xf 1375 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1376 #define G_FW_RI_TPTE_PERM(x) \ 1377 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1378 1379 #define S_FW_RI_TPTE_REMINVDIS 27 1380 #define M_FW_RI_TPTE_REMINVDIS 0x1 1381 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1382 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1383 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1384 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1385 1386 #define S_FW_RI_TPTE_ADDRTYPE 26 1387 #define M_FW_RI_TPTE_ADDRTYPE 1 1388 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1389 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1390 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1391 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1392 1393 #define S_FW_RI_TPTE_MWBINDEN 25 1394 #define M_FW_RI_TPTE_MWBINDEN 0x1 1395 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1396 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1397 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1398 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1399 1400 #define S_FW_RI_TPTE_PS 20 1401 #define M_FW_RI_TPTE_PS 0x1f 1402 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1403 #define G_FW_RI_TPTE_PS(x) \ 1404 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1405 1406 #define S_FW_RI_TPTE_QPID 0 1407 #define M_FW_RI_TPTE_QPID 0xfffff 1408 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1409 #define G_FW_RI_TPTE_QPID(x) \ 1410 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1411 1412 #define S_FW_RI_TPTE_NOSNOOP 31 1413 #define M_FW_RI_TPTE_NOSNOOP 0x1 1414 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1415 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1416 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1417 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1418 1419 #define S_FW_RI_TPTE_PBLADDR 0 1420 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1421 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1422 #define G_FW_RI_TPTE_PBLADDR(x) \ 1423 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1424 1425 #define S_FW_RI_TPTE_DCA 24 1426 #define M_FW_RI_TPTE_DCA 0x1f 1427 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1428 #define G_FW_RI_TPTE_DCA(x) \ 1429 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1430 1431 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1432 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1433 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1434 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1435 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1436 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1437 1438 enum fw_ri_cqe_rxtx { 1439 FW_RI_CQE_RXTX_RX = 0x0, 1440 FW_RI_CQE_RXTX_TX = 0x1, 1441 }; 1442 1443 struct fw_ri_cqe { 1444 union fw_ri_rxtx { 1445 struct fw_ri_scqe { 1446 __be32 qpid_n_stat_rxtx_type; 1447 __be32 plen; 1448 __be32 stag; 1449 __be32 wrid; 1450 } scqe; 1451 struct fw_ri_rcqe { 1452 __be32 qpid_n_stat_rxtx_type; 1453 __be32 plen; 1454 __be32 stag; 1455 __be32 msn; 1456 } rcqe; 1457 struct fw_ri_rcqe_imm { 1458 __be32 qpid_n_stat_rxtx_type; 1459 __be32 plen; 1460 __be32 mo; 1461 __be32 msn; 1462 __u64 imm_data; 1463 } imm_data_rcqe; 1464 } u; 1465 }; 1466 1467 #define S_FW_RI_CQE_QPID 12 1468 #define M_FW_RI_CQE_QPID 0xfffff 1469 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1470 #define G_FW_RI_CQE_QPID(x) \ 1471 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1472 1473 #define S_FW_RI_CQE_NOTIFY 10 1474 #define M_FW_RI_CQE_NOTIFY 0x1 1475 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1476 #define G_FW_RI_CQE_NOTIFY(x) \ 1477 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1478 1479 #define S_FW_RI_CQE_STATUS 5 1480 #define M_FW_RI_CQE_STATUS 0x1f 1481 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1482 #define G_FW_RI_CQE_STATUS(x) \ 1483 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1484 1485 1486 #define S_FW_RI_CQE_RXTX 4 1487 #define M_FW_RI_CQE_RXTX 0x1 1488 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1489 #define G_FW_RI_CQE_RXTX(x) \ 1490 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1491 1492 #define S_FW_RI_CQE_TYPE 0 1493 #define M_FW_RI_CQE_TYPE 0xf 1494 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1495 #define G_FW_RI_CQE_TYPE(x) \ 1496 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1497 1498 enum fw_ri_res_type { 1499 FW_RI_RES_TYPE_SQ, 1500 FW_RI_RES_TYPE_RQ, 1501 FW_RI_RES_TYPE_CQ, 1502 FW_RI_RES_TYPE_SRQ, 1503 }; 1504 1505 enum fw_ri_res_op { 1506 FW_RI_RES_OP_WRITE, 1507 FW_RI_RES_OP_RESET, 1508 }; 1509 1510 struct fw_ri_res { 1511 union fw_ri_restype { 1512 struct fw_ri_res_sqrq { 1513 __u8 restype; 1514 __u8 op; 1515 __be16 r3; 1516 __be32 eqid; 1517 __be32 r4[2]; 1518 __be32 fetchszm_to_iqid; 1519 __be32 dcaen_to_eqsize; 1520 __be64 eqaddr; 1521 } sqrq; 1522 struct fw_ri_res_cq { 1523 __u8 restype; 1524 __u8 op; 1525 __be16 r3; 1526 __be32 iqid; 1527 __be32 r4[2]; 1528 __be32 iqandst_to_iqandstindex; 1529 __be16 iqdroprss_to_iqesize; 1530 __be16 iqsize; 1531 __be64 iqaddr; 1532 __be32 iqns_iqro; 1533 __be32 r6_lo; 1534 __be64 r7; 1535 } cq; 1536 struct fw_ri_res_srq { 1537 __u8 restype; 1538 __u8 op; 1539 __be16 r3; 1540 __be32 eqid; 1541 __be32 r4[2]; 1542 __be32 fetchszm_to_iqid; 1543 __be32 dcaen_to_eqsize; 1544 __be64 eqaddr; 1545 __be32 srqid; 1546 __be32 pdid; 1547 __be32 hwsrqsize; 1548 __be32 hwsrqaddr; 1549 } srq; 1550 } u; 1551 }; 1552 1553 struct fw_ri_res_wr { 1554 __be32 op_nres; 1555 __be32 len16_pkd; 1556 __u64 cookie; 1557 #ifndef C99_NOT_SUPPORTED 1558 struct fw_ri_res res[0]; 1559 #endif 1560 }; 1561 1562 #define S_FW_RI_RES_WR_VFN 8 1563 #define M_FW_RI_RES_WR_VFN 0xff 1564 #define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN) 1565 #define G_FW_RI_RES_WR_VFN(x) \ 1566 (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN) 1567 1568 #define S_FW_RI_RES_WR_NRES 0 1569 #define M_FW_RI_RES_WR_NRES 0xff 1570 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1571 #define G_FW_RI_RES_WR_NRES(x) \ 1572 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1573 1574 #define S_FW_RI_RES_WR_FETCHSZM 26 1575 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1576 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1577 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1578 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1579 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1580 1581 #define S_FW_RI_RES_WR_STATUSPGNS 25 1582 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1583 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1584 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1585 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1586 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1587 1588 #define S_FW_RI_RES_WR_STATUSPGRO 24 1589 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1590 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1591 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1592 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1593 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1594 1595 #define S_FW_RI_RES_WR_FETCHNS 23 1596 #define M_FW_RI_RES_WR_FETCHNS 0x1 1597 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1598 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1599 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1600 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1601 1602 #define S_FW_RI_RES_WR_FETCHRO 22 1603 #define M_FW_RI_RES_WR_FETCHRO 0x1 1604 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1605 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1606 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1607 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1608 1609 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1610 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1611 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1612 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1613 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1614 1615 #define S_FW_RI_RES_WR_CPRIO 19 1616 #define M_FW_RI_RES_WR_CPRIO 0x1 1617 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1618 #define G_FW_RI_RES_WR_CPRIO(x) \ 1619 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1620 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1621 1622 #define S_FW_RI_RES_WR_ONCHIP 18 1623 #define M_FW_RI_RES_WR_ONCHIP 0x1 1624 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1625 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1626 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1627 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1628 1629 #define S_FW_RI_RES_WR_PCIECHN 16 1630 #define M_FW_RI_RES_WR_PCIECHN 0x3 1631 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1632 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1633 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1634 1635 #define S_FW_RI_RES_WR_IQID 0 1636 #define M_FW_RI_RES_WR_IQID 0xffff 1637 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1638 #define G_FW_RI_RES_WR_IQID(x) \ 1639 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1640 1641 #define S_FW_RI_RES_WR_DCAEN 31 1642 #define M_FW_RI_RES_WR_DCAEN 0x1 1643 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1644 #define G_FW_RI_RES_WR_DCAEN(x) \ 1645 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1646 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1647 1648 #define S_FW_RI_RES_WR_DCACPU 26 1649 #define M_FW_RI_RES_WR_DCACPU 0x1f 1650 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1651 #define G_FW_RI_RES_WR_DCACPU(x) \ 1652 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1653 1654 #define S_FW_RI_RES_WR_FBMIN 23 1655 #define M_FW_RI_RES_WR_FBMIN 0x7 1656 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1657 #define G_FW_RI_RES_WR_FBMIN(x) \ 1658 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1659 1660 #define S_FW_RI_RES_WR_FBMAX 20 1661 #define M_FW_RI_RES_WR_FBMAX 0x7 1662 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1663 #define G_FW_RI_RES_WR_FBMAX(x) \ 1664 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1665 1666 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1667 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1668 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1669 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1670 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1671 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1672 1673 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1674 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1675 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1676 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1677 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1678 1679 #define S_FW_RI_RES_WR_EQSIZE 0 1680 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1681 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1682 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1683 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1684 1685 #define S_FW_RI_RES_WR_IQANDST 15 1686 #define M_FW_RI_RES_WR_IQANDST 0x1 1687 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1688 #define G_FW_RI_RES_WR_IQANDST(x) \ 1689 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1690 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1691 1692 #define S_FW_RI_RES_WR_IQANUS 14 1693 #define M_FW_RI_RES_WR_IQANUS 0x1 1694 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1695 #define G_FW_RI_RES_WR_IQANUS(x) \ 1696 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1697 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1698 1699 #define S_FW_RI_RES_WR_IQANUD 12 1700 #define M_FW_RI_RES_WR_IQANUD 0x3 1701 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1702 #define G_FW_RI_RES_WR_IQANUD(x) \ 1703 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1704 1705 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1706 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1707 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1708 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1709 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1710 1711 #define S_FW_RI_RES_WR_IQDROPRSS 15 1712 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1713 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1714 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1715 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1716 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1717 1718 #define S_FW_RI_RES_WR_IQGTSMODE 14 1719 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1720 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1721 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1722 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1723 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1724 1725 #define S_FW_RI_RES_WR_IQPCIECH 12 1726 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1727 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1728 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1729 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1730 1731 #define S_FW_RI_RES_WR_IQDCAEN 11 1732 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1733 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1734 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1735 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1736 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1737 1738 #define S_FW_RI_RES_WR_IQDCACPU 6 1739 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1740 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1741 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1742 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1743 1744 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1745 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1746 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1747 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1748 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1749 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1750 1751 #define S_FW_RI_RES_WR_IQO 3 1752 #define M_FW_RI_RES_WR_IQO 0x1 1753 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1754 #define G_FW_RI_RES_WR_IQO(x) \ 1755 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1756 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1757 1758 #define S_FW_RI_RES_WR_IQCPRIO 2 1759 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1760 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1761 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1762 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1763 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1764 1765 #define S_FW_RI_RES_WR_IQESIZE 0 1766 #define M_FW_RI_RES_WR_IQESIZE 0x3 1767 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1768 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1769 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1770 1771 #define S_FW_RI_RES_WR_IQNS 31 1772 #define M_FW_RI_RES_WR_IQNS 0x1 1773 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1774 #define G_FW_RI_RES_WR_IQNS(x) \ 1775 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1776 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1777 1778 #define S_FW_RI_RES_WR_IQRO 30 1779 #define M_FW_RI_RES_WR_IQRO 0x1 1780 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1781 #define G_FW_RI_RES_WR_IQRO(x) \ 1782 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1783 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1784 1785 struct fw_ri_rdma_write_wr { 1786 __u8 opcode; 1787 __u8 flags; 1788 __u16 wrid; 1789 __u8 r1[3]; 1790 __u8 len16; 1791 __u64 immd_data; 1792 __be32 plen; 1793 __be32 stag_sink; 1794 __be64 to_sink; 1795 #ifndef C99_NOT_SUPPORTED 1796 union { 1797 struct fw_ri_immd immd_src[0]; 1798 struct fw_ri_isgl isgl_src[0]; 1799 } u; 1800 #endif 1801 }; 1802 1803 struct fw_ri_send_wr { 1804 __u8 opcode; 1805 __u8 flags; 1806 __u16 wrid; 1807 __u8 r1[3]; 1808 __u8 len16; 1809 __be32 sendop_pkd; 1810 __be32 stag_inv; 1811 __be32 plen; 1812 __be32 r3; 1813 __be64 r4; 1814 #ifndef C99_NOT_SUPPORTED 1815 union { 1816 struct fw_ri_immd immd_src[0]; 1817 struct fw_ri_isgl isgl_src[0]; 1818 } u; 1819 #endif 1820 }; 1821 1822 #define S_FW_RI_SEND_WR_SENDOP 0 1823 #define M_FW_RI_SEND_WR_SENDOP 0xf 1824 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1825 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1826 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1827 1828 struct fw_ri_rdma_write_cmpl_wr { 1829 __u8 opcode; 1830 __u8 flags; 1831 __u16 wrid; 1832 __u8 r1[3]; 1833 __u8 len16; 1834 __u32 r2; 1835 __be32 stag_inv; 1836 __be32 plen; 1837 __be32 stag_sink; 1838 __be64 to_sink; 1839 union fw_ri_cmpl { 1840 struct fw_ri_immd_cmpl { 1841 __u8 op; 1842 __u8 r1[6]; 1843 __u8 immdlen; 1844 __u8 data[16]; 1845 } immd_src; 1846 struct fw_ri_isgl isgl_src; 1847 } u_cmpl; 1848 __be64 r3; 1849 #ifndef C99_NOT_SUPPORTED 1850 union fw_ri_write { 1851 struct fw_ri_immd immd_src[0]; 1852 struct fw_ri_isgl isgl_src[0]; 1853 } u; 1854 #endif 1855 }; 1856 1857 struct fw_ri_rdma_read_wr { 1858 __u8 opcode; 1859 __u8 flags; 1860 __u16 wrid; 1861 __u8 r1[3]; 1862 __u8 len16; 1863 __be64 r2; 1864 __be32 stag_sink; 1865 __be32 to_sink_hi; 1866 __be32 to_sink_lo; 1867 __be32 plen; 1868 __be32 stag_src; 1869 __be32 to_src_hi; 1870 __be32 to_src_lo; 1871 __be32 r5; 1872 }; 1873 1874 struct fw_ri_recv_wr { 1875 __u8 opcode; 1876 __u8 r1; 1877 __u16 wrid; 1878 __u8 r2[3]; 1879 __u8 len16; 1880 struct fw_ri_isgl isgl; 1881 }; 1882 1883 struct fw_ri_bind_mw_wr { 1884 __u8 opcode; 1885 __u8 flags; 1886 __u16 wrid; 1887 __u8 r1[3]; 1888 __u8 len16; 1889 __u8 qpbinde_to_dcacpu; 1890 __u8 pgsz_shift; 1891 __u8 addr_type; 1892 __u8 mem_perms; 1893 __be32 stag_mr; 1894 __be32 stag_mw; 1895 __be32 r3; 1896 __be64 len_mw; 1897 __be64 va_fbo; 1898 __be64 r4; 1899 }; 1900 1901 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1902 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1903 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1904 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1905 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1906 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1907 1908 #define S_FW_RI_BIND_MW_WR_NS 5 1909 #define M_FW_RI_BIND_MW_WR_NS 0x1 1910 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1911 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1912 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1913 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1914 1915 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1916 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1917 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1918 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1919 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1920 1921 struct fw_ri_fr_nsmr_wr { 1922 __u8 opcode; 1923 __u8 flags; 1924 __u16 wrid; 1925 __u8 r1[3]; 1926 __u8 len16; 1927 __u8 qpbinde_to_dcacpu; 1928 __u8 pgsz_shift; 1929 __u8 addr_type; 1930 __u8 mem_perms; 1931 __be32 stag; 1932 __be32 len_hi; 1933 __be32 len_lo; 1934 __be32 va_hi; 1935 __be32 va_lo_fbo; 1936 }; 1937 1938 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1939 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1940 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1941 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1942 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1943 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1944 1945 #define S_FW_RI_FR_NSMR_WR_NS 5 1946 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1947 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1948 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1949 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1950 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1951 1952 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1953 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1954 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1955 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1956 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1957 1958 struct fw_ri_fr_nsmr_tpte_wr { 1959 __u8 opcode; 1960 __u8 flags; 1961 __u16 wrid; 1962 __u8 r1[3]; 1963 __u8 len16; 1964 __be32 r2; 1965 __be32 stag; 1966 struct fw_ri_tpte tpte; 1967 __be64 pbl[2]; 1968 }; 1969 1970 struct fw_ri_inv_lstag_wr { 1971 __u8 opcode; 1972 __u8 flags; 1973 __u16 wrid; 1974 __u8 r1[3]; 1975 __u8 len16; 1976 __be32 r2; 1977 __be32 stag_inv; 1978 }; 1979 1980 struct fw_ri_send_immediate_wr { 1981 __u8 opcode; 1982 __u8 flags; 1983 __u16 wrid; 1984 __u8 r1[3]; 1985 __u8 len16; 1986 __be32 sendimmop_pkd; 1987 __be32 r3; 1988 __be32 plen; 1989 __be32 r4; 1990 __be64 r5; 1991 #ifndef C99_NOT_SUPPORTED 1992 struct fw_ri_immd immd_src[0]; 1993 #endif 1994 }; 1995 1996 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1997 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1998 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1999 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2000 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2001 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 2002 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2003 2004 enum fw_ri_atomic_op { 2005 FW_RI_ATOMIC_OP_FETCHADD, 2006 FW_RI_ATOMIC_OP_SWAP, 2007 FW_RI_ATOMIC_OP_CMDSWAP, 2008 }; 2009 2010 struct fw_ri_atomic_wr { 2011 __u8 opcode; 2012 __u8 flags; 2013 __u16 wrid; 2014 __u8 r1[3]; 2015 __u8 len16; 2016 __be32 atomicop_pkd; 2017 __be64 r3; 2018 __be32 aopcode_pkd; 2019 __be32 reqid; 2020 __be32 stag; 2021 __be32 to_hi; 2022 __be32 to_lo; 2023 __be32 addswap_data_hi; 2024 __be32 addswap_data_lo; 2025 __be32 addswap_mask_hi; 2026 __be32 addswap_mask_lo; 2027 __be32 compare_data_hi; 2028 __be32 compare_data_lo; 2029 __be32 compare_mask_hi; 2030 __be32 compare_mask_lo; 2031 __be32 r5; 2032 }; 2033 2034 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 2035 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 2036 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 2037 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 2038 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 2039 2040 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 2041 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 2042 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 2043 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 2044 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 2045 2046 enum fw_ri_type { 2047 FW_RI_TYPE_INIT, 2048 FW_RI_TYPE_FINI, 2049 FW_RI_TYPE_TERMINATE 2050 }; 2051 2052 enum fw_ri_init_p2ptype { 2053 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 2054 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 2055 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 2056 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 2057 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 2058 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 2059 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 2060 }; 2061 2062 enum fw_ri_init_rqeqid_srq { 2063 FW_RI_INIT_RQEQID_SRQ = 1 << 31, 2064 }; 2065 2066 struct fw_ri_wr { 2067 __be32 op_compl; 2068 __be32 flowid_len16; 2069 __u64 cookie; 2070 union fw_ri { 2071 struct fw_ri_init { 2072 __u8 type; 2073 __u8 mpareqbit_p2ptype; 2074 __u8 r4[2]; 2075 __u8 mpa_attrs; 2076 __u8 qp_caps; 2077 __be16 nrqe; 2078 __be32 pdid; 2079 __be32 qpid; 2080 __be32 sq_eqid; 2081 __be32 rq_eqid; 2082 __be32 scqid; 2083 __be32 rcqid; 2084 __be32 ord_max; 2085 __be32 ird_max; 2086 __be32 iss; 2087 __be32 irs; 2088 __be32 hwrqsize; 2089 __be32 hwrqaddr; 2090 __be64 r5; 2091 union fw_ri_init_p2p { 2092 struct fw_ri_rdma_write_wr write; 2093 struct fw_ri_rdma_read_wr read; 2094 struct fw_ri_send_wr send; 2095 } u; 2096 } init; 2097 struct fw_ri_fini { 2098 __u8 type; 2099 __u8 r3[7]; 2100 __be64 r4; 2101 } fini; 2102 struct fw_ri_terminate { 2103 __u8 type; 2104 __u8 r3[3]; 2105 __be32 immdlen; 2106 __u8 termmsg[40]; 2107 } terminate; 2108 } u; 2109 }; 2110 2111 #define S_FW_RI_WR_MPAREQBIT 7 2112 #define M_FW_RI_WR_MPAREQBIT 0x1 2113 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 2114 #define G_FW_RI_WR_MPAREQBIT(x) \ 2115 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 2116 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 2117 2118 #define S_FW_RI_WR_0BRRBIT 6 2119 #define M_FW_RI_WR_0BRRBIT 0x1 2120 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 2121 #define G_FW_RI_WR_0BRRBIT(x) \ 2122 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 2123 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 2124 2125 #define S_FW_RI_WR_P2PTYPE 0 2126 #define M_FW_RI_WR_P2PTYPE 0xf 2127 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 2128 #define G_FW_RI_WR_P2PTYPE(x) \ 2129 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 2130 2131 /****************************************************************************** 2132 * F O i S C S I W O R K R E Q U E S T s 2133 *********************************************/ 2134 2135 #define FW_FOISCSI_NAME_MAX_LEN 224 2136 #define FW_FOISCSI_ALIAS_MAX_LEN 224 2137 #define FW_FOISCSI_KEY_MAX_LEN 64 2138 #define FW_FOISCSI_VAL_MAX_LEN 256 2139 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 2140 #define FW_FOISCSI_INIT_NODE_MAX 8 2141 2142 enum fw_chnet_ifconf_wr_subop { 2143 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 2144 2145 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 2146 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 2147 2148 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 2149 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 2150 2151 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 2152 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 2153 2154 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 2155 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 2156 2157 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 2158 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 2159 2160 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 2161 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 2162 2163 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 2164 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 2165 2166 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 2167 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 2168 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 2169 2170 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING4, 2171 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING6, 2172 2173 FW_CHNET_IFCONF_WR_SUBOP_MAX, 2174 }; 2175 2176 struct fw_chnet_ifconf_wr { 2177 __be32 op_compl; 2178 __be32 flowid_len16; 2179 __u64 cookie; 2180 __be32 if_flowid; 2181 __u8 idx; 2182 __u8 subop; 2183 __u8 retval; 2184 __u8 r2; 2185 union { 2186 __be64 r3; 2187 struct fw_chnet_ifconf_ping { 2188 __be16 ping_time; 2189 __u8 ping_rsptype; 2190 __u8 ping_param_rspcode_to_fin_bit; 2191 __u8 ping_pktsize; 2192 __u8 ping_ttl; 2193 __be16 ping_seq; 2194 } ping; 2195 struct fw_chnet_ifconf_mac { 2196 __u8 peer_mac[6]; 2197 __u8 smac_idx; 2198 } mac; 2199 } u; 2200 struct fw_chnet_ifconf_params { 2201 __be32 r0; 2202 __be16 vlanid; 2203 __be16 mtu; 2204 union fw_chnet_ifconf_addr_type { 2205 struct fw_chnet_ifconf_ipv4 { 2206 __be32 addr; 2207 __be32 mask; 2208 __be32 router; 2209 __be32 r0; 2210 __be64 r1; 2211 } ipv4; 2212 struct fw_chnet_ifconf_ipv6 { 2213 __u8 prefix_len; 2214 __u8 r0; 2215 __be16 r1; 2216 __be32 r2; 2217 __be64 addr_hi; 2218 __be64 addr_lo; 2219 __be64 router_hi; 2220 __be64 router_lo; 2221 } ipv6; 2222 } in_attr; 2223 } param; 2224 }; 2225 2226 #define S_FW_CHNET_IFCONF_WR_PING_MACBIT 1 2227 #define M_FW_CHNET_IFCONF_WR_PING_MACBIT 0x1 2228 #define V_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \ 2229 ((x) << S_FW_CHNET_IFCONF_WR_PING_MACBIT) 2230 #define G_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \ 2231 (((x) >> S_FW_CHNET_IFCONF_WR_PING_MACBIT) & \ 2232 M_FW_CHNET_IFCONF_WR_PING_MACBIT) 2233 #define F_FW_CHNET_IFCONF_WR_PING_MACBIT \ 2234 V_FW_CHNET_IFCONF_WR_PING_MACBIT(1U) 2235 2236 #define S_FW_CHNET_IFCONF_WR_FIN_BIT 0 2237 #define M_FW_CHNET_IFCONF_WR_FIN_BIT 0x1 2238 #define V_FW_CHNET_IFCONF_WR_FIN_BIT(x) ((x) << S_FW_CHNET_IFCONF_WR_FIN_BIT) 2239 #define G_FW_CHNET_IFCONF_WR_FIN_BIT(x) \ 2240 (((x) >> S_FW_CHNET_IFCONF_WR_FIN_BIT) & M_FW_CHNET_IFCONF_WR_FIN_BIT) 2241 #define F_FW_CHNET_IFCONF_WR_FIN_BIT V_FW_CHNET_IFCONF_WR_FIN_BIT(1U) 2242 2243 enum fw_foiscsi_node_type { 2244 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 2245 FW_FOISCSI_NODE_TYPE_TARGET, 2246 }; 2247 2248 enum fw_foiscsi_session_type { 2249 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 2250 FW_FOISCSI_SESSION_TYPE_NORMAL, 2251 }; 2252 2253 enum fw_foiscsi_auth_policy { 2254 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 2255 FW_FOISCSI_AUTH_POLICY_MUTUAL, 2256 }; 2257 2258 enum fw_foiscsi_auth_method { 2259 FW_FOISCSI_AUTH_METHOD_NONE = 0, 2260 FW_FOISCSI_AUTH_METHOD_CHAP, 2261 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 2262 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 2263 }; 2264 2265 enum fw_foiscsi_digest_type { 2266 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 2267 FW_FOISCSI_DIGEST_TYPE_CRC32, 2268 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 2269 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 2270 }; 2271 2272 enum fw_foiscsi_wr_subop { 2273 FW_FOISCSI_WR_SUBOP_ADD = 1, 2274 FW_FOISCSI_WR_SUBOP_DEL = 2, 2275 FW_FOISCSI_WR_SUBOP_MOD = 4, 2276 }; 2277 2278 enum fw_coiscsi_stats_wr_subop { 2279 FW_COISCSI_WR_SUBOP_TOT = 1, 2280 FW_COISCSI_WR_SUBOP_MAX = 2, 2281 FW_COISCSI_WR_SUBOP_CUR = 3, 2282 FW_COISCSI_WR_SUBOP_CLR = 4, 2283 }; 2284 2285 enum fw_foiscsi_ctrl_state { 2286 FW_FOISCSI_CTRL_STATE_FREE = 0, 2287 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 2288 FW_FOISCSI_CTRL_STATE_FAILED, 2289 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 2290 FW_FOISCSI_CTRL_STATE_REDIRECT, 2291 }; 2292 2293 struct fw_rdev_wr { 2294 __be32 op_to_immdlen; 2295 __be32 alloc_to_len16; 2296 __be64 cookie; 2297 __u8 protocol; 2298 __u8 event_cause; 2299 __u8 cur_state; 2300 __u8 prev_state; 2301 __be32 flags_to_assoc_flowid; 2302 union rdev_entry { 2303 struct fcoe_rdev_entry { 2304 __be32 flowid; 2305 __u8 protocol; 2306 __u8 event_cause; 2307 __u8 flags; 2308 __u8 rjt_reason; 2309 __u8 cur_login_st; 2310 __u8 prev_login_st; 2311 __be16 rcv_fr_sz; 2312 __u8 rd_xfer_rdy_to_rport_type; 2313 __u8 vft_to_qos; 2314 __u8 org_proc_assoc_to_acc_rsp_code; 2315 __u8 enh_disc_to_tgt; 2316 __u8 wwnn[8]; 2317 __u8 wwpn[8]; 2318 __be16 iqid; 2319 __u8 fc_oui[3]; 2320 __u8 r_id[3]; 2321 } fcoe_rdev; 2322 struct iscsi_rdev_entry { 2323 __be32 flowid; 2324 __u8 protocol; 2325 __u8 event_cause; 2326 __u8 flags; 2327 __u8 r3; 2328 __be16 iscsi_opts; 2329 __be16 tcp_opts; 2330 __be16 ip_opts; 2331 __be16 max_rcv_len; 2332 __be16 max_snd_len; 2333 __be16 first_brst_len; 2334 __be16 max_brst_len; 2335 __be16 r4; 2336 __be16 def_time2wait; 2337 __be16 def_time2ret; 2338 __be16 nop_out_intrvl; 2339 __be16 non_scsi_to; 2340 __be16 isid; 2341 __be16 tsid; 2342 __be16 port; 2343 __be16 tpgt; 2344 __u8 r5[6]; 2345 __be16 iqid; 2346 } iscsi_rdev; 2347 } u; 2348 }; 2349 2350 #define S_FW_RDEV_WR_IMMDLEN 0 2351 #define M_FW_RDEV_WR_IMMDLEN 0xff 2352 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2353 #define G_FW_RDEV_WR_IMMDLEN(x) \ 2354 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2355 2356 #define S_FW_RDEV_WR_ALLOC 31 2357 #define M_FW_RDEV_WR_ALLOC 0x1 2358 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2359 #define G_FW_RDEV_WR_ALLOC(x) \ 2360 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2361 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2362 2363 #define S_FW_RDEV_WR_FREE 30 2364 #define M_FW_RDEV_WR_FREE 0x1 2365 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2366 #define G_FW_RDEV_WR_FREE(x) \ 2367 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2368 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2369 2370 #define S_FW_RDEV_WR_MODIFY 29 2371 #define M_FW_RDEV_WR_MODIFY 0x1 2372 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2373 #define G_FW_RDEV_WR_MODIFY(x) \ 2374 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2375 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2376 2377 #define S_FW_RDEV_WR_FLOWID 8 2378 #define M_FW_RDEV_WR_FLOWID 0xfffff 2379 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2380 #define G_FW_RDEV_WR_FLOWID(x) \ 2381 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2382 2383 #define S_FW_RDEV_WR_LEN16 0 2384 #define M_FW_RDEV_WR_LEN16 0xff 2385 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2386 #define G_FW_RDEV_WR_LEN16(x) \ 2387 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2388 2389 #define S_FW_RDEV_WR_FLAGS 24 2390 #define M_FW_RDEV_WR_FLAGS 0xff 2391 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2392 #define G_FW_RDEV_WR_FLAGS(x) \ 2393 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2394 2395 #define S_FW_RDEV_WR_GET_NEXT 20 2396 #define M_FW_RDEV_WR_GET_NEXT 0xf 2397 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2398 #define G_FW_RDEV_WR_GET_NEXT(x) \ 2399 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2400 2401 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 2402 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2403 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2404 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2405 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2406 2407 #define S_FW_RDEV_WR_RJT 7 2408 #define M_FW_RDEV_WR_RJT 0x1 2409 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2410 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2411 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2412 2413 #define S_FW_RDEV_WR_REASON 0 2414 #define M_FW_RDEV_WR_REASON 0x7f 2415 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2416 #define G_FW_RDEV_WR_REASON(x) \ 2417 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2418 2419 #define S_FW_RDEV_WR_RD_XFER_RDY 7 2420 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2421 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2422 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2423 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2424 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2425 2426 #define S_FW_RDEV_WR_WR_XFER_RDY 6 2427 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2428 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2429 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2430 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2431 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2432 2433 #define S_FW_RDEV_WR_FC_SP 5 2434 #define M_FW_RDEV_WR_FC_SP 0x1 2435 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2436 #define G_FW_RDEV_WR_FC_SP(x) \ 2437 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2438 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2439 2440 #define S_FW_RDEV_WR_RPORT_TYPE 0 2441 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2442 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2443 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2444 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2445 2446 #define S_FW_RDEV_WR_VFT 7 2447 #define M_FW_RDEV_WR_VFT 0x1 2448 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2449 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2450 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2451 2452 #define S_FW_RDEV_WR_NPIV 6 2453 #define M_FW_RDEV_WR_NPIV 0x1 2454 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2455 #define G_FW_RDEV_WR_NPIV(x) \ 2456 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2457 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2458 2459 #define S_FW_RDEV_WR_CLASS 4 2460 #define M_FW_RDEV_WR_CLASS 0x3 2461 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2462 #define G_FW_RDEV_WR_CLASS(x) \ 2463 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2464 2465 #define S_FW_RDEV_WR_SEQ_DEL 3 2466 #define M_FW_RDEV_WR_SEQ_DEL 0x1 2467 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2468 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2469 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2470 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2471 2472 #define S_FW_RDEV_WR_PRIO_PREEMP 2 2473 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2474 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2475 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2476 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2477 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2478 2479 #define S_FW_RDEV_WR_PREF 1 2480 #define M_FW_RDEV_WR_PREF 0x1 2481 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2482 #define G_FW_RDEV_WR_PREF(x) \ 2483 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2484 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2485 2486 #define S_FW_RDEV_WR_QOS 0 2487 #define M_FW_RDEV_WR_QOS 0x1 2488 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2489 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2490 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2491 2492 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2493 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2494 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2495 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2496 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2497 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2498 2499 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2500 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2501 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2502 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2503 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2504 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2505 2506 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2507 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2508 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2509 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2510 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2511 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2512 2513 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2514 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2515 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2516 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2517 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2518 2519 #define S_FW_RDEV_WR_ENH_DISC 7 2520 #define M_FW_RDEV_WR_ENH_DISC 0x1 2521 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2522 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2523 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2524 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2525 2526 #define S_FW_RDEV_WR_REC 6 2527 #define M_FW_RDEV_WR_REC 0x1 2528 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2529 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2530 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2531 2532 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2533 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2534 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2535 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2536 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2537 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2538 2539 #define S_FW_RDEV_WR_RETRY 4 2540 #define M_FW_RDEV_WR_RETRY 0x1 2541 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2542 #define G_FW_RDEV_WR_RETRY(x) \ 2543 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2544 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2545 2546 #define S_FW_RDEV_WR_CONF_CMPL 3 2547 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2548 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2549 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2550 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2551 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2552 2553 #define S_FW_RDEV_WR_DATA_OVLY 2 2554 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2555 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2556 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2557 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2558 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2559 2560 #define S_FW_RDEV_WR_INI 1 2561 #define M_FW_RDEV_WR_INI 0x1 2562 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2563 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2564 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2565 2566 #define S_FW_RDEV_WR_TGT 0 2567 #define M_FW_RDEV_WR_TGT 0x1 2568 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2569 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2570 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2571 2572 struct fw_foiscsi_node_wr { 2573 __be32 op_to_immdlen; 2574 __be32 no_sess_recv_to_len16; 2575 __u64 cookie; 2576 __u8 subop; 2577 __u8 status; 2578 __u8 alias_len; 2579 __u8 iqn_len; 2580 __be32 node_flowid; 2581 __be16 nodeid; 2582 __be16 login_retry; 2583 __be16 retry_timeout; 2584 __be16 r3; 2585 __u8 iqn[224]; 2586 __u8 alias[224]; 2587 __be32 isid_tval_to_isid_cval; 2588 }; 2589 2590 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2591 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2592 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2593 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2594 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2595 2596 #define S_FW_FOISCSI_NODE_WR_NO_SESS_RECV 28 2597 #define M_FW_FOISCSI_NODE_WR_NO_SESS_RECV 0x1 2598 #define V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \ 2599 ((x) << S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) 2600 #define G_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \ 2601 (((x) >> S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) & \ 2602 M_FW_FOISCSI_NODE_WR_NO_SESS_RECV) 2603 #define F_FW_FOISCSI_NODE_WR_NO_SESS_RECV \ 2604 V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(1U) 2605 2606 #define S_FW_FOISCSI_NODE_WR_ISID_TVAL 30 2607 #define M_FW_FOISCSI_NODE_WR_ISID_TVAL 0x3 2608 #define V_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ 2609 ((x) << S_FW_FOISCSI_NODE_WR_ISID_TVAL) 2610 #define G_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ 2611 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_TVAL) & M_FW_FOISCSI_NODE_WR_ISID_TVAL) 2612 2613 #define S_FW_FOISCSI_NODE_WR_ISID_AVAL 24 2614 #define M_FW_FOISCSI_NODE_WR_ISID_AVAL 0x3f 2615 #define V_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ 2616 ((x) << S_FW_FOISCSI_NODE_WR_ISID_AVAL) 2617 #define G_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ 2618 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_AVAL) & M_FW_FOISCSI_NODE_WR_ISID_AVAL) 2619 2620 #define S_FW_FOISCSI_NODE_WR_ISID_BVAL 8 2621 #define M_FW_FOISCSI_NODE_WR_ISID_BVAL 0xffff 2622 #define V_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ 2623 ((x) << S_FW_FOISCSI_NODE_WR_ISID_BVAL) 2624 #define G_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ 2625 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_BVAL) & M_FW_FOISCSI_NODE_WR_ISID_BVAL) 2626 2627 #define S_FW_FOISCSI_NODE_WR_ISID_CVAL 0 2628 #define M_FW_FOISCSI_NODE_WR_ISID_CVAL 0xff 2629 #define V_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ 2630 ((x) << S_FW_FOISCSI_NODE_WR_ISID_CVAL) 2631 #define G_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ 2632 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_CVAL) & M_FW_FOISCSI_NODE_WR_ISID_CVAL) 2633 2634 struct fw_foiscsi_ctrl_wr { 2635 __be32 op_to_no_fin; 2636 __be32 flowid_len16; 2637 __u64 cookie; 2638 __u8 subop; 2639 __u8 status; 2640 __u8 ctrl_state; 2641 __u8 io_state; 2642 __be32 node_id; 2643 __be32 ctrl_id; 2644 __be32 io_id; 2645 struct fw_foiscsi_sess_attr { 2646 __be32 sess_type_to_erl; 2647 __be16 max_conn; 2648 __be16 max_r2t; 2649 __be16 time2wait; 2650 __be16 time2retain; 2651 __be32 max_burst; 2652 __be32 first_burst; 2653 __be32 r1; 2654 } sess_attr; 2655 struct fw_foiscsi_conn_attr { 2656 __be32 hdigest_to_tcp_ws_en; 2657 __be32 max_rcv_dsl; 2658 __be32 ping_tmo; 2659 __be16 dst_port; 2660 __be16 src_port; 2661 union fw_foiscsi_conn_attr_addr { 2662 struct fw_foiscsi_conn_attr_ipv6 { 2663 __be64 dst_addr[2]; 2664 __be64 src_addr[2]; 2665 } ipv6_addr; 2666 struct fw_foiscsi_conn_attr_ipv4 { 2667 __be32 dst_addr; 2668 __be32 src_addr; 2669 } ipv4_addr; 2670 } u; 2671 } conn_attr; 2672 __u8 tgt_name_len; 2673 __u8 r3[7]; 2674 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2675 }; 2676 2677 #define S_FW_FOISCSI_CTRL_WR_PORTID 1 2678 #define M_FW_FOISCSI_CTRL_WR_PORTID 0x7 2679 #define V_FW_FOISCSI_CTRL_WR_PORTID(x) ((x) << S_FW_FOISCSI_CTRL_WR_PORTID) 2680 #define G_FW_FOISCSI_CTRL_WR_PORTID(x) \ 2681 (((x) >> S_FW_FOISCSI_CTRL_WR_PORTID) & M_FW_FOISCSI_CTRL_WR_PORTID) 2682 2683 #define S_FW_FOISCSI_CTRL_WR_NO_FIN 0 2684 #define M_FW_FOISCSI_CTRL_WR_NO_FIN 0x1 2685 #define V_FW_FOISCSI_CTRL_WR_NO_FIN(x) ((x) << S_FW_FOISCSI_CTRL_WR_NO_FIN) 2686 #define G_FW_FOISCSI_CTRL_WR_NO_FIN(x) \ 2687 (((x) >> S_FW_FOISCSI_CTRL_WR_NO_FIN) & M_FW_FOISCSI_CTRL_WR_NO_FIN) 2688 #define F_FW_FOISCSI_CTRL_WR_NO_FIN V_FW_FOISCSI_CTRL_WR_NO_FIN(1U) 2689 2690 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2691 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2692 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2693 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2694 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2695 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2696 2697 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2698 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2699 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2700 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2701 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2702 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2703 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2704 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2705 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2706 2707 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2708 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2709 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2710 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2711 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2712 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2713 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2714 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2715 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2716 2717 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2718 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2719 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2720 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2721 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2722 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2723 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2724 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2725 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2726 2727 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2728 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2729 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2730 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2731 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2732 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2733 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2734 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2735 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2736 2737 #define S_FW_FOISCSI_CTRL_WR_ERL 24 2738 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2739 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2740 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2741 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2742 2743 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2744 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2745 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2746 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2747 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2748 2749 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2750 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2751 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2752 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2753 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2754 2755 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2756 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2757 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2758 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2759 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2760 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2761 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2762 2763 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2764 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2765 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2766 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2767 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2768 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2769 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2770 2771 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2772 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2773 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2774 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2775 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2776 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2777 2778 #define S_FW_FOISCSI_CTRL_WR_IPV6 20 2779 #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 2780 #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 2781 #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 2782 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 2783 #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 2784 2785 #define S_FW_FOISCSI_CTRL_WR_DDP_PGIDX 16 2786 #define M_FW_FOISCSI_CTRL_WR_DDP_PGIDX 0xf 2787 #define V_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ 2788 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) 2789 #define G_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ 2790 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) & M_FW_FOISCSI_CTRL_WR_DDP_PGIDX) 2791 2792 #define S_FW_FOISCSI_CTRL_WR_TCP_WS 12 2793 #define M_FW_FOISCSI_CTRL_WR_TCP_WS 0xf 2794 #define V_FW_FOISCSI_CTRL_WR_TCP_WS(x) ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS) 2795 #define G_FW_FOISCSI_CTRL_WR_TCP_WS(x) \ 2796 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS) & M_FW_FOISCSI_CTRL_WR_TCP_WS) 2797 2798 #define S_FW_FOISCSI_CTRL_WR_TCP_WS_EN 11 2799 #define M_FW_FOISCSI_CTRL_WR_TCP_WS_EN 0x1 2800 #define V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \ 2801 ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) 2802 #define G_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \ 2803 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) & M_FW_FOISCSI_CTRL_WR_TCP_WS_EN) 2804 #define F_FW_FOISCSI_CTRL_WR_TCP_WS_EN V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(1U) 2805 2806 struct fw_foiscsi_chap_wr { 2807 __be32 op_to_kv_flag; 2808 __be32 flowid_len16; 2809 __u64 cookie; 2810 __u8 status; 2811 union fw_foiscsi_len { 2812 struct fw_foiscsi_chap_lens { 2813 __u8 id_len; 2814 __u8 sec_len; 2815 } chapl; 2816 struct fw_foiscsi_vend_kv_lens { 2817 __u8 key_len; 2818 __u8 val_len; 2819 } vend_kvl; 2820 } lenu; 2821 __u8 node_type; 2822 __be16 node_id; 2823 __u8 r3[2]; 2824 union fw_foiscsi_chap_vend { 2825 struct fw_foiscsi_chap { 2826 __u8 chap_id[224]; 2827 __u8 chap_sec[128]; 2828 } chap; 2829 struct fw_foiscsi_vend_kv { 2830 __u8 vend_key[64]; 2831 __u8 vend_val[256]; 2832 } vend_kv; 2833 } u; 2834 }; 2835 2836 #define S_FW_FOISCSI_CHAP_WR_KV_FLAG 20 2837 #define M_FW_FOISCSI_CHAP_WR_KV_FLAG 0x1 2838 #define V_FW_FOISCSI_CHAP_WR_KV_FLAG(x) ((x) << S_FW_FOISCSI_CHAP_WR_KV_FLAG) 2839 #define G_FW_FOISCSI_CHAP_WR_KV_FLAG(x) \ 2840 (((x) >> S_FW_FOISCSI_CHAP_WR_KV_FLAG) & M_FW_FOISCSI_CHAP_WR_KV_FLAG) 2841 #define F_FW_FOISCSI_CHAP_WR_KV_FLAG V_FW_FOISCSI_CHAP_WR_KV_FLAG(1U) 2842 2843 /****************************************************************************** 2844 * C O i S C S I W O R K R E Q U E S T S 2845 ********************************************/ 2846 2847 enum fw_chnet_addr_type { 2848 FW_CHNET_ADDD_TYPE_NONE = 0, 2849 FW_CHNET_ADDR_TYPE_IPV4, 2850 FW_CHNET_ADDR_TYPE_IPV6, 2851 }; 2852 2853 enum fw_msg_wr_type { 2854 FW_MSG_WR_TYPE_RPL = 0, 2855 FW_MSG_WR_TYPE_ERR, 2856 FW_MSG_WR_TYPE_PLD, 2857 }; 2858 2859 struct fw_coiscsi_tgt_wr { 2860 __be32 op_compl; 2861 __be32 flowid_len16; 2862 __u64 cookie; 2863 __u8 subop; 2864 __u8 status; 2865 __be16 r4; 2866 __be32 flags; 2867 struct fw_coiscsi_tgt_conn_attr { 2868 __be32 in_tid; 2869 __be16 in_port; 2870 __u8 in_type; 2871 __u8 r6; 2872 union fw_coiscsi_tgt_conn_attr_addr { 2873 struct fw_coiscsi_tgt_conn_attr_in_addr { 2874 __be32 addr; 2875 __be32 r7; 2876 __be32 r8[2]; 2877 } in_addr; 2878 struct fw_coiscsi_tgt_conn_attr_in_addr6 { 2879 __be64 addr[2]; 2880 } in_addr6; 2881 } u; 2882 } conn_attr; 2883 }; 2884 2885 #define S_FW_COISCSI_TGT_WR_PORTID 0 2886 #define M_FW_COISCSI_TGT_WR_PORTID 0x7 2887 #define V_FW_COISCSI_TGT_WR_PORTID(x) ((x) << S_FW_COISCSI_TGT_WR_PORTID) 2888 #define G_FW_COISCSI_TGT_WR_PORTID(x) \ 2889 (((x) >> S_FW_COISCSI_TGT_WR_PORTID) & M_FW_COISCSI_TGT_WR_PORTID) 2890 2891 struct fw_coiscsi_tgt_conn_wr { 2892 __be32 op_compl; 2893 __be32 flowid_len16; 2894 __u64 cookie; 2895 __u8 subop; 2896 __u8 status; 2897 __be16 iq_id; 2898 __be32 in_stid; 2899 __be32 io_id; 2900 __be32 flags_fin; 2901 union { 2902 struct fw_coiscsi_tgt_conn_tcp { 2903 __be16 in_sport; 2904 __be16 in_dport; 2905 __u8 wscale_wsen; 2906 __u8 r4[3]; 2907 union fw_coiscsi_tgt_conn_tcp_addr { 2908 struct fw_coiscsi_tgt_conn_tcp_in_addr { 2909 __be32 saddr; 2910 __be32 daddr; 2911 } in_addr; 2912 struct fw_coiscsi_tgt_conn_tcp_in_addr6 { 2913 __be64 saddr[2]; 2914 __be64 daddr[2]; 2915 } in_addr6; 2916 } u; 2917 } conn_tcp; 2918 struct fw_coiscsi_tgt_conn_stats { 2919 __be32 ddp_reqs; 2920 __be32 ddp_cmpls; 2921 __be16 ddp_aborts; 2922 __be16 ddp_bps; 2923 } stats; 2924 } u; 2925 struct fw_coiscsi_tgt_conn_iscsi { 2926 __be32 hdigest_to_ddp_pgsz; 2927 __be32 tgt_id; 2928 __be16 max_r2t; 2929 __be16 r5; 2930 __be32 max_burst; 2931 __be32 max_rdsl; 2932 __be32 max_tdsl; 2933 __be32 cur_sn; 2934 __be32 r6; 2935 } conn_iscsi; 2936 }; 2937 2938 #define S_FW_COISCSI_TGT_CONN_WR_PORTID 0 2939 #define M_FW_COISCSI_TGT_CONN_WR_PORTID 0x7 2940 #define V_FW_COISCSI_TGT_CONN_WR_PORTID(x) \ 2941 ((x) << S_FW_COISCSI_TGT_CONN_WR_PORTID) 2942 #define G_FW_COISCSI_TGT_CONN_WR_PORTID(x) \ 2943 (((x) >> S_FW_COISCSI_TGT_CONN_WR_PORTID) & \ 2944 M_FW_COISCSI_TGT_CONN_WR_PORTID) 2945 2946 #define S_FW_COISCSI_TGT_CONN_WR_FIN 0 2947 #define M_FW_COISCSI_TGT_CONN_WR_FIN 0x1 2948 #define V_FW_COISCSI_TGT_CONN_WR_FIN(x) ((x) << S_FW_COISCSI_TGT_CONN_WR_FIN) 2949 #define G_FW_COISCSI_TGT_CONN_WR_FIN(x) \ 2950 (((x) >> S_FW_COISCSI_TGT_CONN_WR_FIN) & M_FW_COISCSI_TGT_CONN_WR_FIN) 2951 #define F_FW_COISCSI_TGT_CONN_WR_FIN V_FW_COISCSI_TGT_CONN_WR_FIN(1U) 2952 2953 #define S_FW_COISCSI_TGT_CONN_WR_WSCALE 1 2954 #define M_FW_COISCSI_TGT_CONN_WR_WSCALE 0xf 2955 #define V_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ 2956 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSCALE) 2957 #define G_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ 2958 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSCALE) & \ 2959 M_FW_COISCSI_TGT_CONN_WR_WSCALE) 2960 2961 #define S_FW_COISCSI_TGT_CONN_WR_WSEN 0 2962 #define M_FW_COISCSI_TGT_CONN_WR_WSEN 0x1 2963 #define V_FW_COISCSI_TGT_CONN_WR_WSEN(x) \ 2964 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSEN) 2965 #define G_FW_COISCSI_TGT_CONN_WR_WSEN(x) \ 2966 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSEN) & M_FW_COISCSI_TGT_CONN_WR_WSEN) 2967 #define F_FW_COISCSI_TGT_CONN_WR_WSEN V_FW_COISCSI_TGT_CONN_WR_WSEN(1U) 2968 2969 struct fw_coiscsi_tgt_xmit_wr { 2970 __be32 op_to_immdlen; 2971 union { 2972 struct cmpl_stat { 2973 __be32 cmpl_status_pkd; 2974 } cs; 2975 struct flowid_len { 2976 __be32 flowid_len16; 2977 } fllen; 2978 } u; 2979 __u64 cookie; 2980 __be16 iq_id; 2981 __be16 r3; 2982 __be32 pz_off; 2983 __be32 t_xfer_len; 2984 union { 2985 __be32 tag; 2986 __be32 datasn; 2987 __be32 ddp_status; 2988 } cu; 2989 }; 2990 2991 #define S_FW_COISCSI_TGT_XMIT_WR_DDGST 23 2992 #define M_FW_COISCSI_TGT_XMIT_WR_DDGST 0x1 2993 #define V_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \ 2994 ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDGST) 2995 #define G_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \ 2996 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDGST) & M_FW_COISCSI_TGT_XMIT_WR_DDGST) 2997 #define F_FW_COISCSI_TGT_XMIT_WR_DDGST V_FW_COISCSI_TGT_XMIT_WR_DDGST(1U) 2998 2999 #define S_FW_COISCSI_TGT_XMIT_WR_HDGST 22 3000 #define M_FW_COISCSI_TGT_XMIT_WR_HDGST 0x1 3001 #define V_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \ 3002 ((x) << S_FW_COISCSI_TGT_XMIT_WR_HDGST) 3003 #define G_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \ 3004 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_HDGST) & M_FW_COISCSI_TGT_XMIT_WR_HDGST) 3005 #define F_FW_COISCSI_TGT_XMIT_WR_HDGST V_FW_COISCSI_TGT_XMIT_WR_HDGST(1U) 3006 3007 #define S_FW_COISCSI_TGT_XMIT_WR_DDP 20 3008 #define M_FW_COISCSI_TGT_XMIT_WR_DDP 0x1 3009 #define V_FW_COISCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDP) 3010 #define G_FW_COISCSI_TGT_XMIT_WR_DDP(x) \ 3011 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDP) & M_FW_COISCSI_TGT_XMIT_WR_DDP) 3012 #define F_FW_COISCSI_TGT_XMIT_WR_DDP V_FW_COISCSI_TGT_XMIT_WR_DDP(1U) 3013 3014 #define S_FW_COISCSI_TGT_XMIT_WR_ABORT 19 3015 #define M_FW_COISCSI_TGT_XMIT_WR_ABORT 0x1 3016 #define V_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \ 3017 ((x) << S_FW_COISCSI_TGT_XMIT_WR_ABORT) 3018 #define G_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \ 3019 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_ABORT) & M_FW_COISCSI_TGT_XMIT_WR_ABORT) 3020 #define F_FW_COISCSI_TGT_XMIT_WR_ABORT V_FW_COISCSI_TGT_XMIT_WR_ABORT(1U) 3021 3022 #define S_FW_COISCSI_TGT_XMIT_WR_FINAL 18 3023 #define M_FW_COISCSI_TGT_XMIT_WR_FINAL 0x1 3024 #define V_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \ 3025 ((x) << S_FW_COISCSI_TGT_XMIT_WR_FINAL) 3026 #define G_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \ 3027 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_FINAL) & M_FW_COISCSI_TGT_XMIT_WR_FINAL) 3028 #define F_FW_COISCSI_TGT_XMIT_WR_FINAL V_FW_COISCSI_TGT_XMIT_WR_FINAL(1U) 3029 3030 #define S_FW_COISCSI_TGT_XMIT_WR_PADLEN 16 3031 #define M_FW_COISCSI_TGT_XMIT_WR_PADLEN 0x3 3032 #define V_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ 3033 ((x) << S_FW_COISCSI_TGT_XMIT_WR_PADLEN) 3034 #define G_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ 3035 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_PADLEN) & \ 3036 M_FW_COISCSI_TGT_XMIT_WR_PADLEN) 3037 3038 #define S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 15 3039 #define M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 0x1 3040 #define V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \ 3041 ((x) << S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) 3042 #define G_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \ 3043 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) & \ 3044 M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) 3045 #define F_FW_COISCSI_TGT_XMIT_WR_INCSTATSN \ 3046 V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(1U) 3047 3048 #define S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0 3049 #define M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0xff 3050 #define V_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3051 ((x) << S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) 3052 #define G_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3053 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) & \ 3054 M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) 3055 3056 #define S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 8 3057 #define M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 0xff 3058 #define V_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ 3059 ((x) << S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) 3060 #define G_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ 3061 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) & \ 3062 M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) 3063 3064 struct fw_coiscsi_stats_wr { 3065 __be32 op_compl; 3066 __be32 flowid_len16; 3067 __u64 cookie; 3068 __u8 subop; 3069 __u8 status; 3070 union fw_coiscsi_stats { 3071 struct fw_coiscsi_resource { 3072 __u8 num_ipv4_tgt; 3073 __u8 num_ipv6_tgt; 3074 __be16 num_l2t_entries; 3075 __be16 num_csocks; 3076 __be16 num_tasks; 3077 __be16 num_ppods_zone[11]; 3078 __be32 num_bufll64; 3079 __u8 r2[12]; 3080 } rsrc; 3081 } u; 3082 }; 3083 3084 #define S_FW_COISCSI_STATS_WR_PORTID 0 3085 #define M_FW_COISCSI_STATS_WR_PORTID 0x7 3086 #define V_FW_COISCSI_STATS_WR_PORTID(x) ((x) << S_FW_COISCSI_STATS_WR_PORTID) 3087 #define G_FW_COISCSI_STATS_WR_PORTID(x) \ 3088 (((x) >> S_FW_COISCSI_STATS_WR_PORTID) & M_FW_COISCSI_STATS_WR_PORTID) 3089 3090 struct fw_isns_wr { 3091 __be32 op_compl; 3092 __be32 flowid_len16; 3093 __u64 cookie; 3094 __u8 subop; 3095 __u8 status; 3096 __be16 iq_id; 3097 __be16 vlanid; 3098 __be16 r4; 3099 struct fw_tcp_conn_attr { 3100 __be32 in_tid; 3101 __be16 in_port; 3102 __u8 in_type; 3103 __u8 r6; 3104 union fw_tcp_conn_attr_addr { 3105 struct fw_tcp_conn_attr_in_addr { 3106 __be32 addr; 3107 __be32 r7; 3108 __be32 r8[2]; 3109 } in_addr; 3110 struct fw_tcp_conn_attr_in_addr6 { 3111 __be64 addr[2]; 3112 } in_addr6; 3113 } u; 3114 } conn_attr; 3115 }; 3116 3117 #define S_FW_ISNS_WR_PORTID 0 3118 #define M_FW_ISNS_WR_PORTID 0x7 3119 #define V_FW_ISNS_WR_PORTID(x) ((x) << S_FW_ISNS_WR_PORTID) 3120 #define G_FW_ISNS_WR_PORTID(x) \ 3121 (((x) >> S_FW_ISNS_WR_PORTID) & M_FW_ISNS_WR_PORTID) 3122 3123 struct fw_isns_xmit_wr { 3124 __be32 op_to_immdlen; 3125 __be32 flowid_len16; 3126 __u64 cookie; 3127 __be16 iq_id; 3128 __be16 r4; 3129 __be32 xfer_len; 3130 __be64 r5; 3131 }; 3132 3133 #define S_FW_ISNS_XMIT_WR_IMMDLEN 0 3134 #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff 3135 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) 3136 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ 3137 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN) 3138 3139 /****************************************************************************** 3140 * F O F C O E W O R K R E Q U E S T s 3141 *******************************************/ 3142 3143 struct fw_fcoe_els_ct_wr { 3144 __be32 op_immdlen; 3145 __be32 flowid_len16; 3146 __be64 cookie; 3147 __be16 iqid; 3148 __u8 tmo_val; 3149 __u8 els_ct_type; 3150 __u8 ctl_pri; 3151 __u8 cp_en_class; 3152 __be16 xfer_cnt; 3153 __u8 fl_to_sp; 3154 __u8 l_id[3]; 3155 __u8 r5; 3156 __u8 r_id[3]; 3157 __be64 rsp_dmaaddr; 3158 __be32 rsp_dmalen; 3159 __be32 r6; 3160 }; 3161 3162 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 3163 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 3164 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 3165 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 3166 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 3167 3168 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 3169 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 3170 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 3171 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 3172 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 3173 3174 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 3175 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 3176 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 3177 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 3178 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 3179 3180 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 3181 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 3182 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 3183 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 3184 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 3185 3186 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 3187 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 3188 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 3189 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 3190 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 3191 3192 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 3193 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 3194 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 3195 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 3196 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 3197 3198 #define S_FW_FCOE_ELS_CT_WR_FL 2 3199 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 3200 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 3201 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 3202 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 3203 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 3204 3205 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 3206 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 3207 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 3208 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 3209 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 3210 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 3211 3212 #define S_FW_FCOE_ELS_CT_WR_SP 0 3213 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 3214 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 3215 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 3216 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 3217 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 3218 3219 /****************************************************************************** 3220 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 3221 *****************************************************************************/ 3222 3223 struct fw_scsi_write_wr { 3224 __be32 op_immdlen; 3225 __be32 flowid_len16; 3226 __be64 cookie; 3227 __be16 iqid; 3228 __u8 tmo_val; 3229 __u8 use_xfer_cnt; 3230 union fw_scsi_write_priv { 3231 struct fcoe_write_priv { 3232 __u8 ctl_pri; 3233 __u8 cp_en_class; 3234 __u8 r3_lo[2]; 3235 } fcoe; 3236 struct iscsi_write_priv { 3237 __u8 r3[4]; 3238 } iscsi; 3239 } u; 3240 __be32 xfer_cnt; 3241 __be32 ini_xfer_cnt; 3242 __be64 rsp_dmaaddr; 3243 __be32 rsp_dmalen; 3244 __be32 r4; 3245 }; 3246 3247 #define S_FW_SCSI_WRITE_WR_OPCODE 24 3248 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 3249 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 3250 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 3251 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 3252 3253 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 3254 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 3255 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 3256 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 3257 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 3258 3259 #define S_FW_SCSI_WRITE_WR_FLOWID 8 3260 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 3261 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 3262 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 3263 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 3264 3265 #define S_FW_SCSI_WRITE_WR_LEN16 0 3266 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 3267 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 3268 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 3269 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 3270 3271 #define S_FW_SCSI_WRITE_WR_CP_EN 6 3272 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 3273 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 3274 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 3275 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 3276 3277 #define S_FW_SCSI_WRITE_WR_CLASS 4 3278 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 3279 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 3280 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 3281 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 3282 3283 struct fw_scsi_read_wr { 3284 __be32 op_immdlen; 3285 __be32 flowid_len16; 3286 __be64 cookie; 3287 __be16 iqid; 3288 __u8 tmo_val; 3289 __u8 use_xfer_cnt; 3290 union fw_scsi_read_priv { 3291 struct fcoe_read_priv { 3292 __u8 ctl_pri; 3293 __u8 cp_en_class; 3294 __u8 r3_lo[2]; 3295 } fcoe; 3296 struct iscsi_read_priv { 3297 __u8 r3[4]; 3298 } iscsi; 3299 } u; 3300 __be32 xfer_cnt; 3301 __be32 ini_xfer_cnt; 3302 __be64 rsp_dmaaddr; 3303 __be32 rsp_dmalen; 3304 __be32 r4; 3305 }; 3306 3307 #define S_FW_SCSI_READ_WR_OPCODE 24 3308 #define M_FW_SCSI_READ_WR_OPCODE 0xff 3309 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 3310 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 3311 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 3312 3313 #define S_FW_SCSI_READ_WR_IMMDLEN 0 3314 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 3315 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 3316 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 3317 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 3318 3319 #define S_FW_SCSI_READ_WR_FLOWID 8 3320 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 3321 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 3322 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 3323 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 3324 3325 #define S_FW_SCSI_READ_WR_LEN16 0 3326 #define M_FW_SCSI_READ_WR_LEN16 0xff 3327 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 3328 #define G_FW_SCSI_READ_WR_LEN16(x) \ 3329 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 3330 3331 #define S_FW_SCSI_READ_WR_CP_EN 6 3332 #define M_FW_SCSI_READ_WR_CP_EN 0x3 3333 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 3334 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 3335 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 3336 3337 #define S_FW_SCSI_READ_WR_CLASS 4 3338 #define M_FW_SCSI_READ_WR_CLASS 0x3 3339 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 3340 #define G_FW_SCSI_READ_WR_CLASS(x) \ 3341 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 3342 3343 struct fw_scsi_cmd_wr { 3344 __be32 op_immdlen; 3345 __be32 flowid_len16; 3346 __be64 cookie; 3347 __be16 iqid; 3348 __u8 tmo_val; 3349 __u8 r3; 3350 union fw_scsi_cmd_priv { 3351 struct fcoe_cmd_priv { 3352 __u8 ctl_pri; 3353 __u8 cp_en_class; 3354 __u8 r4_lo[2]; 3355 } fcoe; 3356 struct iscsi_cmd_priv { 3357 __u8 r4[4]; 3358 } iscsi; 3359 } u; 3360 __u8 r5[8]; 3361 __be64 rsp_dmaaddr; 3362 __be32 rsp_dmalen; 3363 __be32 r6; 3364 }; 3365 3366 #define S_FW_SCSI_CMD_WR_OPCODE 24 3367 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 3368 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 3369 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 3370 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 3371 3372 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 3373 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 3374 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 3375 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 3376 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 3377 3378 #define S_FW_SCSI_CMD_WR_FLOWID 8 3379 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 3380 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 3381 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 3382 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 3383 3384 #define S_FW_SCSI_CMD_WR_LEN16 0 3385 #define M_FW_SCSI_CMD_WR_LEN16 0xff 3386 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 3387 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 3388 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 3389 3390 #define S_FW_SCSI_CMD_WR_CP_EN 6 3391 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 3392 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 3393 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 3394 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 3395 3396 #define S_FW_SCSI_CMD_WR_CLASS 4 3397 #define M_FW_SCSI_CMD_WR_CLASS 0x3 3398 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 3399 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 3400 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 3401 3402 struct fw_scsi_abrt_cls_wr { 3403 __be32 op_immdlen; 3404 __be32 flowid_len16; 3405 __be64 cookie; 3406 __be16 iqid; 3407 __u8 tmo_val; 3408 __u8 sub_opcode_to_chk_all_io; 3409 __u8 r3[4]; 3410 __be64 t_cookie; 3411 }; 3412 3413 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 3414 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 3415 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 3416 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 3417 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 3418 3419 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 3420 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 3421 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3422 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3423 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3424 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3425 3426 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 3427 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 3428 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 3429 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 3430 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 3431 3432 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 3433 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 3434 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 3435 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 3436 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 3437 3438 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 3439 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 3440 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3441 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3442 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3443 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 3444 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3445 3446 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 3447 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 3448 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 3449 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 3450 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 3451 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 3452 3453 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 3454 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 3455 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3456 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3457 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3458 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 3459 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3460 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 3461 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 3462 3463 struct fw_scsi_tgt_acc_wr { 3464 __be32 op_immdlen; 3465 __be32 flowid_len16; 3466 __be64 cookie; 3467 __be16 iqid; 3468 __u8 r3; 3469 __u8 use_burst_len; 3470 union fw_scsi_tgt_acc_priv { 3471 struct fcoe_tgt_acc_priv { 3472 __u8 ctl_pri; 3473 __u8 cp_en_class; 3474 __u8 r4_lo[2]; 3475 } fcoe; 3476 struct iscsi_tgt_acc_priv { 3477 __u8 r4[4]; 3478 } iscsi; 3479 } u; 3480 __be32 burst_len; 3481 __be32 rel_off; 3482 __be64 r5; 3483 __be32 r6; 3484 __be32 tot_xfer_len; 3485 }; 3486 3487 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 3488 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 3489 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 3490 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 3491 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 3492 3493 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 3494 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 3495 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3496 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 3497 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3498 3499 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 3500 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 3501 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 3502 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 3503 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 3504 3505 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 3506 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 3507 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 3508 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 3509 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 3510 3511 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 3512 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 3513 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 3514 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 3515 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 3516 3517 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 3518 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 3519 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 3520 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 3521 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 3522 3523 struct fw_scsi_tgt_xmit_wr { 3524 __be32 op_immdlen; 3525 __be32 flowid_len16; 3526 __be64 cookie; 3527 __be16 iqid; 3528 __u8 auto_rsp; 3529 __u8 use_xfer_cnt; 3530 union fw_scsi_tgt_xmit_priv { 3531 struct fcoe_tgt_xmit_priv { 3532 __u8 ctl_pri; 3533 __u8 cp_en_class; 3534 __u8 r3_lo[2]; 3535 } fcoe; 3536 struct iscsi_tgt_xmit_priv { 3537 __u8 r3[4]; 3538 } iscsi; 3539 } u; 3540 __be32 xfer_cnt; 3541 __be32 r4; 3542 __be64 r5; 3543 __be32 r6; 3544 __be32 tot_xfer_len; 3545 }; 3546 3547 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 3548 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 3549 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 3550 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 3551 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 3552 3553 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 3554 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 3555 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3556 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3557 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3558 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3559 3560 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 3561 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 3562 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 3563 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 3564 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 3565 3566 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 3567 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 3568 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 3569 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 3570 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 3571 3572 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 3573 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 3574 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 3575 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 3576 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 3577 3578 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 3579 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 3580 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 3581 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 3582 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 3583 3584 struct fw_scsi_tgt_rsp_wr { 3585 __be32 op_immdlen; 3586 __be32 flowid_len16; 3587 __be64 cookie; 3588 __be16 iqid; 3589 __u8 r3[2]; 3590 union fw_scsi_tgt_rsp_priv { 3591 struct fcoe_tgt_rsp_priv { 3592 __u8 ctl_pri; 3593 __u8 cp_en_class; 3594 __u8 r4_lo[2]; 3595 } fcoe; 3596 struct iscsi_tgt_rsp_priv { 3597 __u8 r4[4]; 3598 } iscsi; 3599 } u; 3600 __u8 r5[8]; 3601 }; 3602 3603 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 3604 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 3605 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 3606 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 3607 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 3608 3609 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 3610 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 3611 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3612 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 3613 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3614 3615 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 3616 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 3617 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 3618 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 3619 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 3620 3621 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 3622 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 3623 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 3624 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 3625 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 3626 3627 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 3628 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 3629 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 3630 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 3631 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 3632 3633 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 3634 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 3635 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 3636 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 3637 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 3638 3639 struct fw_pofcoe_tcb_wr { 3640 __be32 op_compl; 3641 __be32 equiq_to_len16; 3642 __be32 r4; 3643 __be32 xfer_len; 3644 __be32 tid_to_port; 3645 __be16 x_id; 3646 __be16 vlan_id; 3647 __be64 cookie; 3648 __be32 s_id; 3649 __be32 d_id; 3650 __be32 tag; 3651 __be16 r6; 3652 __be16 iqid; 3653 }; 3654 3655 #define S_FW_POFCOE_TCB_WR_TID 12 3656 #define M_FW_POFCOE_TCB_WR_TID 0xfffff 3657 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 3658 #define G_FW_POFCOE_TCB_WR_TID(x) \ 3659 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 3660 3661 #define S_FW_POFCOE_TCB_WR_ALLOC 4 3662 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 3663 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 3664 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 3665 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 3666 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 3667 3668 #define S_FW_POFCOE_TCB_WR_FREE 3 3669 #define M_FW_POFCOE_TCB_WR_FREE 0x1 3670 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 3671 #define G_FW_POFCOE_TCB_WR_FREE(x) \ 3672 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 3673 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 3674 3675 #define S_FW_POFCOE_TCB_WR_PORT 0 3676 #define M_FW_POFCOE_TCB_WR_PORT 0x7 3677 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 3678 #define G_FW_POFCOE_TCB_WR_PORT(x) \ 3679 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 3680 3681 struct fw_pofcoe_ulptx_wr { 3682 __be32 op_pkd; 3683 __be32 equiq_to_len16; 3684 __u64 cookie; 3685 }; 3686 3687 /******************************************************************* 3688 * T10 DIF related definition 3689 *******************************************************************/ 3690 struct fw_tx_pi_header { 3691 __be16 op_to_inline; 3692 __u8 pi_interval_tag_type; 3693 __u8 num_pi; 3694 __be32 pi_start4_pi_end4; 3695 __u8 tag_gen_enabled_pkd; 3696 __u8 num_pi_dsg; 3697 __be16 app_tag; 3698 __be32 ref_tag; 3699 }; 3700 3701 #define S_FW_TX_PI_HEADER_OP 8 3702 #define M_FW_TX_PI_HEADER_OP 0xff 3703 #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) 3704 #define G_FW_TX_PI_HEADER_OP(x) \ 3705 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) 3706 3707 #define S_FW_TX_PI_HEADER_ULPTXMORE 7 3708 #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 3709 #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) 3710 #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ 3711 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) 3712 #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) 3713 3714 #define S_FW_TX_PI_HEADER_PI_CONTROL 4 3715 #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 3716 #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) 3717 #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ 3718 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) 3719 3720 #define S_FW_TX_PI_HEADER_GUARD_TYPE 2 3721 #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 3722 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) 3723 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ 3724 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) 3725 #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) 3726 3727 #define S_FW_TX_PI_HEADER_VALIDATE 1 3728 #define M_FW_TX_PI_HEADER_VALIDATE 0x1 3729 #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) 3730 #define G_FW_TX_PI_HEADER_VALIDATE(x) \ 3731 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) 3732 #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) 3733 3734 #define S_FW_TX_PI_HEADER_INLINE 0 3735 #define M_FW_TX_PI_HEADER_INLINE 0x1 3736 #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) 3737 #define G_FW_TX_PI_HEADER_INLINE(x) \ 3738 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) 3739 #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) 3740 3741 #define S_FW_TX_PI_HEADER_PI_INTERVAL 7 3742 #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 3743 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3744 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) 3745 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3746 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) 3747 #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) 3748 3749 #define S_FW_TX_PI_HEADER_TAG_TYPE 5 3750 #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 3751 #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) 3752 #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ 3753 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) 3754 3755 #define S_FW_TX_PI_HEADER_PI_START4 22 3756 #define M_FW_TX_PI_HEADER_PI_START4 0x3ff 3757 #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) 3758 #define G_FW_TX_PI_HEADER_PI_START4(x) \ 3759 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) 3760 3761 #define S_FW_TX_PI_HEADER_PI_END4 0 3762 #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff 3763 #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) 3764 #define G_FW_TX_PI_HEADER_PI_END4(x) \ 3765 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) 3766 3767 #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 3768 #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 3769 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3770 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3771 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3772 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ 3773 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3774 3775 enum fw_pi_error_type { 3776 FW_PI_ERROR_GUARD_CHECK_FAILED = 0, 3777 }; 3778 3779 struct fw_pi_error { 3780 __be32 err_type_pkd; 3781 __be32 flowid_len16; 3782 __be16 r2; 3783 __be16 app_tag; 3784 __be32 ref_tag; 3785 __be32 pisc[4]; 3786 }; 3787 3788 #define S_FW_PI_ERROR_ERR_TYPE 24 3789 #define M_FW_PI_ERROR_ERR_TYPE 0xff 3790 #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) 3791 #define G_FW_PI_ERROR_ERR_TYPE(x) \ 3792 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) 3793 3794 struct fw_tlstx_data_wr { 3795 __be32 op_to_immdlen; 3796 __be32 flowid_len16; 3797 __be32 plen; 3798 __be32 lsodisable_to_flags; 3799 __be32 r5; 3800 __be32 ctxloc_to_exp; 3801 __be16 mfs; 3802 __be16 adjustedplen_pkd; 3803 __be16 expinplenmax_pkd; 3804 __u8 pdusinplenmax_pkd; 3805 __u8 r10; 3806 }; 3807 3808 #define S_FW_TLSTX_DATA_WR_OPCODE 24 3809 #define M_FW_TLSTX_DATA_WR_OPCODE 0xff 3810 #define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE) 3811 #define G_FW_TLSTX_DATA_WR_OPCODE(x) \ 3812 (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE) 3813 3814 #define S_FW_TLSTX_DATA_WR_COMPL 21 3815 #define M_FW_TLSTX_DATA_WR_COMPL 0x1 3816 #define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL) 3817 #define G_FW_TLSTX_DATA_WR_COMPL(x) \ 3818 (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL) 3819 #define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U) 3820 3821 #define S_FW_TLSTX_DATA_WR_IMMDLEN 0 3822 #define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff 3823 #define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN) 3824 #define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \ 3825 (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN) 3826 3827 #define S_FW_TLSTX_DATA_WR_FLOWID 8 3828 #define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff 3829 #define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID) 3830 #define G_FW_TLSTX_DATA_WR_FLOWID(x) \ 3831 (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID) 3832 3833 #define S_FW_TLSTX_DATA_WR_LEN16 0 3834 #define M_FW_TLSTX_DATA_WR_LEN16 0xff 3835 #define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16) 3836 #define G_FW_TLSTX_DATA_WR_LEN16(x) \ 3837 (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16) 3838 3839 #define S_FW_TLSTX_DATA_WR_LSODISABLE 31 3840 #define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1 3841 #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3842 ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE) 3843 #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3844 (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE) 3845 #define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U) 3846 3847 #define S_FW_TLSTX_DATA_WR_ALIGNPLD 30 3848 #define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1 3849 #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD) 3850 #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \ 3851 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD) 3852 #define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U) 3853 3854 #define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29 3855 #define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1 3856 #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3857 ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3858 #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3859 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \ 3860 M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3861 #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U) 3862 3863 #define S_FW_TLSTX_DATA_WR_FLAGS 0 3864 #define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff 3865 #define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS) 3866 #define G_FW_TLSTX_DATA_WR_FLAGS(x) \ 3867 (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS) 3868 3869 #define S_FW_TLSTX_DATA_WR_CTXLOC 30 3870 #define M_FW_TLSTX_DATA_WR_CTXLOC 0x3 3871 #define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC) 3872 #define G_FW_TLSTX_DATA_WR_CTXLOC(x) \ 3873 (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC) 3874 3875 #define S_FW_TLSTX_DATA_WR_IVDSGL 29 3876 #define M_FW_TLSTX_DATA_WR_IVDSGL 0x1 3877 #define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL) 3878 #define G_FW_TLSTX_DATA_WR_IVDSGL(x) \ 3879 (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL) 3880 #define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U) 3881 3882 #define S_FW_TLSTX_DATA_WR_KEYSIZE 24 3883 #define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f 3884 #define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE) 3885 #define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \ 3886 (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE) 3887 3888 #define S_FW_TLSTX_DATA_WR_NUMIVS 14 3889 #define M_FW_TLSTX_DATA_WR_NUMIVS 0xff 3890 #define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS) 3891 #define G_FW_TLSTX_DATA_WR_NUMIVS(x) \ 3892 (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS) 3893 3894 #define S_FW_TLSTX_DATA_WR_EXP 0 3895 #define M_FW_TLSTX_DATA_WR_EXP 0x3fff 3896 #define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP) 3897 #define G_FW_TLSTX_DATA_WR_EXP(x) \ 3898 (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP) 3899 3900 #define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1 3901 #define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff 3902 #define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3903 ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3904 #define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3905 (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \ 3906 M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3907 3908 #define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4 3909 #define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff 3910 #define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3911 ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3912 #define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3913 (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \ 3914 M_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3915 3916 #define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2 3917 #define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f 3918 #define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3919 ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3920 #define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3921 (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \ 3922 M_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3923 3924 struct fw_crypto_lookaside_wr { 3925 __be32 op_to_cctx_size; 3926 __be32 len16_pkd; 3927 __be32 session_id; 3928 __be32 rx_chid_to_rx_q_id; 3929 __be32 key_addr; 3930 __be32 pld_size_hash_size; 3931 __be64 cookie; 3932 }; 3933 3934 #define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24 3935 #define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff 3936 #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3937 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3938 #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3939 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \ 3940 M_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3941 3942 #define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23 3943 #define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1 3944 #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3945 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3946 #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3947 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \ 3948 M_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3949 #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U) 3950 3951 #define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15 3952 #define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff 3953 #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 3954 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 3955 #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 3956 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \ 3957 M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 3958 3959 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5 3960 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3 3961 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 3962 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 3963 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 3964 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \ 3965 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 3966 3967 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0 3968 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f 3969 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 3970 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 3971 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 3972 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \ 3973 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 3974 3975 #define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0 3976 #define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff 3977 #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 3978 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16) 3979 #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 3980 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \ 3981 M_FW_CRYPTO_LOOKASIDE_WR_LEN16) 3982 3983 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29 3984 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3 3985 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 3986 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 3987 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 3988 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \ 3989 M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 3990 3991 #define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27 3992 #define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3 3993 #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 3994 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB) 3995 #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 3996 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB) 3997 3998 #define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25 3999 #define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3 4000 #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4001 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4002 #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4003 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \ 4004 M_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4005 4006 #define S_FW_CRYPTO_LOOKASIDE_WR_IV 23 4007 #define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3 4008 #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4009 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV) 4010 #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4011 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV) 4012 4013 #define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15 4014 #define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff 4015 #define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4016 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4017 #define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4018 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\ 4019 M_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4020 4021 #define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10 4022 #define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3 4023 #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4024 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4025 #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4026 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \ 4027 M_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4028 4029 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0 4030 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff 4031 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4032 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4033 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4034 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \ 4035 M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4036 4037 #define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24 4038 #define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff 4039 #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4040 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4041 #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4042 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \ 4043 M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4044 4045 #define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17 4046 #define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f 4047 #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4048 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4049 #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4050 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \ 4051 M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4052 4053 /****************************************************************************** 4054 * C O M M A N D s 4055 *********************/ 4056 4057 /* 4058 * The maximum length of time, in miliseconds, that we expect any firmware 4059 * command to take to execute and return a reply to the host. The RESET 4060 * and INITIALIZE commands can take a fair amount of time to execute but 4061 * most execute in far less time than this maximum. This constant is used 4062 * by host software to determine how long to wait for a firmware command 4063 * reply before declaring the firmware as dead/unreachable ... 4064 */ 4065 #define FW_CMD_MAX_TIMEOUT 10000 4066 4067 /* 4068 * If a host driver does a HELLO and discovers that there's already a MASTER 4069 * selected, we may have to wait for that MASTER to finish issuing RESET, 4070 * configuration and INITIALIZE commands. Also, there's a possibility that 4071 * our own HELLO may get lost if it happens right as the MASTER is issuign a 4072 * RESET command, so we need to be willing to make a few retries of our HELLO. 4073 */ 4074 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 4075 #define FW_CMD_HELLO_RETRIES 3 4076 4077 enum fw_cmd_opcodes { 4078 FW_LDST_CMD = 0x01, 4079 FW_RESET_CMD = 0x03, 4080 FW_HELLO_CMD = 0x04, 4081 FW_BYE_CMD = 0x05, 4082 FW_INITIALIZE_CMD = 0x06, 4083 FW_CAPS_CONFIG_CMD = 0x07, 4084 FW_PARAMS_CMD = 0x08, 4085 FW_PFVF_CMD = 0x09, 4086 FW_IQ_CMD = 0x10, 4087 FW_EQ_MNGT_CMD = 0x11, 4088 FW_EQ_ETH_CMD = 0x12, 4089 FW_EQ_CTRL_CMD = 0x13, 4090 FW_EQ_OFLD_CMD = 0x21, 4091 FW_VI_CMD = 0x14, 4092 FW_VI_MAC_CMD = 0x15, 4093 FW_VI_RXMODE_CMD = 0x16, 4094 FW_VI_ENABLE_CMD = 0x17, 4095 FW_VI_STATS_CMD = 0x1a, 4096 FW_ACL_MAC_CMD = 0x18, 4097 FW_ACL_VLAN_CMD = 0x19, 4098 FW_PORT_CMD = 0x1b, 4099 FW_PORT_STATS_CMD = 0x1c, 4100 FW_PORT_LB_STATS_CMD = 0x1d, 4101 FW_PORT_TRACE_CMD = 0x1e, 4102 FW_PORT_TRACE_MMAP_CMD = 0x1f, 4103 FW_RSS_IND_TBL_CMD = 0x20, 4104 FW_RSS_GLB_CONFIG_CMD = 0x22, 4105 FW_RSS_VI_CONFIG_CMD = 0x23, 4106 FW_SCHED_CMD = 0x24, 4107 FW_DEVLOG_CMD = 0x25, 4108 FW_WATCHDOG_CMD = 0x27, 4109 FW_CLIP_CMD = 0x28, 4110 FW_CHNET_IFACE_CMD = 0x26, 4111 FW_FCOE_RES_INFO_CMD = 0x31, 4112 FW_FCOE_LINK_CMD = 0x32, 4113 FW_FCOE_VNP_CMD = 0x33, 4114 FW_FCOE_SPARAMS_CMD = 0x35, 4115 FW_FCOE_STATS_CMD = 0x37, 4116 FW_FCOE_FCF_CMD = 0x38, 4117 FW_DCB_IEEE_CMD = 0x3a, 4118 FW_DIAG_CMD = 0x3d, 4119 FW_PTP_CMD = 0x3e, 4120 FW_HMA_CMD = 0x3f, 4121 FW_LASTC2E_CMD = 0x40, 4122 FW_ERROR_CMD = 0x80, 4123 FW_DEBUG_CMD = 0x81, 4124 }; 4125 4126 enum fw_cmd_cap { 4127 FW_CMD_CAP_PF = 0x01, 4128 FW_CMD_CAP_DMAQ = 0x02, 4129 FW_CMD_CAP_PORT = 0x04, 4130 FW_CMD_CAP_PORTPROMISC = 0x08, 4131 FW_CMD_CAP_PORTSTATS = 0x10, 4132 FW_CMD_CAP_VF = 0x80, 4133 }; 4134 4135 /* 4136 * Generic command header flit0 4137 */ 4138 struct fw_cmd_hdr { 4139 __be32 hi; 4140 __be32 lo; 4141 }; 4142 4143 #define S_FW_CMD_OP 24 4144 #define M_FW_CMD_OP 0xff 4145 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 4146 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 4147 4148 #define S_FW_CMD_REQUEST 23 4149 #define M_FW_CMD_REQUEST 0x1 4150 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 4151 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 4152 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 4153 4154 #define S_FW_CMD_READ 22 4155 #define M_FW_CMD_READ 0x1 4156 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 4157 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 4158 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 4159 4160 #define S_FW_CMD_WRITE 21 4161 #define M_FW_CMD_WRITE 0x1 4162 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 4163 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 4164 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 4165 4166 #define S_FW_CMD_EXEC 20 4167 #define M_FW_CMD_EXEC 0x1 4168 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 4169 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 4170 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 4171 4172 #define S_FW_CMD_RAMASK 20 4173 #define M_FW_CMD_RAMASK 0xf 4174 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 4175 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 4176 4177 #define S_FW_CMD_RETVAL 8 4178 #define M_FW_CMD_RETVAL 0xff 4179 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 4180 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 4181 4182 #define S_FW_CMD_LEN16 0 4183 #define M_FW_CMD_LEN16 0xff 4184 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 4185 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 4186 4187 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 4188 4189 /* 4190 * address spaces 4191 */ 4192 enum fw_ldst_addrspc { 4193 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 4194 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 4195 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 4196 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 4197 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 4198 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 4199 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 4200 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 4201 FW_LDST_ADDRSPC_MDIO = 0x0018, 4202 FW_LDST_ADDRSPC_MPS = 0x0020, 4203 FW_LDST_ADDRSPC_FUNC = 0x0028, 4204 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 4205 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 4206 FW_LDST_ADDRSPC_LE = 0x0030, 4207 FW_LDST_ADDRSPC_I2C = 0x0038, 4208 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 4209 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 4210 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 4211 FW_LDST_ADDRSPC_CIM_Q = 0x0048, 4212 }; 4213 4214 /* 4215 * MDIO VSC8634 register access control field 4216 */ 4217 enum fw_ldst_mdio_vsc8634_aid { 4218 FW_LDST_MDIO_VS_STANDARD, 4219 FW_LDST_MDIO_VS_EXTENDED, 4220 FW_LDST_MDIO_VS_GPIO 4221 }; 4222 4223 enum fw_ldst_mps_fid { 4224 FW_LDST_MPS_ATRB, 4225 FW_LDST_MPS_RPLC 4226 }; 4227 4228 enum fw_ldst_func_access_ctl { 4229 FW_LDST_FUNC_ACC_CTL_VIID, 4230 FW_LDST_FUNC_ACC_CTL_FID 4231 }; 4232 4233 enum fw_ldst_func_mod_index { 4234 FW_LDST_FUNC_MPS 4235 }; 4236 4237 struct fw_ldst_cmd { 4238 __be32 op_to_addrspace; 4239 __be32 cycles_to_len16; 4240 union fw_ldst { 4241 struct fw_ldst_addrval { 4242 __be32 addr; 4243 __be32 val; 4244 } addrval; 4245 struct fw_ldst_idctxt { 4246 __be32 physid; 4247 __be32 msg_ctxtflush; 4248 __be32 ctxt_data7; 4249 __be32 ctxt_data6; 4250 __be32 ctxt_data5; 4251 __be32 ctxt_data4; 4252 __be32 ctxt_data3; 4253 __be32 ctxt_data2; 4254 __be32 ctxt_data1; 4255 __be32 ctxt_data0; 4256 } idctxt; 4257 struct fw_ldst_mdio { 4258 __be16 paddr_mmd; 4259 __be16 raddr; 4260 __be16 vctl; 4261 __be16 rval; 4262 } mdio; 4263 struct fw_ldst_cim_rq { 4264 __u8 req_first64[8]; 4265 __u8 req_second64[8]; 4266 __u8 resp_first64[8]; 4267 __u8 resp_second64[8]; 4268 __be32 r3[2]; 4269 } cim_rq; 4270 union fw_ldst_mps { 4271 struct fw_ldst_mps_rplc { 4272 __be16 fid_idx; 4273 __be16 rplcpf_pkd; 4274 __be32 rplc255_224; 4275 __be32 rplc223_192; 4276 __be32 rplc191_160; 4277 __be32 rplc159_128; 4278 __be32 rplc127_96; 4279 __be32 rplc95_64; 4280 __be32 rplc63_32; 4281 __be32 rplc31_0; 4282 } rplc; 4283 struct fw_ldst_mps_atrb { 4284 __be16 fid_mpsid; 4285 __be16 r2[3]; 4286 __be32 r3[2]; 4287 __be32 r4; 4288 __be32 atrb; 4289 __be16 vlan[16]; 4290 } atrb; 4291 } mps; 4292 struct fw_ldst_func { 4293 __u8 access_ctl; 4294 __u8 mod_index; 4295 __be16 ctl_id; 4296 __be32 offset; 4297 __be64 data0; 4298 __be64 data1; 4299 } func; 4300 struct fw_ldst_pcie { 4301 __u8 ctrl_to_fn; 4302 __u8 bnum; 4303 __u8 r; 4304 __u8 ext_r; 4305 __u8 select_naccess; 4306 __u8 pcie_fn; 4307 __be16 nset_pkd; 4308 __be32 data[12]; 4309 } pcie; 4310 struct fw_ldst_i2c_deprecated { 4311 __u8 pid_pkd; 4312 __u8 base; 4313 __u8 boffset; 4314 __u8 data; 4315 __be32 r9; 4316 } i2c_deprecated; 4317 struct fw_ldst_i2c { 4318 __u8 pid; 4319 __u8 did; 4320 __u8 boffset; 4321 __u8 blen; 4322 __be32 r9; 4323 __u8 data[48]; 4324 } i2c; 4325 struct fw_ldst_le { 4326 __be32 index; 4327 __be32 r9; 4328 __u8 val[33]; 4329 __u8 r11[7]; 4330 } le; 4331 } u; 4332 }; 4333 4334 #define S_FW_LDST_CMD_ADDRSPACE 0 4335 #define M_FW_LDST_CMD_ADDRSPACE 0xff 4336 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 4337 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 4338 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 4339 4340 #define S_FW_LDST_CMD_CYCLES 16 4341 #define M_FW_LDST_CMD_CYCLES 0xffff 4342 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 4343 #define G_FW_LDST_CMD_CYCLES(x) \ 4344 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 4345 4346 #define S_FW_LDST_CMD_MSG 31 4347 #define M_FW_LDST_CMD_MSG 0x1 4348 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 4349 #define G_FW_LDST_CMD_MSG(x) \ 4350 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 4351 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 4352 4353 #define S_FW_LDST_CMD_CTXTFLUSH 30 4354 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 4355 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 4356 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 4357 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 4358 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 4359 4360 #define S_FW_LDST_CMD_PADDR 8 4361 #define M_FW_LDST_CMD_PADDR 0x1f 4362 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 4363 #define G_FW_LDST_CMD_PADDR(x) \ 4364 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 4365 4366 #define S_FW_LDST_CMD_MMD 0 4367 #define M_FW_LDST_CMD_MMD 0x1f 4368 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 4369 #define G_FW_LDST_CMD_MMD(x) \ 4370 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 4371 4372 #define S_FW_LDST_CMD_FID 15 4373 #define M_FW_LDST_CMD_FID 0x1 4374 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 4375 #define G_FW_LDST_CMD_FID(x) \ 4376 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 4377 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 4378 4379 #define S_FW_LDST_CMD_IDX 0 4380 #define M_FW_LDST_CMD_IDX 0x7fff 4381 #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) 4382 #define G_FW_LDST_CMD_IDX(x) \ 4383 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) 4384 4385 #define S_FW_LDST_CMD_RPLCPF 0 4386 #define M_FW_LDST_CMD_RPLCPF 0xff 4387 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 4388 #define G_FW_LDST_CMD_RPLCPF(x) \ 4389 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 4390 4391 #define S_FW_LDST_CMD_MPSID 0 4392 #define M_FW_LDST_CMD_MPSID 0x7fff 4393 #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) 4394 #define G_FW_LDST_CMD_MPSID(x) \ 4395 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) 4396 4397 #define S_FW_LDST_CMD_CTRL 7 4398 #define M_FW_LDST_CMD_CTRL 0x1 4399 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 4400 #define G_FW_LDST_CMD_CTRL(x) \ 4401 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 4402 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 4403 4404 #define S_FW_LDST_CMD_LC 4 4405 #define M_FW_LDST_CMD_LC 0x1 4406 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 4407 #define G_FW_LDST_CMD_LC(x) \ 4408 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 4409 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 4410 4411 #define S_FW_LDST_CMD_AI 3 4412 #define M_FW_LDST_CMD_AI 0x1 4413 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 4414 #define G_FW_LDST_CMD_AI(x) \ 4415 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 4416 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 4417 4418 #define S_FW_LDST_CMD_FN 0 4419 #define M_FW_LDST_CMD_FN 0x7 4420 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 4421 #define G_FW_LDST_CMD_FN(x) \ 4422 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 4423 4424 #define S_FW_LDST_CMD_SELECT 4 4425 #define M_FW_LDST_CMD_SELECT 0xf 4426 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 4427 #define G_FW_LDST_CMD_SELECT(x) \ 4428 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 4429 4430 #define S_FW_LDST_CMD_NACCESS 0 4431 #define M_FW_LDST_CMD_NACCESS 0xf 4432 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 4433 #define G_FW_LDST_CMD_NACCESS(x) \ 4434 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 4435 4436 #define S_FW_LDST_CMD_NSET 14 4437 #define M_FW_LDST_CMD_NSET 0x3 4438 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 4439 #define G_FW_LDST_CMD_NSET(x) \ 4440 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 4441 4442 #define S_FW_LDST_CMD_PID 6 4443 #define M_FW_LDST_CMD_PID 0x3 4444 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 4445 #define G_FW_LDST_CMD_PID(x) \ 4446 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 4447 4448 struct fw_reset_cmd { 4449 __be32 op_to_write; 4450 __be32 retval_len16; 4451 __be32 val; 4452 __be32 halt_pkd; 4453 }; 4454 4455 #define S_FW_RESET_CMD_HALT 31 4456 #define M_FW_RESET_CMD_HALT 0x1 4457 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 4458 #define G_FW_RESET_CMD_HALT(x) \ 4459 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 4460 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 4461 4462 enum { 4463 FW_HELLO_CMD_STAGE_OS = 0, 4464 FW_HELLO_CMD_STAGE_PREOS0 = 1, 4465 FW_HELLO_CMD_STAGE_PREOS1 = 2, 4466 FW_HELLO_CMD_STAGE_POSTOS = 3, 4467 }; 4468 4469 struct fw_hello_cmd { 4470 __be32 op_to_write; 4471 __be32 retval_len16; 4472 __be32 err_to_clearinit; 4473 __be32 fwrev; 4474 }; 4475 4476 #define S_FW_HELLO_CMD_ERR 31 4477 #define M_FW_HELLO_CMD_ERR 0x1 4478 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 4479 #define G_FW_HELLO_CMD_ERR(x) \ 4480 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 4481 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 4482 4483 #define S_FW_HELLO_CMD_INIT 30 4484 #define M_FW_HELLO_CMD_INIT 0x1 4485 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 4486 #define G_FW_HELLO_CMD_INIT(x) \ 4487 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 4488 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 4489 4490 #define S_FW_HELLO_CMD_MASTERDIS 29 4491 #define M_FW_HELLO_CMD_MASTERDIS 0x1 4492 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 4493 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 4494 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 4495 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 4496 4497 #define S_FW_HELLO_CMD_MASTERFORCE 28 4498 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 4499 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 4500 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 4501 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 4502 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 4503 4504 #define S_FW_HELLO_CMD_MBMASTER 24 4505 #define M_FW_HELLO_CMD_MBMASTER 0xf 4506 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 4507 #define G_FW_HELLO_CMD_MBMASTER(x) \ 4508 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 4509 4510 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 4511 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 4512 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 4513 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 4514 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 4515 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 4516 4517 #define S_FW_HELLO_CMD_MBASYNCNOT 20 4518 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 4519 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 4520 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 4521 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 4522 4523 #define S_FW_HELLO_CMD_STAGE 17 4524 #define M_FW_HELLO_CMD_STAGE 0x7 4525 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 4526 #define G_FW_HELLO_CMD_STAGE(x) \ 4527 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 4528 4529 #define S_FW_HELLO_CMD_CLEARINIT 16 4530 #define M_FW_HELLO_CMD_CLEARINIT 0x1 4531 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 4532 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 4533 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 4534 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 4535 4536 struct fw_bye_cmd { 4537 __be32 op_to_write; 4538 __be32 retval_len16; 4539 __be64 r3; 4540 }; 4541 4542 struct fw_initialize_cmd { 4543 __be32 op_to_write; 4544 __be32 retval_len16; 4545 __be64 r3; 4546 }; 4547 4548 enum fw_caps_config_hm { 4549 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 4550 FW_CAPS_CONFIG_HM_PL = 0x00000002, 4551 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 4552 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 4553 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 4554 FW_CAPS_CONFIG_HM_TP = 0x00000020, 4555 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 4556 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 4557 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 4558 FW_CAPS_CONFIG_HM_MC = 0x00000200, 4559 FW_CAPS_CONFIG_HM_LE = 0x00000400, 4560 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 4561 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 4562 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 4563 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 4564 FW_CAPS_CONFIG_HM_MI = 0x00008000, 4565 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 4566 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 4567 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 4568 FW_CAPS_CONFIG_HM_MA = 0x00080000, 4569 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 4570 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 4571 FW_CAPS_CONFIG_HM_UART = 0x00400000, 4572 FW_CAPS_CONFIG_HM_SF = 0x00800000, 4573 }; 4574 4575 /* 4576 * The VF Register Map. 4577 * 4578 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 4579 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 4580 * the Slice to Module Map Table (see below) in the Physical Function Register 4581 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 4582 * and Offset registers in the PF Register Map. The MBDATA base address is 4583 * quite constrained as it determines the Mailbox Data addresses for both PFs 4584 * and VFs, and therefore must fit in both the VF and PF Register Maps without 4585 * overlapping other registers. 4586 */ 4587 #define FW_T4VF_SGE_BASE_ADDR 0x0000 4588 #define FW_T4VF_MPS_BASE_ADDR 0x0100 4589 #define FW_T4VF_PL_BASE_ADDR 0x0200 4590 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 4591 #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */ 4592 #define FW_T4VF_CIM_BASE_ADDR 0x0300 4593 4594 #define FW_T4VF_REGMAP_START 0x0000 4595 #define FW_T4VF_REGMAP_SIZE 0x0400 4596 4597 enum fw_caps_config_nbm { 4598 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 4599 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 4600 }; 4601 4602 enum fw_caps_config_link { 4603 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 4604 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 4605 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 4606 }; 4607 4608 enum fw_caps_config_switch { 4609 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 4610 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 4611 }; 4612 4613 enum fw_caps_config_nic { 4614 FW_CAPS_CONFIG_NIC = 0x00000001, 4615 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 4616 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 4617 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 4618 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 4619 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 4620 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 4621 }; 4622 4623 enum fw_caps_config_toe { 4624 FW_CAPS_CONFIG_TOE = 0x00000001, 4625 }; 4626 4627 enum fw_caps_config_rdma { 4628 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 4629 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 4630 }; 4631 4632 enum fw_caps_config_iscsi { 4633 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 4634 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 4635 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 4636 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 4637 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 4638 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 4639 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, 4640 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080, 4641 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100, 4642 }; 4643 4644 enum fw_caps_config_crypto { 4645 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001, 4646 FW_CAPS_CONFIG_TLSKEYS = 0x00000002, 4647 FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004, 4648 }; 4649 4650 enum fw_caps_config_fcoe { 4651 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 4652 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 4653 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 4654 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 4655 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 4656 }; 4657 4658 enum fw_memtype_cf { 4659 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 4660 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 4661 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 4662 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 4663 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 4664 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 4665 }; 4666 4667 struct fw_caps_config_cmd { 4668 __be32 op_to_write; 4669 __be32 cfvalid_to_len16; 4670 __be32 r2; 4671 __be32 hwmbitmap; 4672 __be16 nbmcaps; 4673 __be16 linkcaps; 4674 __be16 switchcaps; 4675 __be16 r3; 4676 __be16 niccaps; 4677 __be16 toecaps; 4678 __be16 rdmacaps; 4679 __be16 cryptocaps; 4680 __be16 iscsicaps; 4681 __be16 fcoecaps; 4682 __be32 cfcsum; 4683 __be32 finiver; 4684 __be32 finicsum; 4685 }; 4686 4687 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 4688 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 4689 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 4690 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 4691 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 4692 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 4693 4694 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 4695 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 4696 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4697 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4698 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4699 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 4700 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4701 4702 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 4703 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 4704 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4705 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4706 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4707 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 4708 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4709 4710 /* 4711 * params command mnemonics 4712 */ 4713 enum fw_params_mnem { 4714 FW_PARAMS_MNEM_DEV = 1, /* device params */ 4715 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 4716 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 4717 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 4718 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 4719 FW_PARAMS_MNEM_LAST 4720 }; 4721 4722 /* 4723 * device parameters 4724 */ 4725 enum fw_params_param_dev { 4726 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 4727 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 4728 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 4729 * allocated by the device's 4730 * Lookup Engine 4731 */ 4732 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 4733 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 4734 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 4735 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 4736 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 4737 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 4738 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 4739 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 4740 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 4741 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 4742 FW_PARAMS_PARAM_DEV_CF = 0x0D, 4743 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 4744 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 4745 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 4746 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 4747 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 4748 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 4749 */ 4750 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 4751 */ 4752 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 4753 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 4754 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 4755 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 4756 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, 4757 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 4758 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 4759 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 4760 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 4761 4762 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 4763 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F, 4764 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20, 4765 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21, 4766 FW_PARAMS_PARAM_DEV_RING_BACKBONE = 0x22, 4767 FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23, 4768 FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24, 4769 }; 4770 4771 /* 4772 * dev bypass parameters; actions and modes 4773 */ 4774 enum fw_params_param_dev_bypass { 4775 4776 /* actions 4777 */ 4778 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 4779 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 4780 4781 /* modes 4782 */ 4783 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 4784 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 4785 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 4786 }; 4787 4788 enum fw_params_param_dev_phyfw { 4789 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 4790 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 4791 }; 4792 4793 enum fw_params_param_dev_diag { 4794 FW_PARAM_DEV_DIAG_TMP = 0x00, 4795 FW_PARAM_DEV_DIAG_VDD = 0x01, 4796 FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02, 4797 }; 4798 4799 enum fw_params_param_dev_fwcache { 4800 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 4801 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 4802 }; 4803 4804 /* 4805 * physical and virtual function parameters 4806 */ 4807 enum fw_params_param_pfvf { 4808 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 4809 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 4810 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 4811 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 4812 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 4813 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 4814 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 4815 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 4816 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 4817 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 4818 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 4819 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 4820 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 4821 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 4822 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 4823 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 4824 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 4825 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 4826 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 4827 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 4828 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 4829 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 4830 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 4831 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 4832 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 4833 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 4834 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 4835 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 4836 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 4837 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 4838 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 4839 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 4840 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 4841 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 4842 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 4843 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 4844 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 4845 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 4846 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 4847 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 4848 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 4849 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 4850 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 4851 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 4852 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 4853 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 4854 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 4855 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 4856 FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38, 4857 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 4858 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 4859 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B, 4860 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C, 4861 }; 4862 4863 /* 4864 * dma queue parameters 4865 */ 4866 enum fw_params_param_dmaq { 4867 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 4868 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 4869 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 4870 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03, 4871 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 4872 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 4873 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 4874 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 4875 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14, 4876 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 4877 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30 4878 }; 4879 4880 /* 4881 * chnet parameters 4882 */ 4883 enum fw_params_param_chnet { 4884 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, 4885 }; 4886 4887 enum fw_params_param_chnet_flags { 4888 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, 4889 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, 4890 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, 4891 }; 4892 4893 #define S_FW_PARAMS_MNEM 24 4894 #define M_FW_PARAMS_MNEM 0xff 4895 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 4896 #define G_FW_PARAMS_MNEM(x) \ 4897 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 4898 4899 #define S_FW_PARAMS_PARAM_X 16 4900 #define M_FW_PARAMS_PARAM_X 0xff 4901 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 4902 #define G_FW_PARAMS_PARAM_X(x) \ 4903 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 4904 4905 #define S_FW_PARAMS_PARAM_Y 8 4906 #define M_FW_PARAMS_PARAM_Y 0xff 4907 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 4908 #define G_FW_PARAMS_PARAM_Y(x) \ 4909 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 4910 4911 #define S_FW_PARAMS_PARAM_Z 0 4912 #define M_FW_PARAMS_PARAM_Z 0xff 4913 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 4914 #define G_FW_PARAMS_PARAM_Z(x) \ 4915 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 4916 4917 #define S_FW_PARAMS_PARAM_XYZ 0 4918 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 4919 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 4920 #define G_FW_PARAMS_PARAM_XYZ(x) \ 4921 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 4922 4923 #define S_FW_PARAMS_PARAM_YZ 0 4924 #define M_FW_PARAMS_PARAM_YZ 0xffff 4925 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 4926 #define G_FW_PARAMS_PARAM_YZ(x) \ 4927 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 4928 4929 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31 4930 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1 4931 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4932 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4933 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4934 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \ 4935 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4936 4937 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24 4938 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3 4939 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4940 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4941 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4942 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \ 4943 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4944 4945 #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0 4946 #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff 4947 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4948 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4949 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4950 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4951 4952 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29 4953 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7 4954 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 4955 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 4956 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 4957 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \ 4958 M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 4959 4960 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0 4961 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff 4962 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 4963 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 4964 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 4965 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \ 4966 M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 4967 4968 struct fw_params_cmd { 4969 __be32 op_to_vfn; 4970 __be32 retval_len16; 4971 struct fw_params_param { 4972 __be32 mnem; 4973 __be32 val; 4974 } param[7]; 4975 }; 4976 4977 #define S_FW_PARAMS_CMD_PFN 8 4978 #define M_FW_PARAMS_CMD_PFN 0x7 4979 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 4980 #define G_FW_PARAMS_CMD_PFN(x) \ 4981 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 4982 4983 #define S_FW_PARAMS_CMD_VFN 0 4984 #define M_FW_PARAMS_CMD_VFN 0xff 4985 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 4986 #define G_FW_PARAMS_CMD_VFN(x) \ 4987 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 4988 4989 struct fw_pfvf_cmd { 4990 __be32 op_to_vfn; 4991 __be32 retval_len16; 4992 __be32 niqflint_niq; 4993 __be32 type_to_neq; 4994 __be32 tc_to_nexactf; 4995 __be32 r_caps_to_nethctrl; 4996 __be16 nricq; 4997 __be16 nriqp; 4998 __be32 r4; 4999 }; 5000 5001 #define S_FW_PFVF_CMD_PFN 8 5002 #define M_FW_PFVF_CMD_PFN 0x7 5003 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 5004 #define G_FW_PFVF_CMD_PFN(x) \ 5005 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 5006 5007 #define S_FW_PFVF_CMD_VFN 0 5008 #define M_FW_PFVF_CMD_VFN 0xff 5009 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 5010 #define G_FW_PFVF_CMD_VFN(x) \ 5011 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 5012 5013 #define S_FW_PFVF_CMD_NIQFLINT 20 5014 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 5015 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 5016 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 5017 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 5018 5019 #define S_FW_PFVF_CMD_NIQ 0 5020 #define M_FW_PFVF_CMD_NIQ 0xfffff 5021 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 5022 #define G_FW_PFVF_CMD_NIQ(x) \ 5023 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 5024 5025 #define S_FW_PFVF_CMD_TYPE 31 5026 #define M_FW_PFVF_CMD_TYPE 0x1 5027 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 5028 #define G_FW_PFVF_CMD_TYPE(x) \ 5029 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 5030 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 5031 5032 #define S_FW_PFVF_CMD_CMASK 24 5033 #define M_FW_PFVF_CMD_CMASK 0xf 5034 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 5035 #define G_FW_PFVF_CMD_CMASK(x) \ 5036 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 5037 5038 #define S_FW_PFVF_CMD_PMASK 20 5039 #define M_FW_PFVF_CMD_PMASK 0xf 5040 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 5041 #define G_FW_PFVF_CMD_PMASK(x) \ 5042 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 5043 5044 #define S_FW_PFVF_CMD_NEQ 0 5045 #define M_FW_PFVF_CMD_NEQ 0xfffff 5046 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 5047 #define G_FW_PFVF_CMD_NEQ(x) \ 5048 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 5049 5050 #define S_FW_PFVF_CMD_TC 24 5051 #define M_FW_PFVF_CMD_TC 0xff 5052 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 5053 #define G_FW_PFVF_CMD_TC(x) \ 5054 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 5055 5056 #define S_FW_PFVF_CMD_NVI 16 5057 #define M_FW_PFVF_CMD_NVI 0xff 5058 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 5059 #define G_FW_PFVF_CMD_NVI(x) \ 5060 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 5061 5062 #define S_FW_PFVF_CMD_NEXACTF 0 5063 #define M_FW_PFVF_CMD_NEXACTF 0xffff 5064 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 5065 #define G_FW_PFVF_CMD_NEXACTF(x) \ 5066 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 5067 5068 #define S_FW_PFVF_CMD_R_CAPS 24 5069 #define M_FW_PFVF_CMD_R_CAPS 0xff 5070 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 5071 #define G_FW_PFVF_CMD_R_CAPS(x) \ 5072 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 5073 5074 #define S_FW_PFVF_CMD_WX_CAPS 16 5075 #define M_FW_PFVF_CMD_WX_CAPS 0xff 5076 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 5077 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 5078 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 5079 5080 #define S_FW_PFVF_CMD_NETHCTRL 0 5081 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 5082 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 5083 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 5084 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 5085 5086 /* 5087 * ingress queue type; the first 1K ingress queues can have associated 0, 5088 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 5089 * capabilities 5090 */ 5091 enum fw_iq_type { 5092 FW_IQ_TYPE_FL_INT_CAP, 5093 FW_IQ_TYPE_NO_FL_INT_CAP, 5094 FW_IQ_TYPE_VF_CQ 5095 }; 5096 5097 enum fw_iq_iqtype { 5098 FW_IQ_IQTYPE_OTHER, 5099 FW_IQ_IQTYPE_NIC, 5100 FW_IQ_IQTYPE_OFLD, 5101 }; 5102 5103 struct fw_iq_cmd { 5104 __be32 op_to_vfn; 5105 __be32 alloc_to_len16; 5106 __be16 physiqid; 5107 __be16 iqid; 5108 __be16 fl0id; 5109 __be16 fl1id; 5110 __be32 type_to_iqandstindex; 5111 __be16 iqdroprss_to_iqesize; 5112 __be16 iqsize; 5113 __be64 iqaddr; 5114 __be32 iqns_to_fl0congen; 5115 __be16 fl0dcaen_to_fl0cidxfthresh; 5116 __be16 fl0size; 5117 __be64 fl0addr; 5118 __be32 fl1cngchmap_to_fl1congen; 5119 __be16 fl1dcaen_to_fl1cidxfthresh; 5120 __be16 fl1size; 5121 __be64 fl1addr; 5122 }; 5123 5124 #define S_FW_IQ_CMD_PFN 8 5125 #define M_FW_IQ_CMD_PFN 0x7 5126 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 5127 #define G_FW_IQ_CMD_PFN(x) \ 5128 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 5129 5130 #define S_FW_IQ_CMD_VFN 0 5131 #define M_FW_IQ_CMD_VFN 0xff 5132 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 5133 #define G_FW_IQ_CMD_VFN(x) \ 5134 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 5135 5136 #define S_FW_IQ_CMD_ALLOC 31 5137 #define M_FW_IQ_CMD_ALLOC 0x1 5138 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 5139 #define G_FW_IQ_CMD_ALLOC(x) \ 5140 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 5141 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 5142 5143 #define S_FW_IQ_CMD_FREE 30 5144 #define M_FW_IQ_CMD_FREE 0x1 5145 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 5146 #define G_FW_IQ_CMD_FREE(x) \ 5147 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 5148 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 5149 5150 #define S_FW_IQ_CMD_MODIFY 29 5151 #define M_FW_IQ_CMD_MODIFY 0x1 5152 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 5153 #define G_FW_IQ_CMD_MODIFY(x) \ 5154 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 5155 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 5156 5157 #define S_FW_IQ_CMD_IQSTART 28 5158 #define M_FW_IQ_CMD_IQSTART 0x1 5159 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 5160 #define G_FW_IQ_CMD_IQSTART(x) \ 5161 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 5162 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 5163 5164 #define S_FW_IQ_CMD_IQSTOP 27 5165 #define M_FW_IQ_CMD_IQSTOP 0x1 5166 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 5167 #define G_FW_IQ_CMD_IQSTOP(x) \ 5168 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 5169 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 5170 5171 #define S_FW_IQ_CMD_TYPE 29 5172 #define M_FW_IQ_CMD_TYPE 0x7 5173 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 5174 #define G_FW_IQ_CMD_TYPE(x) \ 5175 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 5176 5177 #define S_FW_IQ_CMD_IQASYNCH 28 5178 #define M_FW_IQ_CMD_IQASYNCH 0x1 5179 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 5180 #define G_FW_IQ_CMD_IQASYNCH(x) \ 5181 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 5182 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 5183 5184 #define S_FW_IQ_CMD_VIID 16 5185 #define M_FW_IQ_CMD_VIID 0xfff 5186 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 5187 #define G_FW_IQ_CMD_VIID(x) \ 5188 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 5189 5190 #define S_FW_IQ_CMD_IQANDST 15 5191 #define M_FW_IQ_CMD_IQANDST 0x1 5192 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 5193 #define G_FW_IQ_CMD_IQANDST(x) \ 5194 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 5195 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 5196 5197 #define S_FW_IQ_CMD_IQANUS 14 5198 #define M_FW_IQ_CMD_IQANUS 0x1 5199 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 5200 #define G_FW_IQ_CMD_IQANUS(x) \ 5201 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 5202 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 5203 5204 #define S_FW_IQ_CMD_IQANUD 12 5205 #define M_FW_IQ_CMD_IQANUD 0x3 5206 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 5207 #define G_FW_IQ_CMD_IQANUD(x) \ 5208 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 5209 5210 #define S_FW_IQ_CMD_IQANDSTINDEX 0 5211 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 5212 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 5213 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 5214 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 5215 5216 #define S_FW_IQ_CMD_IQDROPRSS 15 5217 #define M_FW_IQ_CMD_IQDROPRSS 0x1 5218 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 5219 #define G_FW_IQ_CMD_IQDROPRSS(x) \ 5220 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 5221 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 5222 5223 #define S_FW_IQ_CMD_IQGTSMODE 14 5224 #define M_FW_IQ_CMD_IQGTSMODE 0x1 5225 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 5226 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 5227 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 5228 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 5229 5230 #define S_FW_IQ_CMD_IQPCIECH 12 5231 #define M_FW_IQ_CMD_IQPCIECH 0x3 5232 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 5233 #define G_FW_IQ_CMD_IQPCIECH(x) \ 5234 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 5235 5236 #define S_FW_IQ_CMD_IQDCAEN 11 5237 #define M_FW_IQ_CMD_IQDCAEN 0x1 5238 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 5239 #define G_FW_IQ_CMD_IQDCAEN(x) \ 5240 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 5241 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 5242 5243 #define S_FW_IQ_CMD_IQDCACPU 6 5244 #define M_FW_IQ_CMD_IQDCACPU 0x1f 5245 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 5246 #define G_FW_IQ_CMD_IQDCACPU(x) \ 5247 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 5248 5249 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 5250 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 5251 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 5252 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 5253 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 5254 5255 #define S_FW_IQ_CMD_IQO 3 5256 #define M_FW_IQ_CMD_IQO 0x1 5257 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 5258 #define G_FW_IQ_CMD_IQO(x) \ 5259 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 5260 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 5261 5262 #define S_FW_IQ_CMD_IQCPRIO 2 5263 #define M_FW_IQ_CMD_IQCPRIO 0x1 5264 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 5265 #define G_FW_IQ_CMD_IQCPRIO(x) \ 5266 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 5267 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 5268 5269 #define S_FW_IQ_CMD_IQESIZE 0 5270 #define M_FW_IQ_CMD_IQESIZE 0x3 5271 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 5272 #define G_FW_IQ_CMD_IQESIZE(x) \ 5273 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 5274 5275 #define S_FW_IQ_CMD_IQNS 31 5276 #define M_FW_IQ_CMD_IQNS 0x1 5277 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 5278 #define G_FW_IQ_CMD_IQNS(x) \ 5279 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 5280 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 5281 5282 #define S_FW_IQ_CMD_IQRO 30 5283 #define M_FW_IQ_CMD_IQRO 0x1 5284 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 5285 #define G_FW_IQ_CMD_IQRO(x) \ 5286 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 5287 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 5288 5289 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 5290 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 5291 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 5292 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 5293 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 5294 5295 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 5296 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 5297 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 5298 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 5299 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 5300 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 5301 5302 #define S_FW_IQ_CMD_IQFLINTISCSIC 26 5303 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 5304 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 5305 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 5306 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 5307 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 5308 5309 #define S_FW_IQ_CMD_IQTYPE 24 5310 #define M_FW_IQ_CMD_IQTYPE 0x3 5311 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE) 5312 #define G_FW_IQ_CMD_IQTYPE(x) \ 5313 (((x) >> S_FW_IQ_CMD_IQTYPE) & M_FW_IQ_CMD_IQTYPE) 5314 5315 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 5316 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 5317 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 5318 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 5319 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 5320 5321 #define S_FW_IQ_CMD_FL0CONGDROP 16 5322 #define M_FW_IQ_CMD_FL0CONGDROP 0x1 5323 #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) 5324 #define G_FW_IQ_CMD_FL0CONGDROP(x) \ 5325 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) 5326 #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) 5327 5328 #define S_FW_IQ_CMD_FL0CACHELOCK 15 5329 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 5330 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 5331 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 5332 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 5333 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 5334 5335 #define S_FW_IQ_CMD_FL0DBP 14 5336 #define M_FW_IQ_CMD_FL0DBP 0x1 5337 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 5338 #define G_FW_IQ_CMD_FL0DBP(x) \ 5339 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 5340 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 5341 5342 #define S_FW_IQ_CMD_FL0DATANS 13 5343 #define M_FW_IQ_CMD_FL0DATANS 0x1 5344 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 5345 #define G_FW_IQ_CMD_FL0DATANS(x) \ 5346 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 5347 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 5348 5349 #define S_FW_IQ_CMD_FL0DATARO 12 5350 #define M_FW_IQ_CMD_FL0DATARO 0x1 5351 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 5352 #define G_FW_IQ_CMD_FL0DATARO(x) \ 5353 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 5354 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 5355 5356 #define S_FW_IQ_CMD_FL0CONGCIF 11 5357 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 5358 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 5359 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 5360 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 5361 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 5362 5363 #define S_FW_IQ_CMD_FL0ONCHIP 10 5364 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 5365 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 5366 #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 5367 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 5368 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 5369 5370 #define S_FW_IQ_CMD_FL0STATUSPGNS 9 5371 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 5372 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 5373 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 5374 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 5375 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 5376 5377 #define S_FW_IQ_CMD_FL0STATUSPGRO 8 5378 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 5379 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 5380 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 5381 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 5382 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 5383 5384 #define S_FW_IQ_CMD_FL0FETCHNS 7 5385 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 5386 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 5387 #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 5388 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 5389 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 5390 5391 #define S_FW_IQ_CMD_FL0FETCHRO 6 5392 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 5393 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 5394 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 5395 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 5396 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 5397 5398 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 5399 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 5400 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 5401 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 5402 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 5403 5404 #define S_FW_IQ_CMD_FL0CPRIO 3 5405 #define M_FW_IQ_CMD_FL0CPRIO 0x1 5406 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 5407 #define G_FW_IQ_CMD_FL0CPRIO(x) \ 5408 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 5409 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 5410 5411 #define S_FW_IQ_CMD_FL0PADEN 2 5412 #define M_FW_IQ_CMD_FL0PADEN 0x1 5413 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 5414 #define G_FW_IQ_CMD_FL0PADEN(x) \ 5415 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 5416 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 5417 5418 #define S_FW_IQ_CMD_FL0PACKEN 1 5419 #define M_FW_IQ_CMD_FL0PACKEN 0x1 5420 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 5421 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 5422 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 5423 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 5424 5425 #define S_FW_IQ_CMD_FL0CONGEN 0 5426 #define M_FW_IQ_CMD_FL0CONGEN 0x1 5427 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 5428 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 5429 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 5430 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 5431 5432 #define S_FW_IQ_CMD_FL0DCAEN 15 5433 #define M_FW_IQ_CMD_FL0DCAEN 0x1 5434 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 5435 #define G_FW_IQ_CMD_FL0DCAEN(x) \ 5436 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 5437 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 5438 5439 #define S_FW_IQ_CMD_FL0DCACPU 10 5440 #define M_FW_IQ_CMD_FL0DCACPU 0x1f 5441 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 5442 #define G_FW_IQ_CMD_FL0DCACPU(x) \ 5443 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 5444 5445 #define S_FW_IQ_CMD_FL0FBMIN 7 5446 #define M_FW_IQ_CMD_FL0FBMIN 0x7 5447 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 5448 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 5449 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 5450 5451 #define S_FW_IQ_CMD_FL0FBMAX 4 5452 #define M_FW_IQ_CMD_FL0FBMAX 0x7 5453 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 5454 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 5455 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 5456 5457 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 5458 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 5459 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 5460 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 5461 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 5462 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 5463 5464 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 5465 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 5466 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 5467 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 5468 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 5469 5470 #define S_FW_IQ_CMD_FL1CNGCHMAP 20 5471 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 5472 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 5473 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 5474 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 5475 5476 #define S_FW_IQ_CMD_FL1CONGDROP 16 5477 #define M_FW_IQ_CMD_FL1CONGDROP 0x1 5478 #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) 5479 #define G_FW_IQ_CMD_FL1CONGDROP(x) \ 5480 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) 5481 #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) 5482 5483 #define S_FW_IQ_CMD_FL1CACHELOCK 15 5484 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 5485 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 5486 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 5487 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 5488 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 5489 5490 #define S_FW_IQ_CMD_FL1DBP 14 5491 #define M_FW_IQ_CMD_FL1DBP 0x1 5492 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 5493 #define G_FW_IQ_CMD_FL1DBP(x) \ 5494 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 5495 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 5496 5497 #define S_FW_IQ_CMD_FL1DATANS 13 5498 #define M_FW_IQ_CMD_FL1DATANS 0x1 5499 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 5500 #define G_FW_IQ_CMD_FL1DATANS(x) \ 5501 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 5502 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 5503 5504 #define S_FW_IQ_CMD_FL1DATARO 12 5505 #define M_FW_IQ_CMD_FL1DATARO 0x1 5506 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 5507 #define G_FW_IQ_CMD_FL1DATARO(x) \ 5508 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 5509 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 5510 5511 #define S_FW_IQ_CMD_FL1CONGCIF 11 5512 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 5513 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 5514 #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 5515 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 5516 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 5517 5518 #define S_FW_IQ_CMD_FL1ONCHIP 10 5519 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 5520 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 5521 #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 5522 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 5523 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 5524 5525 #define S_FW_IQ_CMD_FL1STATUSPGNS 9 5526 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 5527 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 5528 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 5529 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 5530 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 5531 5532 #define S_FW_IQ_CMD_FL1STATUSPGRO 8 5533 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 5534 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 5535 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 5536 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 5537 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 5538 5539 #define S_FW_IQ_CMD_FL1FETCHNS 7 5540 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 5541 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 5542 #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 5543 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 5544 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 5545 5546 #define S_FW_IQ_CMD_FL1FETCHRO 6 5547 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 5548 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 5549 #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 5550 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 5551 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 5552 5553 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 5554 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 5555 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 5556 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 5557 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 5558 5559 #define S_FW_IQ_CMD_FL1CPRIO 3 5560 #define M_FW_IQ_CMD_FL1CPRIO 0x1 5561 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 5562 #define G_FW_IQ_CMD_FL1CPRIO(x) \ 5563 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 5564 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 5565 5566 #define S_FW_IQ_CMD_FL1PADEN 2 5567 #define M_FW_IQ_CMD_FL1PADEN 0x1 5568 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 5569 #define G_FW_IQ_CMD_FL1PADEN(x) \ 5570 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 5571 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 5572 5573 #define S_FW_IQ_CMD_FL1PACKEN 1 5574 #define M_FW_IQ_CMD_FL1PACKEN 0x1 5575 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 5576 #define G_FW_IQ_CMD_FL1PACKEN(x) \ 5577 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 5578 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 5579 5580 #define S_FW_IQ_CMD_FL1CONGEN 0 5581 #define M_FW_IQ_CMD_FL1CONGEN 0x1 5582 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 5583 #define G_FW_IQ_CMD_FL1CONGEN(x) \ 5584 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 5585 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 5586 5587 #define S_FW_IQ_CMD_FL1DCAEN 15 5588 #define M_FW_IQ_CMD_FL1DCAEN 0x1 5589 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 5590 #define G_FW_IQ_CMD_FL1DCAEN(x) \ 5591 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 5592 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 5593 5594 #define S_FW_IQ_CMD_FL1DCACPU 10 5595 #define M_FW_IQ_CMD_FL1DCACPU 0x1f 5596 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 5597 #define G_FW_IQ_CMD_FL1DCACPU(x) \ 5598 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 5599 5600 #define S_FW_IQ_CMD_FL1FBMIN 7 5601 #define M_FW_IQ_CMD_FL1FBMIN 0x7 5602 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 5603 #define G_FW_IQ_CMD_FL1FBMIN(x) \ 5604 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 5605 5606 #define S_FW_IQ_CMD_FL1FBMAX 4 5607 #define M_FW_IQ_CMD_FL1FBMAX 0x7 5608 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 5609 #define G_FW_IQ_CMD_FL1FBMAX(x) \ 5610 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 5611 5612 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 5613 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 5614 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 5615 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 5616 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 5617 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 5618 5619 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 5620 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 5621 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 5622 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 5623 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 5624 5625 struct fw_eq_mngt_cmd { 5626 __be32 op_to_vfn; 5627 __be32 alloc_to_len16; 5628 __be32 cmpliqid_eqid; 5629 __be32 physeqid_pkd; 5630 __be32 fetchszm_to_iqid; 5631 __be32 dcaen_to_eqsize; 5632 __be64 eqaddr; 5633 }; 5634 5635 #define S_FW_EQ_MNGT_CMD_PFN 8 5636 #define M_FW_EQ_MNGT_CMD_PFN 0x7 5637 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 5638 #define G_FW_EQ_MNGT_CMD_PFN(x) \ 5639 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 5640 5641 #define S_FW_EQ_MNGT_CMD_VFN 0 5642 #define M_FW_EQ_MNGT_CMD_VFN 0xff 5643 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 5644 #define G_FW_EQ_MNGT_CMD_VFN(x) \ 5645 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 5646 5647 #define S_FW_EQ_MNGT_CMD_ALLOC 31 5648 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 5649 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 5650 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 5651 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 5652 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 5653 5654 #define S_FW_EQ_MNGT_CMD_FREE 30 5655 #define M_FW_EQ_MNGT_CMD_FREE 0x1 5656 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 5657 #define G_FW_EQ_MNGT_CMD_FREE(x) \ 5658 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 5659 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 5660 5661 #define S_FW_EQ_MNGT_CMD_MODIFY 29 5662 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 5663 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 5664 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 5665 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 5666 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 5667 5668 #define S_FW_EQ_MNGT_CMD_EQSTART 28 5669 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 5670 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 5671 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 5672 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 5673 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 5674 5675 #define S_FW_EQ_MNGT_CMD_EQSTOP 27 5676 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 5677 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 5678 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 5679 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 5680 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 5681 5682 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 5683 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 5684 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 5685 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 5686 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 5687 5688 #define S_FW_EQ_MNGT_CMD_EQID 0 5689 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 5690 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 5691 #define G_FW_EQ_MNGT_CMD_EQID(x) \ 5692 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 5693 5694 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 5695 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 5696 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 5697 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 5698 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 5699 5700 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 5701 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 5702 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 5703 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 5704 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 5705 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 5706 5707 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 5708 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 5709 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 5710 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 5711 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 5712 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 5713 5714 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 5715 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 5716 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 5717 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 5718 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 5719 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 5720 5721 #define S_FW_EQ_MNGT_CMD_FETCHNS 23 5722 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 5723 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 5724 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 5725 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 5726 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 5727 5728 #define S_FW_EQ_MNGT_CMD_FETCHRO 22 5729 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 5730 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 5731 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 5732 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 5733 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 5734 5735 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 5736 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 5737 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 5738 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 5739 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 5740 5741 #define S_FW_EQ_MNGT_CMD_CPRIO 19 5742 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 5743 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 5744 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 5745 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 5746 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 5747 5748 #define S_FW_EQ_MNGT_CMD_ONCHIP 18 5749 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 5750 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 5751 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 5752 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 5753 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 5754 5755 #define S_FW_EQ_MNGT_CMD_PCIECHN 16 5756 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 5757 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 5758 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 5759 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 5760 5761 #define S_FW_EQ_MNGT_CMD_IQID 0 5762 #define M_FW_EQ_MNGT_CMD_IQID 0xffff 5763 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 5764 #define G_FW_EQ_MNGT_CMD_IQID(x) \ 5765 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 5766 5767 #define S_FW_EQ_MNGT_CMD_DCAEN 31 5768 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 5769 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 5770 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 5771 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 5772 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 5773 5774 #define S_FW_EQ_MNGT_CMD_DCACPU 26 5775 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 5776 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 5777 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 5778 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 5779 5780 #define S_FW_EQ_MNGT_CMD_FBMIN 23 5781 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 5782 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 5783 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 5784 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 5785 5786 #define S_FW_EQ_MNGT_CMD_FBMAX 20 5787 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 5788 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 5789 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 5790 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 5791 5792 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 5793 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 5794 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5795 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5796 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5797 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5798 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 5799 5800 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 5801 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 5802 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5803 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 5804 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5805 5806 #define S_FW_EQ_MNGT_CMD_EQSIZE 0 5807 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 5808 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 5809 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 5810 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 5811 5812 struct fw_eq_eth_cmd { 5813 __be32 op_to_vfn; 5814 __be32 alloc_to_len16; 5815 __be32 eqid_pkd; 5816 __be32 physeqid_pkd; 5817 __be32 fetchszm_to_iqid; 5818 __be32 dcaen_to_eqsize; 5819 __be64 eqaddr; 5820 __be32 autoequiqe_to_viid; 5821 __be32 r8_lo; 5822 __be64 r9; 5823 }; 5824 5825 #define S_FW_EQ_ETH_CMD_PFN 8 5826 #define M_FW_EQ_ETH_CMD_PFN 0x7 5827 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 5828 #define G_FW_EQ_ETH_CMD_PFN(x) \ 5829 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 5830 5831 #define S_FW_EQ_ETH_CMD_VFN 0 5832 #define M_FW_EQ_ETH_CMD_VFN 0xff 5833 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 5834 #define G_FW_EQ_ETH_CMD_VFN(x) \ 5835 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 5836 5837 #define S_FW_EQ_ETH_CMD_ALLOC 31 5838 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 5839 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 5840 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 5841 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 5842 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 5843 5844 #define S_FW_EQ_ETH_CMD_FREE 30 5845 #define M_FW_EQ_ETH_CMD_FREE 0x1 5846 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 5847 #define G_FW_EQ_ETH_CMD_FREE(x) \ 5848 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 5849 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 5850 5851 #define S_FW_EQ_ETH_CMD_MODIFY 29 5852 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 5853 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 5854 #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 5855 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 5856 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 5857 5858 #define S_FW_EQ_ETH_CMD_EQSTART 28 5859 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 5860 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 5861 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 5862 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 5863 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 5864 5865 #define S_FW_EQ_ETH_CMD_EQSTOP 27 5866 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 5867 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 5868 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 5869 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 5870 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 5871 5872 #define S_FW_EQ_ETH_CMD_EQID 0 5873 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 5874 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 5875 #define G_FW_EQ_ETH_CMD_EQID(x) \ 5876 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 5877 5878 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 5879 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 5880 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 5881 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 5882 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 5883 5884 #define S_FW_EQ_ETH_CMD_FETCHSZM 26 5885 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 5886 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 5887 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 5888 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 5889 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 5890 5891 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 5892 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 5893 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 5894 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 5895 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 5896 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 5897 5898 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 5899 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 5900 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 5901 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 5902 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 5903 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 5904 5905 #define S_FW_EQ_ETH_CMD_FETCHNS 23 5906 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 5907 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 5908 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 5909 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 5910 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 5911 5912 #define S_FW_EQ_ETH_CMD_FETCHRO 22 5913 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 5914 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 5915 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 5916 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 5917 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 5918 5919 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 5920 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 5921 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 5922 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 5923 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 5924 5925 #define S_FW_EQ_ETH_CMD_CPRIO 19 5926 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 5927 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 5928 #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 5929 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 5930 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 5931 5932 #define S_FW_EQ_ETH_CMD_ONCHIP 18 5933 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 5934 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 5935 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 5936 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 5937 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 5938 5939 #define S_FW_EQ_ETH_CMD_PCIECHN 16 5940 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 5941 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 5942 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 5943 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 5944 5945 #define S_FW_EQ_ETH_CMD_IQID 0 5946 #define M_FW_EQ_ETH_CMD_IQID 0xffff 5947 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 5948 #define G_FW_EQ_ETH_CMD_IQID(x) \ 5949 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 5950 5951 #define S_FW_EQ_ETH_CMD_DCAEN 31 5952 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 5953 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 5954 #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 5955 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 5956 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 5957 5958 #define S_FW_EQ_ETH_CMD_DCACPU 26 5959 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 5960 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 5961 #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 5962 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 5963 5964 #define S_FW_EQ_ETH_CMD_FBMIN 23 5965 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 5966 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 5967 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 5968 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 5969 5970 #define S_FW_EQ_ETH_CMD_FBMAX 20 5971 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 5972 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 5973 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 5974 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 5975 5976 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 5977 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 5978 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 5979 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 5980 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 5981 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 5982 5983 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 5984 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 5985 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 5986 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 5987 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 5988 5989 #define S_FW_EQ_ETH_CMD_EQSIZE 0 5990 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 5991 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 5992 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 5993 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 5994 5995 #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 5996 #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 5997 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 5998 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 5999 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 6000 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 6001 6002 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 6003 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 6004 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 6005 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 6006 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 6007 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 6008 6009 #define S_FW_EQ_ETH_CMD_VIID 16 6010 #define M_FW_EQ_ETH_CMD_VIID 0xfff 6011 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 6012 #define G_FW_EQ_ETH_CMD_VIID(x) \ 6013 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 6014 6015 struct fw_eq_ctrl_cmd { 6016 __be32 op_to_vfn; 6017 __be32 alloc_to_len16; 6018 __be32 cmpliqid_eqid; 6019 __be32 physeqid_pkd; 6020 __be32 fetchszm_to_iqid; 6021 __be32 dcaen_to_eqsize; 6022 __be64 eqaddr; 6023 }; 6024 6025 #define S_FW_EQ_CTRL_CMD_PFN 8 6026 #define M_FW_EQ_CTRL_CMD_PFN 0x7 6027 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 6028 #define G_FW_EQ_CTRL_CMD_PFN(x) \ 6029 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 6030 6031 #define S_FW_EQ_CTRL_CMD_VFN 0 6032 #define M_FW_EQ_CTRL_CMD_VFN 0xff 6033 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 6034 #define G_FW_EQ_CTRL_CMD_VFN(x) \ 6035 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 6036 6037 #define S_FW_EQ_CTRL_CMD_ALLOC 31 6038 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 6039 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 6040 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 6041 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 6042 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 6043 6044 #define S_FW_EQ_CTRL_CMD_FREE 30 6045 #define M_FW_EQ_CTRL_CMD_FREE 0x1 6046 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 6047 #define G_FW_EQ_CTRL_CMD_FREE(x) \ 6048 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 6049 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 6050 6051 #define S_FW_EQ_CTRL_CMD_MODIFY 29 6052 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 6053 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 6054 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 6055 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 6056 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 6057 6058 #define S_FW_EQ_CTRL_CMD_EQSTART 28 6059 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 6060 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 6061 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 6062 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 6063 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 6064 6065 #define S_FW_EQ_CTRL_CMD_EQSTOP 27 6066 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 6067 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 6068 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 6069 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 6070 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 6071 6072 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 6073 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 6074 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 6075 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 6076 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 6077 6078 #define S_FW_EQ_CTRL_CMD_EQID 0 6079 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 6080 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 6081 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 6082 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 6083 6084 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 6085 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 6086 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 6087 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 6088 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 6089 6090 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 6091 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 6092 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 6093 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 6094 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 6095 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 6096 6097 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 6098 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 6099 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 6100 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 6101 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 6102 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 6103 6104 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 6105 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 6106 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 6107 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 6108 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 6109 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 6110 6111 #define S_FW_EQ_CTRL_CMD_FETCHNS 23 6112 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 6113 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 6114 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 6115 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 6116 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 6117 6118 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 6119 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 6120 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 6121 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 6122 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 6123 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 6124 6125 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 6126 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 6127 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 6128 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 6129 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 6130 6131 #define S_FW_EQ_CTRL_CMD_CPRIO 19 6132 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 6133 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 6134 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 6135 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 6136 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 6137 6138 #define S_FW_EQ_CTRL_CMD_ONCHIP 18 6139 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 6140 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 6141 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 6142 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 6143 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 6144 6145 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 6146 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 6147 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 6148 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 6149 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 6150 6151 #define S_FW_EQ_CTRL_CMD_IQID 0 6152 #define M_FW_EQ_CTRL_CMD_IQID 0xffff 6153 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 6154 #define G_FW_EQ_CTRL_CMD_IQID(x) \ 6155 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 6156 6157 #define S_FW_EQ_CTRL_CMD_DCAEN 31 6158 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 6159 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 6160 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 6161 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 6162 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 6163 6164 #define S_FW_EQ_CTRL_CMD_DCACPU 26 6165 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 6166 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 6167 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 6168 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 6169 6170 #define S_FW_EQ_CTRL_CMD_FBMIN 23 6171 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 6172 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 6173 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 6174 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 6175 6176 #define S_FW_EQ_CTRL_CMD_FBMAX 20 6177 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 6178 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 6179 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 6180 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 6181 6182 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 6183 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 6184 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6185 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6186 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6187 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6188 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 6189 6190 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 6191 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 6192 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6193 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 6194 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6195 6196 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 6197 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 6198 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 6199 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 6200 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 6201 6202 struct fw_eq_ofld_cmd { 6203 __be32 op_to_vfn; 6204 __be32 alloc_to_len16; 6205 __be32 eqid_pkd; 6206 __be32 physeqid_pkd; 6207 __be32 fetchszm_to_iqid; 6208 __be32 dcaen_to_eqsize; 6209 __be64 eqaddr; 6210 }; 6211 6212 #define S_FW_EQ_OFLD_CMD_PFN 8 6213 #define M_FW_EQ_OFLD_CMD_PFN 0x7 6214 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 6215 #define G_FW_EQ_OFLD_CMD_PFN(x) \ 6216 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 6217 6218 #define S_FW_EQ_OFLD_CMD_VFN 0 6219 #define M_FW_EQ_OFLD_CMD_VFN 0xff 6220 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 6221 #define G_FW_EQ_OFLD_CMD_VFN(x) \ 6222 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 6223 6224 #define S_FW_EQ_OFLD_CMD_ALLOC 31 6225 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 6226 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 6227 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 6228 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 6229 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 6230 6231 #define S_FW_EQ_OFLD_CMD_FREE 30 6232 #define M_FW_EQ_OFLD_CMD_FREE 0x1 6233 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 6234 #define G_FW_EQ_OFLD_CMD_FREE(x) \ 6235 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 6236 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 6237 6238 #define S_FW_EQ_OFLD_CMD_MODIFY 29 6239 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 6240 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 6241 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 6242 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 6243 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 6244 6245 #define S_FW_EQ_OFLD_CMD_EQSTART 28 6246 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 6247 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 6248 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 6249 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 6250 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 6251 6252 #define S_FW_EQ_OFLD_CMD_EQSTOP 27 6253 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 6254 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 6255 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 6256 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 6257 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 6258 6259 #define S_FW_EQ_OFLD_CMD_EQID 0 6260 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 6261 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 6262 #define G_FW_EQ_OFLD_CMD_EQID(x) \ 6263 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 6264 6265 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 6266 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 6267 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 6268 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 6269 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 6270 6271 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 6272 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 6273 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 6274 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 6275 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 6276 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 6277 6278 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 6279 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 6280 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 6281 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 6282 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 6283 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 6284 6285 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 6286 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 6287 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 6288 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 6289 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 6290 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 6291 6292 #define S_FW_EQ_OFLD_CMD_FETCHNS 23 6293 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 6294 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 6295 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 6296 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 6297 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 6298 6299 #define S_FW_EQ_OFLD_CMD_FETCHRO 22 6300 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 6301 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 6302 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 6303 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 6304 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 6305 6306 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 6307 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 6308 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 6309 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 6310 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 6311 6312 #define S_FW_EQ_OFLD_CMD_CPRIO 19 6313 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 6314 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 6315 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 6316 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 6317 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 6318 6319 #define S_FW_EQ_OFLD_CMD_ONCHIP 18 6320 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 6321 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 6322 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 6323 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 6324 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 6325 6326 #define S_FW_EQ_OFLD_CMD_PCIECHN 16 6327 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 6328 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 6329 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 6330 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 6331 6332 #define S_FW_EQ_OFLD_CMD_IQID 0 6333 #define M_FW_EQ_OFLD_CMD_IQID 0xffff 6334 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 6335 #define G_FW_EQ_OFLD_CMD_IQID(x) \ 6336 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 6337 6338 #define S_FW_EQ_OFLD_CMD_DCAEN 31 6339 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 6340 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 6341 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 6342 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 6343 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 6344 6345 #define S_FW_EQ_OFLD_CMD_DCACPU 26 6346 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 6347 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 6348 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 6349 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 6350 6351 #define S_FW_EQ_OFLD_CMD_FBMIN 23 6352 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 6353 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 6354 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 6355 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 6356 6357 #define S_FW_EQ_OFLD_CMD_FBMAX 20 6358 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 6359 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 6360 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 6361 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 6362 6363 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 6364 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 6365 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6366 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6367 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6368 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6369 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 6370 6371 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 6372 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 6373 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6374 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 6375 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6376 6377 #define S_FW_EQ_OFLD_CMD_EQSIZE 0 6378 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 6379 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 6380 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 6381 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 6382 6383 /* Macros for VIID parsing: 6384 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 6385 #define S_FW_VIID_PFN 8 6386 #define M_FW_VIID_PFN 0x7 6387 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 6388 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 6389 6390 #define S_FW_VIID_VIVLD 7 6391 #define M_FW_VIID_VIVLD 0x1 6392 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 6393 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 6394 6395 #define S_FW_VIID_VIN 0 6396 #define M_FW_VIID_VIN 0x7F 6397 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 6398 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 6399 6400 /* Macros for VIID parsing: 6401 VIID - [11:9] PFN, [8] VI Valid, [7:0] VI number */ 6402 #define S_FW_256VIID_PFN 9 6403 #define M_FW_256VIID_PFN 0x7 6404 #define V_FW_256VIID_PFN(x) ((x) << S_FW_256VIID_PFN) 6405 #define G_FW_256VIID_PFN(x) (((x) >> S_FW_256VIID_PFN) & M_FW_256VIID_PFN) 6406 6407 #define S_FW_256VIID_VIVLD 8 6408 #define M_FW_256VIID_VIVLD 0x1 6409 #define V_FW_256VIID_VIVLD(x) ((x) << S_FW_256VIID_VIVLD) 6410 #define G_FW_256VIID_VIVLD(x) (((x) >> S_FW_256VIID_VIVLD) & M_FW_256VIID_VIVLD) 6411 6412 #define S_FW_256VIID_VIN 0 6413 #define M_FW_256VIID_VIN 0xFF 6414 #define V_FW_256VIID_VIN(x) ((x) << S_FW_256VIID_VIN) 6415 #define G_FW_256VIID_VIN(x) (((x) >> S_FW_256VIID_VIN) & M_FW_256VIID_VIN) 6416 6417 enum fw_vi_func { 6418 FW_VI_FUNC_ETH, 6419 FW_VI_FUNC_OFLD, 6420 FW_VI_FUNC_IWARP, 6421 FW_VI_FUNC_OPENISCSI, 6422 FW_VI_FUNC_OPENFCOE, 6423 FW_VI_FUNC_FOISCSI, 6424 FW_VI_FUNC_FOFCOE, 6425 FW_VI_FUNC_FW, 6426 }; 6427 6428 struct fw_vi_cmd { 6429 __be32 op_to_vfn; 6430 __be32 alloc_to_len16; 6431 __be16 type_to_viid; 6432 __u8 mac[6]; 6433 __u8 portid_pkd; 6434 __u8 nmac; 6435 __u8 nmac0[6]; 6436 __be16 norss_rsssize; 6437 __u8 nmac1[6]; 6438 __be16 idsiiq_pkd; 6439 __u8 nmac2[6]; 6440 __be16 idseiq_pkd; 6441 __u8 nmac3[6]; 6442 __be64 r9; 6443 __be64 r10; 6444 }; 6445 6446 #define S_FW_VI_CMD_PFN 8 6447 #define M_FW_VI_CMD_PFN 0x7 6448 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 6449 #define G_FW_VI_CMD_PFN(x) \ 6450 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 6451 6452 #define S_FW_VI_CMD_VFN 0 6453 #define M_FW_VI_CMD_VFN 0xff 6454 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 6455 #define G_FW_VI_CMD_VFN(x) \ 6456 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 6457 6458 #define S_FW_VI_CMD_ALLOC 31 6459 #define M_FW_VI_CMD_ALLOC 0x1 6460 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 6461 #define G_FW_VI_CMD_ALLOC(x) \ 6462 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 6463 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 6464 6465 #define S_FW_VI_CMD_FREE 30 6466 #define M_FW_VI_CMD_FREE 0x1 6467 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 6468 #define G_FW_VI_CMD_FREE(x) \ 6469 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 6470 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 6471 6472 #define S_FW_VI_CMD_TYPE 15 6473 #define M_FW_VI_CMD_TYPE 0x1 6474 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 6475 #define G_FW_VI_CMD_TYPE(x) \ 6476 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 6477 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 6478 6479 #define S_FW_VI_CMD_FUNC 12 6480 #define M_FW_VI_CMD_FUNC 0x7 6481 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 6482 #define G_FW_VI_CMD_FUNC(x) \ 6483 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 6484 6485 #define S_FW_VI_CMD_VIID 0 6486 #define M_FW_VI_CMD_VIID 0xfff 6487 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 6488 #define G_FW_VI_CMD_VIID(x) \ 6489 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 6490 6491 #define S_FW_VI_CMD_PORTID 4 6492 #define M_FW_VI_CMD_PORTID 0xf 6493 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 6494 #define G_FW_VI_CMD_PORTID(x) \ 6495 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 6496 6497 #define S_FW_VI_CMD_NORSS 11 6498 #define M_FW_VI_CMD_NORSS 0x1 6499 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 6500 #define G_FW_VI_CMD_NORSS(x) \ 6501 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 6502 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 6503 6504 #define S_FW_VI_CMD_RSSSIZE 0 6505 #define M_FW_VI_CMD_RSSSIZE 0x7ff 6506 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 6507 #define G_FW_VI_CMD_RSSSIZE(x) \ 6508 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 6509 6510 #define S_FW_VI_CMD_IDSIIQ 0 6511 #define M_FW_VI_CMD_IDSIIQ 0x3ff 6512 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 6513 #define G_FW_VI_CMD_IDSIIQ(x) \ 6514 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 6515 6516 #define S_FW_VI_CMD_IDSEIQ 0 6517 #define M_FW_VI_CMD_IDSEIQ 0x3ff 6518 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 6519 #define G_FW_VI_CMD_IDSEIQ(x) \ 6520 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 6521 6522 /* Special VI_MAC command index ids */ 6523 #define FW_VI_MAC_ADD_MAC 0x3FF 6524 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 6525 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 6526 #define FW_VI_MAC_ID_BASED_FREE 0x3FC 6527 6528 enum fw_vi_mac_smac { 6529 FW_VI_MAC_MPS_TCAM_ENTRY, 6530 FW_VI_MAC_MPS_TCAM_ONLY, 6531 FW_VI_MAC_SMT_ONLY, 6532 FW_VI_MAC_SMT_AND_MPSTCAM 6533 }; 6534 6535 enum fw_vi_mac_result { 6536 FW_VI_MAC_R_SUCCESS, 6537 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 6538 FW_VI_MAC_R_SMAC_FAIL, 6539 FW_VI_MAC_R_F_ACL_CHECK 6540 }; 6541 6542 enum fw_vi_mac_entry_types { 6543 FW_VI_MAC_TYPE_EXACTMAC, 6544 FW_VI_MAC_TYPE_HASHVEC, 6545 FW_VI_MAC_TYPE_RAW, 6546 FW_VI_MAC_TYPE_EXACTMAC_VNI, 6547 }; 6548 6549 struct fw_vi_mac_cmd { 6550 __be32 op_to_viid; 6551 __be32 freemacs_to_len16; 6552 union fw_vi_mac { 6553 struct fw_vi_mac_exact { 6554 __be16 valid_to_idx; 6555 __u8 macaddr[6]; 6556 } exact[7]; 6557 struct fw_vi_mac_hash { 6558 __be64 hashvec; 6559 } hash; 6560 struct fw_vi_mac_raw { 6561 __be32 raw_idx_pkd; 6562 __be32 data0_pkd; 6563 __be32 data1[2]; 6564 __be64 data0m_pkd; 6565 __be32 data1m[2]; 6566 } raw; 6567 struct fw_vi_mac_vni { 6568 __be16 valid_to_idx; 6569 __u8 macaddr[6]; 6570 __be16 r7; 6571 __u8 macaddr_mask[6]; 6572 __be32 lookup_type_to_vni; 6573 __be32 vni_mask_pkd; 6574 } exact_vni[2]; 6575 } u; 6576 }; 6577 6578 #define S_FW_VI_MAC_CMD_VIID 0 6579 #define M_FW_VI_MAC_CMD_VIID 0xfff 6580 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 6581 #define G_FW_VI_MAC_CMD_VIID(x) \ 6582 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 6583 6584 #define S_FW_VI_MAC_CMD_FREEMACS 31 6585 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 6586 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 6587 #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 6588 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 6589 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 6590 6591 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 6592 #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7 6593 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 6594 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \ 6595 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE) 6596 6597 #define S_FW_VI_MAC_CMD_HASHUNIEN 22 6598 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 6599 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 6600 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 6601 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 6602 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 6603 6604 #define S_FW_VI_MAC_CMD_VALID 15 6605 #define M_FW_VI_MAC_CMD_VALID 0x1 6606 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 6607 #define G_FW_VI_MAC_CMD_VALID(x) \ 6608 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 6609 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 6610 6611 #define S_FW_VI_MAC_CMD_PRIO 12 6612 #define M_FW_VI_MAC_CMD_PRIO 0x7 6613 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 6614 #define G_FW_VI_MAC_CMD_PRIO(x) \ 6615 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 6616 6617 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 6618 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 6619 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 6620 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 6621 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 6622 6623 #define S_FW_VI_MAC_CMD_IDX 0 6624 #define M_FW_VI_MAC_CMD_IDX 0x3ff 6625 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 6626 #define G_FW_VI_MAC_CMD_IDX(x) \ 6627 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 6628 6629 #define S_FW_VI_MAC_CMD_RAW_IDX 16 6630 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 6631 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 6632 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 6633 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 6634 6635 #define S_FW_VI_MAC_CMD_DATA0 0 6636 #define M_FW_VI_MAC_CMD_DATA0 0xffff 6637 #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0) 6638 #define G_FW_VI_MAC_CMD_DATA0(x) \ 6639 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0) 6640 6641 #define S_FW_VI_MAC_CMD_LOOKUP_TYPE 31 6642 #define M_FW_VI_MAC_CMD_LOOKUP_TYPE 0x1 6643 #define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x) ((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE) 6644 #define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x) \ 6645 (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE) 6646 #define F_FW_VI_MAC_CMD_LOOKUP_TYPE V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U) 6647 6648 #define S_FW_VI_MAC_CMD_DIP_HIT 30 6649 #define M_FW_VI_MAC_CMD_DIP_HIT 0x1 6650 #define V_FW_VI_MAC_CMD_DIP_HIT(x) ((x) << S_FW_VI_MAC_CMD_DIP_HIT) 6651 #define G_FW_VI_MAC_CMD_DIP_HIT(x) \ 6652 (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT) 6653 #define F_FW_VI_MAC_CMD_DIP_HIT V_FW_VI_MAC_CMD_DIP_HIT(1U) 6654 6655 #define S_FW_VI_MAC_CMD_VNI 0 6656 #define M_FW_VI_MAC_CMD_VNI 0xffffff 6657 #define V_FW_VI_MAC_CMD_VNI(x) ((x) << S_FW_VI_MAC_CMD_VNI) 6658 #define G_FW_VI_MAC_CMD_VNI(x) \ 6659 (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI) 6660 6661 #define S_FW_VI_MAC_CMD_VNI_MASK 0 6662 #define M_FW_VI_MAC_CMD_VNI_MASK 0xffffff 6663 #define V_FW_VI_MAC_CMD_VNI_MASK(x) ((x) << S_FW_VI_MAC_CMD_VNI_MASK) 6664 #define G_FW_VI_MAC_CMD_VNI_MASK(x) \ 6665 (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK) 6666 6667 /* T4 max MTU supported */ 6668 #define T4_MAX_MTU_SUPPORTED 9600 6669 #define FW_RXMODE_MTU_NO_CHG 65535 6670 6671 struct fw_vi_rxmode_cmd { 6672 __be32 op_to_viid; 6673 __be32 retval_len16; 6674 __be32 mtu_to_vlanexen; 6675 __be32 r4_lo; 6676 }; 6677 6678 #define S_FW_VI_RXMODE_CMD_VIID 0 6679 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 6680 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 6681 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 6682 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 6683 6684 #define S_FW_VI_RXMODE_CMD_MTU 16 6685 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 6686 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 6687 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 6688 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 6689 6690 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 6691 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 6692 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 6693 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 6694 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 6695 6696 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 6697 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 6698 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6699 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 6700 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6701 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 6702 6703 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 6704 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 6705 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6706 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 6707 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6708 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 6709 6710 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 6711 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 6712 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 6713 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 6714 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 6715 6716 struct fw_vi_enable_cmd { 6717 __be32 op_to_viid; 6718 __be32 ien_to_len16; 6719 __be16 blinkdur; 6720 __be16 r3; 6721 __be32 r4; 6722 }; 6723 6724 #define S_FW_VI_ENABLE_CMD_VIID 0 6725 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 6726 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 6727 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 6728 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 6729 6730 #define S_FW_VI_ENABLE_CMD_IEN 31 6731 #define M_FW_VI_ENABLE_CMD_IEN 0x1 6732 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 6733 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 6734 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 6735 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 6736 6737 #define S_FW_VI_ENABLE_CMD_EEN 30 6738 #define M_FW_VI_ENABLE_CMD_EEN 0x1 6739 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 6740 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 6741 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 6742 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 6743 6744 #define S_FW_VI_ENABLE_CMD_LED 29 6745 #define M_FW_VI_ENABLE_CMD_LED 0x1 6746 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 6747 #define G_FW_VI_ENABLE_CMD_LED(x) \ 6748 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 6749 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 6750 6751 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 6752 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 6753 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 6754 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 6755 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 6756 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 6757 6758 /* VI VF stats offset definitions */ 6759 #define VI_VF_NUM_STATS 16 6760 enum fw_vi_stats_vf_index { 6761 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 6762 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 6763 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 6764 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 6765 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 6766 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 6767 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 6768 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 6769 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 6770 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 6771 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 6772 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 6773 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 6774 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 6775 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 6776 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 6777 }; 6778 6779 /* VI PF stats offset definitions */ 6780 #define VI_PF_NUM_STATS 17 6781 enum fw_vi_stats_pf_index { 6782 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 6783 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 6784 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 6785 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 6786 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 6787 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 6788 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 6789 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 6790 FW_VI_PF_STAT_RX_BYTES_IX, 6791 FW_VI_PF_STAT_RX_FRAMES_IX, 6792 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 6793 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 6794 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 6795 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 6796 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 6797 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 6798 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 6799 }; 6800 6801 struct fw_vi_stats_cmd { 6802 __be32 op_to_viid; 6803 __be32 retval_len16; 6804 union fw_vi_stats { 6805 struct fw_vi_stats_ctl { 6806 __be16 nstats_ix; 6807 __be16 r6; 6808 __be32 r7; 6809 __be64 stat0; 6810 __be64 stat1; 6811 __be64 stat2; 6812 __be64 stat3; 6813 __be64 stat4; 6814 __be64 stat5; 6815 } ctl; 6816 struct fw_vi_stats_pf { 6817 __be64 tx_bcast_bytes; 6818 __be64 tx_bcast_frames; 6819 __be64 tx_mcast_bytes; 6820 __be64 tx_mcast_frames; 6821 __be64 tx_ucast_bytes; 6822 __be64 tx_ucast_frames; 6823 __be64 tx_offload_bytes; 6824 __be64 tx_offload_frames; 6825 __be64 rx_pf_bytes; 6826 __be64 rx_pf_frames; 6827 __be64 rx_bcast_bytes; 6828 __be64 rx_bcast_frames; 6829 __be64 rx_mcast_bytes; 6830 __be64 rx_mcast_frames; 6831 __be64 rx_ucast_bytes; 6832 __be64 rx_ucast_frames; 6833 __be64 rx_err_frames; 6834 } pf; 6835 struct fw_vi_stats_vf { 6836 __be64 tx_bcast_bytes; 6837 __be64 tx_bcast_frames; 6838 __be64 tx_mcast_bytes; 6839 __be64 tx_mcast_frames; 6840 __be64 tx_ucast_bytes; 6841 __be64 tx_ucast_frames; 6842 __be64 tx_drop_frames; 6843 __be64 tx_offload_bytes; 6844 __be64 tx_offload_frames; 6845 __be64 rx_bcast_bytes; 6846 __be64 rx_bcast_frames; 6847 __be64 rx_mcast_bytes; 6848 __be64 rx_mcast_frames; 6849 __be64 rx_ucast_bytes; 6850 __be64 rx_ucast_frames; 6851 __be64 rx_err_frames; 6852 } vf; 6853 } u; 6854 }; 6855 6856 #define S_FW_VI_STATS_CMD_VIID 0 6857 #define M_FW_VI_STATS_CMD_VIID 0xfff 6858 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 6859 #define G_FW_VI_STATS_CMD_VIID(x) \ 6860 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 6861 6862 #define S_FW_VI_STATS_CMD_NSTATS 12 6863 #define M_FW_VI_STATS_CMD_NSTATS 0x7 6864 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 6865 #define G_FW_VI_STATS_CMD_NSTATS(x) \ 6866 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 6867 6868 #define S_FW_VI_STATS_CMD_IX 0 6869 #define M_FW_VI_STATS_CMD_IX 0x1f 6870 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 6871 #define G_FW_VI_STATS_CMD_IX(x) \ 6872 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 6873 6874 struct fw_acl_mac_cmd { 6875 __be32 op_to_vfn; 6876 __be32 en_to_len16; 6877 __u8 nmac; 6878 __u8 r3[7]; 6879 __be16 r4; 6880 __u8 macaddr0[6]; 6881 __be16 r5; 6882 __u8 macaddr1[6]; 6883 __be16 r6; 6884 __u8 macaddr2[6]; 6885 __be16 r7; 6886 __u8 macaddr3[6]; 6887 }; 6888 6889 #define S_FW_ACL_MAC_CMD_PFN 8 6890 #define M_FW_ACL_MAC_CMD_PFN 0x7 6891 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 6892 #define G_FW_ACL_MAC_CMD_PFN(x) \ 6893 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 6894 6895 #define S_FW_ACL_MAC_CMD_VFN 0 6896 #define M_FW_ACL_MAC_CMD_VFN 0xff 6897 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 6898 #define G_FW_ACL_MAC_CMD_VFN(x) \ 6899 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 6900 6901 #define S_FW_ACL_MAC_CMD_EN 31 6902 #define M_FW_ACL_MAC_CMD_EN 0x1 6903 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 6904 #define G_FW_ACL_MAC_CMD_EN(x) \ 6905 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 6906 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 6907 6908 struct fw_acl_vlan_cmd { 6909 __be32 op_to_vfn; 6910 __be32 en_to_len16; 6911 __u8 nvlan; 6912 __u8 dropnovlan_fm; 6913 __u8 r3_lo[6]; 6914 __be16 vlanid[16]; 6915 }; 6916 6917 #define S_FW_ACL_VLAN_CMD_PFN 8 6918 #define M_FW_ACL_VLAN_CMD_PFN 0x7 6919 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 6920 #define G_FW_ACL_VLAN_CMD_PFN(x) \ 6921 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 6922 6923 #define S_FW_ACL_VLAN_CMD_VFN 0 6924 #define M_FW_ACL_VLAN_CMD_VFN 0xff 6925 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 6926 #define G_FW_ACL_VLAN_CMD_VFN(x) \ 6927 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 6928 6929 #define S_FW_ACL_VLAN_CMD_EN 31 6930 #define M_FW_ACL_VLAN_CMD_EN 0x1 6931 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 6932 #define G_FW_ACL_VLAN_CMD_EN(x) \ 6933 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 6934 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 6935 6936 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 6937 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 6938 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 6939 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 6940 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 6941 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 6942 6943 #define S_FW_ACL_VLAN_CMD_FM 6 6944 #define M_FW_ACL_VLAN_CMD_FM 0x1 6945 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 6946 #define G_FW_ACL_VLAN_CMD_FM(x) \ 6947 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 6948 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 6949 6950 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ 6951 enum fw_port_cap { 6952 FW_PORT_CAP_SPEED_100M = 0x0001, 6953 FW_PORT_CAP_SPEED_1G = 0x0002, 6954 FW_PORT_CAP_SPEED_25G = 0x0004, 6955 FW_PORT_CAP_SPEED_10G = 0x0008, 6956 FW_PORT_CAP_SPEED_40G = 0x0010, 6957 FW_PORT_CAP_SPEED_100G = 0x0020, 6958 FW_PORT_CAP_FC_RX = 0x0040, 6959 FW_PORT_CAP_FC_TX = 0x0080, 6960 FW_PORT_CAP_ANEG = 0x0100, 6961 FW_PORT_CAP_MDIAUTO = 0x0200, 6962 FW_PORT_CAP_MDISTRAIGHT = 0x0400, 6963 FW_PORT_CAP_FEC_RS = 0x0800, 6964 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 6965 FW_PORT_CAP_FORCE_PAUSE = 0x2000, 6966 FW_PORT_CAP_802_3_PAUSE = 0x4000, 6967 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 6968 }; 6969 6970 #define S_FW_PORT_CAP_SPEED 0 6971 #define M_FW_PORT_CAP_SPEED 0x3f 6972 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 6973 #define G_FW_PORT_CAP_SPEED(x) \ 6974 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 6975 6976 #define S_FW_PORT_CAP_FC 6 6977 #define M_FW_PORT_CAP_FC 0x3 6978 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 6979 #define G_FW_PORT_CAP_FC(x) \ 6980 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 6981 6982 #define S_FW_PORT_CAP_ANEG 8 6983 #define M_FW_PORT_CAP_ANEG 0x1 6984 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 6985 #define G_FW_PORT_CAP_ANEG(x) \ 6986 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 6987 6988 #define S_FW_PORT_CAP_FEC 11 6989 #define M_FW_PORT_CAP_FEC 0x3 6990 #define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC) 6991 #define G_FW_PORT_CAP_FEC(x) \ 6992 (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC) 6993 6994 #define S_FW_PORT_CAP_FORCE_PAUSE 13 6995 #define M_FW_PORT_CAP_FORCE_PAUSE 0x1 6996 #define V_FW_PORT_CAP_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP_FORCE_PAUSE) 6997 #define G_FW_PORT_CAP_FORCE_PAUSE(x) \ 6998 (((x) >> S_FW_PORT_CAP_FORCE_PAUSE) & M_FW_PORT_CAP_FORCE_PAUSE) 6999 7000 #define S_FW_PORT_CAP_802_3 14 7001 #define M_FW_PORT_CAP_802_3 0x3 7002 #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) 7003 #define G_FW_PORT_CAP_802_3(x) \ 7004 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) 7005 7006 enum fw_port_mdi { 7007 FW_PORT_CAP_MDI_UNCHANGED, 7008 FW_PORT_CAP_MDI_AUTO, 7009 FW_PORT_CAP_MDI_F_STRAIGHT, 7010 FW_PORT_CAP_MDI_F_CROSSOVER 7011 }; 7012 7013 #define S_FW_PORT_CAP_MDI 9 7014 #define M_FW_PORT_CAP_MDI 3 7015 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 7016 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 7017 7018 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 7019 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 7020 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 7021 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 7022 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 7023 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 7024 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 7025 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 7026 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL 7027 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL 7028 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL 7029 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL 7030 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL 7031 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL 7032 #define FW_PORT_CAP32_FC_RX 0x00010000UL 7033 #define FW_PORT_CAP32_FC_TX 0x00020000UL 7034 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 7035 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 7036 #define FW_PORT_CAP32_ANEG 0x00100000UL 7037 #define FW_PORT_CAP32_MDIAUTO 0x00200000UL 7038 #define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL 7039 #define FW_PORT_CAP32_FEC_RS 0x00800000UL 7040 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 7041 #define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL 7042 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL 7043 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL 7044 #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL 7045 #define FW_PORT_CAP32_RESERVED2 0xe0000000UL 7046 7047 #define S_FW_PORT_CAP32_SPEED 0 7048 #define M_FW_PORT_CAP32_SPEED 0xfff 7049 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED) 7050 #define G_FW_PORT_CAP32_SPEED(x) \ 7051 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED) 7052 7053 #define S_FW_PORT_CAP32_FC 16 7054 #define M_FW_PORT_CAP32_FC 0x3 7055 #define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC) 7056 #define G_FW_PORT_CAP32_FC(x) \ 7057 (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC) 7058 7059 #define S_FW_PORT_CAP32_802_3 18 7060 #define M_FW_PORT_CAP32_802_3 0x3 7061 #define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3) 7062 #define G_FW_PORT_CAP32_802_3(x) \ 7063 (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3) 7064 7065 #define S_FW_PORT_CAP32_ANEG 20 7066 #define M_FW_PORT_CAP32_ANEG 0x1 7067 #define V_FW_PORT_CAP32_ANEG(x) ((x) << S_FW_PORT_CAP32_ANEG) 7068 #define G_FW_PORT_CAP32_ANEG(x) \ 7069 (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG) 7070 7071 #define S_FW_PORT_CAP32_FORCE_PAUSE 28 7072 #define M_FW_PORT_CAP32_FORCE_PAUSE 0x1 7073 #define V_FW_PORT_CAP32_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP32_FORCE_PAUSE) 7074 #define G_FW_PORT_CAP32_FORCE_PAUSE(x) \ 7075 (((x) >> S_FW_PORT_CAP32_FORCE_PAUSE) & M_FW_PORT_CAP32_FORCE_PAUSE) 7076 7077 enum fw_port_mdi32 { 7078 FW_PORT_CAP32_MDI_UNCHANGED, 7079 FW_PORT_CAP32_MDI_AUTO, 7080 FW_PORT_CAP32_MDI_F_STRAIGHT, 7081 FW_PORT_CAP32_MDI_F_CROSSOVER 7082 }; 7083 7084 #define S_FW_PORT_CAP32_MDI 21 7085 #define M_FW_PORT_CAP32_MDI 3 7086 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI) 7087 #define G_FW_PORT_CAP32_MDI(x) \ 7088 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI) 7089 7090 #define S_FW_PORT_CAP32_FEC 23 7091 #define M_FW_PORT_CAP32_FEC 0x1f 7092 #define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC) 7093 #define G_FW_PORT_CAP32_FEC(x) \ 7094 (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC) 7095 7096 /* macros to isolate various 32-bit Port Capabilities sub-fields */ 7097 #define CAP32_SPEED(__cap32) \ 7098 (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) & __cap32) 7099 7100 #define CAP32_FEC(__cap32) \ 7101 (V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32) 7102 7103 #define CAP32_FC(__cap32) \ 7104 (V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC) & __cap32) 7105 7106 enum fw_port_action { 7107 FW_PORT_ACTION_L1_CFG = 0x0001, 7108 FW_PORT_ACTION_L2_CFG = 0x0002, 7109 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 7110 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 7111 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 7112 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 7113 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 7114 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 7115 FW_PORT_ACTION_L1_CFG32 = 0x0009, 7116 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 7117 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 7118 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 7119 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 7120 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 7121 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 7122 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 7123 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 7124 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 7125 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 7126 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 7127 FW_PORT_ACTION_PHY_RESET = 0x0040, 7128 FW_PORT_ACTION_PMA_RESET = 0x0041, 7129 FW_PORT_ACTION_PCS_RESET = 0x0042, 7130 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 7131 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 7132 FW_PORT_ACTION_AN_RESET = 0x0045, 7133 }; 7134 7135 enum fw_port_l2cfg_ctlbf { 7136 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 7137 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 7138 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 7139 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 7140 FW_PORT_L2_CTLBF_IVLAN = 0x10, 7141 FW_PORT_L2_CTLBF_TXIPG = 0x20, 7142 FW_PORT_L2_CTLBF_MTU = 0x40 7143 }; 7144 7145 enum fw_dcb_app_tlv_sf { 7146 FW_DCB_APP_SF_ETHERTYPE, 7147 FW_DCB_APP_SF_SOCKET_TCP, 7148 FW_DCB_APP_SF_SOCKET_UDP, 7149 FW_DCB_APP_SF_SOCKET_ALL, 7150 }; 7151 7152 enum fw_port_dcb_versions { 7153 FW_PORT_DCB_VER_UNKNOWN, 7154 FW_PORT_DCB_VER_CEE1D0, 7155 FW_PORT_DCB_VER_CEE1D01, 7156 FW_PORT_DCB_VER_IEEE, 7157 FW_PORT_DCB_VER_AUTO=7 7158 }; 7159 7160 enum fw_port_dcb_cfg { 7161 FW_PORT_DCB_CFG_PG = 0x01, 7162 FW_PORT_DCB_CFG_PFC = 0x02, 7163 FW_PORT_DCB_CFG_APPL = 0x04 7164 }; 7165 7166 enum fw_port_dcb_cfg_rc { 7167 FW_PORT_DCB_CFG_SUCCESS = 0x0, 7168 FW_PORT_DCB_CFG_ERROR = 0x1 7169 }; 7170 7171 enum fw_port_dcb_type { 7172 FW_PORT_DCB_TYPE_PGID = 0x00, 7173 FW_PORT_DCB_TYPE_PGRATE = 0x01, 7174 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 7175 FW_PORT_DCB_TYPE_PFC = 0x03, 7176 FW_PORT_DCB_TYPE_APP_ID = 0x04, 7177 FW_PORT_DCB_TYPE_CONTROL = 0x05, 7178 }; 7179 7180 enum fw_port_dcb_feature_state { 7181 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 7182 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 7183 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 7184 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 7185 }; 7186 7187 enum fw_port_diag_ops { 7188 FW_PORT_DIAGS_TEMP = 0x00, 7189 FW_PORT_DIAGS_TX_POWER = 0x01, 7190 FW_PORT_DIAGS_RX_POWER = 0x02, 7191 FW_PORT_DIAGS_TX_DIS = 0x03, 7192 }; 7193 7194 struct fw_port_cmd { 7195 __be32 op_to_portid; 7196 __be32 action_to_len16; 7197 union fw_port { 7198 struct fw_port_l1cfg { 7199 __be32 rcap; 7200 __be32 r; 7201 } l1cfg; 7202 struct fw_port_l2cfg { 7203 __u8 ctlbf; 7204 __u8 ovlan3_to_ivlan0; 7205 __be16 ivlantype; 7206 __be16 txipg_force_pinfo; 7207 __be16 mtu; 7208 __be16 ovlan0mask; 7209 __be16 ovlan0type; 7210 __be16 ovlan1mask; 7211 __be16 ovlan1type; 7212 __be16 ovlan2mask; 7213 __be16 ovlan2type; 7214 __be16 ovlan3mask; 7215 __be16 ovlan3type; 7216 } l2cfg; 7217 struct fw_port_info { 7218 __be32 lstatus_to_modtype; 7219 __be16 pcap; 7220 __be16 acap; 7221 __be16 mtu; 7222 __u8 cbllen; 7223 __u8 auxlinfo; 7224 __u8 dcbxdis_pkd; 7225 __u8 r8_lo; 7226 __be16 lpacap; 7227 __be64 r9; 7228 } info; 7229 struct fw_port_diags { 7230 __u8 diagop; 7231 __u8 r[3]; 7232 __be32 diagval; 7233 } diags; 7234 union fw_port_dcb { 7235 struct fw_port_dcb_pgid { 7236 __u8 type; 7237 __u8 apply_pkd; 7238 __u8 r10_lo[2]; 7239 __be32 pgid; 7240 __be64 r11; 7241 } pgid; 7242 struct fw_port_dcb_pgrate { 7243 __u8 type; 7244 __u8 apply_pkd; 7245 __u8 r10_lo[5]; 7246 __u8 num_tcs_supported; 7247 __u8 pgrate[8]; 7248 __u8 tsa[8]; 7249 } pgrate; 7250 struct fw_port_dcb_priorate { 7251 __u8 type; 7252 __u8 apply_pkd; 7253 __u8 r10_lo[6]; 7254 __u8 strict_priorate[8]; 7255 } priorate; 7256 struct fw_port_dcb_pfc { 7257 __u8 type; 7258 __u8 pfcen; 7259 __u8 r10[5]; 7260 __u8 max_pfc_tcs; 7261 __be64 r11; 7262 } pfc; 7263 struct fw_port_app_priority { 7264 __u8 type; 7265 __u8 r10[2]; 7266 __u8 idx; 7267 __u8 user_prio_map; 7268 __u8 sel_field; 7269 __be16 protocolid; 7270 __be64 r12; 7271 } app_priority; 7272 struct fw_port_dcb_control { 7273 __u8 type; 7274 __u8 all_syncd_pkd; 7275 __be16 dcb_version_to_app_state; 7276 __be32 r11; 7277 __be64 r12; 7278 } control; 7279 } dcb; 7280 struct fw_port_l1cfg32 { 7281 __be32 rcap32; 7282 __be32 r; 7283 } l1cfg32; 7284 struct fw_port_info32 { 7285 __be32 lstatus32_to_cbllen32; 7286 __be32 auxlinfo32_mtu32; 7287 __be32 linkattr32; 7288 __be32 pcaps32; 7289 __be32 acaps32; 7290 __be32 lpacaps32; 7291 } info32; 7292 } u; 7293 }; 7294 7295 #define S_FW_PORT_CMD_READ 22 7296 #define M_FW_PORT_CMD_READ 0x1 7297 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 7298 #define G_FW_PORT_CMD_READ(x) \ 7299 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 7300 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 7301 7302 #define S_FW_PORT_CMD_PORTID 0 7303 #define M_FW_PORT_CMD_PORTID 0xf 7304 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 7305 #define G_FW_PORT_CMD_PORTID(x) \ 7306 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 7307 7308 #define S_FW_PORT_CMD_ACTION 16 7309 #define M_FW_PORT_CMD_ACTION 0xffff 7310 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 7311 #define G_FW_PORT_CMD_ACTION(x) \ 7312 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 7313 7314 #define S_FW_PORT_CMD_OVLAN3 7 7315 #define M_FW_PORT_CMD_OVLAN3 0x1 7316 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 7317 #define G_FW_PORT_CMD_OVLAN3(x) \ 7318 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 7319 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 7320 7321 #define S_FW_PORT_CMD_OVLAN2 6 7322 #define M_FW_PORT_CMD_OVLAN2 0x1 7323 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 7324 #define G_FW_PORT_CMD_OVLAN2(x) \ 7325 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 7326 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 7327 7328 #define S_FW_PORT_CMD_OVLAN1 5 7329 #define M_FW_PORT_CMD_OVLAN1 0x1 7330 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 7331 #define G_FW_PORT_CMD_OVLAN1(x) \ 7332 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 7333 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 7334 7335 #define S_FW_PORT_CMD_OVLAN0 4 7336 #define M_FW_PORT_CMD_OVLAN0 0x1 7337 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 7338 #define G_FW_PORT_CMD_OVLAN0(x) \ 7339 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 7340 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 7341 7342 #define S_FW_PORT_CMD_IVLAN0 3 7343 #define M_FW_PORT_CMD_IVLAN0 0x1 7344 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 7345 #define G_FW_PORT_CMD_IVLAN0(x) \ 7346 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 7347 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 7348 7349 #define S_FW_PORT_CMD_TXIPG 3 7350 #define M_FW_PORT_CMD_TXIPG 0x1fff 7351 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 7352 #define G_FW_PORT_CMD_TXIPG(x) \ 7353 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 7354 7355 #define S_FW_PORT_CMD_FORCE_PINFO 0 7356 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 7357 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 7358 #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 7359 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 7360 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 7361 7362 #define S_FW_PORT_CMD_LSTATUS 31 7363 #define M_FW_PORT_CMD_LSTATUS 0x1 7364 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 7365 #define G_FW_PORT_CMD_LSTATUS(x) \ 7366 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 7367 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 7368 7369 #define S_FW_PORT_CMD_LSPEED 24 7370 #define M_FW_PORT_CMD_LSPEED 0x3f 7371 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 7372 #define G_FW_PORT_CMD_LSPEED(x) \ 7373 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 7374 7375 #define S_FW_PORT_CMD_TXPAUSE 23 7376 #define M_FW_PORT_CMD_TXPAUSE 0x1 7377 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 7378 #define G_FW_PORT_CMD_TXPAUSE(x) \ 7379 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 7380 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 7381 7382 #define S_FW_PORT_CMD_RXPAUSE 22 7383 #define M_FW_PORT_CMD_RXPAUSE 0x1 7384 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 7385 #define G_FW_PORT_CMD_RXPAUSE(x) \ 7386 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 7387 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 7388 7389 #define S_FW_PORT_CMD_MDIOCAP 21 7390 #define M_FW_PORT_CMD_MDIOCAP 0x1 7391 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 7392 #define G_FW_PORT_CMD_MDIOCAP(x) \ 7393 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 7394 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 7395 7396 #define S_FW_PORT_CMD_MDIOADDR 16 7397 #define M_FW_PORT_CMD_MDIOADDR 0x1f 7398 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 7399 #define G_FW_PORT_CMD_MDIOADDR(x) \ 7400 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 7401 7402 #define S_FW_PORT_CMD_LPTXPAUSE 15 7403 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 7404 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 7405 #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 7406 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 7407 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 7408 7409 #define S_FW_PORT_CMD_LPRXPAUSE 14 7410 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 7411 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 7412 #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 7413 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 7414 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 7415 7416 #define S_FW_PORT_CMD_PTYPE 8 7417 #define M_FW_PORT_CMD_PTYPE 0x1f 7418 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 7419 #define G_FW_PORT_CMD_PTYPE(x) \ 7420 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 7421 7422 #define S_FW_PORT_CMD_LINKDNRC 5 7423 #define M_FW_PORT_CMD_LINKDNRC 0x7 7424 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 7425 #define G_FW_PORT_CMD_LINKDNRC(x) \ 7426 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 7427 7428 #define S_FW_PORT_CMD_MODTYPE 0 7429 #define M_FW_PORT_CMD_MODTYPE 0x1f 7430 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 7431 #define G_FW_PORT_CMD_MODTYPE(x) \ 7432 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 7433 7434 #define S_FW_PORT_AUXLINFO_KX4 2 7435 #define M_FW_PORT_AUXLINFO_KX4 0x1 7436 #define V_FW_PORT_AUXLINFO_KX4(x) \ 7437 ((x) << S_FW_PORT_AUXLINFO_KX4) 7438 #define G_FW_PORT_AUXLINFO_KX4(x) \ 7439 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 7440 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 7441 7442 #define S_FW_PORT_AUXLINFO_KR 1 7443 #define M_FW_PORT_AUXLINFO_KR 0x1 7444 #define V_FW_PORT_AUXLINFO_KR(x) \ 7445 ((x) << S_FW_PORT_AUXLINFO_KR) 7446 #define G_FW_PORT_AUXLINFO_KR(x) \ 7447 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 7448 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 7449 7450 #define S_FW_PORT_CMD_DCBXDIS 7 7451 #define M_FW_PORT_CMD_DCBXDIS 0x1 7452 #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 7453 #define G_FW_PORT_CMD_DCBXDIS(x) \ 7454 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 7455 #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 7456 7457 #define S_FW_PORT_CMD_APPLY 7 7458 #define M_FW_PORT_CMD_APPLY 0x1 7459 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 7460 #define G_FW_PORT_CMD_APPLY(x) \ 7461 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 7462 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 7463 7464 #define S_FW_PORT_CMD_ALL_SYNCD 7 7465 #define M_FW_PORT_CMD_ALL_SYNCD 0x1 7466 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 7467 #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 7468 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 7469 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 7470 7471 #define S_FW_PORT_CMD_DCB_VERSION 12 7472 #define M_FW_PORT_CMD_DCB_VERSION 0x7 7473 #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) 7474 #define G_FW_PORT_CMD_DCB_VERSION(x) \ 7475 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) 7476 7477 #define S_FW_PORT_CMD_PFC_STATE 8 7478 #define M_FW_PORT_CMD_PFC_STATE 0xf 7479 #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 7480 #define G_FW_PORT_CMD_PFC_STATE(x) \ 7481 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 7482 7483 #define S_FW_PORT_CMD_ETS_STATE 4 7484 #define M_FW_PORT_CMD_ETS_STATE 0xf 7485 #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 7486 #define G_FW_PORT_CMD_ETS_STATE(x) \ 7487 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 7488 7489 #define S_FW_PORT_CMD_APP_STATE 0 7490 #define M_FW_PORT_CMD_APP_STATE 0xf 7491 #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 7492 #define G_FW_PORT_CMD_APP_STATE(x) \ 7493 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 7494 7495 #define S_FW_PORT_CMD_LSTATUS32 31 7496 #define M_FW_PORT_CMD_LSTATUS32 0x1 7497 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32) 7498 #define G_FW_PORT_CMD_LSTATUS32(x) \ 7499 (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32) 7500 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U) 7501 7502 #define S_FW_PORT_CMD_LINKDNRC32 28 7503 #define M_FW_PORT_CMD_LINKDNRC32 0x7 7504 #define V_FW_PORT_CMD_LINKDNRC32(x) ((x) << S_FW_PORT_CMD_LINKDNRC32) 7505 #define G_FW_PORT_CMD_LINKDNRC32(x) \ 7506 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32) 7507 7508 #define S_FW_PORT_CMD_DCBXDIS32 27 7509 #define M_FW_PORT_CMD_DCBXDIS32 0x1 7510 #define V_FW_PORT_CMD_DCBXDIS32(x) ((x) << S_FW_PORT_CMD_DCBXDIS32) 7511 #define G_FW_PORT_CMD_DCBXDIS32(x) \ 7512 (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32) 7513 #define F_FW_PORT_CMD_DCBXDIS32 V_FW_PORT_CMD_DCBXDIS32(1U) 7514 7515 #define S_FW_PORT_CMD_MDIOCAP32 26 7516 #define M_FW_PORT_CMD_MDIOCAP32 0x1 7517 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32) 7518 #define G_FW_PORT_CMD_MDIOCAP32(x) \ 7519 (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32) 7520 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U) 7521 7522 #define S_FW_PORT_CMD_MDIOADDR32 21 7523 #define M_FW_PORT_CMD_MDIOADDR32 0x1f 7524 #define V_FW_PORT_CMD_MDIOADDR32(x) ((x) << S_FW_PORT_CMD_MDIOADDR32) 7525 #define G_FW_PORT_CMD_MDIOADDR32(x) \ 7526 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32) 7527 7528 #define S_FW_PORT_CMD_PORTTYPE32 13 7529 #define M_FW_PORT_CMD_PORTTYPE32 0xff 7530 #define V_FW_PORT_CMD_PORTTYPE32(x) ((x) << S_FW_PORT_CMD_PORTTYPE32) 7531 #define G_FW_PORT_CMD_PORTTYPE32(x) \ 7532 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32) 7533 7534 #define S_FW_PORT_CMD_MODTYPE32 8 7535 #define M_FW_PORT_CMD_MODTYPE32 0x1f 7536 #define V_FW_PORT_CMD_MODTYPE32(x) ((x) << S_FW_PORT_CMD_MODTYPE32) 7537 #define G_FW_PORT_CMD_MODTYPE32(x) \ 7538 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32) 7539 7540 #define S_FW_PORT_CMD_CBLLEN32 0 7541 #define M_FW_PORT_CMD_CBLLEN32 0xff 7542 #define V_FW_PORT_CMD_CBLLEN32(x) ((x) << S_FW_PORT_CMD_CBLLEN32) 7543 #define G_FW_PORT_CMD_CBLLEN32(x) \ 7544 (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32) 7545 7546 #define S_FW_PORT_CMD_AUXLINFO32 24 7547 #define M_FW_PORT_CMD_AUXLINFO32 0xff 7548 #define V_FW_PORT_CMD_AUXLINFO32(x) ((x) << S_FW_PORT_CMD_AUXLINFO32) 7549 #define G_FW_PORT_CMD_AUXLINFO32(x) \ 7550 (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32) 7551 7552 #define S_FW_PORT_AUXLINFO32_KX4 2 7553 #define M_FW_PORT_AUXLINFO32_KX4 0x1 7554 #define V_FW_PORT_AUXLINFO32_KX4(x) \ 7555 ((x) << S_FW_PORT_AUXLINFO32_KX4) 7556 #define G_FW_PORT_AUXLINFO32_KX4(x) \ 7557 (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4) 7558 #define F_FW_PORT_AUXLINFO32_KX4 V_FW_PORT_AUXLINFO32_KX4(1U) 7559 7560 #define S_FW_PORT_AUXLINFO32_KR 1 7561 #define M_FW_PORT_AUXLINFO32_KR 0x1 7562 #define V_FW_PORT_AUXLINFO32_KR(x) \ 7563 ((x) << S_FW_PORT_AUXLINFO32_KR) 7564 #define G_FW_PORT_AUXLINFO32_KR(x) \ 7565 (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR) 7566 #define F_FW_PORT_AUXLINFO32_KR V_FW_PORT_AUXLINFO32_KR(1U) 7567 7568 #define S_FW_PORT_CMD_MTU32 0 7569 #define M_FW_PORT_CMD_MTU32 0xffff 7570 #define V_FW_PORT_CMD_MTU32(x) ((x) << S_FW_PORT_CMD_MTU32) 7571 #define G_FW_PORT_CMD_MTU32(x) \ 7572 (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32) 7573 7574 /* 7575 * These are configured into the VPD and hence tools that generate 7576 * VPD may use this enumeration. 7577 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 7578 * 7579 * REMEMBER: 7580 * Update the Common Code t4_hw.c:t4_get_port_type_description() 7581 * with any new Firmware Port Technology Types! 7582 */ 7583 enum fw_port_type { 7584 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 7585 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 7586 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 7587 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ 7588 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ 7589 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 7590 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 7591 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 7592 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 7593 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 7594 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 7595 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 7596 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 7597 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 7598 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 7599 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 7600 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */ 7601 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ 7602 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */ 7603 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ 7604 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ 7605 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ 7606 FW_PORT_TYPE_KR_XLAUI = 22, /* No, 4, 40G/10G/1G, No AN*/ 7607 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 7608 }; 7609 7610 /* These are read from module's EEPROM and determined once the 7611 module is inserted. */ 7612 enum fw_port_module_type { 7613 FW_PORT_MOD_TYPE_NA = 0x0, 7614 FW_PORT_MOD_TYPE_LR = 0x1, 7615 FW_PORT_MOD_TYPE_SR = 0x2, 7616 FW_PORT_MOD_TYPE_ER = 0x3, 7617 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 7618 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 7619 FW_PORT_MOD_TYPE_LRM = 0x6, 7620 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 7621 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 7622 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 7623 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 7624 }; 7625 7626 /* used by FW and tools may use this to generate VPD */ 7627 enum fw_port_mod_sub_type { 7628 FW_PORT_MOD_SUB_TYPE_NA, 7629 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 7630 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 7631 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 7632 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 7633 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 7634 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 7635 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, 7636 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 7637 7638 /* 7639 * The following will never been in the VPD. They are TWINAX cable 7640 * lengths decoded from SFP+ module i2c PROMs. These should almost 7641 * certainly go somewhere else ... 7642 */ 7643 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 7644 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 7645 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 7646 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 7647 }; 7648 7649 /* link down reason codes (3b) */ 7650 enum fw_port_link_dn_rc { 7651 FW_PORT_LINK_DN_RC_NONE, 7652 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 7653 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 7654 FW_PORT_LINK_DN_RESERVED3, 7655 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 7656 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 7657 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 7658 FW_PORT_LINK_DN_RESERVED7 7659 }; 7660 enum fw_port_stats_tx_index { 7661 FW_STAT_TX_PORT_BYTES_IX = 0, 7662 FW_STAT_TX_PORT_FRAMES_IX, 7663 FW_STAT_TX_PORT_BCAST_IX, 7664 FW_STAT_TX_PORT_MCAST_IX, 7665 FW_STAT_TX_PORT_UCAST_IX, 7666 FW_STAT_TX_PORT_ERROR_IX, 7667 FW_STAT_TX_PORT_64B_IX, 7668 FW_STAT_TX_PORT_65B_127B_IX, 7669 FW_STAT_TX_PORT_128B_255B_IX, 7670 FW_STAT_TX_PORT_256B_511B_IX, 7671 FW_STAT_TX_PORT_512B_1023B_IX, 7672 FW_STAT_TX_PORT_1024B_1518B_IX, 7673 FW_STAT_TX_PORT_1519B_MAX_IX, 7674 FW_STAT_TX_PORT_DROP_IX, 7675 FW_STAT_TX_PORT_PAUSE_IX, 7676 FW_STAT_TX_PORT_PPP0_IX, 7677 FW_STAT_TX_PORT_PPP1_IX, 7678 FW_STAT_TX_PORT_PPP2_IX, 7679 FW_STAT_TX_PORT_PPP3_IX, 7680 FW_STAT_TX_PORT_PPP4_IX, 7681 FW_STAT_TX_PORT_PPP5_IX, 7682 FW_STAT_TX_PORT_PPP6_IX, 7683 FW_STAT_TX_PORT_PPP7_IX, 7684 FW_NUM_PORT_TX_STATS 7685 }; 7686 7687 enum fw_port_stat_rx_index { 7688 FW_STAT_RX_PORT_BYTES_IX = 0, 7689 FW_STAT_RX_PORT_FRAMES_IX, 7690 FW_STAT_RX_PORT_BCAST_IX, 7691 FW_STAT_RX_PORT_MCAST_IX, 7692 FW_STAT_RX_PORT_UCAST_IX, 7693 FW_STAT_RX_PORT_MTU_ERROR_IX, 7694 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 7695 FW_STAT_RX_PORT_CRC_ERROR_IX, 7696 FW_STAT_RX_PORT_LEN_ERROR_IX, 7697 FW_STAT_RX_PORT_SYM_ERROR_IX, 7698 FW_STAT_RX_PORT_64B_IX, 7699 FW_STAT_RX_PORT_65B_127B_IX, 7700 FW_STAT_RX_PORT_128B_255B_IX, 7701 FW_STAT_RX_PORT_256B_511B_IX, 7702 FW_STAT_RX_PORT_512B_1023B_IX, 7703 FW_STAT_RX_PORT_1024B_1518B_IX, 7704 FW_STAT_RX_PORT_1519B_MAX_IX, 7705 FW_STAT_RX_PORT_PAUSE_IX, 7706 FW_STAT_RX_PORT_PPP0_IX, 7707 FW_STAT_RX_PORT_PPP1_IX, 7708 FW_STAT_RX_PORT_PPP2_IX, 7709 FW_STAT_RX_PORT_PPP3_IX, 7710 FW_STAT_RX_PORT_PPP4_IX, 7711 FW_STAT_RX_PORT_PPP5_IX, 7712 FW_STAT_RX_PORT_PPP6_IX, 7713 FW_STAT_RX_PORT_PPP7_IX, 7714 FW_STAT_RX_PORT_LESS_64B_IX, 7715 FW_STAT_RX_PORT_MAC_ERROR_IX, 7716 FW_NUM_PORT_RX_STATS 7717 }; 7718 /* port stats */ 7719 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ 7720 FW_NUM_PORT_RX_STATS) 7721 7722 7723 struct fw_port_stats_cmd { 7724 __be32 op_to_portid; 7725 __be32 retval_len16; 7726 union fw_port_stats { 7727 struct fw_port_stats_ctl { 7728 __u8 nstats_bg_bm; 7729 __u8 tx_ix; 7730 __be16 r6; 7731 __be32 r7; 7732 __be64 stat0; 7733 __be64 stat1; 7734 __be64 stat2; 7735 __be64 stat3; 7736 __be64 stat4; 7737 __be64 stat5; 7738 } ctl; 7739 struct fw_port_stats_all { 7740 __be64 tx_bytes; 7741 __be64 tx_frames; 7742 __be64 tx_bcast; 7743 __be64 tx_mcast; 7744 __be64 tx_ucast; 7745 __be64 tx_error; 7746 __be64 tx_64b; 7747 __be64 tx_65b_127b; 7748 __be64 tx_128b_255b; 7749 __be64 tx_256b_511b; 7750 __be64 tx_512b_1023b; 7751 __be64 tx_1024b_1518b; 7752 __be64 tx_1519b_max; 7753 __be64 tx_drop; 7754 __be64 tx_pause; 7755 __be64 tx_ppp0; 7756 __be64 tx_ppp1; 7757 __be64 tx_ppp2; 7758 __be64 tx_ppp3; 7759 __be64 tx_ppp4; 7760 __be64 tx_ppp5; 7761 __be64 tx_ppp6; 7762 __be64 tx_ppp7; 7763 __be64 rx_bytes; 7764 __be64 rx_frames; 7765 __be64 rx_bcast; 7766 __be64 rx_mcast; 7767 __be64 rx_ucast; 7768 __be64 rx_mtu_error; 7769 __be64 rx_mtu_crc_error; 7770 __be64 rx_crc_error; 7771 __be64 rx_len_error; 7772 __be64 rx_sym_error; 7773 __be64 rx_64b; 7774 __be64 rx_65b_127b; 7775 __be64 rx_128b_255b; 7776 __be64 rx_256b_511b; 7777 __be64 rx_512b_1023b; 7778 __be64 rx_1024b_1518b; 7779 __be64 rx_1519b_max; 7780 __be64 rx_pause; 7781 __be64 rx_ppp0; 7782 __be64 rx_ppp1; 7783 __be64 rx_ppp2; 7784 __be64 rx_ppp3; 7785 __be64 rx_ppp4; 7786 __be64 rx_ppp5; 7787 __be64 rx_ppp6; 7788 __be64 rx_ppp7; 7789 __be64 rx_less_64b; 7790 __be64 rx_bg_drop; 7791 __be64 rx_bg_trunc; 7792 } all; 7793 } u; 7794 }; 7795 7796 #define S_FW_PORT_STATS_CMD_NSTATS 4 7797 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 7798 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 7799 #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 7800 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 7801 7802 #define S_FW_PORT_STATS_CMD_BG_BM 0 7803 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 7804 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 7805 #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 7806 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 7807 7808 #define S_FW_PORT_STATS_CMD_TX 7 7809 #define M_FW_PORT_STATS_CMD_TX 0x1 7810 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 7811 #define G_FW_PORT_STATS_CMD_TX(x) \ 7812 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 7813 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 7814 7815 #define S_FW_PORT_STATS_CMD_IX 0 7816 #define M_FW_PORT_STATS_CMD_IX 0x3f 7817 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 7818 #define G_FW_PORT_STATS_CMD_IX(x) \ 7819 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 7820 7821 /* port loopback stats */ 7822 #define FW_NUM_LB_STATS 14 7823 enum fw_port_lb_stats_index { 7824 FW_STAT_LB_PORT_BYTES_IX, 7825 FW_STAT_LB_PORT_FRAMES_IX, 7826 FW_STAT_LB_PORT_BCAST_IX, 7827 FW_STAT_LB_PORT_MCAST_IX, 7828 FW_STAT_LB_PORT_UCAST_IX, 7829 FW_STAT_LB_PORT_ERROR_IX, 7830 FW_STAT_LB_PORT_64B_IX, 7831 FW_STAT_LB_PORT_65B_127B_IX, 7832 FW_STAT_LB_PORT_128B_255B_IX, 7833 FW_STAT_LB_PORT_256B_511B_IX, 7834 FW_STAT_LB_PORT_512B_1023B_IX, 7835 FW_STAT_LB_PORT_1024B_1518B_IX, 7836 FW_STAT_LB_PORT_1519B_MAX_IX, 7837 FW_STAT_LB_PORT_DROP_FRAMES_IX 7838 }; 7839 7840 struct fw_port_lb_stats_cmd { 7841 __be32 op_to_lbport; 7842 __be32 retval_len16; 7843 union fw_port_lb_stats { 7844 struct fw_port_lb_stats_ctl { 7845 __u8 nstats_bg_bm; 7846 __u8 ix_pkd; 7847 __be16 r6; 7848 __be32 r7; 7849 __be64 stat0; 7850 __be64 stat1; 7851 __be64 stat2; 7852 __be64 stat3; 7853 __be64 stat4; 7854 __be64 stat5; 7855 } ctl; 7856 struct fw_port_lb_stats_all { 7857 __be64 tx_bytes; 7858 __be64 tx_frames; 7859 __be64 tx_bcast; 7860 __be64 tx_mcast; 7861 __be64 tx_ucast; 7862 __be64 tx_error; 7863 __be64 tx_64b; 7864 __be64 tx_65b_127b; 7865 __be64 tx_128b_255b; 7866 __be64 tx_256b_511b; 7867 __be64 tx_512b_1023b; 7868 __be64 tx_1024b_1518b; 7869 __be64 tx_1519b_max; 7870 __be64 rx_lb_drop; 7871 __be64 rx_lb_trunc; 7872 } all; 7873 } u; 7874 }; 7875 7876 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 7877 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 7878 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7879 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 7880 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7881 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 7882 7883 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 7884 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 7885 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7886 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 7887 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7888 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 7889 7890 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 7891 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 7892 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 7893 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 7894 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 7895 7896 #define S_FW_PORT_LB_STATS_CMD_IX 0 7897 #define M_FW_PORT_LB_STATS_CMD_IX 0xf 7898 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 7899 #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 7900 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 7901 7902 /* Trace related defines */ 7903 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 7904 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 7905 7906 struct fw_port_trace_cmd { 7907 __be32 op_to_portid; 7908 __be32 retval_len16; 7909 __be16 traceen_to_pciech; 7910 __be16 qnum; 7911 __be32 r5; 7912 }; 7913 7914 #define S_FW_PORT_TRACE_CMD_PORTID 0 7915 #define M_FW_PORT_TRACE_CMD_PORTID 0xf 7916 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 7917 #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 7918 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 7919 7920 #define S_FW_PORT_TRACE_CMD_TRACEEN 15 7921 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 7922 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 7923 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 7924 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 7925 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 7926 7927 #define S_FW_PORT_TRACE_CMD_FLTMODE 14 7928 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 7929 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 7930 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 7931 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 7932 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 7933 7934 #define S_FW_PORT_TRACE_CMD_DUPLEN 13 7935 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 7936 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 7937 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 7938 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 7939 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 7940 7941 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 7942 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 7943 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 7944 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 7945 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 7946 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 7947 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 7948 7949 #define S_FW_PORT_TRACE_CMD_PCIECH 6 7950 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 7951 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 7952 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 7953 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 7954 7955 struct fw_port_trace_mmap_cmd { 7956 __be32 op_to_portid; 7957 __be32 retval_len16; 7958 __be32 fid_to_skipoffset; 7959 __be32 minpktsize_capturemax; 7960 __u8 map[224]; 7961 }; 7962 7963 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 7964 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 7965 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 7966 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 7967 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 7968 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 7969 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 7970 7971 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 7972 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 7973 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 7974 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 7975 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 7976 7977 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 7978 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 7979 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 7980 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 7981 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 7982 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 7983 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 7984 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 7985 7986 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 7987 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 7988 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 7989 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 7990 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 7991 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 7992 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 7993 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 7994 7995 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 7996 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 7997 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 7998 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 7999 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 8000 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 8001 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 8002 8003 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 8004 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 8005 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 8006 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 8007 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 8008 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 8009 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 8010 8011 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 8012 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 8013 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 8014 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 8015 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 8016 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 8017 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 8018 8019 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 8020 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 8021 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 8022 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 8023 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 8024 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 8025 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 8026 8027 enum fw_ptp_subop { 8028 8029 /* none */ 8030 FW_PTP_SC_INIT_TIMER = 0x00, 8031 FW_PTP_SC_TX_TYPE = 0x01, 8032 8033 /* init */ 8034 FW_PTP_SC_RXTIME_STAMP = 0x08, 8035 FW_PTP_SC_RDRX_TYPE = 0x09, 8036 8037 /* ts */ 8038 FW_PTP_SC_ADJ_FREQ = 0x10, 8039 FW_PTP_SC_ADJ_TIME = 0x11, 8040 FW_PTP_SC_ADJ_FTIME = 0x12, 8041 FW_PTP_SC_WALL_CLOCK = 0x13, 8042 FW_PTP_SC_GET_TIME = 0x14, 8043 FW_PTP_SC_SET_TIME = 0x15, 8044 }; 8045 8046 struct fw_ptp_cmd { 8047 __be32 op_to_portid; 8048 __be32 retval_len16; 8049 union fw_ptp { 8050 struct fw_ptp_sc { 8051 __u8 sc; 8052 __u8 r3[7]; 8053 } scmd; 8054 struct fw_ptp_init { 8055 __u8 sc; 8056 __u8 txchan; 8057 __be16 absid; 8058 __be16 mode; 8059 __be16 r3; 8060 } init; 8061 struct fw_ptp_ts { 8062 __u8 sc; 8063 __u8 sign; 8064 __be16 r3; 8065 __be32 ppb; 8066 __be64 tm; 8067 } ts; 8068 } u; 8069 __be64 r3; 8070 }; 8071 8072 #define S_FW_PTP_CMD_PORTID 0 8073 #define M_FW_PTP_CMD_PORTID 0xf 8074 #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) 8075 #define G_FW_PTP_CMD_PORTID(x) \ 8076 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) 8077 8078 struct fw_rss_ind_tbl_cmd { 8079 __be32 op_to_viid; 8080 __be32 retval_len16; 8081 __be16 niqid; 8082 __be16 startidx; 8083 __be32 r3; 8084 __be32 iq0_to_iq2; 8085 __be32 iq3_to_iq5; 8086 __be32 iq6_to_iq8; 8087 __be32 iq9_to_iq11; 8088 __be32 iq12_to_iq14; 8089 __be32 iq15_to_iq17; 8090 __be32 iq18_to_iq20; 8091 __be32 iq21_to_iq23; 8092 __be32 iq24_to_iq26; 8093 __be32 iq27_to_iq29; 8094 __be32 iq30_iq31; 8095 __be32 r15_lo; 8096 }; 8097 8098 #define S_FW_RSS_IND_TBL_CMD_VIID 0 8099 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 8100 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 8101 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 8102 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 8103 8104 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 8105 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 8106 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 8107 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 8108 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 8109 8110 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 8111 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 8112 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 8113 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 8114 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 8115 8116 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 8117 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 8118 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 8119 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 8120 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 8121 8122 #define S_FW_RSS_IND_TBL_CMD_IQ3 20 8123 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 8124 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 8125 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 8126 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 8127 8128 #define S_FW_RSS_IND_TBL_CMD_IQ4 10 8129 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 8130 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 8131 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 8132 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 8133 8134 #define S_FW_RSS_IND_TBL_CMD_IQ5 0 8135 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 8136 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 8137 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 8138 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 8139 8140 #define S_FW_RSS_IND_TBL_CMD_IQ6 20 8141 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 8142 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 8143 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 8144 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 8145 8146 #define S_FW_RSS_IND_TBL_CMD_IQ7 10 8147 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 8148 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 8149 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 8150 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 8151 8152 #define S_FW_RSS_IND_TBL_CMD_IQ8 0 8153 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 8154 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 8155 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 8156 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 8157 8158 #define S_FW_RSS_IND_TBL_CMD_IQ9 20 8159 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 8160 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 8161 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 8162 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 8163 8164 #define S_FW_RSS_IND_TBL_CMD_IQ10 10 8165 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 8166 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 8167 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 8168 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 8169 8170 #define S_FW_RSS_IND_TBL_CMD_IQ11 0 8171 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 8172 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 8173 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 8174 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 8175 8176 #define S_FW_RSS_IND_TBL_CMD_IQ12 20 8177 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 8178 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 8179 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 8180 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 8181 8182 #define S_FW_RSS_IND_TBL_CMD_IQ13 10 8183 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 8184 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 8185 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 8186 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 8187 8188 #define S_FW_RSS_IND_TBL_CMD_IQ14 0 8189 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 8190 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 8191 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 8192 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 8193 8194 #define S_FW_RSS_IND_TBL_CMD_IQ15 20 8195 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 8196 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 8197 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 8198 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 8199 8200 #define S_FW_RSS_IND_TBL_CMD_IQ16 10 8201 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 8202 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 8203 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 8204 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 8205 8206 #define S_FW_RSS_IND_TBL_CMD_IQ17 0 8207 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 8208 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 8209 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 8210 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 8211 8212 #define S_FW_RSS_IND_TBL_CMD_IQ18 20 8213 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 8214 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 8215 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 8216 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 8217 8218 #define S_FW_RSS_IND_TBL_CMD_IQ19 10 8219 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 8220 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 8221 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 8222 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 8223 8224 #define S_FW_RSS_IND_TBL_CMD_IQ20 0 8225 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 8226 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 8227 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 8228 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 8229 8230 #define S_FW_RSS_IND_TBL_CMD_IQ21 20 8231 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 8232 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 8233 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 8234 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 8235 8236 #define S_FW_RSS_IND_TBL_CMD_IQ22 10 8237 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 8238 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 8239 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 8240 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 8241 8242 #define S_FW_RSS_IND_TBL_CMD_IQ23 0 8243 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 8244 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 8245 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 8246 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 8247 8248 #define S_FW_RSS_IND_TBL_CMD_IQ24 20 8249 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 8250 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 8251 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 8252 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 8253 8254 #define S_FW_RSS_IND_TBL_CMD_IQ25 10 8255 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 8256 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 8257 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 8258 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 8259 8260 #define S_FW_RSS_IND_TBL_CMD_IQ26 0 8261 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 8262 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 8263 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 8264 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 8265 8266 #define S_FW_RSS_IND_TBL_CMD_IQ27 20 8267 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 8268 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 8269 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 8270 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 8271 8272 #define S_FW_RSS_IND_TBL_CMD_IQ28 10 8273 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 8274 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 8275 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 8276 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 8277 8278 #define S_FW_RSS_IND_TBL_CMD_IQ29 0 8279 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 8280 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 8281 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 8282 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 8283 8284 #define S_FW_RSS_IND_TBL_CMD_IQ30 20 8285 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 8286 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 8287 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 8288 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 8289 8290 #define S_FW_RSS_IND_TBL_CMD_IQ31 10 8291 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 8292 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 8293 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 8294 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 8295 8296 struct fw_rss_glb_config_cmd { 8297 __be32 op_to_write; 8298 __be32 retval_len16; 8299 union fw_rss_glb_config { 8300 struct fw_rss_glb_config_manual { 8301 __be32 mode_pkd; 8302 __be32 r3; 8303 __be64 r4; 8304 __be64 r5; 8305 } manual; 8306 struct fw_rss_glb_config_basicvirtual { 8307 __be32 mode_keymode; 8308 __be32 synmapen_to_hashtoeplitz; 8309 __be64 r8; 8310 __be64 r9; 8311 } basicvirtual; 8312 } u; 8313 }; 8314 8315 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 8316 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 8317 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 8318 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 8319 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 8320 8321 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 8322 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 8323 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 8324 8325 #define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26 8326 #define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3 8327 #define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8328 ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8329 #define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8330 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \ 8331 M_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8332 8333 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0 8334 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1 8335 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2 8336 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3 8337 8338 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 8339 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 8340 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8341 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8342 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8343 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 8344 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8345 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 8346 8347 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 8348 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 8349 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8350 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8351 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8352 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 8353 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8354 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 8355 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 8356 8357 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 8358 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 8359 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8360 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8361 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8362 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 8363 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8364 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 8365 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 8366 8367 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 8368 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 8369 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8370 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8371 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8372 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 8373 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8374 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 8375 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 8376 8377 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 8378 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 8379 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8380 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8381 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8382 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 8383 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8384 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 8385 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 8386 8387 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 8388 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 8389 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8390 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8391 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8392 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 8393 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8394 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 8395 8396 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 8397 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 8398 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8399 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8400 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8401 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 8402 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8403 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 8404 8405 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 8406 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 8407 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8408 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8409 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8410 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 8411 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8412 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 8413 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 8414 8415 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 8416 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 8417 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8418 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8419 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8420 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 8421 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8422 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 8423 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 8424 8425 struct fw_rss_vi_config_cmd { 8426 __be32 op_to_viid; 8427 __be32 retval_len16; 8428 union fw_rss_vi_config { 8429 struct fw_rss_vi_config_manual { 8430 __be64 r3; 8431 __be64 r4; 8432 __be64 r5; 8433 } manual; 8434 struct fw_rss_vi_config_basicvirtual { 8435 __be32 r6; 8436 __be32 defaultq_to_udpen; 8437 __be32 secretkeyidx_pkd; 8438 __be32 secretkeyxor; 8439 __be64 r10; 8440 } basicvirtual; 8441 } u; 8442 }; 8443 8444 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 8445 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 8446 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 8447 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 8448 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 8449 8450 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 8451 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 8452 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8453 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8454 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8455 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 8456 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8457 8458 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 8459 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 8460 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8461 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8462 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8463 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 8464 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8465 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 8466 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 8467 8468 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 8469 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 8470 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8471 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8472 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8473 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 8474 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8475 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 8476 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 8477 8478 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 8479 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 8480 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8481 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8482 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8483 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 8484 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8485 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 8486 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 8487 8488 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 8489 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 8490 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8491 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8492 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8493 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 8494 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8495 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 8496 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 8497 8498 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 8499 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 8500 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 8501 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 8502 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 8503 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 8504 8505 #define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0 8506 #define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf 8507 #define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8508 ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 8509 #define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8510 (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \ 8511 M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 8512 8513 enum fw_sched_sc { 8514 FW_SCHED_SC_CONFIG = 0, 8515 FW_SCHED_SC_PARAMS = 1, 8516 }; 8517 8518 enum fw_sched_type { 8519 FW_SCHED_TYPE_PKTSCHED = 0, 8520 FW_SCHED_TYPE_STREAMSCHED = 1, 8521 }; 8522 8523 enum fw_sched_params_level { 8524 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 8525 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 8526 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 8527 }; 8528 8529 enum fw_sched_params_mode { 8530 FW_SCHED_PARAMS_MODE_CLASS = 0, 8531 FW_SCHED_PARAMS_MODE_FLOW = 1, 8532 }; 8533 8534 enum fw_sched_params_unit { 8535 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 8536 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 8537 }; 8538 8539 enum fw_sched_params_rate { 8540 FW_SCHED_PARAMS_RATE_REL = 0, 8541 FW_SCHED_PARAMS_RATE_ABS = 1, 8542 }; 8543 8544 struct fw_sched_cmd { 8545 __be32 op_to_write; 8546 __be32 retval_len16; 8547 union fw_sched { 8548 struct fw_sched_config { 8549 __u8 sc; 8550 __u8 type; 8551 __u8 minmaxen; 8552 __u8 r3[5]; 8553 __u8 nclasses[4]; 8554 __be32 r4; 8555 } config; 8556 struct fw_sched_params { 8557 __u8 sc; 8558 __u8 type; 8559 __u8 level; 8560 __u8 mode; 8561 __u8 unit; 8562 __u8 rate; 8563 __u8 ch; 8564 __u8 cl; 8565 __be32 min; 8566 __be32 max; 8567 __be16 weight; 8568 __be16 pktsize; 8569 __be16 burstsize; 8570 __be16 r4; 8571 } params; 8572 } u; 8573 }; 8574 8575 /* 8576 * length of the formatting string 8577 */ 8578 #define FW_DEVLOG_FMT_LEN 192 8579 8580 /* 8581 * maximum number of the formatting string parameters 8582 */ 8583 #define FW_DEVLOG_FMT_PARAMS_NUM 8 8584 8585 /* 8586 * priority levels 8587 */ 8588 enum fw_devlog_level { 8589 FW_DEVLOG_LEVEL_EMERG = 0x0, 8590 FW_DEVLOG_LEVEL_CRIT = 0x1, 8591 FW_DEVLOG_LEVEL_ERR = 0x2, 8592 FW_DEVLOG_LEVEL_NOTICE = 0x3, 8593 FW_DEVLOG_LEVEL_INFO = 0x4, 8594 FW_DEVLOG_LEVEL_DEBUG = 0x5, 8595 FW_DEVLOG_LEVEL_MAX = 0x5, 8596 }; 8597 8598 /* 8599 * facilities that may send a log message 8600 */ 8601 enum fw_devlog_facility { 8602 FW_DEVLOG_FACILITY_CORE = 0x00, 8603 FW_DEVLOG_FACILITY_CF = 0x01, 8604 FW_DEVLOG_FACILITY_SCHED = 0x02, 8605 FW_DEVLOG_FACILITY_TIMER = 0x04, 8606 FW_DEVLOG_FACILITY_RES = 0x06, 8607 FW_DEVLOG_FACILITY_HW = 0x08, 8608 FW_DEVLOG_FACILITY_FLR = 0x10, 8609 FW_DEVLOG_FACILITY_DMAQ = 0x12, 8610 FW_DEVLOG_FACILITY_PHY = 0x14, 8611 FW_DEVLOG_FACILITY_MAC = 0x16, 8612 FW_DEVLOG_FACILITY_PORT = 0x18, 8613 FW_DEVLOG_FACILITY_VI = 0x1A, 8614 FW_DEVLOG_FACILITY_FILTER = 0x1C, 8615 FW_DEVLOG_FACILITY_ACL = 0x1E, 8616 FW_DEVLOG_FACILITY_TM = 0x20, 8617 FW_DEVLOG_FACILITY_QFC = 0x22, 8618 FW_DEVLOG_FACILITY_DCB = 0x24, 8619 FW_DEVLOG_FACILITY_ETH = 0x26, 8620 FW_DEVLOG_FACILITY_OFLD = 0x28, 8621 FW_DEVLOG_FACILITY_RI = 0x2A, 8622 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 8623 FW_DEVLOG_FACILITY_FCOE = 0x2E, 8624 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 8625 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 8626 FW_DEVLOG_FACILITY_CHNET = 0x34, 8627 FW_DEVLOG_FACILITY_COISCSI = 0x36, 8628 FW_DEVLOG_FACILITY_MAX = 0x38, 8629 }; 8630 8631 /* 8632 * log message format 8633 */ 8634 struct fw_devlog_e { 8635 __be64 timestamp; 8636 __be32 seqno; 8637 __be16 reserved1; 8638 __u8 level; 8639 __u8 facility; 8640 __u8 fmt[FW_DEVLOG_FMT_LEN]; 8641 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 8642 __be32 reserved3[4]; 8643 }; 8644 8645 struct fw_devlog_cmd { 8646 __be32 op_to_write; 8647 __be32 retval_len16; 8648 __u8 level; 8649 __u8 r2[7]; 8650 __be32 memtype_devlog_memaddr16_devlog; 8651 __be32 memsize_devlog; 8652 __be32 r3[2]; 8653 }; 8654 8655 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 8656 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 8657 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8658 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8659 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8660 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8661 8662 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 8663 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 8664 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8665 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8666 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8667 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 8668 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8669 8670 enum fw_watchdog_actions { 8671 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 8672 FW_WATCHDOG_ACTION_FLR = 1, 8673 FW_WATCHDOG_ACTION_BYPASS = 2, 8674 FW_WATCHDOG_ACTION_TMPCHK = 3, 8675 FW_WATCHDOG_ACTION_PAUSEOFF = 4, 8676 8677 FW_WATCHDOG_ACTION_MAX = 5, 8678 }; 8679 8680 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 8681 8682 struct fw_watchdog_cmd { 8683 __be32 op_to_vfn; 8684 __be32 retval_len16; 8685 __be32 timeout; 8686 __be32 action; 8687 }; 8688 8689 #define S_FW_WATCHDOG_CMD_PFN 8 8690 #define M_FW_WATCHDOG_CMD_PFN 0x7 8691 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 8692 #define G_FW_WATCHDOG_CMD_PFN(x) \ 8693 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 8694 8695 #define S_FW_WATCHDOG_CMD_VFN 0 8696 #define M_FW_WATCHDOG_CMD_VFN 0xff 8697 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 8698 #define G_FW_WATCHDOG_CMD_VFN(x) \ 8699 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 8700 8701 struct fw_clip_cmd { 8702 __be32 op_to_write; 8703 __be32 alloc_to_len16; 8704 __be64 ip_hi; 8705 __be64 ip_lo; 8706 __be32 r4[2]; 8707 }; 8708 8709 #define S_FW_CLIP_CMD_ALLOC 31 8710 #define M_FW_CLIP_CMD_ALLOC 0x1 8711 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 8712 #define G_FW_CLIP_CMD_ALLOC(x) \ 8713 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 8714 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 8715 8716 #define S_FW_CLIP_CMD_FREE 30 8717 #define M_FW_CLIP_CMD_FREE 0x1 8718 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 8719 #define G_FW_CLIP_CMD_FREE(x) \ 8720 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 8721 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 8722 8723 #define S_FW_CLIP_CMD_INDEX 16 8724 #define M_FW_CLIP_CMD_INDEX 0x1fff 8725 #define V_FW_CLIP_CMD_INDEX(x) ((x) << S_FW_CLIP_CMD_INDEX) 8726 #define G_FW_CLIP_CMD_INDEX(x) \ 8727 (((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX) 8728 8729 /****************************************************************************** 8730 * F O i S C S I C O M M A N D s 8731 **************************************/ 8732 8733 #define FW_CHNET_IFACE_ADDR_MAX 3 8734 8735 enum fw_chnet_iface_cmd_subop { 8736 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 8737 8738 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 8739 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 8740 8741 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 8742 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 8743 8744 FW_CHNET_IFACE_CMD_SUBOP_MAX, 8745 }; 8746 8747 struct fw_chnet_iface_cmd { 8748 __be32 op_to_portid; 8749 __be32 retval_len16; 8750 __u8 subop; 8751 __u8 r2[2]; 8752 __u8 flags; 8753 __be32 ifid_ifstate; 8754 __be16 mtu; 8755 __be16 vlanid; 8756 __be32 r3; 8757 __be16 r4; 8758 __u8 mac[6]; 8759 }; 8760 8761 #define S_FW_CHNET_IFACE_CMD_PORTID 0 8762 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 8763 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 8764 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 8765 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 8766 8767 #define S_FW_CHNET_IFACE_CMD_RSS_IQID 16 8768 #define M_FW_CHNET_IFACE_CMD_RSS_IQID 0xffff 8769 #define V_FW_CHNET_IFACE_CMD_RSS_IQID(x) \ 8770 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID) 8771 #define G_FW_CHNET_IFACE_CMD_RSS_IQID(x) \ 8772 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID) & M_FW_CHNET_IFACE_CMD_RSS_IQID) 8773 8774 #define S_FW_CHNET_IFACE_CMD_RSS_IQID_F 0 8775 #define M_FW_CHNET_IFACE_CMD_RSS_IQID_F 0x1 8776 #define V_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \ 8777 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID_F) 8778 #define G_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \ 8779 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID_F) & \ 8780 M_FW_CHNET_IFACE_CMD_RSS_IQID_F) 8781 #define F_FW_CHNET_IFACE_CMD_RSS_IQID_F V_FW_CHNET_IFACE_CMD_RSS_IQID_F(1U) 8782 8783 #define S_FW_CHNET_IFACE_CMD_IFID 8 8784 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 8785 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 8786 #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 8787 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 8788 8789 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 8790 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 8791 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 8792 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 8793 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 8794 8795 struct fw_fcoe_res_info_cmd { 8796 __be32 op_to_read; 8797 __be32 retval_len16; 8798 __be16 e_d_tov; 8799 __be16 r_a_tov_seq; 8800 __be16 r_a_tov_els; 8801 __be16 r_r_tov; 8802 __be32 max_xchgs; 8803 __be32 max_ssns; 8804 __be32 used_xchgs; 8805 __be32 used_ssns; 8806 __be32 max_fcfs; 8807 __be32 max_vnps; 8808 __be32 used_fcfs; 8809 __be32 used_vnps; 8810 }; 8811 8812 struct fw_fcoe_link_cmd { 8813 __be32 op_to_portid; 8814 __be32 retval_len16; 8815 __be32 sub_opcode_fcfi; 8816 __u8 r3; 8817 __u8 lstatus; 8818 __be16 flags; 8819 __u8 r4; 8820 __u8 set_vlan; 8821 __be16 vlan_id; 8822 __be32 vnpi_pkd; 8823 __be16 r6; 8824 __u8 phy_mac[6]; 8825 __u8 vnport_wwnn[8]; 8826 __u8 vnport_wwpn[8]; 8827 }; 8828 8829 #define S_FW_FCOE_LINK_CMD_PORTID 0 8830 #define M_FW_FCOE_LINK_CMD_PORTID 0xf 8831 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 8832 #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 8833 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 8834 8835 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 8836 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 8837 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 8838 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 8839 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 8840 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 8841 8842 #define S_FW_FCOE_LINK_CMD_FCFI 0 8843 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 8844 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 8845 #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 8846 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 8847 8848 #define S_FW_FCOE_LINK_CMD_VNPI 0 8849 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 8850 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 8851 #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 8852 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 8853 8854 struct fw_fcoe_vnp_cmd { 8855 __be32 op_to_fcfi; 8856 __be32 alloc_to_len16; 8857 __be32 gen_wwn_to_vnpi; 8858 __be32 vf_id; 8859 __be16 iqid; 8860 __u8 vnport_mac[6]; 8861 __u8 vnport_wwnn[8]; 8862 __u8 vnport_wwpn[8]; 8863 __u8 cmn_srv_parms[16]; 8864 __u8 clsp_word_0_1[8]; 8865 }; 8866 8867 #define S_FW_FCOE_VNP_CMD_FCFI 0 8868 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 8869 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 8870 #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 8871 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 8872 8873 #define S_FW_FCOE_VNP_CMD_ALLOC 31 8874 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 8875 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 8876 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 8877 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 8878 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 8879 8880 #define S_FW_FCOE_VNP_CMD_FREE 30 8881 #define M_FW_FCOE_VNP_CMD_FREE 0x1 8882 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 8883 #define G_FW_FCOE_VNP_CMD_FREE(x) \ 8884 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 8885 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 8886 8887 #define S_FW_FCOE_VNP_CMD_MODIFY 29 8888 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 8889 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 8890 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 8891 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 8892 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 8893 8894 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 8895 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 8896 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 8897 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 8898 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 8899 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 8900 8901 #define S_FW_FCOE_VNP_CMD_PERSIST 21 8902 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 8903 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 8904 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 8905 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 8906 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 8907 8908 #define S_FW_FCOE_VNP_CMD_VFID_EN 20 8909 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 8910 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 8911 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 8912 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 8913 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 8914 8915 #define S_FW_FCOE_VNP_CMD_VNPI 0 8916 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 8917 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 8918 #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 8919 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 8920 8921 struct fw_fcoe_sparams_cmd { 8922 __be32 op_to_portid; 8923 __be32 retval_len16; 8924 __u8 r3[7]; 8925 __u8 cos; 8926 __u8 lport_wwnn[8]; 8927 __u8 lport_wwpn[8]; 8928 __u8 cmn_srv_parms[16]; 8929 __u8 cls_srv_parms[16]; 8930 }; 8931 8932 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 8933 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 8934 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 8935 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 8936 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 8937 8938 struct fw_fcoe_stats_cmd { 8939 __be32 op_to_flowid; 8940 __be32 free_to_len16; 8941 union fw_fcoe_stats { 8942 struct fw_fcoe_stats_ctl { 8943 __u8 nstats_port; 8944 __u8 port_valid_ix; 8945 __be16 r6; 8946 __be32 r7; 8947 __be64 stat0; 8948 __be64 stat1; 8949 __be64 stat2; 8950 __be64 stat3; 8951 __be64 stat4; 8952 __be64 stat5; 8953 } ctl; 8954 struct fw_fcoe_port_stats { 8955 __be64 tx_bcast_bytes; 8956 __be64 tx_bcast_frames; 8957 __be64 tx_mcast_bytes; 8958 __be64 tx_mcast_frames; 8959 __be64 tx_ucast_bytes; 8960 __be64 tx_ucast_frames; 8961 __be64 tx_drop_frames; 8962 __be64 tx_offload_bytes; 8963 __be64 tx_offload_frames; 8964 __be64 rx_bcast_bytes; 8965 __be64 rx_bcast_frames; 8966 __be64 rx_mcast_bytes; 8967 __be64 rx_mcast_frames; 8968 __be64 rx_ucast_bytes; 8969 __be64 rx_ucast_frames; 8970 __be64 rx_err_frames; 8971 } port_stats; 8972 struct fw_fcoe_fcf_stats { 8973 __be32 fip_tx_bytes; 8974 __be32 fip_tx_fr; 8975 __be64 fcf_ka; 8976 __be64 mcast_adv_rcvd; 8977 __be16 ucast_adv_rcvd; 8978 __be16 sol_sent; 8979 __be16 vlan_req; 8980 __be16 vlan_rpl; 8981 __be16 clr_vlink; 8982 __be16 link_down; 8983 __be16 link_up; 8984 __be16 logo; 8985 __be16 flogi_req; 8986 __be16 flogi_rpl; 8987 __be16 fdisc_req; 8988 __be16 fdisc_rpl; 8989 __be16 fka_prd_chg; 8990 __be16 fc_map_chg; 8991 __be16 vfid_chg; 8992 __u8 no_fka_req; 8993 __u8 no_vnp; 8994 } fcf_stats; 8995 struct fw_fcoe_pcb_stats { 8996 __be64 tx_bytes; 8997 __be64 tx_frames; 8998 __be64 rx_bytes; 8999 __be64 rx_frames; 9000 __be32 vnp_ka; 9001 __be32 unsol_els_rcvd; 9002 __be64 unsol_cmd_rcvd; 9003 __be16 implicit_logo; 9004 __be16 flogi_inv_sparm; 9005 __be16 fdisc_inv_sparm; 9006 __be16 flogi_rjt; 9007 __be16 fdisc_rjt; 9008 __be16 no_ssn; 9009 __be16 mac_flt_fail; 9010 __be16 inv_fr_rcvd; 9011 } pcb_stats; 9012 struct fw_fcoe_scb_stats { 9013 __be64 tx_bytes; 9014 __be64 tx_frames; 9015 __be64 rx_bytes; 9016 __be64 rx_frames; 9017 __be32 host_abrt_req; 9018 __be32 adap_auto_abrt; 9019 __be32 adap_abrt_rsp; 9020 __be32 host_ios_req; 9021 __be16 ssn_offl_ios; 9022 __be16 ssn_not_rdy_ios; 9023 __u8 rx_data_ddp_err; 9024 __u8 ddp_flt_set_err; 9025 __be16 rx_data_fr_err; 9026 __u8 bad_st_abrt_req; 9027 __u8 no_io_abrt_req; 9028 __u8 abort_tmo; 9029 __u8 abort_tmo_2; 9030 __be32 abort_req; 9031 __u8 no_ppod_res_tmo; 9032 __u8 bp_tmo; 9033 __u8 adap_auto_cls; 9034 __u8 no_io_cls_req; 9035 __be32 host_cls_req; 9036 __be64 unsol_cmd_rcvd; 9037 __be32 plogi_req_rcvd; 9038 __be32 prli_req_rcvd; 9039 __be16 logo_req_rcvd; 9040 __be16 prlo_req_rcvd; 9041 __be16 plogi_rjt_rcvd; 9042 __be16 prli_rjt_rcvd; 9043 __be32 adisc_req_rcvd; 9044 __be32 rscn_rcvd; 9045 __be32 rrq_req_rcvd; 9046 __be32 unsol_els_rcvd; 9047 __u8 adisc_rjt_rcvd; 9048 __u8 scr_rjt; 9049 __u8 ct_rjt; 9050 __u8 inval_bls_rcvd; 9051 __be32 ba_rjt_rcvd; 9052 } scb_stats; 9053 } u; 9054 }; 9055 9056 #define S_FW_FCOE_STATS_CMD_FLOWID 0 9057 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 9058 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 9059 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 9060 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 9061 9062 #define S_FW_FCOE_STATS_CMD_FREE 30 9063 #define M_FW_FCOE_STATS_CMD_FREE 0x1 9064 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 9065 #define G_FW_FCOE_STATS_CMD_FREE(x) \ 9066 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 9067 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 9068 9069 #define S_FW_FCOE_STATS_CMD_NSTATS 4 9070 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 9071 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 9072 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 9073 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 9074 9075 #define S_FW_FCOE_STATS_CMD_PORT 0 9076 #define M_FW_FCOE_STATS_CMD_PORT 0x3 9077 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 9078 #define G_FW_FCOE_STATS_CMD_PORT(x) \ 9079 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 9080 9081 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 9082 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 9083 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 9084 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 9085 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 9086 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 9087 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 9088 9089 #define S_FW_FCOE_STATS_CMD_IX 0 9090 #define M_FW_FCOE_STATS_CMD_IX 0x3f 9091 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 9092 #define G_FW_FCOE_STATS_CMD_IX(x) \ 9093 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 9094 9095 struct fw_fcoe_fcf_cmd { 9096 __be32 op_to_fcfi; 9097 __be32 retval_len16; 9098 __be16 priority_pkd; 9099 __u8 mac[6]; 9100 __u8 name_id[8]; 9101 __u8 fabric[8]; 9102 __be16 vf_id; 9103 __be16 max_fcoe_size; 9104 __u8 vlan_id; 9105 __u8 fc_map[3]; 9106 __be32 fka_adv; 9107 __be32 r6; 9108 __u8 r7_hi; 9109 __u8 fpma_to_portid; 9110 __u8 spma_mac[6]; 9111 __be64 r8; 9112 }; 9113 9114 #define S_FW_FCOE_FCF_CMD_FCFI 0 9115 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 9116 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 9117 #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 9118 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 9119 9120 #define S_FW_FCOE_FCF_CMD_PRIORITY 0 9121 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 9122 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 9123 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 9124 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 9125 9126 #define S_FW_FCOE_FCF_CMD_FPMA 6 9127 #define M_FW_FCOE_FCF_CMD_FPMA 0x1 9128 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 9129 #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 9130 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 9131 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 9132 9133 #define S_FW_FCOE_FCF_CMD_SPMA 5 9134 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 9135 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 9136 #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 9137 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 9138 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 9139 9140 #define S_FW_FCOE_FCF_CMD_LOGIN 4 9141 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 9142 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 9143 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 9144 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 9145 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 9146 9147 #define S_FW_FCOE_FCF_CMD_PORTID 0 9148 #define M_FW_FCOE_FCF_CMD_PORTID 0xf 9149 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 9150 #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 9151 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 9152 9153 /****************************************************************************** 9154 * E R R O R a n d D E B U G C O M M A N D s 9155 ******************************************************/ 9156 9157 enum fw_error_type { 9158 FW_ERROR_TYPE_EXCEPTION = 0x0, 9159 FW_ERROR_TYPE_HWMODULE = 0x1, 9160 FW_ERROR_TYPE_WR = 0x2, 9161 FW_ERROR_TYPE_ACL = 0x3, 9162 }; 9163 9164 enum fw_dcb_ieee_locations { 9165 FW_IEEE_LOC_LOCAL, 9166 FW_IEEE_LOC_PEER, 9167 FW_IEEE_LOC_OPERATIONAL, 9168 }; 9169 9170 struct fw_dcb_ieee_cmd { 9171 __be32 op_to_location; 9172 __be32 changed_to_len16; 9173 union fw_dcbx_stats { 9174 struct fw_dcbx_pfc_stats_ieee { 9175 __be32 pfc_mbc_pkd; 9176 __be32 pfc_willing_to_pfc_en; 9177 } dcbx_pfc_stats; 9178 struct fw_dcbx_ets_stats_ieee { 9179 __be32 cbs_to_ets_max_tc; 9180 __be32 pg_table; 9181 __u8 pg_percent[8]; 9182 __u8 tsa[8]; 9183 } dcbx_ets_stats; 9184 struct fw_dcbx_app_stats_ieee { 9185 __be32 num_apps_pkd; 9186 __be32 r6; 9187 __be32 app[4]; 9188 } dcbx_app_stats; 9189 struct fw_dcbx_control { 9190 __be32 multi_peer_invalidated; 9191 __u8 version; 9192 __u8 r6[3]; 9193 } dcbx_control; 9194 } u; 9195 }; 9196 9197 #define S_FW_DCB_IEEE_CMD_PORT 8 9198 #define M_FW_DCB_IEEE_CMD_PORT 0x7 9199 #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT) 9200 #define G_FW_DCB_IEEE_CMD_PORT(x) \ 9201 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT) 9202 9203 #define S_FW_DCB_IEEE_CMD_FEATURE 2 9204 #define M_FW_DCB_IEEE_CMD_FEATURE 0x7 9205 #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE) 9206 #define G_FW_DCB_IEEE_CMD_FEATURE(x) \ 9207 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE) 9208 9209 #define S_FW_DCB_IEEE_CMD_LOCATION 0 9210 #define M_FW_DCB_IEEE_CMD_LOCATION 0x3 9211 #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION) 9212 #define G_FW_DCB_IEEE_CMD_LOCATION(x) \ 9213 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION) 9214 9215 #define S_FW_DCB_IEEE_CMD_CHANGED 20 9216 #define M_FW_DCB_IEEE_CMD_CHANGED 0x1 9217 #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED) 9218 #define G_FW_DCB_IEEE_CMD_CHANGED(x) \ 9219 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED) 9220 #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U) 9221 9222 #define S_FW_DCB_IEEE_CMD_RECEIVED 19 9223 #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1 9224 #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED) 9225 #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \ 9226 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED) 9227 #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U) 9228 9229 #define S_FW_DCB_IEEE_CMD_APPLY 18 9230 #define M_FW_DCB_IEEE_CMD_APPLY 0x1 9231 #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY) 9232 #define G_FW_DCB_IEEE_CMD_APPLY(x) \ 9233 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY) 9234 #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U) 9235 9236 #define S_FW_DCB_IEEE_CMD_DISABLED 17 9237 #define M_FW_DCB_IEEE_CMD_DISABLED 0x1 9238 #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED) 9239 #define G_FW_DCB_IEEE_CMD_DISABLED(x) \ 9240 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED) 9241 #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U) 9242 9243 #define S_FW_DCB_IEEE_CMD_MORE 16 9244 #define M_FW_DCB_IEEE_CMD_MORE 0x1 9245 #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE) 9246 #define G_FW_DCB_IEEE_CMD_MORE(x) \ 9247 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE) 9248 #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U) 9249 9250 #define S_FW_DCB_IEEE_CMD_PFC_MBC 0 9251 #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1 9252 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC) 9253 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \ 9254 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC) 9255 #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U) 9256 9257 #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16 9258 #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1 9259 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 9260 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING) 9261 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 9262 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING) 9263 #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U) 9264 9265 #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8 9266 #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff 9267 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC) 9268 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \ 9269 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC) 9270 9271 #define S_FW_DCB_IEEE_CMD_PFC_EN 0 9272 #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff 9273 #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN) 9274 #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \ 9275 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN) 9276 9277 #define S_FW_DCB_IEEE_CMD_CBS 16 9278 #define M_FW_DCB_IEEE_CMD_CBS 0x1 9279 #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS) 9280 #define G_FW_DCB_IEEE_CMD_CBS(x) \ 9281 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS) 9282 #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U) 9283 9284 #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8 9285 #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1 9286 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 9287 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING) 9288 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 9289 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING) 9290 #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U) 9291 9292 #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0 9293 #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff 9294 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC) 9295 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \ 9296 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC) 9297 9298 #define S_FW_DCB_IEEE_CMD_NUM_APPS 0 9299 #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7 9300 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS) 9301 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \ 9302 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS) 9303 9304 #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31 9305 #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1 9306 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER) 9307 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \ 9308 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER) 9309 #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U) 9310 9311 #define S_FW_DCB_IEEE_CMD_INVALIDATED 30 9312 #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1 9313 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9314 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED) 9315 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9316 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED) 9317 #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U) 9318 9319 /* Hand-written */ 9320 #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16 9321 #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff 9322 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9323 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \ 9324 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9325 9326 #define S_FW_DCB_IEEE_CMD_APP_SELECT 3 9327 #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7 9328 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT) 9329 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \ 9330 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT) 9331 9332 #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0 9333 #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7 9334 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY) 9335 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \ 9336 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY) 9337 9338 9339 struct fw_error_cmd { 9340 __be32 op_to_type; 9341 __be32 len16_pkd; 9342 union fw_error { 9343 struct fw_error_exception { 9344 __be32 info[6]; 9345 } exception; 9346 struct fw_error_hwmodule { 9347 __be32 regaddr; 9348 __be32 regval; 9349 } hwmodule; 9350 struct fw_error_wr { 9351 __be16 cidx; 9352 __be16 pfn_vfn; 9353 __be32 eqid; 9354 __u8 wrhdr[16]; 9355 } wr; 9356 struct fw_error_acl { 9357 __be16 cidx; 9358 __be16 pfn_vfn; 9359 __be32 eqid; 9360 __be16 mv_pkd; 9361 __u8 val[6]; 9362 __be64 r4; 9363 } acl; 9364 } u; 9365 }; 9366 9367 #define S_FW_ERROR_CMD_FATAL 4 9368 #define M_FW_ERROR_CMD_FATAL 0x1 9369 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 9370 #define G_FW_ERROR_CMD_FATAL(x) \ 9371 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 9372 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 9373 9374 #define S_FW_ERROR_CMD_TYPE 0 9375 #define M_FW_ERROR_CMD_TYPE 0xf 9376 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 9377 #define G_FW_ERROR_CMD_TYPE(x) \ 9378 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 9379 9380 #define S_FW_ERROR_CMD_PFN 8 9381 #define M_FW_ERROR_CMD_PFN 0x7 9382 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9383 #define G_FW_ERROR_CMD_PFN(x) \ 9384 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9385 9386 #define S_FW_ERROR_CMD_VFN 0 9387 #define M_FW_ERROR_CMD_VFN 0xff 9388 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9389 #define G_FW_ERROR_CMD_VFN(x) \ 9390 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9391 9392 #define S_FW_ERROR_CMD_PFN 8 9393 #define M_FW_ERROR_CMD_PFN 0x7 9394 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9395 #define G_FW_ERROR_CMD_PFN(x) \ 9396 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9397 9398 #define S_FW_ERROR_CMD_VFN 0 9399 #define M_FW_ERROR_CMD_VFN 0xff 9400 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9401 #define G_FW_ERROR_CMD_VFN(x) \ 9402 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9403 9404 #define S_FW_ERROR_CMD_MV 15 9405 #define M_FW_ERROR_CMD_MV 0x1 9406 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 9407 #define G_FW_ERROR_CMD_MV(x) \ 9408 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 9409 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 9410 9411 struct fw_debug_cmd { 9412 __be32 op_type; 9413 __be32 len16_pkd; 9414 union fw_debug { 9415 struct fw_debug_assert { 9416 __be32 fcid; 9417 __be32 line; 9418 __be32 x; 9419 __be32 y; 9420 __u8 filename_0_7[8]; 9421 __u8 filename_8_15[8]; 9422 __be64 r3; 9423 } assert; 9424 struct fw_debug_prt { 9425 __be16 dprtstridx; 9426 __be16 r3[3]; 9427 __be32 dprtstrparam0; 9428 __be32 dprtstrparam1; 9429 __be32 dprtstrparam2; 9430 __be32 dprtstrparam3; 9431 } prt; 9432 } u; 9433 }; 9434 9435 #define S_FW_DEBUG_CMD_TYPE 0 9436 #define M_FW_DEBUG_CMD_TYPE 0xff 9437 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 9438 #define G_FW_DEBUG_CMD_TYPE(x) \ 9439 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 9440 9441 enum fw_diag_cmd_type { 9442 FW_DIAG_CMD_TYPE_OFLDIAG = 0, 9443 }; 9444 9445 enum fw_diag_cmd_ofldiag_op { 9446 FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0, 9447 FW_DIAG_CMD_OFLDIAG_TEST_START, 9448 FW_DIAG_CMD_OFLDIAG_TEST_STOP, 9449 FW_DIAG_CMD_OFLDIAG_TEST_STATUS, 9450 }; 9451 9452 enum fw_diag_cmd_ofldiag_status { 9453 FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0, 9454 FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING, 9455 FW_DIAG_CMD_OFLDIAG_STATUS_FAILED, 9456 FW_DIAG_CMD_OFLDIAG_STATUS_PASSED, 9457 }; 9458 9459 struct fw_diag_cmd { 9460 __be32 op_type; 9461 __be32 len16_pkd; 9462 union fw_diag_test { 9463 struct fw_diag_test_ofldiag { 9464 __u8 test_op; 9465 __u8 r3; 9466 __be16 test_status; 9467 __be32 duration; 9468 } ofldiag; 9469 } u; 9470 }; 9471 9472 #define S_FW_DIAG_CMD_TYPE 0 9473 #define M_FW_DIAG_CMD_TYPE 0xff 9474 #define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE) 9475 #define G_FW_DIAG_CMD_TYPE(x) \ 9476 (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE) 9477 9478 struct fw_hma_cmd { 9479 __be32 op_pkd; 9480 __be32 retval_len16; 9481 __be32 mode_to_pcie_params; 9482 __be32 naddr_size; 9483 __be32 addr_size_pkd; 9484 __be32 r6; 9485 __be64 phy_address[5]; 9486 }; 9487 9488 #define S_FW_HMA_CMD_MODE 31 9489 #define M_FW_HMA_CMD_MODE 0x1 9490 #define V_FW_HMA_CMD_MODE(x) ((x) << S_FW_HMA_CMD_MODE) 9491 #define G_FW_HMA_CMD_MODE(x) \ 9492 (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE) 9493 #define F_FW_HMA_CMD_MODE V_FW_HMA_CMD_MODE(1U) 9494 9495 #define S_FW_HMA_CMD_SOC 30 9496 #define M_FW_HMA_CMD_SOC 0x1 9497 #define V_FW_HMA_CMD_SOC(x) ((x) << S_FW_HMA_CMD_SOC) 9498 #define G_FW_HMA_CMD_SOC(x) (((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC) 9499 #define F_FW_HMA_CMD_SOC V_FW_HMA_CMD_SOC(1U) 9500 9501 #define S_FW_HMA_CMD_EOC 29 9502 #define M_FW_HMA_CMD_EOC 0x1 9503 #define V_FW_HMA_CMD_EOC(x) ((x) << S_FW_HMA_CMD_EOC) 9504 #define G_FW_HMA_CMD_EOC(x) (((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC) 9505 #define F_FW_HMA_CMD_EOC V_FW_HMA_CMD_EOC(1U) 9506 9507 #define S_FW_HMA_CMD_PCIE_PARAMS 0 9508 #define M_FW_HMA_CMD_PCIE_PARAMS 0x7ffffff 9509 #define V_FW_HMA_CMD_PCIE_PARAMS(x) ((x) << S_FW_HMA_CMD_PCIE_PARAMS) 9510 #define G_FW_HMA_CMD_PCIE_PARAMS(x) \ 9511 (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS) 9512 9513 #define S_FW_HMA_CMD_NADDR 12 9514 #define M_FW_HMA_CMD_NADDR 0x3f 9515 #define V_FW_HMA_CMD_NADDR(x) ((x) << S_FW_HMA_CMD_NADDR) 9516 #define G_FW_HMA_CMD_NADDR(x) \ 9517 (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR) 9518 9519 #define S_FW_HMA_CMD_SIZE 0 9520 #define M_FW_HMA_CMD_SIZE 0xfff 9521 #define V_FW_HMA_CMD_SIZE(x) ((x) << S_FW_HMA_CMD_SIZE) 9522 #define G_FW_HMA_CMD_SIZE(x) \ 9523 (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE) 9524 9525 #define S_FW_HMA_CMD_ADDR_SIZE 11 9526 #define M_FW_HMA_CMD_ADDR_SIZE 0x1fffff 9527 #define V_FW_HMA_CMD_ADDR_SIZE(x) ((x) << S_FW_HMA_CMD_ADDR_SIZE) 9528 #define G_FW_HMA_CMD_ADDR_SIZE(x) \ 9529 (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE) 9530 9531 /****************************************************************************** 9532 * P C I E F W R E G I S T E R 9533 **************************************/ 9534 9535 enum pcie_fw_eval { 9536 PCIE_FW_EVAL_CRASH = 0, 9537 PCIE_FW_EVAL_PREP = 1, 9538 PCIE_FW_EVAL_CONF = 2, 9539 PCIE_FW_EVAL_INIT = 3, 9540 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 9541 PCIE_FW_EVAL_OVERHEAT = 5, 9542 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 9543 }; 9544 9545 /** 9546 * Register definitions for the PCIE_FW register which the firmware uses 9547 * to retain status across RESETs. This register should be considered 9548 * as a READ-ONLY register for Host Software and only to be used to 9549 * track firmware initialization/error state, etc. 9550 */ 9551 #define S_PCIE_FW_ERR 31 9552 #define M_PCIE_FW_ERR 0x1 9553 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 9554 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 9555 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 9556 9557 #define S_PCIE_FW_INIT 30 9558 #define M_PCIE_FW_INIT 0x1 9559 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 9560 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 9561 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 9562 9563 #define S_PCIE_FW_HALT 29 9564 #define M_PCIE_FW_HALT 0x1 9565 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 9566 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 9567 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 9568 9569 #define S_PCIE_FW_EVAL 24 9570 #define M_PCIE_FW_EVAL 0x7 9571 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 9572 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 9573 9574 #define S_PCIE_FW_STAGE 21 9575 #define M_PCIE_FW_STAGE 0x7 9576 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 9577 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 9578 9579 #define S_PCIE_FW_ASYNCNOT_VLD 20 9580 #define M_PCIE_FW_ASYNCNOT_VLD 0x1 9581 #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 9582 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 9583 #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 9584 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 9585 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 9586 9587 #define S_PCIE_FW_ASYNCNOTINT 19 9588 #define M_PCIE_FW_ASYNCNOTINT 0x1 9589 #define V_PCIE_FW_ASYNCNOTINT(x) \ 9590 ((x) << S_PCIE_FW_ASYNCNOTINT) 9591 #define G_PCIE_FW_ASYNCNOTINT(x) \ 9592 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 9593 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 9594 9595 #define S_PCIE_FW_ASYNCNOT 16 9596 #define M_PCIE_FW_ASYNCNOT 0x7 9597 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 9598 #define G_PCIE_FW_ASYNCNOT(x) \ 9599 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 9600 9601 #define S_PCIE_FW_MASTER_VLD 15 9602 #define M_PCIE_FW_MASTER_VLD 0x1 9603 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 9604 #define G_PCIE_FW_MASTER_VLD(x) \ 9605 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 9606 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 9607 9608 #define S_PCIE_FW_MASTER 12 9609 #define M_PCIE_FW_MASTER 0x7 9610 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 9611 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 9612 9613 #define S_PCIE_FW_RESET_VLD 11 9614 #define M_PCIE_FW_RESET_VLD 0x1 9615 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 9616 #define G_PCIE_FW_RESET_VLD(x) \ 9617 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 9618 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 9619 9620 #define S_PCIE_FW_RESET 8 9621 #define M_PCIE_FW_RESET 0x7 9622 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 9623 #define G_PCIE_FW_RESET(x) \ 9624 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 9625 9626 #define S_PCIE_FW_REGISTERED 0 9627 #define M_PCIE_FW_REGISTERED 0xff 9628 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 9629 #define G_PCIE_FW_REGISTERED(x) \ 9630 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 9631 9632 9633 /****************************************************************************** 9634 * P C I E F W P F 0 R E G I S T E R 9635 **********************************************/ 9636 9637 /* 9638 * this register is available as 32-bit of persistent storage (across 9639 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 9640 * will not write it) 9641 */ 9642 9643 9644 /****************************************************************************** 9645 * P C I E F W P F 7 R E G I S T E R 9646 **********************************************/ 9647 9648 /* 9649 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to 9650 * access the "devlog" which needing to contact firmware. The encoding is 9651 * mostly the same as that returned by the DEVLOG command except for the size 9652 * which is encoded as the number of entries in multiples-1 of 128 here rather 9653 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 9654 * and 15 means 2048. This of course in turn constrains the allowed values 9655 * for the devlog size ... 9656 */ 9657 #define PCIE_FW_PF_DEVLOG 7 9658 9659 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 9660 #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf 9661 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9662 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) 9663 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9664 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ 9665 M_PCIE_FW_PF_DEVLOG_NENTRIES128) 9666 9667 #define S_PCIE_FW_PF_DEVLOG_ADDR16 4 9668 #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff 9669 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) 9670 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ 9671 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) 9672 9673 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 9674 #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf 9675 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) 9676 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ 9677 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) 9678 9679 9680 /****************************************************************************** 9681 * B I N A R Y H E A D E R F O R M A T 9682 **********************************************/ 9683 9684 /* 9685 * firmware binary header format 9686 */ 9687 struct fw_hdr { 9688 __u8 ver; 9689 __u8 chip; /* terminator chip family */ 9690 __be16 len512; /* bin length in units of 512-bytes */ 9691 __be32 fw_ver; /* firmware version */ 9692 __be32 tp_microcode_ver; /* tcp processor microcode version */ 9693 __u8 intfver_nic; 9694 __u8 intfver_vnic; 9695 __u8 intfver_ofld; 9696 __u8 intfver_ri; 9697 __u8 intfver_iscsipdu; 9698 __u8 intfver_iscsi; 9699 __u8 intfver_fcoepdu; 9700 __u8 intfver_fcoe; 9701 __u32 reserved2; 9702 __u32 reserved3; 9703 __be32 magic; /* runtime or bootstrap fw */ 9704 __be32 flags; 9705 __be32 reserved6[23]; 9706 }; 9707 9708 enum fw_hdr_chip { 9709 FW_HDR_CHIP_T4, 9710 FW_HDR_CHIP_T5, 9711 FW_HDR_CHIP_T6 9712 }; 9713 9714 #define S_FW_HDR_FW_VER_MAJOR 24 9715 #define M_FW_HDR_FW_VER_MAJOR 0xff 9716 #define V_FW_HDR_FW_VER_MAJOR(x) \ 9717 ((x) << S_FW_HDR_FW_VER_MAJOR) 9718 #define G_FW_HDR_FW_VER_MAJOR(x) \ 9719 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 9720 9721 #define S_FW_HDR_FW_VER_MINOR 16 9722 #define M_FW_HDR_FW_VER_MINOR 0xff 9723 #define V_FW_HDR_FW_VER_MINOR(x) \ 9724 ((x) << S_FW_HDR_FW_VER_MINOR) 9725 #define G_FW_HDR_FW_VER_MINOR(x) \ 9726 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 9727 9728 #define S_FW_HDR_FW_VER_MICRO 8 9729 #define M_FW_HDR_FW_VER_MICRO 0xff 9730 #define V_FW_HDR_FW_VER_MICRO(x) \ 9731 ((x) << S_FW_HDR_FW_VER_MICRO) 9732 #define G_FW_HDR_FW_VER_MICRO(x) \ 9733 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 9734 9735 #define S_FW_HDR_FW_VER_BUILD 0 9736 #define M_FW_HDR_FW_VER_BUILD 0xff 9737 #define V_FW_HDR_FW_VER_BUILD(x) \ 9738 ((x) << S_FW_HDR_FW_VER_BUILD) 9739 #define G_FW_HDR_FW_VER_BUILD(x) \ 9740 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 9741 9742 enum { 9743 T4FW_VERSION_MAJOR = 0x01, 9744 T4FW_VERSION_MINOR = 0x13, 9745 T4FW_VERSION_MICRO = 0x01, 9746 T4FW_VERSION_BUILD = 0x00, 9747 9748 T5FW_VERSION_MAJOR = 0x01, 9749 T5FW_VERSION_MINOR = 0x13, 9750 T5FW_VERSION_MICRO = 0x01, 9751 T5FW_VERSION_BUILD = 0x00, 9752 9753 T6FW_VERSION_MAJOR = 0x01, 9754 T6FW_VERSION_MINOR = 0x13, 9755 T6FW_VERSION_MICRO = 0x01, 9756 T6FW_VERSION_BUILD = 0x00, 9757 }; 9758 9759 enum { 9760 /* T4 9761 */ 9762 T4FW_HDR_INTFVER_NIC = 0x00, 9763 T4FW_HDR_INTFVER_VNIC = 0x00, 9764 T4FW_HDR_INTFVER_OFLD = 0x00, 9765 T4FW_HDR_INTFVER_RI = 0x00, 9766 T4FW_HDR_INTFVER_ISCSIPDU= 0x00, 9767 T4FW_HDR_INTFVER_ISCSI = 0x00, 9768 T4FW_HDR_INTFVER_FCOEPDU = 0x00, 9769 T4FW_HDR_INTFVER_FCOE = 0x00, 9770 9771 /* T5 9772 */ 9773 T5FW_HDR_INTFVER_NIC = 0x00, 9774 T5FW_HDR_INTFVER_VNIC = 0x00, 9775 T5FW_HDR_INTFVER_OFLD = 0x00, 9776 T5FW_HDR_INTFVER_RI = 0x00, 9777 T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 9778 T5FW_HDR_INTFVER_ISCSI = 0x00, 9779 T5FW_HDR_INTFVER_FCOEPDU= 0x00, 9780 T5FW_HDR_INTFVER_FCOE = 0x00, 9781 9782 /* T6 9783 */ 9784 T6FW_HDR_INTFVER_NIC = 0x00, 9785 T6FW_HDR_INTFVER_VNIC = 0x00, 9786 T6FW_HDR_INTFVER_OFLD = 0x00, 9787 T6FW_HDR_INTFVER_RI = 0x00, 9788 T6FW_HDR_INTFVER_ISCSIPDU= 0x00, 9789 T6FW_HDR_INTFVER_ISCSI = 0x00, 9790 T6FW_HDR_INTFVER_FCOEPDU= 0x00, 9791 T6FW_HDR_INTFVER_FCOE = 0x00, 9792 }; 9793 9794 enum { 9795 FW_HDR_MAGIC_RUNTIME = 0x00000000, 9796 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 9797 }; 9798 9799 enum fw_hdr_flags { 9800 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 9801 }; 9802 9803 /* 9804 * External PHY firmware binary header format 9805 */ 9806 struct fw_ephy_hdr { 9807 __u8 ver; 9808 __u8 reserved; 9809 __be16 len512; /* bin length in units of 512-bytes */ 9810 __be32 magic; 9811 9812 __be16 vendor_id; 9813 __be16 device_id; 9814 __be32 version; 9815 9816 __be32 reserved1[4]; 9817 }; 9818 9819 enum { 9820 FW_EPHY_HDR_MAGIC = 0x65706879, 9821 }; 9822 9823 struct fw_ifconf_dhcp_info { 9824 __be32 addr; 9825 __be32 mask; 9826 __be16 vlanid; 9827 __be16 mtu; 9828 __be32 gw; 9829 __u8 op; 9830 __u8 len; 9831 __u8 data[270]; 9832 }; 9833 9834 #endif /* _T4FW_INTERFACE_H_ */ 9835