1 /*- 2 * Copyright (c) 2012-2016 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _T4FW_INTERFACE_H_ 31 #define _T4FW_INTERFACE_H_ 32 33 /****************************************************************************** 34 * R E T U R N V A L U E S 35 ********************************/ 36 37 enum fw_retval { 38 FW_SUCCESS = 0, /* completed successfully */ 39 FW_EPERM = 1, /* operation not permitted */ 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ 48 FW_ENODEV = 19, /* no such device */ 49 FW_EINVAL = 22, /* invalid argument */ 50 FW_ENOSPC = 28, /* no space left on device */ 51 FW_ENOSYS = 38, /* functionality not implemented */ 52 FW_ENODATA = 61, /* no data available */ 53 FW_EPROTO = 71, /* protocol error */ 54 FW_EADDRINUSE = 98, /* address already in use */ 55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 56 FW_ENETDOWN = 100, /* network is down */ 57 FW_ENETUNREACH = 101, /* network is unreachable */ 58 FW_ENOBUFS = 105, /* no buffer space available */ 59 FW_ETIMEDOUT = 110, /* timeout */ 60 FW_EINPROGRESS = 115, /* fw internal */ 61 FW_SCSI_ABORT_REQUESTED = 128, /* */ 62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 63 FW_SCSI_ABORTED = 130, /* */ 64 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 65 FW_ERR_LINK_DOWN = 132, /* */ 66 FW_RDEV_NOT_READY = 133, /* */ 67 FW_ERR_RDEV_LOST = 134, /* */ 68 FW_ERR_RDEV_LOGO = 135, /* */ 69 FW_FCOE_NO_XCHG = 136, /* */ 70 FW_SCSI_RSP_ERR = 137, /* */ 71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 73 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 74 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 76 }; 77 78 /****************************************************************************** 79 * M E M O R Y T Y P E s 80 ******************************/ 81 82 enum fw_memtype { 83 FW_MEMTYPE_EDC0 = 0x0, 84 FW_MEMTYPE_EDC1 = 0x1, 85 FW_MEMTYPE_EXTMEM = 0x2, 86 FW_MEMTYPE_FLASH = 0x4, 87 FW_MEMTYPE_INTERNAL = 0x5, 88 FW_MEMTYPE_EXTMEM1 = 0x6, 89 }; 90 91 /****************************************************************************** 92 * W O R K R E Q U E S T s 93 ********************************/ 94 95 enum fw_wr_opcodes { 96 FW_FRAG_WR = 0x1d, 97 FW_FILTER_WR = 0x02, 98 FW_ULPTX_WR = 0x04, 99 FW_TP_WR = 0x05, 100 FW_ETH_TX_PKT_WR = 0x08, 101 FW_ETH_TX_PKT2_WR = 0x44, 102 FW_ETH_TX_PKTS_WR = 0x09, 103 FW_ETH_TX_EO_WR = 0x1c, 104 FW_EQ_FLUSH_WR = 0x1b, 105 FW_OFLD_CONNECTION_WR = 0x2f, 106 FW_FLOWC_WR = 0x0a, 107 FW_OFLD_TX_DATA_WR = 0x0b, 108 FW_CMD_WR = 0x10, 109 FW_ETH_TX_PKT_VM_WR = 0x11, 110 FW_RI_RES_WR = 0x0c, 111 FW_RI_RDMA_WRITE_WR = 0x14, 112 FW_RI_SEND_WR = 0x15, 113 FW_RI_RDMA_READ_WR = 0x16, 114 FW_RI_RECV_WR = 0x17, 115 FW_RI_BIND_MW_WR = 0x18, 116 FW_RI_FR_NSMR_WR = 0x19, 117 FW_RI_INV_LSTAG_WR = 0x1a, 118 FW_RI_SEND_IMMEDIATE_WR = 0x15, 119 FW_RI_ATOMIC_WR = 0x16, 120 FW_RI_WR = 0x0d, 121 FW_CHNET_IFCONF_WR = 0x6b, 122 FW_RDEV_WR = 0x38, 123 FW_FOISCSI_NODE_WR = 0x60, 124 FW_FOISCSI_CTRL_WR = 0x6a, 125 FW_FOISCSI_CHAP_WR = 0x6c, 126 FW_FCOE_ELS_CT_WR = 0x30, 127 FW_SCSI_WRITE_WR = 0x31, 128 FW_SCSI_READ_WR = 0x32, 129 FW_SCSI_CMD_WR = 0x33, 130 FW_SCSI_ABRT_CLS_WR = 0x34, 131 FW_SCSI_TGT_ACC_WR = 0x35, 132 FW_SCSI_TGT_XMIT_WR = 0x36, 133 FW_SCSI_TGT_RSP_WR = 0x37, 134 FW_POFCOE_TCB_WR = 0x42, 135 FW_POFCOE_ULPTX_WR = 0x43, 136 FW_ISCSI_TX_DATA_WR = 0x45, 137 FW_PTP_TX_PKT_WR = 0x46, 138 FW_SEC_LOOKASIDE_LPBK_WR= 0x6d, 139 FW_COiSCSI_TGT_WR = 0x70, 140 FW_COiSCSI_TGT_CONN_WR = 0x71, 141 FW_COiSCSI_TGT_XMIT_WR = 0x72, 142 FW_ISNS_WR = 0x75, 143 FW_ISNS_XMIT_WR = 0x76, 144 FW_LASTC2E_WR = 0x80 145 }; 146 147 /* 148 * Generic work request header flit0 149 */ 150 struct fw_wr_hdr { 151 __be32 hi; 152 __be32 lo; 153 }; 154 155 /* work request opcode (hi) 156 */ 157 #define S_FW_WR_OP 24 158 #define M_FW_WR_OP 0xff 159 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 160 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 161 162 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 163 */ 164 #define S_FW_WR_ATOMIC 23 165 #define M_FW_WR_ATOMIC 0x1 166 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 167 #define G_FW_WR_ATOMIC(x) \ 168 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 169 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 170 171 /* flush flag (hi) - firmware flushes flushable work request buffered 172 * in the flow context. 173 */ 174 #define S_FW_WR_FLUSH 22 175 #define M_FW_WR_FLUSH 0x1 176 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 177 #define G_FW_WR_FLUSH(x) \ 178 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 179 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 180 181 /* completion flag (hi) - firmware generates a cpl_fw6_ack 182 */ 183 #define S_FW_WR_COMPL 21 184 #define M_FW_WR_COMPL 0x1 185 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 186 #define G_FW_WR_COMPL(x) \ 187 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 188 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 189 190 191 /* work request immediate data lengh (hi) 192 */ 193 #define S_FW_WR_IMMDLEN 0 194 #define M_FW_WR_IMMDLEN 0xff 195 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 196 #define G_FW_WR_IMMDLEN(x) \ 197 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 198 199 /* egress queue status update to associated ingress queue entry (lo) 200 */ 201 #define S_FW_WR_EQUIQ 31 202 #define M_FW_WR_EQUIQ 0x1 203 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 204 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 205 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 206 207 /* egress queue status update to egress queue status entry (lo) 208 */ 209 #define S_FW_WR_EQUEQ 30 210 #define M_FW_WR_EQUEQ 0x1 211 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 212 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 213 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 214 215 /* flow context identifier (lo) 216 */ 217 #define S_FW_WR_FLOWID 8 218 #define M_FW_WR_FLOWID 0xfffff 219 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 220 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 221 222 /* length in units of 16-bytes (lo) 223 */ 224 #define S_FW_WR_LEN16 0 225 #define M_FW_WR_LEN16 0xff 226 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 227 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 228 229 struct fw_frag_wr { 230 __be32 op_to_fragoff16; 231 __be32 flowid_len16; 232 __be64 r4; 233 }; 234 235 #define S_FW_FRAG_WR_EOF 15 236 #define M_FW_FRAG_WR_EOF 0x1 237 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 238 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 239 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 240 241 #define S_FW_FRAG_WR_FRAGOFF16 8 242 #define M_FW_FRAG_WR_FRAGOFF16 0x7f 243 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 244 #define G_FW_FRAG_WR_FRAGOFF16(x) \ 245 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 246 247 /* valid filter configurations for compressed tuple 248 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 249 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 250 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 251 * OV - Outer VLAN/VNIC_ID, 252 */ 253 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 254 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 255 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 256 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 257 #define HW_TPL_FR_MT_E_PR_T 0x370 258 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 259 #define HW_TPL_FR_MT_E_T_P_FC 0X353 260 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 261 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 262 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 263 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 264 #define HW_TPL_FR_M_E_PR_FC 0X2E1 265 #define HW_TPL_FR_M_E_T_FC 0X2D1 266 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 267 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 268 #define HW_TPL_FR_M_T_IV_FC 0X299 269 #define HW_TPL_FR_M_T_OV_FC 0X295 270 #define HW_TPL_FR_E_PR_T_P 0X272 271 #define HW_TPL_FR_E_PR_T_FC 0X271 272 #define HW_TPL_FR_E_IV_FC 0X249 273 #define HW_TPL_FR_E_OV_FC 0X245 274 #define HW_TPL_FR_PR_T_IV_FC 0X239 275 #define HW_TPL_FR_PR_T_OV_FC 0X235 276 #define HW_TPL_FR_IV_OV_FC 0X20D 277 #define HW_TPL_MT_M_E_PR 0X1E0 278 #define HW_TPL_MT_M_E_T 0X1D0 279 #define HW_TPL_MT_E_PR_T_FC 0X171 280 #define HW_TPL_MT_E_IV 0X148 281 #define HW_TPL_MT_E_OV 0X144 282 #define HW_TPL_MT_PR_T_IV 0X138 283 #define HW_TPL_MT_PR_T_OV 0X134 284 #define HW_TPL_M_E_PR_P 0X0E2 285 #define HW_TPL_M_E_T_P 0X0D2 286 #define HW_TPL_E_PR_T_P_FC 0X073 287 #define HW_TPL_E_IV_P 0X04A 288 #define HW_TPL_E_OV_P 0X046 289 #define HW_TPL_PR_T_IV_P 0X03A 290 #define HW_TPL_PR_T_OV_P 0X036 291 292 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 293 enum fw_filter_wr_cookie { 294 FW_FILTER_WR_SUCCESS, 295 FW_FILTER_WR_FLT_ADDED, 296 FW_FILTER_WR_FLT_DELETED, 297 FW_FILTER_WR_SMT_TBL_FULL, 298 FW_FILTER_WR_EINVAL, 299 }; 300 301 struct fw_filter_wr { 302 __be32 op_pkd; 303 __be32 len16_pkd; 304 __be64 r3; 305 __be32 tid_to_iq; 306 __be32 del_filter_to_l2tix; 307 __be16 ethtype; 308 __be16 ethtypem; 309 __u8 frag_to_ovlan_vldm; 310 __u8 smac_sel; 311 __be16 rx_chan_rx_rpl_iq; 312 __be32 maci_to_matchtypem; 313 __u8 ptcl; 314 __u8 ptclm; 315 __u8 ttyp; 316 __u8 ttypm; 317 __be16 ivlan; 318 __be16 ivlanm; 319 __be16 ovlan; 320 __be16 ovlanm; 321 __u8 lip[16]; 322 __u8 lipm[16]; 323 __u8 fip[16]; 324 __u8 fipm[16]; 325 __be16 lp; 326 __be16 lpm; 327 __be16 fp; 328 __be16 fpm; 329 __be16 r7; 330 __u8 sma[6]; 331 }; 332 333 #define S_FW_FILTER_WR_TID 12 334 #define M_FW_FILTER_WR_TID 0xfffff 335 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 336 #define G_FW_FILTER_WR_TID(x) \ 337 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 338 339 #define S_FW_FILTER_WR_RQTYPE 11 340 #define M_FW_FILTER_WR_RQTYPE 0x1 341 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 342 #define G_FW_FILTER_WR_RQTYPE(x) \ 343 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 344 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 345 346 #define S_FW_FILTER_WR_NOREPLY 10 347 #define M_FW_FILTER_WR_NOREPLY 0x1 348 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 349 #define G_FW_FILTER_WR_NOREPLY(x) \ 350 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 351 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 352 353 #define S_FW_FILTER_WR_IQ 0 354 #define M_FW_FILTER_WR_IQ 0x3ff 355 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 356 #define G_FW_FILTER_WR_IQ(x) \ 357 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 358 359 #define S_FW_FILTER_WR_DEL_FILTER 31 360 #define M_FW_FILTER_WR_DEL_FILTER 0x1 361 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 362 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 363 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 364 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 365 366 #define S_FW_FILTER_WR_RPTTID 25 367 #define M_FW_FILTER_WR_RPTTID 0x1 368 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 369 #define G_FW_FILTER_WR_RPTTID(x) \ 370 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 371 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 372 373 #define S_FW_FILTER_WR_DROP 24 374 #define M_FW_FILTER_WR_DROP 0x1 375 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 376 #define G_FW_FILTER_WR_DROP(x) \ 377 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 378 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 379 380 #define S_FW_FILTER_WR_DIRSTEER 23 381 #define M_FW_FILTER_WR_DIRSTEER 0x1 382 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 383 #define G_FW_FILTER_WR_DIRSTEER(x) \ 384 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 385 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 386 387 #define S_FW_FILTER_WR_MASKHASH 22 388 #define M_FW_FILTER_WR_MASKHASH 0x1 389 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 390 #define G_FW_FILTER_WR_MASKHASH(x) \ 391 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 392 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 393 394 #define S_FW_FILTER_WR_DIRSTEERHASH 21 395 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 396 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 397 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 398 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 399 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 400 401 #define S_FW_FILTER_WR_LPBK 20 402 #define M_FW_FILTER_WR_LPBK 0x1 403 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 404 #define G_FW_FILTER_WR_LPBK(x) \ 405 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 406 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 407 408 #define S_FW_FILTER_WR_DMAC 19 409 #define M_FW_FILTER_WR_DMAC 0x1 410 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 411 #define G_FW_FILTER_WR_DMAC(x) \ 412 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 413 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 414 415 #define S_FW_FILTER_WR_SMAC 18 416 #define M_FW_FILTER_WR_SMAC 0x1 417 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 418 #define G_FW_FILTER_WR_SMAC(x) \ 419 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 420 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 421 422 #define S_FW_FILTER_WR_INSVLAN 17 423 #define M_FW_FILTER_WR_INSVLAN 0x1 424 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 425 #define G_FW_FILTER_WR_INSVLAN(x) \ 426 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 427 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 428 429 #define S_FW_FILTER_WR_RMVLAN 16 430 #define M_FW_FILTER_WR_RMVLAN 0x1 431 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 432 #define G_FW_FILTER_WR_RMVLAN(x) \ 433 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 434 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 435 436 #define S_FW_FILTER_WR_HITCNTS 15 437 #define M_FW_FILTER_WR_HITCNTS 0x1 438 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 439 #define G_FW_FILTER_WR_HITCNTS(x) \ 440 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 441 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 442 443 #define S_FW_FILTER_WR_TXCHAN 13 444 #define M_FW_FILTER_WR_TXCHAN 0x3 445 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 446 #define G_FW_FILTER_WR_TXCHAN(x) \ 447 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 448 449 #define S_FW_FILTER_WR_PRIO 12 450 #define M_FW_FILTER_WR_PRIO 0x1 451 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 452 #define G_FW_FILTER_WR_PRIO(x) \ 453 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 454 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 455 456 #define S_FW_FILTER_WR_L2TIX 0 457 #define M_FW_FILTER_WR_L2TIX 0xfff 458 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 459 #define G_FW_FILTER_WR_L2TIX(x) \ 460 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 461 462 #define S_FW_FILTER_WR_FRAG 7 463 #define M_FW_FILTER_WR_FRAG 0x1 464 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 465 #define G_FW_FILTER_WR_FRAG(x) \ 466 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 467 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 468 469 #define S_FW_FILTER_WR_FRAGM 6 470 #define M_FW_FILTER_WR_FRAGM 0x1 471 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 472 #define G_FW_FILTER_WR_FRAGM(x) \ 473 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 474 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 475 476 #define S_FW_FILTER_WR_IVLAN_VLD 5 477 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 478 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 479 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 480 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 481 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 482 483 #define S_FW_FILTER_WR_OVLAN_VLD 4 484 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 485 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 486 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 487 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 488 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 489 490 #define S_FW_FILTER_WR_IVLAN_VLDM 3 491 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 492 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 493 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 494 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 495 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 496 497 #define S_FW_FILTER_WR_OVLAN_VLDM 2 498 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 499 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 500 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 501 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 502 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 503 504 #define S_FW_FILTER_WR_RX_CHAN 15 505 #define M_FW_FILTER_WR_RX_CHAN 0x1 506 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 507 #define G_FW_FILTER_WR_RX_CHAN(x) \ 508 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 509 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 510 511 #define S_FW_FILTER_WR_RX_RPL_IQ 0 512 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 513 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 514 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 515 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 516 517 #define S_FW_FILTER_WR_MACI 23 518 #define M_FW_FILTER_WR_MACI 0x1ff 519 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 520 #define G_FW_FILTER_WR_MACI(x) \ 521 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 522 523 #define S_FW_FILTER_WR_MACIM 14 524 #define M_FW_FILTER_WR_MACIM 0x1ff 525 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 526 #define G_FW_FILTER_WR_MACIM(x) \ 527 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 528 529 #define S_FW_FILTER_WR_FCOE 13 530 #define M_FW_FILTER_WR_FCOE 0x1 531 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 532 #define G_FW_FILTER_WR_FCOE(x) \ 533 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 534 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 535 536 #define S_FW_FILTER_WR_FCOEM 12 537 #define M_FW_FILTER_WR_FCOEM 0x1 538 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 539 #define G_FW_FILTER_WR_FCOEM(x) \ 540 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 541 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 542 543 #define S_FW_FILTER_WR_PORT 9 544 #define M_FW_FILTER_WR_PORT 0x7 545 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 546 #define G_FW_FILTER_WR_PORT(x) \ 547 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 548 549 #define S_FW_FILTER_WR_PORTM 6 550 #define M_FW_FILTER_WR_PORTM 0x7 551 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 552 #define G_FW_FILTER_WR_PORTM(x) \ 553 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 554 555 #define S_FW_FILTER_WR_MATCHTYPE 3 556 #define M_FW_FILTER_WR_MATCHTYPE 0x7 557 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 558 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 559 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 560 561 #define S_FW_FILTER_WR_MATCHTYPEM 0 562 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 563 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 564 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 565 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 566 567 struct fw_ulptx_wr { 568 __be32 op_to_compl; 569 __be32 flowid_len16; 570 __u64 cookie; 571 }; 572 573 struct fw_tp_wr { 574 __be32 op_to_immdlen; 575 __be32 flowid_len16; 576 __u64 cookie; 577 }; 578 579 struct fw_eth_tx_pkt_wr { 580 __be32 op_immdlen; 581 __be32 equiq_to_len16; 582 __be64 r3; 583 }; 584 585 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 586 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 587 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 588 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 589 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 590 591 struct fw_eth_tx_pkt2_wr { 592 __be32 op_immdlen; 593 __be32 equiq_to_len16; 594 __be32 r3; 595 __be32 L4ChkDisable_to_IpHdrLen; 596 }; 597 598 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 599 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 600 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 601 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 602 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 603 604 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 605 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 606 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 607 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 608 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 609 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 610 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 611 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 612 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 613 614 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 615 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 616 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 617 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 618 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 619 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 620 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 621 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 622 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 623 624 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 625 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 626 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 627 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 628 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 629 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 630 631 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 632 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 633 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 634 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 635 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 636 637 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 638 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 639 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 640 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 641 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 642 643 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 644 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 645 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 646 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 647 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 648 649 struct fw_eth_tx_pkts_wr { 650 __be32 op_pkd; 651 __be32 equiq_to_len16; 652 __be32 r3; 653 __be16 plen; 654 __u8 npkt; 655 __u8 type; 656 }; 657 658 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 659 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 660 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 661 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 662 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 663 664 struct fw_eth_tx_pkt_ptp_wr { 665 __be32 op_immdlen; 666 __be32 equiq_to_len16; 667 __be64 r3; 668 }; 669 670 enum fw_eth_tx_eo_type { 671 FW_ETH_TX_EO_TYPE_UDPSEG, 672 FW_ETH_TX_EO_TYPE_TCPSEG, 673 FW_ETH_TX_EO_TYPE_NVGRESEG, 674 FW_ETH_TX_EO_TYPE_VXLANSEG, 675 FW_ETH_TX_EO_TYPE_GENEVESEG, 676 }; 677 678 struct fw_eth_tx_eo_wr { 679 __be32 op_immdlen; 680 __be32 equiq_to_len16; 681 __be64 r3; 682 union fw_eth_tx_eo { 683 struct fw_eth_tx_eo_udpseg { 684 __u8 type; 685 __u8 ethlen; 686 __be16 iplen; 687 __u8 udplen; 688 __u8 rtplen; 689 __be16 r4; 690 __be16 mss; 691 __be16 schedpktsize; 692 __be32 plen; 693 } udpseg; 694 struct fw_eth_tx_eo_tcpseg { 695 __u8 type; 696 __u8 ethlen; 697 __be16 iplen; 698 __u8 tcplen; 699 __u8 tsclk_tsoff; 700 __be16 r4; 701 __be16 mss; 702 __be16 r5; 703 __be32 plen; 704 } tcpseg; 705 struct fw_eth_tx_eo_nvgreseg { 706 __u8 type; 707 __u8 iphdroffout; 708 __be16 grehdroff; 709 __be16 iphdroffin; 710 __be16 tcphdroffin; 711 __be16 mss; 712 __be16 r4; 713 __be32 plen; 714 } nvgreseg; 715 struct fw_eth_tx_eo_vxlanseg { 716 __u8 type; 717 __u8 iphdroffout; 718 __be16 vxlanhdroff; 719 __be16 iphdroffin; 720 __be16 tcphdroffin; 721 __be16 mss; 722 __be16 r4; 723 __be32 plen; 724 725 } vxlanseg; 726 struct fw_eth_tx_eo_geneveseg { 727 __u8 type; 728 __u8 iphdroffout; 729 __be16 genevehdroff; 730 __be16 iphdroffin; 731 __be16 tcphdroffin; 732 __be16 mss; 733 __be16 r4; 734 __be32 plen; 735 } geneveseg; 736 } u; 737 }; 738 739 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0 740 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 741 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 742 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 743 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 744 745 #define S_FW_ETH_TX_EO_WR_TSCLK 6 746 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3 747 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 748 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 749 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 750 751 #define S_FW_ETH_TX_EO_WR_TSOFF 0 752 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 753 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 754 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 755 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 756 757 struct fw_eq_flush_wr { 758 __u8 opcode; 759 __u8 r1[3]; 760 __be32 equiq_to_len16; 761 __be64 r3; 762 }; 763 764 struct fw_ofld_connection_wr { 765 __be32 op_compl; 766 __be32 len16_pkd; 767 __u64 cookie; 768 __be64 r2; 769 __be64 r3; 770 struct fw_ofld_connection_le { 771 __be32 version_cpl; 772 __be32 filter; 773 __be32 r1; 774 __be16 lport; 775 __be16 pport; 776 union fw_ofld_connection_leip { 777 struct fw_ofld_connection_le_ipv4 { 778 __be32 pip; 779 __be32 lip; 780 __be64 r0; 781 __be64 r1; 782 __be64 r2; 783 } ipv4; 784 struct fw_ofld_connection_le_ipv6 { 785 __be64 pip_hi; 786 __be64 pip_lo; 787 __be64 lip_hi; 788 __be64 lip_lo; 789 } ipv6; 790 } u; 791 } le; 792 struct fw_ofld_connection_tcb { 793 __be32 t_state_to_astid; 794 __be16 cplrxdataack_cplpassacceptrpl; 795 __be16 rcv_adv; 796 __be32 rcv_nxt; 797 __be32 tx_max; 798 __be64 opt0; 799 __be32 opt2; 800 __be32 r1; 801 __be64 r2; 802 __be64 r3; 803 } tcb; 804 }; 805 806 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 807 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 808 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 809 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 810 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 811 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 812 M_FW_OFLD_CONNECTION_WR_VERSION) 813 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 814 815 #define S_FW_OFLD_CONNECTION_WR_CPL 30 816 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 817 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 818 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 819 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 820 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 821 822 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 823 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 824 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 825 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 826 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 827 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 828 M_FW_OFLD_CONNECTION_WR_T_STATE) 829 830 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 831 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 832 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 833 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 834 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 835 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 836 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 837 838 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 839 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 840 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 841 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 842 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 843 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 844 845 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 846 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 847 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 848 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 849 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 850 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 851 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 852 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 853 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 854 855 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 856 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 857 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 858 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 859 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 860 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 861 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 862 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 863 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 864 865 enum fw_flowc_mnem_tcpstate { 866 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 867 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 868 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 869 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 870 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 871 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 872 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 873 * will resend FIN - equiv ESTAB 874 */ 875 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 876 * will resend FIN but have 877 * received FIN 878 */ 879 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 880 * will resend FIN but have 881 * received FIN 882 */ 883 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 884 * waiting for FIN 885 */ 886 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 887 }; 888 889 enum fw_flowc_mnem_eostate { 890 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 891 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 892 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 893 * outstanding payload 894 */ 895 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 896 * discarding outstanding payload 897 */ 898 }; 899 900 enum fw_flowc_mnem { 901 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 902 FW_FLOWC_MNEM_CH = 1, 903 FW_FLOWC_MNEM_PORT = 2, 904 FW_FLOWC_MNEM_IQID = 3, 905 FW_FLOWC_MNEM_SNDNXT = 4, 906 FW_FLOWC_MNEM_RCVNXT = 5, 907 FW_FLOWC_MNEM_SNDBUF = 6, 908 FW_FLOWC_MNEM_MSS = 7, 909 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 910 FW_FLOWC_MNEM_TCPSTATE = 9, 911 FW_FLOWC_MNEM_EOSTATE = 10, 912 FW_FLOWC_MNEM_SCHEDCLASS = 11, 913 FW_FLOWC_MNEM_DCBPRIO = 12, 914 FW_FLOWC_MNEM_SND_SCALE = 13, 915 FW_FLOWC_MNEM_RCV_SCALE = 14, 916 FW_FLOWC_MNEM_MAX = 15, 917 }; 918 919 struct fw_flowc_mnemval { 920 __u8 mnemonic; 921 __u8 r4[3]; 922 __be32 val; 923 }; 924 925 struct fw_flowc_wr { 926 __be32 op_to_nparams; 927 __be32 flowid_len16; 928 #ifndef C99_NOT_SUPPORTED 929 struct fw_flowc_mnemval mnemval[0]; 930 #endif 931 }; 932 933 #define S_FW_FLOWC_WR_NPARAMS 0 934 #define M_FW_FLOWC_WR_NPARAMS 0xff 935 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 936 #define G_FW_FLOWC_WR_NPARAMS(x) \ 937 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 938 939 struct fw_ofld_tx_data_wr { 940 __be32 op_to_immdlen; 941 __be32 flowid_len16; 942 __be32 plen; 943 __be32 lsodisable_to_flags; 944 }; 945 946 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 947 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 948 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 949 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 950 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 951 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 952 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 953 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 954 955 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 956 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 957 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 958 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 959 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 960 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 961 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 962 963 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 964 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 965 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 966 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 967 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 968 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 969 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 970 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 971 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 972 973 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0 974 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 975 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 976 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 977 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 978 979 980 /* Use fw_ofld_tx_data_wr structure */ 981 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 982 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 983 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 984 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 985 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 986 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 987 988 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 989 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 990 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 991 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 992 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 993 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 994 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 995 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 996 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 997 998 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 999 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 1000 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1001 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1002 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1003 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 1004 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1005 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 1006 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1007 1008 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1009 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1010 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1011 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1012 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1013 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1014 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1015 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1016 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1017 1018 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1019 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1020 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1021 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1022 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1023 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1024 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1025 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1026 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1027 1028 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1029 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1030 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1031 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1032 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1033 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1034 1035 struct fw_cmd_wr { 1036 __be32 op_dma; 1037 __be32 len16_pkd; 1038 __be64 cookie_daddr; 1039 }; 1040 1041 #define S_FW_CMD_WR_DMA 17 1042 #define M_FW_CMD_WR_DMA 0x1 1043 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1044 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1045 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1046 1047 struct fw_eth_tx_pkt_vm_wr { 1048 __be32 op_immdlen; 1049 __be32 equiq_to_len16; 1050 __be32 r3[2]; 1051 __u8 ethmacdst[6]; 1052 __u8 ethmacsrc[6]; 1053 __be16 ethtype; 1054 __be16 vlantci; 1055 }; 1056 1057 /****************************************************************************** 1058 * R I W O R K R E Q U E S T s 1059 **************************************/ 1060 1061 enum fw_ri_wr_opcode { 1062 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1063 FW_RI_READ_REQ = 0x1, 1064 FW_RI_READ_RESP = 0x2, 1065 FW_RI_SEND = 0x3, 1066 FW_RI_SEND_WITH_INV = 0x4, 1067 FW_RI_SEND_WITH_SE = 0x5, 1068 FW_RI_SEND_WITH_SE_INV = 0x6, 1069 FW_RI_TERMINATE = 0x7, 1070 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1071 FW_RI_BIND_MW = 0x9, 1072 FW_RI_FAST_REGISTER = 0xa, 1073 FW_RI_LOCAL_INV = 0xb, 1074 FW_RI_QP_MODIFY = 0xc, 1075 FW_RI_BYPASS = 0xd, 1076 FW_RI_RECEIVE = 0xe, 1077 #if 0 1078 FW_RI_SEND_IMMEDIATE = 0x8, 1079 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1080 FW_RI_ATOMIC_REQUEST = 0xa, 1081 FW_RI_ATOMIC_RESPONSE = 0xb, 1082 1083 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1084 FW_RI_FAST_REGISTER = 0xd, 1085 FW_RI_LOCAL_INV = 0xe, 1086 #endif 1087 FW_RI_SGE_EC_CR_RETURN = 0xf 1088 }; 1089 1090 enum fw_ri_wr_flags { 1091 FW_RI_COMPLETION_FLAG = 0x01, 1092 FW_RI_NOTIFICATION_FLAG = 0x02, 1093 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1094 FW_RI_READ_FENCE_FLAG = 0x08, 1095 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1096 FW_RI_RDMA_READ_INVALIDATE = 0x20 1097 }; 1098 1099 enum fw_ri_mpa_attrs { 1100 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1101 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1102 FW_RI_MPA_CRC_ENABLE = 0x04, 1103 FW_RI_MPA_IETF_ENABLE = 0x08 1104 }; 1105 1106 enum fw_ri_qp_caps { 1107 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1108 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1109 FW_RI_QP_BIND_ENABLE = 0x04, 1110 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1111 FW_RI_QP_STAG0_ENABLE = 0x10, 1112 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1113 }; 1114 1115 enum fw_ri_addr_type { 1116 FW_RI_ZERO_BASED_TO = 0x00, 1117 FW_RI_VA_BASED_TO = 0x01 1118 }; 1119 1120 enum fw_ri_mem_perms { 1121 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1122 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1123 FW_RI_MEM_ACCESS_REM = 0x03, 1124 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1125 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1126 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1127 }; 1128 1129 enum fw_ri_stag_type { 1130 FW_RI_STAG_NSMR = 0x00, 1131 FW_RI_STAG_SMR = 0x01, 1132 FW_RI_STAG_MW = 0x02, 1133 FW_RI_STAG_MW_RELAXED = 0x03 1134 }; 1135 1136 enum fw_ri_data_op { 1137 FW_RI_DATA_IMMD = 0x81, 1138 FW_RI_DATA_DSGL = 0x82, 1139 FW_RI_DATA_ISGL = 0x83 1140 }; 1141 1142 enum fw_ri_sgl_depth { 1143 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1144 FW_RI_SGL_DEPTH_MAX_RQ = 4 1145 }; 1146 1147 enum fw_ri_cqe_err { 1148 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1149 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1150 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1151 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1152 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1153 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1154 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1155 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1156 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1157 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1158 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1159 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1160 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1161 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1162 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1163 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1164 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1165 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1166 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1167 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1168 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1169 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1170 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1171 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1172 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1173 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1174 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1175 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1176 1177 }; 1178 1179 struct fw_ri_dsge_pair { 1180 __be32 len[2]; 1181 __be64 addr[2]; 1182 }; 1183 1184 struct fw_ri_dsgl { 1185 __u8 op; 1186 __u8 r1; 1187 __be16 nsge; 1188 __be32 len0; 1189 __be64 addr0; 1190 #ifndef C99_NOT_SUPPORTED 1191 struct fw_ri_dsge_pair sge[0]; 1192 #endif 1193 }; 1194 1195 struct fw_ri_sge { 1196 __be32 stag; 1197 __be32 len; 1198 __be64 to; 1199 }; 1200 1201 struct fw_ri_isgl { 1202 __u8 op; 1203 __u8 r1; 1204 __be16 nsge; 1205 __be32 r2; 1206 #ifndef C99_NOT_SUPPORTED 1207 struct fw_ri_sge sge[0]; 1208 #endif 1209 }; 1210 1211 struct fw_ri_immd { 1212 __u8 op; 1213 __u8 r1; 1214 __be16 r2; 1215 __be32 immdlen; 1216 #ifndef C99_NOT_SUPPORTED 1217 __u8 data[0]; 1218 #endif 1219 }; 1220 1221 struct fw_ri_tpte { 1222 __be32 valid_to_pdid; 1223 __be32 locread_to_qpid; 1224 __be32 nosnoop_pbladdr; 1225 __be32 len_lo; 1226 __be32 va_hi; 1227 __be32 va_lo_fbo; 1228 __be32 dca_mwbcnt_pstag; 1229 __be32 len_hi; 1230 }; 1231 1232 #define S_FW_RI_TPTE_VALID 31 1233 #define M_FW_RI_TPTE_VALID 0x1 1234 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1235 #define G_FW_RI_TPTE_VALID(x) \ 1236 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1237 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1238 1239 #define S_FW_RI_TPTE_STAGKEY 23 1240 #define M_FW_RI_TPTE_STAGKEY 0xff 1241 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1242 #define G_FW_RI_TPTE_STAGKEY(x) \ 1243 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1244 1245 #define S_FW_RI_TPTE_STAGSTATE 22 1246 #define M_FW_RI_TPTE_STAGSTATE 0x1 1247 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1248 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1249 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1250 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1251 1252 #define S_FW_RI_TPTE_STAGTYPE 20 1253 #define M_FW_RI_TPTE_STAGTYPE 0x3 1254 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1255 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1256 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1257 1258 #define S_FW_RI_TPTE_PDID 0 1259 #define M_FW_RI_TPTE_PDID 0xfffff 1260 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1261 #define G_FW_RI_TPTE_PDID(x) \ 1262 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1263 1264 #define S_FW_RI_TPTE_PERM 28 1265 #define M_FW_RI_TPTE_PERM 0xf 1266 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1267 #define G_FW_RI_TPTE_PERM(x) \ 1268 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1269 1270 #define S_FW_RI_TPTE_REMINVDIS 27 1271 #define M_FW_RI_TPTE_REMINVDIS 0x1 1272 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1273 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1274 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1275 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1276 1277 #define S_FW_RI_TPTE_ADDRTYPE 26 1278 #define M_FW_RI_TPTE_ADDRTYPE 1 1279 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1280 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1281 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1282 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1283 1284 #define S_FW_RI_TPTE_MWBINDEN 25 1285 #define M_FW_RI_TPTE_MWBINDEN 0x1 1286 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1287 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1288 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1289 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1290 1291 #define S_FW_RI_TPTE_PS 20 1292 #define M_FW_RI_TPTE_PS 0x1f 1293 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1294 #define G_FW_RI_TPTE_PS(x) \ 1295 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1296 1297 #define S_FW_RI_TPTE_QPID 0 1298 #define M_FW_RI_TPTE_QPID 0xfffff 1299 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1300 #define G_FW_RI_TPTE_QPID(x) \ 1301 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1302 1303 #define S_FW_RI_TPTE_NOSNOOP 31 1304 #define M_FW_RI_TPTE_NOSNOOP 0x1 1305 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1306 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1307 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1308 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1309 1310 #define S_FW_RI_TPTE_PBLADDR 0 1311 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1312 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1313 #define G_FW_RI_TPTE_PBLADDR(x) \ 1314 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1315 1316 #define S_FW_RI_TPTE_DCA 24 1317 #define M_FW_RI_TPTE_DCA 0x1f 1318 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1319 #define G_FW_RI_TPTE_DCA(x) \ 1320 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1321 1322 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1323 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1324 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1325 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1326 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1327 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1328 1329 enum fw_ri_cqe_rxtx { 1330 FW_RI_CQE_RXTX_RX = 0x0, 1331 FW_RI_CQE_RXTX_TX = 0x1, 1332 }; 1333 1334 struct fw_ri_cqe { 1335 union fw_ri_rxtx { 1336 struct fw_ri_scqe { 1337 __be32 qpid_n_stat_rxtx_type; 1338 __be32 plen; 1339 __be32 reserved; 1340 __be32 wrid; 1341 } scqe; 1342 struct fw_ri_rcqe { 1343 __be32 qpid_n_stat_rxtx_type; 1344 __be32 plen; 1345 __be32 stag; 1346 __be32 msn; 1347 } rcqe; 1348 } u; 1349 }; 1350 1351 #define S_FW_RI_CQE_QPID 12 1352 #define M_FW_RI_CQE_QPID 0xfffff 1353 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1354 #define G_FW_RI_CQE_QPID(x) \ 1355 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1356 1357 #define S_FW_RI_CQE_NOTIFY 10 1358 #define M_FW_RI_CQE_NOTIFY 0x1 1359 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1360 #define G_FW_RI_CQE_NOTIFY(x) \ 1361 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1362 1363 #define S_FW_RI_CQE_STATUS 5 1364 #define M_FW_RI_CQE_STATUS 0x1f 1365 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1366 #define G_FW_RI_CQE_STATUS(x) \ 1367 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1368 1369 1370 #define S_FW_RI_CQE_RXTX 4 1371 #define M_FW_RI_CQE_RXTX 0x1 1372 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1373 #define G_FW_RI_CQE_RXTX(x) \ 1374 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1375 1376 #define S_FW_RI_CQE_TYPE 0 1377 #define M_FW_RI_CQE_TYPE 0xf 1378 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1379 #define G_FW_RI_CQE_TYPE(x) \ 1380 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1381 1382 enum fw_ri_res_type { 1383 FW_RI_RES_TYPE_SQ, 1384 FW_RI_RES_TYPE_RQ, 1385 FW_RI_RES_TYPE_CQ, 1386 FW_RI_RES_TYPE_SRQ, 1387 }; 1388 1389 enum fw_ri_res_op { 1390 FW_RI_RES_OP_WRITE, 1391 FW_RI_RES_OP_RESET, 1392 }; 1393 1394 struct fw_ri_res { 1395 union fw_ri_restype { 1396 struct fw_ri_res_sqrq { 1397 __u8 restype; 1398 __u8 op; 1399 __be16 r3; 1400 __be32 eqid; 1401 __be32 r4[2]; 1402 __be32 fetchszm_to_iqid; 1403 __be32 dcaen_to_eqsize; 1404 __be64 eqaddr; 1405 } sqrq; 1406 struct fw_ri_res_cq { 1407 __u8 restype; 1408 __u8 op; 1409 __be16 r3; 1410 __be32 iqid; 1411 __be32 r4[2]; 1412 __be32 iqandst_to_iqandstindex; 1413 __be16 iqdroprss_to_iqesize; 1414 __be16 iqsize; 1415 __be64 iqaddr; 1416 __be32 iqns_iqro; 1417 __be32 r6_lo; 1418 __be64 r7; 1419 } cq; 1420 struct fw_ri_res_srq { 1421 __u8 restype; 1422 __u8 op; 1423 __be16 r3; 1424 __be32 eqid; 1425 __be32 r4[2]; 1426 __be32 fetchszm_to_iqid; 1427 __be32 dcaen_to_eqsize; 1428 __be64 eqaddr; 1429 __be32 srqid; 1430 __be32 pdid; 1431 __be32 hwsrqsize; 1432 __be32 hwsrqaddr; 1433 } srq; 1434 } u; 1435 }; 1436 1437 struct fw_ri_res_wr { 1438 __be32 op_nres; 1439 __be32 len16_pkd; 1440 __u64 cookie; 1441 #ifndef C99_NOT_SUPPORTED 1442 struct fw_ri_res res[0]; 1443 #endif 1444 }; 1445 1446 #define S_FW_RI_RES_WR_NRES 0 1447 #define M_FW_RI_RES_WR_NRES 0xff 1448 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1449 #define G_FW_RI_RES_WR_NRES(x) \ 1450 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1451 1452 #define S_FW_RI_RES_WR_FETCHSZM 26 1453 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1454 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1455 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1456 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1457 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1458 1459 #define S_FW_RI_RES_WR_STATUSPGNS 25 1460 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1461 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1462 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1463 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1464 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1465 1466 #define S_FW_RI_RES_WR_STATUSPGRO 24 1467 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1468 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1469 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1470 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1471 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1472 1473 #define S_FW_RI_RES_WR_FETCHNS 23 1474 #define M_FW_RI_RES_WR_FETCHNS 0x1 1475 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1476 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1477 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1478 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1479 1480 #define S_FW_RI_RES_WR_FETCHRO 22 1481 #define M_FW_RI_RES_WR_FETCHRO 0x1 1482 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1483 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1484 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1485 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1486 1487 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1488 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1489 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1490 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1491 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1492 1493 #define S_FW_RI_RES_WR_CPRIO 19 1494 #define M_FW_RI_RES_WR_CPRIO 0x1 1495 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1496 #define G_FW_RI_RES_WR_CPRIO(x) \ 1497 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1498 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1499 1500 #define S_FW_RI_RES_WR_ONCHIP 18 1501 #define M_FW_RI_RES_WR_ONCHIP 0x1 1502 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1503 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1504 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1505 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1506 1507 #define S_FW_RI_RES_WR_PCIECHN 16 1508 #define M_FW_RI_RES_WR_PCIECHN 0x3 1509 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1510 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1511 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1512 1513 #define S_FW_RI_RES_WR_IQID 0 1514 #define M_FW_RI_RES_WR_IQID 0xffff 1515 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1516 #define G_FW_RI_RES_WR_IQID(x) \ 1517 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1518 1519 #define S_FW_RI_RES_WR_DCAEN 31 1520 #define M_FW_RI_RES_WR_DCAEN 0x1 1521 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1522 #define G_FW_RI_RES_WR_DCAEN(x) \ 1523 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1524 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1525 1526 #define S_FW_RI_RES_WR_DCACPU 26 1527 #define M_FW_RI_RES_WR_DCACPU 0x1f 1528 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1529 #define G_FW_RI_RES_WR_DCACPU(x) \ 1530 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1531 1532 #define S_FW_RI_RES_WR_FBMIN 23 1533 #define M_FW_RI_RES_WR_FBMIN 0x7 1534 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1535 #define G_FW_RI_RES_WR_FBMIN(x) \ 1536 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1537 1538 #define S_FW_RI_RES_WR_FBMAX 20 1539 #define M_FW_RI_RES_WR_FBMAX 0x7 1540 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1541 #define G_FW_RI_RES_WR_FBMAX(x) \ 1542 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1543 1544 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1545 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1546 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1547 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1548 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1549 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1550 1551 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1552 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1553 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1554 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1555 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1556 1557 #define S_FW_RI_RES_WR_EQSIZE 0 1558 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1559 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1560 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1561 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1562 1563 #define S_FW_RI_RES_WR_IQANDST 15 1564 #define M_FW_RI_RES_WR_IQANDST 0x1 1565 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1566 #define G_FW_RI_RES_WR_IQANDST(x) \ 1567 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1568 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1569 1570 #define S_FW_RI_RES_WR_IQANUS 14 1571 #define M_FW_RI_RES_WR_IQANUS 0x1 1572 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1573 #define G_FW_RI_RES_WR_IQANUS(x) \ 1574 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1575 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1576 1577 #define S_FW_RI_RES_WR_IQANUD 12 1578 #define M_FW_RI_RES_WR_IQANUD 0x3 1579 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1580 #define G_FW_RI_RES_WR_IQANUD(x) \ 1581 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1582 1583 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1584 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1585 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1586 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1587 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1588 1589 #define S_FW_RI_RES_WR_IQDROPRSS 15 1590 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1591 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1592 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1593 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1594 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1595 1596 #define S_FW_RI_RES_WR_IQGTSMODE 14 1597 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1598 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1599 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1600 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1601 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1602 1603 #define S_FW_RI_RES_WR_IQPCIECH 12 1604 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1605 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1606 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1607 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1608 1609 #define S_FW_RI_RES_WR_IQDCAEN 11 1610 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1611 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1612 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1613 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1614 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1615 1616 #define S_FW_RI_RES_WR_IQDCACPU 6 1617 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1618 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1619 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1620 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1621 1622 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1623 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1624 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1625 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1626 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1627 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1628 1629 #define S_FW_RI_RES_WR_IQO 3 1630 #define M_FW_RI_RES_WR_IQO 0x1 1631 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1632 #define G_FW_RI_RES_WR_IQO(x) \ 1633 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1634 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1635 1636 #define S_FW_RI_RES_WR_IQCPRIO 2 1637 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1638 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1639 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1640 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1641 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1642 1643 #define S_FW_RI_RES_WR_IQESIZE 0 1644 #define M_FW_RI_RES_WR_IQESIZE 0x3 1645 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1646 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1647 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1648 1649 #define S_FW_RI_RES_WR_IQNS 31 1650 #define M_FW_RI_RES_WR_IQNS 0x1 1651 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1652 #define G_FW_RI_RES_WR_IQNS(x) \ 1653 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1654 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1655 1656 #define S_FW_RI_RES_WR_IQRO 30 1657 #define M_FW_RI_RES_WR_IQRO 0x1 1658 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1659 #define G_FW_RI_RES_WR_IQRO(x) \ 1660 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1661 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1662 1663 struct fw_ri_rdma_write_wr { 1664 __u8 opcode; 1665 __u8 flags; 1666 __u16 wrid; 1667 __u8 r1[3]; 1668 __u8 len16; 1669 __be64 r2; 1670 __be32 plen; 1671 __be32 stag_sink; 1672 __be64 to_sink; 1673 #ifndef C99_NOT_SUPPORTED 1674 union { 1675 struct fw_ri_immd immd_src[0]; 1676 struct fw_ri_isgl isgl_src[0]; 1677 } u; 1678 #endif 1679 }; 1680 1681 struct fw_ri_send_wr { 1682 __u8 opcode; 1683 __u8 flags; 1684 __u16 wrid; 1685 __u8 r1[3]; 1686 __u8 len16; 1687 __be32 sendop_pkd; 1688 __be32 stag_inv; 1689 __be32 plen; 1690 __be32 r3; 1691 __be64 r4; 1692 #ifndef C99_NOT_SUPPORTED 1693 union { 1694 struct fw_ri_immd immd_src[0]; 1695 struct fw_ri_isgl isgl_src[0]; 1696 } u; 1697 #endif 1698 }; 1699 1700 #define S_FW_RI_SEND_WR_SENDOP 0 1701 #define M_FW_RI_SEND_WR_SENDOP 0xf 1702 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1703 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1704 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1705 1706 struct fw_ri_rdma_read_wr { 1707 __u8 opcode; 1708 __u8 flags; 1709 __u16 wrid; 1710 __u8 r1[3]; 1711 __u8 len16; 1712 __be64 r2; 1713 __be32 stag_sink; 1714 __be32 to_sink_hi; 1715 __be32 to_sink_lo; 1716 __be32 plen; 1717 __be32 stag_src; 1718 __be32 to_src_hi; 1719 __be32 to_src_lo; 1720 __be32 r5; 1721 }; 1722 1723 struct fw_ri_recv_wr { 1724 __u8 opcode; 1725 __u8 r1; 1726 __u16 wrid; 1727 __u8 r2[3]; 1728 __u8 len16; 1729 struct fw_ri_isgl isgl; 1730 }; 1731 1732 struct fw_ri_bind_mw_wr { 1733 __u8 opcode; 1734 __u8 flags; 1735 __u16 wrid; 1736 __u8 r1[3]; 1737 __u8 len16; 1738 __u8 qpbinde_to_dcacpu; 1739 __u8 pgsz_shift; 1740 __u8 addr_type; 1741 __u8 mem_perms; 1742 __be32 stag_mr; 1743 __be32 stag_mw; 1744 __be32 r3; 1745 __be64 len_mw; 1746 __be64 va_fbo; 1747 __be64 r4; 1748 }; 1749 1750 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1751 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1752 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1753 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1754 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1755 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1756 1757 #define S_FW_RI_BIND_MW_WR_NS 5 1758 #define M_FW_RI_BIND_MW_WR_NS 0x1 1759 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1760 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1761 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1762 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1763 1764 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1765 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1766 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1767 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1768 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1769 1770 struct fw_ri_fr_nsmr_wr { 1771 __u8 opcode; 1772 __u8 flags; 1773 __u16 wrid; 1774 __u8 r1[3]; 1775 __u8 len16; 1776 __u8 qpbinde_to_dcacpu; 1777 __u8 pgsz_shift; 1778 __u8 addr_type; 1779 __u8 mem_perms; 1780 __be32 stag; 1781 __be32 len_hi; 1782 __be32 len_lo; 1783 __be32 va_hi; 1784 __be32 va_lo_fbo; 1785 }; 1786 1787 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1788 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1789 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1790 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1791 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1792 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1793 1794 #define S_FW_RI_FR_NSMR_WR_NS 5 1795 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1796 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1797 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1798 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1799 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1800 1801 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1802 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1803 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1804 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1805 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1806 1807 struct fw_ri_inv_lstag_wr { 1808 __u8 opcode; 1809 __u8 flags; 1810 __u16 wrid; 1811 __u8 r1[3]; 1812 __u8 len16; 1813 __be32 r2; 1814 __be32 stag_inv; 1815 }; 1816 1817 struct fw_ri_send_immediate_wr { 1818 __u8 opcode; 1819 __u8 flags; 1820 __u16 wrid; 1821 __u8 r1[3]; 1822 __u8 len16; 1823 __be32 sendimmop_pkd; 1824 __be32 r3; 1825 __be32 plen; 1826 __be32 r4; 1827 __be64 r5; 1828 #ifndef C99_NOT_SUPPORTED 1829 struct fw_ri_immd immd_src[0]; 1830 #endif 1831 }; 1832 1833 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1834 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1835 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1836 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1837 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1838 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1839 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1840 1841 enum fw_ri_atomic_op { 1842 FW_RI_ATOMIC_OP_FETCHADD, 1843 FW_RI_ATOMIC_OP_SWAP, 1844 FW_RI_ATOMIC_OP_CMDSWAP, 1845 }; 1846 1847 struct fw_ri_atomic_wr { 1848 __u8 opcode; 1849 __u8 flags; 1850 __u16 wrid; 1851 __u8 r1[3]; 1852 __u8 len16; 1853 __be32 atomicop_pkd; 1854 __be64 r3; 1855 __be32 aopcode_pkd; 1856 __be32 reqid; 1857 __be32 stag; 1858 __be32 to_hi; 1859 __be32 to_lo; 1860 __be32 addswap_data_hi; 1861 __be32 addswap_data_lo; 1862 __be32 addswap_mask_hi; 1863 __be32 addswap_mask_lo; 1864 __be32 compare_data_hi; 1865 __be32 compare_data_lo; 1866 __be32 compare_mask_hi; 1867 __be32 compare_mask_lo; 1868 __be32 r5; 1869 }; 1870 1871 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1872 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1873 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 1874 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 1875 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 1876 1877 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 1878 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 1879 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 1880 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 1881 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 1882 1883 enum fw_ri_type { 1884 FW_RI_TYPE_INIT, 1885 FW_RI_TYPE_FINI, 1886 FW_RI_TYPE_TERMINATE 1887 }; 1888 1889 enum fw_ri_init_p2ptype { 1890 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 1891 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 1892 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 1893 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 1894 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 1895 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 1896 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 1897 }; 1898 1899 enum fw_ri_init_rqeqid_srq { 1900 FW_RI_INIT_RQEQID_SRQ = 1 << 31, 1901 }; 1902 1903 struct fw_ri_wr { 1904 __be32 op_compl; 1905 __be32 flowid_len16; 1906 __u64 cookie; 1907 union fw_ri { 1908 struct fw_ri_init { 1909 __u8 type; 1910 __u8 mpareqbit_p2ptype; 1911 __u8 r4[2]; 1912 __u8 mpa_attrs; 1913 __u8 qp_caps; 1914 __be16 nrqe; 1915 __be32 pdid; 1916 __be32 qpid; 1917 __be32 sq_eqid; 1918 __be32 rq_eqid; 1919 __be32 scqid; 1920 __be32 rcqid; 1921 __be32 ord_max; 1922 __be32 ird_max; 1923 __be32 iss; 1924 __be32 irs; 1925 __be32 hwrqsize; 1926 __be32 hwrqaddr; 1927 __be64 r5; 1928 union fw_ri_init_p2p { 1929 struct fw_ri_rdma_write_wr write; 1930 struct fw_ri_rdma_read_wr read; 1931 struct fw_ri_send_wr send; 1932 } u; 1933 } init; 1934 struct fw_ri_fini { 1935 __u8 type; 1936 __u8 r3[7]; 1937 __be64 r4; 1938 } fini; 1939 struct fw_ri_terminate { 1940 __u8 type; 1941 __u8 r3[3]; 1942 __be32 immdlen; 1943 __u8 termmsg[40]; 1944 } terminate; 1945 } u; 1946 }; 1947 1948 #define S_FW_RI_WR_MPAREQBIT 7 1949 #define M_FW_RI_WR_MPAREQBIT 0x1 1950 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 1951 #define G_FW_RI_WR_MPAREQBIT(x) \ 1952 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 1953 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 1954 1955 #define S_FW_RI_WR_0BRRBIT 6 1956 #define M_FW_RI_WR_0BRRBIT 0x1 1957 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 1958 #define G_FW_RI_WR_0BRRBIT(x) \ 1959 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 1960 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 1961 1962 #define S_FW_RI_WR_P2PTYPE 0 1963 #define M_FW_RI_WR_P2PTYPE 0xf 1964 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 1965 #define G_FW_RI_WR_P2PTYPE(x) \ 1966 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 1967 1968 /****************************************************************************** 1969 * F O i S C S I W O R K R E Q U E S T s 1970 *********************************************/ 1971 1972 #define FW_FOISCSI_NAME_MAX_LEN 224 1973 #define FW_FOISCSI_ALIAS_MAX_LEN 224 1974 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 1975 #define FW_FOISCSI_INIT_NODE_MAX 8 1976 1977 enum fw_chnet_ifconf_wr_subop { 1978 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 1979 1980 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 1981 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 1982 1983 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 1984 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 1985 1986 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 1987 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 1988 1989 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 1990 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 1991 1992 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 1993 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 1994 1995 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 1996 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 1997 1998 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 1999 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 2000 2001 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 2002 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 2003 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 2004 2005 FW_CHNET_IFCONF_WR_SUBOP_MAX, 2006 }; 2007 2008 struct fw_chnet_ifconf_wr { 2009 __be32 op_compl; 2010 __be32 flowid_len16; 2011 __be64 cookie; 2012 __be32 if_flowid; 2013 __u8 idx; 2014 __u8 subop; 2015 __u8 retval; 2016 __u8 r2; 2017 __be64 r3; 2018 struct fw_chnet_ifconf_params { 2019 __be32 r0; 2020 __be16 vlanid; 2021 __be16 mtu; 2022 union fw_chnet_ifconf_addr_type { 2023 struct fw_chnet_ifconf_ipv4 { 2024 __be32 addr; 2025 __be32 mask; 2026 __be32 router; 2027 __be32 r0; 2028 __be64 r1; 2029 } ipv4; 2030 struct fw_chnet_ifconf_ipv6 { 2031 __u8 prefix_len; 2032 __u8 r0; 2033 __be16 r1; 2034 __be32 r2; 2035 __be64 addr_hi; 2036 __be64 addr_lo; 2037 __be64 router_hi; 2038 __be64 router_lo; 2039 } ipv6; 2040 } in_attr; 2041 } param; 2042 }; 2043 2044 enum fw_foiscsi_node_type { 2045 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 2046 FW_FOISCSI_NODE_TYPE_TARGET, 2047 }; 2048 2049 enum fw_foiscsi_session_type { 2050 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 2051 FW_FOISCSI_SESSION_TYPE_NORMAL, 2052 }; 2053 2054 enum fw_foiscsi_auth_policy { 2055 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 2056 FW_FOISCSI_AUTH_POLICY_MUTUAL, 2057 }; 2058 2059 enum fw_foiscsi_auth_method { 2060 FW_FOISCSI_AUTH_METHOD_NONE = 0, 2061 FW_FOISCSI_AUTH_METHOD_CHAP, 2062 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 2063 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 2064 }; 2065 2066 enum fw_foiscsi_digest_type { 2067 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 2068 FW_FOISCSI_DIGEST_TYPE_CRC32, 2069 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 2070 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 2071 }; 2072 2073 enum fw_foiscsi_wr_subop { 2074 FW_FOISCSI_WR_SUBOP_ADD = 1, 2075 FW_FOISCSI_WR_SUBOP_DEL = 2, 2076 FW_FOISCSI_WR_SUBOP_MOD = 4, 2077 }; 2078 2079 enum fw_foiscsi_ctrl_state { 2080 FW_FOISCSI_CTRL_STATE_FREE = 0, 2081 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 2082 FW_FOISCSI_CTRL_STATE_FAILED, 2083 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 2084 FW_FOISCSI_CTRL_STATE_REDIRECT, 2085 }; 2086 2087 struct fw_rdev_wr { 2088 __be32 op_to_immdlen; 2089 __be32 alloc_to_len16; 2090 __be64 cookie; 2091 __u8 protocol; 2092 __u8 event_cause; 2093 __u8 cur_state; 2094 __u8 prev_state; 2095 __be32 flags_to_assoc_flowid; 2096 union rdev_entry { 2097 struct fcoe_rdev_entry { 2098 __be32 flowid; 2099 __u8 protocol; 2100 __u8 event_cause; 2101 __u8 flags; 2102 __u8 rjt_reason; 2103 __u8 cur_login_st; 2104 __u8 prev_login_st; 2105 __be16 rcv_fr_sz; 2106 __u8 rd_xfer_rdy_to_rport_type; 2107 __u8 vft_to_qos; 2108 __u8 org_proc_assoc_to_acc_rsp_code; 2109 __u8 enh_disc_to_tgt; 2110 __u8 wwnn[8]; 2111 __u8 wwpn[8]; 2112 __be16 iqid; 2113 __u8 fc_oui[3]; 2114 __u8 r_id[3]; 2115 } fcoe_rdev; 2116 struct iscsi_rdev_entry { 2117 __be32 flowid; 2118 __u8 protocol; 2119 __u8 event_cause; 2120 __u8 flags; 2121 __u8 r3; 2122 __be16 iscsi_opts; 2123 __be16 tcp_opts; 2124 __be16 ip_opts; 2125 __be16 max_rcv_len; 2126 __be16 max_snd_len; 2127 __be16 first_brst_len; 2128 __be16 max_brst_len; 2129 __be16 r4; 2130 __be16 def_time2wait; 2131 __be16 def_time2ret; 2132 __be16 nop_out_intrvl; 2133 __be16 non_scsi_to; 2134 __be16 isid; 2135 __be16 tsid; 2136 __be16 port; 2137 __be16 tpgt; 2138 __u8 r5[6]; 2139 __be16 iqid; 2140 } iscsi_rdev; 2141 } u; 2142 }; 2143 2144 #define S_FW_RDEV_WR_IMMDLEN 0 2145 #define M_FW_RDEV_WR_IMMDLEN 0xff 2146 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2147 #define G_FW_RDEV_WR_IMMDLEN(x) \ 2148 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2149 2150 #define S_FW_RDEV_WR_ALLOC 31 2151 #define M_FW_RDEV_WR_ALLOC 0x1 2152 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2153 #define G_FW_RDEV_WR_ALLOC(x) \ 2154 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2155 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2156 2157 #define S_FW_RDEV_WR_FREE 30 2158 #define M_FW_RDEV_WR_FREE 0x1 2159 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2160 #define G_FW_RDEV_WR_FREE(x) \ 2161 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2162 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2163 2164 #define S_FW_RDEV_WR_MODIFY 29 2165 #define M_FW_RDEV_WR_MODIFY 0x1 2166 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2167 #define G_FW_RDEV_WR_MODIFY(x) \ 2168 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2169 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2170 2171 #define S_FW_RDEV_WR_FLOWID 8 2172 #define M_FW_RDEV_WR_FLOWID 0xfffff 2173 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2174 #define G_FW_RDEV_WR_FLOWID(x) \ 2175 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2176 2177 #define S_FW_RDEV_WR_LEN16 0 2178 #define M_FW_RDEV_WR_LEN16 0xff 2179 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2180 #define G_FW_RDEV_WR_LEN16(x) \ 2181 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2182 2183 #define S_FW_RDEV_WR_FLAGS 24 2184 #define M_FW_RDEV_WR_FLAGS 0xff 2185 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2186 #define G_FW_RDEV_WR_FLAGS(x) \ 2187 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2188 2189 #define S_FW_RDEV_WR_GET_NEXT 20 2190 #define M_FW_RDEV_WR_GET_NEXT 0xf 2191 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2192 #define G_FW_RDEV_WR_GET_NEXT(x) \ 2193 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2194 2195 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 2196 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2197 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2198 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2199 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2200 2201 #define S_FW_RDEV_WR_RJT 7 2202 #define M_FW_RDEV_WR_RJT 0x1 2203 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2204 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2205 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2206 2207 #define S_FW_RDEV_WR_REASON 0 2208 #define M_FW_RDEV_WR_REASON 0x7f 2209 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2210 #define G_FW_RDEV_WR_REASON(x) \ 2211 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2212 2213 #define S_FW_RDEV_WR_RD_XFER_RDY 7 2214 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2215 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2216 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2217 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2218 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2219 2220 #define S_FW_RDEV_WR_WR_XFER_RDY 6 2221 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2222 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2223 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2224 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2225 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2226 2227 #define S_FW_RDEV_WR_FC_SP 5 2228 #define M_FW_RDEV_WR_FC_SP 0x1 2229 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2230 #define G_FW_RDEV_WR_FC_SP(x) \ 2231 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2232 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2233 2234 #define S_FW_RDEV_WR_RPORT_TYPE 0 2235 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2236 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2237 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2238 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2239 2240 #define S_FW_RDEV_WR_VFT 7 2241 #define M_FW_RDEV_WR_VFT 0x1 2242 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2243 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2244 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2245 2246 #define S_FW_RDEV_WR_NPIV 6 2247 #define M_FW_RDEV_WR_NPIV 0x1 2248 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2249 #define G_FW_RDEV_WR_NPIV(x) \ 2250 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2251 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2252 2253 #define S_FW_RDEV_WR_CLASS 4 2254 #define M_FW_RDEV_WR_CLASS 0x3 2255 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2256 #define G_FW_RDEV_WR_CLASS(x) \ 2257 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2258 2259 #define S_FW_RDEV_WR_SEQ_DEL 3 2260 #define M_FW_RDEV_WR_SEQ_DEL 0x1 2261 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2262 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2263 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2264 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2265 2266 #define S_FW_RDEV_WR_PRIO_PREEMP 2 2267 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2268 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2269 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2270 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2271 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2272 2273 #define S_FW_RDEV_WR_PREF 1 2274 #define M_FW_RDEV_WR_PREF 0x1 2275 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2276 #define G_FW_RDEV_WR_PREF(x) \ 2277 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2278 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2279 2280 #define S_FW_RDEV_WR_QOS 0 2281 #define M_FW_RDEV_WR_QOS 0x1 2282 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2283 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2284 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2285 2286 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2287 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2288 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2289 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2290 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2291 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2292 2293 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2294 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2295 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2296 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2297 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2298 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2299 2300 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2301 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2302 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2303 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2304 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2305 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2306 2307 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2308 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2309 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2310 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2311 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2312 2313 #define S_FW_RDEV_WR_ENH_DISC 7 2314 #define M_FW_RDEV_WR_ENH_DISC 0x1 2315 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2316 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2317 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2318 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2319 2320 #define S_FW_RDEV_WR_REC 6 2321 #define M_FW_RDEV_WR_REC 0x1 2322 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2323 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2324 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2325 2326 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2327 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2328 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2329 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2330 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2331 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2332 2333 #define S_FW_RDEV_WR_RETRY 4 2334 #define M_FW_RDEV_WR_RETRY 0x1 2335 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2336 #define G_FW_RDEV_WR_RETRY(x) \ 2337 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2338 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2339 2340 #define S_FW_RDEV_WR_CONF_CMPL 3 2341 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2342 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2343 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2344 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2345 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2346 2347 #define S_FW_RDEV_WR_DATA_OVLY 2 2348 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2349 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2350 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2351 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2352 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2353 2354 #define S_FW_RDEV_WR_INI 1 2355 #define M_FW_RDEV_WR_INI 0x1 2356 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2357 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2358 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2359 2360 #define S_FW_RDEV_WR_TGT 0 2361 #define M_FW_RDEV_WR_TGT 0x1 2362 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2363 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2364 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2365 2366 struct fw_foiscsi_node_wr { 2367 __be32 op_to_immdlen; 2368 __be32 flowid_len16; 2369 __u64 cookie; 2370 __u8 subop; 2371 __u8 status; 2372 __u8 alias_len; 2373 __u8 iqn_len; 2374 __be32 node_flowid; 2375 __be16 nodeid; 2376 __be16 login_retry; 2377 __be16 retry_timeout; 2378 __be16 r3; 2379 __u8 iqn[224]; 2380 __u8 alias[224]; 2381 }; 2382 2383 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2384 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2385 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2386 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2387 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2388 2389 struct fw_foiscsi_ctrl_wr { 2390 __be32 op_compl; 2391 __be32 flowid_len16; 2392 __u64 cookie; 2393 __u8 subop; 2394 __u8 status; 2395 __u8 ctrl_state; 2396 __u8 io_state; 2397 __be32 node_id; 2398 __be32 ctrl_id; 2399 __be32 io_id; 2400 struct fw_foiscsi_sess_attr { 2401 __be32 sess_type_to_erl; 2402 __be16 max_conn; 2403 __be16 max_r2t; 2404 __be16 time2wait; 2405 __be16 time2retain; 2406 __be32 max_burst; 2407 __be32 first_burst; 2408 __be32 r1; 2409 } sess_attr; 2410 struct fw_foiscsi_conn_attr { 2411 __be32 hdigest_to_ddp_pgsz; 2412 __be32 max_rcv_dsl; 2413 __be32 ping_tmo; 2414 __be16 dst_port; 2415 __be16 src_port; 2416 union fw_foiscsi_conn_attr_addr { 2417 struct fw_foiscsi_conn_attr_ipv6 { 2418 __be64 dst_addr[2]; 2419 __be64 src_addr[2]; 2420 } ipv6_addr; 2421 struct fw_foiscsi_conn_attr_ipv4 { 2422 __be32 dst_addr; 2423 __be32 src_addr; 2424 } ipv4_addr; 2425 } u; 2426 } conn_attr; 2427 __u8 tgt_name_len; 2428 __u8 r3[7]; 2429 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2430 }; 2431 2432 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2433 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2434 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2435 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2436 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2437 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2438 2439 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2440 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2441 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2442 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2443 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2444 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2445 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2446 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2447 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2448 2449 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2450 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2451 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2452 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2453 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2454 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2455 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2456 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2457 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2458 2459 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2460 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2461 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2462 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2463 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2464 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2465 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2466 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2467 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2468 2469 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2470 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2471 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2472 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2473 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2474 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2475 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2476 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2477 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2478 2479 #define S_FW_FOISCSI_CTRL_WR_ERL 24 2480 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2481 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2482 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2483 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2484 2485 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2486 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2487 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2488 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2489 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2490 2491 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2492 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2493 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2494 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2495 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2496 2497 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2498 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2499 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2500 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2501 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2502 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2503 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2504 2505 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2506 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2507 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2508 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2509 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2510 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2511 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2512 2513 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2514 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2515 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2516 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2517 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2518 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2519 2520 #define S_FW_FOISCSI_CTRL_WR_IPV6 20 2521 #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 2522 #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 2523 #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 2524 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 2525 #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 2526 2527 struct fw_foiscsi_chap_wr { 2528 __be32 op_compl; 2529 __be32 flowid_len16; 2530 __u64 cookie; 2531 __u8 status; 2532 __u8 id_len; 2533 __u8 sec_len; 2534 __u8 node_type; 2535 __be16 node_id; 2536 __u8 r3[2]; 2537 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2538 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 2539 }; 2540 2541 /****************************************************************************** 2542 * C O i S C S I W O R K R E Q U E S T S 2543 ********************************************/ 2544 2545 enum fw_chnet_addr_type { 2546 FW_CHNET_ADDD_TYPE_NONE = 0, 2547 FW_CHNET_ADDR_TYPE_IPV4, 2548 FW_CHNET_ADDR_TYPE_IPV6, 2549 }; 2550 2551 enum fw_msg_wr_type { 2552 FW_MSG_WR_TYPE_RPL = 0, 2553 FW_MSG_WR_TYPE_ERR, 2554 FW_MSG_WR_TYPE_PLD, 2555 }; 2556 2557 struct fw_coiscsi_tgt_wr { 2558 __be32 op_compl; 2559 __be32 flowid_len16; 2560 __u64 cookie; 2561 __u8 subop; 2562 __u8 status; 2563 __be16 r4; 2564 __be32 flags; 2565 struct fw_coiscsi_tgt_conn_attr { 2566 __be32 in_tid; 2567 __be16 in_port; 2568 __u8 in_type; 2569 __u8 r6; 2570 union fw_coiscsi_tgt_conn_attr_addr { 2571 struct fw_coiscsi_tgt_conn_attr_in_addr { 2572 __be32 addr; 2573 __be32 r7; 2574 __be32 r8[2]; 2575 } in_addr; 2576 struct fw_coiscsi_tgt_conn_attr_in_addr6 { 2577 __be64 addr[2]; 2578 } in_addr6; 2579 } u; 2580 } conn_attr; 2581 }; 2582 2583 struct fw_coiscsi_tgt_conn_wr { 2584 __be32 op_compl; 2585 __be32 flowid_len16; 2586 __u64 cookie; 2587 __u8 subop; 2588 __u8 status; 2589 __be16 iq_id; 2590 __be32 in_stid; 2591 __be32 io_id; 2592 __be32 flags; 2593 struct fw_coiscsi_tgt_conn_tcp { 2594 __be16 in_sport; 2595 __be16 in_dport; 2596 __be32 r4; 2597 union fw_coiscsi_tgt_conn_tcp_addr { 2598 struct fw_coiscsi_tgt_conn_tcp_in_addr { 2599 __be32 saddr; 2600 __be32 daddr; 2601 } in_addr; 2602 struct fw_coiscsi_tgt_conn_tcp_in_addr6 { 2603 __be64 saddr[2]; 2604 __be64 daddr[2]; 2605 } in_addr6; 2606 } u; 2607 } conn_tcp; 2608 struct fw_coiscsi_tgt_conn_iscsi { 2609 __be32 hdigest_to_ddp_pgsz; 2610 __be32 tgt_id; 2611 __be16 max_r2t; 2612 __be16 r5; 2613 __be32 max_burst; 2614 __be32 max_rdsl; 2615 __be32 max_tdsl; 2616 __be32 nxt_sn; 2617 __be32 r6; 2618 } conn_iscsi; 2619 }; 2620 2621 struct fw_coiscsi_tgt_xmit_wr { 2622 __be32 op_to_immdlen; 2623 __be32 flowid_len16; 2624 __be64 cookie; 2625 __be16 iq_id; 2626 __be16 r4; 2627 __be32 datasn; 2628 __be32 t_xfer_len; 2629 __be32 flags; 2630 __be32 tag; 2631 __be32 tidx; 2632 __be32 r5[2]; 2633 }; 2634 2635 #define S_FW_COiSCSI_TGT_XMIT_WR_DDGST 23 2636 #define M_FW_COiSCSI_TGT_XMIT_WR_DDGST 0x1 2637 #define V_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 2638 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDGST) 2639 #define G_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 2640 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDGST) & M_FW_COiSCSI_TGT_XMIT_WR_DDGST) 2641 #define F_FW_COiSCSI_TGT_XMIT_WR_DDGST V_FW_COiSCSI_TGT_XMIT_WR_DDGST(1U) 2642 2643 #define S_FW_COiSCSI_TGT_XMIT_WR_HDGST 22 2644 #define M_FW_COiSCSI_TGT_XMIT_WR_HDGST 0x1 2645 #define V_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 2646 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_HDGST) 2647 #define G_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 2648 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_HDGST) & M_FW_COiSCSI_TGT_XMIT_WR_HDGST) 2649 #define F_FW_COiSCSI_TGT_XMIT_WR_HDGST V_FW_COiSCSI_TGT_XMIT_WR_HDGST(1U) 2650 2651 #define S_FW_COiSCSI_TGT_XMIT_WR_DDP 20 2652 #define M_FW_COiSCSI_TGT_XMIT_WR_DDP 0x1 2653 #define V_FW_COiSCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDP) 2654 #define G_FW_COiSCSI_TGT_XMIT_WR_DDP(x) \ 2655 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDP) & M_FW_COiSCSI_TGT_XMIT_WR_DDP) 2656 #define F_FW_COiSCSI_TGT_XMIT_WR_DDP V_FW_COiSCSI_TGT_XMIT_WR_DDP(1U) 2657 2658 #define S_FW_COiSCSI_TGT_XMIT_WR_ABORT 19 2659 #define M_FW_COiSCSI_TGT_XMIT_WR_ABORT 0x1 2660 #define V_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \ 2661 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_ABORT) 2662 #define G_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \ 2663 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_ABORT) & M_FW_COiSCSI_TGT_XMIT_WR_ABORT) 2664 #define F_FW_COiSCSI_TGT_XMIT_WR_ABORT V_FW_COiSCSI_TGT_XMIT_WR_ABORT(1U) 2665 2666 #define S_FW_COiSCSI_TGT_XMIT_WR_FINAL 18 2667 #define M_FW_COiSCSI_TGT_XMIT_WR_FINAL 0x1 2668 #define V_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \ 2669 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_FINAL) 2670 #define G_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \ 2671 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_FINAL) & M_FW_COiSCSI_TGT_XMIT_WR_FINAL) 2672 #define F_FW_COiSCSI_TGT_XMIT_WR_FINAL V_FW_COiSCSI_TGT_XMIT_WR_FINAL(1U) 2673 2674 #define S_FW_COiSCSI_TGT_XMIT_WR_PADLEN 16 2675 #define M_FW_COiSCSI_TGT_XMIT_WR_PADLEN 0x3 2676 #define V_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \ 2677 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) 2678 #define G_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \ 2679 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) & \ 2680 M_FW_COiSCSI_TGT_XMIT_WR_PADLEN) 2681 2682 #define S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0 2683 #define M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0xff 2684 #define V_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2685 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 2686 #define G_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2687 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) & \ 2688 M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 2689 2690 struct fw_isns_wr { 2691 __be32 op_compl; 2692 __be32 flowid_len16; 2693 __u64 cookie; 2694 __u8 subop; 2695 __u8 status; 2696 __be16 iq_id; 2697 __be32 r4; 2698 struct fw_tcp_conn_attr { 2699 __be32 in_tid; 2700 __be16 in_port; 2701 __u8 in_type; 2702 __u8 r6; 2703 union fw_tcp_conn_attr_addr { 2704 struct fw_tcp_conn_attr_in_addr { 2705 __be32 addr; 2706 __be32 r7; 2707 __be32 r8[2]; 2708 } in_addr; 2709 struct fw_tcp_conn_attr_in_addr6 { 2710 __be64 addr[2]; 2711 } in_addr6; 2712 } u; 2713 } conn_attr; 2714 }; 2715 2716 struct fw_isns_xmit_wr { 2717 __be32 op_to_immdlen; 2718 __be32 flowid_len16; 2719 __be64 cookie; 2720 __be16 iq_id; 2721 __be16 r4; 2722 __be32 xfer_len; 2723 __be64 r5; 2724 }; 2725 2726 #define S_FW_ISNS_XMIT_WR_IMMDLEN 0 2727 #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff 2728 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) 2729 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ 2730 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN) 2731 2732 /****************************************************************************** 2733 * F O F C O E W O R K R E Q U E S T s 2734 *******************************************/ 2735 2736 struct fw_fcoe_els_ct_wr { 2737 __be32 op_immdlen; 2738 __be32 flowid_len16; 2739 __be64 cookie; 2740 __be16 iqid; 2741 __u8 tmo_val; 2742 __u8 els_ct_type; 2743 __u8 ctl_pri; 2744 __u8 cp_en_class; 2745 __be16 xfer_cnt; 2746 __u8 fl_to_sp; 2747 __u8 l_id[3]; 2748 __u8 r5; 2749 __u8 r_id[3]; 2750 __be64 rsp_dmaaddr; 2751 __be32 rsp_dmalen; 2752 __be32 r6; 2753 }; 2754 2755 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2756 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2757 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2758 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2759 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2760 2761 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2762 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2763 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2764 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2765 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2766 2767 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2768 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2769 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2770 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2771 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2772 2773 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 2774 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2775 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2776 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2777 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2778 2779 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2780 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2781 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2782 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2783 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2784 2785 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 2786 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2787 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2788 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2789 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2790 2791 #define S_FW_FCOE_ELS_CT_WR_FL 2 2792 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 2793 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2794 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2795 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2796 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2797 2798 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 2799 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2800 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2801 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2802 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2803 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2804 2805 #define S_FW_FCOE_ELS_CT_WR_SP 0 2806 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 2807 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2808 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2809 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2810 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2811 2812 /****************************************************************************** 2813 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 2814 *****************************************************************************/ 2815 2816 struct fw_scsi_write_wr { 2817 __be32 op_immdlen; 2818 __be32 flowid_len16; 2819 __be64 cookie; 2820 __be16 iqid; 2821 __u8 tmo_val; 2822 __u8 use_xfer_cnt; 2823 union fw_scsi_write_priv { 2824 struct fcoe_write_priv { 2825 __u8 ctl_pri; 2826 __u8 cp_en_class; 2827 __u8 r3_lo[2]; 2828 } fcoe; 2829 struct iscsi_write_priv { 2830 __u8 r3[4]; 2831 } iscsi; 2832 } u; 2833 __be32 xfer_cnt; 2834 __be32 ini_xfer_cnt; 2835 __be64 rsp_dmaaddr; 2836 __be32 rsp_dmalen; 2837 __be32 r4; 2838 }; 2839 2840 #define S_FW_SCSI_WRITE_WR_OPCODE 24 2841 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2842 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2843 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2844 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2845 2846 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2847 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2848 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2849 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2850 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2851 2852 #define S_FW_SCSI_WRITE_WR_FLOWID 8 2853 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2854 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2855 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2856 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2857 2858 #define S_FW_SCSI_WRITE_WR_LEN16 0 2859 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 2860 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2861 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 2862 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 2863 2864 #define S_FW_SCSI_WRITE_WR_CP_EN 6 2865 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 2866 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 2867 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 2868 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 2869 2870 #define S_FW_SCSI_WRITE_WR_CLASS 4 2871 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 2872 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 2873 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 2874 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 2875 2876 struct fw_scsi_read_wr { 2877 __be32 op_immdlen; 2878 __be32 flowid_len16; 2879 __be64 cookie; 2880 __be16 iqid; 2881 __u8 tmo_val; 2882 __u8 use_xfer_cnt; 2883 union fw_scsi_read_priv { 2884 struct fcoe_read_priv { 2885 __u8 ctl_pri; 2886 __u8 cp_en_class; 2887 __u8 r3_lo[2]; 2888 } fcoe; 2889 struct iscsi_read_priv { 2890 __u8 r3[4]; 2891 } iscsi; 2892 } u; 2893 __be32 xfer_cnt; 2894 __be32 ini_xfer_cnt; 2895 __be64 rsp_dmaaddr; 2896 __be32 rsp_dmalen; 2897 __be32 r4; 2898 }; 2899 2900 #define S_FW_SCSI_READ_WR_OPCODE 24 2901 #define M_FW_SCSI_READ_WR_OPCODE 0xff 2902 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 2903 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 2904 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 2905 2906 #define S_FW_SCSI_READ_WR_IMMDLEN 0 2907 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 2908 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 2909 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 2910 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 2911 2912 #define S_FW_SCSI_READ_WR_FLOWID 8 2913 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 2914 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 2915 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 2916 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 2917 2918 #define S_FW_SCSI_READ_WR_LEN16 0 2919 #define M_FW_SCSI_READ_WR_LEN16 0xff 2920 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 2921 #define G_FW_SCSI_READ_WR_LEN16(x) \ 2922 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 2923 2924 #define S_FW_SCSI_READ_WR_CP_EN 6 2925 #define M_FW_SCSI_READ_WR_CP_EN 0x3 2926 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 2927 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 2928 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 2929 2930 #define S_FW_SCSI_READ_WR_CLASS 4 2931 #define M_FW_SCSI_READ_WR_CLASS 0x3 2932 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 2933 #define G_FW_SCSI_READ_WR_CLASS(x) \ 2934 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 2935 2936 struct fw_scsi_cmd_wr { 2937 __be32 op_immdlen; 2938 __be32 flowid_len16; 2939 __be64 cookie; 2940 __be16 iqid; 2941 __u8 tmo_val; 2942 __u8 r3; 2943 union fw_scsi_cmd_priv { 2944 struct fcoe_cmd_priv { 2945 __u8 ctl_pri; 2946 __u8 cp_en_class; 2947 __u8 r4_lo[2]; 2948 } fcoe; 2949 struct iscsi_cmd_priv { 2950 __u8 r4[4]; 2951 } iscsi; 2952 } u; 2953 __u8 r5[8]; 2954 __be64 rsp_dmaaddr; 2955 __be32 rsp_dmalen; 2956 __be32 r6; 2957 }; 2958 2959 #define S_FW_SCSI_CMD_WR_OPCODE 24 2960 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 2961 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 2962 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 2963 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 2964 2965 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 2966 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 2967 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 2968 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 2969 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 2970 2971 #define S_FW_SCSI_CMD_WR_FLOWID 8 2972 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 2973 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 2974 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 2975 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 2976 2977 #define S_FW_SCSI_CMD_WR_LEN16 0 2978 #define M_FW_SCSI_CMD_WR_LEN16 0xff 2979 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 2980 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 2981 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 2982 2983 #define S_FW_SCSI_CMD_WR_CP_EN 6 2984 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 2985 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 2986 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 2987 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 2988 2989 #define S_FW_SCSI_CMD_WR_CLASS 4 2990 #define M_FW_SCSI_CMD_WR_CLASS 0x3 2991 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 2992 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 2993 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 2994 2995 struct fw_scsi_abrt_cls_wr { 2996 __be32 op_immdlen; 2997 __be32 flowid_len16; 2998 __be64 cookie; 2999 __be16 iqid; 3000 __u8 tmo_val; 3001 __u8 sub_opcode_to_chk_all_io; 3002 __u8 r3[4]; 3003 __be64 t_cookie; 3004 }; 3005 3006 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 3007 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 3008 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 3009 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 3010 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 3011 3012 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 3013 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 3014 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3015 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3016 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3017 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3018 3019 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 3020 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 3021 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 3022 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 3023 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 3024 3025 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 3026 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 3027 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 3028 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 3029 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 3030 3031 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 3032 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 3033 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3034 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3035 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3036 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 3037 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3038 3039 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 3040 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 3041 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 3042 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 3043 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 3044 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 3045 3046 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 3047 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 3048 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3049 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3050 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3051 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 3052 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3053 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 3054 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 3055 3056 struct fw_scsi_tgt_acc_wr { 3057 __be32 op_immdlen; 3058 __be32 flowid_len16; 3059 __be64 cookie; 3060 __be16 iqid; 3061 __u8 r3; 3062 __u8 use_burst_len; 3063 union fw_scsi_tgt_acc_priv { 3064 struct fcoe_tgt_acc_priv { 3065 __u8 ctl_pri; 3066 __u8 cp_en_class; 3067 __u8 r4_lo[2]; 3068 } fcoe; 3069 struct iscsi_tgt_acc_priv { 3070 __u8 r4[4]; 3071 } iscsi; 3072 } u; 3073 __be32 burst_len; 3074 __be32 rel_off; 3075 __be64 r5; 3076 __be32 r6; 3077 __be32 tot_xfer_len; 3078 }; 3079 3080 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 3081 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 3082 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 3083 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 3084 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 3085 3086 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 3087 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 3088 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3089 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 3090 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3091 3092 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 3093 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 3094 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 3095 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 3096 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 3097 3098 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 3099 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 3100 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 3101 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 3102 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 3103 3104 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 3105 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 3106 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 3107 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 3108 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 3109 3110 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 3111 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 3112 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 3113 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 3114 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 3115 3116 struct fw_scsi_tgt_xmit_wr { 3117 __be32 op_immdlen; 3118 __be32 flowid_len16; 3119 __be64 cookie; 3120 __be16 iqid; 3121 __u8 auto_rsp; 3122 __u8 use_xfer_cnt; 3123 union fw_scsi_tgt_xmit_priv { 3124 struct fcoe_tgt_xmit_priv { 3125 __u8 ctl_pri; 3126 __u8 cp_en_class; 3127 __u8 r3_lo[2]; 3128 } fcoe; 3129 struct iscsi_tgt_xmit_priv { 3130 __u8 r3[4]; 3131 } iscsi; 3132 } u; 3133 __be32 xfer_cnt; 3134 __be32 r4; 3135 __be64 r5; 3136 __be32 r6; 3137 __be32 tot_xfer_len; 3138 }; 3139 3140 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 3141 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 3142 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 3143 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 3144 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 3145 3146 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 3147 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 3148 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3149 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3150 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3151 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3152 3153 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 3154 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 3155 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 3156 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 3157 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 3158 3159 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 3160 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 3161 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 3162 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 3163 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 3164 3165 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 3166 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 3167 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 3168 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 3169 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 3170 3171 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 3172 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 3173 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 3174 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 3175 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 3176 3177 struct fw_scsi_tgt_rsp_wr { 3178 __be32 op_immdlen; 3179 __be32 flowid_len16; 3180 __be64 cookie; 3181 __be16 iqid; 3182 __u8 r3[2]; 3183 union fw_scsi_tgt_rsp_priv { 3184 struct fcoe_tgt_rsp_priv { 3185 __u8 ctl_pri; 3186 __u8 cp_en_class; 3187 __u8 r4_lo[2]; 3188 } fcoe; 3189 struct iscsi_tgt_rsp_priv { 3190 __u8 r4[4]; 3191 } iscsi; 3192 } u; 3193 __u8 r5[8]; 3194 }; 3195 3196 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 3197 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 3198 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 3199 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 3200 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 3201 3202 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 3203 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 3204 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3205 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 3206 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3207 3208 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 3209 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 3210 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 3211 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 3212 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 3213 3214 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 3215 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 3216 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 3217 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 3218 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 3219 3220 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 3221 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 3222 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 3223 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 3224 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 3225 3226 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 3227 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 3228 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 3229 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 3230 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 3231 3232 struct fw_pofcoe_tcb_wr { 3233 __be32 op_compl; 3234 __be32 equiq_to_len16; 3235 __be32 r4; 3236 __be32 xfer_len; 3237 __be32 tid_to_port; 3238 __be16 x_id; 3239 __be16 vlan_id; 3240 __be64 cookie; 3241 __be32 s_id; 3242 __be32 d_id; 3243 __be32 tag; 3244 __be16 r6; 3245 __be16 iqid; 3246 }; 3247 3248 #define S_FW_POFCOE_TCB_WR_TID 12 3249 #define M_FW_POFCOE_TCB_WR_TID 0xfffff 3250 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 3251 #define G_FW_POFCOE_TCB_WR_TID(x) \ 3252 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 3253 3254 #define S_FW_POFCOE_TCB_WR_ALLOC 4 3255 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 3256 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 3257 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 3258 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 3259 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 3260 3261 #define S_FW_POFCOE_TCB_WR_FREE 3 3262 #define M_FW_POFCOE_TCB_WR_FREE 0x1 3263 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 3264 #define G_FW_POFCOE_TCB_WR_FREE(x) \ 3265 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 3266 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 3267 3268 #define S_FW_POFCOE_TCB_WR_PORT 0 3269 #define M_FW_POFCOE_TCB_WR_PORT 0x7 3270 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 3271 #define G_FW_POFCOE_TCB_WR_PORT(x) \ 3272 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 3273 3274 struct fw_pofcoe_ulptx_wr { 3275 __be32 op_pkd; 3276 __be32 equiq_to_len16; 3277 __u64 cookie; 3278 }; 3279 3280 /******************************************************************* 3281 * T10 DIF related definition 3282 *******************************************************************/ 3283 struct fw_tx_pi_header { 3284 __be16 op_to_inline; 3285 __u8 pi_interval_tag_type; 3286 __u8 num_pi; 3287 __be32 pi_start4_pi_end4; 3288 __u8 tag_gen_enabled_pkd; 3289 __u8 num_pi_dsg; 3290 __be16 app_tag; 3291 __be32 ref_tag; 3292 }; 3293 3294 #define S_FW_TX_PI_HEADER_OP 8 3295 #define M_FW_TX_PI_HEADER_OP 0xff 3296 #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) 3297 #define G_FW_TX_PI_HEADER_OP(x) \ 3298 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) 3299 3300 #define S_FW_TX_PI_HEADER_ULPTXMORE 7 3301 #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 3302 #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) 3303 #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ 3304 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) 3305 #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) 3306 3307 #define S_FW_TX_PI_HEADER_PI_CONTROL 4 3308 #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 3309 #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) 3310 #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ 3311 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) 3312 3313 #define S_FW_TX_PI_HEADER_GUARD_TYPE 2 3314 #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 3315 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) 3316 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ 3317 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) 3318 #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) 3319 3320 #define S_FW_TX_PI_HEADER_VALIDATE 1 3321 #define M_FW_TX_PI_HEADER_VALIDATE 0x1 3322 #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) 3323 #define G_FW_TX_PI_HEADER_VALIDATE(x) \ 3324 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) 3325 #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) 3326 3327 #define S_FW_TX_PI_HEADER_INLINE 0 3328 #define M_FW_TX_PI_HEADER_INLINE 0x1 3329 #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) 3330 #define G_FW_TX_PI_HEADER_INLINE(x) \ 3331 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) 3332 #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) 3333 3334 #define S_FW_TX_PI_HEADER_PI_INTERVAL 7 3335 #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 3336 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3337 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) 3338 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3339 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) 3340 #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) 3341 3342 #define S_FW_TX_PI_HEADER_TAG_TYPE 5 3343 #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 3344 #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) 3345 #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ 3346 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) 3347 3348 #define S_FW_TX_PI_HEADER_PI_START4 22 3349 #define M_FW_TX_PI_HEADER_PI_START4 0x3ff 3350 #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) 3351 #define G_FW_TX_PI_HEADER_PI_START4(x) \ 3352 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) 3353 3354 #define S_FW_TX_PI_HEADER_PI_END4 0 3355 #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff 3356 #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) 3357 #define G_FW_TX_PI_HEADER_PI_END4(x) \ 3358 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) 3359 3360 #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 3361 #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 3362 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3363 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3364 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3365 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ 3366 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3367 3368 enum fw_pi_error_type { 3369 FW_PI_ERROR_GUARD_CHECK_FAILED = 0, 3370 }; 3371 3372 struct fw_pi_error { 3373 __be32 err_type_pkd; 3374 __be32 flowid_len16; 3375 __be16 r2; 3376 __be16 app_tag; 3377 __be32 ref_tag; 3378 __be32 pisc[4]; 3379 }; 3380 3381 #define S_FW_PI_ERROR_ERR_TYPE 24 3382 #define M_FW_PI_ERROR_ERR_TYPE 0xff 3383 #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) 3384 #define G_FW_PI_ERROR_ERR_TYPE(x) \ 3385 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) 3386 3387 3388 struct fw_sec_lookaside_lpbk_wr { 3389 __be32 op_to_cctx_size; 3390 __be32 len16_pkd; 3391 __be32 session_id; 3392 __be32 rx_chid_to_rx_q_id; 3393 __be32 key_addr; 3394 __be32 pld_size_hash_size; 3395 __be64 cookie; 3396 }; 3397 3398 #define S_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE 24 3399 #define M_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE 0xff 3400 #define V_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE(x) \ 3401 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE) 3402 #define G_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE(x) \ 3403 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE) & \ 3404 M_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE) 3405 3406 #define S_FW_SEC_LOOKASIDE_LPBK_WR_COMPL 23 3407 #define M_FW_SEC_LOOKASIDE_LPBK_WR_COMPL 0x1 3408 #define V_FW_SEC_LOOKASIDE_LPBK_WR_COMPL(x) \ 3409 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_COMPL) 3410 #define G_FW_SEC_LOOKASIDE_LPBK_WR_COMPL(x) \ 3411 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_COMPL) & \ 3412 M_FW_SEC_LOOKASIDE_LPBK_WR_COMPL) 3413 #define F_FW_SEC_LOOKASIDE_LPBK_WR_COMPL V_FW_SEC_LOOKASIDE_LPBK_WR_COMPL(1U) 3414 3415 #define S_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN 15 3416 #define M_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN 0xff 3417 #define V_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN(x) \ 3418 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN) 3419 #define G_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN(x) \ 3420 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN) & \ 3421 M_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN) 3422 3423 #define S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC 5 3424 #define M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC 0x3 3425 #define V_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC(x) \ 3426 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC) 3427 #define G_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC(x) \ 3428 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC) & \ 3429 M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC) 3430 3431 #define S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE 0 3432 #define M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE 0x1f 3433 #define V_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE(x) \ 3434 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE) 3435 #define G_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE(x) \ 3436 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE) & \ 3437 M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE) 3438 3439 #define S_FW_SEC_LOOKASIDE_LPBK_WR_LEN16 0 3440 #define M_FW_SEC_LOOKASIDE_LPBK_WR_LEN16 0xff 3441 #define V_FW_SEC_LOOKASIDE_LPBK_WR_LEN16(x) \ 3442 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_LEN16) 3443 #define G_FW_SEC_LOOKASIDE_LPBK_WR_LEN16(x) \ 3444 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_LEN16) & \ 3445 M_FW_SEC_LOOKASIDE_LPBK_WR_LEN16) 3446 3447 #define S_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID 29 3448 #define M_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID 0x3 3449 #define V_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID(x) \ 3450 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID) 3451 #define G_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID(x) \ 3452 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID) & \ 3453 M_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID) 3454 3455 #define S_FW_SEC_LOOKASIDE_LPBK_WR_LCB 27 3456 #define M_FW_SEC_LOOKASIDE_LPBK_WR_LCB 0x3 3457 #define V_FW_SEC_LOOKASIDE_LPBK_WR_LCB(x) \ 3458 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_LCB) 3459 #define G_FW_SEC_LOOKASIDE_LPBK_WR_LCB(x) \ 3460 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_LCB) & M_FW_SEC_LOOKASIDE_LPBK_WR_LCB) 3461 3462 #define S_FW_SEC_LOOKASIDE_LPBK_WR_PHASH 25 3463 #define M_FW_SEC_LOOKASIDE_LPBK_WR_PHASH 0x3 3464 #define V_FW_SEC_LOOKASIDE_LPBK_WR_PHASH(x) \ 3465 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_PHASH) 3466 #define G_FW_SEC_LOOKASIDE_LPBK_WR_PHASH(x) \ 3467 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_PHASH) & \ 3468 M_FW_SEC_LOOKASIDE_LPBK_WR_PHASH) 3469 3470 #define S_FW_SEC_LOOKASIDE_LPBK_WR_IV 23 3471 #define M_FW_SEC_LOOKASIDE_LPBK_WR_IV 0x3 3472 #define V_FW_SEC_LOOKASIDE_LPBK_WR_IV(x) \ 3473 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_IV) 3474 #define G_FW_SEC_LOOKASIDE_LPBK_WR_IV(x) \ 3475 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_IV) & M_FW_SEC_LOOKASIDE_LPBK_WR_IV) 3476 3477 #define S_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH 10 3478 #define M_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH 0x3 3479 #define V_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH(x) \ 3480 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH) 3481 #define G_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH(x) \ 3482 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH) & \ 3483 M_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH) 3484 3485 #define S_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID 0 3486 #define M_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID 0x3ff 3487 #define V_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID(x) \ 3488 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID) 3489 #define G_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID(x) \ 3490 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID) & \ 3491 M_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID) 3492 3493 #define S_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE 24 3494 #define M_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE 0xff 3495 #define V_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE(x) \ 3496 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE) 3497 #define G_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE(x) \ 3498 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE) & \ 3499 M_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE) 3500 3501 #define S_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE 17 3502 #define M_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE 0x7f 3503 #define V_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE(x) \ 3504 ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE) 3505 #define G_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE(x) \ 3506 (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE) & \ 3507 M_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE) 3508 3509 /****************************************************************************** 3510 * C O M M A N D s 3511 *********************/ 3512 3513 /* 3514 * The maximum length of time, in miliseconds, that we expect any firmware 3515 * command to take to execute and return a reply to the host. The RESET 3516 * and INITIALIZE commands can take a fair amount of time to execute but 3517 * most execute in far less time than this maximum. This constant is used 3518 * by host software to determine how long to wait for a firmware command 3519 * reply before declaring the firmware as dead/unreachable ... 3520 */ 3521 #define FW_CMD_MAX_TIMEOUT 10000 3522 3523 /* 3524 * If a host driver does a HELLO and discovers that there's already a MASTER 3525 * selected, we may have to wait for that MASTER to finish issuing RESET, 3526 * configuration and INITIALIZE commands. Also, there's a possibility that 3527 * our own HELLO may get lost if it happens right as the MASTER is issuign a 3528 * RESET command, so we need to be willing to make a few retries of our HELLO. 3529 */ 3530 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 3531 #define FW_CMD_HELLO_RETRIES 3 3532 3533 enum fw_cmd_opcodes { 3534 FW_LDST_CMD = 0x01, 3535 FW_RESET_CMD = 0x03, 3536 FW_HELLO_CMD = 0x04, 3537 FW_BYE_CMD = 0x05, 3538 FW_INITIALIZE_CMD = 0x06, 3539 FW_CAPS_CONFIG_CMD = 0x07, 3540 FW_PARAMS_CMD = 0x08, 3541 FW_PFVF_CMD = 0x09, 3542 FW_IQ_CMD = 0x10, 3543 FW_EQ_MNGT_CMD = 0x11, 3544 FW_EQ_ETH_CMD = 0x12, 3545 FW_EQ_CTRL_CMD = 0x13, 3546 FW_EQ_OFLD_CMD = 0x21, 3547 FW_VI_CMD = 0x14, 3548 FW_VI_MAC_CMD = 0x15, 3549 FW_VI_RXMODE_CMD = 0x16, 3550 FW_VI_ENABLE_CMD = 0x17, 3551 FW_VI_STATS_CMD = 0x1a, 3552 FW_ACL_MAC_CMD = 0x18, 3553 FW_ACL_VLAN_CMD = 0x19, 3554 FW_PORT_CMD = 0x1b, 3555 FW_PORT_STATS_CMD = 0x1c, 3556 FW_PORT_LB_STATS_CMD = 0x1d, 3557 FW_PORT_TRACE_CMD = 0x1e, 3558 FW_PORT_TRACE_MMAP_CMD = 0x1f, 3559 FW_RSS_IND_TBL_CMD = 0x20, 3560 FW_RSS_GLB_CONFIG_CMD = 0x22, 3561 FW_RSS_VI_CONFIG_CMD = 0x23, 3562 FW_SCHED_CMD = 0x24, 3563 FW_DEVLOG_CMD = 0x25, 3564 FW_WATCHDOG_CMD = 0x27, 3565 FW_CLIP_CMD = 0x28, 3566 FW_CHNET_IFACE_CMD = 0x26, 3567 FW_FCOE_RES_INFO_CMD = 0x31, 3568 FW_FCOE_LINK_CMD = 0x32, 3569 FW_FCOE_VNP_CMD = 0x33, 3570 FW_FCOE_SPARAMS_CMD = 0x35, 3571 FW_FCOE_STATS_CMD = 0x37, 3572 FW_FCOE_FCF_CMD = 0x38, 3573 FW_DCB_IEEE_CMD = 0x3a, 3574 FW_PTP_CMD = 0x3e, 3575 FW_LASTC2E_CMD = 0x40, 3576 FW_ERROR_CMD = 0x80, 3577 FW_DEBUG_CMD = 0x81, 3578 }; 3579 3580 enum fw_cmd_cap { 3581 FW_CMD_CAP_PF = 0x01, 3582 FW_CMD_CAP_DMAQ = 0x02, 3583 FW_CMD_CAP_PORT = 0x04, 3584 FW_CMD_CAP_PORTPROMISC = 0x08, 3585 FW_CMD_CAP_PORTSTATS = 0x10, 3586 FW_CMD_CAP_VF = 0x80, 3587 }; 3588 3589 /* 3590 * Generic command header flit0 3591 */ 3592 struct fw_cmd_hdr { 3593 __be32 hi; 3594 __be32 lo; 3595 }; 3596 3597 #define S_FW_CMD_OP 24 3598 #define M_FW_CMD_OP 0xff 3599 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 3600 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 3601 3602 #define S_FW_CMD_REQUEST 23 3603 #define M_FW_CMD_REQUEST 0x1 3604 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 3605 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 3606 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 3607 3608 #define S_FW_CMD_READ 22 3609 #define M_FW_CMD_READ 0x1 3610 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 3611 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 3612 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 3613 3614 #define S_FW_CMD_WRITE 21 3615 #define M_FW_CMD_WRITE 0x1 3616 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 3617 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 3618 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 3619 3620 #define S_FW_CMD_EXEC 20 3621 #define M_FW_CMD_EXEC 0x1 3622 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 3623 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 3624 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 3625 3626 #define S_FW_CMD_RAMASK 20 3627 #define M_FW_CMD_RAMASK 0xf 3628 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 3629 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 3630 3631 #define S_FW_CMD_RETVAL 8 3632 #define M_FW_CMD_RETVAL 0xff 3633 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 3634 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 3635 3636 #define S_FW_CMD_LEN16 0 3637 #define M_FW_CMD_LEN16 0xff 3638 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 3639 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 3640 3641 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 3642 3643 /* 3644 * address spaces 3645 */ 3646 enum fw_ldst_addrspc { 3647 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 3648 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 3649 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 3650 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 3651 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 3652 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 3653 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 3654 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 3655 FW_LDST_ADDRSPC_MDIO = 0x0018, 3656 FW_LDST_ADDRSPC_MPS = 0x0020, 3657 FW_LDST_ADDRSPC_FUNC = 0x0028, 3658 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 3659 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 3660 FW_LDST_ADDRSPC_LE = 0x0030, 3661 FW_LDST_ADDRSPC_I2C = 0x0038, 3662 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 3663 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 3664 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 3665 FW_LDST_ADDRSPC_CIM_Q = 0x0048, 3666 }; 3667 3668 /* 3669 * MDIO VSC8634 register access control field 3670 */ 3671 enum fw_ldst_mdio_vsc8634_aid { 3672 FW_LDST_MDIO_VS_STANDARD, 3673 FW_LDST_MDIO_VS_EXTENDED, 3674 FW_LDST_MDIO_VS_GPIO 3675 }; 3676 3677 enum fw_ldst_mps_fid { 3678 FW_LDST_MPS_ATRB, 3679 FW_LDST_MPS_RPLC 3680 }; 3681 3682 enum fw_ldst_func_access_ctl { 3683 FW_LDST_FUNC_ACC_CTL_VIID, 3684 FW_LDST_FUNC_ACC_CTL_FID 3685 }; 3686 3687 enum fw_ldst_func_mod_index { 3688 FW_LDST_FUNC_MPS 3689 }; 3690 3691 struct fw_ldst_cmd { 3692 __be32 op_to_addrspace; 3693 __be32 cycles_to_len16; 3694 union fw_ldst { 3695 struct fw_ldst_addrval { 3696 __be32 addr; 3697 __be32 val; 3698 } addrval; 3699 struct fw_ldst_idctxt { 3700 __be32 physid; 3701 __be32 msg_ctxtflush; 3702 __be32 ctxt_data7; 3703 __be32 ctxt_data6; 3704 __be32 ctxt_data5; 3705 __be32 ctxt_data4; 3706 __be32 ctxt_data3; 3707 __be32 ctxt_data2; 3708 __be32 ctxt_data1; 3709 __be32 ctxt_data0; 3710 } idctxt; 3711 struct fw_ldst_mdio { 3712 __be16 paddr_mmd; 3713 __be16 raddr; 3714 __be16 vctl; 3715 __be16 rval; 3716 } mdio; 3717 struct fw_ldst_cim_rq { 3718 __u8 req_first64[8]; 3719 __u8 req_second64[8]; 3720 __u8 resp_first64[8]; 3721 __u8 resp_second64[8]; 3722 __be32 r3[2]; 3723 } cim_rq; 3724 union fw_ldst_mps { 3725 struct fw_ldst_mps_rplc { 3726 __be16 fid_idx; 3727 __be16 rplcpf_pkd; 3728 __be32 rplc255_224; 3729 __be32 rplc223_192; 3730 __be32 rplc191_160; 3731 __be32 rplc159_128; 3732 __be32 rplc127_96; 3733 __be32 rplc95_64; 3734 __be32 rplc63_32; 3735 __be32 rplc31_0; 3736 } rplc; 3737 struct fw_ldst_mps_atrb { 3738 __be16 fid_mpsid; 3739 __be16 r2[3]; 3740 __be32 r3[2]; 3741 __be32 r4; 3742 __be32 atrb; 3743 __be16 vlan[16]; 3744 } atrb; 3745 } mps; 3746 struct fw_ldst_func { 3747 __u8 access_ctl; 3748 __u8 mod_index; 3749 __be16 ctl_id; 3750 __be32 offset; 3751 __be64 data0; 3752 __be64 data1; 3753 } func; 3754 struct fw_ldst_pcie { 3755 __u8 ctrl_to_fn; 3756 __u8 bnum; 3757 __u8 r; 3758 __u8 ext_r; 3759 __u8 select_naccess; 3760 __u8 pcie_fn; 3761 __be16 nset_pkd; 3762 __be32 data[12]; 3763 } pcie; 3764 struct fw_ldst_i2c_deprecated { 3765 __u8 pid_pkd; 3766 __u8 base; 3767 __u8 boffset; 3768 __u8 data; 3769 __be32 r9; 3770 } i2c_deprecated; 3771 struct fw_ldst_i2c { 3772 __u8 pid; 3773 __u8 did; 3774 __u8 boffset; 3775 __u8 blen; 3776 __be32 r9; 3777 __u8 data[48]; 3778 } i2c; 3779 struct fw_ldst_le { 3780 __be32 index; 3781 __be32 r9; 3782 __u8 val[33]; 3783 __u8 r11[7]; 3784 } le; 3785 } u; 3786 }; 3787 3788 #define S_FW_LDST_CMD_ADDRSPACE 0 3789 #define M_FW_LDST_CMD_ADDRSPACE 0xff 3790 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 3791 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 3792 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 3793 3794 #define S_FW_LDST_CMD_CYCLES 16 3795 #define M_FW_LDST_CMD_CYCLES 0xffff 3796 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 3797 #define G_FW_LDST_CMD_CYCLES(x) \ 3798 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 3799 3800 #define S_FW_LDST_CMD_MSG 31 3801 #define M_FW_LDST_CMD_MSG 0x1 3802 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 3803 #define G_FW_LDST_CMD_MSG(x) \ 3804 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 3805 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 3806 3807 #define S_FW_LDST_CMD_CTXTFLUSH 30 3808 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 3809 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 3810 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 3811 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 3812 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 3813 3814 #define S_FW_LDST_CMD_PADDR 8 3815 #define M_FW_LDST_CMD_PADDR 0x1f 3816 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 3817 #define G_FW_LDST_CMD_PADDR(x) \ 3818 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 3819 3820 #define S_FW_LDST_CMD_MMD 0 3821 #define M_FW_LDST_CMD_MMD 0x1f 3822 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 3823 #define G_FW_LDST_CMD_MMD(x) \ 3824 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 3825 3826 #define S_FW_LDST_CMD_FID 15 3827 #define M_FW_LDST_CMD_FID 0x1 3828 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 3829 #define G_FW_LDST_CMD_FID(x) \ 3830 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 3831 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 3832 3833 #define S_FW_LDST_CMD_IDX 0 3834 #define M_FW_LDST_CMD_IDX 0x7fff 3835 #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) 3836 #define G_FW_LDST_CMD_IDX(x) \ 3837 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) 3838 3839 #define S_FW_LDST_CMD_RPLCPF 0 3840 #define M_FW_LDST_CMD_RPLCPF 0xff 3841 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 3842 #define G_FW_LDST_CMD_RPLCPF(x) \ 3843 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 3844 3845 #define S_FW_LDST_CMD_MPSID 0 3846 #define M_FW_LDST_CMD_MPSID 0x7fff 3847 #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) 3848 #define G_FW_LDST_CMD_MPSID(x) \ 3849 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) 3850 3851 #define S_FW_LDST_CMD_CTRL 7 3852 #define M_FW_LDST_CMD_CTRL 0x1 3853 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 3854 #define G_FW_LDST_CMD_CTRL(x) \ 3855 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 3856 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 3857 3858 #define S_FW_LDST_CMD_LC 4 3859 #define M_FW_LDST_CMD_LC 0x1 3860 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 3861 #define G_FW_LDST_CMD_LC(x) \ 3862 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 3863 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 3864 3865 #define S_FW_LDST_CMD_AI 3 3866 #define M_FW_LDST_CMD_AI 0x1 3867 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 3868 #define G_FW_LDST_CMD_AI(x) \ 3869 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 3870 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 3871 3872 #define S_FW_LDST_CMD_FN 0 3873 #define M_FW_LDST_CMD_FN 0x7 3874 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 3875 #define G_FW_LDST_CMD_FN(x) \ 3876 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 3877 3878 #define S_FW_LDST_CMD_SELECT 4 3879 #define M_FW_LDST_CMD_SELECT 0xf 3880 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 3881 #define G_FW_LDST_CMD_SELECT(x) \ 3882 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 3883 3884 #define S_FW_LDST_CMD_NACCESS 0 3885 #define M_FW_LDST_CMD_NACCESS 0xf 3886 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 3887 #define G_FW_LDST_CMD_NACCESS(x) \ 3888 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 3889 3890 #define S_FW_LDST_CMD_NSET 14 3891 #define M_FW_LDST_CMD_NSET 0x3 3892 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 3893 #define G_FW_LDST_CMD_NSET(x) \ 3894 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 3895 3896 #define S_FW_LDST_CMD_PID 6 3897 #define M_FW_LDST_CMD_PID 0x3 3898 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 3899 #define G_FW_LDST_CMD_PID(x) \ 3900 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 3901 3902 struct fw_reset_cmd { 3903 __be32 op_to_write; 3904 __be32 retval_len16; 3905 __be32 val; 3906 __be32 halt_pkd; 3907 }; 3908 3909 #define S_FW_RESET_CMD_HALT 31 3910 #define M_FW_RESET_CMD_HALT 0x1 3911 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 3912 #define G_FW_RESET_CMD_HALT(x) \ 3913 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 3914 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 3915 3916 enum { 3917 FW_HELLO_CMD_STAGE_OS = 0, 3918 FW_HELLO_CMD_STAGE_PREOS0 = 1, 3919 FW_HELLO_CMD_STAGE_PREOS1 = 2, 3920 FW_HELLO_CMD_STAGE_POSTOS = 3, 3921 }; 3922 3923 struct fw_hello_cmd { 3924 __be32 op_to_write; 3925 __be32 retval_len16; 3926 __be32 err_to_clearinit; 3927 __be32 fwrev; 3928 }; 3929 3930 #define S_FW_HELLO_CMD_ERR 31 3931 #define M_FW_HELLO_CMD_ERR 0x1 3932 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 3933 #define G_FW_HELLO_CMD_ERR(x) \ 3934 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 3935 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 3936 3937 #define S_FW_HELLO_CMD_INIT 30 3938 #define M_FW_HELLO_CMD_INIT 0x1 3939 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 3940 #define G_FW_HELLO_CMD_INIT(x) \ 3941 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 3942 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 3943 3944 #define S_FW_HELLO_CMD_MASTERDIS 29 3945 #define M_FW_HELLO_CMD_MASTERDIS 0x1 3946 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 3947 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 3948 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 3949 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 3950 3951 #define S_FW_HELLO_CMD_MASTERFORCE 28 3952 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 3953 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 3954 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 3955 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 3956 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 3957 3958 #define S_FW_HELLO_CMD_MBMASTER 24 3959 #define M_FW_HELLO_CMD_MBMASTER 0xf 3960 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 3961 #define G_FW_HELLO_CMD_MBMASTER(x) \ 3962 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 3963 3964 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 3965 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 3966 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 3967 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 3968 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 3969 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 3970 3971 #define S_FW_HELLO_CMD_MBASYNCNOT 20 3972 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 3973 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 3974 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 3975 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 3976 3977 #define S_FW_HELLO_CMD_STAGE 17 3978 #define M_FW_HELLO_CMD_STAGE 0x7 3979 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 3980 #define G_FW_HELLO_CMD_STAGE(x) \ 3981 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 3982 3983 #define S_FW_HELLO_CMD_CLEARINIT 16 3984 #define M_FW_HELLO_CMD_CLEARINIT 0x1 3985 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 3986 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 3987 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 3988 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 3989 3990 struct fw_bye_cmd { 3991 __be32 op_to_write; 3992 __be32 retval_len16; 3993 __be64 r3; 3994 }; 3995 3996 struct fw_initialize_cmd { 3997 __be32 op_to_write; 3998 __be32 retval_len16; 3999 __be64 r3; 4000 }; 4001 4002 enum fw_caps_config_hm { 4003 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 4004 FW_CAPS_CONFIG_HM_PL = 0x00000002, 4005 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 4006 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 4007 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 4008 FW_CAPS_CONFIG_HM_TP = 0x00000020, 4009 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 4010 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 4011 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 4012 FW_CAPS_CONFIG_HM_MC = 0x00000200, 4013 FW_CAPS_CONFIG_HM_LE = 0x00000400, 4014 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 4015 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 4016 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 4017 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 4018 FW_CAPS_CONFIG_HM_MI = 0x00008000, 4019 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 4020 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 4021 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 4022 FW_CAPS_CONFIG_HM_MA = 0x00080000, 4023 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 4024 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 4025 FW_CAPS_CONFIG_HM_UART = 0x00400000, 4026 FW_CAPS_CONFIG_HM_SF = 0x00800000, 4027 }; 4028 4029 /* 4030 * The VF Register Map. 4031 * 4032 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 4033 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 4034 * the Slice to Module Map Table (see below) in the Physical Function Register 4035 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 4036 * and Offset registers in the PF Register Map. The MBDATA base address is 4037 * quite constrained as it determines the Mailbox Data addresses for both PFs 4038 * and VFs, and therefore must fit in both the VF and PF Register Maps without 4039 * overlapping other registers. 4040 */ 4041 #define FW_T4VF_SGE_BASE_ADDR 0x0000 4042 #define FW_T4VF_MPS_BASE_ADDR 0x0100 4043 #define FW_T4VF_PL_BASE_ADDR 0x0200 4044 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 4045 #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */ 4046 #define FW_T4VF_CIM_BASE_ADDR 0x0300 4047 4048 #define FW_T4VF_REGMAP_START 0x0000 4049 #define FW_T4VF_REGMAP_SIZE 0x0400 4050 4051 enum fw_caps_config_nbm { 4052 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 4053 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 4054 }; 4055 4056 enum fw_caps_config_link { 4057 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 4058 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 4059 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 4060 }; 4061 4062 enum fw_caps_config_switch { 4063 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 4064 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 4065 }; 4066 4067 enum fw_caps_config_nic { 4068 FW_CAPS_CONFIG_NIC = 0x00000001, 4069 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 4070 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 4071 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 4072 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 4073 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 4074 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 4075 }; 4076 4077 enum fw_caps_config_toe { 4078 FW_CAPS_CONFIG_TOE = 0x00000001, 4079 }; 4080 4081 enum fw_caps_config_rdma { 4082 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 4083 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 4084 }; 4085 4086 enum fw_caps_config_iscsi { 4087 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 4088 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 4089 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 4090 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 4091 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 4092 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 4093 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, 4094 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080, 4095 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100, 4096 }; 4097 4098 enum fw_caps_config_tls { 4099 FW_CAPS_CONFIG_TLSKEYS = 0x00000001, 4100 }; 4101 4102 enum fw_caps_config_fcoe { 4103 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 4104 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 4105 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 4106 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 4107 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 4108 }; 4109 4110 enum fw_memtype_cf { 4111 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 4112 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 4113 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 4114 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 4115 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 4116 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 4117 }; 4118 4119 struct fw_caps_config_cmd { 4120 __be32 op_to_write; 4121 __be32 cfvalid_to_len16; 4122 __be32 r2; 4123 __be32 hwmbitmap; 4124 __be16 nbmcaps; 4125 __be16 linkcaps; 4126 __be16 switchcaps; 4127 __be16 r3; 4128 __be16 niccaps; 4129 __be16 toecaps; 4130 __be16 rdmacaps; 4131 __be16 tlscaps; 4132 __be16 iscsicaps; 4133 __be16 fcoecaps; 4134 __be32 cfcsum; 4135 __be32 finiver; 4136 __be32 finicsum; 4137 }; 4138 4139 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 4140 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 4141 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 4142 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 4143 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 4144 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 4145 4146 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 4147 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 4148 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4149 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4150 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4151 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 4152 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4153 4154 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 4155 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 4156 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4157 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4158 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4159 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 4160 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4161 4162 /* 4163 * params command mnemonics 4164 */ 4165 enum fw_params_mnem { 4166 FW_PARAMS_MNEM_DEV = 1, /* device params */ 4167 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 4168 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 4169 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 4170 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 4171 FW_PARAMS_MNEM_LAST 4172 }; 4173 4174 /* 4175 * device parameters 4176 */ 4177 enum fw_params_param_dev { 4178 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 4179 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 4180 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 4181 * allocated by the device's 4182 * Lookup Engine 4183 */ 4184 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 4185 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 4186 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 4187 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 4188 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 4189 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 4190 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 4191 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 4192 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 4193 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 4194 FW_PARAMS_PARAM_DEV_CF = 0x0D, 4195 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 4196 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 4197 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 4198 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 4199 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 4200 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 4201 */ 4202 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 4203 */ 4204 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 4205 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 4206 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 4207 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 4208 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, 4209 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 4210 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 4211 }; 4212 4213 /* 4214 * dev bypass parameters; actions and modes 4215 */ 4216 enum fw_params_param_dev_bypass { 4217 4218 /* actions 4219 */ 4220 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 4221 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 4222 4223 /* modes 4224 */ 4225 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 4226 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 4227 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 4228 }; 4229 4230 enum fw_params_param_dev_phyfw { 4231 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 4232 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 4233 }; 4234 4235 enum fw_params_param_dev_diag { 4236 FW_PARAM_DEV_DIAG_TMP = 0x00, 4237 FW_PARAM_DEV_DIAG_VDD = 0x01, 4238 }; 4239 4240 enum fw_params_param_dev_fwcache { 4241 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 4242 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 4243 }; 4244 4245 /* 4246 * physical and virtual function parameters 4247 */ 4248 enum fw_params_param_pfvf { 4249 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 4250 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 4251 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 4252 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 4253 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 4254 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 4255 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 4256 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 4257 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 4258 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 4259 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 4260 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 4261 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 4262 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 4263 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 4264 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 4265 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 4266 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 4267 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 4268 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 4269 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 4270 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 4271 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 4272 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 4273 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 4274 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 4275 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 4276 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 4277 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 4278 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 4279 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 4280 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 4281 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 4282 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 4283 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 4284 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 4285 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 4286 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 4287 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 4288 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 4289 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 4290 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 4291 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 4292 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 4293 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 4294 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 4295 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 4296 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 4297 }; 4298 4299 /* 4300 * dma queue parameters 4301 */ 4302 enum fw_params_param_dmaq { 4303 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 4304 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 4305 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 4306 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03, 4307 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 4308 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 4309 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 4310 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 4311 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14, 4312 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 4313 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30 4314 }; 4315 4316 /* 4317 * chnet parameters 4318 */ 4319 enum fw_params_param_chnet { 4320 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, 4321 }; 4322 4323 enum fw_params_param_chnet_flags { 4324 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, 4325 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, 4326 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, 4327 }; 4328 4329 #define S_FW_PARAMS_MNEM 24 4330 #define M_FW_PARAMS_MNEM 0xff 4331 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 4332 #define G_FW_PARAMS_MNEM(x) \ 4333 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 4334 4335 #define S_FW_PARAMS_PARAM_X 16 4336 #define M_FW_PARAMS_PARAM_X 0xff 4337 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 4338 #define G_FW_PARAMS_PARAM_X(x) \ 4339 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 4340 4341 #define S_FW_PARAMS_PARAM_Y 8 4342 #define M_FW_PARAMS_PARAM_Y 0xff 4343 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 4344 #define G_FW_PARAMS_PARAM_Y(x) \ 4345 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 4346 4347 #define S_FW_PARAMS_PARAM_Z 0 4348 #define M_FW_PARAMS_PARAM_Z 0xff 4349 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 4350 #define G_FW_PARAMS_PARAM_Z(x) \ 4351 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 4352 4353 #define S_FW_PARAMS_PARAM_XYZ 0 4354 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 4355 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 4356 #define G_FW_PARAMS_PARAM_XYZ(x) \ 4357 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 4358 4359 #define S_FW_PARAMS_PARAM_YZ 0 4360 #define M_FW_PARAMS_PARAM_YZ 0xffff 4361 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 4362 #define G_FW_PARAMS_PARAM_YZ(x) \ 4363 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 4364 4365 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31 4366 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1 4367 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4368 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4369 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4370 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \ 4371 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4372 4373 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24 4374 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3 4375 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4376 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4377 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4378 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \ 4379 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4380 4381 #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0 4382 #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff 4383 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4384 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4385 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4386 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4387 4388 struct fw_params_cmd { 4389 __be32 op_to_vfn; 4390 __be32 retval_len16; 4391 struct fw_params_param { 4392 __be32 mnem; 4393 __be32 val; 4394 } param[7]; 4395 }; 4396 4397 #define S_FW_PARAMS_CMD_PFN 8 4398 #define M_FW_PARAMS_CMD_PFN 0x7 4399 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 4400 #define G_FW_PARAMS_CMD_PFN(x) \ 4401 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 4402 4403 #define S_FW_PARAMS_CMD_VFN 0 4404 #define M_FW_PARAMS_CMD_VFN 0xff 4405 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 4406 #define G_FW_PARAMS_CMD_VFN(x) \ 4407 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 4408 4409 struct fw_pfvf_cmd { 4410 __be32 op_to_vfn; 4411 __be32 retval_len16; 4412 __be32 niqflint_niq; 4413 __be32 type_to_neq; 4414 __be32 tc_to_nexactf; 4415 __be32 r_caps_to_nethctrl; 4416 __be16 nricq; 4417 __be16 nriqp; 4418 __be32 r4; 4419 }; 4420 4421 #define S_FW_PFVF_CMD_PFN 8 4422 #define M_FW_PFVF_CMD_PFN 0x7 4423 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 4424 #define G_FW_PFVF_CMD_PFN(x) \ 4425 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 4426 4427 #define S_FW_PFVF_CMD_VFN 0 4428 #define M_FW_PFVF_CMD_VFN 0xff 4429 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 4430 #define G_FW_PFVF_CMD_VFN(x) \ 4431 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 4432 4433 #define S_FW_PFVF_CMD_NIQFLINT 20 4434 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 4435 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 4436 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 4437 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 4438 4439 #define S_FW_PFVF_CMD_NIQ 0 4440 #define M_FW_PFVF_CMD_NIQ 0xfffff 4441 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 4442 #define G_FW_PFVF_CMD_NIQ(x) \ 4443 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 4444 4445 #define S_FW_PFVF_CMD_TYPE 31 4446 #define M_FW_PFVF_CMD_TYPE 0x1 4447 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 4448 #define G_FW_PFVF_CMD_TYPE(x) \ 4449 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 4450 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 4451 4452 #define S_FW_PFVF_CMD_CMASK 24 4453 #define M_FW_PFVF_CMD_CMASK 0xf 4454 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 4455 #define G_FW_PFVF_CMD_CMASK(x) \ 4456 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 4457 4458 #define S_FW_PFVF_CMD_PMASK 20 4459 #define M_FW_PFVF_CMD_PMASK 0xf 4460 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 4461 #define G_FW_PFVF_CMD_PMASK(x) \ 4462 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 4463 4464 #define S_FW_PFVF_CMD_NEQ 0 4465 #define M_FW_PFVF_CMD_NEQ 0xfffff 4466 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 4467 #define G_FW_PFVF_CMD_NEQ(x) \ 4468 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 4469 4470 #define S_FW_PFVF_CMD_TC 24 4471 #define M_FW_PFVF_CMD_TC 0xff 4472 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 4473 #define G_FW_PFVF_CMD_TC(x) \ 4474 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 4475 4476 #define S_FW_PFVF_CMD_NVI 16 4477 #define M_FW_PFVF_CMD_NVI 0xff 4478 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 4479 #define G_FW_PFVF_CMD_NVI(x) \ 4480 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 4481 4482 #define S_FW_PFVF_CMD_NEXACTF 0 4483 #define M_FW_PFVF_CMD_NEXACTF 0xffff 4484 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 4485 #define G_FW_PFVF_CMD_NEXACTF(x) \ 4486 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 4487 4488 #define S_FW_PFVF_CMD_R_CAPS 24 4489 #define M_FW_PFVF_CMD_R_CAPS 0xff 4490 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 4491 #define G_FW_PFVF_CMD_R_CAPS(x) \ 4492 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 4493 4494 #define S_FW_PFVF_CMD_WX_CAPS 16 4495 #define M_FW_PFVF_CMD_WX_CAPS 0xff 4496 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 4497 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 4498 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 4499 4500 #define S_FW_PFVF_CMD_NETHCTRL 0 4501 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 4502 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 4503 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 4504 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 4505 4506 /* 4507 * ingress queue type; the first 1K ingress queues can have associated 0, 4508 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 4509 * capabilities 4510 */ 4511 enum fw_iq_type { 4512 FW_IQ_TYPE_FL_INT_CAP, 4513 FW_IQ_TYPE_NO_FL_INT_CAP 4514 }; 4515 4516 struct fw_iq_cmd { 4517 __be32 op_to_vfn; 4518 __be32 alloc_to_len16; 4519 __be16 physiqid; 4520 __be16 iqid; 4521 __be16 fl0id; 4522 __be16 fl1id; 4523 __be32 type_to_iqandstindex; 4524 __be16 iqdroprss_to_iqesize; 4525 __be16 iqsize; 4526 __be64 iqaddr; 4527 __be32 iqns_to_fl0congen; 4528 __be16 fl0dcaen_to_fl0cidxfthresh; 4529 __be16 fl0size; 4530 __be64 fl0addr; 4531 __be32 fl1cngchmap_to_fl1congen; 4532 __be16 fl1dcaen_to_fl1cidxfthresh; 4533 __be16 fl1size; 4534 __be64 fl1addr; 4535 }; 4536 4537 #define S_FW_IQ_CMD_PFN 8 4538 #define M_FW_IQ_CMD_PFN 0x7 4539 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 4540 #define G_FW_IQ_CMD_PFN(x) \ 4541 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 4542 4543 #define S_FW_IQ_CMD_VFN 0 4544 #define M_FW_IQ_CMD_VFN 0xff 4545 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 4546 #define G_FW_IQ_CMD_VFN(x) \ 4547 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 4548 4549 #define S_FW_IQ_CMD_ALLOC 31 4550 #define M_FW_IQ_CMD_ALLOC 0x1 4551 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 4552 #define G_FW_IQ_CMD_ALLOC(x) \ 4553 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 4554 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 4555 4556 #define S_FW_IQ_CMD_FREE 30 4557 #define M_FW_IQ_CMD_FREE 0x1 4558 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 4559 #define G_FW_IQ_CMD_FREE(x) \ 4560 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 4561 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 4562 4563 #define S_FW_IQ_CMD_MODIFY 29 4564 #define M_FW_IQ_CMD_MODIFY 0x1 4565 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 4566 #define G_FW_IQ_CMD_MODIFY(x) \ 4567 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 4568 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 4569 4570 #define S_FW_IQ_CMD_IQSTART 28 4571 #define M_FW_IQ_CMD_IQSTART 0x1 4572 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 4573 #define G_FW_IQ_CMD_IQSTART(x) \ 4574 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 4575 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 4576 4577 #define S_FW_IQ_CMD_IQSTOP 27 4578 #define M_FW_IQ_CMD_IQSTOP 0x1 4579 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 4580 #define G_FW_IQ_CMD_IQSTOP(x) \ 4581 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 4582 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 4583 4584 #define S_FW_IQ_CMD_TYPE 29 4585 #define M_FW_IQ_CMD_TYPE 0x7 4586 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 4587 #define G_FW_IQ_CMD_TYPE(x) \ 4588 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 4589 4590 #define S_FW_IQ_CMD_IQASYNCH 28 4591 #define M_FW_IQ_CMD_IQASYNCH 0x1 4592 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 4593 #define G_FW_IQ_CMD_IQASYNCH(x) \ 4594 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 4595 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 4596 4597 #define S_FW_IQ_CMD_VIID 16 4598 #define M_FW_IQ_CMD_VIID 0xfff 4599 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 4600 #define G_FW_IQ_CMD_VIID(x) \ 4601 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 4602 4603 #define S_FW_IQ_CMD_IQANDST 15 4604 #define M_FW_IQ_CMD_IQANDST 0x1 4605 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 4606 #define G_FW_IQ_CMD_IQANDST(x) \ 4607 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 4608 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 4609 4610 #define S_FW_IQ_CMD_IQANUS 14 4611 #define M_FW_IQ_CMD_IQANUS 0x1 4612 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 4613 #define G_FW_IQ_CMD_IQANUS(x) \ 4614 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 4615 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 4616 4617 #define S_FW_IQ_CMD_IQANUD 12 4618 #define M_FW_IQ_CMD_IQANUD 0x3 4619 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 4620 #define G_FW_IQ_CMD_IQANUD(x) \ 4621 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 4622 4623 #define S_FW_IQ_CMD_IQANDSTINDEX 0 4624 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 4625 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 4626 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 4627 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 4628 4629 #define S_FW_IQ_CMD_IQDROPRSS 15 4630 #define M_FW_IQ_CMD_IQDROPRSS 0x1 4631 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 4632 #define G_FW_IQ_CMD_IQDROPRSS(x) \ 4633 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 4634 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 4635 4636 #define S_FW_IQ_CMD_IQGTSMODE 14 4637 #define M_FW_IQ_CMD_IQGTSMODE 0x1 4638 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 4639 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 4640 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 4641 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 4642 4643 #define S_FW_IQ_CMD_IQPCIECH 12 4644 #define M_FW_IQ_CMD_IQPCIECH 0x3 4645 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 4646 #define G_FW_IQ_CMD_IQPCIECH(x) \ 4647 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 4648 4649 #define S_FW_IQ_CMD_IQDCAEN 11 4650 #define M_FW_IQ_CMD_IQDCAEN 0x1 4651 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 4652 #define G_FW_IQ_CMD_IQDCAEN(x) \ 4653 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 4654 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 4655 4656 #define S_FW_IQ_CMD_IQDCACPU 6 4657 #define M_FW_IQ_CMD_IQDCACPU 0x1f 4658 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 4659 #define G_FW_IQ_CMD_IQDCACPU(x) \ 4660 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 4661 4662 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 4663 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 4664 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 4665 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 4666 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 4667 4668 #define S_FW_IQ_CMD_IQO 3 4669 #define M_FW_IQ_CMD_IQO 0x1 4670 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 4671 #define G_FW_IQ_CMD_IQO(x) \ 4672 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 4673 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 4674 4675 #define S_FW_IQ_CMD_IQCPRIO 2 4676 #define M_FW_IQ_CMD_IQCPRIO 0x1 4677 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 4678 #define G_FW_IQ_CMD_IQCPRIO(x) \ 4679 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 4680 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 4681 4682 #define S_FW_IQ_CMD_IQESIZE 0 4683 #define M_FW_IQ_CMD_IQESIZE 0x3 4684 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 4685 #define G_FW_IQ_CMD_IQESIZE(x) \ 4686 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 4687 4688 #define S_FW_IQ_CMD_IQNS 31 4689 #define M_FW_IQ_CMD_IQNS 0x1 4690 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 4691 #define G_FW_IQ_CMD_IQNS(x) \ 4692 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 4693 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 4694 4695 #define S_FW_IQ_CMD_IQRO 30 4696 #define M_FW_IQ_CMD_IQRO 0x1 4697 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 4698 #define G_FW_IQ_CMD_IQRO(x) \ 4699 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 4700 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 4701 4702 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 4703 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 4704 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 4705 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 4706 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 4707 4708 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 4709 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 4710 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 4711 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 4712 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 4713 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 4714 4715 #define S_FW_IQ_CMD_IQFLINTISCSIC 26 4716 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 4717 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 4718 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 4719 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 4720 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 4721 4722 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 4723 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 4724 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 4725 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 4726 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 4727 4728 #define S_FW_IQ_CMD_FL0CONGDROP 16 4729 #define M_FW_IQ_CMD_FL0CONGDROP 0x1 4730 #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) 4731 #define G_FW_IQ_CMD_FL0CONGDROP(x) \ 4732 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) 4733 #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) 4734 4735 #define S_FW_IQ_CMD_FL0CACHELOCK 15 4736 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 4737 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 4738 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 4739 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 4740 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 4741 4742 #define S_FW_IQ_CMD_FL0DBP 14 4743 #define M_FW_IQ_CMD_FL0DBP 0x1 4744 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 4745 #define G_FW_IQ_CMD_FL0DBP(x) \ 4746 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 4747 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 4748 4749 #define S_FW_IQ_CMD_FL0DATANS 13 4750 #define M_FW_IQ_CMD_FL0DATANS 0x1 4751 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 4752 #define G_FW_IQ_CMD_FL0DATANS(x) \ 4753 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 4754 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 4755 4756 #define S_FW_IQ_CMD_FL0DATARO 12 4757 #define M_FW_IQ_CMD_FL0DATARO 0x1 4758 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 4759 #define G_FW_IQ_CMD_FL0DATARO(x) \ 4760 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 4761 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 4762 4763 #define S_FW_IQ_CMD_FL0CONGCIF 11 4764 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 4765 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 4766 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 4767 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 4768 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 4769 4770 #define S_FW_IQ_CMD_FL0ONCHIP 10 4771 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 4772 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 4773 #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 4774 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 4775 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 4776 4777 #define S_FW_IQ_CMD_FL0STATUSPGNS 9 4778 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 4779 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 4780 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 4781 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 4782 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 4783 4784 #define S_FW_IQ_CMD_FL0STATUSPGRO 8 4785 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 4786 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 4787 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 4788 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 4789 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 4790 4791 #define S_FW_IQ_CMD_FL0FETCHNS 7 4792 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 4793 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 4794 #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 4795 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 4796 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 4797 4798 #define S_FW_IQ_CMD_FL0FETCHRO 6 4799 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 4800 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 4801 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 4802 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 4803 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 4804 4805 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 4806 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 4807 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 4808 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 4809 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 4810 4811 #define S_FW_IQ_CMD_FL0CPRIO 3 4812 #define M_FW_IQ_CMD_FL0CPRIO 0x1 4813 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 4814 #define G_FW_IQ_CMD_FL0CPRIO(x) \ 4815 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 4816 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 4817 4818 #define S_FW_IQ_CMD_FL0PADEN 2 4819 #define M_FW_IQ_CMD_FL0PADEN 0x1 4820 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 4821 #define G_FW_IQ_CMD_FL0PADEN(x) \ 4822 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 4823 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 4824 4825 #define S_FW_IQ_CMD_FL0PACKEN 1 4826 #define M_FW_IQ_CMD_FL0PACKEN 0x1 4827 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 4828 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 4829 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 4830 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 4831 4832 #define S_FW_IQ_CMD_FL0CONGEN 0 4833 #define M_FW_IQ_CMD_FL0CONGEN 0x1 4834 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 4835 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 4836 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 4837 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 4838 4839 #define S_FW_IQ_CMD_FL0DCAEN 15 4840 #define M_FW_IQ_CMD_FL0DCAEN 0x1 4841 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 4842 #define G_FW_IQ_CMD_FL0DCAEN(x) \ 4843 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 4844 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 4845 4846 #define S_FW_IQ_CMD_FL0DCACPU 10 4847 #define M_FW_IQ_CMD_FL0DCACPU 0x1f 4848 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 4849 #define G_FW_IQ_CMD_FL0DCACPU(x) \ 4850 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 4851 4852 #define S_FW_IQ_CMD_FL0FBMIN 7 4853 #define M_FW_IQ_CMD_FL0FBMIN 0x7 4854 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 4855 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 4856 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 4857 4858 #define S_FW_IQ_CMD_FL0FBMAX 4 4859 #define M_FW_IQ_CMD_FL0FBMAX 0x7 4860 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 4861 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 4862 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 4863 4864 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 4865 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 4866 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 4867 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 4868 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 4869 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 4870 4871 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 4872 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 4873 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 4874 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 4875 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 4876 4877 #define S_FW_IQ_CMD_FL1CNGCHMAP 20 4878 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 4879 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 4880 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 4881 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 4882 4883 #define S_FW_IQ_CMD_FL1CONGDROP 16 4884 #define M_FW_IQ_CMD_FL1CONGDROP 0x1 4885 #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) 4886 #define G_FW_IQ_CMD_FL1CONGDROP(x) \ 4887 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) 4888 #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) 4889 4890 #define S_FW_IQ_CMD_FL1CACHELOCK 15 4891 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 4892 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 4893 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 4894 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 4895 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 4896 4897 #define S_FW_IQ_CMD_FL1DBP 14 4898 #define M_FW_IQ_CMD_FL1DBP 0x1 4899 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 4900 #define G_FW_IQ_CMD_FL1DBP(x) \ 4901 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 4902 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 4903 4904 #define S_FW_IQ_CMD_FL1DATANS 13 4905 #define M_FW_IQ_CMD_FL1DATANS 0x1 4906 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 4907 #define G_FW_IQ_CMD_FL1DATANS(x) \ 4908 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 4909 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 4910 4911 #define S_FW_IQ_CMD_FL1DATARO 12 4912 #define M_FW_IQ_CMD_FL1DATARO 0x1 4913 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 4914 #define G_FW_IQ_CMD_FL1DATARO(x) \ 4915 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 4916 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 4917 4918 #define S_FW_IQ_CMD_FL1CONGCIF 11 4919 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 4920 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 4921 #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 4922 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 4923 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 4924 4925 #define S_FW_IQ_CMD_FL1ONCHIP 10 4926 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 4927 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 4928 #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 4929 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 4930 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 4931 4932 #define S_FW_IQ_CMD_FL1STATUSPGNS 9 4933 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 4934 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 4935 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 4936 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 4937 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 4938 4939 #define S_FW_IQ_CMD_FL1STATUSPGRO 8 4940 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 4941 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 4942 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 4943 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 4944 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 4945 4946 #define S_FW_IQ_CMD_FL1FETCHNS 7 4947 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 4948 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 4949 #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 4950 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 4951 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 4952 4953 #define S_FW_IQ_CMD_FL1FETCHRO 6 4954 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 4955 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 4956 #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 4957 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 4958 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 4959 4960 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 4961 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 4962 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 4963 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 4964 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 4965 4966 #define S_FW_IQ_CMD_FL1CPRIO 3 4967 #define M_FW_IQ_CMD_FL1CPRIO 0x1 4968 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 4969 #define G_FW_IQ_CMD_FL1CPRIO(x) \ 4970 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 4971 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 4972 4973 #define S_FW_IQ_CMD_FL1PADEN 2 4974 #define M_FW_IQ_CMD_FL1PADEN 0x1 4975 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 4976 #define G_FW_IQ_CMD_FL1PADEN(x) \ 4977 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 4978 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 4979 4980 #define S_FW_IQ_CMD_FL1PACKEN 1 4981 #define M_FW_IQ_CMD_FL1PACKEN 0x1 4982 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 4983 #define G_FW_IQ_CMD_FL1PACKEN(x) \ 4984 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 4985 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 4986 4987 #define S_FW_IQ_CMD_FL1CONGEN 0 4988 #define M_FW_IQ_CMD_FL1CONGEN 0x1 4989 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 4990 #define G_FW_IQ_CMD_FL1CONGEN(x) \ 4991 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 4992 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 4993 4994 #define S_FW_IQ_CMD_FL1DCAEN 15 4995 #define M_FW_IQ_CMD_FL1DCAEN 0x1 4996 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 4997 #define G_FW_IQ_CMD_FL1DCAEN(x) \ 4998 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 4999 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 5000 5001 #define S_FW_IQ_CMD_FL1DCACPU 10 5002 #define M_FW_IQ_CMD_FL1DCACPU 0x1f 5003 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 5004 #define G_FW_IQ_CMD_FL1DCACPU(x) \ 5005 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 5006 5007 #define S_FW_IQ_CMD_FL1FBMIN 7 5008 #define M_FW_IQ_CMD_FL1FBMIN 0x7 5009 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 5010 #define G_FW_IQ_CMD_FL1FBMIN(x) \ 5011 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 5012 5013 #define S_FW_IQ_CMD_FL1FBMAX 4 5014 #define M_FW_IQ_CMD_FL1FBMAX 0x7 5015 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 5016 #define G_FW_IQ_CMD_FL1FBMAX(x) \ 5017 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 5018 5019 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 5020 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 5021 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 5022 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 5023 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 5024 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 5025 5026 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 5027 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 5028 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 5029 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 5030 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 5031 5032 struct fw_eq_mngt_cmd { 5033 __be32 op_to_vfn; 5034 __be32 alloc_to_len16; 5035 __be32 cmpliqid_eqid; 5036 __be32 physeqid_pkd; 5037 __be32 fetchszm_to_iqid; 5038 __be32 dcaen_to_eqsize; 5039 __be64 eqaddr; 5040 }; 5041 5042 #define S_FW_EQ_MNGT_CMD_PFN 8 5043 #define M_FW_EQ_MNGT_CMD_PFN 0x7 5044 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 5045 #define G_FW_EQ_MNGT_CMD_PFN(x) \ 5046 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 5047 5048 #define S_FW_EQ_MNGT_CMD_VFN 0 5049 #define M_FW_EQ_MNGT_CMD_VFN 0xff 5050 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 5051 #define G_FW_EQ_MNGT_CMD_VFN(x) \ 5052 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 5053 5054 #define S_FW_EQ_MNGT_CMD_ALLOC 31 5055 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 5056 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 5057 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 5058 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 5059 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 5060 5061 #define S_FW_EQ_MNGT_CMD_FREE 30 5062 #define M_FW_EQ_MNGT_CMD_FREE 0x1 5063 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 5064 #define G_FW_EQ_MNGT_CMD_FREE(x) \ 5065 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 5066 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 5067 5068 #define S_FW_EQ_MNGT_CMD_MODIFY 29 5069 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 5070 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 5071 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 5072 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 5073 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 5074 5075 #define S_FW_EQ_MNGT_CMD_EQSTART 28 5076 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 5077 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 5078 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 5079 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 5080 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 5081 5082 #define S_FW_EQ_MNGT_CMD_EQSTOP 27 5083 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 5084 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 5085 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 5086 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 5087 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 5088 5089 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 5090 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 5091 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 5092 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 5093 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 5094 5095 #define S_FW_EQ_MNGT_CMD_EQID 0 5096 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 5097 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 5098 #define G_FW_EQ_MNGT_CMD_EQID(x) \ 5099 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 5100 5101 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 5102 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 5103 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 5104 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 5105 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 5106 5107 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 5108 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 5109 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 5110 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 5111 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 5112 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 5113 5114 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 5115 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 5116 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 5117 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 5118 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 5119 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 5120 5121 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 5122 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 5123 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 5124 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 5125 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 5126 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 5127 5128 #define S_FW_EQ_MNGT_CMD_FETCHNS 23 5129 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 5130 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 5131 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 5132 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 5133 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 5134 5135 #define S_FW_EQ_MNGT_CMD_FETCHRO 22 5136 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 5137 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 5138 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 5139 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 5140 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 5141 5142 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 5143 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 5144 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 5145 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 5146 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 5147 5148 #define S_FW_EQ_MNGT_CMD_CPRIO 19 5149 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 5150 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 5151 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 5152 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 5153 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 5154 5155 #define S_FW_EQ_MNGT_CMD_ONCHIP 18 5156 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 5157 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 5158 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 5159 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 5160 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 5161 5162 #define S_FW_EQ_MNGT_CMD_PCIECHN 16 5163 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 5164 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 5165 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 5166 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 5167 5168 #define S_FW_EQ_MNGT_CMD_IQID 0 5169 #define M_FW_EQ_MNGT_CMD_IQID 0xffff 5170 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 5171 #define G_FW_EQ_MNGT_CMD_IQID(x) \ 5172 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 5173 5174 #define S_FW_EQ_MNGT_CMD_DCAEN 31 5175 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 5176 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 5177 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 5178 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 5179 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 5180 5181 #define S_FW_EQ_MNGT_CMD_DCACPU 26 5182 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 5183 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 5184 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 5185 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 5186 5187 #define S_FW_EQ_MNGT_CMD_FBMIN 23 5188 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 5189 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 5190 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 5191 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 5192 5193 #define S_FW_EQ_MNGT_CMD_FBMAX 20 5194 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 5195 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 5196 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 5197 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 5198 5199 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 5200 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 5201 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5202 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5203 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5204 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5205 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 5206 5207 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 5208 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 5209 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5210 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 5211 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5212 5213 #define S_FW_EQ_MNGT_CMD_EQSIZE 0 5214 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 5215 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 5216 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 5217 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 5218 5219 struct fw_eq_eth_cmd { 5220 __be32 op_to_vfn; 5221 __be32 alloc_to_len16; 5222 __be32 eqid_pkd; 5223 __be32 physeqid_pkd; 5224 __be32 fetchszm_to_iqid; 5225 __be32 dcaen_to_eqsize; 5226 __be64 eqaddr; 5227 __be32 autoequiqe_to_viid; 5228 __be32 r8_lo; 5229 __be64 r9; 5230 }; 5231 5232 #define S_FW_EQ_ETH_CMD_PFN 8 5233 #define M_FW_EQ_ETH_CMD_PFN 0x7 5234 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 5235 #define G_FW_EQ_ETH_CMD_PFN(x) \ 5236 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 5237 5238 #define S_FW_EQ_ETH_CMD_VFN 0 5239 #define M_FW_EQ_ETH_CMD_VFN 0xff 5240 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 5241 #define G_FW_EQ_ETH_CMD_VFN(x) \ 5242 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 5243 5244 #define S_FW_EQ_ETH_CMD_ALLOC 31 5245 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 5246 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 5247 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 5248 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 5249 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 5250 5251 #define S_FW_EQ_ETH_CMD_FREE 30 5252 #define M_FW_EQ_ETH_CMD_FREE 0x1 5253 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 5254 #define G_FW_EQ_ETH_CMD_FREE(x) \ 5255 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 5256 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 5257 5258 #define S_FW_EQ_ETH_CMD_MODIFY 29 5259 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 5260 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 5261 #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 5262 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 5263 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 5264 5265 #define S_FW_EQ_ETH_CMD_EQSTART 28 5266 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 5267 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 5268 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 5269 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 5270 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 5271 5272 #define S_FW_EQ_ETH_CMD_EQSTOP 27 5273 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 5274 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 5275 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 5276 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 5277 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 5278 5279 #define S_FW_EQ_ETH_CMD_EQID 0 5280 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 5281 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 5282 #define G_FW_EQ_ETH_CMD_EQID(x) \ 5283 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 5284 5285 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 5286 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 5287 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 5288 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 5289 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 5290 5291 #define S_FW_EQ_ETH_CMD_FETCHSZM 26 5292 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 5293 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 5294 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 5295 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 5296 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 5297 5298 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 5299 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 5300 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 5301 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 5302 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 5303 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 5304 5305 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 5306 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 5307 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 5308 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 5309 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 5310 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 5311 5312 #define S_FW_EQ_ETH_CMD_FETCHNS 23 5313 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 5314 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 5315 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 5316 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 5317 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 5318 5319 #define S_FW_EQ_ETH_CMD_FETCHRO 22 5320 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 5321 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 5322 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 5323 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 5324 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 5325 5326 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 5327 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 5328 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 5329 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 5330 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 5331 5332 #define S_FW_EQ_ETH_CMD_CPRIO 19 5333 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 5334 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 5335 #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 5336 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 5337 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 5338 5339 #define S_FW_EQ_ETH_CMD_ONCHIP 18 5340 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 5341 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 5342 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 5343 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 5344 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 5345 5346 #define S_FW_EQ_ETH_CMD_PCIECHN 16 5347 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 5348 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 5349 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 5350 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 5351 5352 #define S_FW_EQ_ETH_CMD_IQID 0 5353 #define M_FW_EQ_ETH_CMD_IQID 0xffff 5354 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 5355 #define G_FW_EQ_ETH_CMD_IQID(x) \ 5356 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 5357 5358 #define S_FW_EQ_ETH_CMD_DCAEN 31 5359 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 5360 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 5361 #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 5362 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 5363 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 5364 5365 #define S_FW_EQ_ETH_CMD_DCACPU 26 5366 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 5367 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 5368 #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 5369 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 5370 5371 #define S_FW_EQ_ETH_CMD_FBMIN 23 5372 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 5373 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 5374 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 5375 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 5376 5377 #define S_FW_EQ_ETH_CMD_FBMAX 20 5378 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 5379 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 5380 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 5381 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 5382 5383 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 5384 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 5385 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 5386 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 5387 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 5388 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 5389 5390 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 5391 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 5392 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 5393 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 5394 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 5395 5396 #define S_FW_EQ_ETH_CMD_EQSIZE 0 5397 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 5398 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 5399 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 5400 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 5401 5402 #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 5403 #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 5404 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 5405 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 5406 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 5407 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 5408 5409 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 5410 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 5411 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 5412 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 5413 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 5414 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 5415 5416 #define S_FW_EQ_ETH_CMD_VIID 16 5417 #define M_FW_EQ_ETH_CMD_VIID 0xfff 5418 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 5419 #define G_FW_EQ_ETH_CMD_VIID(x) \ 5420 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 5421 5422 struct fw_eq_ctrl_cmd { 5423 __be32 op_to_vfn; 5424 __be32 alloc_to_len16; 5425 __be32 cmpliqid_eqid; 5426 __be32 physeqid_pkd; 5427 __be32 fetchszm_to_iqid; 5428 __be32 dcaen_to_eqsize; 5429 __be64 eqaddr; 5430 }; 5431 5432 #define S_FW_EQ_CTRL_CMD_PFN 8 5433 #define M_FW_EQ_CTRL_CMD_PFN 0x7 5434 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 5435 #define G_FW_EQ_CTRL_CMD_PFN(x) \ 5436 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 5437 5438 #define S_FW_EQ_CTRL_CMD_VFN 0 5439 #define M_FW_EQ_CTRL_CMD_VFN 0xff 5440 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 5441 #define G_FW_EQ_CTRL_CMD_VFN(x) \ 5442 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 5443 5444 #define S_FW_EQ_CTRL_CMD_ALLOC 31 5445 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 5446 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 5447 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 5448 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 5449 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 5450 5451 #define S_FW_EQ_CTRL_CMD_FREE 30 5452 #define M_FW_EQ_CTRL_CMD_FREE 0x1 5453 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 5454 #define G_FW_EQ_CTRL_CMD_FREE(x) \ 5455 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 5456 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 5457 5458 #define S_FW_EQ_CTRL_CMD_MODIFY 29 5459 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 5460 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 5461 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 5462 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 5463 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 5464 5465 #define S_FW_EQ_CTRL_CMD_EQSTART 28 5466 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 5467 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 5468 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 5469 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 5470 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 5471 5472 #define S_FW_EQ_CTRL_CMD_EQSTOP 27 5473 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 5474 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 5475 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 5476 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 5477 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 5478 5479 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 5480 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 5481 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 5482 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 5483 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 5484 5485 #define S_FW_EQ_CTRL_CMD_EQID 0 5486 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 5487 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 5488 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 5489 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 5490 5491 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 5492 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 5493 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 5494 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 5495 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 5496 5497 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 5498 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 5499 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 5500 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 5501 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 5502 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 5503 5504 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 5505 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 5506 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 5507 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 5508 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 5509 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 5510 5511 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 5512 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 5513 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 5514 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 5515 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 5516 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 5517 5518 #define S_FW_EQ_CTRL_CMD_FETCHNS 23 5519 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 5520 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 5521 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 5522 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 5523 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 5524 5525 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 5526 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 5527 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 5528 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 5529 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 5530 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 5531 5532 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 5533 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 5534 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 5535 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 5536 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 5537 5538 #define S_FW_EQ_CTRL_CMD_CPRIO 19 5539 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 5540 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 5541 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 5542 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 5543 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 5544 5545 #define S_FW_EQ_CTRL_CMD_ONCHIP 18 5546 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 5547 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 5548 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 5549 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 5550 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 5551 5552 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 5553 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 5554 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 5555 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 5556 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 5557 5558 #define S_FW_EQ_CTRL_CMD_IQID 0 5559 #define M_FW_EQ_CTRL_CMD_IQID 0xffff 5560 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 5561 #define G_FW_EQ_CTRL_CMD_IQID(x) \ 5562 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 5563 5564 #define S_FW_EQ_CTRL_CMD_DCAEN 31 5565 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 5566 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 5567 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 5568 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 5569 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 5570 5571 #define S_FW_EQ_CTRL_CMD_DCACPU 26 5572 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 5573 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 5574 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 5575 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 5576 5577 #define S_FW_EQ_CTRL_CMD_FBMIN 23 5578 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 5579 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 5580 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 5581 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 5582 5583 #define S_FW_EQ_CTRL_CMD_FBMAX 20 5584 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 5585 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 5586 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 5587 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 5588 5589 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 5590 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 5591 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 5592 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 5593 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 5594 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 5595 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 5596 5597 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 5598 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 5599 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 5600 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 5601 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 5602 5603 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 5604 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 5605 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 5606 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 5607 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 5608 5609 struct fw_eq_ofld_cmd { 5610 __be32 op_to_vfn; 5611 __be32 alloc_to_len16; 5612 __be32 eqid_pkd; 5613 __be32 physeqid_pkd; 5614 __be32 fetchszm_to_iqid; 5615 __be32 dcaen_to_eqsize; 5616 __be64 eqaddr; 5617 }; 5618 5619 #define S_FW_EQ_OFLD_CMD_PFN 8 5620 #define M_FW_EQ_OFLD_CMD_PFN 0x7 5621 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 5622 #define G_FW_EQ_OFLD_CMD_PFN(x) \ 5623 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 5624 5625 #define S_FW_EQ_OFLD_CMD_VFN 0 5626 #define M_FW_EQ_OFLD_CMD_VFN 0xff 5627 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 5628 #define G_FW_EQ_OFLD_CMD_VFN(x) \ 5629 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 5630 5631 #define S_FW_EQ_OFLD_CMD_ALLOC 31 5632 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 5633 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 5634 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 5635 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 5636 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 5637 5638 #define S_FW_EQ_OFLD_CMD_FREE 30 5639 #define M_FW_EQ_OFLD_CMD_FREE 0x1 5640 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 5641 #define G_FW_EQ_OFLD_CMD_FREE(x) \ 5642 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 5643 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 5644 5645 #define S_FW_EQ_OFLD_CMD_MODIFY 29 5646 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 5647 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 5648 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 5649 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 5650 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 5651 5652 #define S_FW_EQ_OFLD_CMD_EQSTART 28 5653 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 5654 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 5655 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 5656 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 5657 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 5658 5659 #define S_FW_EQ_OFLD_CMD_EQSTOP 27 5660 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 5661 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 5662 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 5663 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 5664 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 5665 5666 #define S_FW_EQ_OFLD_CMD_EQID 0 5667 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 5668 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 5669 #define G_FW_EQ_OFLD_CMD_EQID(x) \ 5670 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 5671 5672 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 5673 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 5674 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 5675 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 5676 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 5677 5678 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 5679 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 5680 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 5681 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 5682 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 5683 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 5684 5685 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 5686 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 5687 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 5688 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 5689 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 5690 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 5691 5692 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 5693 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 5694 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 5695 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 5696 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 5697 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 5698 5699 #define S_FW_EQ_OFLD_CMD_FETCHNS 23 5700 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 5701 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 5702 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 5703 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 5704 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 5705 5706 #define S_FW_EQ_OFLD_CMD_FETCHRO 22 5707 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 5708 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 5709 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 5710 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 5711 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 5712 5713 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 5714 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 5715 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 5716 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 5717 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 5718 5719 #define S_FW_EQ_OFLD_CMD_CPRIO 19 5720 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 5721 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 5722 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 5723 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 5724 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 5725 5726 #define S_FW_EQ_OFLD_CMD_ONCHIP 18 5727 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 5728 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 5729 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 5730 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 5731 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 5732 5733 #define S_FW_EQ_OFLD_CMD_PCIECHN 16 5734 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 5735 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 5736 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 5737 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 5738 5739 #define S_FW_EQ_OFLD_CMD_IQID 0 5740 #define M_FW_EQ_OFLD_CMD_IQID 0xffff 5741 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 5742 #define G_FW_EQ_OFLD_CMD_IQID(x) \ 5743 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 5744 5745 #define S_FW_EQ_OFLD_CMD_DCAEN 31 5746 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 5747 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 5748 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 5749 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 5750 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 5751 5752 #define S_FW_EQ_OFLD_CMD_DCACPU 26 5753 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 5754 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 5755 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 5756 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 5757 5758 #define S_FW_EQ_OFLD_CMD_FBMIN 23 5759 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 5760 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 5761 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 5762 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 5763 5764 #define S_FW_EQ_OFLD_CMD_FBMAX 20 5765 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 5766 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 5767 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 5768 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 5769 5770 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 5771 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 5772 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 5773 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 5774 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 5775 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 5776 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 5777 5778 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 5779 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 5780 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 5781 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 5782 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 5783 5784 #define S_FW_EQ_OFLD_CMD_EQSIZE 0 5785 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 5786 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 5787 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 5788 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 5789 5790 /* Macros for VIID parsing: 5791 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 5792 #define S_FW_VIID_PFN 8 5793 #define M_FW_VIID_PFN 0x7 5794 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 5795 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 5796 5797 #define S_FW_VIID_VIVLD 7 5798 #define M_FW_VIID_VIVLD 0x1 5799 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 5800 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 5801 5802 #define S_FW_VIID_VIN 0 5803 #define M_FW_VIID_VIN 0x7F 5804 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 5805 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 5806 5807 enum fw_vi_func { 5808 FW_VI_FUNC_ETH, 5809 FW_VI_FUNC_OFLD, 5810 FW_VI_FUNC_IWARP, 5811 FW_VI_FUNC_OPENISCSI, 5812 FW_VI_FUNC_OPENFCOE, 5813 FW_VI_FUNC_FOISCSI, 5814 FW_VI_FUNC_FOFCOE, 5815 FW_VI_FUNC_FW, 5816 }; 5817 5818 struct fw_vi_cmd { 5819 __be32 op_to_vfn; 5820 __be32 alloc_to_len16; 5821 __be16 type_to_viid; 5822 __u8 mac[6]; 5823 __u8 portid_pkd; 5824 __u8 nmac; 5825 __u8 nmac0[6]; 5826 __be16 norss_rsssize; 5827 __u8 nmac1[6]; 5828 __be16 idsiiq_pkd; 5829 __u8 nmac2[6]; 5830 __be16 idseiq_pkd; 5831 __u8 nmac3[6]; 5832 __be64 r9; 5833 __be64 r10; 5834 }; 5835 5836 #define S_FW_VI_CMD_PFN 8 5837 #define M_FW_VI_CMD_PFN 0x7 5838 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 5839 #define G_FW_VI_CMD_PFN(x) \ 5840 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 5841 5842 #define S_FW_VI_CMD_VFN 0 5843 #define M_FW_VI_CMD_VFN 0xff 5844 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 5845 #define G_FW_VI_CMD_VFN(x) \ 5846 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 5847 5848 #define S_FW_VI_CMD_ALLOC 31 5849 #define M_FW_VI_CMD_ALLOC 0x1 5850 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 5851 #define G_FW_VI_CMD_ALLOC(x) \ 5852 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 5853 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 5854 5855 #define S_FW_VI_CMD_FREE 30 5856 #define M_FW_VI_CMD_FREE 0x1 5857 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 5858 #define G_FW_VI_CMD_FREE(x) \ 5859 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 5860 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 5861 5862 #define S_FW_VI_CMD_TYPE 15 5863 #define M_FW_VI_CMD_TYPE 0x1 5864 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 5865 #define G_FW_VI_CMD_TYPE(x) \ 5866 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 5867 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 5868 5869 #define S_FW_VI_CMD_FUNC 12 5870 #define M_FW_VI_CMD_FUNC 0x7 5871 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 5872 #define G_FW_VI_CMD_FUNC(x) \ 5873 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 5874 5875 #define S_FW_VI_CMD_VIID 0 5876 #define M_FW_VI_CMD_VIID 0xfff 5877 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 5878 #define G_FW_VI_CMD_VIID(x) \ 5879 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 5880 5881 #define S_FW_VI_CMD_PORTID 4 5882 #define M_FW_VI_CMD_PORTID 0xf 5883 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 5884 #define G_FW_VI_CMD_PORTID(x) \ 5885 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 5886 5887 #define S_FW_VI_CMD_NORSS 11 5888 #define M_FW_VI_CMD_NORSS 0x1 5889 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 5890 #define G_FW_VI_CMD_NORSS(x) \ 5891 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 5892 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 5893 5894 #define S_FW_VI_CMD_RSSSIZE 0 5895 #define M_FW_VI_CMD_RSSSIZE 0x7ff 5896 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 5897 #define G_FW_VI_CMD_RSSSIZE(x) \ 5898 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 5899 5900 #define S_FW_VI_CMD_IDSIIQ 0 5901 #define M_FW_VI_CMD_IDSIIQ 0x3ff 5902 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 5903 #define G_FW_VI_CMD_IDSIIQ(x) \ 5904 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 5905 5906 #define S_FW_VI_CMD_IDSEIQ 0 5907 #define M_FW_VI_CMD_IDSEIQ 0x3ff 5908 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 5909 #define G_FW_VI_CMD_IDSEIQ(x) \ 5910 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 5911 5912 /* Special VI_MAC command index ids */ 5913 #define FW_VI_MAC_ADD_MAC 0x3FF 5914 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 5915 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 5916 5917 enum fw_vi_mac_smac { 5918 FW_VI_MAC_MPS_TCAM_ENTRY, 5919 FW_VI_MAC_MPS_TCAM_ONLY, 5920 FW_VI_MAC_SMT_ONLY, 5921 FW_VI_MAC_SMT_AND_MPSTCAM 5922 }; 5923 5924 enum fw_vi_mac_result { 5925 FW_VI_MAC_R_SUCCESS, 5926 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 5927 FW_VI_MAC_R_SMAC_FAIL, 5928 FW_VI_MAC_R_F_ACL_CHECK 5929 }; 5930 5931 enum fw_vi_mac_entry_types { 5932 FW_VI_MAC_TYPE_EXACTMAC, 5933 FW_VI_MAC_TYPE_HASHVEC, 5934 FW_VI_MAC_TYPE_RAW, 5935 }; 5936 5937 struct fw_vi_mac_cmd { 5938 __be32 op_to_viid; 5939 __be32 freemacs_to_len16; 5940 union fw_vi_mac { 5941 struct fw_vi_mac_exact { 5942 __be16 valid_to_idx; 5943 __u8 macaddr[6]; 5944 } exact[7]; 5945 struct fw_vi_mac_hash { 5946 __be64 hashvec; 5947 } hash; 5948 struct fw_vi_mac_raw { 5949 __be32 raw_idx_pkd; 5950 __be32 data0_pkd; 5951 __be32 data1[2]; 5952 __be64 data0m_pkd; 5953 __be32 data1m[2]; 5954 } raw; 5955 } u; 5956 }; 5957 5958 #define S_FW_VI_MAC_CMD_VIID 0 5959 #define M_FW_VI_MAC_CMD_VIID 0xfff 5960 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 5961 #define G_FW_VI_MAC_CMD_VIID(x) \ 5962 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 5963 5964 #define S_FW_VI_MAC_CMD_FREEMACS 31 5965 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 5966 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 5967 #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 5968 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 5969 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 5970 5971 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 5972 #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7 5973 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 5974 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \ 5975 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE) 5976 5977 #define S_FW_VI_MAC_CMD_HASHUNIEN 22 5978 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 5979 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 5980 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 5981 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 5982 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 5983 5984 #define S_FW_VI_MAC_CMD_VALID 15 5985 #define M_FW_VI_MAC_CMD_VALID 0x1 5986 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 5987 #define G_FW_VI_MAC_CMD_VALID(x) \ 5988 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 5989 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 5990 5991 #define S_FW_VI_MAC_CMD_PRIO 12 5992 #define M_FW_VI_MAC_CMD_PRIO 0x7 5993 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 5994 #define G_FW_VI_MAC_CMD_PRIO(x) \ 5995 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 5996 5997 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 5998 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 5999 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 6000 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 6001 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 6002 6003 #define S_FW_VI_MAC_CMD_IDX 0 6004 #define M_FW_VI_MAC_CMD_IDX 0x3ff 6005 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 6006 #define G_FW_VI_MAC_CMD_IDX(x) \ 6007 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 6008 6009 #define S_FW_VI_MAC_CMD_RAW_IDX 16 6010 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 6011 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 6012 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 6013 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 6014 6015 #define S_FW_VI_MAC_CMD_DATA0 0 6016 #define M_FW_VI_MAC_CMD_DATA0 0xffff 6017 #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0) 6018 #define G_FW_VI_MAC_CMD_DATA0(x) \ 6019 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0) 6020 6021 /* T4 max MTU supported */ 6022 #define T4_MAX_MTU_SUPPORTED 9600 6023 #define FW_RXMODE_MTU_NO_CHG 65535 6024 6025 struct fw_vi_rxmode_cmd { 6026 __be32 op_to_viid; 6027 __be32 retval_len16; 6028 __be32 mtu_to_vlanexen; 6029 __be32 r4_lo; 6030 }; 6031 6032 #define S_FW_VI_RXMODE_CMD_VIID 0 6033 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 6034 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 6035 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 6036 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 6037 6038 #define S_FW_VI_RXMODE_CMD_MTU 16 6039 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 6040 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 6041 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 6042 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 6043 6044 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 6045 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 6046 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 6047 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 6048 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 6049 6050 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 6051 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 6052 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6053 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 6054 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6055 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 6056 6057 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 6058 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 6059 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6060 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 6061 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6062 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 6063 6064 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 6065 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 6066 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 6067 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 6068 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 6069 6070 struct fw_vi_enable_cmd { 6071 __be32 op_to_viid; 6072 __be32 ien_to_len16; 6073 __be16 blinkdur; 6074 __be16 r3; 6075 __be32 r4; 6076 }; 6077 6078 #define S_FW_VI_ENABLE_CMD_VIID 0 6079 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 6080 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 6081 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 6082 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 6083 6084 #define S_FW_VI_ENABLE_CMD_IEN 31 6085 #define M_FW_VI_ENABLE_CMD_IEN 0x1 6086 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 6087 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 6088 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 6089 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 6090 6091 #define S_FW_VI_ENABLE_CMD_EEN 30 6092 #define M_FW_VI_ENABLE_CMD_EEN 0x1 6093 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 6094 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 6095 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 6096 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 6097 6098 #define S_FW_VI_ENABLE_CMD_LED 29 6099 #define M_FW_VI_ENABLE_CMD_LED 0x1 6100 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 6101 #define G_FW_VI_ENABLE_CMD_LED(x) \ 6102 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 6103 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 6104 6105 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 6106 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 6107 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 6108 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 6109 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 6110 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 6111 6112 /* VI VF stats offset definitions */ 6113 #define VI_VF_NUM_STATS 16 6114 enum fw_vi_stats_vf_index { 6115 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 6116 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 6117 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 6118 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 6119 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 6120 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 6121 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 6122 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 6123 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 6124 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 6125 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 6126 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 6127 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 6128 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 6129 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 6130 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 6131 }; 6132 6133 /* VI PF stats offset definitions */ 6134 #define VI_PF_NUM_STATS 17 6135 enum fw_vi_stats_pf_index { 6136 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 6137 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 6138 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 6139 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 6140 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 6141 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 6142 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 6143 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 6144 FW_VI_PF_STAT_RX_BYTES_IX, 6145 FW_VI_PF_STAT_RX_FRAMES_IX, 6146 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 6147 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 6148 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 6149 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 6150 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 6151 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 6152 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 6153 }; 6154 6155 struct fw_vi_stats_cmd { 6156 __be32 op_to_viid; 6157 __be32 retval_len16; 6158 union fw_vi_stats { 6159 struct fw_vi_stats_ctl { 6160 __be16 nstats_ix; 6161 __be16 r6; 6162 __be32 r7; 6163 __be64 stat0; 6164 __be64 stat1; 6165 __be64 stat2; 6166 __be64 stat3; 6167 __be64 stat4; 6168 __be64 stat5; 6169 } ctl; 6170 struct fw_vi_stats_pf { 6171 __be64 tx_bcast_bytes; 6172 __be64 tx_bcast_frames; 6173 __be64 tx_mcast_bytes; 6174 __be64 tx_mcast_frames; 6175 __be64 tx_ucast_bytes; 6176 __be64 tx_ucast_frames; 6177 __be64 tx_offload_bytes; 6178 __be64 tx_offload_frames; 6179 __be64 rx_pf_bytes; 6180 __be64 rx_pf_frames; 6181 __be64 rx_bcast_bytes; 6182 __be64 rx_bcast_frames; 6183 __be64 rx_mcast_bytes; 6184 __be64 rx_mcast_frames; 6185 __be64 rx_ucast_bytes; 6186 __be64 rx_ucast_frames; 6187 __be64 rx_err_frames; 6188 } pf; 6189 struct fw_vi_stats_vf { 6190 __be64 tx_bcast_bytes; 6191 __be64 tx_bcast_frames; 6192 __be64 tx_mcast_bytes; 6193 __be64 tx_mcast_frames; 6194 __be64 tx_ucast_bytes; 6195 __be64 tx_ucast_frames; 6196 __be64 tx_drop_frames; 6197 __be64 tx_offload_bytes; 6198 __be64 tx_offload_frames; 6199 __be64 rx_bcast_bytes; 6200 __be64 rx_bcast_frames; 6201 __be64 rx_mcast_bytes; 6202 __be64 rx_mcast_frames; 6203 __be64 rx_ucast_bytes; 6204 __be64 rx_ucast_frames; 6205 __be64 rx_err_frames; 6206 } vf; 6207 } u; 6208 }; 6209 6210 #define S_FW_VI_STATS_CMD_VIID 0 6211 #define M_FW_VI_STATS_CMD_VIID 0xfff 6212 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 6213 #define G_FW_VI_STATS_CMD_VIID(x) \ 6214 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 6215 6216 #define S_FW_VI_STATS_CMD_NSTATS 12 6217 #define M_FW_VI_STATS_CMD_NSTATS 0x7 6218 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 6219 #define G_FW_VI_STATS_CMD_NSTATS(x) \ 6220 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 6221 6222 #define S_FW_VI_STATS_CMD_IX 0 6223 #define M_FW_VI_STATS_CMD_IX 0x1f 6224 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 6225 #define G_FW_VI_STATS_CMD_IX(x) \ 6226 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 6227 6228 struct fw_acl_mac_cmd { 6229 __be32 op_to_vfn; 6230 __be32 en_to_len16; 6231 __u8 nmac; 6232 __u8 r3[7]; 6233 __be16 r4; 6234 __u8 macaddr0[6]; 6235 __be16 r5; 6236 __u8 macaddr1[6]; 6237 __be16 r6; 6238 __u8 macaddr2[6]; 6239 __be16 r7; 6240 __u8 macaddr3[6]; 6241 }; 6242 6243 #define S_FW_ACL_MAC_CMD_PFN 8 6244 #define M_FW_ACL_MAC_CMD_PFN 0x7 6245 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 6246 #define G_FW_ACL_MAC_CMD_PFN(x) \ 6247 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 6248 6249 #define S_FW_ACL_MAC_CMD_VFN 0 6250 #define M_FW_ACL_MAC_CMD_VFN 0xff 6251 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 6252 #define G_FW_ACL_MAC_CMD_VFN(x) \ 6253 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 6254 6255 #define S_FW_ACL_MAC_CMD_EN 31 6256 #define M_FW_ACL_MAC_CMD_EN 0x1 6257 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 6258 #define G_FW_ACL_MAC_CMD_EN(x) \ 6259 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 6260 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 6261 6262 struct fw_acl_vlan_cmd { 6263 __be32 op_to_vfn; 6264 __be32 en_to_len16; 6265 __u8 nvlan; 6266 __u8 dropnovlan_fm; 6267 __u8 r3_lo[6]; 6268 __be16 vlanid[16]; 6269 }; 6270 6271 #define S_FW_ACL_VLAN_CMD_PFN 8 6272 #define M_FW_ACL_VLAN_CMD_PFN 0x7 6273 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 6274 #define G_FW_ACL_VLAN_CMD_PFN(x) \ 6275 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 6276 6277 #define S_FW_ACL_VLAN_CMD_VFN 0 6278 #define M_FW_ACL_VLAN_CMD_VFN 0xff 6279 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 6280 #define G_FW_ACL_VLAN_CMD_VFN(x) \ 6281 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 6282 6283 #define S_FW_ACL_VLAN_CMD_EN 31 6284 #define M_FW_ACL_VLAN_CMD_EN 0x1 6285 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 6286 #define G_FW_ACL_VLAN_CMD_EN(x) \ 6287 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 6288 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 6289 6290 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 6291 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 6292 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 6293 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 6294 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 6295 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 6296 6297 #define S_FW_ACL_VLAN_CMD_FM 6 6298 #define M_FW_ACL_VLAN_CMD_FM 0x1 6299 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 6300 #define G_FW_ACL_VLAN_CMD_FM(x) \ 6301 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 6302 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 6303 6304 /* port capabilities bitmap */ 6305 enum fw_port_cap { 6306 FW_PORT_CAP_SPEED_100M = 0x0001, 6307 FW_PORT_CAP_SPEED_1G = 0x0002, 6308 FW_PORT_CAP_SPEED_2_5G = 0x0004, 6309 FW_PORT_CAP_SPEED_10G = 0x0008, 6310 FW_PORT_CAP_SPEED_40G = 0x0010, 6311 FW_PORT_CAP_SPEED_100G = 0x0020, 6312 FW_PORT_CAP_FC_RX = 0x0040, 6313 FW_PORT_CAP_FC_TX = 0x0080, 6314 FW_PORT_CAP_ANEG = 0x0100, 6315 FW_PORT_CAP_MDIX = 0x0200, 6316 FW_PORT_CAP_MDIAUTO = 0x0400, 6317 FW_PORT_CAP_FEC = 0x0800, 6318 FW_PORT_CAP_TECHKR = 0x1000, 6319 FW_PORT_CAP_TECHKX4 = 0x2000, 6320 FW_PORT_CAP_802_3_PAUSE = 0x4000, 6321 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 6322 }; 6323 6324 #define S_FW_PORT_AUXLINFO_MDI 3 6325 #define M_FW_PORT_AUXLINFO_MDI 0x3 6326 #define V_FW_PORT_AUXLINFO_MDI(x) ((x) << S_FW_PORT_AUXLINFO_MDI) 6327 #define G_FW_PORT_AUXLINFO_MDI(x) \ 6328 (((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI) 6329 6330 #define S_FW_PORT_AUXLINFO_KX4 2 6331 #define M_FW_PORT_AUXLINFO_KX4 0x1 6332 #define V_FW_PORT_AUXLINFO_KX4(x) ((x) << S_FW_PORT_AUXLINFO_KX4) 6333 #define G_FW_PORT_AUXLINFO_KX4(x) \ 6334 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 6335 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 6336 6337 #define S_FW_PORT_AUXLINFO_KR 1 6338 #define M_FW_PORT_AUXLINFO_KR 0x1 6339 #define V_FW_PORT_AUXLINFO_KR(x) ((x) << S_FW_PORT_AUXLINFO_KR) 6340 #define G_FW_PORT_AUXLINFO_KR(x) \ 6341 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 6342 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 6343 6344 #define S_FW_PORT_AUXLINFO_FEC 0 6345 #define M_FW_PORT_AUXLINFO_FEC 0x1 6346 #define V_FW_PORT_AUXLINFO_FEC(x) ((x) << S_FW_PORT_AUXLINFO_FEC) 6347 #define G_FW_PORT_AUXLINFO_FEC(x) \ 6348 (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) 6349 #define F_FW_PORT_AUXLINFO_FEC V_FW_PORT_AUXLINFO_FEC(1U) 6350 6351 #define S_FW_PORT_RCAP_AUX 11 6352 #define M_FW_PORT_RCAP_AUX 0x7 6353 #define V_FW_PORT_RCAP_AUX(x) ((x) << S_FW_PORT_RCAP_AUX) 6354 #define G_FW_PORT_RCAP_AUX(x) \ 6355 (((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX) 6356 6357 #define S_FW_PORT_CAP_SPEED 0 6358 #define M_FW_PORT_CAP_SPEED 0x3f 6359 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 6360 #define G_FW_PORT_CAP_SPEED(x) \ 6361 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 6362 6363 #define S_FW_PORT_CAP_FC 6 6364 #define M_FW_PORT_CAP_FC 0x3 6365 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 6366 #define G_FW_PORT_CAP_FC(x) \ 6367 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 6368 6369 #define S_FW_PORT_CAP_ANEG 8 6370 #define M_FW_PORT_CAP_ANEG 0x1 6371 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 6372 #define G_FW_PORT_CAP_ANEG(x) \ 6373 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 6374 6375 #define S_FW_PORT_CAP_802_3 14 6376 #define M_FW_PORT_CAP_802_3 0x3 6377 #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) 6378 #define G_FW_PORT_CAP_802_3(x) \ 6379 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) 6380 6381 enum fw_port_mdi { 6382 FW_PORT_CAP_MDI_UNCHANGED, 6383 FW_PORT_CAP_MDI_AUTO, 6384 FW_PORT_CAP_MDI_F_STRAIGHT, 6385 FW_PORT_CAP_MDI_F_CROSSOVER 6386 }; 6387 6388 #define S_FW_PORT_CAP_MDI 9 6389 #define M_FW_PORT_CAP_MDI 3 6390 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 6391 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 6392 6393 enum fw_port_action { 6394 FW_PORT_ACTION_L1_CFG = 0x0001, 6395 FW_PORT_ACTION_L2_CFG = 0x0002, 6396 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 6397 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 6398 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 6399 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 6400 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 6401 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 6402 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 6403 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 6404 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 6405 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 6406 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 6407 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 6408 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 6409 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 6410 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 6411 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 6412 FW_PORT_ACTION_PHY_RESET = 0x0040, 6413 FW_PORT_ACTION_PMA_RESET = 0x0041, 6414 FW_PORT_ACTION_PCS_RESET = 0x0042, 6415 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 6416 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 6417 FW_PORT_ACTION_AN_RESET = 0x0045, 6418 6419 }; 6420 6421 enum fw_port_l2cfg_ctlbf { 6422 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 6423 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 6424 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 6425 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 6426 FW_PORT_L2_CTLBF_IVLAN = 0x10, 6427 FW_PORT_L2_CTLBF_TXIPG = 0x20, 6428 FW_PORT_L2_CTLBF_MTU = 0x40 6429 }; 6430 6431 enum fw_dcb_app_tlv_sf { 6432 FW_DCB_APP_SF_ETHERTYPE, 6433 FW_DCB_APP_SF_SOCKET_TCP, 6434 FW_DCB_APP_SF_SOCKET_UDP, 6435 FW_DCB_APP_SF_SOCKET_ALL, 6436 }; 6437 6438 enum fw_port_dcb_versions { 6439 FW_PORT_DCB_VER_UNKNOWN, 6440 FW_PORT_DCB_VER_CEE1D0, 6441 FW_PORT_DCB_VER_CEE1D01, 6442 FW_PORT_DCB_VER_IEEE, 6443 FW_PORT_DCB_VER_AUTO=7 6444 }; 6445 6446 enum fw_port_dcb_cfg { 6447 FW_PORT_DCB_CFG_PG = 0x01, 6448 FW_PORT_DCB_CFG_PFC = 0x02, 6449 FW_PORT_DCB_CFG_APPL = 0x04 6450 }; 6451 6452 enum fw_port_dcb_cfg_rc { 6453 FW_PORT_DCB_CFG_SUCCESS = 0x0, 6454 FW_PORT_DCB_CFG_ERROR = 0x1 6455 }; 6456 6457 enum fw_port_dcb_type { 6458 FW_PORT_DCB_TYPE_PGID = 0x00, 6459 FW_PORT_DCB_TYPE_PGRATE = 0x01, 6460 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 6461 FW_PORT_DCB_TYPE_PFC = 0x03, 6462 FW_PORT_DCB_TYPE_APP_ID = 0x04, 6463 FW_PORT_DCB_TYPE_CONTROL = 0x05, 6464 }; 6465 6466 enum fw_port_dcb_feature_state { 6467 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 6468 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 6469 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 6470 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 6471 }; 6472 6473 enum fw_port_diag_ops { 6474 FW_PORT_DIAGS_TEMP = 0x00, 6475 FW_PORT_DIAGS_TX_POWER = 0x01, 6476 FW_PORT_DIAGS_RX_POWER = 0x02, 6477 FW_PORT_DIAGS_TX_DIS = 0x03, 6478 }; 6479 6480 struct fw_port_cmd { 6481 __be32 op_to_portid; 6482 __be32 action_to_len16; 6483 union fw_port { 6484 struct fw_port_l1cfg { 6485 __be32 rcap; 6486 __be32 r; 6487 } l1cfg; 6488 struct fw_port_l2cfg { 6489 __u8 ctlbf; 6490 __u8 ovlan3_to_ivlan0; 6491 __be16 ivlantype; 6492 __be16 txipg_force_pinfo; 6493 __be16 mtu; 6494 __be16 ovlan0mask; 6495 __be16 ovlan0type; 6496 __be16 ovlan1mask; 6497 __be16 ovlan1type; 6498 __be16 ovlan2mask; 6499 __be16 ovlan2type; 6500 __be16 ovlan3mask; 6501 __be16 ovlan3type; 6502 } l2cfg; 6503 struct fw_port_info { 6504 __be32 lstatus_to_modtype; 6505 __be16 pcap; 6506 __be16 acap; 6507 __be16 mtu; 6508 __u8 cbllen; 6509 __u8 auxlinfo; 6510 __u8 dcbxdis_pkd; 6511 __u8 r8_lo; 6512 __be16 lpacap; 6513 __be64 r9; 6514 } info; 6515 struct fw_port_diags { 6516 __u8 diagop; 6517 __u8 r[3]; 6518 __be32 diagval; 6519 } diags; 6520 union fw_port_dcb { 6521 struct fw_port_dcb_pgid { 6522 __u8 type; 6523 __u8 apply_pkd; 6524 __u8 r10_lo[2]; 6525 __be32 pgid; 6526 __be64 r11; 6527 } pgid; 6528 struct fw_port_dcb_pgrate { 6529 __u8 type; 6530 __u8 apply_pkd; 6531 __u8 r10_lo[5]; 6532 __u8 num_tcs_supported; 6533 __u8 pgrate[8]; 6534 __u8 tsa[8]; 6535 } pgrate; 6536 struct fw_port_dcb_priorate { 6537 __u8 type; 6538 __u8 apply_pkd; 6539 __u8 r10_lo[6]; 6540 __u8 strict_priorate[8]; 6541 } priorate; 6542 struct fw_port_dcb_pfc { 6543 __u8 type; 6544 __u8 pfcen; 6545 __u8 r10[5]; 6546 __u8 max_pfc_tcs; 6547 __be64 r11; 6548 } pfc; 6549 struct fw_port_app_priority { 6550 __u8 type; 6551 __u8 r10[2]; 6552 __u8 idx; 6553 __u8 user_prio_map; 6554 __u8 sel_field; 6555 __be16 protocolid; 6556 __be64 r12; 6557 } app_priority; 6558 struct fw_port_dcb_control { 6559 __u8 type; 6560 __u8 all_syncd_pkd; 6561 __be16 dcb_version_to_app_state; 6562 __be32 r11; 6563 __be64 r12; 6564 } control; 6565 } dcb; 6566 } u; 6567 }; 6568 6569 #define S_FW_PORT_CMD_READ 22 6570 #define M_FW_PORT_CMD_READ 0x1 6571 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 6572 #define G_FW_PORT_CMD_READ(x) \ 6573 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 6574 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 6575 6576 #define S_FW_PORT_CMD_PORTID 0 6577 #define M_FW_PORT_CMD_PORTID 0xf 6578 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 6579 #define G_FW_PORT_CMD_PORTID(x) \ 6580 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 6581 6582 #define S_FW_PORT_CMD_ACTION 16 6583 #define M_FW_PORT_CMD_ACTION 0xffff 6584 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 6585 #define G_FW_PORT_CMD_ACTION(x) \ 6586 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 6587 6588 #define S_FW_PORT_CMD_OVLAN3 7 6589 #define M_FW_PORT_CMD_OVLAN3 0x1 6590 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 6591 #define G_FW_PORT_CMD_OVLAN3(x) \ 6592 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 6593 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 6594 6595 #define S_FW_PORT_CMD_OVLAN2 6 6596 #define M_FW_PORT_CMD_OVLAN2 0x1 6597 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 6598 #define G_FW_PORT_CMD_OVLAN2(x) \ 6599 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 6600 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 6601 6602 #define S_FW_PORT_CMD_OVLAN1 5 6603 #define M_FW_PORT_CMD_OVLAN1 0x1 6604 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 6605 #define G_FW_PORT_CMD_OVLAN1(x) \ 6606 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 6607 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 6608 6609 #define S_FW_PORT_CMD_OVLAN0 4 6610 #define M_FW_PORT_CMD_OVLAN0 0x1 6611 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 6612 #define G_FW_PORT_CMD_OVLAN0(x) \ 6613 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 6614 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 6615 6616 #define S_FW_PORT_CMD_IVLAN0 3 6617 #define M_FW_PORT_CMD_IVLAN0 0x1 6618 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 6619 #define G_FW_PORT_CMD_IVLAN0(x) \ 6620 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 6621 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 6622 6623 #define S_FW_PORT_CMD_TXIPG 3 6624 #define M_FW_PORT_CMD_TXIPG 0x1fff 6625 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 6626 #define G_FW_PORT_CMD_TXIPG(x) \ 6627 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 6628 6629 #define S_FW_PORT_CMD_FORCE_PINFO 0 6630 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 6631 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 6632 #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 6633 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 6634 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 6635 6636 #define S_FW_PORT_CMD_LSTATUS 31 6637 #define M_FW_PORT_CMD_LSTATUS 0x1 6638 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 6639 #define G_FW_PORT_CMD_LSTATUS(x) \ 6640 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 6641 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 6642 6643 #define S_FW_PORT_CMD_LSPEED 24 6644 #define M_FW_PORT_CMD_LSPEED 0x3f 6645 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 6646 #define G_FW_PORT_CMD_LSPEED(x) \ 6647 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 6648 6649 #define S_FW_PORT_CMD_TXPAUSE 23 6650 #define M_FW_PORT_CMD_TXPAUSE 0x1 6651 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 6652 #define G_FW_PORT_CMD_TXPAUSE(x) \ 6653 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 6654 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 6655 6656 #define S_FW_PORT_CMD_RXPAUSE 22 6657 #define M_FW_PORT_CMD_RXPAUSE 0x1 6658 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 6659 #define G_FW_PORT_CMD_RXPAUSE(x) \ 6660 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 6661 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 6662 6663 #define S_FW_PORT_CMD_MDIOCAP 21 6664 #define M_FW_PORT_CMD_MDIOCAP 0x1 6665 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 6666 #define G_FW_PORT_CMD_MDIOCAP(x) \ 6667 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 6668 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 6669 6670 #define S_FW_PORT_CMD_MDIOADDR 16 6671 #define M_FW_PORT_CMD_MDIOADDR 0x1f 6672 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 6673 #define G_FW_PORT_CMD_MDIOADDR(x) \ 6674 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 6675 6676 #define S_FW_PORT_CMD_LPTXPAUSE 15 6677 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 6678 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 6679 #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 6680 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 6681 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 6682 6683 #define S_FW_PORT_CMD_LPRXPAUSE 14 6684 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 6685 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 6686 #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 6687 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 6688 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 6689 6690 #define S_FW_PORT_CMD_PTYPE 8 6691 #define M_FW_PORT_CMD_PTYPE 0x1f 6692 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 6693 #define G_FW_PORT_CMD_PTYPE(x) \ 6694 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 6695 6696 #define S_FW_PORT_CMD_LINKDNRC 5 6697 #define M_FW_PORT_CMD_LINKDNRC 0x7 6698 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 6699 #define G_FW_PORT_CMD_LINKDNRC(x) \ 6700 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 6701 6702 #define S_FW_PORT_CMD_MODTYPE 0 6703 #define M_FW_PORT_CMD_MODTYPE 0x1f 6704 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 6705 #define G_FW_PORT_CMD_MODTYPE(x) \ 6706 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 6707 6708 #define S_FW_PORT_CMD_DCBXDIS 7 6709 #define M_FW_PORT_CMD_DCBXDIS 0x1 6710 #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 6711 #define G_FW_PORT_CMD_DCBXDIS(x) \ 6712 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 6713 #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 6714 6715 #define S_FW_PORT_CMD_APPLY 7 6716 #define M_FW_PORT_CMD_APPLY 0x1 6717 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 6718 #define G_FW_PORT_CMD_APPLY(x) \ 6719 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 6720 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 6721 6722 #define S_FW_PORT_CMD_ALL_SYNCD 7 6723 #define M_FW_PORT_CMD_ALL_SYNCD 0x1 6724 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 6725 #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 6726 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 6727 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 6728 6729 #define S_FW_PORT_CMD_DCB_VERSION 12 6730 #define M_FW_PORT_CMD_DCB_VERSION 0x7 6731 #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) 6732 #define G_FW_PORT_CMD_DCB_VERSION(x) \ 6733 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) 6734 6735 #define S_FW_PORT_CMD_PFC_STATE 8 6736 #define M_FW_PORT_CMD_PFC_STATE 0xf 6737 #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 6738 #define G_FW_PORT_CMD_PFC_STATE(x) \ 6739 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 6740 6741 #define S_FW_PORT_CMD_ETS_STATE 4 6742 #define M_FW_PORT_CMD_ETS_STATE 0xf 6743 #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 6744 #define G_FW_PORT_CMD_ETS_STATE(x) \ 6745 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 6746 6747 #define S_FW_PORT_CMD_APP_STATE 0 6748 #define M_FW_PORT_CMD_APP_STATE 0xf 6749 #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 6750 #define G_FW_PORT_CMD_APP_STATE(x) \ 6751 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 6752 6753 /* 6754 * These are configured into the VPD and hence tools that generate 6755 * VPD may use this enumeration. 6756 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 6757 * 6758 * REMEMBER: 6759 * Update the Common Code t4_hw.c:t4_get_port_type_description() 6760 * with any new Firmware Port Technology Types! 6761 */ 6762 enum fw_port_type { 6763 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 6764 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 6765 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 6766 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ 6767 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ 6768 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 6769 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 6770 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 6771 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 6772 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 6773 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 6774 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 6775 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 6776 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 6777 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 6778 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 6779 6780 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 6781 }; 6782 6783 /* These are read from module's EEPROM and determined once the 6784 module is inserted. */ 6785 enum fw_port_module_type { 6786 FW_PORT_MOD_TYPE_NA = 0x0, 6787 FW_PORT_MOD_TYPE_LR = 0x1, 6788 FW_PORT_MOD_TYPE_SR = 0x2, 6789 FW_PORT_MOD_TYPE_ER = 0x3, 6790 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 6791 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 6792 FW_PORT_MOD_TYPE_LRM = 0x6, 6793 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 6794 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 6795 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 6796 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 6797 }; 6798 6799 /* used by FW and tools may use this to generate VPD */ 6800 enum fw_port_mod_sub_type { 6801 FW_PORT_MOD_SUB_TYPE_NA, 6802 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 6803 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 6804 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 6805 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 6806 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 6807 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 6808 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, 6809 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 6810 6811 /* 6812 * The following will never been in the VPD. They are TWINAX cable 6813 * lengths decoded from SFP+ module i2c PROMs. These should almost 6814 * certainly go somewhere else ... 6815 */ 6816 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 6817 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 6818 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 6819 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 6820 }; 6821 6822 /* link down reason codes (3b) */ 6823 enum fw_port_link_dn_rc { 6824 FW_PORT_LINK_DN_RC_NONE, 6825 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 6826 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 6827 FW_PORT_LINK_DN_RESERVED3, 6828 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 6829 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 6830 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 6831 FW_PORT_LINK_DN_RESERVED7 6832 }; 6833 enum fw_port_stats_tx_index { 6834 FW_STAT_TX_PORT_BYTES_IX = 0, 6835 FW_STAT_TX_PORT_FRAMES_IX, 6836 FW_STAT_TX_PORT_BCAST_IX, 6837 FW_STAT_TX_PORT_MCAST_IX, 6838 FW_STAT_TX_PORT_UCAST_IX, 6839 FW_STAT_TX_PORT_ERROR_IX, 6840 FW_STAT_TX_PORT_64B_IX, 6841 FW_STAT_TX_PORT_65B_127B_IX, 6842 FW_STAT_TX_PORT_128B_255B_IX, 6843 FW_STAT_TX_PORT_256B_511B_IX, 6844 FW_STAT_TX_PORT_512B_1023B_IX, 6845 FW_STAT_TX_PORT_1024B_1518B_IX, 6846 FW_STAT_TX_PORT_1519B_MAX_IX, 6847 FW_STAT_TX_PORT_DROP_IX, 6848 FW_STAT_TX_PORT_PAUSE_IX, 6849 FW_STAT_TX_PORT_PPP0_IX, 6850 FW_STAT_TX_PORT_PPP1_IX, 6851 FW_STAT_TX_PORT_PPP2_IX, 6852 FW_STAT_TX_PORT_PPP3_IX, 6853 FW_STAT_TX_PORT_PPP4_IX, 6854 FW_STAT_TX_PORT_PPP5_IX, 6855 FW_STAT_TX_PORT_PPP6_IX, 6856 FW_STAT_TX_PORT_PPP7_IX, 6857 FW_NUM_PORT_TX_STATS 6858 }; 6859 6860 enum fw_port_stat_rx_index { 6861 FW_STAT_RX_PORT_BYTES_IX = 0, 6862 FW_STAT_RX_PORT_FRAMES_IX, 6863 FW_STAT_RX_PORT_BCAST_IX, 6864 FW_STAT_RX_PORT_MCAST_IX, 6865 FW_STAT_RX_PORT_UCAST_IX, 6866 FW_STAT_RX_PORT_MTU_ERROR_IX, 6867 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 6868 FW_STAT_RX_PORT_CRC_ERROR_IX, 6869 FW_STAT_RX_PORT_LEN_ERROR_IX, 6870 FW_STAT_RX_PORT_SYM_ERROR_IX, 6871 FW_STAT_RX_PORT_64B_IX, 6872 FW_STAT_RX_PORT_65B_127B_IX, 6873 FW_STAT_RX_PORT_128B_255B_IX, 6874 FW_STAT_RX_PORT_256B_511B_IX, 6875 FW_STAT_RX_PORT_512B_1023B_IX, 6876 FW_STAT_RX_PORT_1024B_1518B_IX, 6877 FW_STAT_RX_PORT_1519B_MAX_IX, 6878 FW_STAT_RX_PORT_PAUSE_IX, 6879 FW_STAT_RX_PORT_PPP0_IX, 6880 FW_STAT_RX_PORT_PPP1_IX, 6881 FW_STAT_RX_PORT_PPP2_IX, 6882 FW_STAT_RX_PORT_PPP3_IX, 6883 FW_STAT_RX_PORT_PPP4_IX, 6884 FW_STAT_RX_PORT_PPP5_IX, 6885 FW_STAT_RX_PORT_PPP6_IX, 6886 FW_STAT_RX_PORT_PPP7_IX, 6887 FW_STAT_RX_PORT_LESS_64B_IX, 6888 FW_STAT_RX_PORT_MAC_ERROR_IX, 6889 FW_NUM_PORT_RX_STATS 6890 }; 6891 /* port stats */ 6892 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ 6893 FW_NUM_PORT_RX_STATS) 6894 6895 6896 struct fw_port_stats_cmd { 6897 __be32 op_to_portid; 6898 __be32 retval_len16; 6899 union fw_port_stats { 6900 struct fw_port_stats_ctl { 6901 __u8 nstats_bg_bm; 6902 __u8 tx_ix; 6903 __be16 r6; 6904 __be32 r7; 6905 __be64 stat0; 6906 __be64 stat1; 6907 __be64 stat2; 6908 __be64 stat3; 6909 __be64 stat4; 6910 __be64 stat5; 6911 } ctl; 6912 struct fw_port_stats_all { 6913 __be64 tx_bytes; 6914 __be64 tx_frames; 6915 __be64 tx_bcast; 6916 __be64 tx_mcast; 6917 __be64 tx_ucast; 6918 __be64 tx_error; 6919 __be64 tx_64b; 6920 __be64 tx_65b_127b; 6921 __be64 tx_128b_255b; 6922 __be64 tx_256b_511b; 6923 __be64 tx_512b_1023b; 6924 __be64 tx_1024b_1518b; 6925 __be64 tx_1519b_max; 6926 __be64 tx_drop; 6927 __be64 tx_pause; 6928 __be64 tx_ppp0; 6929 __be64 tx_ppp1; 6930 __be64 tx_ppp2; 6931 __be64 tx_ppp3; 6932 __be64 tx_ppp4; 6933 __be64 tx_ppp5; 6934 __be64 tx_ppp6; 6935 __be64 tx_ppp7; 6936 __be64 rx_bytes; 6937 __be64 rx_frames; 6938 __be64 rx_bcast; 6939 __be64 rx_mcast; 6940 __be64 rx_ucast; 6941 __be64 rx_mtu_error; 6942 __be64 rx_mtu_crc_error; 6943 __be64 rx_crc_error; 6944 __be64 rx_len_error; 6945 __be64 rx_sym_error; 6946 __be64 rx_64b; 6947 __be64 rx_65b_127b; 6948 __be64 rx_128b_255b; 6949 __be64 rx_256b_511b; 6950 __be64 rx_512b_1023b; 6951 __be64 rx_1024b_1518b; 6952 __be64 rx_1519b_max; 6953 __be64 rx_pause; 6954 __be64 rx_ppp0; 6955 __be64 rx_ppp1; 6956 __be64 rx_ppp2; 6957 __be64 rx_ppp3; 6958 __be64 rx_ppp4; 6959 __be64 rx_ppp5; 6960 __be64 rx_ppp6; 6961 __be64 rx_ppp7; 6962 __be64 rx_less_64b; 6963 __be64 rx_bg_drop; 6964 __be64 rx_bg_trunc; 6965 } all; 6966 } u; 6967 }; 6968 6969 #define S_FW_PORT_STATS_CMD_NSTATS 4 6970 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 6971 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 6972 #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 6973 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 6974 6975 #define S_FW_PORT_STATS_CMD_BG_BM 0 6976 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 6977 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 6978 #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 6979 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 6980 6981 #define S_FW_PORT_STATS_CMD_TX 7 6982 #define M_FW_PORT_STATS_CMD_TX 0x1 6983 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 6984 #define G_FW_PORT_STATS_CMD_TX(x) \ 6985 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 6986 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 6987 6988 #define S_FW_PORT_STATS_CMD_IX 0 6989 #define M_FW_PORT_STATS_CMD_IX 0x3f 6990 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 6991 #define G_FW_PORT_STATS_CMD_IX(x) \ 6992 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 6993 6994 /* port loopback stats */ 6995 #define FW_NUM_LB_STATS 14 6996 enum fw_port_lb_stats_index { 6997 FW_STAT_LB_PORT_BYTES_IX, 6998 FW_STAT_LB_PORT_FRAMES_IX, 6999 FW_STAT_LB_PORT_BCAST_IX, 7000 FW_STAT_LB_PORT_MCAST_IX, 7001 FW_STAT_LB_PORT_UCAST_IX, 7002 FW_STAT_LB_PORT_ERROR_IX, 7003 FW_STAT_LB_PORT_64B_IX, 7004 FW_STAT_LB_PORT_65B_127B_IX, 7005 FW_STAT_LB_PORT_128B_255B_IX, 7006 FW_STAT_LB_PORT_256B_511B_IX, 7007 FW_STAT_LB_PORT_512B_1023B_IX, 7008 FW_STAT_LB_PORT_1024B_1518B_IX, 7009 FW_STAT_LB_PORT_1519B_MAX_IX, 7010 FW_STAT_LB_PORT_DROP_FRAMES_IX 7011 }; 7012 7013 struct fw_port_lb_stats_cmd { 7014 __be32 op_to_lbport; 7015 __be32 retval_len16; 7016 union fw_port_lb_stats { 7017 struct fw_port_lb_stats_ctl { 7018 __u8 nstats_bg_bm; 7019 __u8 ix_pkd; 7020 __be16 r6; 7021 __be32 r7; 7022 __be64 stat0; 7023 __be64 stat1; 7024 __be64 stat2; 7025 __be64 stat3; 7026 __be64 stat4; 7027 __be64 stat5; 7028 } ctl; 7029 struct fw_port_lb_stats_all { 7030 __be64 tx_bytes; 7031 __be64 tx_frames; 7032 __be64 tx_bcast; 7033 __be64 tx_mcast; 7034 __be64 tx_ucast; 7035 __be64 tx_error; 7036 __be64 tx_64b; 7037 __be64 tx_65b_127b; 7038 __be64 tx_128b_255b; 7039 __be64 tx_256b_511b; 7040 __be64 tx_512b_1023b; 7041 __be64 tx_1024b_1518b; 7042 __be64 tx_1519b_max; 7043 __be64 rx_lb_drop; 7044 __be64 rx_lb_trunc; 7045 } all; 7046 } u; 7047 }; 7048 7049 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 7050 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 7051 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7052 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 7053 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7054 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 7055 7056 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 7057 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 7058 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7059 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 7060 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7061 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 7062 7063 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 7064 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 7065 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 7066 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 7067 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 7068 7069 #define S_FW_PORT_LB_STATS_CMD_IX 0 7070 #define M_FW_PORT_LB_STATS_CMD_IX 0xf 7071 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 7072 #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 7073 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 7074 7075 /* Trace related defines */ 7076 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 7077 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 7078 7079 struct fw_port_trace_cmd { 7080 __be32 op_to_portid; 7081 __be32 retval_len16; 7082 __be16 traceen_to_pciech; 7083 __be16 qnum; 7084 __be32 r5; 7085 }; 7086 7087 #define S_FW_PORT_TRACE_CMD_PORTID 0 7088 #define M_FW_PORT_TRACE_CMD_PORTID 0xf 7089 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 7090 #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 7091 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 7092 7093 #define S_FW_PORT_TRACE_CMD_TRACEEN 15 7094 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 7095 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 7096 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 7097 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 7098 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 7099 7100 #define S_FW_PORT_TRACE_CMD_FLTMODE 14 7101 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 7102 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 7103 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 7104 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 7105 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 7106 7107 #define S_FW_PORT_TRACE_CMD_DUPLEN 13 7108 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 7109 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 7110 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 7111 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 7112 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 7113 7114 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 7115 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 7116 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 7117 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 7118 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 7119 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 7120 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 7121 7122 #define S_FW_PORT_TRACE_CMD_PCIECH 6 7123 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 7124 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 7125 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 7126 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 7127 7128 struct fw_port_trace_mmap_cmd { 7129 __be32 op_to_portid; 7130 __be32 retval_len16; 7131 __be32 fid_to_skipoffset; 7132 __be32 minpktsize_capturemax; 7133 __u8 map[224]; 7134 }; 7135 7136 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 7137 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 7138 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 7139 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 7140 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 7141 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 7142 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 7143 7144 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 7145 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 7146 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 7147 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 7148 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 7149 7150 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 7151 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 7152 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 7153 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 7154 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 7155 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 7156 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 7157 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 7158 7159 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 7160 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 7161 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 7162 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 7163 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 7164 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 7165 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 7166 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 7167 7168 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 7169 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 7170 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 7171 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 7172 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 7173 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 7174 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 7175 7176 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 7177 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 7178 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 7179 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 7180 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 7181 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 7182 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 7183 7184 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 7185 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 7186 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 7187 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 7188 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 7189 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 7190 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 7191 7192 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 7193 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 7194 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 7195 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 7196 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 7197 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 7198 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 7199 7200 enum fw_ptp_subop { 7201 7202 /* none */ 7203 FW_PTP_SC_INIT_TIMER = 0x00, 7204 FW_PTP_SC_TX_TYPE = 0x01, 7205 7206 /* init */ 7207 FW_PTP_SC_RXTIME_STAMP = 0x08, 7208 FW_PTP_SC_RDRX_TYPE = 0x09, 7209 7210 /* ts */ 7211 FW_PTP_SC_ADJ_FREQ = 0x10, 7212 FW_PTP_SC_ADJ_TIME = 0x11, 7213 FW_PTP_SC_ADJ_FTIME = 0x12, 7214 FW_PTP_SC_WALL_CLOCK = 0x13, 7215 FW_PTP_SC_GET_TIME = 0x14, 7216 FW_PTP_SC_SET_TIME = 0x15, 7217 }; 7218 7219 struct fw_ptp_cmd { 7220 __be32 op_to_portid; 7221 __be32 retval_len16; 7222 union fw_ptp { 7223 struct fw_ptp_sc { 7224 __u8 sc; 7225 __u8 r3[7]; 7226 } scmd; 7227 struct fw_ptp_init { 7228 __u8 sc; 7229 __u8 txchan; 7230 __be16 absid; 7231 __be16 mode; 7232 __be16 r3; 7233 } init; 7234 struct fw_ptp_ts { 7235 __u8 sc; 7236 __u8 sign; 7237 __be16 r3; 7238 __be32 ppb; 7239 __be64 tm; 7240 } ts; 7241 } u; 7242 __be64 r3; 7243 }; 7244 7245 #define S_FW_PTP_CMD_PORTID 0 7246 #define M_FW_PTP_CMD_PORTID 0xf 7247 #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) 7248 #define G_FW_PTP_CMD_PORTID(x) \ 7249 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) 7250 7251 struct fw_rss_ind_tbl_cmd { 7252 __be32 op_to_viid; 7253 __be32 retval_len16; 7254 __be16 niqid; 7255 __be16 startidx; 7256 __be32 r3; 7257 __be32 iq0_to_iq2; 7258 __be32 iq3_to_iq5; 7259 __be32 iq6_to_iq8; 7260 __be32 iq9_to_iq11; 7261 __be32 iq12_to_iq14; 7262 __be32 iq15_to_iq17; 7263 __be32 iq18_to_iq20; 7264 __be32 iq21_to_iq23; 7265 __be32 iq24_to_iq26; 7266 __be32 iq27_to_iq29; 7267 __be32 iq30_iq31; 7268 __be32 r15_lo; 7269 }; 7270 7271 #define S_FW_RSS_IND_TBL_CMD_VIID 0 7272 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 7273 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 7274 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 7275 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 7276 7277 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 7278 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 7279 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 7280 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 7281 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 7282 7283 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 7284 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 7285 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 7286 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 7287 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 7288 7289 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 7290 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 7291 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 7292 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 7293 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 7294 7295 #define S_FW_RSS_IND_TBL_CMD_IQ3 20 7296 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 7297 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 7298 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 7299 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 7300 7301 #define S_FW_RSS_IND_TBL_CMD_IQ4 10 7302 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 7303 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 7304 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 7305 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 7306 7307 #define S_FW_RSS_IND_TBL_CMD_IQ5 0 7308 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 7309 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 7310 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 7311 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 7312 7313 #define S_FW_RSS_IND_TBL_CMD_IQ6 20 7314 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 7315 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 7316 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 7317 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 7318 7319 #define S_FW_RSS_IND_TBL_CMD_IQ7 10 7320 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 7321 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 7322 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 7323 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 7324 7325 #define S_FW_RSS_IND_TBL_CMD_IQ8 0 7326 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 7327 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 7328 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 7329 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 7330 7331 #define S_FW_RSS_IND_TBL_CMD_IQ9 20 7332 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 7333 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 7334 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 7335 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 7336 7337 #define S_FW_RSS_IND_TBL_CMD_IQ10 10 7338 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 7339 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 7340 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 7341 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 7342 7343 #define S_FW_RSS_IND_TBL_CMD_IQ11 0 7344 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 7345 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 7346 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 7347 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 7348 7349 #define S_FW_RSS_IND_TBL_CMD_IQ12 20 7350 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 7351 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 7352 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 7353 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 7354 7355 #define S_FW_RSS_IND_TBL_CMD_IQ13 10 7356 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 7357 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 7358 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 7359 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 7360 7361 #define S_FW_RSS_IND_TBL_CMD_IQ14 0 7362 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 7363 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 7364 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 7365 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 7366 7367 #define S_FW_RSS_IND_TBL_CMD_IQ15 20 7368 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 7369 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 7370 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 7371 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 7372 7373 #define S_FW_RSS_IND_TBL_CMD_IQ16 10 7374 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 7375 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 7376 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 7377 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 7378 7379 #define S_FW_RSS_IND_TBL_CMD_IQ17 0 7380 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 7381 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 7382 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 7383 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 7384 7385 #define S_FW_RSS_IND_TBL_CMD_IQ18 20 7386 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 7387 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 7388 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 7389 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 7390 7391 #define S_FW_RSS_IND_TBL_CMD_IQ19 10 7392 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 7393 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 7394 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 7395 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 7396 7397 #define S_FW_RSS_IND_TBL_CMD_IQ20 0 7398 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 7399 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 7400 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 7401 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 7402 7403 #define S_FW_RSS_IND_TBL_CMD_IQ21 20 7404 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 7405 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 7406 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 7407 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 7408 7409 #define S_FW_RSS_IND_TBL_CMD_IQ22 10 7410 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 7411 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 7412 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 7413 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 7414 7415 #define S_FW_RSS_IND_TBL_CMD_IQ23 0 7416 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 7417 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 7418 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 7419 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 7420 7421 #define S_FW_RSS_IND_TBL_CMD_IQ24 20 7422 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 7423 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 7424 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 7425 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 7426 7427 #define S_FW_RSS_IND_TBL_CMD_IQ25 10 7428 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 7429 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 7430 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 7431 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 7432 7433 #define S_FW_RSS_IND_TBL_CMD_IQ26 0 7434 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 7435 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 7436 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 7437 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 7438 7439 #define S_FW_RSS_IND_TBL_CMD_IQ27 20 7440 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 7441 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 7442 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 7443 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 7444 7445 #define S_FW_RSS_IND_TBL_CMD_IQ28 10 7446 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 7447 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 7448 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 7449 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 7450 7451 #define S_FW_RSS_IND_TBL_CMD_IQ29 0 7452 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 7453 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 7454 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 7455 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 7456 7457 #define S_FW_RSS_IND_TBL_CMD_IQ30 20 7458 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 7459 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 7460 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 7461 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 7462 7463 #define S_FW_RSS_IND_TBL_CMD_IQ31 10 7464 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 7465 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 7466 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 7467 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 7468 7469 struct fw_rss_glb_config_cmd { 7470 __be32 op_to_write; 7471 __be32 retval_len16; 7472 union fw_rss_glb_config { 7473 struct fw_rss_glb_config_manual { 7474 __be32 mode_pkd; 7475 __be32 r3; 7476 __be64 r4; 7477 __be64 r5; 7478 } manual; 7479 struct fw_rss_glb_config_basicvirtual { 7480 __be32 mode_pkd; 7481 __be32 synmapen_to_hashtoeplitz; 7482 __be64 r8; 7483 __be64 r9; 7484 } basicvirtual; 7485 } u; 7486 }; 7487 7488 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 7489 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 7490 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 7491 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 7492 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 7493 7494 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 7495 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 7496 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 7497 7498 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 7499 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 7500 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 7501 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 7502 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 7503 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 7504 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 7505 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 7506 7507 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 7508 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 7509 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 7510 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 7511 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 7512 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 7513 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 7514 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 7515 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 7516 7517 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 7518 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 7519 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 7520 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 7521 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 7522 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 7523 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 7524 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 7525 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 7526 7527 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 7528 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 7529 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 7530 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 7531 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 7532 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 7533 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 7534 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 7535 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 7536 7537 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 7538 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 7539 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 7540 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 7541 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 7542 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 7543 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 7544 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 7545 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 7546 7547 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 7548 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 7549 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 7550 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 7551 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 7552 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 7553 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 7554 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 7555 7556 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 7557 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 7558 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 7559 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 7560 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 7561 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 7562 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 7563 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 7564 7565 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 7566 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 7567 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 7568 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 7569 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 7570 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 7571 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 7572 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 7573 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 7574 7575 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 7576 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 7577 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 7578 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 7579 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 7580 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 7581 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 7582 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 7583 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 7584 7585 struct fw_rss_vi_config_cmd { 7586 __be32 op_to_viid; 7587 __be32 retval_len16; 7588 union fw_rss_vi_config { 7589 struct fw_rss_vi_config_manual { 7590 __be64 r3; 7591 __be64 r4; 7592 __be64 r5; 7593 } manual; 7594 struct fw_rss_vi_config_basicvirtual { 7595 __be32 r6; 7596 __be32 defaultq_to_udpen; 7597 __be64 r9; 7598 __be64 r10; 7599 } basicvirtual; 7600 } u; 7601 }; 7602 7603 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 7604 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 7605 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 7606 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 7607 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 7608 7609 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 7610 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 7611 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 7612 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 7613 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 7614 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 7615 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 7616 7617 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 7618 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 7619 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 7620 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 7621 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 7622 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 7623 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 7624 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 7625 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 7626 7627 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 7628 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 7629 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 7630 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 7631 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 7632 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 7633 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 7634 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 7635 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 7636 7637 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 7638 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 7639 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 7640 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 7641 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 7642 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 7643 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 7644 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 7645 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 7646 7647 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 7648 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 7649 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 7650 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 7651 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 7652 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 7653 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 7654 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 7655 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 7656 7657 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 7658 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 7659 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 7660 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 7661 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 7662 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 7663 7664 enum fw_sched_sc { 7665 FW_SCHED_SC_CONFIG = 0, 7666 FW_SCHED_SC_PARAMS = 1, 7667 }; 7668 7669 enum fw_sched_type { 7670 FW_SCHED_TYPE_PKTSCHED = 0, 7671 FW_SCHED_TYPE_STREAMSCHED = 1, 7672 }; 7673 7674 enum fw_sched_params_level { 7675 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 7676 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 7677 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 7678 }; 7679 7680 enum fw_sched_params_mode { 7681 FW_SCHED_PARAMS_MODE_CLASS = 0, 7682 FW_SCHED_PARAMS_MODE_FLOW = 1, 7683 }; 7684 7685 enum fw_sched_params_unit { 7686 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 7687 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 7688 }; 7689 7690 enum fw_sched_params_rate { 7691 FW_SCHED_PARAMS_RATE_REL = 0, 7692 FW_SCHED_PARAMS_RATE_ABS = 1, 7693 }; 7694 7695 struct fw_sched_cmd { 7696 __be32 op_to_write; 7697 __be32 retval_len16; 7698 union fw_sched { 7699 struct fw_sched_config { 7700 __u8 sc; 7701 __u8 type; 7702 __u8 minmaxen; 7703 __u8 r3[5]; 7704 __u8 nclasses[4]; 7705 __be32 r4; 7706 } config; 7707 struct fw_sched_params { 7708 __u8 sc; 7709 __u8 type; 7710 __u8 level; 7711 __u8 mode; 7712 __u8 unit; 7713 __u8 rate; 7714 __u8 ch; 7715 __u8 cl; 7716 __be32 min; 7717 __be32 max; 7718 __be16 weight; 7719 __be16 pktsize; 7720 __be16 burstsize; 7721 __be16 r4; 7722 } params; 7723 } u; 7724 }; 7725 7726 /* 7727 * length of the formatting string 7728 */ 7729 #define FW_DEVLOG_FMT_LEN 192 7730 7731 /* 7732 * maximum number of the formatting string parameters 7733 */ 7734 #define FW_DEVLOG_FMT_PARAMS_NUM 8 7735 7736 /* 7737 * priority levels 7738 */ 7739 enum fw_devlog_level { 7740 FW_DEVLOG_LEVEL_EMERG = 0x0, 7741 FW_DEVLOG_LEVEL_CRIT = 0x1, 7742 FW_DEVLOG_LEVEL_ERR = 0x2, 7743 FW_DEVLOG_LEVEL_NOTICE = 0x3, 7744 FW_DEVLOG_LEVEL_INFO = 0x4, 7745 FW_DEVLOG_LEVEL_DEBUG = 0x5, 7746 FW_DEVLOG_LEVEL_MAX = 0x5, 7747 }; 7748 7749 /* 7750 * facilities that may send a log message 7751 */ 7752 enum fw_devlog_facility { 7753 FW_DEVLOG_FACILITY_CORE = 0x00, 7754 FW_DEVLOG_FACILITY_CF = 0x01, 7755 FW_DEVLOG_FACILITY_SCHED = 0x02, 7756 FW_DEVLOG_FACILITY_TIMER = 0x04, 7757 FW_DEVLOG_FACILITY_RES = 0x06, 7758 FW_DEVLOG_FACILITY_HW = 0x08, 7759 FW_DEVLOG_FACILITY_FLR = 0x10, 7760 FW_DEVLOG_FACILITY_DMAQ = 0x12, 7761 FW_DEVLOG_FACILITY_PHY = 0x14, 7762 FW_DEVLOG_FACILITY_MAC = 0x16, 7763 FW_DEVLOG_FACILITY_PORT = 0x18, 7764 FW_DEVLOG_FACILITY_VI = 0x1A, 7765 FW_DEVLOG_FACILITY_FILTER = 0x1C, 7766 FW_DEVLOG_FACILITY_ACL = 0x1E, 7767 FW_DEVLOG_FACILITY_TM = 0x20, 7768 FW_DEVLOG_FACILITY_QFC = 0x22, 7769 FW_DEVLOG_FACILITY_DCB = 0x24, 7770 FW_DEVLOG_FACILITY_ETH = 0x26, 7771 FW_DEVLOG_FACILITY_OFLD = 0x28, 7772 FW_DEVLOG_FACILITY_RI = 0x2A, 7773 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 7774 FW_DEVLOG_FACILITY_FCOE = 0x2E, 7775 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 7776 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 7777 FW_DEVLOG_FACILITY_CHNET = 0x34, 7778 FW_DEVLOG_FACILITY_COiSCSI = 0x36, 7779 FW_DEVLOG_FACILITY_MAX = 0x38, 7780 }; 7781 7782 /* 7783 * log message format 7784 */ 7785 struct fw_devlog_e { 7786 __be64 timestamp; 7787 __be32 seqno; 7788 __be16 reserved1; 7789 __u8 level; 7790 __u8 facility; 7791 __u8 fmt[FW_DEVLOG_FMT_LEN]; 7792 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 7793 __be32 reserved3[4]; 7794 }; 7795 7796 struct fw_devlog_cmd { 7797 __be32 op_to_write; 7798 __be32 retval_len16; 7799 __u8 level; 7800 __u8 r2[7]; 7801 __be32 memtype_devlog_memaddr16_devlog; 7802 __be32 memsize_devlog; 7803 __be32 r3[2]; 7804 }; 7805 7806 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 7807 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 7808 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 7809 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 7810 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 7811 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 7812 7813 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 7814 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 7815 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 7816 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 7817 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 7818 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 7819 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 7820 7821 enum fw_watchdog_actions { 7822 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 7823 FW_WATCHDOG_ACTION_FLR = 1, 7824 FW_WATCHDOG_ACTION_BYPASS = 2, 7825 FW_WATCHDOG_ACTION_TMPCHK = 3, 7826 FW_WATCHDOG_ACTION_PAUSEOFF = 4, 7827 7828 FW_WATCHDOG_ACTION_MAX = 5, 7829 }; 7830 7831 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 7832 7833 struct fw_watchdog_cmd { 7834 __be32 op_to_vfn; 7835 __be32 retval_len16; 7836 __be32 timeout; 7837 __be32 action; 7838 }; 7839 7840 #define S_FW_WATCHDOG_CMD_PFN 8 7841 #define M_FW_WATCHDOG_CMD_PFN 0x7 7842 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 7843 #define G_FW_WATCHDOG_CMD_PFN(x) \ 7844 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 7845 7846 #define S_FW_WATCHDOG_CMD_VFN 0 7847 #define M_FW_WATCHDOG_CMD_VFN 0xff 7848 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 7849 #define G_FW_WATCHDOG_CMD_VFN(x) \ 7850 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 7851 7852 struct fw_clip_cmd { 7853 __be32 op_to_write; 7854 __be32 alloc_to_len16; 7855 __be64 ip_hi; 7856 __be64 ip_lo; 7857 __be32 r4[2]; 7858 }; 7859 7860 #define S_FW_CLIP_CMD_ALLOC 31 7861 #define M_FW_CLIP_CMD_ALLOC 0x1 7862 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 7863 #define G_FW_CLIP_CMD_ALLOC(x) \ 7864 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 7865 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 7866 7867 #define S_FW_CLIP_CMD_FREE 30 7868 #define M_FW_CLIP_CMD_FREE 0x1 7869 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 7870 #define G_FW_CLIP_CMD_FREE(x) \ 7871 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 7872 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 7873 7874 /****************************************************************************** 7875 * F O i S C S I C O M M A N D s 7876 **************************************/ 7877 7878 #define FW_CHNET_IFACE_ADDR_MAX 3 7879 7880 enum fw_chnet_iface_cmd_subop { 7881 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 7882 7883 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 7884 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 7885 7886 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 7887 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 7888 7889 FW_CHNET_IFACE_CMD_SUBOP_MAX, 7890 }; 7891 7892 struct fw_chnet_iface_cmd { 7893 __be32 op_to_portid; 7894 __be32 retval_len16; 7895 __u8 subop; 7896 __u8 r2[3]; 7897 __be32 ifid_ifstate; 7898 __be16 mtu; 7899 __be16 vlanid; 7900 __be32 r3; 7901 __be16 r4; 7902 __u8 mac[6]; 7903 }; 7904 7905 #define S_FW_CHNET_IFACE_CMD_PORTID 0 7906 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 7907 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 7908 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 7909 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 7910 7911 #define S_FW_CHNET_IFACE_CMD_IFID 8 7912 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 7913 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 7914 #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 7915 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 7916 7917 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 7918 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 7919 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 7920 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 7921 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 7922 7923 struct fw_fcoe_res_info_cmd { 7924 __be32 op_to_read; 7925 __be32 retval_len16; 7926 __be16 e_d_tov; 7927 __be16 r_a_tov_seq; 7928 __be16 r_a_tov_els; 7929 __be16 r_r_tov; 7930 __be32 max_xchgs; 7931 __be32 max_ssns; 7932 __be32 used_xchgs; 7933 __be32 used_ssns; 7934 __be32 max_fcfs; 7935 __be32 max_vnps; 7936 __be32 used_fcfs; 7937 __be32 used_vnps; 7938 }; 7939 7940 struct fw_fcoe_link_cmd { 7941 __be32 op_to_portid; 7942 __be32 retval_len16; 7943 __be32 sub_opcode_fcfi; 7944 __u8 r3; 7945 __u8 lstatus; 7946 __be16 flags; 7947 __u8 r4; 7948 __u8 set_vlan; 7949 __be16 vlan_id; 7950 __be32 vnpi_pkd; 7951 __be16 r6; 7952 __u8 phy_mac[6]; 7953 __u8 vnport_wwnn[8]; 7954 __u8 vnport_wwpn[8]; 7955 }; 7956 7957 #define S_FW_FCOE_LINK_CMD_PORTID 0 7958 #define M_FW_FCOE_LINK_CMD_PORTID 0xf 7959 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 7960 #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 7961 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 7962 7963 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 7964 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 7965 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 7966 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 7967 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 7968 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 7969 7970 #define S_FW_FCOE_LINK_CMD_FCFI 0 7971 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 7972 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 7973 #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 7974 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 7975 7976 #define S_FW_FCOE_LINK_CMD_VNPI 0 7977 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 7978 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 7979 #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 7980 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 7981 7982 struct fw_fcoe_vnp_cmd { 7983 __be32 op_to_fcfi; 7984 __be32 alloc_to_len16; 7985 __be32 gen_wwn_to_vnpi; 7986 __be32 vf_id; 7987 __be16 iqid; 7988 __u8 vnport_mac[6]; 7989 __u8 vnport_wwnn[8]; 7990 __u8 vnport_wwpn[8]; 7991 __u8 cmn_srv_parms[16]; 7992 __u8 clsp_word_0_1[8]; 7993 }; 7994 7995 #define S_FW_FCOE_VNP_CMD_FCFI 0 7996 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 7997 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 7998 #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 7999 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 8000 8001 #define S_FW_FCOE_VNP_CMD_ALLOC 31 8002 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 8003 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 8004 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 8005 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 8006 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 8007 8008 #define S_FW_FCOE_VNP_CMD_FREE 30 8009 #define M_FW_FCOE_VNP_CMD_FREE 0x1 8010 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 8011 #define G_FW_FCOE_VNP_CMD_FREE(x) \ 8012 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 8013 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 8014 8015 #define S_FW_FCOE_VNP_CMD_MODIFY 29 8016 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 8017 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 8018 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 8019 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 8020 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 8021 8022 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 8023 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 8024 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 8025 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 8026 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 8027 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 8028 8029 #define S_FW_FCOE_VNP_CMD_PERSIST 21 8030 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 8031 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 8032 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 8033 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 8034 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 8035 8036 #define S_FW_FCOE_VNP_CMD_VFID_EN 20 8037 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 8038 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 8039 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 8040 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 8041 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 8042 8043 #define S_FW_FCOE_VNP_CMD_VNPI 0 8044 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 8045 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 8046 #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 8047 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 8048 8049 struct fw_fcoe_sparams_cmd { 8050 __be32 op_to_portid; 8051 __be32 retval_len16; 8052 __u8 r3[7]; 8053 __u8 cos; 8054 __u8 lport_wwnn[8]; 8055 __u8 lport_wwpn[8]; 8056 __u8 cmn_srv_parms[16]; 8057 __u8 cls_srv_parms[16]; 8058 }; 8059 8060 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 8061 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 8062 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 8063 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 8064 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 8065 8066 struct fw_fcoe_stats_cmd { 8067 __be32 op_to_flowid; 8068 __be32 free_to_len16; 8069 union fw_fcoe_stats { 8070 struct fw_fcoe_stats_ctl { 8071 __u8 nstats_port; 8072 __u8 port_valid_ix; 8073 __be16 r6; 8074 __be32 r7; 8075 __be64 stat0; 8076 __be64 stat1; 8077 __be64 stat2; 8078 __be64 stat3; 8079 __be64 stat4; 8080 __be64 stat5; 8081 } ctl; 8082 struct fw_fcoe_port_stats { 8083 __be64 tx_bcast_bytes; 8084 __be64 tx_bcast_frames; 8085 __be64 tx_mcast_bytes; 8086 __be64 tx_mcast_frames; 8087 __be64 tx_ucast_bytes; 8088 __be64 tx_ucast_frames; 8089 __be64 tx_drop_frames; 8090 __be64 tx_offload_bytes; 8091 __be64 tx_offload_frames; 8092 __be64 rx_bcast_bytes; 8093 __be64 rx_bcast_frames; 8094 __be64 rx_mcast_bytes; 8095 __be64 rx_mcast_frames; 8096 __be64 rx_ucast_bytes; 8097 __be64 rx_ucast_frames; 8098 __be64 rx_err_frames; 8099 } port_stats; 8100 struct fw_fcoe_fcf_stats { 8101 __be32 fip_tx_bytes; 8102 __be32 fip_tx_fr; 8103 __be64 fcf_ka; 8104 __be64 mcast_adv_rcvd; 8105 __be16 ucast_adv_rcvd; 8106 __be16 sol_sent; 8107 __be16 vlan_req; 8108 __be16 vlan_rpl; 8109 __be16 clr_vlink; 8110 __be16 link_down; 8111 __be16 link_up; 8112 __be16 logo; 8113 __be16 flogi_req; 8114 __be16 flogi_rpl; 8115 __be16 fdisc_req; 8116 __be16 fdisc_rpl; 8117 __be16 fka_prd_chg; 8118 __be16 fc_map_chg; 8119 __be16 vfid_chg; 8120 __u8 no_fka_req; 8121 __u8 no_vnp; 8122 } fcf_stats; 8123 struct fw_fcoe_pcb_stats { 8124 __be64 tx_bytes; 8125 __be64 tx_frames; 8126 __be64 rx_bytes; 8127 __be64 rx_frames; 8128 __be32 vnp_ka; 8129 __be32 unsol_els_rcvd; 8130 __be64 unsol_cmd_rcvd; 8131 __be16 implicit_logo; 8132 __be16 flogi_inv_sparm; 8133 __be16 fdisc_inv_sparm; 8134 __be16 flogi_rjt; 8135 __be16 fdisc_rjt; 8136 __be16 no_ssn; 8137 __be16 mac_flt_fail; 8138 __be16 inv_fr_rcvd; 8139 } pcb_stats; 8140 struct fw_fcoe_scb_stats { 8141 __be64 tx_bytes; 8142 __be64 tx_frames; 8143 __be64 rx_bytes; 8144 __be64 rx_frames; 8145 __be32 host_abrt_req; 8146 __be32 adap_auto_abrt; 8147 __be32 adap_abrt_rsp; 8148 __be32 host_ios_req; 8149 __be16 ssn_offl_ios; 8150 __be16 ssn_not_rdy_ios; 8151 __u8 rx_data_ddp_err; 8152 __u8 ddp_flt_set_err; 8153 __be16 rx_data_fr_err; 8154 __u8 bad_st_abrt_req; 8155 __u8 no_io_abrt_req; 8156 __u8 abort_tmo; 8157 __u8 abort_tmo_2; 8158 __be32 abort_req; 8159 __u8 no_ppod_res_tmo; 8160 __u8 bp_tmo; 8161 __u8 adap_auto_cls; 8162 __u8 no_io_cls_req; 8163 __be32 host_cls_req; 8164 __be64 unsol_cmd_rcvd; 8165 __be32 plogi_req_rcvd; 8166 __be32 prli_req_rcvd; 8167 __be16 logo_req_rcvd; 8168 __be16 prlo_req_rcvd; 8169 __be16 plogi_rjt_rcvd; 8170 __be16 prli_rjt_rcvd; 8171 __be32 adisc_req_rcvd; 8172 __be32 rscn_rcvd; 8173 __be32 rrq_req_rcvd; 8174 __be32 unsol_els_rcvd; 8175 __u8 adisc_rjt_rcvd; 8176 __u8 scr_rjt; 8177 __u8 ct_rjt; 8178 __u8 inval_bls_rcvd; 8179 __be32 ba_rjt_rcvd; 8180 } scb_stats; 8181 } u; 8182 }; 8183 8184 #define S_FW_FCOE_STATS_CMD_FLOWID 0 8185 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 8186 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 8187 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 8188 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 8189 8190 #define S_FW_FCOE_STATS_CMD_FREE 30 8191 #define M_FW_FCOE_STATS_CMD_FREE 0x1 8192 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 8193 #define G_FW_FCOE_STATS_CMD_FREE(x) \ 8194 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 8195 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 8196 8197 #define S_FW_FCOE_STATS_CMD_NSTATS 4 8198 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 8199 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 8200 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 8201 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 8202 8203 #define S_FW_FCOE_STATS_CMD_PORT 0 8204 #define M_FW_FCOE_STATS_CMD_PORT 0x3 8205 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 8206 #define G_FW_FCOE_STATS_CMD_PORT(x) \ 8207 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 8208 8209 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 8210 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 8211 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 8212 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 8213 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 8214 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 8215 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 8216 8217 #define S_FW_FCOE_STATS_CMD_IX 0 8218 #define M_FW_FCOE_STATS_CMD_IX 0x3f 8219 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 8220 #define G_FW_FCOE_STATS_CMD_IX(x) \ 8221 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 8222 8223 struct fw_fcoe_fcf_cmd { 8224 __be32 op_to_fcfi; 8225 __be32 retval_len16; 8226 __be16 priority_pkd; 8227 __u8 mac[6]; 8228 __u8 name_id[8]; 8229 __u8 fabric[8]; 8230 __be16 vf_id; 8231 __be16 max_fcoe_size; 8232 __u8 vlan_id; 8233 __u8 fc_map[3]; 8234 __be32 fka_adv; 8235 __be32 r6; 8236 __u8 r7_hi; 8237 __u8 fpma_to_portid; 8238 __u8 spma_mac[6]; 8239 __be64 r8; 8240 }; 8241 8242 #define S_FW_FCOE_FCF_CMD_FCFI 0 8243 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 8244 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 8245 #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 8246 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 8247 8248 #define S_FW_FCOE_FCF_CMD_PRIORITY 0 8249 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 8250 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 8251 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 8252 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 8253 8254 #define S_FW_FCOE_FCF_CMD_FPMA 6 8255 #define M_FW_FCOE_FCF_CMD_FPMA 0x1 8256 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 8257 #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 8258 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 8259 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 8260 8261 #define S_FW_FCOE_FCF_CMD_SPMA 5 8262 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 8263 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 8264 #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 8265 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 8266 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 8267 8268 #define S_FW_FCOE_FCF_CMD_LOGIN 4 8269 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 8270 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 8271 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 8272 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 8273 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 8274 8275 #define S_FW_FCOE_FCF_CMD_PORTID 0 8276 #define M_FW_FCOE_FCF_CMD_PORTID 0xf 8277 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 8278 #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 8279 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 8280 8281 /****************************************************************************** 8282 * E R R O R a n d D E B U G C O M M A N D s 8283 ******************************************************/ 8284 8285 enum fw_error_type { 8286 FW_ERROR_TYPE_EXCEPTION = 0x0, 8287 FW_ERROR_TYPE_HWMODULE = 0x1, 8288 FW_ERROR_TYPE_WR = 0x2, 8289 FW_ERROR_TYPE_ACL = 0x3, 8290 }; 8291 8292 enum fw_dcb_ieee_locations { 8293 FW_IEEE_LOC_LOCAL, 8294 FW_IEEE_LOC_PEER, 8295 FW_IEEE_LOC_OPERATIONAL, 8296 }; 8297 8298 struct fw_dcb_ieee_cmd { 8299 __be32 op_to_location; 8300 __be32 changed_to_len16; 8301 union fw_dcbx_stats { 8302 struct fw_dcbx_pfc_stats_ieee { 8303 __be32 pfc_mbc_pkd; 8304 __be32 pfc_willing_to_pfc_en; 8305 } dcbx_pfc_stats; 8306 struct fw_dcbx_ets_stats_ieee { 8307 __be32 cbs_to_ets_max_tc; 8308 __be32 pg_table; 8309 __u8 pg_percent[8]; 8310 __u8 tsa[8]; 8311 } dcbx_ets_stats; 8312 struct fw_dcbx_app_stats_ieee { 8313 __be32 num_apps_pkd; 8314 __be32 r6; 8315 __be32 app[4]; 8316 } dcbx_app_stats; 8317 struct fw_dcbx_control { 8318 __be32 multi_peer_invalidated; 8319 __be32 r5_lo; 8320 } dcbx_control; 8321 } u; 8322 }; 8323 8324 #define S_FW_DCB_IEEE_CMD_PORT 8 8325 #define M_FW_DCB_IEEE_CMD_PORT 0x7 8326 #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT) 8327 #define G_FW_DCB_IEEE_CMD_PORT(x) \ 8328 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT) 8329 8330 #define S_FW_DCB_IEEE_CMD_FEATURE 2 8331 #define M_FW_DCB_IEEE_CMD_FEATURE 0x7 8332 #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE) 8333 #define G_FW_DCB_IEEE_CMD_FEATURE(x) \ 8334 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE) 8335 8336 #define S_FW_DCB_IEEE_CMD_LOCATION 0 8337 #define M_FW_DCB_IEEE_CMD_LOCATION 0x3 8338 #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION) 8339 #define G_FW_DCB_IEEE_CMD_LOCATION(x) \ 8340 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION) 8341 8342 #define S_FW_DCB_IEEE_CMD_CHANGED 20 8343 #define M_FW_DCB_IEEE_CMD_CHANGED 0x1 8344 #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED) 8345 #define G_FW_DCB_IEEE_CMD_CHANGED(x) \ 8346 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED) 8347 #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U) 8348 8349 #define S_FW_DCB_IEEE_CMD_RECEIVED 19 8350 #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1 8351 #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED) 8352 #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \ 8353 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED) 8354 #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U) 8355 8356 #define S_FW_DCB_IEEE_CMD_APPLY 18 8357 #define M_FW_DCB_IEEE_CMD_APPLY 0x1 8358 #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY) 8359 #define G_FW_DCB_IEEE_CMD_APPLY(x) \ 8360 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY) 8361 #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U) 8362 8363 #define S_FW_DCB_IEEE_CMD_DISABLED 17 8364 #define M_FW_DCB_IEEE_CMD_DISABLED 0x1 8365 #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED) 8366 #define G_FW_DCB_IEEE_CMD_DISABLED(x) \ 8367 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED) 8368 #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U) 8369 8370 #define S_FW_DCB_IEEE_CMD_MORE 16 8371 #define M_FW_DCB_IEEE_CMD_MORE 0x1 8372 #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE) 8373 #define G_FW_DCB_IEEE_CMD_MORE(x) \ 8374 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE) 8375 #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U) 8376 8377 #define S_FW_DCB_IEEE_CMD_PFC_MBC 0 8378 #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1 8379 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC) 8380 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \ 8381 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC) 8382 #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U) 8383 8384 #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16 8385 #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1 8386 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 8387 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING) 8388 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 8389 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING) 8390 #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U) 8391 8392 #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8 8393 #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff 8394 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC) 8395 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \ 8396 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC) 8397 8398 #define S_FW_DCB_IEEE_CMD_PFC_EN 0 8399 #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff 8400 #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN) 8401 #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \ 8402 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN) 8403 8404 #define S_FW_DCB_IEEE_CMD_CBS 16 8405 #define M_FW_DCB_IEEE_CMD_CBS 0x1 8406 #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS) 8407 #define G_FW_DCB_IEEE_CMD_CBS(x) \ 8408 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS) 8409 #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U) 8410 8411 #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8 8412 #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1 8413 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 8414 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING) 8415 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 8416 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING) 8417 #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U) 8418 8419 #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0 8420 #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff 8421 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC) 8422 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \ 8423 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC) 8424 8425 #define S_FW_DCB_IEEE_CMD_NUM_APPS 0 8426 #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7 8427 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS) 8428 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \ 8429 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS) 8430 8431 #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31 8432 #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1 8433 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER) 8434 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \ 8435 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER) 8436 #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U) 8437 8438 #define S_FW_DCB_IEEE_CMD_INVALIDATED 30 8439 #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1 8440 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 8441 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED) 8442 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 8443 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED) 8444 #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U) 8445 8446 /* Hand-written */ 8447 #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16 8448 #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff 8449 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL) 8450 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \ 8451 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL) 8452 8453 #define S_FW_DCB_IEEE_CMD_APP_SELECT 3 8454 #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7 8455 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT) 8456 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \ 8457 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT) 8458 8459 #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0 8460 #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7 8461 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY) 8462 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \ 8463 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY) 8464 8465 8466 struct fw_error_cmd { 8467 __be32 op_to_type; 8468 __be32 len16_pkd; 8469 union fw_error { 8470 struct fw_error_exception { 8471 __be32 info[6]; 8472 } exception; 8473 struct fw_error_hwmodule { 8474 __be32 regaddr; 8475 __be32 regval; 8476 } hwmodule; 8477 struct fw_error_wr { 8478 __be16 cidx; 8479 __be16 pfn_vfn; 8480 __be32 eqid; 8481 __u8 wrhdr[16]; 8482 } wr; 8483 struct fw_error_acl { 8484 __be16 cidx; 8485 __be16 pfn_vfn; 8486 __be32 eqid; 8487 __be16 mv_pkd; 8488 __u8 val[6]; 8489 __be64 r4; 8490 } acl; 8491 } u; 8492 }; 8493 8494 #define S_FW_ERROR_CMD_FATAL 4 8495 #define M_FW_ERROR_CMD_FATAL 0x1 8496 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 8497 #define G_FW_ERROR_CMD_FATAL(x) \ 8498 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 8499 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 8500 8501 #define S_FW_ERROR_CMD_TYPE 0 8502 #define M_FW_ERROR_CMD_TYPE 0xf 8503 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 8504 #define G_FW_ERROR_CMD_TYPE(x) \ 8505 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 8506 8507 #define S_FW_ERROR_CMD_PFN 8 8508 #define M_FW_ERROR_CMD_PFN 0x7 8509 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 8510 #define G_FW_ERROR_CMD_PFN(x) \ 8511 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 8512 8513 #define S_FW_ERROR_CMD_VFN 0 8514 #define M_FW_ERROR_CMD_VFN 0xff 8515 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 8516 #define G_FW_ERROR_CMD_VFN(x) \ 8517 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 8518 8519 #define S_FW_ERROR_CMD_PFN 8 8520 #define M_FW_ERROR_CMD_PFN 0x7 8521 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 8522 #define G_FW_ERROR_CMD_PFN(x) \ 8523 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 8524 8525 #define S_FW_ERROR_CMD_VFN 0 8526 #define M_FW_ERROR_CMD_VFN 0xff 8527 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 8528 #define G_FW_ERROR_CMD_VFN(x) \ 8529 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 8530 8531 #define S_FW_ERROR_CMD_MV 15 8532 #define M_FW_ERROR_CMD_MV 0x1 8533 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 8534 #define G_FW_ERROR_CMD_MV(x) \ 8535 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 8536 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 8537 8538 struct fw_debug_cmd { 8539 __be32 op_type; 8540 __be32 len16_pkd; 8541 union fw_debug { 8542 struct fw_debug_assert { 8543 __be32 fcid; 8544 __be32 line; 8545 __be32 x; 8546 __be32 y; 8547 __u8 filename_0_7[8]; 8548 __u8 filename_8_15[8]; 8549 __be64 r3; 8550 } assert; 8551 struct fw_debug_prt { 8552 __be16 dprtstridx; 8553 __be16 r3[3]; 8554 __be32 dprtstrparam0; 8555 __be32 dprtstrparam1; 8556 __be32 dprtstrparam2; 8557 __be32 dprtstrparam3; 8558 } prt; 8559 } u; 8560 }; 8561 8562 #define S_FW_DEBUG_CMD_TYPE 0 8563 #define M_FW_DEBUG_CMD_TYPE 0xff 8564 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 8565 #define G_FW_DEBUG_CMD_TYPE(x) \ 8566 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 8567 8568 /****************************************************************************** 8569 * P C I E F W R E G I S T E R 8570 **************************************/ 8571 8572 enum pcie_fw_eval { 8573 PCIE_FW_EVAL_CRASH = 0, 8574 PCIE_FW_EVAL_PREP = 1, 8575 PCIE_FW_EVAL_CONF = 2, 8576 PCIE_FW_EVAL_INIT = 3, 8577 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 8578 PCIE_FW_EVAL_OVERHEAT = 5, 8579 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 8580 }; 8581 8582 /** 8583 * Register definitions for the PCIE_FW register which the firmware uses 8584 * to retain status across RESETs. This register should be considered 8585 * as a READ-ONLY register for Host Software and only to be used to 8586 * track firmware initialization/error state, etc. 8587 */ 8588 #define S_PCIE_FW_ERR 31 8589 #define M_PCIE_FW_ERR 0x1 8590 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 8591 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 8592 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 8593 8594 #define S_PCIE_FW_INIT 30 8595 #define M_PCIE_FW_INIT 0x1 8596 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 8597 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 8598 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 8599 8600 #define S_PCIE_FW_HALT 29 8601 #define M_PCIE_FW_HALT 0x1 8602 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 8603 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 8604 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 8605 8606 #define S_PCIE_FW_EVAL 24 8607 #define M_PCIE_FW_EVAL 0x7 8608 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 8609 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 8610 8611 #define S_PCIE_FW_STAGE 21 8612 #define M_PCIE_FW_STAGE 0x7 8613 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 8614 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 8615 8616 #define S_PCIE_FW_ASYNCNOT_VLD 20 8617 #define M_PCIE_FW_ASYNCNOT_VLD 0x1 8618 #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 8619 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 8620 #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 8621 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 8622 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 8623 8624 #define S_PCIE_FW_ASYNCNOTINT 19 8625 #define M_PCIE_FW_ASYNCNOTINT 0x1 8626 #define V_PCIE_FW_ASYNCNOTINT(x) \ 8627 ((x) << S_PCIE_FW_ASYNCNOTINT) 8628 #define G_PCIE_FW_ASYNCNOTINT(x) \ 8629 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 8630 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 8631 8632 #define S_PCIE_FW_ASYNCNOT 16 8633 #define M_PCIE_FW_ASYNCNOT 0x7 8634 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 8635 #define G_PCIE_FW_ASYNCNOT(x) \ 8636 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 8637 8638 #define S_PCIE_FW_MASTER_VLD 15 8639 #define M_PCIE_FW_MASTER_VLD 0x1 8640 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 8641 #define G_PCIE_FW_MASTER_VLD(x) \ 8642 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 8643 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 8644 8645 #define S_PCIE_FW_MASTER 12 8646 #define M_PCIE_FW_MASTER 0x7 8647 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 8648 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 8649 8650 #define S_PCIE_FW_RESET_VLD 11 8651 #define M_PCIE_FW_RESET_VLD 0x1 8652 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 8653 #define G_PCIE_FW_RESET_VLD(x) \ 8654 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 8655 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 8656 8657 #define S_PCIE_FW_RESET 8 8658 #define M_PCIE_FW_RESET 0x7 8659 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 8660 #define G_PCIE_FW_RESET(x) \ 8661 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 8662 8663 #define S_PCIE_FW_REGISTERED 0 8664 #define M_PCIE_FW_REGISTERED 0xff 8665 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 8666 #define G_PCIE_FW_REGISTERED(x) \ 8667 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 8668 8669 8670 /****************************************************************************** 8671 * P C I E F W P F 0 R E G I S T E R 8672 **********************************************/ 8673 8674 /* 8675 * this register is available as 32-bit of persistent storage (across 8676 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 8677 * will not write it) 8678 */ 8679 8680 8681 /****************************************************************************** 8682 * P C I E F W P F 7 R E G I S T E R 8683 **********************************************/ 8684 8685 /* 8686 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to 8687 * access the "devlog" which needing to contact firmware. The encoding is 8688 * mostly the same as that returned by the DEVLOG command except for the size 8689 * which is encoded as the number of entries in multiples-1 of 128 here rather 8690 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 8691 * and 15 means 2048. This of course in turn constrains the allowed values 8692 * for the devlog size ... 8693 */ 8694 #define PCIE_FW_PF_DEVLOG 7 8695 8696 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 8697 #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf 8698 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 8699 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) 8700 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 8701 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ 8702 M_PCIE_FW_PF_DEVLOG_NENTRIES128) 8703 8704 #define S_PCIE_FW_PF_DEVLOG_ADDR16 4 8705 #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff 8706 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) 8707 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ 8708 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) 8709 8710 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 8711 #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf 8712 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) 8713 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ 8714 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) 8715 8716 8717 /****************************************************************************** 8718 * B I N A R Y H E A D E R F O R M A T 8719 **********************************************/ 8720 8721 /* 8722 * firmware binary header format 8723 */ 8724 struct fw_hdr { 8725 __u8 ver; 8726 __u8 chip; /* terminator chip family */ 8727 __be16 len512; /* bin length in units of 512-bytes */ 8728 __be32 fw_ver; /* firmware version */ 8729 __be32 tp_microcode_ver; /* tcp processor microcode version */ 8730 __u8 intfver_nic; 8731 __u8 intfver_vnic; 8732 __u8 intfver_ofld; 8733 __u8 intfver_ri; 8734 __u8 intfver_iscsipdu; 8735 __u8 intfver_iscsi; 8736 __u8 intfver_fcoepdu; 8737 __u8 intfver_fcoe; 8738 __u32 reserved2; 8739 __u32 reserved3; 8740 __be32 magic; /* runtime or bootstrap fw */ 8741 __be32 flags; 8742 __be32 reserved6[23]; 8743 }; 8744 8745 enum fw_hdr_chip { 8746 FW_HDR_CHIP_T4, 8747 FW_HDR_CHIP_T5, 8748 FW_HDR_CHIP_T6 8749 }; 8750 8751 #define S_FW_HDR_FW_VER_MAJOR 24 8752 #define M_FW_HDR_FW_VER_MAJOR 0xff 8753 #define V_FW_HDR_FW_VER_MAJOR(x) \ 8754 ((x) << S_FW_HDR_FW_VER_MAJOR) 8755 #define G_FW_HDR_FW_VER_MAJOR(x) \ 8756 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 8757 8758 #define S_FW_HDR_FW_VER_MINOR 16 8759 #define M_FW_HDR_FW_VER_MINOR 0xff 8760 #define V_FW_HDR_FW_VER_MINOR(x) \ 8761 ((x) << S_FW_HDR_FW_VER_MINOR) 8762 #define G_FW_HDR_FW_VER_MINOR(x) \ 8763 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 8764 8765 #define S_FW_HDR_FW_VER_MICRO 8 8766 #define M_FW_HDR_FW_VER_MICRO 0xff 8767 #define V_FW_HDR_FW_VER_MICRO(x) \ 8768 ((x) << S_FW_HDR_FW_VER_MICRO) 8769 #define G_FW_HDR_FW_VER_MICRO(x) \ 8770 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 8771 8772 #define S_FW_HDR_FW_VER_BUILD 0 8773 #define M_FW_HDR_FW_VER_BUILD 0xff 8774 #define V_FW_HDR_FW_VER_BUILD(x) \ 8775 ((x) << S_FW_HDR_FW_VER_BUILD) 8776 #define G_FW_HDR_FW_VER_BUILD(x) \ 8777 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 8778 8779 enum { 8780 T4FW_VERSION_MAJOR = 0x01, 8781 T4FW_VERSION_MINOR = 0x05, 8782 T4FW_VERSION_MICRO = 0x25, 8783 T4FW_VERSION_BUILD = 0x00, 8784 8785 T5FW_VERSION_MAJOR = 0x01, 8786 T5FW_VERSION_MINOR = 0x05, 8787 T5FW_VERSION_MICRO = 0x25, 8788 T5FW_VERSION_BUILD = 0x00, 8789 }; 8790 8791 enum { 8792 /* T4 8793 */ 8794 T4FW_HDR_INTFVER_NIC = 0x00, 8795 T4FW_HDR_INTFVER_VNIC = 0x00, 8796 T4FW_HDR_INTFVER_OFLD = 0x00, 8797 T4FW_HDR_INTFVER_RI = 0x00, 8798 T4FW_HDR_INTFVER_ISCSIPDU= 0x00, 8799 T4FW_HDR_INTFVER_ISCSI = 0x00, 8800 T4FW_HDR_INTFVER_FCOEPDU = 0x00, 8801 T4FW_HDR_INTFVER_FCOE = 0x00, 8802 8803 /* T5 8804 */ 8805 T5FW_HDR_INTFVER_NIC = 0x00, 8806 T5FW_HDR_INTFVER_VNIC = 0x00, 8807 T5FW_HDR_INTFVER_OFLD = 0x00, 8808 T5FW_HDR_INTFVER_RI = 0x00, 8809 T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 8810 T5FW_HDR_INTFVER_ISCSI = 0x00, 8811 T5FW_HDR_INTFVER_FCOEPDU= 0x00, 8812 T5FW_HDR_INTFVER_FCOE = 0x00, 8813 8814 /* T6 8815 */ 8816 T6FW_HDR_INTFVER_NIC = 0x00, 8817 T6FW_HDR_INTFVER_VNIC = 0x00, 8818 T6FW_HDR_INTFVER_OFLD = 0x00, 8819 T6FW_HDR_INTFVER_RI = 0x00, 8820 T6FW_HDR_INTFVER_ISCSIPDU= 0x00, 8821 T6FW_HDR_INTFVER_ISCSI = 0x00, 8822 T6FW_HDR_INTFVER_FCOEPDU= 0x00, 8823 T6FW_HDR_INTFVER_FCOE = 0x00, 8824 }; 8825 8826 enum { 8827 FW_HDR_MAGIC_RUNTIME = 0x00000000, 8828 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 8829 }; 8830 8831 enum fw_hdr_flags { 8832 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 8833 }; 8834 8835 /* 8836 * External PHY firmware binary header format 8837 */ 8838 struct fw_ephy_hdr { 8839 __u8 ver; 8840 __u8 reserved; 8841 __be16 len512; /* bin length in units of 512-bytes */ 8842 __be32 magic; 8843 8844 __be16 vendor_id; 8845 __be16 device_id; 8846 __be32 version; 8847 8848 __be32 reserved1[4]; 8849 }; 8850 8851 enum { 8852 FW_EPHY_HDR_MAGIC = 0x65706879, 8853 }; 8854 8855 #endif /* _T4FW_INTERFACE_H_ */ 8856